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Add support for RISC-V architecture.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
e23eba97
NC		 12016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
2 Andrew Waterman <andrew@sifive.com>
3
4 Add support for RISC-V architecture.
5 * configure.ac: Add entry for bfd_riscv_arch.
6 * configure: Regenerate.
7 * disassemble.c (disassembler): Add support for riscv.
8 (disassembler_usage): Likewise.
9 * riscv-dis.c: New file.
10 * riscv-opc.c: New file.
11
b5cefcca
L		 122016-10-21 H.J. Lu <hongjiu.lu@intel.com>
13
14 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
15 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
16 (rm_table): Update the RM_0FAE_REG_7 entry.
17 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
18 (cpu_flags): Remove CpuPCOMMIT.
19 * i386-opc.h (CpuPCOMMIT): Removed.
20 (i386_cpu_flags): Remove cpupcommit.
21 * i386-opc.tbl: Remove pcommit.
22 * i386-init.h: Regenerated.
23 * i386-tbl.h: Likewise.
24
9889cbb1
L		 252016-10-20 H.J. Lu <hongjiu.lu@intel.com>
26
27 PR binutis/20705
28 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
29 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
30 32-bit mode. Don't check vex.register_specifier in 32-bit
31 mode.
32 (OP_VEX): Check for invalid mask registers.
33
28596323
L		 342016-10-18 H.J. Lu <hongjiu.lu@intel.com>
35
36 PR binutis/20699
37 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
38 sizeflag.
39
da8d7d66
L		 402016-10-18 H.J. Lu <hongjiu.lu@intel.com>
41
42 PR binutis/20704
43 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
44
eaf02703
MR		 452016-10-18 Maciej W. Rozycki <macro@imgtec.com>
46
47 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
48 local variable to `index_regno'.
49
decf5bd1
CM		 502016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
51
52 * arc-tbl.h: Removed any "inv.+" instructions from the table.
53
e5b06ef0
CZ		 542016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
55
56 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
57 usage on ISA basis.
58
93562a34
JW		 592016-10-11 Jiong Wang <jiong.wang@arm.com>
60
61 PR target/20666
62 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
63
362c0c4d
JW		 642016-10-07 Jiong Wang <jiong.wang@arm.com>
65
66 PR target/20667
67 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
68 available.
69
1047201f
AM		 702016-10-07 Alan Modra <amodra@gmail.com>
71
72 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
73
1a0670f3
AM		 742016-10-06 Alan Modra <amodra@gmail.com>
75
76 * aarch64-opc.c: Spell fall through comments consistently.
77 * i386-dis.c: Likewise.
78 * aarch64-dis.c: Add missing fall through comments.
79 * aarch64-opc.c: Likewise.
80 * arc-dis.c: Likewise.
81 * arm-dis.c: Likewise.
82 * i386-dis.c: Likewise.
83 * m68k-dis.c: Likewise.
84 * mep-asm.c: Likewise.
85 * ns32k-dis.c: Likewise.
86 * sh-dis.c: Likewise.
87 * tic4x-dis.c: Likewise.
88 * tic6x-dis.c: Likewise.
89 * vax-dis.c: Likewise.
90
2b804145
AM		 912016-10-06 Alan Modra <amodra@gmail.com>
92
93 * arc-ext.c (create_map): Add missing break.
94 * msp430-decode.opc (encode_as): Likewise.
95 * msp430-decode.c: Regenerate.
96
616ec358
AM		 972016-10-06 Alan Modra <amodra@gmail.com>
98
99 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
100 * crx-dis.c (print_insn_crx): Likewise.
101
72da393d
L		 1022016-09-30 H.J. Lu <hongjiu.lu@intel.com>
103
104 PR binutils/20657
105 * i386-dis.c (putop): Don't assign alt twice.
106
744ce302
JW		 1072016-09-29 Jiong Wang <jiong.wang@arm.com>
108
109 PR target/20553
110 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
111
a5721ba2
AM		 1122016-09-29 Alan Modra <amodra@gmail.com>
113
114 * ppc-opc.c (L): Make compulsory.
115 (LOPT): New, optional form of L.
116 (HTM_R): Define as LOPT.
117 (L0, L1): Delete.
118 (L32OPT): New, optional for 32-bit L.
119 (L2OPT): New, 2-bit L for dcbf.
120 (SVC_LEC): Update.
121 (L2): Define.
122 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
123 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
124 <dcbf>: Use L2OPT.
125 <tlbiel, tlbie>: Use LOPT.
126 <wclr, wclrall>: Use L2.
127
c5da1932
VZ		 1282016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
129
130 * Makefile.in: Regenerate.
131 * configure: Likewise.
132
2b848ebd
CZ		 1332016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
134
135 * arc-ext-tbl.h (EXTINSN2OPF): Define.
136 (EXTINSN2OP): Use EXTINSN2OPF.
137 (bspeekm, bspop, modapp): New extension instructions.
138 * arc-opc.c (F_DNZ_ND): Define.
139 (F_DNZ_D): Likewise.
140 (F_SIZEB1): Changed.
141 (C_DNZ_D): Define.
142 (C_HARD): Changed.
143 * arc-tbl.h (dbnz): New instruction.
144 (prealloc): Allow it for ARC EM.
145 (xbfu): Likewise.
146
ad43e107
RS		 1472016-09-21 Richard Sandiford <richard.sandiford@arm.com>
148
149 * aarch64-opc.c (print_immediate_offset_address): Print spaces
150 after commas in addresses.
151 (aarch64_print_operand): Likewise.
152
ab3b8fcf
RS		 1532016-09-21 Richard Sandiford <richard.sandiford@arm.com>
154
155 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
156 rather than "should be" or "expected to be" in error messages.
157
bb7eff52
RS		 1582016-09-21 Richard Sandiford <richard.sandiford@arm.com>
159
160 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
161 (print_mnemonic_name): ...here.
162 (print_comment): New function.
163 (print_aarch64_insn): Call it.
164 * aarch64-opc.c (aarch64_conds): Add SVE names.
165 (aarch64_print_operand): Print alternative condition names in
166 a comment.
167
c0890d26
RS		 1682016-09-21 Richard Sandiford <richard.sandiford@arm.com>
169
170 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
171 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
172 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
173 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
174 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
175 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
176 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
177 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
178 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
179 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
180 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
181 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
182 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
183 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
184 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
185 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
186 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
187 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
188 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
189 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
190 (OP_SVE_XWU, OP_SVE_XXU): New macros.
191 (aarch64_feature_sve): New variable.
192 (SVE): New macro.
193 (_SVE_INSN): Likewise.
194 (aarch64_opcode_table): Add SVE instructions.
195 * aarch64-opc.h (extract_fields): Declare.
196 * aarch64-opc-2.c: Regenerate.
197 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
198 * aarch64-asm-2.c: Regenerate.
199 * aarch64-dis.c (extract_fields): Make global.
200 (do_misc_decoding): Handle the new SVE aarch64_ops.
201 * aarch64-dis-2.c: Regenerate.
202
116b6019
RS		 2032016-09-21 Richard Sandiford <richard.sandiford@arm.com>
204
205 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
206 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
207 aarch64_field_kinds.
208 * aarch64-opc.c (fields): Add corresponding entries.
209 * aarch64-asm.c (aarch64_get_variant): New function.
210 (aarch64_encode_variant_using_iclass): Likewise.
211 (aarch64_opcode_encode): Call it.
212 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
213 (aarch64_opcode_decode): Call it.
214
047cd301
RS		 2152016-09-21 Richard Sandiford <richard.sandiford@arm.com>
216
217 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
218 and FP register operands.
219 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
220 (FLD_SVE_Vn): New aarch64_field_kinds.
221 * aarch64-opc.c (fields): Add corresponding entries.
222 (aarch64_print_operand): Handle the new SVE core and FP register
223 operands.
224 * aarch64-opc-2.c: Regenerate.
225 * aarch64-asm-2.c: Likewise.
226 * aarch64-dis-2.c: Likewise.
227
165d4950
RS		 2282016-09-21 Richard Sandiford <richard.sandiford@arm.com>
229
230 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
231 immediate operands.
232 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
233 * aarch64-opc.c (fields): Add corresponding entry.
234 (operand_general_constraint_met_p): Handle the new SVE FP immediate
235 operands.
236 (aarch64_print_operand): Likewise.
237 * aarch64-opc-2.c: Regenerate.
238 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
239 (ins_sve_float_zero_one): New inserters.
240 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
241 (aarch64_ins_sve_float_half_two): Likewise.
242 (aarch64_ins_sve_float_zero_one): Likewise.
243 * aarch64-asm-2.c: Regenerate.
244 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
245 (ext_sve_float_zero_one): New extractors.
246 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
247 (aarch64_ext_sve_float_half_two): Likewise.
248 (aarch64_ext_sve_float_zero_one): Likewise.
249 * aarch64-dis-2.c: Regenerate.
250
e950b345
RS		 2512016-09-21 Richard Sandiford <richard.sandiford@arm.com>
252
253 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
254 integer immediate operands.
255 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
256 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
257 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
258 * aarch64-opc.c (fields): Add corresponding entries.
259 (operand_general_constraint_met_p): Handle the new SVE integer
260 immediate operands.
261 (aarch64_print_operand): Likewise.
262 (aarch64_sve_dupm_mov_immediate_p): New function.
263 * aarch64-opc-2.c: Regenerate.
264 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
265 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
266 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
267 (aarch64_ins_limm): ...here.
268 (aarch64_ins_inv_limm): New function.
269 (aarch64_ins_sve_aimm): Likewise.
270 (aarch64_ins_sve_asimm): Likewise.
271 (aarch64_ins_sve_limm_mov): Likewise.
272 (aarch64_ins_sve_shlimm): Likewise.
273 (aarch64_ins_sve_shrimm): Likewise.
274 * aarch64-asm-2.c: Regenerate.
275 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
276 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
277 * aarch64-dis.c (decode_limm): New function, split out from...
278 (aarch64_ext_limm): ...here.
279 (aarch64_ext_inv_limm): New function.
280 (decode_sve_aimm): Likewise.
281 (aarch64_ext_sve_aimm): Likewise.
282 (aarch64_ext_sve_asimm): Likewise.
283 (aarch64_ext_sve_limm_mov): Likewise.
284 (aarch64_top_bit): Likewise.
285 (aarch64_ext_sve_shlimm): Likewise.
286 (aarch64_ext_sve_shrimm): Likewise.
287 * aarch64-dis-2.c: Regenerate.
288
98907a70
RS		 2892016-09-21 Richard Sandiford <richard.sandiford@arm.com>
290
291 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
292 operands.
293 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
294 the AARCH64_MOD_MUL_VL entry.
295 (value_aligned_p): Cope with non-power-of-two alignments.
296 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
297 (print_immediate_offset_address): Likewise.
298 (aarch64_print_operand): Likewise.
299 * aarch64-opc-2.c: Regenerate.
300 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
301 (ins_sve_addr_ri_s9xvl): New inserters.
302 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
303 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
304 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
305 * aarch64-asm-2.c: Regenerate.
306 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
307 (ext_sve_addr_ri_s9xvl): New extractors.
308 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
309 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
310 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
311 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
312 * aarch64-dis-2.c: Regenerate.
313
4df068de
RS		 3142016-09-21 Richard Sandiford <richard.sandiford@arm.com>
315
316 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
317 address operands.
318 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
319 (FLD_SVE_xs_22): New aarch64_field_kinds.
320 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
321 (get_operand_specific_data): New function.
322 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
323 FLD_SVE_xs_14 and FLD_SVE_xs_22.
324 (operand_general_constraint_met_p): Handle the new SVE address
325 operands.
326 (sve_reg): New array.
327 (get_addr_sve_reg_name): New function.
328 (aarch64_print_operand): Handle the new SVE address operands.
329 * aarch64-opc-2.c: Regenerate.
330 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
331 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
332 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
333 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
334 (aarch64_ins_sve_addr_rr_lsl): Likewise.
335 (aarch64_ins_sve_addr_rz_xtw): Likewise.
336 (aarch64_ins_sve_addr_zi_u5): Likewise.
337 (aarch64_ins_sve_addr_zz): Likewise.
338 (aarch64_ins_sve_addr_zz_lsl): Likewise.
339 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
340 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
341 * aarch64-asm-2.c: Regenerate.
342 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
343 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
344 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
345 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
346 (aarch64_ext_sve_addr_ri_u6): Likewise.
347 (aarch64_ext_sve_addr_rr_lsl): Likewise.
348 (aarch64_ext_sve_addr_rz_xtw): Likewise.
349 (aarch64_ext_sve_addr_zi_u5): Likewise.
350 (aarch64_ext_sve_addr_zz): Likewise.
351 (aarch64_ext_sve_addr_zz_lsl): Likewise.
352 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
353 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
354 * aarch64-dis-2.c: Regenerate.
355
2442d846
RS		 3562016-09-21 Richard Sandiford <richard.sandiford@arm.com>
357
358 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
359 AARCH64_OPND_SVE_PATTERN_SCALED.
360 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
361 * aarch64-opc.c (fields): Add a corresponding entry.
362 (set_multiplier_out_of_range_error): New function.
363 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
364 (operand_general_constraint_met_p): Handle
365 AARCH64_OPND_SVE_PATTERN_SCALED.
366 (print_register_offset_address): Use PRIi64 to print the
367 shift amount.
368 (aarch64_print_operand): Likewise. Handle
369 AARCH64_OPND_SVE_PATTERN_SCALED.
370 * aarch64-opc-2.c: Regenerate.
371 * aarch64-asm.h (ins_sve_scale): New inserter.
372 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
373 * aarch64-asm-2.c: Regenerate.
374 * aarch64-dis.h (ext_sve_scale): New inserter.
375 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
376 * aarch64-dis-2.c: Regenerate.
377
245d2e3f
RS		 3782016-09-21 Richard Sandiford <richard.sandiford@arm.com>
379
380 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
381 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
382 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
383 (FLD_SVE_prfop): Likewise.
384 * aarch64-opc.c: Include libiberty.h.
385 (aarch64_sve_pattern_array): New variable.
386 (aarch64_sve_prfop_array): Likewise.
387 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
388 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
389 AARCH64_OPND_SVE_PRFOP.
390 * aarch64-asm-2.c: Regenerate.
391 * aarch64-dis-2.c: Likewise.
392 * aarch64-opc-2.c: Likewise.
393
d50c751e
RS		 3942016-09-21 Richard Sandiford <richard.sandiford@arm.com>
395
396 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
397 AARCH64_OPND_QLF_P_[ZM].
398 (aarch64_print_operand): Print /z and /m where appropriate.
399
f11ad6bc
RS		 4002016-09-21 Richard Sandiford <richard.sandiford@arm.com>
401
402 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
403 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
404 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
405 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
406 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
407 * aarch64-opc.c (fields): Add corresponding entries here.
408 (operand_general_constraint_met_p): Check that SVE register lists
409 have the correct length. Check the ranges of SVE index registers.
410 Check for cases where p8-p15 are used in 3-bit predicate fields.
411 (aarch64_print_operand): Handle the new SVE operands.
412 * aarch64-opc-2.c: Regenerate.
413 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
414 * aarch64-asm.c (aarch64_ins_sve_index): New function.
415 (aarch64_ins_sve_reglist): Likewise.
416 * aarch64-asm-2.c: Regenerate.
417 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
418 * aarch64-dis.c (aarch64_ext_sve_index): New function.
419 (aarch64_ext_sve_reglist): Likewise.
420 * aarch64-dis-2.c: Regenerate.
421
0c608d6b
RS		 4222016-09-21 Richard Sandiford <richard.sandiford@arm.com>
423
424 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
425 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
426 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
427 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
428 tied operands.
429
01dbfe4c
RS		 4302016-09-21 Richard Sandiford <richard.sandiford@arm.com>
431
432 * aarch64-opc.c (get_offset_int_reg_name): New function.
433 (print_immediate_offset_address): Likewise.
434 (print_register_offset_address): Take the base and offset
435 registers as parameters.
436 (aarch64_print_operand): Update caller accordingly. Use
437 print_immediate_offset_address.
438
72e9f319
RS		 4392016-09-21 Richard Sandiford <richard.sandiford@arm.com>
440
441 * aarch64-opc.c (BANK): New macro.
442 (R32, R64): Take a register number as argument
443 (int_reg): Use BANK.
444
8a7f0c1b
RS		 4452016-09-21 Richard Sandiford <richard.sandiford@arm.com>
446
447 * aarch64-opc.c (print_register_list): Add a prefix parameter.
448 (aarch64_print_operand): Update accordingly.
449
aa2aa4c6
RS		 4502016-09-21 Richard Sandiford <richard.sandiford@arm.com>
451
452 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
453 for FPIMM.
454 * aarch64-asm.h (ins_fpimm): New inserter.
455 * aarch64-asm.c (aarch64_ins_fpimm): New function.
456 * aarch64-asm-2.c: Regenerate.
457 * aarch64-dis.h (ext_fpimm): New extractor.
458 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
459 (aarch64_ext_fpimm): New function.
460 * aarch64-dis-2.c: Regenerate.
461
b5464a68
RS		 4622016-09-21 Richard Sandiford <richard.sandiford@arm.com>
463
464 * aarch64-asm.c: Include libiberty.h.
465 (insert_fields): New function.
466 (aarch64_ins_imm): Use it.
467 * aarch64-dis.c (extract_fields): New function.
468 (aarch64_ext_imm): Use it.
469
42408347
RS		 4702016-09-21 Richard Sandiford <richard.sandiford@arm.com>
471
472 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
473 with an esize parameter.
474 (operand_general_constraint_met_p): Update accordingly.
475 Fix misindented code.
476 * aarch64-asm.c (aarch64_ins_limm): Update call to
477 aarch64_logical_immediate_p.
478
4989adac
RS		 4792016-09-21 Richard Sandiford <richard.sandiford@arm.com>
480
481 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
482
bd11d5d8
RS		 4832016-09-21 Richard Sandiford <richard.sandiford@arm.com>
484
485 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
486
f807f43d
CZ		 4872016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
488
489 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
490
fd486b63
PB		 4912016-09-14 Peter Bergner <bergner@vnet.ibm.com>
492
493 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
494 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
495 xor3>: Delete mnemonics.
496 <cp_abort>: Rename mnemonic from ...
497 <cpabort>: ...to this.
498 <setb>: Change to a X form instruction.
499 <sync>: Change to 1 operand form.
500 <copy>: Delete mnemonic.
501 <copy_first>: Rename mnemonic from ...
502 <copy>: ...to this.
503 <paste, paste.>: Delete mnemonics.
504 <paste_last>: Rename mnemonic from ...
505 <paste.>: ...to this.
506
dce08442
AK		 5072016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
508
509 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
510
952c3f51
AK		 5112016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
512
513 * s390-mkopc.c (main): Support alternate arch strings.
514
8b71537b
PS		 5152016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
516
517 * s390-opc.txt: Fix kmctr instruction type.
518
5b64d091
L		 5192016-09-07 H.J. Lu <hongjiu.lu@intel.com>
520
521 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
522 * i386-init.h: Regenerated.
523
7763838e
CM		 5242016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
525
526 * opcodes/arc-dis.c (print_insn_arc): Changed.
527
1b8b6532
JM		 5282016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
529
530 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
531 camellia_fl.
532
1a336194
TP		 5332016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
534
535 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
536 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
537 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
538
6b40c462
L		 5392016-08-24 H.J. Lu <hongjiu.lu@intel.com>
540
541 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
542 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
543 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
544 PREFIX_MOD_3_0FAE_REG_4.
545 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
546 PREFIX_MOD_3_0FAE_REG_4.
547 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
548 (cpu_flags): Add CpuPTWRITE.
549 * i386-opc.h (CpuPTWRITE): New.
550 (i386_cpu_flags): Add cpuptwrite.
551 * i386-opc.tbl: Add ptwrite instruction.
552 * i386-init.h: Regenerated.
553 * i386-tbl.h: Likewise.
554
ab548d2d
AK		 5552016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
556
557 * arc-dis.h: Wrap around in extern "C".
558
344bde0a
RS		 5592016-08-23 Richard Sandiford <richard.sandiford@arm.com>
560
561 * aarch64-tbl.h (V8_2_INSN): New macro.
562 (aarch64_opcode_table): Use it.
563
5ce912d8
RS		 5642016-08-23 Richard Sandiford <richard.sandiford@arm.com>
565
566 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
567 CORE_INSN, __FP_INSN and SIMD_INSN.
568
9d30b0bd
RS		 5692016-08-23 Richard Sandiford <richard.sandiford@arm.com>
570
571 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
572 (aarch64_opcode_table): Update uses accordingly.
573
dfdaec14
AJ		 5742016-07-25 Andrew Jenner <andrew@codesourcery.com>
575 Kwok Cheung Yeung <kcy@codesourcery.com>
576
577 opcodes/
578 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
579 'e_cmplwi' to 'e_cmpli' instead.
580 (OPVUPRT, OPVUPRT_MASK): Define.
581 (powerpc_opcodes): Add E200Z4 insns.
582 (vle_opcodes): Add context save/restore insns.
583
7bd374a4
MR		 5842016-07-27 Maciej W. Rozycki <macro@imgtec.com>
585
586 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
587 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
588 "j".
589
db18dbab
GM		 5902016-07-27 Graham Markall <graham.markall@embecosm.com>
591
592 * arc-nps400-tbl.h: Change block comments to GNU format.
593 * arc-dis.c: Add new globals addrtypenames,
594 addrtypenames_max, and addtypeunknown.
595 (get_addrtype): New function.
596 (print_insn_arc): Print colons and address types when
597 required.
598 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
599 define insert and extract functions for all address types.
600 (arc_operands): Add operands for colon and all address
601 types.
602 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
603 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
604 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
605 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
606 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
607 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
608
fecd57f9
L		 6092016-07-21 H.J. Lu <hongjiu.lu@intel.com>
610
611 * configure: Regenerated.
612
37fd5ef3
CZ		 6132016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
614
615 * arc-dis.c (skipclass): New structure.
616 (decodelist): New variable.
617 (is_compatible_p): New function.
618 (new_element): Likewise.
619 (skip_class_p): Likewise.
620 (find_format_from_table): Use skip_class_p function.
621 (find_format): Decode first the extension instructions.
622 (print_insn_arc): Select either ARCEM or ARCHS based on elf
623 e_flags.
624 (parse_option): New function.
625 (parse_disassembler_options): Likewise.
626 (print_arc_disassembler_options): Likewise.
627 (print_insn_arc): Use parse_disassembler_options function. Proper
628 select ARCv2 cpu variant.
629 * disassemble.c (disassembler_usage): Add ARC disassembler
630 options.
631
92281a5b
MR		 6322016-07-13 Maciej W. Rozycki <macro@imgtec.com>
633
634 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
635 annotation from the "nal" entry and reorder it beyond "bltzal".
636
6e7ced37
JM		 6372016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
638
639 * sparc-opc.c (ldtxa): New macro.
640 (sparc_opcodes): Use the macro defined above to add entries for
641 the LDTXA instructions.
642 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
643 instruction.
644
2f831b9a 6452016-07-07 James Bowman <james.bowman@ftdichip.com>
646
647 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
648 and "jmpc".
649
c07315e0
JB		 6502016-07-01 Jan Beulich <jbeulich@suse.com>
651
652 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
653 (movzb): Adjust to cover all permitted suffixes.
654 (movzw): New.
655 * i386-tbl.h: Re-generate.
656
9243100a
JB		 6572016-07-01 Jan Beulich <jbeulich@suse.com>
658
659 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
660 (lgdt): Remove Tbyte from non-64-bit variant.
661 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
662 xsaves64, xsavec64): Remove Disp16.
663 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
664 Remove Disp32S from non-64-bit variants. Remove Disp16 from
665 64-bit variants.
666 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
667 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
668 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
669 64-bit variants.
670 * i386-tbl.h: Re-generate.
671
8325cc63
JB		 6722016-07-01 Jan Beulich <jbeulich@suse.com>
673
674 * i386-opc.tbl (xlat): Remove RepPrefixOk.
675 * i386-tbl.h: Re-generate.
676
838441e4
YQ		 6772016-06-30 Yao Qi <yao.qi@linaro.org>
678
679 * arm-dis.c (print_insn): Fix typo in comment.
680
dab26bf4
RS		 6812016-06-28 Richard Sandiford <richard.sandiford@arm.com>
682
683 * aarch64-opc.c (operand_general_constraint_met_p): Check the
684 range of ldst_elemlist operands.
685 (print_register_list): Use PRIi64 to print the index.
686 (aarch64_print_operand): Likewise.
687
5703197e
TS		 6882016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
689
690 * mcore-opc.h: Remove sentinal.
691 * mcore-dis.c (print_insn_mcore): Adjust.
692
ce440d63
GM		 6932016-06-23 Graham Markall <graham.markall@embecosm.com>
694
695 * arc-opc.c: Correct description of availability of NPS400
696 features.
697
6fd3a02d
PB		 6982016-06-22 Peter Bergner <bergner@vnet.ibm.com>
699
700 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
701 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
702 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
703 xor3>: New mnemonics.
704 <setb>: Change to a VX form instruction.
705 (insert_sh6): Add support for rldixor.
706 (extract_sh6): Likewise.
707
6b477896
TS		 7082016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
709
710 * arc-ext.h: Wrap in extern C.
711
bdd582db
GM		 7122016-06-21 Graham Markall <graham.markall@embecosm.com>
713
714 * arc-dis.c (arc_insn_length): Add comment on instruction length.
715 Use same method for determining instruction length on ARC700 and
716 NPS-400.
717 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
718 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
719 with the NPS400 subclass.
720 * arc-opc.c: Likewise.
721
96074adc
JM		 7222016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
723
724 * sparc-opc.c (rdasr): New macro.
725 (wrasr): Likewise.
726 (rdpr): Likewise.
727 (wrpr): Likewise.
728 (rdhpr): Likewise.
729 (wrhpr): Likewise.
730 (sparc_opcodes): Use the macros above to fix and expand the
731 definition of read/write instructions from/to
732 asr/privileged/hyperprivileged instructions.
733 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
734 %hva_mask_nz. Prefer softint_set and softint_clear over
735 set_softint and clear_softint.
736 (print_insn_sparc): Support %ver in Rd.
737
7a10c22f
JM		 7382016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
739
740 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
741 architecture according to the hardware capabilities they require.
742
4f26fb3a
JM		 7432016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
744
745 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
746 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
747 bfd_mach_sparc_v9{c,d,e,v,m}.
748 * sparc-opc.c (MASK_V9C): Define.
749 (MASK_V9D): Likewise.
750 (MASK_V9E): Likewise.
751 (MASK_V9V): Likewise.
752 (MASK_V9M): Likewise.
753 (v6): Add MASK_V9{C,D,E,V,M}.
754 (v6notlet): Likewise.
755 (v7): Likewise.
756 (v8): Likewise.
757 (v9): Likewise.
758 (v9andleon): Likewise.
759 (v9a): Likewise.
760 (v9b): Likewise.
761 (v9c): Define.
762 (v9d): Likewise.
763 (v9e): Likewise.
764 (v9v): Likewise.
765 (v9m): Likewise.
766 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
767
3ee6e4fb
NC		 7682016-06-15 Nick Clifton <nickc@redhat.com>
769
770 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
771 constants to match expected behaviour.
772 (nds32_parse_opcode): Likewise. Also for whitespace.
773
02f3be19
AB		 7742016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
775
776 * arc-opc.c (extract_rhv1): Extract value from insn.
777
6f9f37ed 7782016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 779
780 * arc-nps400-tbl.h: Add ldbit instruction.
781 * arc-opc.c: Add flag classes required for ldbit.
782
6f9f37ed 7832016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 784
785 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
786 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
787 support the above instructions.
788
6f9f37ed 7892016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 790
791 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
792 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
793 csma, cbba, zncv, and hofs.
794 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
795 support the above instructions.
796
7972016-06-06 Graham Markall <graham.markall@embecosm.com>
798
799 * arc-nps400-tbl.h: Add andab and orab instructions.
800
8012016-06-06 Graham Markall <graham.markall@embecosm.com>
802
803 * arc-nps400-tbl.h: Add addl-like instructions.
804
8052016-06-06 Graham Markall <graham.markall@embecosm.com>
806
807 * arc-nps400-tbl.h: Add mxb and imxb instructions.
808
8092016-06-06 Graham Markall <graham.markall@embecosm.com>
810
811 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
812 instructions.
813
b2cc3f6f
AK		 8142016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
815
816 * s390-dis.c (option_use_insn_len_bits_p): New file scope
817 variable.
818 (init_disasm): Handle new command line option "insnlength".
819 (print_s390_disassembler_options): Mention new option in help
820 output.
821 (print_insn_s390): Use the encoded insn length when dumping
822 unknown instructions.
823
1857fe72
DC		 8242016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
825
826 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
827 to the address and set as symbol address for LDS/ STS immediate operands.
828
14b57c7c
AM		 8292016-06-07 Alan Modra <amodra@gmail.com>
830
831 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
832 cpu for "vle" to e500.
833 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
834 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
835 (PPCNONE): Delete, substitute throughout.
836 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
837 except for major opcode 4 and 31.
838 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
839
4d1464f2
MW		 8402016-06-07 Matthew Wahab <matthew.wahab@arm.com>
841
842 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
843 ARM_EXT_RAS in relevant entries.
844
026122a6
PB		 8452016-06-03 Peter Bergner <bergner@vnet.ibm.com>
846
847 PR binutils/20196
848 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
849 opcodes for E6500.
850
07f5af7d
L		 8512016-06-03 H.J. Lu <hongjiu.lu@intel.com>
852
853 PR binutis/18386
854 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
855 (indir_v_mode): New.
856 Add comments for '&'.
857 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
858 (putop): Handle '&'.
859 (intel_operand_size): Handle indir_v_mode.
860 (OP_E_register): Likewise.
861 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
862 64-bit indirect call/jmp for AMD64.
863 * i386-tbl.h: Regenerated
864
4eb6f892
AB		 8652016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
866
867 * arc-dis.c (struct arc_operand_iterator): New structure.
868 (find_format_from_table): All the old content from find_format,
869 with some minor adjustments, and parameter renaming.
870 (find_format_long_instructions): New function.
871 (find_format): Rewritten.
872 (arc_insn_length): Add LSB parameter.
873 (extract_operand_value): New function.
874 (operand_iterator_next): New function.
875 (print_insn_arc): Use new functions to find opcode, and iterator
876 over operands.
877 * arc-opc.c (insert_nps_3bit_dst_short): New function.
878 (extract_nps_3bit_dst_short): New function.
879 (insert_nps_3bit_src2_short): New function.
880 (extract_nps_3bit_src2_short): New function.
881 (insert_nps_bitop1_size): New function.
882 (extract_nps_bitop1_size): New function.
883 (insert_nps_bitop2_size): New function.
884 (extract_nps_bitop2_size): New function.
885 (insert_nps_bitop_mod4_msb): New function.
886 (extract_nps_bitop_mod4_msb): New function.
887 (insert_nps_bitop_mod4_lsb): New function.
888 (extract_nps_bitop_mod4_lsb): New function.
889 (insert_nps_bitop_dst_pos3_pos4): New function.
890 (extract_nps_bitop_dst_pos3_pos4): New function.
891 (insert_nps_bitop_ins_ext): New function.
892 (extract_nps_bitop_ins_ext): New function.
893 (arc_operands): Add new operands.
894 (arc_long_opcodes): New global array.
895 (arc_num_long_opcodes): New global.
896 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
897
1fe0971e
TS		 8982016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
899
900 * nds32-asm.h: Add extern "C".
901 * sh-opc.h: Likewise.
902
315f180f
GM		 9032016-06-01 Graham Markall <graham.markall@embecosm.com>
904
905 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
906 0,b,limm to the rflt instruction.
907
a2b5fccc
TS		 9082016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
909
910 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
911 constant.
912
0cbd0046
L		 9132016-05-29 H.J. Lu <hongjiu.lu@intel.com>
914
915 PR gas/20145
916 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
917 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
918 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
919 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
920 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
921 * i386-init.h: Regenerated.
922
1848e567
L		 9232016-05-27 H.J. Lu <hongjiu.lu@intel.com>
924
925 PR gas/20145
926 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
927 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
928 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
929 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
930 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
931 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
932 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
933 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
934 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
935 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
936 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
937 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
938 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
939 CpuRegMask for AVX512.
940 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
941 and CpuRegMask.
942 (set_bitfield_from_cpu_flag_init): New function.
943 (set_bitfield): Remove const on f. Call
944 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
945 * i386-opc.h (CpuRegMMX): New.
946 (CpuRegXMM): Likewise.
947 (CpuRegYMM): Likewise.
948 (CpuRegZMM): Likewise.
949 (CpuRegMask): Likewise.
950 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
951 and cpuregmask.
952 * i386-init.h: Regenerated.
953 * i386-tbl.h: Likewise.
954
e92bae62
L		 9552016-05-27 H.J. Lu <hongjiu.lu@intel.com>
956
957 PR gas/20154
958 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
959 (opcode_modifiers): Add AMD64 and Intel64.
960 (main): Properly verify CpuMax.
961 * i386-opc.h (CpuAMD64): Removed.
962 (CpuIntel64): Likewise.
963 (CpuMax): Set to CpuNo64.
964 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
965 (AMD64): New.
966 (Intel64): Likewise.
967 (i386_opcode_modifier): Add amd64 and intel64.
968 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
969 on call and jmp.
970 * i386-init.h: Regenerated.
971 * i386-tbl.h: Likewise.
972
e89c5eaa
L		 9732016-05-27 H.J. Lu <hongjiu.lu@intel.com>
974
975 PR gas/20154
976 * i386-gen.c (main): Fail if CpuMax is incorrect.
977 * i386-opc.h (CpuMax): Set to CpuIntel64.
978 * i386-tbl.h: Regenerated.
979
77d66e7b
NC		 9802016-05-27 Nick Clifton <nickc@redhat.com>
981
982 PR target/20150
983 * msp430-dis.c (msp430dis_read_two_bytes): New function.
984 (msp430dis_opcode_unsigned): New function.
985 (msp430dis_opcode_signed): New function.
986 (msp430_singleoperand): Use the new opcode reading functions.
987 Only disassenmble bytes if they were successfully read.
988 (msp430_doubleoperand): Likewise.
989 (msp430_branchinstr): Likewise.
990 (msp430x_callx_instr): Likewise.
991 (print_insn_msp430): Check that it is safe to read bytes before
992 attempting disassembly. Use the new opcode reading functions.
993
19dfcc89
PB		 9942016-05-26 Peter Bergner <bergner@vnet.ibm.com>
995
996 * ppc-opc.c (CY): New define. Document it.
997 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
998
f3ad7637
L		 9992016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1000
1001 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1002 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1003 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1004 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1005 CPU_ANY_AVX_FLAGS.
1006 * i386-init.h: Regenerated.
1007
f1360d58
L		 10082016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1009
1010 PR gas/20141
1011 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1012 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1013 * i386-init.h: Regenerated.
1014
293f5f65
L		 10152016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1016
1017 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1018 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1019 * i386-init.h: Regenerated.
1020
d9eca1df
CZ		 10212016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1022
1023 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1024 information.
1025 (print_insn_arc): Set insn_type information.
1026 * arc-opc.c (C_CC): Add F_CLASS_COND.
1027 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1028 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1029 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1030 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1031 (brne, brne_s, jeq_s, jne_s): Likewise.
1032
87789e08
CZ		 10332016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1034
1035 * arc-tbl.h (neg): New instruction variant.
1036
c810e0b8
CZ		 10372016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1038
1039 * arc-dis.c (find_format, find_format, get_auxreg)
1040 (print_insn_arc): Changed.
1041 * arc-ext.h (INSERT_XOP): Likewise.
1042
3d207518
TS		 10432016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1044
1045 * tic54x-dis.c (sprint_mmr): Adjust.
1046 * tic54x-opc.c: Likewise.
1047
514e58b7
AM		 10482016-05-19 Alan Modra <amodra@gmail.com>
1049
1050 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1051
e43de63c
AM		 10522016-05-19 Alan Modra <amodra@gmail.com>
1053
1054 * ppc-opc.c: Formatting.
1055 (NSISIGNOPT): Define.
1056 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1057
1401d2fe
MR		 10582016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1059
1060 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1061 replacing references to `micromips_ase' throughout.
1062 (_print_insn_mips): Don't use file-level microMIPS annotation to
1063 determine the disassembly mode with the symbol table.
1064
1178da44
PB		 10652016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1066
1067 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1068
8f4f9071
MF		 10692016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1070
1071 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1072 mips64r6.
1073 * mips-opc.c (D34): New macro.
1074 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1075
8bc52696
AF		 10762016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1077
1078 * i386-dis.c (prefix_table): Add RDPID instruction.
1079 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1080 (cpu_flags): Add RDPID bitfield.
1081 * i386-opc.h (enum): Add RDPID element.
1082 (i386_cpu_flags): Add RDPID field.
1083 * i386-opc.tbl: Add RDPID instruction.
1084 * i386-init.h: Regenerate.
1085 * i386-tbl.h: Regenerate.
1086
39d911fc
TP		 10872016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1088
1089 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1090 branch type of a symbol.
1091 (print_insn): Likewise.
1092
16a1fa25
TP		 10932016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1094
1095 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1096 Mainline Security Extensions instructions.
1097 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1098 Extensions instructions.
1099 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1100 instructions.
1101 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1102 special registers.
1103
d751b79e
JM		 11042016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1105
1106 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1107
945e0f82
CZ		 11082016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1109
1110 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1111 (arcExtMap_genOpcode): Likewise.
1112 * arc-opc.c (arg_32bit_rc): Define new variable.
1113 (arg_32bit_u6): Likewise.
1114 (arg_32bit_limm): Likewise.
1115
20f55f38
SN		 11162016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1117
1118 * aarch64-gen.c (VERIFIER): Define.
1119 * aarch64-opc.c (VERIFIER): Define.
1120 (verify_ldpsw): Use static linkage.
1121 * aarch64-opc.h (verify_ldpsw): Remove.
1122 * aarch64-tbl.h: Use VERIFIER for verifiers.
1123
4bd13cde
NC		 11242016-04-28 Nick Clifton <nickc@redhat.com>
1125
1126 PR target/19722
1127 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1128 * aarch64-opc.c (verify_ldpsw): New function.
1129 * aarch64-opc.h (verify_ldpsw): New prototype.
1130 * aarch64-tbl.h: Add initialiser for verifier field.
1131 (LDPSW): Set verifier to verify_ldpsw.
1132
c0f92bf9
L		 11332016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1134
1135 PR binutils/19983
1136 PR binutils/19984
1137 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1138 smaller than address size.
1139
e6c7cdec
TS		 11402016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1141
1142 * alpha-dis.c: Regenerate.
1143 * crx-dis.c: Likewise.
1144 * disassemble.c: Likewise.
1145 * epiphany-opc.c: Likewise.
1146 * fr30-opc.c: Likewise.
1147 * frv-opc.c: Likewise.
1148 * ip2k-opc.c: Likewise.
1149 * iq2000-opc.c: Likewise.
1150 * lm32-opc.c: Likewise.
1151 * lm32-opinst.c: Likewise.
1152 * m32c-opc.c: Likewise.
1153 * m32r-opc.c: Likewise.
1154 * m32r-opinst.c: Likewise.
1155 * mep-opc.c: Likewise.
1156 * mt-opc.c: Likewise.
1157 * or1k-opc.c: Likewise.
1158 * or1k-opinst.c: Likewise.
1159 * tic80-opc.c: Likewise.
1160 * xc16x-opc.c: Likewise.
1161 * xstormy16-opc.c: Likewise.
1162
537aefaf
AB		 11632016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1164
1165 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1166 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1167 calcsd, and calcxd instructions.
1168 * arc-opc.c (insert_nps_bitop_size): Delete.
1169 (extract_nps_bitop_size): Delete.
1170 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1171 (extract_nps_qcmp_m3): Define.
1172 (extract_nps_qcmp_m2): Define.
1173 (extract_nps_qcmp_m1): Define.
1174 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1175 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1176 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1177 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1178 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1179 NPS_QCMP_M3.
1180
c8f785f2
AB		 11812016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1182
1183 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1184
6fd8e7c2
L		 11852016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1186
1187 * Makefile.in: Regenerated with automake 1.11.6.
1188 * aclocal.m4: Likewise.
1189
4b0c052e
AB		 11902016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1191
1192 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1193 instructions.
1194 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1195 (extract_nps_cmem_uimm16): New function.
1196 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1197
cb040366
AB		 11982016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1199
1200 * arc-dis.c (arc_insn_length): New function.
1201 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1202 (find_format): Change insnLen parameter to unsigned.
1203
accc0180
NC		 12042016-04-13 Nick Clifton <nickc@redhat.com>
1205
1206 PR target/19937
1207 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1208 the LD.B and LD.BU instructions.
1209
f36e33da
CZ		 12102016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1211
1212 * arc-dis.c (find_format): Check for extension flags.
1213 (print_flags): New function.
1214 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1215 .extAuxRegister.
1216 * arc-ext.c (arcExtMap_coreRegName): Use
1217 LAST_EXTENSION_CORE_REGISTER.
1218 (arcExtMap_coreReadWrite): Likewise.
1219 (dump_ARC_extmap): Update printing.
1220 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1221 (arc_aux_regs): Add cpu field.
1222 * arc-regs.h: Add cpu field, lower case name aux registers.
1223
1c2e355e
CZ		 12242016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1225
1226 * arc-tbl.h: Add rtsc, sleep with no arguments.
1227
b99747ae
CZ		 12282016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1229
1230 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1231 Initialize.
1232 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1233 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1234 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1235 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1236 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1237 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1238 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1239 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1240 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1241 (arc_opcode arc_opcodes): Null terminate the array.
1242 (arc_num_opcodes): Remove.
1243 * arc-ext.h (INSERT_XOP): Define.
1244 (extInstruction_t): Likewise.
1245 (arcExtMap_instName): Delete.
1246 (arcExtMap_insn): New function.
1247 (arcExtMap_genOpcode): Likewise.
1248 * arc-ext.c (ExtInstruction): Remove.
1249 (create_map): Zero initialize instruction fields.
1250 (arcExtMap_instName): Remove.
1251 (arcExtMap_insn): New function.
1252 (dump_ARC_extmap): More info while debuging.
1253 (arcExtMap_genOpcode): New function.
1254 * arc-dis.c (find_format): New function.
1255 (print_insn_arc): Use find_format.
1256 (arc_get_disassembler): Enable dump_ARC_extmap only when
1257 debugging.
1258
92708cec
MR		 12592016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1260
1261 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1262 instruction bits out.
1263
a42a4f84
AB		 12642016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1265
1266 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1267 * arc-opc.c (arc_flag_operands): Add new flags.
1268 (arc_flag_classes): Add new classes.
1269
1328504b
AB		 12702016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1271
1272 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1273
820f03ff
AB		 12742016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1275
1276 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1277 encode1, rflt, crc16, and crc32 instructions.
1278 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1279 (arc_flag_classes): Add C_NPS_R.
1280 (insert_nps_bitop_size_2b): New function.
1281 (extract_nps_bitop_size_2b): Likewise.
1282 (insert_nps_bitop_uimm8): Likewise.
1283 (extract_nps_bitop_uimm8): Likewise.
1284 (arc_operands): Add new operand entries.
1285
8ddf6b2a
CZ		 12862016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1287
b99747ae
CZ		 1288 * arc-regs.h: Add a new subclass field. Add double assist
1289 accumulator register values.
1290 * arc-tbl.h: Use DPA subclass to mark the double assist
1291 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1292 * arc-opc.c (RSP): Define instead of SP.
1293 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1294
589a7d88
JW		 12952016-04-05 Jiong Wang <jiong.wang@arm.com>
1296
1297 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1298
0a191de9 12992016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1300
1301 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1302 NPS_R_SRC1.
1303
0a106562
AB		 13042016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1305
1306 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1307 issues. No functional changes.
1308
bd05ac5f
CZ		 13092016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1310
b99747ae
CZ		 1311 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1312 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1313 (RTT): Remove duplicate.
1314 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1315 (PCT_CONFIG*): Remove.
1316 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1317
9885948f
CZ		 13182016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1319
b99747ae 1320 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1321
f2dd8838
CZ		 13222016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1323
b99747ae
CZ		 1324 * arc-tbl.h (invld07): Remove.
1325 * arc-ext-tbl.h: New file.
1326 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1327 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1328
0d2f91fe
JK		 13292016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1330
1331 Fix -Wstack-usage warnings.
1332 * aarch64-dis.c (print_operands): Substitute size.
1333 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1334
a6b71f42
JM		 13352016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1336
1337 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1338 to get a proper diagnostic when an invalid ASR register is used.
1339
9780e045
NC		 13402016-03-22 Nick Clifton <nickc@redhat.com>
1341
1342 * configure: Regenerate.
1343
e23e8ebe
AB		 13442016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1345
1346 * arc-nps400-tbl.h: New file.
1347 * arc-opc.c: Add top level comment.
1348 (insert_nps_3bit_dst): New function.
1349 (extract_nps_3bit_dst): New function.
1350 (insert_nps_3bit_src2): New function.
1351 (extract_nps_3bit_src2): New function.
1352 (insert_nps_bitop_size): New function.
1353 (extract_nps_bitop_size): New function.
1354 (arc_flag_operands): Add nps400 entries.
1355 (arc_flag_classes): Add nps400 entries.
1356 (arc_operands): Add nps400 entries.
1357 (arc_opcodes): Add nps400 include.
1358
1ae8ab47
AB		 13592016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1360
1361 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1362 the new class enum values.
1363
8699fc3e
AB		 13642016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1365
1366 * arc-dis.c (print_insn_arc): Handle nps400.
1367
24740d83
AB		 13682016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1369
1370 * arc-opc.c (BASE): Delete.
1371
8678914f
NC		 13722016-03-18 Nick Clifton <nickc@redhat.com>
1373
1374 PR target/19721
1375 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1376 of MOV insn that aliases an ORR insn.
1377
cc933301
JW		 13782016-03-16 Jiong Wang <jiong.wang@arm.com>
1379
1380 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1381
f86f5863
TS		 13822016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1383
1384 * mcore-opc.h: Add const qualifiers.
1385 * microblaze-opc.h (struct op_code_struct): Likewise.
1386 * sh-opc.h: Likewise.
1387 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1388 (tic4x_print_op): Likewise.
1389
62de1c63
AM		 13902016-03-02 Alan Modra <amodra@gmail.com>
1391
d11698cd 1392 * or1k-desc.h: Regenerate.
62de1c63 1393 * fr30-ibld.c: Regenerate.
c697cf0b 1394 * rl78-decode.c: Regenerate.
62de1c63 1395
020efce5
NC		 13962016-03-01 Nick Clifton <nickc@redhat.com>
1397
1398 PR target/19747
1399 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1400
b0c11777
RL		 14012016-02-24 Renlin Li <renlin.li@arm.com>
1402
1403 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1404 (print_insn_coprocessor): Support fp16 instructions.
1405
3e309328
RL		 14062016-02-24 Renlin Li <renlin.li@arm.com>
1407
1408 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1409 vminnm, vrint(mpna).
1410
8afc7bea
RL		 14112016-02-24 Renlin Li <renlin.li@arm.com>
1412
1413 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1414 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1415
4fd7268a
L		 14162016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1417
1418 * i386-dis.c (print_insn): Parenthesize expression to prevent
1419 truncated addresses.
1420 (OP_J): Likewise.
1421
4670103e
CZ		 14222016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1423 Janek van Oirschot <jvanoirs@synopsys.com>
1424
b99747ae
CZ		 1425 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1426 variable.
4670103e 1427
c1d9289f
NC		 14282016-02-04 Nick Clifton <nickc@redhat.com>
1429
1430 PR target/19561
1431 * msp430-dis.c (print_insn_msp430): Add a special case for
1432 decoding an RRC instruction with the ZC bit set in the extension
1433 word.
1434
a143b004
AB		 14352016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1436
1437 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1438 * epiphany-ibld.c: Regenerate.
1439 * fr30-ibld.c: Regenerate.
1440 * frv-ibld.c: Regenerate.
1441 * ip2k-ibld.c: Regenerate.
1442 * iq2000-ibld.c: Regenerate.
1443 * lm32-ibld.c: Regenerate.
1444 * m32c-ibld.c: Regenerate.
1445 * m32r-ibld.c: Regenerate.
1446 * mep-ibld.c: Regenerate.
1447 * mt-ibld.c: Regenerate.
1448 * or1k-ibld.c: Regenerate.
1449 * xc16x-ibld.c: Regenerate.
1450 * xstormy16-ibld.c: Regenerate.
1451
b89807c6
AB		 14522016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1453
1454 * epiphany-dis.c: Regenerated from latest cpu files.
1455
d8c823c8
MM		 14562016-02-01 Michael McConville <mmcco@mykolab.com>
1457
1458 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1459 test bit.
1460
5bc5ae88
RL		 14612016-01-25 Renlin Li <renlin.li@arm.com>
1462
1463 * arm-dis.c (mapping_symbol_for_insn): New function.
1464 (find_ifthen_state): Call mapping_symbol_for_insn().
1465
0bff6e2d
MW		 14662016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1467
1468 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1469 of MSR UAO immediate operand.
1470
100b4f2e
MR		 14712016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1472
1473 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1474 instruction support.
1475
5c14705f
AM		 14762016-01-17 Alan Modra <amodra@gmail.com>
1477
1478 * configure: Regenerate.
1479
4d82fe66
NC		 14802016-01-14 Nick Clifton <nickc@redhat.com>
1481
1482 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1483 instructions that can support stack pointer operations.
1484 * rl78-decode.c: Regenerate.
1485 * rl78-dis.c: Fix display of stack pointer in MOVW based
1486 instructions.
1487
651657fa
MW		 14882016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1489
1490 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1491 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1492 erxtatus_el1 and erxaddr_el1.
1493
105bde57
MW		 14942016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1495
1496 * arm-dis.c (arm_opcodes): Add "esb".
1497 (thumb_opcodes): Likewise.
1498
afa8d405
PB		 14992016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1500
1501 * ppc-opc.c <xscmpnedp>: Delete.
1502 <xvcmpnedp>: Likewise.
1503 <xvcmpnedp.>: Likewise.
1504 <xvcmpnesp>: Likewise.
1505 <xvcmpnesp.>: Likewise.
1506
83c3256e
AS		 15072016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1508
1509 PR gas/13050
1510 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1511 addition to ISA_A.
1512
6f2750fe
AM		 15132016-01-01 Alan Modra <amodra@gmail.com>
1514
1515 Update year range in copyright notice of all files.
1516
3499769a
AM		 1517For older changes see ChangeLog-2015
1518\f
1519Copyright (C) 2016 Free Software Foundation, Inc.
1520
1521Copying and distribution of this file, with or without modification,
1522are permitted in any medium without royalty provided the copyright
1523notice and this notice are preserved.
1524
1525Local Variables:
1526mode: change-log
1527left-margin: 8
1528fill-column: 74
1529version-control: never
1530End:
GDB Binutils - Deliverables
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