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Fix disassembly of RX zero-offset register indirect instructions.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
e292aa7a
NC		 12015-11-02 Nick Clifton <nickc@redhat.com>
2
3 * rx-decode.opc (rx_disp): If the displacement is zero, set the
4 type to RX_Operand_Zero_Indirect.
5 * rx-decode.c: Regenerate.
6 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
7
43cdf5ae
YQ		 82015-10-28 Yao Qi <yao.qi@linaro.org>
9
10 * aarch64-dis.c (aarch64_decode_insn): Add one argument
11 noaliases_p. Update comments. Pass noaliases_p rather than
12 no_aliases to aarch64_opcode_decode.
13 (print_insn_aarch64_word): Pass no_aliases to
14 aarch64_decode_insn.
15
c2f28758
VK		 162015-10-27 Vinay <Vinay.G@kpit.com>
17
18 PR binutils/19159
19 * rl78-decode.opc (MOV): Added offset to DE register in index
20 addressing mode.
21 * rl78-decode.c: Regenerate.
22
46662804
VK		 232015-10-27 Vinay Kumar <vinay.g@kpit.com>
24
25 PR binutils/19158
26 * rl78-decode.opc: Add 's' print operator to instructions that
27 access system registers.
28 * rl78-decode.c: Regenerate.
29 * rl78-dis.c (print_insn_rl78_common): Decode all system
30 registers.
31
02f12cd4
VK		 322015-10-27 Vinay Kumar <vinay.g@kpit.com>
33
34 PR binutils/19157
35 * rl78-decode.opc: Add 'a' print operator to mov instructions
36 using stack pointer plus index addressing.
37 * rl78-decode.c: Regenerate.
38
485f23cf
AK		 392015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
40
41 * s390-opc.c: Fix comment.
42 * s390-opc.txt: Change instruction type for troo, trot, trto, and
43 trtt to RRF_U0RER since the second parameter does not need to be a
44 register pair.
45
3f94e60d
NC		 462015-10-08 Nick Clifton <nickc@redhat.com>
47
48 * arc-dis.c (print_insn_arc): Initiallise insn array.
49
875880c6
YQ		 502015-10-07 Yao Qi <yao.qi@linaro.org>
51
52 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
53 'name' rather than 'template'.
54 * aarch64-opc.c (aarch64_print_operand): Likewise.
55
886a2506
NC		 562015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
57
58 * arc-dis.c: Revamped file for ARC support
59 * arc-dis.h: Likewise.
60 * arc-ext.c: Likewise.
61 * arc-ext.h: Likewise.
62 * arc-opc.c: Likewise.
63 * arc-fxi.h: New file.
64 * arc-regs.h: Likewise.
65 * arc-tbl.h: Likewise.
66
36f4aab1
YQ		 672015-10-02 Yao Qi <yao.qi@linaro.org>
68
69 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
70 argument insn type to aarch64_insn. Rename to ...
71 (aarch64_decode_insn): ... it.
72 (print_insn_aarch64_word): Caller updated.
73
7232d389
YQ		 742015-10-02 Yao Qi <yao.qi@linaro.org>
75
76 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
77 (print_insn_aarch64_word): Caller updated.
78
7ecc513a
DV		 792015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
80
81 * s390-mkopc.c (main): Parse htm and vx flag.
82 * s390-opc.txt: Mark instructions from the hardware transactional
83 memory and vector facilities with the "htm"/"vx" flag.
84
b08b78e7
NC		 852015-09-28 Nick Clifton <nickc@redhat.com>
86
87 * po/de.po: Updated German translation.
88
36f7a941
TR		 892015-09-28 Tom Rix <tom@bumblecow.com>
90
91 * ppc-opc.c (PPC500): Mark some opcodes as invalid
92
b6518b38
NC		 932015-09-23 Nick Clifton <nickc@redhat.com>
94
95 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
96 function.
97 * tic30-dis.c (print_branch): Likewise.
98 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
99 value before left shifting.
100 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
101 * hppa-dis.c (print_insn_hppa): Likewise.
102 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
103 array.
104 * msp430-dis.c (msp430_singleoperand): Likewise.
105 (msp430_doubleoperand): Likewise.
106 (print_insn_msp430): Likewise.
107 * nds32-asm.c (parse_operand): Likewise.
108 * sh-opc.h (MASK): Likewise.
109 * v850-dis.c (get_operand_value): Likewise.
110
f04265ec
NC		 1112015-09-22 Nick Clifton <nickc@redhat.com>
112
113 * rx-decode.opc (bwl): Use RX_Bad_Size.
114 (sbwl): Likewise.
115 (ubwl): Likewise. Rename to ubw.
116 (uBWL): Rename to uBW.
117 Replace all references to uBWL with uBW.
118 * rx-decode.c: Regenerate.
119 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
120 (opsize_names): Likewise.
121 (print_insn_rx): Detect and report RX_Bad_Size.
122
6dca4fd1
AB		 1232015-09-22 Anton Blanchard <anton@samba.org>
124
125 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
126
38074311
JM		 1272015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
128
129 * sparc-dis.c (print_insn_sparc): Handle the privileged register
130 %pmcdper.
131
5f40e14d
JS		 1322015-08-24 Jan Stancek <jstancek@redhat.com>
133
134 * i386-dis.c (print_insn): Fix decoding of three byte operands.
135
ab4e4ed5
AF		 1362015-08-21 Alexander Fomin <alexander.fomin@intel.com>
137
138 PR binutils/18257
139 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
140 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
141 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
142 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
143 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
144 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
145 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
146 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
147 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
148 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
149 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
150 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
151 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
152 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
153 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
154 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
155 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
156 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
157 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
158 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
159 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
160 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
161 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
162 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
163 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
164 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
165 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
166 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
167 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
168 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
169 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
170 (vex_w_table): Replace terminals with MOD_TABLE entries for
171 most of mask instructions.
172
919b75f7
AM		 1732015-08-17 Alan Modra <amodra@gmail.com>
174
175 * cgen.sh: Trim trailing space from cgen output.
176 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
177 (print_dis_table): Likewise.
178 * opc2c.c (dump_lines): Likewise.
179 (orig_filename): Warning fix.
180 * ia64-asmtab.c: Regenerate.
181
4ab90a7a
AV		 1822015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
183
184 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
185 and higher with ARM instruction set will now mark the 26-bit
186 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
187 (arm_opcodes): Fix for unpredictable nop being recognized as a
188 teq.
189
40fc1451
SD		 1902015-08-12 Simon Dardis <simon.dardis@imgtec.com>
191
192 * micromips-opc.c (micromips_opcodes): Re-order table so that move
193 based on 'or' is first.
194 * mips-opc.c (mips_builtin_opcodes): Ditto.
195
922c5db5
NC		 1962015-08-11 Nick Clifton <nickc@redhat.com>
197
198 PR 18800
199 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
200 instruction.
201
75fb7498
RS		 2022015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
203
204 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
205
36aed29d
AP		 2062015-08-07 Amit Pawar <Amit.Pawar@amd.com>
207
208 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
209 * i386-init.h: Regenerated.
210
a8484f96
L		 2112015-07-30 H.J. Lu <hongjiu.lu@intel.com>
212
213 PR binutils/13571
214 * i386-dis.c (MOD_0FC3): New.
215 (PREFIX_0FC3): Renamed to ...
216 (PREFIX_MOD_0_0FC3): This.
217 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
218 (prefix_table): Replace Ma with Ev on movntiS.
219 (mod_table): Add MOD_0FC3.
220
37a42ee9
L		 2212015-07-27 H.J. Lu <hongjiu.lu@intel.com>
222
223 * configure: Regenerated.
224
070fe95d
AM		 2252015-07-23 Alan Modra <amodra@gmail.com>
226
227 PR 18708
228 * i386-dis.c (get64): Avoid signed integer overflow.
229
20c2a615
L		 2302015-07-22 Alexander Fomin <alexander.fomin@intel.com>
231
232 PR binutils/18631
233 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
234 "EXEvexHalfBcstXmmq" for the second operand.
235 (EVEX_W_0F79_P_2): Likewise.
236 (EVEX_W_0F7A_P_2): Likewise.
237 (EVEX_W_0F7B_P_2): Likewise.
238
6f1c2142
AM		 2392015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
240
241 * arm-dis.c (print_insn_coprocessor): Added support for quarter
242 float bitfield format.
243 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
244 quarter float bitfield format.
245
8a643cc3
L		 2462015-07-14 H.J. Lu <hongjiu.lu@intel.com>
247
248 * configure: Regenerated.
249
ef5a96d5
AM		 2502015-07-03 Alan Modra <amodra@gmail.com>
251
252 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
253 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
254 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
255
c8c8175b
SL		 2562015-07-01 Sandra Loosemore <sandra@codesourcery.com>
257 Cesar Philippidis <cesar@codesourcery.com>
258
259 * nios2-dis.c (nios2_extract_opcode): New.
260 (nios2_disassembler_state): New.
261 (nios2_find_opcode_hash): Use mach parameter to select correct
262 disassembler state.
263 (nios2_print_insn_arg): Extend to support new R2 argument letters
264 and formats.
265 (print_insn_nios2): Check for 16-bit instruction at end of memory.
266 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
267 (NIOS2_NUM_OPCODES): Rename to...
268 (NIOS2_NUM_R1_OPCODES): This.
269 (nios2_r2_opcodes): New.
270 (NIOS2_NUM_R2_OPCODES): New.
271 (nios2_num_r2_opcodes): New.
272 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
273 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
274 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
275 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
276 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
277
9916071f
AP		 2782015-06-30 Amit Pawar <Amit.Pawar@amd.com>
279
280 * i386-dis.c (OP_Mwaitx): New.
281 (rm_table): Add monitorx/mwaitx.
282 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
283 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
284 (operand_type_init): Add CpuMWAITX.
285 * i386-opc.h (CpuMWAITX): New.
286 (i386_cpu_flags): Add cpumwaitx.
287 * i386-opc.tbl: Add monitorx and mwaitx.
288 * i386-init.h: Regenerated.
289 * i386-tbl.h: Likewise.
290
7b934113
PB		 2912015-06-22 Peter Bergner <bergner@vnet.ibm.com>
292
293 * ppc-opc.c (insert_ls): Test for invalid LS operands.
294 (insert_esync): New function.
295 (LS, WC): Use insert_ls.
296 (ESYNC): Use insert_esync.
297
bdc4de1b
NC		 2982015-06-22 Nick Clifton <nickc@redhat.com>
299
300 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
301 requested region lies beyond it.
302 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
303 looking for 32-bit insns.
304 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
305 data.
306 * sh-dis.c (print_insn_sh): Likewise.
307 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
308 blocks of instructions.
309 * vax-dis.c (print_insn_vax): Check that the requested address
310 does not clash with the stop_vma.
311
11a0cf2e
PB		 3122015-06-19 Peter Bergner <bergner@vnet.ibm.com>
313
070fe95d 314 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 315 * ppc-opc.c (FXM4): Add non-zero optional value.
316 (TBR): Likewise.
317 (SXL): Likewise.
318 (insert_fxm): Handle new default operand value.
319 (extract_fxm): Likewise.
320 (insert_tbr): Likewise.
321 (extract_tbr): Likewise.
322
bdfa8b95
MW		 3232015-06-16 Matthew Wahab <matthew.wahab@arm.com>
324
325 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
326
24b4cf66
SN		 3272015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
328
329 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
330
99a2c561
PB		 3312015-06-12 Peter Bergner <bergner@vnet.ibm.com>
332
333 * ppc-opc.c: Add comment accidentally removed by old commit.
334 (MTMSRD_L): Delete.
335
40f77f82
AM		 3362015-06-04 Peter Bergner <bergner@vnet.ibm.com>
337
338 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
339
13be46a2
NC		 3402015-06-04 Nick Clifton <nickc@redhat.com>
341
342 PR 18474
343 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
344
ddfded2f
MW		 3452015-06-02 Matthew Wahab <matthew.wahab@arm.com>
346
347 * arm-dis.c (arm_opcodes): Add "setpan".
348 (thumb_opcodes): Add "setpan".
349
1af1dd51
MW		 3502015-06-02 Matthew Wahab <matthew.wahab@arm.com>
351
352 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
353 macros.
354
9e1f0fa7
MW		 3552015-06-02 Matthew Wahab <matthew.wahab@arm.com>
356
357 * aarch64-tbl.h (aarch64_feature_rdma): New.
358 (RDMA): New.
359 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
360 * aarch64-asm-2.c: Regenerate.
361 * aarch64-dis-2.c: Regenerate.
362 * aarch64-opc-2.c: Regenerate.
363
290806fd
MW		 3642015-06-02 Matthew Wahab <matthew.wahab@arm.com>
365
366 * aarch64-tbl.h (aarch64_feature_lor): New.
367 (LOR): New.
368 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
369 "stllrb", "stllrh".
370 * aarch64-asm-2.c: Regenerate.
371 * aarch64-dis-2.c: Regenerate.
372 * aarch64-opc-2.c: Regenerate.
373
f21cce2c
MW		 3742015-06-01 Matthew Wahab <matthew.wahab@arm.com>
375
376 * aarch64-opc.c (F_ARCHEXT): New.
377 (aarch64_sys_regs): Add "pan".
378 (aarch64_sys_reg_supported_p): New.
379 (aarch64_pstatefields): Add "pan".
380 (aarch64_pstatefield_supported_p): New.
381
d194d186
JB		 3822015-06-01 Jan Beulich <jbeulich@suse.com>
383
384 * i386-tbl.h: Regenerate.
385
3a8547d2
JB		 3862015-06-01 Jan Beulich <jbeulich@suse.com>
387
388 * i386-dis.c (print_insn): Swap rounding mode specifier and
389 general purpose register in Intel mode.
390
015c54d5
JB		 3912015-06-01 Jan Beulich <jbeulich@suse.com>
392
393 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
394 * i386-tbl.h: Regenerate.
395
071f0063
L		 3962015-05-18 H.J. Lu <hongjiu.lu@intel.com>
397
398 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
399 * i386-init.h: Regenerated.
400
5db04b09
L		 4012015-05-15 H.J. Lu <hongjiu.lu@intel.com>
402
403 PR binutis/18386
404 * i386-dis.c: Add comments for '@'.
405 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
406 (enum x86_64_isa): New.
407 (isa64): Likewise.
408 (print_i386_disassembler_options): Add amd64 and intel64.
409 (print_insn): Handle amd64 and intel64.
410 (putop): Handle '@'.
411 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
412 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
413 * i386-opc.h (AMD64): New.
414 (CpuIntel64): Likewise.
415 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
416 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
417 Mark direct call/jmp without Disp16|Disp32 as Intel64.
418 * i386-init.h: Regenerated.
419 * i386-tbl.h: Likewise.
420
4bc0608a
PB		 4212015-05-14 Peter Bergner <bergner@vnet.ibm.com>
422
423 * ppc-opc.c (IH) New define.
424 (powerpc_opcodes) <wait>: Do not enable for POWER7.
425 <tlbie>: Add RS operand for POWER7.
426 <slbia>: Add IH operand for POWER6.
427
70cead07
L		 4282015-05-11 H.J. Lu <hongjiu.lu@intel.com>
429
430 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
431 direct branch.
432 (jmp): Likewise.
433 * i386-tbl.h: Regenerated.
434
7b6d09fb
L		 4352015-05-11 H.J. Lu <hongjiu.lu@intel.com>
436
437 * configure.ac: Support bfd_iamcu_arch.
438 * disassemble.c (disassembler): Support bfd_iamcu_arch.
439 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
440 CPU_IAMCU_COMPAT_FLAGS.
441 (cpu_flags): Add CpuIAMCU.
442 * i386-opc.h (CpuIAMCU): New.
443 (i386_cpu_flags): Add cpuiamcu.
444 * configure: Regenerated.
445 * i386-init.h: Likewise.
446 * i386-tbl.h: Likewise.
447
31955f99
L		 4482015-05-08 H.J. Lu <hongjiu.lu@intel.com>
449
450 PR binutis/18386
451 * i386-dis.c (X86_64_E8): New.
452 (X86_64_E9): Likewise.
453 Update comments on 'T', 'U', 'V'. Add comments for '^'.
454 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
455 (x86_64_table): Add X86_64_E8 and X86_64_E9.
456 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
457 (putop): Handle '^'.
458 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
459 REX_W.
460
0952813b
DD		 4612015-04-30 DJ Delorie <dj@redhat.com>
462
463 * disassemble.c (disassembler): Choose suitable disassembler based
464 on E_ABI.
465 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
466 it to decode mul/div insns.
467 * rl78-decode.c: Regenerate.
468 * rl78-dis.c (print_insn_rl78): Rename to...
469 (print_insn_rl78_common): ...this, take ISA parameter.
470 (print_insn_rl78): New.
471 (print_insn_rl78_g10): New.
472 (print_insn_rl78_g13): New.
473 (print_insn_rl78_g14): New.
474 (rl78_get_disassembler): New.
475
f9d3ecaa
NC		 4762015-04-29 Nick Clifton <nickc@redhat.com>
477
478 * po/fr.po: Updated French translation.
479
4fff86c5
PB		 4802015-04-27 Peter Bergner <bergner@vnet.ibm.com>
481
482 * ppc-opc.c (DCBT_EO): New define.
483 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
484 <lharx>: Likewise.
485 <stbcx.>: Likewise.
486 <sthcx.>: Likewise.
487 <waitrsv>: Do not enable for POWER7 and later.
488 <waitimpl>: Likewise.
489 <dcbt>: Default to the two operand form of the instruction for all
490 "old" cpus. For "new" cpus, use the operand ordering that matches
491 whether the cpu is server or embedded.
492 <dcbtst>: Likewise.
493
3b78cfe1
AK		 4942015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
495
496 * s390-opc.c: New instruction type VV0UU2.
497 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
498 and WFC.
499
04d824a4
JB		 5002015-04-23 Jan Beulich <jbeulich@suse.com>
501
502 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
503 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
504 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
505 (vfpclasspd, vfpclassps): Add %XZ.
506
09708981
L		 5072015-04-15 H.J. Lu <hongjiu.lu@intel.com>
508
509 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
510 (PREFIX_UD_REPZ): Likewise.
511 (PREFIX_UD_REPNZ): Likewise.
512 (PREFIX_UD_DATA): Likewise.
513 (PREFIX_UD_ADDR): Likewise.
514 (PREFIX_UD_LOCK): Likewise.
515
3888916d
L		 5162015-04-15 H.J. Lu <hongjiu.lu@intel.com>
517
518 * i386-dis.c (prefix_requirement): Removed.
519 (print_insn): Don't set prefix_requirement. Check
520 dp->prefix_requirement instead of prefix_requirement.
521
f24bcbaa
L		 5222015-04-15 H.J. Lu <hongjiu.lu@intel.com>
523
524 PR binutils/17898
525 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
526 (PREFIX_MOD_0_0FC7_REG_6): This.
527 (PREFIX_MOD_3_0FC7_REG_6): New.
528 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
529 (prefix_table): Replace PREFIX_0FC7_REG_6 with
530 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
531 PREFIX_MOD_3_0FC7_REG_7.
532 (mod_table): Replace PREFIX_0FC7_REG_6 with
533 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
534 PREFIX_MOD_3_0FC7_REG_7.
535
507bd325
L		 5362015-04-15 H.J. Lu <hongjiu.lu@intel.com>
537
538 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
539 (PREFIX_MANDATORY_REPNZ): Likewise.
540 (PREFIX_MANDATORY_DATA): Likewise.
541 (PREFIX_MANDATORY_ADDR): Likewise.
542 (PREFIX_MANDATORY_LOCK): Likewise.
543 (PREFIX_MANDATORY): Likewise.
544 (PREFIX_UD_SHIFT): Set to 8
545 (PREFIX_UD_REPZ): Updated.
546 (PREFIX_UD_REPNZ): Likewise.
547 (PREFIX_UD_DATA): Likewise.
548 (PREFIX_UD_ADDR): Likewise.
549 (PREFIX_UD_LOCK): Likewise.
550 (PREFIX_IGNORED_SHIFT): New.
551 (PREFIX_IGNORED_REPZ): Likewise.
552 (PREFIX_IGNORED_REPNZ): Likewise.
553 (PREFIX_IGNORED_DATA): Likewise.
554 (PREFIX_IGNORED_ADDR): Likewise.
555 (PREFIX_IGNORED_LOCK): Likewise.
556 (PREFIX_OPCODE): Likewise.
557 (PREFIX_IGNORED): Likewise.
558 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
559 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
560 (three_byte_table): Likewise.
561 (mod_table): Likewise.
562 (mandatory_prefix): Renamed to ...
563 (prefix_requirement): This.
564 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
565 Update PREFIX_90 entry.
566 (get_valid_dis386): Check prefix_requirement to see if a prefix
567 should be ignored.
568 (print_insn): Replace mandatory_prefix with prefix_requirement.
569
f0fba320
RL		 5702015-04-15 Renlin Li <renlin.li@arm.com>
571
572 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
573 use it for ssat and ssat16.
574 (print_insn_thumb32): Add handle case for 'D' control code.
575
bf890a93
IT		 5762015-04-06 Ilya Tocar <ilya.tocar@intel.com>
577 H.J. Lu <hongjiu.lu@intel.com>
578
579 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
580 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
581 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
582 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
583 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
584 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
585 Fill prefix_requirement field.
586 (struct dis386): Add prefix_requirement field.
587 (dis386): Fill prefix_requirement field.
588 (dis386_twobyte): Ditto.
589 (twobyte_has_mandatory_prefix_: Remove.
590 (reg_table): Fill prefix_requirement field.
591 (prefix_table): Ditto.
592 (x86_64_table): Ditto.
593 (three_byte_table): Ditto.
594 (xop_table): Ditto.
595 (vex_table): Ditto.
596 (vex_len_table): Ditto.
597 (vex_w_table): Ditto.
598 (mod_table): Ditto.
599 (bad_opcode): Ditto.
600 (print_insn): Use prefix_requirement.
601 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
602 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
603 (float_reg): Ditto.
604
2f783c1f
MF		 6052015-03-30 Mike Frysinger <vapier@gentoo.org>
606
607 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
608
b9d94d62
L		 6092015-03-29 H.J. Lu <hongjiu.lu@intel.com>
610
611 * Makefile.in: Regenerated.
612
27c49e9a
AB		 6132015-03-25 Anton Blanchard <anton@samba.org>
614
615 * ppc-dis.c (disassemble_init_powerpc): Only initialise
616 powerpc_opcd_indices and vle_opcd_indices once.
617
c4e676f1
AB		 6182015-03-25 Anton Blanchard <anton@samba.org>
619
620 * ppc-opc.c (powerpc_opcodes): Add slbfee.
621
823d2571
TG		 6222015-03-24 Terry Guo <terry.guo@arm.com>
623
624 * arm-dis.c (opcode32): Updated to use new arm feature struct.
625 (opcode16): Likewise.
626 (coprocessor_opcodes): Replace bit with feature struct.
627 (neon_opcodes): Likewise.
628 (arm_opcodes): Likewise.
629 (thumb_opcodes): Likewise.
630 (thumb32_opcodes): Likewise.
631 (print_insn_coprocessor): Likewise.
632 (print_insn_arm): Likewise.
633 (select_arm_features): Follow new feature struct.
634
029f3522
GG		 6352015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
636
637 * i386-dis.c (rm_table): Add clzero.
638 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
639 Add CPU_CLZERO_FLAGS.
640 (cpu_flags): Add CpuCLZERO.
641 * i386-opc.h: Add CpuCLZERO.
642 * i386-opc.tbl: Add clzero.
643 * i386-init.h: Re-generated.
644 * i386-tbl.h: Re-generated.
645
6914869a
AB		 6462015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
647
648 * mips-opc.c (decode_mips_operand): Fix constraint issues
649 with u and y operands.
650
21e20815
AB		 6512015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
652
653 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
654
6b1d7593
AK		 6552015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
656
657 * s390-opc.c: Add new IBM z13 instructions.
658 * s390-opc.txt: Likewise.
659
c8f89a34
JW		 6602015-03-10 Renlin Li <renlin.li@arm.com>
661
662 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
663 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
664 related alias.
665 * aarch64-asm-2.c: Regenerate.
666 * aarch64-dis-2.c: Likewise.
667 * aarch64-opc-2.c: Likewise.
668
d8282f0e
JW		 6692015-03-03 Jiong Wang <jiong.wang@arm.com>
670
671 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
672
ac994365
OE		 6732015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
674
675 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
676 arch_sh_up.
677 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
678 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
679
fd63f640
V		 6802015-02-23 Vinay <Vinay.G@kpit.com>
681
682 * rl78-decode.opc (MOV): Added space between two operands for
683 'mov' instruction in index addressing mode.
684 * rl78-decode.c: Regenerate.
685
f63c1776
PA		 6862015-02-19 Pedro Alves <palves@redhat.com>
687
688 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
689
07774fcc
PA		 6902015-02-10 Pedro Alves <palves@redhat.com>
691 Tom Tromey <tromey@redhat.com>
692
693 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
694 microblaze_and, microblaze_xor.
695 * microblaze-opc.h (opcodes): Adjust.
696
3f8107ab
AM		 6972015-01-28 James Bowman <james.bowman@ftdichip.com>
698
699 * Makefile.am: Add FT32 files.
700 * configure.ac: Handle FT32.
701 * disassemble.c (disassembler): Call print_insn_ft32.
702 * ft32-dis.c: New file.
703 * ft32-opc.c: New file.
704 * Makefile.in: Regenerate.
705 * configure: Regenerate.
706 * po/POTFILES.in: Regenerate.
707
e5fe4957
KLC		 7082015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
709
710 * nds32-asm.c (keyword_sr): Add new system registers.
711
1e2e8c52
AK		 7122015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
713
714 * s390-dis.c (s390_extract_operand): Support vector register
715 operands.
716 (s390_print_insn_with_opcode): Support new operands types and add
717 new handling of optional operands.
718 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
719 and include opcode/s390.h instead.
720 (struct op_struct): New field `flags'.
721 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
722 (dumpTable): Dump flags.
723 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
724 string.
725 * s390-opc.c: Add new operands types, instruction formats, and
726 instruction masks.
727 (s390_opformats): Add new formats for .insn.
728 * s390-opc.txt: Add new instructions.
729
b90efa5b 7302015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 731
b90efa5b 732 Update year range in copyright notice of all files.
bffb6004 733
b90efa5b 734For older changes see ChangeLog-2014
252b5132 735\f
b90efa5b 736Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 737
738Copying and distribution of this file, with or without modification,
739are permitted in any medium without royalty provided the copyright
740notice and this notice are preserved.
741
252b5132 742Local Variables:
2f6d2f85
NC		 743mode: change-log
744left-margin: 8
745fill-column: 74
252b5132
RH		 746version-control: never
747End:
GDB Binutils - Deliverables
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