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* Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
a656ed5b
L		 12008-08-01 H.J. Lu <hongjiu.lu@intel.com>
2
3 * i386-reg.tbl: Use Dw2Inval on AVX registers.
4 * i386-tbl.h: Regenerated.
5
081ba1b3
AM		 62008-07-30 Michael J. Eager <eager@eagercon.com>
7
8 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
9 * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
10 (insert_sprg, PPC405): Use PPC_OPCODE_405.
11 (powerpc_opcodes): Add Xilinx APU related opcodes.
12
0af1713e
AM		 132008-07-30 Alan Modra <amodra@bigpond.net.au>
14
15 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
16
30c09090
RS		 172008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
18
19 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
20
c27e721e
AN		 212008-07-07 Adam Nemet <anemet@caviumnetworks.com>
22
23 * mips-opc.c (CP): New macro.
24 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
25 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
26 dmtc2 Octeon instructions.
27
bd2e2557
SS		 282008-07-07 Stan Shebs <stan@codesourcery.com>
29
30 * dis-init.c (init_disassemble_info): Init endian_code field.
31 * arm-dis.c (print_insn): Disassemble code according to
32 setting of endian_code.
33 (print_insn_big_arm): Detect when BE8 extension flag has been set.
34
6ba2a415
RS		 352008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
36
37 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
38 for ELF symbols.
39
c8187e15
PB		 402008-06-25 Peter Bergner <bergner@vnet.ibm.com>
41
42 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
43 (print_ppc_disassembler_options): Likewise.
44 * ppc-opc.c (PPC464): Define.
45 (powerpc_opcodes): Add mfdcrux and mtdcrux.
46
7a283e07
RW		 472008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
48
49 * configure: Regenerate.
50
fa452fa6
PB		 512008-06-13 Peter Bergner <bergner@vnet.ibm.com>
52
53 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
54 ppc_cpu_t typedef.
55 (struct dis_private): New.
56 (POWERPC_DIALECT): New define.
57 (powerpc_dialect): Renamed to...
58 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
59 struct dis_private.
60 (print_insn_big_powerpc): Update for using structure in
61 info->private_data.
62 (print_insn_little_powerpc): Likewise.
63 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
64 (skip_optional_operands): Likewise.
65 (print_insn_powerpc): Likewise. Remove initialization of dialect.
66 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
67 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
68 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
69 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
70 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
71 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
72 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
73 param to be of type ppc_cpu_t. Update prototype.
74
bb35fb24
NC		 752008-06-12 Adam Nemet <anemet@caviumnetworks.com>
76
77 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
78 +s, +S.
79 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
80 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
81 syncw, syncws, vm3mulu, vm0 and vmulu.
82
dd3cbb7e
NC		 83 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
84 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
85 seqi, sne and snei.
86
a5dabbb0
L		 872008-05-30 H.J. Lu <hongjiu.lu@intel.com>
88
89 * i386-opc.tbl: Add vmovd with 64bit operand.
90 * i386-tbl.h: Regenerated.
91
725a9891
MS		 922008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
93
94 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
95
cbc80391
L		 962008-05-22 H.J. Lu <hongjiu.lu@intel.com>
97
98 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
99 * i386-tbl.h: Regenerated.
100
116615c5
L		 1012008-05-22 H.J. Lu <hongjiu.lu@intel.com>
102
103 PR gas/6517
104 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
105 into 32bit and 64bit. Remove Reg64|Qword and add
106 IgnoreSize|No_qSuf on 32bit version.
107 * i386-tbl.h: Regenerated.
108
d9479f2d
L		 1092008-05-21 H.J. Lu <hongjiu.lu@intel.com>
110
111 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
112 * i386-tbl.h: Regenerated.
113
3ce6fddb
NC		 1142008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
115
116 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
117
8944f3c2
AM		 1182008-05-14 Alan Modra <amodra@bigpond.net.au>
119
120 * Makefile.am: Run "make dep-am".
121 * Makefile.in: Regenerate.
122
f1f8f695
L		 1232008-05-02 H.J. Lu <hongjiu.lu@intel.com>
124
125 * i386-dis.c (MOVBE_Fixup): New.
126 (Mo): Likewise.
127 (PREFIX_0F3880): Likewise.
128 (PREFIX_0F3881): Likewise.
129 (PREFIX_0F38F0): Updated.
130 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
131 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
132 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
133
134 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
135 CPU_EPT_FLAGS.
136 (cpu_flags): Add CpuMovbe and CpuEPT.
137
138 * i386-opc.h (CpuMovbe): New.
139 (CpuEPT): Likewise.
140 (CpuLM): Updated.
141 (i386_cpu_flags): Add cpumovbe and cpuept.
142
143 * i386-opc.tbl: Add entries for movbe and EPT instructions.
144 * i386-init.h: Regenerated.
145 * i386-tbl.h: Likewise.
146
89aa3097
AN		 1472008-04-29 Adam Nemet <anemet@caviumnetworks.com>
148
149 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
150 the two drem and the two dremu macros.
151
39c5c168
AN		 1522008-04-28 Adam Nemet <anemet@caviumnetworks.com>
153
154 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
155 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
156 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
157 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
158
f04d18b7
DM		 1592008-04-25 David S. Miller <davem@davemloft.net>
160
161 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
162 instead of %sys_tick_cmpr, as suggested in architecture manuals.
163
6194aaab
L		 1642008-04-23 Paolo Bonzini <bonzini@gnu.org>
165
166 * aclocal.m4: Regenerate.
167 * configure: Regenerate.
168
1a6b486f
DM		 1692008-04-23 David S. Miller <davem@davemloft.net>
170
171 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
172 extended values.
173 (prefetch_table): Add missing values.
174
81f8a913
L		 1752008-04-22 H.J. Lu <hongjiu.lu@intel.com>
176
177 * i386-gen.c (opcode_modifiers): Add NoAVX.
178
179 * i386-opc.h (NoAVX): New.
180 (OldGcc): Updated.
181 (i386_opcode_modifier): Add noavx.
182
183 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
184 instructions which don't have AVX equivalent.
185 * i386-tbl.h: Regenerated.
186
dae39acc
L		 1872008-04-18 H.J. Lu <hongjiu.lu@intel.com>
188
189 * i386-dis.c (OP_VEX_FMA): New.
190 (OP_EX_VexImmW): Likewise.
191 (VexFMA): Likewise.
192 (Vex128FMA): Likewise.
193 (EXVexImmW): Likewise.
194 (get_vex_imm8): Likewise.
195 (OP_EX_VexReg): Likewise.
196 (vex_i4_done): Renamed to ...
197 (vex_w_done): This.
198 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
199 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
200 FMA instructions.
201 (print_insn): Updated.
202 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
203 (OP_REG_VexI4): Check invalid high registers.
204
ce886ab1
DR		 2052008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
206 Michael Meissner <michael.meissner@amd.com>
207
208 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
209 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 210
19a6653c
AM		 2112008-04-14 Edmar Wienskoski <edmar@freescale.com>
212
213 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
214 accept Power E500MC instructions.
215 (print_ppc_disassembler_options): Document -Me500mc.
216 * ppc-opc.c (DUIS, DUI, T): New.
217 (XRT, XRTRA): Likewise.
218 (E500MC): Likewise.
219 (powerpc_opcodes): Add new Power E500MC instructions.
220
112b7c50
AK		 2212008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
222
223 * s390-dis.c (init_disasm): Evaluate disassembler_options.
224 (print_s390_disassembler_options): New function.
225 * disassemble.c (disassembler_usage): Invoke
226 print_s390_disassembler_options.
227
7ff42648
AK		 2282008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
229
230 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
231 of local variables used for mnemonic parsing: prefix, suffix and
232 number.
233
45a5551e
AK		 2342008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
235
236 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
237 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
238 (s390_crb_extensions): New extensions table.
239 (insertExpandedMnemonic): Handle '$' tag.
240 * s390-opc.txt: Remove conditional jump variants which can now
241 be expanded automatically.
242 Replace '*' tag with '$' in the compare and branch instructions.
243
06c8514a
L		 2442008-04-07 H.J. Lu <hongjiu.lu@intel.com>
245
246 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
247 (PREFIX_VEX_3AXX): Likewis.
248
b122c285
L		 2492008-04-07 H.J. Lu <hongjiu.lu@intel.com>
250
251 * i386-opc.tbl: Remove 4 extra blank lines.
252
594ab6a3
L		 2532008-04-04 H.J. Lu <hongjiu.lu@intel.com>
254
255 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
256 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
257 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
258 * i386-opc.tbl: Likewise.
259
260 * i386-opc.h (CpuCLMUL): Renamed to ...
261 (CpuPCLMUL): This.
262 (CpuFMA): Updated.
263 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
264
265 * i386-init.h: Regenerated.
266
c0f3af97
L		 2672008-04-03 H.J. Lu <hongjiu.lu@intel.com>
268
269 * i386-dis.c (OP_E_register): New.
270 (OP_E_memory): Likewise.
271 (OP_VEX): Likewise.
272 (OP_EX_Vex): Likewise.
273 (OP_EX_VexW): Likewise.
274 (OP_XMM_Vex): Likewise.
275 (OP_XMM_VexW): Likewise.
276 (OP_REG_VexI4): Likewise.
277 (PCLMUL_Fixup): Likewise.
278 (VEXI4_Fixup): Likewise.
279 (VZERO_Fixup): Likewise.
280 (VCMP_Fixup): Likewise.
281 (VPERMIL2_Fixup): Likewise.
282 (rex_original): Likewise.
283 (rex_ignored): Likewise.
284 (Mxmm): Likewise.
285 (XMM): Likewise.
286 (EXxmm): Likewise.
287 (EXxmmq): Likewise.
288 (EXymmq): Likewise.
289 (Vex): Likewise.
290 (Vex128): Likewise.
291 (Vex256): Likewise.
292 (VexI4): Likewise.
293 (EXdVex): Likewise.
294 (EXqVex): Likewise.
295 (EXVexW): Likewise.
296 (EXdVexW): Likewise.
297 (EXqVexW): Likewise.
298 (XMVex): Likewise.
299 (XMVexW): Likewise.
300 (XMVexI4): Likewise.
301 (PCLMUL): Likewise.
302 (VZERO): Likewise.
303 (VCMP): Likewise.
304 (VPERMIL2): Likewise.
305 (xmm_mode): Likewise.
306 (xmmq_mode): Likewise.
307 (ymmq_mode): Likewise.
308 (vex_mode): Likewise.
309 (vex128_mode): Likewise.
310 (vex256_mode): Likewise.
311 (USE_VEX_C4_TABLE): Likewise.
312 (USE_VEX_C5_TABLE): Likewise.
313 (USE_VEX_LEN_TABLE): Likewise.
314 (VEX_C4_TABLE): Likewise.
315 (VEX_C5_TABLE): Likewise.
316 (VEX_LEN_TABLE): Likewise.
317 (REG_VEX_XX): Likewise.
318 (MOD_VEX_XXX): Likewise.
319 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
320 (PREFIX_0F3A44): Likewise.
321 (PREFIX_0F3ADF): Likewise.
322 (PREFIX_VEX_XXX): Likewise.
323 (VEX_OF): Likewise.
324 (VEX_OF38): Likewise.
325 (VEX_OF3A): Likewise.
326 (VEX_LEN_XXX): Likewise.
327 (vex): Likewise.
328 (need_vex): Likewise.
329 (need_vex_reg): Likewise.
330 (vex_i4_done): Likewise.
331 (vex_table): Likewise.
332 (vex_len_table): Likewise.
333 (OP_REG_VexI4): Likewise.
334 (vex_cmp_op): Likewise.
335 (pclmul_op): Likewise.
336 (vpermil2_op): Likewise.
337 (m_mode): Updated.
338 (es_reg): Likewise.
339 (PREFIX_0F38F0): Likewise.
340 (PREFIX_0F3A60): Likewise.
341 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
342 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
343 and PREFIX_VEX_XXX entries.
344 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
345 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
346 PREFIX_0F3ADF.
347 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
348 Add MOD_VEX_XXX entries.
349 (ckprefix): Initialize rex_original and rex_ignored. Store the
350 REX byte in rex_original.
351 (get_valid_dis386): Handle the implicit prefix in VEX prefix
352 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
353 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
354 calling get_valid_dis386. Use rex_original and rex_ignored when
355 printing out REX.
356 (putop): Handle "XY".
357 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
358 ymmq_mode.
359 (OP_E_extended): Updated to use OP_E_register and
360 OP_E_memory.
361 (OP_XMM): Handle VEX.
362 (OP_EX): Likewise.
363 (XMM_Fixup): Likewise.
364 (CMP_Fixup): Use ARRAY_SIZE.
365
366 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
367 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
368 (operand_type_init): Add OPERAND_TYPE_REGYMM and
369 OPERAND_TYPE_VEX_IMM4.
370 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
371 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
372 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
373 VexImmExt and SSE2AVX.
374 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
375
376 * i386-opc.h (CpuAVX): New.
377 (CpuAES): Likewise.
378 (CpuCLMUL): Likewise.
379 (CpuFMA): Likewise.
380 (Vex): Likewise.
381 (Vex256): Likewise.
382 (VexNDS): Likewise.
383 (VexNDD): Likewise.
384 (VexW0): Likewise.
385 (VexW1): Likewise.
386 (Vex0F): Likewise.
387 (Vex0F38): Likewise.
388 (Vex0F3A): Likewise.
389 (Vex3Sources): Likewise.
390 (VexImmExt): Likewise.
391 (SSE2AVX): Likewise.
392 (RegYMM): Likewise.
393 (Ymmword): Likewise.
394 (Vex_Imm4): Likewise.
395 (Implicit1stXmm0): Likewise.
396 (CpuXsave): Updated.
397 (CpuLM): Likewise.
398 (ByteOkIntel): Likewise.
399 (OldGcc): Likewise.
400 (Control): Likewise.
401 (Unspecified): Likewise.
402 (OTMax): Likewise.
403 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
404 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
405 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
406 vex3sources, veximmext and sse2avx.
407 (i386_operand_type): Add regymm, ymmword and vex_imm4.
408
409 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
410
411 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
412
413 * i386-init.h: Regenerated.
414 * i386-tbl.h: Likewise.
415
b21c9cb4
BS		 4162008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
417
418 From Robin Getz <robin.getz@analog.com>
419 * bfin-dis.c (bu32): Typedef.
420 (enum const_forms_t): Add c_uimm32 and c_huimm32.
421 (constant_formats[]): Add uimm32 and huimm16.
422 (fmtconst_val): New.
423 (uimm32): Define.
424 (huimm32): Define.
425 (imm16_val): Define.
426 (luimm16_val): Define.
427 (struct saved_state): Define.
428 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
429 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
430 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
431 (get_allreg): New.
432 (decode_LDIMMhalf_0): Print out the whole register value.
433
ee171c8f
BS		 434 From Jie Zhang <jie.zhang@analog.com>
435 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
436 multiply and multiply-accumulate to data register instruction.
437
086134ec
BS		 438 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
439 c_imm32, c_huimm32e): Define.
440 (constant_formats): Add flags for printing decimal, leading spaces, and
441 exact symbols.
442 (comment, parallel): Add global flags in all disassembly.
443 (fmtconst): Take advantage of new flags, and print default in hex.
444 (fmtconst_val): Likewise.
445 (decode_macfunc): Be consistant with spaces, tabs, comments,
446 capitalization in disassembly, fix minor coding style issues.
447 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
448 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
449 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
450 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
451 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
452 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
453 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
454 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
455 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
456 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
457 _print_insn_bfin, print_insn_bfin): Likewise.
458
58c85be7
RW		 4592008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
460
461 * aclocal.m4: Regenerate.
462 * configure: Likewise.
463 * Makefile.in: Likewise.
464
50e7d84b
AM		 4652008-03-13 Alan Modra <amodra@bigpond.net.au>
466
467 * Makefile.am: Run "make dep-am".
468 * Makefile.in: Regenerate.
469 * configure: Regenerate.
470
de866fcc
AM		 4712008-03-07 Alan Modra <amodra@bigpond.net.au>
472
473 * ppc-opc.c (powerpc_opcodes): Order and format.
474
28dbc079
L		 4752008-03-01 H.J. Lu <hongjiu.lu@intel.com>
476
477 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
478 * i386-tbl.h: Regenerated.
479
849830bd
L		 4802008-02-23 H.J. Lu <hongjiu.lu@intel.com>
481
482 * i386-opc.tbl: Disallow 16-bit near indirect branches for
483 x86-64.
484 * i386-tbl.h: Regenerated.
485
743ddb6b
JB		 4862008-02-21 Jan Beulich <jbeulich@novell.com>
487
488 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
489 and Fword for far indirect jmp. Allow Reg16 and Word for near
490 indirect jmp on x86-64. Disallow Fword for lcall.
491 * i386-tbl.h: Re-generate.
492
796d5313
NC		 4932008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
494
495 * cr16-opc.c (cr16_num_optab): Defined
496
65da13b5
L		 4972008-02-16 H.J. Lu <hongjiu.lu@intel.com>
498
499 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
500 * i386-init.h: Regenerated.
501
0e336180
NC		 5022008-02-14 Nick Clifton <nickc@redhat.com>
503
504 PR binutils/5524
505 * configure.in (SHARED_LIBADD): Select the correct host specific
506 file extension for shared libraries.
507 * configure: Regenerate.
508
b7240065
JB		 5092008-02-13 Jan Beulich <jbeulich@novell.com>
510
511 * i386-opc.h (RegFlat): New.
512 * i386-reg.tbl (flat): Add.
513 * i386-tbl.h: Re-generate.
514
34b772a6
JB		 5152008-02-13 Jan Beulich <jbeulich@novell.com>
516
517 * i386-dis.c (a_mode): New.
518 (cond_jump_mode): Adjust.
519 (Ma): Change to a_mode.
520 (intel_operand_size): Handle a_mode.
521 * i386-opc.tbl: Allow Dword and Qword for bound.
522 * i386-tbl.h: Re-generate.
523
a60de03c
JB		 5242008-02-13 Jan Beulich <jbeulich@novell.com>
525
526 * i386-gen.c (process_i386_registers): Process new fields.
527 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
528 unsigned char. Add dw2_regnum and Dw2Inval.
529 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
530 register names.
531 * i386-tbl.h: Re-generate.
532
f03fe4c1
L		 5332008-02-11 H.J. Lu <hongjiu.lu@intel.com>
534
4b6bc8eb 535 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 536 * i386-init.h: Updated.
537
475a2301
L		 5382008-02-11 H.J. Lu <hongjiu.lu@intel.com>
539
540 * i386-gen.c (cpu_flags): Add CpuXsave.
541
542 * i386-opc.h (CpuXsave): New.
4b6bc8eb 543 (CpuLM): Updated.
475a2301
L		 544 (i386_cpu_flags): Add cpuxsave.
545
546 * i386-dis.c (MOD_0FAE_REG_4): New.
547 (RM_0F01_REG_2): Likewise.
548 (MOD_0FAE_REG_5): Updated.
549 (RM_0F01_REG_3): Likewise.
550 (reg_table): Use MOD_0FAE_REG_4.
551 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
552 for xrstor.
553 (rm_table): Add RM_0F01_REG_2.
554
555 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
556 * i386-init.h: Regenerated.
557 * i386-tbl.h: Likewise.
558
595785c6 5592008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 560
595785c6
JB		 561 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
562 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
563 * i386-tbl.h: Re-generate.
564
bb8541b9
L		 5652008-02-04 H.J. Lu <hongjiu.lu@intel.com>
566
567 PR 5715
568 * configure: Regenerated.
569
57b592a3
AN		 5702008-02-04 Adam Nemet <anemet@caviumnetworks.com>
571
572 * mips-dis.c: Update copyright.
573 (mips_arch_choices): Add Octeon.
574 * mips-opc.c: Update copyright.
575 (IOCT): New macro.
576 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
577
930bb4cf
AM		 5782008-01-29 Alan Modra <amodra@bigpond.net.au>
579
580 * ppc-opc.c: Support optional L form mtmsr.
581
82c18208
L		 5822008-01-24 H.J. Lu <hongjiu.lu@intel.com>
583
584 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
585
599121aa
L		 5862008-01-23 H.J. Lu <hongjiu.lu@intel.com>
587
588 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
589 * i386-init.h: Regenerated.
590
80098f51
TG		 5912008-01-23 Tristan Gingold <gingold@adacore.com>
592
593 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
594 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
595
115c7c25
L		 5962008-01-22 H.J. Lu <hongjiu.lu@intel.com>
597
598 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
599 (cpu_flags): Likewise.
600
601 * i386-opc.h (CpuMMX2): Removed.
602 (CpuSSE): Updated.
603
604 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
605 * i386-init.h: Regenerated.
606 * i386-tbl.h: Likewise.
607
6305a203
L		 6082008-01-22 H.J. Lu <hongjiu.lu@intel.com>
609
610 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
611 CPU_SMX_FLAGS.
612 * i386-init.h: Regenerated.
613
fd07a1c8
L		 6142008-01-15 H.J. Lu <hongjiu.lu@intel.com>
615
616 * i386-opc.tbl: Use Qword on movddup.
617 * i386-tbl.h: Regenerated.
618
321fd21e
L		 6192008-01-15 H.J. Lu <hongjiu.lu@intel.com>
620
621 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
622 * i386-tbl.h: Regenerated.
623
4ee52178
L		 6242008-01-15 H.J. Lu <hongjiu.lu@intel.com>
625
626 * i386-dis.c (Mx): New.
627 (PREFIX_0FC3): Likewise.
628 (PREFIX_0FC7_REG_6): Updated.
629 (dis386_twobyte): Use PREFIX_0FC3.
630 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
631 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
632 movntss.
633
5c07affc
L		 6342008-01-14 H.J. Lu <hongjiu.lu@intel.com>
635
636 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
637 (operand_types): Add Mem.
638
639 * i386-opc.h (IntelSyntax): New.
640 * i386-opc.h (Mem): New.
641 (Byte): Updated.
642 (Opcode_Modifier_Max): Updated.
643 (i386_opcode_modifier): Add intelsyntax.
644 (i386_operand_type): Add mem.
645
646 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
647 instructions.
648
649 * i386-reg.tbl: Add size for accumulator.
650
651 * i386-init.h: Regenerated.
652 * i386-tbl.h: Likewise.
653
0d6a2f58
L		 6542008-01-13 H.J. Lu <hongjiu.lu@intel.com>
655
656 * i386-opc.h (Byte): Fix a typo.
657
7d5e4556
L		 6582008-01-12 H.J. Lu <hongjiu.lu@intel.com>
659
660 PR gas/5534
661 * i386-gen.c (operand_type_init): Add Dword to
662 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
663 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
664 Qword and Xmmword.
665 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
666 Xmmword, Unspecified and Anysize.
667 (set_bitfield): Make Mmword an alias of Qword. Make Oword
668 an alias of Xmmword.
669
670 * i386-opc.h (CheckSize): Removed.
671 (Byte): Updated.
672 (Word): Likewise.
673 (Dword): Likewise.
674 (Qword): Likewise.
675 (Xmmword): Likewise.
676 (FWait): Updated.
677 (OTMax): Likewise.
678 (i386_opcode_modifier): Remove checksize, byte, word, dword,
679 qword and xmmword.
680 (Fword): New.
681 (TBYTE): Likewise.
682 (Unspecified): Likewise.
683 (Anysize): Likewise.
684 (i386_operand_type): Add byte, word, dword, fword, qword,
685 tbyte xmmword, unspecified and anysize.
686
687 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
688 Tbyte, Xmmword, Unspecified and Anysize.
689
690 * i386-reg.tbl: Add size for accumulator.
691
692 * i386-init.h: Regenerated.
693 * i386-tbl.h: Likewise.
694
b5b1fc4f
L		 6952008-01-10 H.J. Lu <hongjiu.lu@intel.com>
696
697 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
698 (REG_0F18): Updated.
699 (reg_table): Updated.
700 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
701 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
702
50e8458f
L		 7032008-01-08 H.J. Lu <hongjiu.lu@intel.com>
704
705 * i386-gen.c (set_bitfield): Use fail () on error.
706
3d4d5afa
L		 7072008-01-08 H.J. Lu <hongjiu.lu@intel.com>
708
709 * i386-gen.c (lineno): New.
710 (filename): Likewise.
711 (set_bitfield): Report filename and line numer on error.
712 (process_i386_opcodes): Set filename and update lineno.
713 (process_i386_registers): Likewise.
714
e1d4d893
L		 7152008-01-05 H.J. Lu <hongjiu.lu@intel.com>
716
717 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
718 ATTSyntax.
719
720 * i386-opc.h (IntelMnemonic): Renamed to ..
721 (ATTSyntax): This
722 (Opcode_Modifier_Max): Updated.
723 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
724 and intelsyntax.
725
8944f3c2 726 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 727 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
728 * i386-tbl.h: Regenerated.
729
6f143e4d
L		 7302008-01-04 H.J. Lu <hongjiu.lu@intel.com>
731
732 * i386-gen.c: Update copyright to 2008.
733 * i386-opc.h: Likewise.
734 * i386-opc.tbl: Likewise.
735
736 * i386-init.h: Regenerated.
737 * i386-tbl.h: Likewise.
738
c6add537
L		 7392008-01-04 H.J. Lu <hongjiu.lu@intel.com>
740
741 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
742 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
743 * i386-tbl.h: Regenerated.
744
3629bb00
L		 7452008-01-03 H.J. Lu <hongjiu.lu@intel.com>
746
747 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
748 CpuSSE4_2_Or_ABM.
749 (cpu_flags): Likewise.
750
751 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
752 (CpuSSE4_2_Or_ABM): Likewise.
753 (CpuLM): Updated.
754 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
755
756 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
757 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
758 and CpuPadLock, respectively.
759 * i386-init.h: Regenerated.
760 * i386-tbl.h: Likewise.
761
24995bd6
L		 7622008-01-03 H.J. Lu <hongjiu.lu@intel.com>
763
764 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
765
766 * i386-opc.h (No_xSuf): Removed.
767 (CheckSize): Updated.
768
769 * i386-tbl.h: Regenerated.
770
e0329a22
L		 7712008-01-02 H.J. Lu <hongjiu.lu@intel.com>
772
773 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
774 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
775 CPU_SSE5_FLAGS.
776 (cpu_flags): Add CpuSSE4_2_Or_ABM.
777
778 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
779 (CpuLM): Updated.
780 (i386_cpu_flags): Add cpusse4_2_or_abm.
781
782 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
783 CpuABM|CpuSSE4_2 on popcnt.
784 * i386-init.h: Regenerated.
785 * i386-tbl.h: Likewise.
786
f2a9c676
L		 7872008-01-02 H.J. Lu <hongjiu.lu@intel.com>
788
789 * i386-opc.h: Update comments.
790
d978b5be
L		 7912008-01-02 H.J. Lu <hongjiu.lu@intel.com>
792
793 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
794 * i386-opc.h: Likewise.
795 * i386-opc.tbl: Likewise.
796
582d5edd
L		 7972008-01-02 H.J. Lu <hongjiu.lu@intel.com>
798
799 PR gas/5534
800 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
801 Byte, Word, Dword, QWord and Xmmword.
802
803 * i386-opc.h (No_xSuf): New.
804 (CheckSize): Likewise.
805 (Byte): Likewise.
806 (Word): Likewise.
807 (Dword): Likewise.
808 (QWord): Likewise.
809 (Xmmword): Likewise.
810 (FWait): Updated.
811 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
812 Dword, QWord and Xmmword.
813
814 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
815 used.
816 * i386-tbl.h: Regenerated.
817
3fe15143
MK		 8182008-01-02 Mark Kettenis <kettenis@gnu.org>
819
820 * m88k-dis.c (instructions): Fix fcvt.* instructions.
821 From Miod Vallat.
822
6c7ac64e 823For older changes see ChangeLog-2007
252b5132
RH		 824\f
825Local Variables:
2f6d2f85
NC		 826mode: change-log
827left-margin: 8
828fill-column: 74
252b5132
RH		 829version-control: never
830End:
GDB Binutils - Deliverables
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