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opcodes: handle mach-o for thumb/arm disambiguation.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
e49d43ff
TG		 12015-11-23 Tristan Gingold <gingold@adacore.com>
2
3 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
4
250aafa4
MW		 52015-11-20 Matthew Wahab <matthew.wahab@arm.com>
6
7 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
8 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
9 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
10 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
11 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
12 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
13 cnthv_ctl_el2, cnthv_cval_el2.
14 (aarch64_sys_reg_supported_p): Update for the new system
15 registers.
16
a915c10f
NC		 172015-11-20 Nick Clifton <nickc@redhat.com>
18
19 PR binutils/19224
20 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
21
f8c2a965
NC		 222015-11-20 Nick Clifton <nickc@redhat.com>
23
24 * po/zh_CN.po: Updated simplified Chinese translation.
25
c2825638
MW		 262015-11-19 Matthew Wahab <matthew.wahab@arm.com>
27
28 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
29 of MSR PAN immediate operand.
30
e7286c56
NC		 312015-11-16 Nick Clifton <nickc@redhat.com>
32
33 * rx-dis.c (condition_names): Replace always and never with
34 invalid, since the always/never conditions can never be legal.
35
d8bd95ef
TG		 362015-11-13 Tristan Gingold <gingold@adacore.com>
37
38 * configure: Regenerate.
39
a680de9a
PB		 402015-11-11 Alan Modra <amodra@gmail.com>
41 Peter Bergner <bergner@vnet.ibm.com>
42
43 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
44 Add PPC_OPCODE_VSX3 to the vsx entry.
45 (powerpc_init_dialect): Set default dialect to power9.
46 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
47 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
48 extract_l1 insert_xtq6, extract_xtq6): New static functions.
49 (insert_esync): Test for illegal L operand value.
50 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
51 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
52 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
53 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
54 PPCVSX3): New defines.
55 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
56 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
57 <mcrxr>: Use XBFRARB_MASK.
58 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
59 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
60 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
61 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
62 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
63 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
64 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
65 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
66 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
67 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
68 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
69 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
70 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
71 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
72 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
73 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
74 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
75 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
76 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
77 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
78 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
79 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
80 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
81 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
82 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
83 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
84 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
85 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
86 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
87 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
88 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
89 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
90
854eb72b
NC		 912015-11-02 Nick Clifton <nickc@redhat.com>
92
93 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
94 instructions.
95 * rx-decode.c: Regenerate.
96
e292aa7a
NC		 972015-11-02 Nick Clifton <nickc@redhat.com>
98
99 * rx-decode.opc (rx_disp): If the displacement is zero, set the
100 type to RX_Operand_Zero_Indirect.
101 * rx-decode.c: Regenerate.
102 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
103
43cdf5ae
YQ		 1042015-10-28 Yao Qi <yao.qi@linaro.org>
105
106 * aarch64-dis.c (aarch64_decode_insn): Add one argument
107 noaliases_p. Update comments. Pass noaliases_p rather than
108 no_aliases to aarch64_opcode_decode.
109 (print_insn_aarch64_word): Pass no_aliases to
110 aarch64_decode_insn.
111
c2f28758
VK		 1122015-10-27 Vinay <Vinay.G@kpit.com>
113
114 PR binutils/19159
115 * rl78-decode.opc (MOV): Added offset to DE register in index
116 addressing mode.
117 * rl78-decode.c: Regenerate.
118
46662804
VK		 1192015-10-27 Vinay Kumar <vinay.g@kpit.com>
120
121 PR binutils/19158
122 * rl78-decode.opc: Add 's' print operator to instructions that
123 access system registers.
124 * rl78-decode.c: Regenerate.
125 * rl78-dis.c (print_insn_rl78_common): Decode all system
126 registers.
127
02f12cd4
VK		 1282015-10-27 Vinay Kumar <vinay.g@kpit.com>
129
130 PR binutils/19157
131 * rl78-decode.opc: Add 'a' print operator to mov instructions
132 using stack pointer plus index addressing.
133 * rl78-decode.c: Regenerate.
134
485f23cf
AK		 1352015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
136
137 * s390-opc.c: Fix comment.
138 * s390-opc.txt: Change instruction type for troo, trot, trto, and
139 trtt to RRF_U0RER since the second parameter does not need to be a
140 register pair.
141
3f94e60d
NC		 1422015-10-08 Nick Clifton <nickc@redhat.com>
143
144 * arc-dis.c (print_insn_arc): Initiallise insn array.
145
875880c6
YQ		 1462015-10-07 Yao Qi <yao.qi@linaro.org>
147
148 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
149 'name' rather than 'template'.
150 * aarch64-opc.c (aarch64_print_operand): Likewise.
151
886a2506
NC		 1522015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
153
154 * arc-dis.c: Revamped file for ARC support
155 * arc-dis.h: Likewise.
156 * arc-ext.c: Likewise.
157 * arc-ext.h: Likewise.
158 * arc-opc.c: Likewise.
159 * arc-fxi.h: New file.
160 * arc-regs.h: Likewise.
161 * arc-tbl.h: Likewise.
162
36f4aab1
YQ		 1632015-10-02 Yao Qi <yao.qi@linaro.org>
164
165 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
166 argument insn type to aarch64_insn. Rename to ...
167 (aarch64_decode_insn): ... it.
168 (print_insn_aarch64_word): Caller updated.
169
7232d389
YQ		 1702015-10-02 Yao Qi <yao.qi@linaro.org>
171
172 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
173 (print_insn_aarch64_word): Caller updated.
174
7ecc513a
DV		 1752015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
176
177 * s390-mkopc.c (main): Parse htm and vx flag.
178 * s390-opc.txt: Mark instructions from the hardware transactional
179 memory and vector facilities with the "htm"/"vx" flag.
180
b08b78e7
NC		 1812015-09-28 Nick Clifton <nickc@redhat.com>
182
183 * po/de.po: Updated German translation.
184
36f7a941
TR		 1852015-09-28 Tom Rix <tom@bumblecow.com>
186
187 * ppc-opc.c (PPC500): Mark some opcodes as invalid
188
b6518b38
NC		 1892015-09-23 Nick Clifton <nickc@redhat.com>
190
191 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
192 function.
193 * tic30-dis.c (print_branch): Likewise.
194 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
195 value before left shifting.
196 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
197 * hppa-dis.c (print_insn_hppa): Likewise.
198 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
199 array.
200 * msp430-dis.c (msp430_singleoperand): Likewise.
201 (msp430_doubleoperand): Likewise.
202 (print_insn_msp430): Likewise.
203 * nds32-asm.c (parse_operand): Likewise.
204 * sh-opc.h (MASK): Likewise.
205 * v850-dis.c (get_operand_value): Likewise.
206
f04265ec
NC		 2072015-09-22 Nick Clifton <nickc@redhat.com>
208
209 * rx-decode.opc (bwl): Use RX_Bad_Size.
210 (sbwl): Likewise.
211 (ubwl): Likewise. Rename to ubw.
212 (uBWL): Rename to uBW.
213 Replace all references to uBWL with uBW.
214 * rx-decode.c: Regenerate.
215 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
216 (opsize_names): Likewise.
217 (print_insn_rx): Detect and report RX_Bad_Size.
218
6dca4fd1
AB		 2192015-09-22 Anton Blanchard <anton@samba.org>
220
221 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
222
38074311
JM		 2232015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
224
225 * sparc-dis.c (print_insn_sparc): Handle the privileged register
226 %pmcdper.
227
5f40e14d
JS		 2282015-08-24 Jan Stancek <jstancek@redhat.com>
229
230 * i386-dis.c (print_insn): Fix decoding of three byte operands.
231
ab4e4ed5
AF		 2322015-08-21 Alexander Fomin <alexander.fomin@intel.com>
233
234 PR binutils/18257
235 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
236 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
237 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
238 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
239 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
240 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
241 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
242 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
243 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
244 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
245 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
246 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
247 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
248 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
249 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
250 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
251 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
252 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
253 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
254 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
255 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
256 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
257 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
258 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
259 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
260 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
261 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
262 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
263 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
264 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
265 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
266 (vex_w_table): Replace terminals with MOD_TABLE entries for
267 most of mask instructions.
268
919b75f7
AM		 2692015-08-17 Alan Modra <amodra@gmail.com>
270
271 * cgen.sh: Trim trailing space from cgen output.
272 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
273 (print_dis_table): Likewise.
274 * opc2c.c (dump_lines): Likewise.
275 (orig_filename): Warning fix.
276 * ia64-asmtab.c: Regenerate.
277
4ab90a7a
AV		 2782015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
279
280 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
281 and higher with ARM instruction set will now mark the 26-bit
282 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
283 (arm_opcodes): Fix for unpredictable nop being recognized as a
284 teq.
285
40fc1451
SD		 2862015-08-12 Simon Dardis <simon.dardis@imgtec.com>
287
288 * micromips-opc.c (micromips_opcodes): Re-order table so that move
289 based on 'or' is first.
290 * mips-opc.c (mips_builtin_opcodes): Ditto.
291
922c5db5
NC		 2922015-08-11 Nick Clifton <nickc@redhat.com>
293
294 PR 18800
295 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
296 instruction.
297
75fb7498
RS		 2982015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
299
300 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
301
36aed29d
AP		 3022015-08-07 Amit Pawar <Amit.Pawar@amd.com>
303
304 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
305 * i386-init.h: Regenerated.
306
a8484f96
L		 3072015-07-30 H.J. Lu <hongjiu.lu@intel.com>
308
309 PR binutils/13571
310 * i386-dis.c (MOD_0FC3): New.
311 (PREFIX_0FC3): Renamed to ...
312 (PREFIX_MOD_0_0FC3): This.
313 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
314 (prefix_table): Replace Ma with Ev on movntiS.
315 (mod_table): Add MOD_0FC3.
316
37a42ee9
L		 3172015-07-27 H.J. Lu <hongjiu.lu@intel.com>
318
319 * configure: Regenerated.
320
070fe95d
AM		 3212015-07-23 Alan Modra <amodra@gmail.com>
322
323 PR 18708
324 * i386-dis.c (get64): Avoid signed integer overflow.
325
20c2a615
L		 3262015-07-22 Alexander Fomin <alexander.fomin@intel.com>
327
328 PR binutils/18631
329 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
330 "EXEvexHalfBcstXmmq" for the second operand.
331 (EVEX_W_0F79_P_2): Likewise.
332 (EVEX_W_0F7A_P_2): Likewise.
333 (EVEX_W_0F7B_P_2): Likewise.
334
6f1c2142
AM		 3352015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
336
337 * arm-dis.c (print_insn_coprocessor): Added support for quarter
338 float bitfield format.
339 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
340 quarter float bitfield format.
341
8a643cc3
L		 3422015-07-14 H.J. Lu <hongjiu.lu@intel.com>
343
344 * configure: Regenerated.
345
ef5a96d5
AM		 3462015-07-03 Alan Modra <amodra@gmail.com>
347
348 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
349 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
350 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
351
c8c8175b
SL		 3522015-07-01 Sandra Loosemore <sandra@codesourcery.com>
353 Cesar Philippidis <cesar@codesourcery.com>
354
355 * nios2-dis.c (nios2_extract_opcode): New.
356 (nios2_disassembler_state): New.
357 (nios2_find_opcode_hash): Use mach parameter to select correct
358 disassembler state.
359 (nios2_print_insn_arg): Extend to support new R2 argument letters
360 and formats.
361 (print_insn_nios2): Check for 16-bit instruction at end of memory.
362 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
363 (NIOS2_NUM_OPCODES): Rename to...
364 (NIOS2_NUM_R1_OPCODES): This.
365 (nios2_r2_opcodes): New.
366 (NIOS2_NUM_R2_OPCODES): New.
367 (nios2_num_r2_opcodes): New.
368 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
369 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
370 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
371 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
372 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
373
9916071f
AP		 3742015-06-30 Amit Pawar <Amit.Pawar@amd.com>
375
376 * i386-dis.c (OP_Mwaitx): New.
377 (rm_table): Add monitorx/mwaitx.
378 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
379 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
380 (operand_type_init): Add CpuMWAITX.
381 * i386-opc.h (CpuMWAITX): New.
382 (i386_cpu_flags): Add cpumwaitx.
383 * i386-opc.tbl: Add monitorx and mwaitx.
384 * i386-init.h: Regenerated.
385 * i386-tbl.h: Likewise.
386
7b934113
PB		 3872015-06-22 Peter Bergner <bergner@vnet.ibm.com>
388
389 * ppc-opc.c (insert_ls): Test for invalid LS operands.
390 (insert_esync): New function.
391 (LS, WC): Use insert_ls.
392 (ESYNC): Use insert_esync.
393
bdc4de1b
NC		 3942015-06-22 Nick Clifton <nickc@redhat.com>
395
396 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
397 requested region lies beyond it.
398 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
399 looking for 32-bit insns.
400 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
401 data.
402 * sh-dis.c (print_insn_sh): Likewise.
403 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
404 blocks of instructions.
405 * vax-dis.c (print_insn_vax): Check that the requested address
406 does not clash with the stop_vma.
407
11a0cf2e
PB		 4082015-06-19 Peter Bergner <bergner@vnet.ibm.com>
409
070fe95d 410 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 411 * ppc-opc.c (FXM4): Add non-zero optional value.
412 (TBR): Likewise.
413 (SXL): Likewise.
414 (insert_fxm): Handle new default operand value.
415 (extract_fxm): Likewise.
416 (insert_tbr): Likewise.
417 (extract_tbr): Likewise.
418
bdfa8b95
MW		 4192015-06-16 Matthew Wahab <matthew.wahab@arm.com>
420
421 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
422
24b4cf66
SN		 4232015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
424
425 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
426
99a2c561
PB		 4272015-06-12 Peter Bergner <bergner@vnet.ibm.com>
428
429 * ppc-opc.c: Add comment accidentally removed by old commit.
430 (MTMSRD_L): Delete.
431
40f77f82
AM		 4322015-06-04 Peter Bergner <bergner@vnet.ibm.com>
433
434 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
435
13be46a2
NC		 4362015-06-04 Nick Clifton <nickc@redhat.com>
437
438 PR 18474
439 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
440
ddfded2f
MW		 4412015-06-02 Matthew Wahab <matthew.wahab@arm.com>
442
443 * arm-dis.c (arm_opcodes): Add "setpan".
444 (thumb_opcodes): Add "setpan".
445
1af1dd51
MW		 4462015-06-02 Matthew Wahab <matthew.wahab@arm.com>
447
448 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
449 macros.
450
9e1f0fa7
MW		 4512015-06-02 Matthew Wahab <matthew.wahab@arm.com>
452
453 * aarch64-tbl.h (aarch64_feature_rdma): New.
454 (RDMA): New.
455 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
456 * aarch64-asm-2.c: Regenerate.
457 * aarch64-dis-2.c: Regenerate.
458 * aarch64-opc-2.c: Regenerate.
459
290806fd
MW		 4602015-06-02 Matthew Wahab <matthew.wahab@arm.com>
461
462 * aarch64-tbl.h (aarch64_feature_lor): New.
463 (LOR): New.
464 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
465 "stllrb", "stllrh".
466 * aarch64-asm-2.c: Regenerate.
467 * aarch64-dis-2.c: Regenerate.
468 * aarch64-opc-2.c: Regenerate.
469
f21cce2c
MW		 4702015-06-01 Matthew Wahab <matthew.wahab@arm.com>
471
472 * aarch64-opc.c (F_ARCHEXT): New.
473 (aarch64_sys_regs): Add "pan".
474 (aarch64_sys_reg_supported_p): New.
475 (aarch64_pstatefields): Add "pan".
476 (aarch64_pstatefield_supported_p): New.
477
d194d186
JB		 4782015-06-01 Jan Beulich <jbeulich@suse.com>
479
480 * i386-tbl.h: Regenerate.
481
3a8547d2
JB		 4822015-06-01 Jan Beulich <jbeulich@suse.com>
483
484 * i386-dis.c (print_insn): Swap rounding mode specifier and
485 general purpose register in Intel mode.
486
015c54d5
JB		 4872015-06-01 Jan Beulich <jbeulich@suse.com>
488
489 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
490 * i386-tbl.h: Regenerate.
491
071f0063
L		 4922015-05-18 H.J. Lu <hongjiu.lu@intel.com>
493
494 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
495 * i386-init.h: Regenerated.
496
5db04b09
L		 4972015-05-15 H.J. Lu <hongjiu.lu@intel.com>
498
499 PR binutis/18386
500 * i386-dis.c: Add comments for '@'.
501 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
502 (enum x86_64_isa): New.
503 (isa64): Likewise.
504 (print_i386_disassembler_options): Add amd64 and intel64.
505 (print_insn): Handle amd64 and intel64.
506 (putop): Handle '@'.
507 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
508 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
509 * i386-opc.h (AMD64): New.
510 (CpuIntel64): Likewise.
511 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
512 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
513 Mark direct call/jmp without Disp16|Disp32 as Intel64.
514 * i386-init.h: Regenerated.
515 * i386-tbl.h: Likewise.
516
4bc0608a
PB		 5172015-05-14 Peter Bergner <bergner@vnet.ibm.com>
518
519 * ppc-opc.c (IH) New define.
520 (powerpc_opcodes) <wait>: Do not enable for POWER7.
521 <tlbie>: Add RS operand for POWER7.
522 <slbia>: Add IH operand for POWER6.
523
70cead07
L		 5242015-05-11 H.J. Lu <hongjiu.lu@intel.com>
525
526 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
527 direct branch.
528 (jmp): Likewise.
529 * i386-tbl.h: Regenerated.
530
7b6d09fb
L		 5312015-05-11 H.J. Lu <hongjiu.lu@intel.com>
532
533 * configure.ac: Support bfd_iamcu_arch.
534 * disassemble.c (disassembler): Support bfd_iamcu_arch.
535 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
536 CPU_IAMCU_COMPAT_FLAGS.
537 (cpu_flags): Add CpuIAMCU.
538 * i386-opc.h (CpuIAMCU): New.
539 (i386_cpu_flags): Add cpuiamcu.
540 * configure: Regenerated.
541 * i386-init.h: Likewise.
542 * i386-tbl.h: Likewise.
543
31955f99
L		 5442015-05-08 H.J. Lu <hongjiu.lu@intel.com>
545
546 PR binutis/18386
547 * i386-dis.c (X86_64_E8): New.
548 (X86_64_E9): Likewise.
549 Update comments on 'T', 'U', 'V'. Add comments for '^'.
550 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
551 (x86_64_table): Add X86_64_E8 and X86_64_E9.
552 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
553 (putop): Handle '^'.
554 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
555 REX_W.
556
0952813b
DD		 5572015-04-30 DJ Delorie <dj@redhat.com>
558
559 * disassemble.c (disassembler): Choose suitable disassembler based
560 on E_ABI.
561 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
562 it to decode mul/div insns.
563 * rl78-decode.c: Regenerate.
564 * rl78-dis.c (print_insn_rl78): Rename to...
565 (print_insn_rl78_common): ...this, take ISA parameter.
566 (print_insn_rl78): New.
567 (print_insn_rl78_g10): New.
568 (print_insn_rl78_g13): New.
569 (print_insn_rl78_g14): New.
570 (rl78_get_disassembler): New.
571
f9d3ecaa
NC		 5722015-04-29 Nick Clifton <nickc@redhat.com>
573
574 * po/fr.po: Updated French translation.
575
4fff86c5
PB		 5762015-04-27 Peter Bergner <bergner@vnet.ibm.com>
577
578 * ppc-opc.c (DCBT_EO): New define.
579 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
580 <lharx>: Likewise.
581 <stbcx.>: Likewise.
582 <sthcx.>: Likewise.
583 <waitrsv>: Do not enable for POWER7 and later.
584 <waitimpl>: Likewise.
585 <dcbt>: Default to the two operand form of the instruction for all
586 "old" cpus. For "new" cpus, use the operand ordering that matches
587 whether the cpu is server or embedded.
588 <dcbtst>: Likewise.
589
3b78cfe1
AK		 5902015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
591
592 * s390-opc.c: New instruction type VV0UU2.
593 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
594 and WFC.
595
04d824a4
JB		 5962015-04-23 Jan Beulich <jbeulich@suse.com>
597
598 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
599 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
600 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
601 (vfpclasspd, vfpclassps): Add %XZ.
602
09708981
L		 6032015-04-15 H.J. Lu <hongjiu.lu@intel.com>
604
605 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
606 (PREFIX_UD_REPZ): Likewise.
607 (PREFIX_UD_REPNZ): Likewise.
608 (PREFIX_UD_DATA): Likewise.
609 (PREFIX_UD_ADDR): Likewise.
610 (PREFIX_UD_LOCK): Likewise.
611
3888916d
L		 6122015-04-15 H.J. Lu <hongjiu.lu@intel.com>
613
614 * i386-dis.c (prefix_requirement): Removed.
615 (print_insn): Don't set prefix_requirement. Check
616 dp->prefix_requirement instead of prefix_requirement.
617
f24bcbaa
L		 6182015-04-15 H.J. Lu <hongjiu.lu@intel.com>
619
620 PR binutils/17898
621 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
622 (PREFIX_MOD_0_0FC7_REG_6): This.
623 (PREFIX_MOD_3_0FC7_REG_6): New.
624 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
625 (prefix_table): Replace PREFIX_0FC7_REG_6 with
626 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
627 PREFIX_MOD_3_0FC7_REG_7.
628 (mod_table): Replace PREFIX_0FC7_REG_6 with
629 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
630 PREFIX_MOD_3_0FC7_REG_7.
631
507bd325
L		 6322015-04-15 H.J. Lu <hongjiu.lu@intel.com>
633
634 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
635 (PREFIX_MANDATORY_REPNZ): Likewise.
636 (PREFIX_MANDATORY_DATA): Likewise.
637 (PREFIX_MANDATORY_ADDR): Likewise.
638 (PREFIX_MANDATORY_LOCK): Likewise.
639 (PREFIX_MANDATORY): Likewise.
640 (PREFIX_UD_SHIFT): Set to 8
641 (PREFIX_UD_REPZ): Updated.
642 (PREFIX_UD_REPNZ): Likewise.
643 (PREFIX_UD_DATA): Likewise.
644 (PREFIX_UD_ADDR): Likewise.
645 (PREFIX_UD_LOCK): Likewise.
646 (PREFIX_IGNORED_SHIFT): New.
647 (PREFIX_IGNORED_REPZ): Likewise.
648 (PREFIX_IGNORED_REPNZ): Likewise.
649 (PREFIX_IGNORED_DATA): Likewise.
650 (PREFIX_IGNORED_ADDR): Likewise.
651 (PREFIX_IGNORED_LOCK): Likewise.
652 (PREFIX_OPCODE): Likewise.
653 (PREFIX_IGNORED): Likewise.
654 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
655 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
656 (three_byte_table): Likewise.
657 (mod_table): Likewise.
658 (mandatory_prefix): Renamed to ...
659 (prefix_requirement): This.
660 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
661 Update PREFIX_90 entry.
662 (get_valid_dis386): Check prefix_requirement to see if a prefix
663 should be ignored.
664 (print_insn): Replace mandatory_prefix with prefix_requirement.
665
f0fba320
RL		 6662015-04-15 Renlin Li <renlin.li@arm.com>
667
668 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
669 use it for ssat and ssat16.
670 (print_insn_thumb32): Add handle case for 'D' control code.
671
bf890a93
IT		 6722015-04-06 Ilya Tocar <ilya.tocar@intel.com>
673 H.J. Lu <hongjiu.lu@intel.com>
674
675 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
676 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
677 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
678 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
679 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
680 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
681 Fill prefix_requirement field.
682 (struct dis386): Add prefix_requirement field.
683 (dis386): Fill prefix_requirement field.
684 (dis386_twobyte): Ditto.
685 (twobyte_has_mandatory_prefix_: Remove.
686 (reg_table): Fill prefix_requirement field.
687 (prefix_table): Ditto.
688 (x86_64_table): Ditto.
689 (three_byte_table): Ditto.
690 (xop_table): Ditto.
691 (vex_table): Ditto.
692 (vex_len_table): Ditto.
693 (vex_w_table): Ditto.
694 (mod_table): Ditto.
695 (bad_opcode): Ditto.
696 (print_insn): Use prefix_requirement.
697 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
698 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
699 (float_reg): Ditto.
700
2f783c1f
MF		 7012015-03-30 Mike Frysinger <vapier@gentoo.org>
702
703 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
704
b9d94d62
L		 7052015-03-29 H.J. Lu <hongjiu.lu@intel.com>
706
707 * Makefile.in: Regenerated.
708
27c49e9a
AB		 7092015-03-25 Anton Blanchard <anton@samba.org>
710
711 * ppc-dis.c (disassemble_init_powerpc): Only initialise
712 powerpc_opcd_indices and vle_opcd_indices once.
713
c4e676f1
AB		 7142015-03-25 Anton Blanchard <anton@samba.org>
715
716 * ppc-opc.c (powerpc_opcodes): Add slbfee.
717
823d2571
TG		 7182015-03-24 Terry Guo <terry.guo@arm.com>
719
720 * arm-dis.c (opcode32): Updated to use new arm feature struct.
721 (opcode16): Likewise.
722 (coprocessor_opcodes): Replace bit with feature struct.
723 (neon_opcodes): Likewise.
724 (arm_opcodes): Likewise.
725 (thumb_opcodes): Likewise.
726 (thumb32_opcodes): Likewise.
727 (print_insn_coprocessor): Likewise.
728 (print_insn_arm): Likewise.
729 (select_arm_features): Follow new feature struct.
730
029f3522
GG		 7312015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
732
733 * i386-dis.c (rm_table): Add clzero.
734 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
735 Add CPU_CLZERO_FLAGS.
736 (cpu_flags): Add CpuCLZERO.
737 * i386-opc.h: Add CpuCLZERO.
738 * i386-opc.tbl: Add clzero.
739 * i386-init.h: Re-generated.
740 * i386-tbl.h: Re-generated.
741
6914869a
AB		 7422015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
743
744 * mips-opc.c (decode_mips_operand): Fix constraint issues
745 with u and y operands.
746
21e20815
AB		 7472015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
748
749 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
750
6b1d7593
AK		 7512015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
752
753 * s390-opc.c: Add new IBM z13 instructions.
754 * s390-opc.txt: Likewise.
755
c8f89a34
JW		 7562015-03-10 Renlin Li <renlin.li@arm.com>
757
758 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
759 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
760 related alias.
761 * aarch64-asm-2.c: Regenerate.
762 * aarch64-dis-2.c: Likewise.
763 * aarch64-opc-2.c: Likewise.
764
d8282f0e
JW		 7652015-03-03 Jiong Wang <jiong.wang@arm.com>
766
767 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
768
ac994365
OE		 7692015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
770
771 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
772 arch_sh_up.
773 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
774 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
775
fd63f640
V		 7762015-02-23 Vinay <Vinay.G@kpit.com>
777
778 * rl78-decode.opc (MOV): Added space between two operands for
779 'mov' instruction in index addressing mode.
780 * rl78-decode.c: Regenerate.
781
f63c1776
PA		 7822015-02-19 Pedro Alves <palves@redhat.com>
783
784 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
785
07774fcc
PA		 7862015-02-10 Pedro Alves <palves@redhat.com>
787 Tom Tromey <tromey@redhat.com>
788
789 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
790 microblaze_and, microblaze_xor.
791 * microblaze-opc.h (opcodes): Adjust.
792
3f8107ab
AM		 7932015-01-28 James Bowman <james.bowman@ftdichip.com>
794
795 * Makefile.am: Add FT32 files.
796 * configure.ac: Handle FT32.
797 * disassemble.c (disassembler): Call print_insn_ft32.
798 * ft32-dis.c: New file.
799 * ft32-opc.c: New file.
800 * Makefile.in: Regenerate.
801 * configure: Regenerate.
802 * po/POTFILES.in: Regenerate.
803
e5fe4957
KLC		 8042015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
805
806 * nds32-asm.c (keyword_sr): Add new system registers.
807
1e2e8c52
AK		 8082015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
809
810 * s390-dis.c (s390_extract_operand): Support vector register
811 operands.
812 (s390_print_insn_with_opcode): Support new operands types and add
813 new handling of optional operands.
814 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
815 and include opcode/s390.h instead.
816 (struct op_struct): New field `flags'.
817 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
818 (dumpTable): Dump flags.
819 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
820 string.
821 * s390-opc.c: Add new operands types, instruction formats, and
822 instruction masks.
823 (s390_opformats): Add new formats for .insn.
824 * s390-opc.txt: Add new instructions.
825
b90efa5b 8262015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 827
b90efa5b 828 Update year range in copyright notice of all files.
bffb6004 829
b90efa5b 830For older changes see ChangeLog-2014
252b5132 831\f
b90efa5b 832Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 833
834Copying and distribution of this file, with or without modification,
835are permitted in any medium without royalty provided the copyright
836notice and this notice are preserved.
837
252b5132 838Local Variables:
2f6d2f85
NC		 839mode: change-log
840left-margin: 8
841fill-column: 74
252b5132
RH		 842version-control: never
843End:
GDB Binutils - Deliverables
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