Commit | Line | Data |
---|---|---|
ab20fa4a YQ |
1 | 2017-05-24 Yao Qi <yao.qi@linaro.org> |
2 | ||
3 | * rl78-dis.c (rl78_get_disassembler): If parameter abfd | |
4 | is NULL, set cpu to E_FLAG_RL78_ANY_CPU. | |
5 | ||
003ca0fd YQ |
6 | 2017-05-24 Yao Qi <yao.qi@linaro.org> |
7 | ||
8 | * disassemble.c (disassembler): Add arguments a, big and mach. | |
9 | Use them. | |
10 | ||
04ef582a L |
11 | 2017-05-22 H.J. Lu <hongjiu.lu@intel.com> |
12 | ||
13 | * i386-dis.c (NOTRACK_Fixup): New. | |
14 | (NOTRACK): Likewise. | |
15 | (NOTRACK_PREFIX): Likewise. | |
16 | (last_active_prefix): Likewise. | |
17 | (reg_table): Use NOTRACK on indirect call and jmp. | |
18 | (ckprefix): Set last_active_prefix. | |
19 | (prefix_name): Return "notrack" for NOTRACK_PREFIX. | |
20 | * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk. | |
21 | * i386-opc.h (NoTrackPrefixOk): New. | |
22 | (i386_opcode_modifier): Add notrackprefixok. | |
23 | * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp. | |
24 | Add notrack. | |
25 | * i386-tbl.h: Regenerated. | |
26 | ||
64517994 JM |
27 | 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> |
28 | ||
29 | * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8. | |
30 | (X_IMM2): Define. | |
31 | (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and | |
32 | bfd_mach_sparc_v9m8. | |
33 | (print_insn_sparc): Handle new operand types. | |
34 | * sparc-opc.c (MASK_M8): Define. | |
35 | (v6): Add MASK_M8. | |
36 | (v6notlet): Likewise. | |
37 | (v7): Likewise. | |
38 | (v8): Likewise. | |
39 | (v9): Likewise. | |
40 | (v9a): Likewise. | |
41 | (v9b): Likewise. | |
42 | (v9c): Likewise. | |
43 | (v9d): Likewise. | |
44 | (v9e): Likewise. | |
45 | (v9v): Likewise. | |
46 | (v9m): Likewise. | |
47 | (v9andleon): Likewise. | |
48 | (m8): Define. | |
49 | (HWS_VM8): Define. | |
50 | (HWS2_VM8): Likewise. | |
51 | (sparc_opcode_archs): Add entry for "m8". | |
52 | (sparc_opcodes): Add OSA2017 and M8 instructions | |
53 | dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl, | |
54 | fpx{ll,ra,rl}64x, | |
55 | ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d}, | |
56 | ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb, | |
57 | revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x}, | |
58 | stm{h,w,x}a, stmf{s,d}, stmf{s,d}a. | |
59 | (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT, | |
60 | ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR, | |
61 | ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL, | |
62 | ASI_CORE_SELECT_COMMIT_NHT. | |
63 | ||
535b785f AM |
64 | 2017-05-18 Alan Modra <amodra@gmail.com> |
65 | ||
66 | * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE. | |
67 | * aarch64-dis.c: Likewise. | |
68 | * aarch64-gen.c: Likewise. | |
69 | * aarch64-opc.c: Likewise. | |
70 | ||
25499ac7 MR |
71 | 2017-05-15 Maciej W. Rozycki <macro@imgtec.com> |
72 | Matthew Fortune <matthew.fortune@imgtec.com> | |
73 | ||
74 | * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and | |
75 | ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry. | |
76 | (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag. | |
77 | (print_insn_arg) <OP_REG28>: Add handler. | |
78 | (validate_insn_args) <OP_REG28>: Handle. | |
79 | (print_mips16_insn_arg): Handle MIPS16 instructions that require | |
80 | 32-bit encoding and 9-bit immediates. | |
81 | (print_insn_mips16): Handle MIPS16 instructions that require | |
82 | 32-bit encoding and MFC0/MTC0 operand decoding. | |
83 | * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'> | |
84 | <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers. | |
85 | (RD_C0, WR_C0, E2, E2MT): New macros. | |
86 | (mips16_opcodes): Add entries for MIPS16e2 instructions: | |
87 | GP-relative "addiu" and its "addu" spelling, "andi", "cache", | |
88 | "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh", | |
89 | "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0", | |
90 | "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause", | |
91 | "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw" | |
92 | instructions, "swl", "swr", "sync" and its "sync_acquire", | |
93 | "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases, | |
94 | "xori", "dmt", "dvpe", "emt" and "evpe". Add split | |
95 | regular/extended entries for original MIPS16 ISA revision | |
96 | instructions whose extended forms are subdecoded in the MIPS16e2 | |
97 | ISA revision: "li", "sll" and "srl". | |
98 | ||
fdfb4752 MR |
99 | 2017-05-15 Maciej W. Rozycki <macro@imgtec.com> |
100 | ||
101 | * mips-dis.c (print_insn_args) <default>: Remove an MT ASE | |
102 | reference in CP0 move operand decoding. | |
103 | ||
a4f89915 MR |
104 | 2017-05-12 Maciej W. Rozycki <macro@imgtec.com> |
105 | ||
106 | * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand | |
107 | type to hexadecimal. | |
108 | (mips16_opcodes): Add operandless "break" and "sdbbp" entries. | |
109 | ||
99e2d67a MR |
110 | 2017-05-11 Maciej W. Rozycki <macro@imgtec.com> |
111 | ||
112 | * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs", | |
113 | "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release", | |
114 | "sync_rmb" and "sync_wmb" as aliases. | |
115 | * micromips-opc.c (micromips_opcodes): Mark "sync_acquire", | |
116 | "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases. | |
117 | ||
53a346d8 CZ |
118 | 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> |
119 | ||
120 | * arc-dis.c (parse_option): Update quarkse_em option.. | |
121 | * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to | |
122 | QUARKSE1. | |
123 | (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2. | |
124 | ||
f91d48de KC |
125 | 2017-05-03 Kito Cheng <kito.cheng@gmail.com> |
126 | ||
127 | * riscv-dis.c (print_insn_args): Handle 'Co' operands. | |
128 | ||
43e379d7 MC |
129 | 2017-05-01 Michael Clark <michaeljclark@mac.com> |
130 | ||
131 | * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary | |
132 | register. | |
133 | ||
a4ddc54e MR |
134 | 2017-05-02 Maciej W. Rozycki <macro@imgtec.com> |
135 | ||
136 | * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps | |
137 | and branches and not synthetic data instructions. | |
138 | ||
fe50e98c BE |
139 | 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de> |
140 | ||
141 | * arm-dis.c (print_insn_thumb32): Fix value_in_comment. | |
142 | ||
126124cc CZ |
143 | 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> |
144 | ||
145 | * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics. | |
146 | * arc-opc.c (insert_r13el): New function. | |
147 | (R13_EL): Define. | |
148 | * arc-tbl.h: Add new enter/leave variants. | |
149 | ||
be6a24d8 CZ |
150 | 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> |
151 | ||
152 | * arc-tbl.h: Reorder NOP entry to be before MOV instructions. | |
153 | ||
0348fd79 MR |
154 | 2017-04-25 Maciej W. Rozycki <macro@imgtec.com> |
155 | ||
156 | * mips-dis.c (print_mips_disassembler_options): Add | |
157 | `no-aliases'. | |
158 | ||
6e3d1f07 MR |
159 | 2017-04-25 Maciej W. Rozycki <macro@imgtec.com> |
160 | ||
161 | * mips16-opc.c (AL): New macro. | |
162 | (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms | |
163 | of "ld" and "lw" as aliases. | |
164 | ||
957f6b39 TC |
165 | 2017-04-24 Tamar Christina <tamar.christina@arm.com> |
166 | ||
167 | * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE | |
168 | arguments. | |
169 | ||
a8cc8a54 AM |
170 | 2017-04-22 Alexander Fedotov <alfedotov@gmail.com> |
171 | Alan Modra <amodra@gmail.com> | |
172 | ||
173 | * ppc-opc.c (ELEV): Define. | |
174 | (vle_opcodes): Add se_rfgi and e_sc. | |
175 | (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx | |
176 | for E200Z4. | |
177 | ||
3ab87b68 JM |
178 | 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com> |
179 | ||
180 | * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9. | |
181 | ||
792f174f NC |
182 | 2017-04-21 Nick Clifton <nickc@redhat.com> |
183 | ||
184 | PR binutils/21380 | |
185 | * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R, | |
186 | LD3R and LD4R. | |
187 | ||
42742084 AM |
188 | 2017-04-13 Alan Modra <amodra@gmail.com> |
189 | ||
190 | * epiphany-desc.c: Regenerate. | |
191 | * fr30-desc.c: Regenerate. | |
192 | * frv-desc.c: Regenerate. | |
193 | * ip2k-desc.c: Regenerate. | |
194 | * iq2000-desc.c: Regenerate. | |
195 | * lm32-desc.c: Regenerate. | |
196 | * m32c-desc.c: Regenerate. | |
197 | * m32r-desc.c: Regenerate. | |
198 | * mep-desc.c: Regenerate. | |
199 | * mt-desc.c: Regenerate. | |
200 | * or1k-desc.c: Regenerate. | |
201 | * xc16x-desc.c: Regenerate. | |
202 | * xstormy16-desc.c: Regenerate. | |
203 | ||
9a85b496 AM |
204 | 2017-04-11 Alan Modra <amodra@gmail.com> |
205 | ||
ef85eab0 | 206 | * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2, |
c03dc33b AM |
207 | PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set |
208 | PPC_OPCODE_TMR for e6500. | |
9a85b496 AM |
209 | * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500. |
210 | (PPCVEC3): Define as PPC_OPCODE_POWER9. | |
9570835e AM |
211 | (PPCVSX2): Define as PPC_OPCODE_POWER8. |
212 | (PPCVSX3): Define as PPC_OPCODE_POWER9. | |
ef85eab0 | 213 | (PPCHTM): Define as PPC_OPCODE_POWER8. |
c03dc33b | 214 | (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500. |
9a85b496 | 215 | |
62adc510 AM |
216 | 2017-04-10 Alan Modra <amodra@gmail.com> |
217 | ||
218 | * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440. | |
219 | * ppc-opc.c (MULHW): Add PPC_OPCODE_476. | |
220 | (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit | |
221 | removal of PPC_OPCODE_440 from ppc476 cpu selection bits. | |
222 | ||
aa808707 PC |
223 | 2017-04-09 Pip Cet <pipcet@gmail.com> |
224 | ||
225 | * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify | |
226 | appropriate floating-point precision directly. | |
227 | ||
ac8f0f72 AM |
228 | 2017-04-07 Alan Modra <amodra@gmail.com> |
229 | ||
230 | * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl, | |
231 | lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx, | |
232 | lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx, | |
233 | lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only | |
234 | vector instructions with E6500 not PPCVEC2. | |
235 | ||
62ecb94c PC |
236 | 2017-04-06 Pip Cet <pipcet@gmail.com> |
237 | ||
238 | * Makefile.am: Add wasm32-dis.c. | |
239 | * configure.ac: Add wasm32-dis.c to wasm32 target. | |
240 | * disassemble.c: Add wasm32 disassembler code. | |
241 | * wasm32-dis.c: New file. | |
242 | * Makefile.in: Regenerate. | |
243 | * configure: Regenerate. | |
244 | * po/POTFILES.in: Regenerate. | |
245 | * po/opcodes.pot: Regenerate. | |
246 | ||
f995bbe8 PA |
247 | 2017-04-05 Pedro Alves <palves@redhat.com> |
248 | ||
249 | * arc-dis.c (parse_option, parse_disassembler_options): Constify. | |
250 | * arm-dis.c (parse_arm_disassembler_options): Constify. | |
251 | * ppc-dis.c (powerpc_init_dialect): Constify local. | |
252 | * vax-dis.c (parse_disassembler_options): Constify. | |
253 | ||
b5292032 PD |
254 | 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com> |
255 | ||
256 | * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to | |
257 | RISCV_GP_SYMBOL. | |
258 | ||
f96bd6c2 PC |
259 | 2017-03-30 Pip Cet <pipcet@gmail.com> |
260 | ||
261 | * configure.ac: Add (empty) bfd_wasm32_arch target. | |
262 | * configure: Regenerate | |
263 | * po/opcodes.pot: Regenerate. | |
264 | ||
f7c514a3 JM |
265 | 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com> |
266 | ||
267 | Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, & | |
268 | OSA2015. | |
269 | * opcodes/sparc-opc.c (asi_table): New ASIs. | |
270 | ||
52be03fd AM |
271 | 2017-03-29 Alan Modra <amodra@gmail.com> |
272 | ||
273 | * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add | |
274 | "raw" option. | |
275 | (lookup_powerpc): Don't special case -1 dialect. Handle | |
276 | PPC_OPCODE_RAW. | |
277 | (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first | |
278 | lookup_powerpc call, pass it on second. | |
279 | ||
9b753937 AM |
280 | 2017-03-27 Alan Modra <amodra@gmail.com> |
281 | ||
282 | PR 21303 | |
283 | * ppc-dis.c (struct ppc_mopt): Comment. | |
284 | (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu. | |
285 | ||
c0c31e91 RZ |
286 | 2017-03-27 Rinat Zelig <rinat@mellanox.com> |
287 | ||
288 | * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format. | |
289 | * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, | |
290 | F_NPS_M, F_NPS_CORE, F_NPS_ALL. | |
291 | (insert_nps_misc_imm_offset): New function. | |
292 | (extract_nps_misc imm_offset): New function. | |
293 | (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T. | |
294 | (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T. | |
295 | ||
2253c8f0 AK |
296 | 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
297 | ||
298 | * s390-mkopc.c (main): Remove vx2 check. | |
299 | * s390-opc.txt: Remove vx2 instruction flags. | |
300 | ||
645d3342 RZ |
301 | 2017-03-21 Rinat Zelig <rinat@mellanox.com> |
302 | ||
303 | * arc-nps400-tbl.h: Add cp32/cp16 instructions format. | |
304 | * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET. | |
305 | (insert_nps_imm_offset): New function. | |
306 | (extract_nps_imm_offset): New function. | |
307 | (insert_nps_imm_entry): New function. | |
308 | (extract_nps_imm_entry): New function. | |
309 | ||
4b94dd2d AM |
310 | 2017-03-17 Alan Modra <amodra@gmail.com> |
311 | ||
312 | PR 21248 | |
313 | * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33, | |
314 | mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after | |
315 | those spr mnemonics they alias. Similarly for mtibatl, mtibatu. | |
316 | ||
b416fe87 KC |
317 | 2017-03-14 Kito Cheng <kito.cheng@gmail.com> |
318 | ||
319 | * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding. | |
320 | <c.andi>: Likewise. | |
321 | <c.addiw> Likewise. | |
322 | ||
03b039a5 KC |
323 | 2017-03-14 Kito Cheng <kito.cheng@gmail.com> |
324 | ||
325 | * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode. | |
326 | ||
2c232b83 AW |
327 | 2017-03-13 Andrew Waterman <andrew@sifive.com> |
328 | ||
329 | * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode. | |
330 | <srl> Likewise. | |
331 | <srai> Likewise. | |
332 | <sra> Likewise. | |
333 | ||
86fa6981 L |
334 | 2017-03-09 H.J. Lu <hongjiu.lu@intel.com> |
335 | ||
336 | * i386-gen.c (opcode_modifiers): Replace S with Load. | |
337 | * i386-opc.h (S): Removed. | |
338 | (Load): New. | |
339 | (i386_opcode_modifier): Replace s with load. | |
340 | * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3} | |
341 | and {evex}. Replace S with Load. | |
342 | * i386-tbl.h: Regenerated. | |
343 | ||
c1fe188b L |
344 | 2017-03-09 H.J. Lu <hongjiu.lu@intel.com> |
345 | ||
346 | * i386-opc.tbl: Use CpuCET on rdsspq. | |
347 | * i386-tbl.h: Regenerated. | |
348 | ||
4b8b687e PB |
349 | 2017-03-08 Peter Bergner <bergner@vnet.ibm.com> |
350 | ||
351 | * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2; | |
352 | <vsx>: Do not use PPC_OPCODE_VSX3; | |
353 | ||
1437d063 PB |
354 | 2017-03-08 Peter Bergner <bergner@vnet.ibm.com> |
355 | ||
356 | * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic. | |
357 | ||
603555e5 L |
358 | 2017-03-06 H.J. Lu <hongjiu.lu@intel.com> |
359 | ||
360 | * i386-dis.c (REG_0F1E_MOD_3): New enum. | |
361 | (MOD_0F1E_PREFIX_1): Likewise. | |
362 | (MOD_0F38F5_PREFIX_2): Likewise. | |
363 | (MOD_0F38F6_PREFIX_0): Likewise. | |
364 | (RM_0F1E_MOD_3_REG_7): Likewise. | |
365 | (PREFIX_MOD_0_0F01_REG_5): Likewise. | |
366 | (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. | |
367 | (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise. | |
368 | (PREFIX_0F1E): Likewise. | |
369 | (PREFIX_MOD_0_0FAE_REG_5): Likewise. | |
370 | (PREFIX_0F38F5): Likewise. | |
371 | (dis386_twobyte): Use PREFIX_0F1E. | |
372 | (reg_table): Add REG_0F1E_MOD_3. | |
373 | (prefix_table): Add PREFIX_MOD_0_0F01_REG_5, | |
374 | PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2, | |
375 | PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update | |
376 | PREFIX_0FAE_REG_6 and PREFIX_0F38F6. | |
377 | (three_byte_table): Use PREFIX_0F38F5. | |
378 | (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5. | |
379 | Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0. | |
380 | (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0, | |
381 | RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and | |
382 | PREFIX_MOD_3_0F01_REG_5_RM_2. | |
383 | * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS. | |
384 | (cpu_flags): Add CpuCET. | |
385 | * i386-opc.h (CpuCET): New enum. | |
386 | (CpuUnused): Commented out. | |
387 | (i386_cpu_flags): Add cpucet. | |
388 | * i386-opc.tbl: Add Intel CET instructions. | |
389 | * i386-init.h: Regenerated. | |
390 | * i386-tbl.h: Likewise. | |
391 | ||
73f07bff AM |
392 | 2017-03-06 Alan Modra <amodra@gmail.com> |
393 | ||
394 | PR 21124 | |
395 | * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram) | |
396 | (extract_raq, extract_ras, extract_rbx): New functions. | |
397 | (powerpc_operands): Use opposite corresponding insert function. | |
398 | (Q_MASK): Define. | |
399 | (powerpc_opcodes): Apply Q_MASK to all quad insns with even | |
400 | register restriction. | |
401 | ||
65b48a81 PB |
402 | 2017-02-28 Peter Bergner <bergner@vnet.ibm.com> |
403 | ||
404 | * disassemble.c Include "safe-ctype.h". | |
405 | (disassemble_init_for_target): Handle s390 init. | |
406 | (remove_whitespace_and_extra_commas): New function. | |
407 | (disassembler_options_cmp): Likewise. | |
408 | * arm-dis.c: Include "libiberty.h". | |
409 | (NUM_ELEM): Delete. | |
410 | (regnames): Use long disassembler style names. | |
411 | Add force-thumb and no-force-thumb options. | |
412 | (NUM_ARM_REGNAMES): Rename from this... | |
413 | (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE. | |
414 | (get_arm_regname_num_options): Delete. | |
415 | (set_arm_regname_option): Likewise. | |
416 | (get_arm_regnames): Likewise. | |
417 | (parse_disassembler_options): Likewise. | |
418 | (parse_arm_disassembler_option): Rename from this... | |
419 | (parse_arm_disassembler_options): ...to this. Make static. | |
420 | Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options. | |
421 | (print_insn): Use parse_arm_disassembler_options. | |
422 | (disassembler_options_arm): New function. | |
423 | (print_arm_disassembler_options): Handle updated regnames. | |
424 | * ppc-dis.c: Include "libiberty.h". | |
425 | (ppc_opts): Add "32" and "64" entries. | |
426 | (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp. | |
427 | (powerpc_init_dialect): Add break to switch statement. | |
428 | Use new FOR_EACH_DISASSEMBLER_OPTION macro. | |
429 | (disassembler_options_powerpc): New function. | |
430 | (print_ppc_disassembler_options): Use ARRAY_SIZE. | |
431 | Remove printing of "32" and "64". | |
432 | * s390-dis.c: Include "libiberty.h". | |
433 | (init_flag): Remove unneeded variable. | |
434 | (struct s390_options_t): New structure type. | |
435 | (options): New structure. | |
436 | (init_disasm): Rename from this... | |
437 | (disassemble_init_s390): ...to this. Add initializations for | |
438 | current_arch_mask and option_use_insn_len_bits_p. Remove init_flag. | |
439 | (print_insn_s390): Delete call to init_disasm. | |
440 | (disassembler_options_s390): New function. | |
441 | (print_s390_disassembler_options): Print using information from | |
442 | struct 'options'. | |
443 | * po/opcodes.pot: Regenerate. | |
444 | ||
15c7c1d8 JB |
445 | 2017-02-28 Jan Beulich <jbeulich@suse.com> |
446 | ||
447 | * i386-dis.c (PCMPESTR_Fixup): New. | |
448 | (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete. | |
449 | (prefix_table): Use PCMPESTR_Fixup. | |
450 | (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use | |
451 | PCMPESTR_Fixup. | |
452 | (vex_w_table): Delete VPCMPESTR{I,M} entries. | |
453 | * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm): | |
454 | Split 64-bit and non-64-bit variants. | |
455 | * opcodes/i386-tbl.h: Re-generate. | |
456 | ||
582e12bf RS |
457 | 2017-02-24 Richard Sandiford <richard.sandiford@arm.com> |
458 | ||
459 | * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD) | |
460 | (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD) | |
461 | (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S) | |
462 | (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H) | |
463 | (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH) | |
464 | (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD) | |
465 | (OP_SVE_V_HSD): New macros. | |
466 | (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD) | |
467 | (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD) | |
468 | (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete. | |
469 | (aarch64_opcode_table): Add new SVE instructions. | |
470 | (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate | |
471 | for rotation operands. Add new SVE operands. | |
472 | * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter. | |
473 | (ins_sve_quad_index): Likewise. | |
474 | (ins_imm_rotate): Split into... | |
475 | (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters. | |
476 | * aarch64-asm.c (aarch64_ins_imm_rotate): Split into... | |
477 | (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two | |
478 | functions. | |
479 | (aarch64_ins_sve_addr_ri_s4): New function. | |
480 | (aarch64_ins_sve_quad_index): Likewise. | |
481 | (do_misc_encoding): Handle "MOV Zn.Q, Qm". | |
482 | * aarch64-asm-2.c: Regenerate. | |
483 | * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor. | |
484 | (ext_sve_quad_index): Likewise. | |
485 | (ext_imm_rotate): Split into... | |
486 | (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors. | |
487 | * aarch64-dis.c (aarch64_ext_imm_rotate): Split into... | |
488 | (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two | |
489 | functions. | |
490 | (aarch64_ext_sve_addr_ri_s4): New function. | |
491 | (aarch64_ext_sve_quad_index): Likewise. | |
492 | (aarch64_ext_sve_index): Allow quad indices. | |
493 | (do_misc_decoding): Likewise. | |
494 | * aarch64-dis-2.c: Regenerate. | |
495 | * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New | |
496 | aarch64_field_kinds. | |
497 | (OPD_F_OD_MASK): Widen by one bit. | |
498 | (OPD_F_NO_ZR): Bump accordingly. | |
499 | (get_operand_field_width): New function. | |
500 | * aarch64-opc.c (fields): Add new SVE fields. | |
501 | (operand_general_constraint_met_p): Handle new SVE operands. | |
502 | (aarch64_print_operand): Likewise. | |
503 | * aarch64-opc-2.c: Regenerate. | |
504 | ||
f482d304 RS |
505 | 2017-02-24 Richard Sandiford <richard.sandiford@arm.com> |
506 | ||
507 | * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with... | |
508 | (aarch64_feature_compnum): ...this. | |
509 | (SIMD_V8_3): Replace with... | |
510 | (COMPNUM): ...this. | |
511 | (CNUM_INSN): New macro. | |
512 | (aarch64_opcode_table): Use it for the complex number instructions. | |
513 | ||
7db2c588 JB |
514 | 2017-02-24 Jan Beulich <jbeulich@suse.com> |
515 | ||
516 | * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST. | |
517 | ||
1e9d41d4 SL |
518 | 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com> |
519 | ||
520 | Add support for associating SPARC ASIs with an architecture level. | |
521 | * include/opcode/sparc.h (sparc_asi): New sparc_asi struct. | |
522 | * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/ | |
523 | decoding of SPARC ASIs. | |
524 | ||
53c4d625 JB |
525 | 2017-02-23 Jan Beulich <jbeulich@suse.com> |
526 | ||
527 | * i386-dis.c (get_valid_dis386): Don't special case VEX opcode | |
528 | 82. For 3-byte VEX only special case opcode 77 in VEX_0F space. | |
529 | ||
11648de5 JB |
530 | 2017-02-21 Jan Beulich <jbeulich@suse.com> |
531 | ||
532 | * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand | |
533 | 1 (instead of to itself). Correct typo. | |
534 | ||
f98d33be AW |
535 | 2017-02-14 Andrew Waterman <andrew@sifive.com> |
536 | ||
537 | * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and | |
538 | pseudoinstructions. | |
539 | ||
773fb663 RS |
540 | 2017-02-15 Richard Sandiford <richard.sandiford@arm.com> |
541 | ||
542 | * aarch64-opc.c (aarch64_sys_regs): Add SVE registers. | |
543 | (aarch64_sys_reg_supported_p): Handle them. | |
544 | ||
cc07cda6 CZ |
545 | 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com> |
546 | ||
547 | * arc-opc.c (UIMM6_20R): Define. | |
548 | (SIMM12_20): Use above. | |
549 | (SIMM12_20R): Define. | |
550 | (SIMM3_5_S): Use above. | |
551 | (UIMM7_A32_11R_S): Define. | |
552 | (UIMM7_9_S): Use above. | |
553 | (UIMM3_13R_S): Define. | |
554 | (SIMM11_A32_7_S): Use above. | |
555 | (SIMM9_8R): Define. | |
556 | (UIMM10_A32_8_S): Use above. | |
557 | (UIMM8_8R_S): Define. | |
558 | (W6): Use above. | |
559 | (arc_relax_opcodes): Use all above defines. | |
560 | ||
66a5a740 VG |
561 | 2017-02-15 Vineet Gupta <vgupta@synopsys.com> |
562 | ||
563 | * arc-regs.h: Distinguish some of the registers different on | |
564 | ARC700 and HS38 cpus. | |
565 | ||
7e0de605 AM |
566 | 2017-02-14 Alan Modra <amodra@gmail.com> |
567 | ||
568 | PR 21118 | |
569 | * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries | |
570 | with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR. | |
571 | ||
54064fdb AM |
572 | 2017-02-11 Stafford Horne <shorne@gmail.com> |
573 | Alan Modra <amodra@gmail.com> | |
574 | ||
575 | * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps. | |
576 | Use insn_bytes_value and insn_int_value directly instead. Don't | |
577 | free allocated memory until function exit. | |
578 | ||
dce75bf9 NP |
579 | 2017-02-10 Nicholas Piggin <npiggin@gmail.com> |
580 | ||
581 | * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics. | |
582 | ||
1b7e3d2f NC |
583 | 2017-02-03 Nick Clifton <nickc@redhat.com> |
584 | ||
585 | PR 21096 | |
586 | * aarch64-opc.c (print_register_list): Ensure that the register | |
587 | list index will fir into the tb buffer. | |
588 | (print_register_offset_address): Likewise. | |
589 | * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf. | |
590 | ||
8ec5cf65 AD |
591 | 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com> |
592 | ||
593 | PR 21056 | |
594 | * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel | |
595 | instructions when the previous fetch packet ends with a 32-bit | |
596 | instruction. | |
597 | ||
a1aa5e81 DD |
598 | 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu> |
599 | ||
600 | * pru-opc.c: Remove vague reference to a future GDB port. | |
601 | ||
add3afb2 NC |
602 | 2017-01-20 Nick Clifton <nickc@redhat.com> |
603 | ||
604 | * po/ga.po: Updated Irish translation. | |
605 | ||
c13a63b0 SN |
606 | 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com> |
607 | ||
608 | * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly. | |
609 | ||
9608051a YQ |
610 | 2017-01-13 Yao Qi <yao.qi@linaro.org> |
611 | ||
612 | * m68k-dis.c (match_insn_m68k): Extend comments. Return -1 | |
613 | if FETCH_DATA returns 0. | |
614 | (m68k_scan_mask): Likewise. | |
615 | (print_insn_m68k): Update code to handle -1 return value. | |
616 | ||
f622ea96 YQ |
617 | 2017-01-13 Yao Qi <yao.qi@linaro.org> |
618 | ||
619 | * m68k-dis.c (enum print_insn_arg_error): New. | |
620 | (NEXTBYTE): Replace -3 with | |
621 | PRINT_INSN_ARG_MEMORY_ERROR. | |
622 | (NEXTULONG): Likewise. | |
623 | (NEXTSINGLE): Likewise. | |
624 | (NEXTDOUBLE): Likewise. | |
625 | (NEXTDOUBLE): Likewise. | |
626 | (NEXTPACKED): Likewise. | |
627 | (FETCH_ARG): Likewise. | |
628 | (FETCH_DATA): Update comments. | |
629 | (print_insn_arg): Update comments. Replace magic numbers with | |
630 | enum. | |
631 | (match_insn_m68k): Likewise. | |
632 | ||
620214f7 IT |
633 | 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
634 | ||
635 | * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2. | |
636 | * i386-dis-evex.h (evex_table): Updated. | |
637 | * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS, | |
638 | CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS. | |
639 | (cpu_flags): Add CpuAVX512_VPOPCNTDQ. | |
640 | * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New. | |
641 | (i386_cpu_flags): Add cpuavx512_vpopcntdq. | |
642 | * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions. | |
643 | * i386-init.h: Regenerate. | |
644 | * i386-tbl.h: Ditto. | |
645 | ||
d95014a2 YQ |
646 | 2017-01-12 Yao Qi <yao.qi@linaro.org> |
647 | ||
648 | * msp430-dis.c (msp430_singleoperand): Return -1 if | |
649 | msp430dis_opcode_signed returns false. | |
650 | (msp430_doubleoperand): Likewise. | |
651 | (msp430_branchinstr): Return -1 if | |
652 | msp430dis_opcode_unsigned returns false. | |
653 | (msp430x_calla_instr): Likewise. | |
654 | (print_insn_msp430): Likewise. | |
655 | ||
0ae60c3e NC |
656 | 2017-01-05 Nick Clifton <nickc@redhat.com> |
657 | ||
658 | PR 20946 | |
659 | * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name | |
660 | could not be matched. | |
661 | (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning | |
662 | NULL. | |
663 | ||
d74d4880 SN |
664 | 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com> |
665 | ||
666 | * aarch64-tbl.h (RCPC, RCPC_INSN): Define. | |
667 | (aarch64_opcode_table): Use RCPC_INSN. | |
668 | ||
cc917fd9 KC |
669 | 2017-01-03 Kito Cheng <kito.cheng@gmail.com> |
670 | ||
671 | * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA | |
672 | extension. | |
673 | * riscv-opcodes/all-opcodes: Likewise. | |
674 | ||
b52d3cfc DP |
675 | 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org> |
676 | ||
677 | * riscv-dis.c (print_insn_args): Add fall through comment. | |
678 | ||
f90c58d5 NC |
679 | 2017-01-03 Nick Clifton <nickc@redhat.com> |
680 | ||
681 | * po/sr.po: New Serbian translation. | |
682 | * configure.ac (ALL_LINGUAS): Add sr. | |
683 | * configure: Regenerate. | |
684 | ||
f47b0d4a AM |
685 | 2017-01-02 Alan Modra <amodra@gmail.com> |
686 | ||
687 | * epiphany-desc.h: Regenerate. | |
688 | * epiphany-opc.h: Regenerate. | |
689 | * fr30-desc.h: Regenerate. | |
690 | * fr30-opc.h: Regenerate. | |
691 | * frv-desc.h: Regenerate. | |
692 | * frv-opc.h: Regenerate. | |
693 | * ip2k-desc.h: Regenerate. | |
694 | * ip2k-opc.h: Regenerate. | |
695 | * iq2000-desc.h: Regenerate. | |
696 | * iq2000-opc.h: Regenerate. | |
697 | * lm32-desc.h: Regenerate. | |
698 | * lm32-opc.h: Regenerate. | |
699 | * m32c-desc.h: Regenerate. | |
700 | * m32c-opc.h: Regenerate. | |
701 | * m32r-desc.h: Regenerate. | |
702 | * m32r-opc.h: Regenerate. | |
703 | * mep-desc.h: Regenerate. | |
704 | * mep-opc.h: Regenerate. | |
705 | * mt-desc.h: Regenerate. | |
706 | * mt-opc.h: Regenerate. | |
707 | * or1k-desc.h: Regenerate. | |
708 | * or1k-opc.h: Regenerate. | |
709 | * xc16x-desc.h: Regenerate. | |
710 | * xc16x-opc.h: Regenerate. | |
711 | * xstormy16-desc.h: Regenerate. | |
712 | * xstormy16-opc.h: Regenerate. | |
713 | ||
2571583a AM |
714 | 2017-01-02 Alan Modra <amodra@gmail.com> |
715 | ||
716 | Update year range in copyright notice of all files. | |
717 | ||
5c1ad6b5 | 718 | For older changes see ChangeLog-2016 |
3499769a | 719 | \f |
5c1ad6b5 | 720 | Copyright (C) 2017 Free Software Foundation, Inc. |
3499769a AM |
721 | |
722 | Copying and distribution of this file, with or without modification, | |
723 | are permitted in any medium without royalty provided the copyright | |
724 | notice and this notice are preserved. | |
725 | ||
726 | Local Variables: | |
727 | mode: change-log | |
728 | left-margin: 8 | |
729 | fill-column: 74 | |
730 | version-control: never | |
731 | End: |