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MIPS: Add microMIPS R5 support
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
f5b2fd52
MR		 12017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
2 Maciej W. Rozycki <macro@imgtec.com>
3
4 * micromips-opc.c (I36): New macro.
5 (micromips_opcodes): Add "eretnc".
6
9785fc2a
MR		 72017-06-30 Maciej W. Rozycki <macro@imgtec.com>
8 Andrew Bennett <andrew.bennett@imgtec.com>
9
10 * mips-dis.c (mips_calculate_combination_ases): Handle the
11 ASE_XPA_VIRT flag.
12 (parse_mips_ase_option): New function.
13 (parse_mips_dis_option): Factor out ASE option handling to the
14 new function. Call `mips_calculate_combination_ases'.
15 * mips-opc.c (XPAVZ): New macro.
16 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
17 "mfhgc0", "mthc0" and "mthgc0".
18
60804c53
MR		 192017-06-29 Maciej W. Rozycki <macro@imgtec.com>
20
21 * mips-dis.c (mips_calculate_combination_ases): New function.
22 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
23 calculation to the new function.
24 (set_default_mips_dis_options): Call the new function.
25
2e74f9dd
AK		 262017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
27
28 * arc-dis.c (parse_disassembler_options): Use
29 FOR_EACH_DISASSEMBLER_OPTION.
30
e1e94c49
AK		 312017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
32
33 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
34 disassembler option strings.
35 (parse_cpu_option): Likewise.
36
65a55fbb
TC		 372017-06-28 Tamar Christina <tamar.christina@arm.com>
38
39 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
40 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
41 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
42 (aarch64_feature_dotprod, DOT_INSN): New.
43 (udot, sdot): New.
44 * aarch64-dis-2.c: Regenerated.
45
c604a79a
JW		 462017-06-28 Jiong Wang <jiong.wang@arm.com>
47
48 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
49
38bf472a
MR		 502017-06-28 Maciej W. Rozycki <macro@imgtec.com>
51 Matthew Fortune <matthew.fortune@imgtec.com>
52 Andrew Bennett <andrew.bennett@imgtec.com>
53
54 * mips-formats.h (INT_BIAS): New macro.
55 (INT_ADJ): Redefine in INT_BIAS terms.
56 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
57 (mips_print_save_restore): New function.
58 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
59 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
60 call.
61 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
62 (print_mips16_insn_arg): Call `mips_print_save_restore' for
63 OP_SAVE_RESTORE_LIST handling, factored out from here.
64 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
65 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
66 (mips_builtin_opcodes): Add "restore" and "save" entries.
67 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
68 (IAMR2): New macro.
69 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
70
9bdfdbf9
AW		 712017-06-23 Andrew Waterman <andrew@sifive.com>
72
73 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
74 alias; do not mark SLTI instruction as an alias.
75
2234eee6
L		 762017-06-21 H.J. Lu <hongjiu.lu@intel.com>
77
78 * i386-dis.c (RM_0FAE_REG_5): Removed.
79 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
80 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
81 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
82 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
83 PREFIX_MOD_3_0F01_REG_5_RM_0.
84 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
85 PREFIX_MOD_3_0FAE_REG_5.
86 (mod_table): Update MOD_0FAE_REG_5.
87 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
88 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
89 * i386-tbl.h: Regenerated.
90
c2f76402
L		 912017-06-21 H.J. Lu <hongjiu.lu@intel.com>
92
93 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
94 * i386-opc.tbl: Likewise.
95 * i386-tbl.h: Regenerated.
96
9fef80d6
L		 972017-06-21 H.J. Lu <hongjiu.lu@intel.com>
98
99 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
100 and "jmp{&|}".
101 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
102 prefix.
103
0f6d864d
NC		 1042017-06-19 Nick Clifton <nickc@redhat.com>
105
106 PR binutils/21614
107 * score-dis.c (score_opcodes): Add sentinel.
108
e197589b
AM		 1092017-06-16 Alan Modra <amodra@gmail.com>
110
111 * rx-decode.c: Regenerate.
112
0d96e4df
L		 1132017-06-15 H.J. Lu <hongjiu.lu@intel.com>
114
115 PR binutils/21594
116 * i386-dis.c (OP_E_register): Check valid bnd register.
117 (OP_G): Likewise.
118
cd3ea7c6
NC		 1192017-06-15 Nick Clifton <nickc@redhat.com>
120
121 PR binutils/21595
122 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
123 range value.
124
63323b5b
NC		 1252017-06-15 Nick Clifton <nickc@redhat.com>
126
127 PR binutils/21588
128 * rl78-decode.opc (OP_BUF_LEN): Define.
129 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
130 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
131 array.
132 * rl78-decode.c: Regenerate.
133
08c7881b
NC		 1342017-06-15 Nick Clifton <nickc@redhat.com>
135
136 PR binutils/21586
137 * bfin-dis.c (gregs): Clip index to prevent overflow.
138 (regs): Likewise.
139 (regs_lo): Likewise.
140 (regs_hi): Likewise.
141
e64519d1
NC		 1422017-06-14 Nick Clifton <nickc@redhat.com>
143
144 PR binutils/21576
145 * score7-dis.c (score_opcodes): Add sentinel.
146
6394c606
YQ		 1472017-06-14 Yao Qi <yao.qi@linaro.org>
148
149 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
150 * arm-dis.c: Likewise.
151 * ia64-dis.c: Likewise.
152 * mips-dis.c: Likewise.
153 * spu-dis.c: Likewise.
154 * disassemble.h (print_insn_aarch64): New declaration, moved from
155 include/dis-asm.h.
156 (print_insn_big_arm, print_insn_big_mips): Likewise.
157 (print_insn_i386, print_insn_ia64): Likewise.
158 (print_insn_little_arm, print_insn_little_mips): Likewise.
159
db5fa770
NC		 1602017-06-14 Nick Clifton <nickc@redhat.com>
161
162 PR binutils/21587
163 * rx-decode.opc: Include libiberty.h
164 (GET_SCALE): New macro - validates access to SCALE array.
165 (GET_PSCALE): New macro - validates access to PSCALE array.
166 (DIs, SIs, S2Is, rx_disp): Use new macros.
167 * rx-decode.c: Regenerate.
168
05c966f3
AV		 1692017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
170
171 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
172
10045478
AK		 1732017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
174
175 * arc-dis.c (enforced_isa_mask): Declare.
176 (cpu_types): Likewise.
177 (parse_cpu_option): New function.
178 (parse_disassembler_options): Use it.
179 (print_insn_arc): Use enforced_isa_mask.
180 (print_arc_disassembler_options): Document new options.
181
88c1242d
YQ		 1822017-05-24 Yao Qi <yao.qi@linaro.org>
183
184 * alpha-dis.c: Include disassemble.h, don't include
185 dis-asm.h.
186 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
187 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
188 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
189 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
190 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
191 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
192 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
193 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
194 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
195 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
196 * moxie-dis.c, msp430-dis.c, mt-dis.c:
197 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
198 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
199 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
200 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
201 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
202 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
203 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
204 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
205 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
206 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
207 * z80-dis.c, z8k-dis.c: Likewise.
208 * disassemble.h: New file.
209
ab20fa4a
YQ		 2102017-05-24 Yao Qi <yao.qi@linaro.org>
211
212 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
213 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
214
003ca0fd
YQ		 2152017-05-24 Yao Qi <yao.qi@linaro.org>
216
217 * disassemble.c (disassembler): Add arguments a, big and mach.
218 Use them.
219
04ef582a
L		 2202017-05-22 H.J. Lu <hongjiu.lu@intel.com>
221
222 * i386-dis.c (NOTRACK_Fixup): New.
223 (NOTRACK): Likewise.
224 (NOTRACK_PREFIX): Likewise.
225 (last_active_prefix): Likewise.
226 (reg_table): Use NOTRACK on indirect call and jmp.
227 (ckprefix): Set last_active_prefix.
228 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
229 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
230 * i386-opc.h (NoTrackPrefixOk): New.
231 (i386_opcode_modifier): Add notrackprefixok.
232 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
233 Add notrack.
234 * i386-tbl.h: Regenerated.
235
64517994
JM		 2362017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
237
238 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
239 (X_IMM2): Define.
240 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
241 bfd_mach_sparc_v9m8.
242 (print_insn_sparc): Handle new operand types.
243 * sparc-opc.c (MASK_M8): Define.
244 (v6): Add MASK_M8.
245 (v6notlet): Likewise.
246 (v7): Likewise.
247 (v8): Likewise.
248 (v9): Likewise.
249 (v9a): Likewise.
250 (v9b): Likewise.
251 (v9c): Likewise.
252 (v9d): Likewise.
253 (v9e): Likewise.
254 (v9v): Likewise.
255 (v9m): Likewise.
256 (v9andleon): Likewise.
257 (m8): Define.
258 (HWS_VM8): Define.
259 (HWS2_VM8): Likewise.
260 (sparc_opcode_archs): Add entry for "m8".
261 (sparc_opcodes): Add OSA2017 and M8 instructions
262 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
263 fpx{ll,ra,rl}64x,
264 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
265 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
266 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
267 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
268 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
269 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
270 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
271 ASI_CORE_SELECT_COMMIT_NHT.
272
535b785f
AM		 2732017-05-18 Alan Modra <amodra@gmail.com>
274
275 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
276 * aarch64-dis.c: Likewise.
277 * aarch64-gen.c: Likewise.
278 * aarch64-opc.c: Likewise.
279
25499ac7
MR		 2802017-05-15 Maciej W. Rozycki <macro@imgtec.com>
281 Matthew Fortune <matthew.fortune@imgtec.com>
282
283 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
284 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
285 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
286 (print_insn_arg) <OP_REG28>: Add handler.
287 (validate_insn_args) <OP_REG28>: Handle.
288 (print_mips16_insn_arg): Handle MIPS16 instructions that require
289 32-bit encoding and 9-bit immediates.
290 (print_insn_mips16): Handle MIPS16 instructions that require
291 32-bit encoding and MFC0/MTC0 operand decoding.
292 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
293 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
294 (RD_C0, WR_C0, E2, E2MT): New macros.
295 (mips16_opcodes): Add entries for MIPS16e2 instructions:
296 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
297 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
298 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
299 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
300 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
301 instructions, "swl", "swr", "sync" and its "sync_acquire",
302 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
303 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
304 regular/extended entries for original MIPS16 ISA revision
305 instructions whose extended forms are subdecoded in the MIPS16e2
306 ISA revision: "li", "sll" and "srl".
307
fdfb4752
MR		 3082017-05-15 Maciej W. Rozycki <macro@imgtec.com>
309
310 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
311 reference in CP0 move operand decoding.
312
a4f89915
MR		 3132017-05-12 Maciej W. Rozycki <macro@imgtec.com>
314
315 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
316 type to hexadecimal.
317 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
318
99e2d67a
MR		 3192017-05-11 Maciej W. Rozycki <macro@imgtec.com>
320
321 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
322 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
323 "sync_rmb" and "sync_wmb" as aliases.
324 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
325 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
326
53a346d8
CZ		 3272017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
328
329 * arc-dis.c (parse_option): Update quarkse_em option..
330 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
331 QUARKSE1.
332 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
333
f91d48de
KC		 3342017-05-03 Kito Cheng <kito.cheng@gmail.com>
335
336 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
337
43e379d7
MC		 3382017-05-01 Michael Clark <michaeljclark@mac.com>
339
340 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
341 register.
342
a4ddc54e
MR		 3432017-05-02 Maciej W. Rozycki <macro@imgtec.com>
344
345 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
346 and branches and not synthetic data instructions.
347
fe50e98c
BE		 3482017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
349
350 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
351
126124cc
CZ		 3522017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
353
354 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
355 * arc-opc.c (insert_r13el): New function.
356 (R13_EL): Define.
357 * arc-tbl.h: Add new enter/leave variants.
358
be6a24d8
CZ		 3592017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
360
361 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
362
0348fd79
MR		 3632017-04-25 Maciej W. Rozycki <macro@imgtec.com>
364
365 * mips-dis.c (print_mips_disassembler_options): Add
366 `no-aliases'.
367
6e3d1f07
MR		 3682017-04-25 Maciej W. Rozycki <macro@imgtec.com>
369
370 * mips16-opc.c (AL): New macro.
371 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
372 of "ld" and "lw" as aliases.
373
957f6b39
TC		 3742017-04-24 Tamar Christina <tamar.christina@arm.com>
375
376 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
377 arguments.
378
a8cc8a54
AM		 3792017-04-22 Alexander Fedotov <alfedotov@gmail.com>
380 Alan Modra <amodra@gmail.com>
381
382 * ppc-opc.c (ELEV): Define.
383 (vle_opcodes): Add se_rfgi and e_sc.
384 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
385 for E200Z4.
386
3ab87b68
JM		 3872017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
388
389 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
390
792f174f
NC		 3912017-04-21 Nick Clifton <nickc@redhat.com>
392
393 PR binutils/21380
394 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
395 LD3R and LD4R.
396
42742084
AM		 3972017-04-13 Alan Modra <amodra@gmail.com>
398
399 * epiphany-desc.c: Regenerate.
400 * fr30-desc.c: Regenerate.
401 * frv-desc.c: Regenerate.
402 * ip2k-desc.c: Regenerate.
403 * iq2000-desc.c: Regenerate.
404 * lm32-desc.c: Regenerate.
405 * m32c-desc.c: Regenerate.
406 * m32r-desc.c: Regenerate.
407 * mep-desc.c: Regenerate.
408 * mt-desc.c: Regenerate.
409 * or1k-desc.c: Regenerate.
410 * xc16x-desc.c: Regenerate.
411 * xstormy16-desc.c: Regenerate.
412
9a85b496
AM		 4132017-04-11 Alan Modra <amodra@gmail.com>
414
ef85eab0 415 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 416 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
417 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 418 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
419 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 420 (PPCVSX2): Define as PPC_OPCODE_POWER8.
421 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 422 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 423 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 424
62adc510
AM		 4252017-04-10 Alan Modra <amodra@gmail.com>
426
427 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
428 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
429 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
430 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
431
aa808707
PC		 4322017-04-09 Pip Cet <pipcet@gmail.com>
433
434 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
435 appropriate floating-point precision directly.
436
ac8f0f72
AM		 4372017-04-07 Alan Modra <amodra@gmail.com>
438
439 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
440 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
441 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
442 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
443 vector instructions with E6500 not PPCVEC2.
444
62ecb94c
PC		 4452017-04-06 Pip Cet <pipcet@gmail.com>
446
447 * Makefile.am: Add wasm32-dis.c.
448 * configure.ac: Add wasm32-dis.c to wasm32 target.
449 * disassemble.c: Add wasm32 disassembler code.
450 * wasm32-dis.c: New file.
451 * Makefile.in: Regenerate.
452 * configure: Regenerate.
453 * po/POTFILES.in: Regenerate.
454 * po/opcodes.pot: Regenerate.
455
f995bbe8
PA		 4562017-04-05 Pedro Alves <palves@redhat.com>
457
458 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
459 * arm-dis.c (parse_arm_disassembler_options): Constify.
460 * ppc-dis.c (powerpc_init_dialect): Constify local.
461 * vax-dis.c (parse_disassembler_options): Constify.
462
b5292032
PD		 4632017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
464
465 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
466 RISCV_GP_SYMBOL.
467
f96bd6c2
PC		 4682017-03-30 Pip Cet <pipcet@gmail.com>
469
470 * configure.ac: Add (empty) bfd_wasm32_arch target.
471 * configure: Regenerate
472 * po/opcodes.pot: Regenerate.
473
f7c514a3
JM		 4742017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
475
476 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
477 OSA2015.
478 * opcodes/sparc-opc.c (asi_table): New ASIs.
479
52be03fd
AM		 4802017-03-29 Alan Modra <amodra@gmail.com>
481
482 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
483 "raw" option.
484 (lookup_powerpc): Don't special case -1 dialect. Handle
485 PPC_OPCODE_RAW.
486 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
487 lookup_powerpc call, pass it on second.
488
9b753937
AM		 4892017-03-27 Alan Modra <amodra@gmail.com>
490
491 PR 21303
492 * ppc-dis.c (struct ppc_mopt): Comment.
493 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
494
c0c31e91
RZ		 4952017-03-27 Rinat Zelig <rinat@mellanox.com>
496
497 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
498 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
499 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
500 (insert_nps_misc_imm_offset): New function.
501 (extract_nps_misc imm_offset): New function.
502 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
503 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
504
2253c8f0
AK		 5052017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
506
507 * s390-mkopc.c (main): Remove vx2 check.
508 * s390-opc.txt: Remove vx2 instruction flags.
509
645d3342
RZ		 5102017-03-21 Rinat Zelig <rinat@mellanox.com>
511
512 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
513 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
514 (insert_nps_imm_offset): New function.
515 (extract_nps_imm_offset): New function.
516 (insert_nps_imm_entry): New function.
517 (extract_nps_imm_entry): New function.
518
4b94dd2d
AM		 5192017-03-17 Alan Modra <amodra@gmail.com>
520
521 PR 21248
522 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
523 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
524 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
525
b416fe87
KC		 5262017-03-14 Kito Cheng <kito.cheng@gmail.com>
527
528 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
529 <c.andi>: Likewise.
530 <c.addiw> Likewise.
531
03b039a5
KC		 5322017-03-14 Kito Cheng <kito.cheng@gmail.com>
533
534 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
535
2c232b83
AW		 5362017-03-13 Andrew Waterman <andrew@sifive.com>
537
538 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
539 <srl> Likewise.
540 <srai> Likewise.
541 <sra> Likewise.
542
86fa6981
L		 5432017-03-09 H.J. Lu <hongjiu.lu@intel.com>
544
545 * i386-gen.c (opcode_modifiers): Replace S with Load.
546 * i386-opc.h (S): Removed.
547 (Load): New.
548 (i386_opcode_modifier): Replace s with load.
549 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
550 and {evex}. Replace S with Load.
551 * i386-tbl.h: Regenerated.
552
c1fe188b
L		 5532017-03-09 H.J. Lu <hongjiu.lu@intel.com>
554
555 * i386-opc.tbl: Use CpuCET on rdsspq.
556 * i386-tbl.h: Regenerated.
557
4b8b687e
PB		 5582017-03-08 Peter Bergner <bergner@vnet.ibm.com>
559
560 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
561 <vsx>: Do not use PPC_OPCODE_VSX3;
562
1437d063
PB		 5632017-03-08 Peter Bergner <bergner@vnet.ibm.com>
564
565 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
566
603555e5
L		 5672017-03-06 H.J. Lu <hongjiu.lu@intel.com>
568
569 * i386-dis.c (REG_0F1E_MOD_3): New enum.
570 (MOD_0F1E_PREFIX_1): Likewise.
571 (MOD_0F38F5_PREFIX_2): Likewise.
572 (MOD_0F38F6_PREFIX_0): Likewise.
573 (RM_0F1E_MOD_3_REG_7): Likewise.
574 (PREFIX_MOD_0_0F01_REG_5): Likewise.
575 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
576 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
577 (PREFIX_0F1E): Likewise.
578 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
579 (PREFIX_0F38F5): Likewise.
580 (dis386_twobyte): Use PREFIX_0F1E.
581 (reg_table): Add REG_0F1E_MOD_3.
582 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
583 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
584 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
585 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
586 (three_byte_table): Use PREFIX_0F38F5.
587 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
588 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
589 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
590 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
591 PREFIX_MOD_3_0F01_REG_5_RM_2.
592 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
593 (cpu_flags): Add CpuCET.
594 * i386-opc.h (CpuCET): New enum.
595 (CpuUnused): Commented out.
596 (i386_cpu_flags): Add cpucet.
597 * i386-opc.tbl: Add Intel CET instructions.
598 * i386-init.h: Regenerated.
599 * i386-tbl.h: Likewise.
600
73f07bff
AM		 6012017-03-06 Alan Modra <amodra@gmail.com>
602
603 PR 21124
604 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
605 (extract_raq, extract_ras, extract_rbx): New functions.
606 (powerpc_operands): Use opposite corresponding insert function.
607 (Q_MASK): Define.
608 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
609 register restriction.
610
65b48a81
PB		 6112017-02-28 Peter Bergner <bergner@vnet.ibm.com>
612
613 * disassemble.c Include "safe-ctype.h".
614 (disassemble_init_for_target): Handle s390 init.
615 (remove_whitespace_and_extra_commas): New function.
616 (disassembler_options_cmp): Likewise.
617 * arm-dis.c: Include "libiberty.h".
618 (NUM_ELEM): Delete.
619 (regnames): Use long disassembler style names.
620 Add force-thumb and no-force-thumb options.
621 (NUM_ARM_REGNAMES): Rename from this...
622 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
623 (get_arm_regname_num_options): Delete.
624 (set_arm_regname_option): Likewise.
625 (get_arm_regnames): Likewise.
626 (parse_disassembler_options): Likewise.
627 (parse_arm_disassembler_option): Rename from this...
628 (parse_arm_disassembler_options): ...to this. Make static.
629 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
630 (print_insn): Use parse_arm_disassembler_options.
631 (disassembler_options_arm): New function.
632 (print_arm_disassembler_options): Handle updated regnames.
633 * ppc-dis.c: Include "libiberty.h".
634 (ppc_opts): Add "32" and "64" entries.
635 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
636 (powerpc_init_dialect): Add break to switch statement.
637 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
638 (disassembler_options_powerpc): New function.
639 (print_ppc_disassembler_options): Use ARRAY_SIZE.
640 Remove printing of "32" and "64".
641 * s390-dis.c: Include "libiberty.h".
642 (init_flag): Remove unneeded variable.
643 (struct s390_options_t): New structure type.
644 (options): New structure.
645 (init_disasm): Rename from this...
646 (disassemble_init_s390): ...to this. Add initializations for
647 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
648 (print_insn_s390): Delete call to init_disasm.
649 (disassembler_options_s390): New function.
650 (print_s390_disassembler_options): Print using information from
651 struct 'options'.
652 * po/opcodes.pot: Regenerate.
653
15c7c1d8
JB		 6542017-02-28 Jan Beulich <jbeulich@suse.com>
655
656 * i386-dis.c (PCMPESTR_Fixup): New.
657 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
658 (prefix_table): Use PCMPESTR_Fixup.
659 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
660 PCMPESTR_Fixup.
661 (vex_w_table): Delete VPCMPESTR{I,M} entries.
662 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
663 Split 64-bit and non-64-bit variants.
664 * opcodes/i386-tbl.h: Re-generate.
665
582e12bf
RS		 6662017-02-24 Richard Sandiford <richard.sandiford@arm.com>
667
668 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
669 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
670 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
671 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
672 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
673 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
674 (OP_SVE_V_HSD): New macros.
675 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
676 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
677 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
678 (aarch64_opcode_table): Add new SVE instructions.
679 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
680 for rotation operands. Add new SVE operands.
681 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
682 (ins_sve_quad_index): Likewise.
683 (ins_imm_rotate): Split into...
684 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
685 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
686 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
687 functions.
688 (aarch64_ins_sve_addr_ri_s4): New function.
689 (aarch64_ins_sve_quad_index): Likewise.
690 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
691 * aarch64-asm-2.c: Regenerate.
692 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
693 (ext_sve_quad_index): Likewise.
694 (ext_imm_rotate): Split into...
695 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
696 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
697 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
698 functions.
699 (aarch64_ext_sve_addr_ri_s4): New function.
700 (aarch64_ext_sve_quad_index): Likewise.
701 (aarch64_ext_sve_index): Allow quad indices.
702 (do_misc_decoding): Likewise.
703 * aarch64-dis-2.c: Regenerate.
704 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
705 aarch64_field_kinds.
706 (OPD_F_OD_MASK): Widen by one bit.
707 (OPD_F_NO_ZR): Bump accordingly.
708 (get_operand_field_width): New function.
709 * aarch64-opc.c (fields): Add new SVE fields.
710 (operand_general_constraint_met_p): Handle new SVE operands.
711 (aarch64_print_operand): Likewise.
712 * aarch64-opc-2.c: Regenerate.
713
f482d304
RS		 7142017-02-24 Richard Sandiford <richard.sandiford@arm.com>
715
716 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
717 (aarch64_feature_compnum): ...this.
718 (SIMD_V8_3): Replace with...
719 (COMPNUM): ...this.
720 (CNUM_INSN): New macro.
721 (aarch64_opcode_table): Use it for the complex number instructions.
722
7db2c588
JB		 7232017-02-24 Jan Beulich <jbeulich@suse.com>
724
725 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
726
1e9d41d4
SL		 7272017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
728
729 Add support for associating SPARC ASIs with an architecture level.
730 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
731 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
732 decoding of SPARC ASIs.
733
53c4d625
JB		 7342017-02-23 Jan Beulich <jbeulich@suse.com>
735
736 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
737 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
738
11648de5
JB		 7392017-02-21 Jan Beulich <jbeulich@suse.com>
740
741 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
742 1 (instead of to itself). Correct typo.
743
f98d33be
AW		 7442017-02-14 Andrew Waterman <andrew@sifive.com>
745
746 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
747 pseudoinstructions.
748
773fb663
RS		 7492017-02-15 Richard Sandiford <richard.sandiford@arm.com>
750
751 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
752 (aarch64_sys_reg_supported_p): Handle them.
753
cc07cda6
CZ		 7542017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
755
756 * arc-opc.c (UIMM6_20R): Define.
757 (SIMM12_20): Use above.
758 (SIMM12_20R): Define.
759 (SIMM3_5_S): Use above.
760 (UIMM7_A32_11R_S): Define.
761 (UIMM7_9_S): Use above.
762 (UIMM3_13R_S): Define.
763 (SIMM11_A32_7_S): Use above.
764 (SIMM9_8R): Define.
765 (UIMM10_A32_8_S): Use above.
766 (UIMM8_8R_S): Define.
767 (W6): Use above.
768 (arc_relax_opcodes): Use all above defines.
769
66a5a740
VG		 7702017-02-15 Vineet Gupta <vgupta@synopsys.com>
771
772 * arc-regs.h: Distinguish some of the registers different on
773 ARC700 and HS38 cpus.
774
7e0de605
AM		 7752017-02-14 Alan Modra <amodra@gmail.com>
776
777 PR 21118
778 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
779 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
780
54064fdb
AM		 7812017-02-11 Stafford Horne <shorne@gmail.com>
782 Alan Modra <amodra@gmail.com>
783
784 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
785 Use insn_bytes_value and insn_int_value directly instead. Don't
786 free allocated memory until function exit.
787
dce75bf9
NP		 7882017-02-10 Nicholas Piggin <npiggin@gmail.com>
789
790 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
791
1b7e3d2f
NC		 7922017-02-03 Nick Clifton <nickc@redhat.com>
793
794 PR 21096
795 * aarch64-opc.c (print_register_list): Ensure that the register
796 list index will fir into the tb buffer.
797 (print_register_offset_address): Likewise.
798 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
799
8ec5cf65
AD		 8002017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
801
802 PR 21056
803 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
804 instructions when the previous fetch packet ends with a 32-bit
805 instruction.
806
a1aa5e81
DD		 8072017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
808
809 * pru-opc.c: Remove vague reference to a future GDB port.
810
add3afb2
NC		 8112017-01-20 Nick Clifton <nickc@redhat.com>
812
813 * po/ga.po: Updated Irish translation.
814
c13a63b0
SN		 8152017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
816
817 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
818
9608051a
YQ		 8192017-01-13 Yao Qi <yao.qi@linaro.org>
820
821 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
822 if FETCH_DATA returns 0.
823 (m68k_scan_mask): Likewise.
824 (print_insn_m68k): Update code to handle -1 return value.
825
f622ea96
YQ		 8262017-01-13 Yao Qi <yao.qi@linaro.org>
827
828 * m68k-dis.c (enum print_insn_arg_error): New.
829 (NEXTBYTE): Replace -3 with
830 PRINT_INSN_ARG_MEMORY_ERROR.
831 (NEXTULONG): Likewise.
832 (NEXTSINGLE): Likewise.
833 (NEXTDOUBLE): Likewise.
834 (NEXTDOUBLE): Likewise.
835 (NEXTPACKED): Likewise.
836 (FETCH_ARG): Likewise.
837 (FETCH_DATA): Update comments.
838 (print_insn_arg): Update comments. Replace magic numbers with
839 enum.
840 (match_insn_m68k): Likewise.
841
620214f7
IT		 8422017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
843
844 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
845 * i386-dis-evex.h (evex_table): Updated.
846 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
847 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
848 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
849 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
850 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
851 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
852 * i386-init.h: Regenerate.
853 * i386-tbl.h: Ditto.
854
d95014a2
YQ		 8552017-01-12 Yao Qi <yao.qi@linaro.org>
856
857 * msp430-dis.c (msp430_singleoperand): Return -1 if
858 msp430dis_opcode_signed returns false.
859 (msp430_doubleoperand): Likewise.
860 (msp430_branchinstr): Return -1 if
861 msp430dis_opcode_unsigned returns false.
862 (msp430x_calla_instr): Likewise.
863 (print_insn_msp430): Likewise.
864
0ae60c3e
NC		 8652017-01-05 Nick Clifton <nickc@redhat.com>
866
867 PR 20946
868 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
869 could not be matched.
870 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
871 NULL.
872
d74d4880
SN		 8732017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
874
875 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
876 (aarch64_opcode_table): Use RCPC_INSN.
877
cc917fd9
KC		 8782017-01-03 Kito Cheng <kito.cheng@gmail.com>
879
880 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
881 extension.
882 * riscv-opcodes/all-opcodes: Likewise.
883
b52d3cfc
DP		 8842017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
885
886 * riscv-dis.c (print_insn_args): Add fall through comment.
887
f90c58d5
NC		 8882017-01-03 Nick Clifton <nickc@redhat.com>
889
890 * po/sr.po: New Serbian translation.
891 * configure.ac (ALL_LINGUAS): Add sr.
892 * configure: Regenerate.
893
f47b0d4a
AM		 8942017-01-02 Alan Modra <amodra@gmail.com>
895
896 * epiphany-desc.h: Regenerate.
897 * epiphany-opc.h: Regenerate.
898 * fr30-desc.h: Regenerate.
899 * fr30-opc.h: Regenerate.
900 * frv-desc.h: Regenerate.
901 * frv-opc.h: Regenerate.
902 * ip2k-desc.h: Regenerate.
903 * ip2k-opc.h: Regenerate.
904 * iq2000-desc.h: Regenerate.
905 * iq2000-opc.h: Regenerate.
906 * lm32-desc.h: Regenerate.
907 * lm32-opc.h: Regenerate.
908 * m32c-desc.h: Regenerate.
909 * m32c-opc.h: Regenerate.
910 * m32r-desc.h: Regenerate.
911 * m32r-opc.h: Regenerate.
912 * mep-desc.h: Regenerate.
913 * mep-opc.h: Regenerate.
914 * mt-desc.h: Regenerate.
915 * mt-opc.h: Regenerate.
916 * or1k-desc.h: Regenerate.
917 * or1k-opc.h: Regenerate.
918 * xc16x-desc.h: Regenerate.
919 * xc16x-opc.h: Regenerate.
920 * xstormy16-desc.h: Regenerate.
921 * xstormy16-opc.h: Regenerate.
922
2571583a
AM		 9232017-01-02 Alan Modra <amodra@gmail.com>
924
925 Update year range in copyright notice of all files.
926
5c1ad6b5 927For older changes see ChangeLog-2016
3499769a 928\f
5c1ad6b5 929Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 930
931Copying and distribution of this file, with or without modification,
932are permitted in any medium without royalty provided the copyright
933notice and this notice are preserved.
934
935Local Variables:
936mode: change-log
937left-margin: 8
938fill-column: 74
939version-control: never
940End:
GDB Binutils - Deliverables
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