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[gdb/testsuite] Add missing initial prompt read in multidictionary.exp
[deliverable/binutils-gdb.git] / opcodes / aarch64-opc.c
CommitLineData
a06ea964 1/* aarch64-opc.c -- AArch64 opcode support.
82704155 2 Copyright (C) 2009-2019 Free Software Foundation, Inc.
a06ea964
NC		 3 Contributed by ARM Ltd.
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
20
21#include "sysdep.h"
22#include <assert.h>
23#include <stdlib.h>
24#include <stdio.h>
2d5d5a8f 25#include "bfd_stdint.h"
a06ea964
NC		 26#include <stdarg.h>
27#include <inttypes.h>
28
29#include "opintl.h"
245d2e3f 30#include "libiberty.h"
a06ea964
NC		 31
32#include "aarch64-opc.h"
33
34#ifdef DEBUG_AARCH64
35int debug_dump = FALSE;
36#endif /* DEBUG_AARCH64 */
37
245d2e3f
RS		 38/* The enumeration strings associated with each value of a 5-bit SVE
39 pattern operand. A null entry indicates a reserved meaning. */
40const char *const aarch64_sve_pattern_array[32] = {
41 /* 0-7. */
42 "pow2",
43 "vl1",
44 "vl2",
45 "vl3",
46 "vl4",
47 "vl5",
48 "vl6",
49 "vl7",
50 /* 8-15. */
51 "vl8",
52 "vl16",
53 "vl32",
54 "vl64",
55 "vl128",
56 "vl256",
57 0,
58 0,
59 /* 16-23. */
60 0,
61 0,
62 0,
63 0,
64 0,
65 0,
66 0,
67 0,
68 /* 24-31. */
69 0,
70 0,
71 0,
72 0,
73 0,
74 "mul4",
75 "mul3",
76 "all"
77};
78
79/* The enumeration strings associated with each value of a 4-bit SVE
80 prefetch operand. A null entry indicates a reserved meaning. */
81const char *const aarch64_sve_prfop_array[16] = {
82 /* 0-7. */
83 "pldl1keep",
84 "pldl1strm",
85 "pldl2keep",
86 "pldl2strm",
87 "pldl3keep",
88 "pldl3strm",
89 0,
90 0,
91 /* 8-15. */
92 "pstl1keep",
93 "pstl1strm",
94 "pstl2keep",
95 "pstl2strm",
96 "pstl3keep",
97 "pstl3strm",
98 0,
99 0
100};
101
a06ea964
NC		 102/* Helper functions to determine which operand to be used to encode/decode
103 the size:Q fields for AdvSIMD instructions. */
104
105static inline bfd_boolean
106vector_qualifier_p (enum aarch64_opnd_qualifier qualifier)
107{
108 return ((qualifier >= AARCH64_OPND_QLF_V_8B
109 && qualifier <= AARCH64_OPND_QLF_V_1Q) ? TRUE
110 : FALSE);
111}
112
113static inline bfd_boolean
114fp_qualifier_p (enum aarch64_opnd_qualifier qualifier)
115{
116 return ((qualifier >= AARCH64_OPND_QLF_S_B
117 && qualifier <= AARCH64_OPND_QLF_S_Q) ? TRUE
118 : FALSE);
119}
120
121enum data_pattern
122{
123 DP_UNKNOWN,
124 DP_VECTOR_3SAME,
125 DP_VECTOR_LONG,
126 DP_VECTOR_WIDE,
127 DP_VECTOR_ACROSS_LANES,
128};
129
130static const char significant_operand_index [] =
131{
132 0, /* DP_UNKNOWN, by default using operand 0. */
133 0, /* DP_VECTOR_3SAME */
134 1, /* DP_VECTOR_LONG */
135 2, /* DP_VECTOR_WIDE */
136 1, /* DP_VECTOR_ACROSS_LANES */
137};
138
139/* Given a sequence of qualifiers in QUALIFIERS, determine and return
140 the data pattern.
141 N.B. QUALIFIERS is a possible sequence of qualifiers each of which
142 corresponds to one of a sequence of operands. */
143
144static enum data_pattern
145get_data_pattern (const aarch64_opnd_qualifier_seq_t qualifiers)
146{
147 if (vector_qualifier_p (qualifiers[0]) == TRUE)
148 {
149 /* e.g. v.4s, v.4s, v.4s
150 or v.4h, v.4h, v.h[3]. */
151 if (qualifiers[0] == qualifiers[1]
152 && vector_qualifier_p (qualifiers[2]) == TRUE
153 && (aarch64_get_qualifier_esize (qualifiers[0])
154 == aarch64_get_qualifier_esize (qualifiers[1]))
155 && (aarch64_get_qualifier_esize (qualifiers[0])
156 == aarch64_get_qualifier_esize (qualifiers[2])))
157 return DP_VECTOR_3SAME;
158 /* e.g. v.8h, v.8b, v.8b.
159 or v.4s, v.4h, v.h[2].
160 or v.8h, v.16b. */
161 if (vector_qualifier_p (qualifiers[1]) == TRUE
162 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
163 && (aarch64_get_qualifier_esize (qualifiers[0])
164 == aarch64_get_qualifier_esize (qualifiers[1]) << 1))
165 return DP_VECTOR_LONG;
166 /* e.g. v.8h, v.8h, v.8b. */
167 if (qualifiers[0] == qualifiers[1]
168 && vector_qualifier_p (qualifiers[2]) == TRUE
169 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
170 && (aarch64_get_qualifier_esize (qualifiers[0])
171 == aarch64_get_qualifier_esize (qualifiers[2]) << 1)
172 && (aarch64_get_qualifier_esize (qualifiers[0])
173 == aarch64_get_qualifier_esize (qualifiers[1])))
174 return DP_VECTOR_WIDE;
175 }
176 else if (fp_qualifier_p (qualifiers[0]) == TRUE)
177 {
178 /* e.g. SADDLV <V><d>, <Vn>.<T>. */
179 if (vector_qualifier_p (qualifiers[1]) == TRUE
180 && qualifiers[2] == AARCH64_OPND_QLF_NIL)
181 return DP_VECTOR_ACROSS_LANES;
182 }
183
184 return DP_UNKNOWN;
185}
186
187/* Select the operand to do the encoding/decoding of the 'size:Q' fields in
188 the AdvSIMD instructions. */
189/* N.B. it is possible to do some optimization that doesn't call
190 get_data_pattern each time when we need to select an operand. We can
191 either buffer the caculated the result or statically generate the data,
192 however, it is not obvious that the optimization will bring significant
193 benefit. */
194
195int
196aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *opcode)
197{
198 return
199 significant_operand_index [get_data_pattern (opcode->qualifiers_list[0])];
200}
201\f
202const aarch64_field fields[] =
203{
204 { 0, 0 }, /* NIL. */
205 { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
206 { 0, 4 }, /* nzcv: flag bit specifier, encoded in the "nzcv" field. */
207 { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
208 { 16, 3 }, /* abc: a:b:c bits in AdvSIMD modified immediate. */
209 { 5, 19 }, /* imm19: e.g. in CBZ. */
210 { 5, 19 }, /* immhi: e.g. in ADRP. */
211 { 29, 2 }, /* immlo: e.g. in ADRP. */
212 { 22, 2 }, /* size: in most AdvSIMD and floating-point instructions. */
213 { 10, 2 }, /* vldst_size: size field in the AdvSIMD load/store inst. */
214 { 29, 1 }, /* op: in AdvSIMD modified immediate instructions. */
215 { 30, 1 }, /* Q: in most AdvSIMD instructions. */
216 { 0, 5 }, /* Rt: in load/store instructions. */
217 { 0, 5 }, /* Rd: in many integer instructions. */
218 { 5, 5 }, /* Rn: in many integer instructions. */
219 { 10, 5 }, /* Rt2: in load/store pair instructions. */
220 { 10, 5 }, /* Ra: in fp instructions. */
221 { 5, 3 }, /* op2: in the system instructions. */
222 { 8, 4 }, /* CRm: in the system instructions. */
223 { 12, 4 }, /* CRn: in the system instructions. */
224 { 16, 3 }, /* op1: in the system instructions. */
225 { 19, 2 }, /* op0: in the system instructions. */
226 { 10, 3 }, /* imm3: in add/sub extended reg instructions. */
227 { 12, 4 }, /* cond: condition flags as a source operand. */
228 { 12, 4 }, /* opcode: in advsimd load/store instructions. */
229 { 12, 4 }, /* cmode: in advsimd modified immediate instructions. */
230 { 13, 3 }, /* asisdlso_opcode: opcode in advsimd ld/st single element. */
231 { 13, 2 }, /* len: in advsimd tbl/tbx instructions. */
232 { 16, 5 }, /* Rm: in ld/st reg offset and some integer inst. */
233 { 16, 5 }, /* Rs: in load/store exclusive instructions. */
234 { 13, 3 }, /* option: in ld/st reg offset + add/sub extended reg inst. */
235 { 12, 1 }, /* S: in load/store reg offset instructions. */
236 { 21, 2 }, /* hw: in move wide constant instructions. */
237 { 22, 2 }, /* opc: in load/store reg offset instructions. */
238 { 23, 1 }, /* opc1: in load/store reg offset instructions. */
239 { 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */
240 { 22, 2 }, /* type: floating point type field in fp data inst. */
241 { 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */
242 { 10, 6 }, /* imm6: in add/sub reg shifted instructions. */
f42f1a1d 243 { 15, 6 }, /* imm6_2: in rmif instructions. */
a06ea964 244 { 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */
f42f1a1d 245 { 0, 4 }, /* imm4_2: in rmif instructions. */
193614f2 246 { 10, 4 }, /* imm4_3: in adddg/subg instructions. */
a06ea964
NC		 247 { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
248 { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
249 { 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
250 { 12, 9 }, /* imm9: in load/store pre/post index instructions. */
251 { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
252 { 5, 14 }, /* imm14: in test bit and branch instructions. */
253 { 5, 16 }, /* imm16: in exception instructions. */
254 { 0, 26 }, /* imm26: in unconditional branch instructions. */
255 { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
256 { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
257 { 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
258 { 19, 4 }, /* immh: in advsimd shift by immediate instructions. */
3f06e550 259 { 22, 1 }, /* S: in LDRAA and LDRAB instructions. */
a06ea964
NC		 260 { 22, 1 }, /* N: in logical (immediate) instructions. */
261 { 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
262 { 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
263 { 31, 1 }, /* sf: in integer data processing instructions. */
ee804238 264 { 30, 1 }, /* lse_size: in LSE extension atomic instructions. */
a06ea964
NC		 265 { 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */
266 { 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */
267 { 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */
268 { 31, 1 }, /* b5: in the test bit and branch instructions. */
269 { 19, 5 }, /* b40: in the test bit and branch instructions. */
270 { 10, 6 }, /* scale: in the fixed-point scalar to fp converting inst. */
116b6019
RS		 271 { 4, 1 }, /* SVE_M_4: Merge/zero select, bit 4. */
272 { 14, 1 }, /* SVE_M_14: Merge/zero select, bit 14. */
273 { 16, 1 }, /* SVE_M_16: Merge/zero select, bit 16. */
e950b345 274 { 17, 1 }, /* SVE_N: SVE equivalent of N. */
f11ad6bc
RS		 275 { 0, 4 }, /* SVE_Pd: p0-p15, bits [3,0]. */
276 { 10, 3 }, /* SVE_Pg3: p0-p7, bits [12,10]. */
277 { 5, 4 }, /* SVE_Pg4_5: p0-p15, bits [8,5]. */
278 { 10, 4 }, /* SVE_Pg4_10: p0-p15, bits [13,10]. */
279 { 16, 4 }, /* SVE_Pg4_16: p0-p15, bits [19,16]. */
280 { 16, 4 }, /* SVE_Pm: p0-p15, bits [19,16]. */
281 { 5, 4 }, /* SVE_Pn: p0-p15, bits [8,5]. */
282 { 0, 4 }, /* SVE_Pt: p0-p15, bits [3,0]. */
047cd301
RS		 283 { 5, 5 }, /* SVE_Rm: SVE alternative position for Rm. */
284 { 16, 5 }, /* SVE_Rn: SVE alternative position for Rn. */
285 { 0, 5 }, /* SVE_Vd: Scalar SIMD&FP register, bits [4,0]. */
286 { 5, 5 }, /* SVE_Vm: Scalar SIMD&FP register, bits [9,5]. */
287 { 5, 5 }, /* SVE_Vn: Scalar SIMD&FP register, bits [9,5]. */
f11ad6bc
RS		 288 { 5, 5 }, /* SVE_Za_5: SVE vector register, bits [9,5]. */
289 { 16, 5 }, /* SVE_Za_16: SVE vector register, bits [20,16]. */
290 { 0, 5 }, /* SVE_Zd: SVE vector register. bits [4,0]. */
291 { 5, 5 }, /* SVE_Zm_5: SVE vector register, bits [9,5]. */
292 { 16, 5 }, /* SVE_Zm_16: SVE vector register, bits [20,16]. */
293 { 5, 5 }, /* SVE_Zn: SVE vector register, bits [9,5]. */
294 { 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
165d4950 295 { 5, 1 }, /* SVE_i1: single-bit immediate. */
582e12bf 296 { 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
116adc27
MM		 297 { 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */
298 { 19, 2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */
31e36ab3 299 { 20, 1 }, /* SVE_i2h: high bit of 2bit immediate, bits. */
e950b345 300 { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
2442d846 301 { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
e950b345
RS		 302 { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
303 { 16, 5 }, /* SVE_imm5b: secondary 5-bit immediate field. */
4df068de 304 { 16, 6 }, /* SVE_imm6: 6-bit immediate field. */
e950b345
RS		 305 { 14, 7 }, /* SVE_imm7: 7-bit immediate field. */
306 { 5, 8 }, /* SVE_imm8: 8-bit immediate field. */
307 { 5, 9 }, /* SVE_imm9: 9-bit immediate field. */
308 { 11, 6 }, /* SVE_immr: SVE equivalent of immr. */
309 { 5, 6 }, /* SVE_imms: SVE equivalent of imms. */
4df068de 310 { 10, 2 }, /* SVE_msz: 2-bit shift amount for ADR. */
245d2e3f
RS		 311 { 5, 5 }, /* SVE_pattern: vector pattern enumeration. */
312 { 0, 4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */
582e12bf
RS		 313 { 16, 1 }, /* SVE_rot1: 1-bit rotation amount. */
314 { 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
adccc507 315 { 10, 1 }, /* SVE_rot3: 1-bit rotation amount at bit 10. */
116b6019 316 { 22, 1 }, /* SVE_sz: 1-bit element size select. */
3bd82c86 317 { 17, 2 }, /* SVE_size: 2-bit element size, bits [18,17]. */
0a57e14f 318 { 30, 1 }, /* SVE_sz2: 1-bit element size select. */
116b6019 319 { 16, 4 }, /* SVE_tsz: triangular size select. */
f11ad6bc 320 { 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
116b6019
RS		 321 { 8, 2 }, /* SVE_tszl_8: triangular size select low, bits [9,8]. */
322 { 19, 2 }, /* SVE_tszl_19: triangular size select low, bits [20,19]. */
4df068de 323 { 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */
c2c4ff8d
SN		 324 { 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */
325 { 11, 2 }, /* rotate1: FCMLA immediate rotate. */
326 { 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */
327 { 12, 1 }, /* rotate3: FCADD immediate rotate. */
f42f1a1d 328 { 12, 2 }, /* SM3: Indexed element SM3 2 bits index immediate. */
6456d318 329 { 22, 1 }, /* sz: 1-bit element size select. */
a06ea964
NC		 330};
331
332enum aarch64_operand_class
333aarch64_get_operand_class (enum aarch64_opnd type)
334{
335 return aarch64_operands[type].op_class;
336}
337
338const char *
339aarch64_get_operand_name (enum aarch64_opnd type)
340{
341 return aarch64_operands[type].name;
342}
343
344/* Get operand description string.
345 This is usually for the diagnosis purpose. */
346const char *
347aarch64_get_operand_desc (enum aarch64_opnd type)
348{
349 return aarch64_operands[type].desc;
350}
351
352/* Table of all conditional affixes. */
353const aarch64_cond aarch64_conds[16] =
354{
bb7eff52
RS		 355 {{"eq", "none"}, 0x0},
356 {{"ne", "any"}, 0x1},
357 {{"cs", "hs", "nlast"}, 0x2},
358 {{"cc", "lo", "ul", "last"}, 0x3},
359 {{"mi", "first"}, 0x4},
360 {{"pl", "nfrst"}, 0x5},
a06ea964
NC		 361 {{"vs"}, 0x6},
362 {{"vc"}, 0x7},
bb7eff52
RS		 363 {{"hi", "pmore"}, 0x8},
364 {{"ls", "plast"}, 0x9},
365 {{"ge", "tcont"}, 0xa},
366 {{"lt", "tstop"}, 0xb},
a06ea964
NC		 367 {{"gt"}, 0xc},
368 {{"le"}, 0xd},
369 {{"al"}, 0xe},
370 {{"nv"}, 0xf},
371};
372
373const aarch64_cond *
374get_cond_from_value (aarch64_insn value)
375{
376 assert (value < 16);
377 return &aarch64_conds[(unsigned int) value];
378}
379
380const aarch64_cond *
381get_inverted_cond (const aarch64_cond *cond)
382{
383 return &aarch64_conds[cond->value ^ 0x1];
384}
385
386/* Table describing the operand extension/shifting operators; indexed by
387 enum aarch64_modifier_kind.
388
389 The value column provides the most common values for encoding modifiers,
390 which enables table-driven encoding/decoding for the modifiers. */
391const struct aarch64_name_value_pair aarch64_operand_modifiers [] =
392{
393 {"none", 0x0},
394 {"msl", 0x0},
395 {"ror", 0x3},
396 {"asr", 0x2},
397 {"lsr", 0x1},
398 {"lsl", 0x0},
399 {"uxtb", 0x0},
400 {"uxth", 0x1},
401 {"uxtw", 0x2},
402 {"uxtx", 0x3},
403 {"sxtb", 0x4},
404 {"sxth", 0x5},
405 {"sxtw", 0x6},
406 {"sxtx", 0x7},
2442d846 407 {"mul", 0x0},
98907a70 408 {"mul vl", 0x0},
a06ea964
NC		 409 {NULL, 0},
410};
411
412enum aarch64_modifier_kind
413aarch64_get_operand_modifier (const struct aarch64_name_value_pair *desc)
414{
415 return desc - aarch64_operand_modifiers;
416}
417
418aarch64_insn
419aarch64_get_operand_modifier_value (enum aarch64_modifier_kind kind)
420{
421 return aarch64_operand_modifiers[kind].value;
422}
423
424enum aarch64_modifier_kind
425aarch64_get_operand_modifier_from_value (aarch64_insn value,
426 bfd_boolean extend_p)
427{
428 if (extend_p == TRUE)
429 return AARCH64_MOD_UXTB + value;
430 else
431 return AARCH64_MOD_LSL - value;
432}
433
434bfd_boolean
435aarch64_extend_operator_p (enum aarch64_modifier_kind kind)
436{
437 return (kind > AARCH64_MOD_LSL && kind <= AARCH64_MOD_SXTX)
438 ? TRUE : FALSE;
439}
440
441static inline bfd_boolean
442aarch64_shift_operator_p (enum aarch64_modifier_kind kind)
443{
444 return (kind >= AARCH64_MOD_ROR && kind <= AARCH64_MOD_LSL)
445 ? TRUE : FALSE;
446}
447
448const struct aarch64_name_value_pair aarch64_barrier_options[16] =
449{
450 { "#0x00", 0x0 },
451 { "oshld", 0x1 },
452 { "oshst", 0x2 },
453 { "osh", 0x3 },
454 { "#0x04", 0x4 },
455 { "nshld", 0x5 },
456 { "nshst", 0x6 },
457 { "nsh", 0x7 },
458 { "#0x08", 0x8 },
459 { "ishld", 0x9 },
460 { "ishst", 0xa },
461 { "ish", 0xb },
462 { "#0x0c", 0xc },
463 { "ld", 0xd },
464 { "st", 0xe },
465 { "sy", 0xf },
466};
467
9ed608f9
MW		 468/* Table describing the operands supported by the aliases of the HINT
469 instruction.
470
471 The name column is the operand that is accepted for the alias. The value
472 column is the hint number of the alias. The list of operands is terminated
473 by NULL in the name column. */
474
475const struct aarch64_name_value_pair aarch64_hint_options[] =
476{
ff605452
SD		 477 /* BTI. This is also the F_DEFAULT entry for AARCH64_OPND_BTI_TARGET. */
478 { " ", HINT_ENCODE (HINT_OPD_F_NOPRINT, 0x20) },
479 { "csync", HINT_OPD_CSYNC }, /* PSB CSYNC. */
480 { "c", HINT_OPD_C }, /* BTI C. */
481 { "j", HINT_OPD_J }, /* BTI J. */
482 { "jc", HINT_OPD_JC }, /* BTI JC. */
483 { NULL, HINT_OPD_NULL },
9ed608f9
MW		 484};
485
a32c3ff8 486/* op -> op: load = 0 instruction = 1 store = 2
a06ea964
NC		 487 l -> level: 1-3
488 t -> temporal: temporal (retained) = 0 non-temporal (streaming) = 1 */
a32c3ff8 489#define B(op,l,t) (((op) << 3) | (((l) - 1) << 1) | (t))
a06ea964
NC		 490const struct aarch64_name_value_pair aarch64_prfops[32] =
491{
492 { "pldl1keep", B(0, 1, 0) },
493 { "pldl1strm", B(0, 1, 1) },
494 { "pldl2keep", B(0, 2, 0) },
495 { "pldl2strm", B(0, 2, 1) },
496 { "pldl3keep", B(0, 3, 0) },
497 { "pldl3strm", B(0, 3, 1) },
a1ccaec9
YZ		 498 { NULL, 0x06 },
499 { NULL, 0x07 },
a32c3ff8
NC		 500 { "plil1keep", B(1, 1, 0) },
501 { "plil1strm", B(1, 1, 1) },
502 { "plil2keep", B(1, 2, 0) },
503 { "plil2strm", B(1, 2, 1) },
504 { "plil3keep", B(1, 3, 0) },
505 { "plil3strm", B(1, 3, 1) },
a1ccaec9
YZ		 506 { NULL, 0x0e },
507 { NULL, 0x0f },
a32c3ff8
NC		 508 { "pstl1keep", B(2, 1, 0) },
509 { "pstl1strm", B(2, 1, 1) },
510 { "pstl2keep", B(2, 2, 0) },
511 { "pstl2strm", B(2, 2, 1) },
512 { "pstl3keep", B(2, 3, 0) },
513 { "pstl3strm", B(2, 3, 1) },
a1ccaec9
YZ		 514 { NULL, 0x16 },
515 { NULL, 0x17 },
516 { NULL, 0x18 },
517 { NULL, 0x19 },
518 { NULL, 0x1a },
519 { NULL, 0x1b },
520 { NULL, 0x1c },
521 { NULL, 0x1d },
522 { NULL, 0x1e },
523 { NULL, 0x1f },
a06ea964
NC		 524};
525#undef B
526\f
527/* Utilities on value constraint. */
528
529static inline int
530value_in_range_p (int64_t value, int low, int high)
531{
532 return (value >= low && value <= high) ? 1 : 0;
533}
534
98907a70 535/* Return true if VALUE is a multiple of ALIGN. */
a06ea964
NC		 536static inline int
537value_aligned_p (int64_t value, int align)
538{
98907a70 539 return (value % align) == 0;
a06ea964
NC		 540}
541
542/* A signed value fits in a field. */
543static inline int
544value_fit_signed_field_p (int64_t value, unsigned width)
545{
546 assert (width < 32);
547 if (width < sizeof (value) * 8)
548 {
549 int64_t lim = (int64_t)1 << (width - 1);
550 if (value >= -lim && value < lim)
551 return 1;
552 }
553 return 0;
554}
555
556/* An unsigned value fits in a field. */
557static inline int
558value_fit_unsigned_field_p (int64_t value, unsigned width)
559{
560 assert (width < 32);
561 if (width < sizeof (value) * 8)
562 {
563 int64_t lim = (int64_t)1 << width;
564 if (value >= 0 && value < lim)
565 return 1;
566 }
567 return 0;
568}
569
570/* Return 1 if OPERAND is SP or WSP. */
571int
572aarch64_stack_pointer_p (const aarch64_opnd_info *operand)
573{
574 return ((aarch64_get_operand_class (operand->type)
575 == AARCH64_OPND_CLASS_INT_REG)
576 && operand_maybe_stack_pointer (aarch64_operands + operand->type)
577 && operand->reg.regno == 31);
578}
579
580/* Return 1 if OPERAND is XZR or WZP. */
581int
582aarch64_zero_register_p (const aarch64_opnd_info *operand)
583{
584 return ((aarch64_get_operand_class (operand->type)
585 == AARCH64_OPND_CLASS_INT_REG)
586 && !operand_maybe_stack_pointer (aarch64_operands + operand->type)
587 && operand->reg.regno == 31);
588}
589
590/* Return true if the operand *OPERAND that has the operand code
591 OPERAND->TYPE and been qualified by OPERAND->QUALIFIER can be also
592 qualified by the qualifier TARGET. */
593
594static inline int
595operand_also_qualified_p (const struct aarch64_opnd_info *operand,
596 aarch64_opnd_qualifier_t target)
597{
598 switch (operand->qualifier)
599 {
600 case AARCH64_OPND_QLF_W:
601 if (target == AARCH64_OPND_QLF_WSP && aarch64_stack_pointer_p (operand))
602 return 1;
603 break;
604 case AARCH64_OPND_QLF_X:
605 if (target == AARCH64_OPND_QLF_SP && aarch64_stack_pointer_p (operand))
606 return 1;
607 break;
608 case AARCH64_OPND_QLF_WSP:
609 if (target == AARCH64_OPND_QLF_W
610 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
611 return 1;
612 break;
613 case AARCH64_OPND_QLF_SP:
614 if (target == AARCH64_OPND_QLF_X
615 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
616 return 1;
617 break;
618 default:
619 break;
620 }
621
622 return 0;
623}
624
625/* Given qualifier sequence list QSEQ_LIST and the known qualifier KNOWN_QLF
626 for operand KNOWN_IDX, return the expected qualifier for operand IDX.
627
628 Return NIL if more than one expected qualifiers are found. */
629
630aarch64_opnd_qualifier_t
631aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *qseq_list,
632 int idx,
633 const aarch64_opnd_qualifier_t known_qlf,
634 int known_idx)
635{
636 int i, saved_i;
637
638 /* Special case.
639
640 When the known qualifier is NIL, we have to assume that there is only
641 one qualifier sequence in the *QSEQ_LIST and return the corresponding
642 qualifier directly. One scenario is that for instruction
643 PRFM <prfop>, [<Xn|SP>, #:lo12:<symbol>]
644 which has only one possible valid qualifier sequence
645 NIL, S_D
646 the caller may pass NIL in KNOWN_QLF to obtain S_D so that it can
647 determine the correct relocation type (i.e. LDST64_LO12) for PRFM.
648
649 Because the qualifier NIL has dual roles in the qualifier sequence:
650 it can mean no qualifier for the operand, or the qualifer sequence is
651 not in use (when all qualifiers in the sequence are NILs), we have to
652 handle this special case here. */
653 if (known_qlf == AARCH64_OPND_NIL)
654 {
655 assert (qseq_list[0][known_idx] == AARCH64_OPND_NIL);
656 return qseq_list[0][idx];
657 }
658
659 for (i = 0, saved_i = -1; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
660 {
661 if (qseq_list[i][known_idx] == known_qlf)
662 {
663 if (saved_i != -1)
664 /* More than one sequences are found to have KNOWN_QLF at
665 KNOWN_IDX. */
666 return AARCH64_OPND_NIL;
667 saved_i = i;
668 }
669 }
670
671 return qseq_list[saved_i][idx];
672}
673
674enum operand_qualifier_kind
675{
676 OQK_NIL,
677 OQK_OPD_VARIANT,
678 OQK_VALUE_IN_RANGE,
679 OQK_MISC,
680};
681
682/* Operand qualifier description. */
683struct operand_qualifier_data
684{
685 /* The usage of the three data fields depends on the qualifier kind. */
686 int data0;
687 int data1;
688 int data2;
689 /* Description. */
690 const char *desc;
691 /* Kind. */
692 enum operand_qualifier_kind kind;
693};
694
695/* Indexed by the operand qualifier enumerators. */
696struct operand_qualifier_data aarch64_opnd_qualifiers[] =
697{
698 {0, 0, 0, "NIL", OQK_NIL},
699
700 /* Operand variant qualifiers.
701 First 3 fields:
702 element size, number of elements and common value for encoding. */
703
704 {4, 1, 0x0, "w", OQK_OPD_VARIANT},
705 {8, 1, 0x1, "x", OQK_OPD_VARIANT},
706 {4, 1, 0x0, "wsp", OQK_OPD_VARIANT},
707 {8, 1, 0x1, "sp", OQK_OPD_VARIANT},
708
709 {1, 1, 0x0, "b", OQK_OPD_VARIANT},
710 {2, 1, 0x1, "h", OQK_OPD_VARIANT},
711 {4, 1, 0x2, "s", OQK_OPD_VARIANT},
712 {8, 1, 0x3, "d", OQK_OPD_VARIANT},
713 {16, 1, 0x4, "q", OQK_OPD_VARIANT},
66e6f0b7 714 {4, 1, 0x0, "4b", OQK_OPD_VARIANT},
a06ea964 715
a3b3345a 716 {1, 4, 0x0, "4b", OQK_OPD_VARIANT},
a06ea964
NC		 717 {1, 8, 0x0, "8b", OQK_OPD_VARIANT},
718 {1, 16, 0x1, "16b", OQK_OPD_VARIANT},
3067d3b9 719 {2, 2, 0x0, "2h", OQK_OPD_VARIANT},
a06ea964
NC		 720 {2, 4, 0x2, "4h", OQK_OPD_VARIANT},
721 {2, 8, 0x3, "8h", OQK_OPD_VARIANT},
722 {4, 2, 0x4, "2s", OQK_OPD_VARIANT},
723 {4, 4, 0x5, "4s", OQK_OPD_VARIANT},
724 {8, 1, 0x6, "1d", OQK_OPD_VARIANT},
725 {8, 2, 0x7, "2d", OQK_OPD_VARIANT},
726 {16, 1, 0x8, "1q", OQK_OPD_VARIANT},
727
d50c751e
RS		 728 {0, 0, 0, "z", OQK_OPD_VARIANT},
729 {0, 0, 0, "m", OQK_OPD_VARIANT},
730
fb3265b3
SD		 731 /* Qualifier for scaled immediate for Tag granule (stg,st2g,etc). */
732 {16, 0, 0, "tag", OQK_OPD_VARIANT},
733
a06ea964
NC		 734 /* Qualifiers constraining the value range.
735 First 3 fields:
736 Lower bound, higher bound, unused. */
737
a6a51754 738 {0, 15, 0, "CR", OQK_VALUE_IN_RANGE},
a06ea964
NC		 739 {0, 7, 0, "imm_0_7" , OQK_VALUE_IN_RANGE},
740 {0, 15, 0, "imm_0_15", OQK_VALUE_IN_RANGE},
741 {0, 31, 0, "imm_0_31", OQK_VALUE_IN_RANGE},
742 {0, 63, 0, "imm_0_63", OQK_VALUE_IN_RANGE},
743 {1, 32, 0, "imm_1_32", OQK_VALUE_IN_RANGE},
744 {1, 64, 0, "imm_1_64", OQK_VALUE_IN_RANGE},
745
746 /* Qualifiers for miscellaneous purpose.
747 First 3 fields:
748 unused, unused and unused. */
749
750 {0, 0, 0, "lsl", 0},
751 {0, 0, 0, "msl", 0},
752
753 {0, 0, 0, "retrieving", 0},
754};
755
756static inline bfd_boolean
757operand_variant_qualifier_p (aarch64_opnd_qualifier_t qualifier)
758{
759 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_OPD_VARIANT)
760 ? TRUE : FALSE;
761}
762
763static inline bfd_boolean
764qualifier_value_in_range_constraint_p (aarch64_opnd_qualifier_t qualifier)
765{
766 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_VALUE_IN_RANGE)
767 ? TRUE : FALSE;
768}
769
770const char*
771aarch64_get_qualifier_name (aarch64_opnd_qualifier_t qualifier)
772{
773 return aarch64_opnd_qualifiers[qualifier].desc;
774}
775
776/* Given an operand qualifier, return the expected data element size
777 of a qualified operand. */
778unsigned char
779aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t qualifier)
780{
781 assert (operand_variant_qualifier_p (qualifier) == TRUE);
782 return aarch64_opnd_qualifiers[qualifier].data0;
783}
784
785unsigned char
786aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t qualifier)
787{
788 assert (operand_variant_qualifier_p (qualifier) == TRUE);
789 return aarch64_opnd_qualifiers[qualifier].data1;
790}
791
792aarch64_insn
793aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t qualifier)
794{
795 assert (operand_variant_qualifier_p (qualifier) == TRUE);
796 return aarch64_opnd_qualifiers[qualifier].data2;
797}
798
799static int
800get_lower_bound (aarch64_opnd_qualifier_t qualifier)
801{
802 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
803 return aarch64_opnd_qualifiers[qualifier].data0;
804}
805
806static int
807get_upper_bound (aarch64_opnd_qualifier_t qualifier)
808{
809 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
810 return aarch64_opnd_qualifiers[qualifier].data1;
811}
812
813#ifdef DEBUG_AARCH64
814void
815aarch64_verbose (const char *str, ...)
816{
817 va_list ap;
818 va_start (ap, str);
819 printf ("#### ");
820 vprintf (str, ap);
821 printf ("\n");
822 va_end (ap);
823}
824
825static inline void
826dump_qualifier_sequence (const aarch64_opnd_qualifier_t *qualifier)
827{
828 int i;
829 printf ("#### \t");
830 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i, ++qualifier)
831 printf ("%s,", aarch64_get_qualifier_name (*qualifier));
832 printf ("\n");
833}
834
835static void
836dump_match_qualifiers (const struct aarch64_opnd_info *opnd,
837 const aarch64_opnd_qualifier_t *qualifier)
838{
839 int i;
840 aarch64_opnd_qualifier_t curr[AARCH64_MAX_OPND_NUM];
841
842 aarch64_verbose ("dump_match_qualifiers:");
843 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
844 curr[i] = opnd[i].qualifier;
845 dump_qualifier_sequence (curr);
846 aarch64_verbose ("against");
847 dump_qualifier_sequence (qualifier);
848}
849#endif /* DEBUG_AARCH64 */
850
a68f4cd2
TC		 851/* This function checks if the given instruction INSN is a destructive
852 instruction based on the usage of the registers. It does not recognize
853 unary destructive instructions. */
854bfd_boolean
855aarch64_is_destructive_by_operands (const aarch64_opcode *opcode)
856{
857 int i = 0;
858 const enum aarch64_opnd *opnds = opcode->operands;
859
860 if (opnds[0] == AARCH64_OPND_NIL)
861 return FALSE;
862
863 while (opnds[++i] != AARCH64_OPND_NIL)
864 if (opnds[i] == opnds[0])
865 return TRUE;
866
867 return FALSE;
868}
869
a06ea964
NC		 870/* TODO improve this, we can have an extra field at the runtime to
871 store the number of operands rather than calculating it every time. */
872
873int
874aarch64_num_of_operands (const aarch64_opcode *opcode)
875{
876 int i = 0;
877 const enum aarch64_opnd *opnds = opcode->operands;
878 while (opnds[i++] != AARCH64_OPND_NIL)
879 ;
880 --i;
881 assert (i >= 0 && i <= AARCH64_MAX_OPND_NUM);
882 return i;
883}
884
885/* Find the best matched qualifier sequence in *QUALIFIERS_LIST for INST.
886 If succeeds, fill the found sequence in *RET, return 1; otherwise return 0.
887
888 N.B. on the entry, it is very likely that only some operands in *INST
889 have had their qualifiers been established.
890
891 If STOP_AT is not -1, the function will only try to match
892 the qualifier sequence for operands before and including the operand
893 of index STOP_AT; and on success *RET will only be filled with the first
894 (STOP_AT+1) qualifiers.
895
896 A couple examples of the matching algorithm:
897
898 X,W,NIL should match
899 X,W,NIL
900
901 NIL,NIL should match
902 X ,NIL
903
904 Apart from serving the main encoding routine, this can also be called
905 during or after the operand decoding. */
906
907int
908aarch64_find_best_match (const aarch64_inst *inst,
909 const aarch64_opnd_qualifier_seq_t *qualifiers_list,
910 int stop_at, aarch64_opnd_qualifier_t *ret)
911{
912 int found = 0;
913 int i, num_opnds;
914 const aarch64_opnd_qualifier_t *qualifiers;
915
916 num_opnds = aarch64_num_of_operands (inst->opcode);
917 if (num_opnds == 0)
918 {
919 DEBUG_TRACE ("SUCCEED: no operand");
920 return 1;
921 }
922
923 if (stop_at < 0 || stop_at >= num_opnds)
924 stop_at = num_opnds - 1;
925
926 /* For each pattern. */
927 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
928 {
929 int j;
930 qualifiers = *qualifiers_list;
931
932 /* Start as positive. */
933 found = 1;
934
935 DEBUG_TRACE ("%d", i);
936#ifdef DEBUG_AARCH64
937 if (debug_dump)
938 dump_match_qualifiers (inst->operands, qualifiers);
939#endif
940
941 /* Most opcodes has much fewer patterns in the list.
942 First NIL qualifier indicates the end in the list. */
943 if (empty_qualifier_sequence_p (qualifiers) == TRUE)
944 {
945 DEBUG_TRACE_IF (i == 0, "SUCCEED: empty qualifier list");
946 if (i)
947 found = 0;
948 break;
949 }
950
951 for (j = 0; j < num_opnds && j <= stop_at; ++j, ++qualifiers)
952 {
953 if (inst->operands[j].qualifier == AARCH64_OPND_QLF_NIL)
954 {
955 /* Either the operand does not have qualifier, or the qualifier
956 for the operand needs to be deduced from the qualifier
957 sequence.
958 In the latter case, any constraint checking related with
959 the obtained qualifier should be done later in
960 operand_general_constraint_met_p. */
961 continue;
962 }
963 else if (*qualifiers != inst->operands[j].qualifier)
964 {
965 /* Unless the target qualifier can also qualify the operand
966 (which has already had a non-nil qualifier), non-equal
967 qualifiers are generally un-matched. */
968 if (operand_also_qualified_p (inst->operands + j, *qualifiers))
969 continue;
970 else
971 {
972 found = 0;
973 break;
974 }
975 }
976 else
977 continue; /* Equal qualifiers are certainly matched. */
978 }
979
980 /* Qualifiers established. */
981 if (found == 1)
982 break;
983 }
984
985 if (found == 1)
986 {
987 /* Fill the result in *RET. */
988 int j;
989 qualifiers = *qualifiers_list;
990
991 DEBUG_TRACE ("complete qualifiers using list %d", i);
992#ifdef DEBUG_AARCH64
993 if (debug_dump)
994 dump_qualifier_sequence (qualifiers);
995#endif
996
997 for (j = 0; j <= stop_at; ++j, ++qualifiers)
998 ret[j] = *qualifiers;
999 for (; j < AARCH64_MAX_OPND_NUM; ++j)
1000 ret[j] = AARCH64_OPND_QLF_NIL;
1001
1002 DEBUG_TRACE ("SUCCESS");
1003 return 1;
1004 }
1005
1006 DEBUG_TRACE ("FAIL");
1007 return 0;
1008}
1009
1010/* Operand qualifier matching and resolving.
1011
1012 Return 1 if the operand qualifier(s) in *INST match one of the qualifier
1013 sequences in INST->OPCODE->qualifiers_list; otherwise return 0.
1014
1015 if UPDATE_P == TRUE, update the qualifier(s) in *INST after the matching
1016 succeeds. */
1017
1018static int
1019match_operands_qualifier (aarch64_inst *inst, bfd_boolean update_p)
1020{
4989adac 1021 int i, nops;
a06ea964
NC		 1022 aarch64_opnd_qualifier_seq_t qualifiers;
1023
1024 if (!aarch64_find_best_match (inst, inst->opcode->qualifiers_list, -1,
1025 qualifiers))
1026 {
1027 DEBUG_TRACE ("matching FAIL");
1028 return 0;
1029 }
1030
4989adac
RS		 1031 if (inst->opcode->flags & F_STRICT)
1032 {
1033 /* Require an exact qualifier match, even for NIL qualifiers. */
1034 nops = aarch64_num_of_operands (inst->opcode);
1035 for (i = 0; i < nops; ++i)
1036 if (inst->operands[i].qualifier != qualifiers[i])
1037 return FALSE;
1038 }
1039
a06ea964
NC		 1040 /* Update the qualifiers. */
1041 if (update_p == TRUE)
1042 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
1043 {
1044 if (inst->opcode->operands[i] == AARCH64_OPND_NIL)
1045 break;
1046 DEBUG_TRACE_IF (inst->operands[i].qualifier != qualifiers[i],
1047 "update %s with %s for operand %d",
1048 aarch64_get_qualifier_name (inst->operands[i].qualifier),
1049 aarch64_get_qualifier_name (qualifiers[i]), i);
1050 inst->operands[i].qualifier = qualifiers[i];
1051 }
1052
1053 DEBUG_TRACE ("matching SUCCESS");
1054 return 1;
1055}
1056
1057/* Return TRUE if VALUE is a wide constant that can be moved into a general
1058 register by MOVZ.
1059
1060 IS32 indicates whether value is a 32-bit immediate or not.
1061 If SHIFT_AMOUNT is not NULL, on the return of TRUE, the logical left shift
1062 amount will be returned in *SHIFT_AMOUNT. */
1063
1064bfd_boolean
1065aarch64_wide_constant_p (int64_t value, int is32, unsigned int *shift_amount)
1066{
1067 int amount;
1068
1069 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1070
1071 if (is32)
1072 {
1073 /* Allow all zeros or all ones in top 32-bits, so that
1074 32-bit constant expressions like ~0x80000000 are
1075 permitted. */
1076 uint64_t ext = value;
1077 if (ext >> 32 != 0 && ext >> 32 != (uint64_t) 0xffffffff)
1078 /* Immediate out of range. */
1079 return FALSE;
1080 value &= (int64_t) 0xffffffff;
1081 }
1082
1083 /* first, try movz then movn */
1084 amount = -1;
1085 if ((value & ((int64_t) 0xffff << 0)) == value)
1086 amount = 0;
1087 else if ((value & ((int64_t) 0xffff << 16)) == value)
1088 amount = 16;
1089 else if (!is32 && (value & ((int64_t) 0xffff << 32)) == value)
1090 amount = 32;
1091 else if (!is32 && (value & ((int64_t) 0xffff << 48)) == value)
1092 amount = 48;
1093
1094 if (amount == -1)
1095 {
1096 DEBUG_TRACE ("exit FALSE with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1097 return FALSE;
1098 }
1099
1100 if (shift_amount != NULL)
1101 *shift_amount = amount;
1102
1103 DEBUG_TRACE ("exit TRUE with amount %d", amount);
1104
1105 return TRUE;
1106}
1107
1108/* Build the accepted values for immediate logical SIMD instructions.
1109
1110 The standard encodings of the immediate value are:
1111 N imms immr SIMD size R S
1112 1 ssssss rrrrrr 64 UInt(rrrrrr) UInt(ssssss)
1113 0 0sssss 0rrrrr 32 UInt(rrrrr) UInt(sssss)
1114 0 10ssss 00rrrr 16 UInt(rrrr) UInt(ssss)
1115 0 110sss 000rrr 8 UInt(rrr) UInt(sss)
1116 0 1110ss 0000rr 4 UInt(rr) UInt(ss)
1117 0 11110s 00000r 2 UInt(r) UInt(s)
1118 where all-ones value of S is reserved.
1119
1120 Let's call E the SIMD size.
1121
1122 The immediate value is: S+1 bits '1' rotated to the right by R.
1123
1124 The total of valid encodings is 64*63 + 32*31 + ... + 2*1 = 5334
1125 (remember S != E - 1). */
1126
1127#define TOTAL_IMM_NB 5334
1128
1129typedef struct
1130{
1131 uint64_t imm;
1132 aarch64_insn encoding;
1133} simd_imm_encoding;
1134
1135static simd_imm_encoding simd_immediates[TOTAL_IMM_NB];
1136
1137static int
1138simd_imm_encoding_cmp(const void *i1, const void *i2)
1139{
1140 const simd_imm_encoding *imm1 = (const simd_imm_encoding *)i1;
1141 const simd_imm_encoding *imm2 = (const simd_imm_encoding *)i2;
1142
1143 if (imm1->imm < imm2->imm)
1144 return -1;
1145 if (imm1->imm > imm2->imm)
1146 return +1;
1147 return 0;
1148}
1149
1150/* immediate bitfield standard encoding
1151 imm13<12> imm13<5:0> imm13<11:6> SIMD size R S
1152 1 ssssss rrrrrr 64 rrrrrr ssssss
1153 0 0sssss 0rrrrr 32 rrrrr sssss
1154 0 10ssss 00rrrr 16 rrrr ssss
1155 0 110sss 000rrr 8 rrr sss
1156 0 1110ss 0000rr 4 rr ss
1157 0 11110s 00000r 2 r s */
1158static inline int
1159encode_immediate_bitfield (int is64, uint32_t s, uint32_t r)
1160{
1161 return (is64 << 12) | (r << 6) | s;
1162}
1163
1164static void
1165build_immediate_table (void)
1166{
1167 uint32_t log_e, e, s, r, s_mask;
1168 uint64_t mask, imm;
1169 int nb_imms;
1170 int is64;
1171
1172 nb_imms = 0;
1173 for (log_e = 1; log_e <= 6; log_e++)
1174 {
1175 /* Get element size. */
1176 e = 1u << log_e;
1177 if (log_e == 6)
1178 {
1179 is64 = 1;
1180 mask = 0xffffffffffffffffull;
1181 s_mask = 0;
1182 }
1183 else
1184 {
1185 is64 = 0;
1186 mask = (1ull << e) - 1;
1187 /* log_e s_mask
1188 1 ((1 << 4) - 1) << 2 = 111100
1189 2 ((1 << 3) - 1) << 3 = 111000
1190 3 ((1 << 2) - 1) << 4 = 110000
1191 4 ((1 << 1) - 1) << 5 = 100000
1192 5 ((1 << 0) - 1) << 6 = 000000 */
1193 s_mask = ((1u << (5 - log_e)) - 1) << (log_e + 1);
1194 }
1195 for (s = 0; s < e - 1; s++)
1196 for (r = 0; r < e; r++)
1197 {
1198 /* s+1 consecutive bits to 1 (s < 63) */
1199 imm = (1ull << (s + 1)) - 1;
1200 /* rotate right by r */
1201 if (r != 0)
1202 imm = (imm >> r) | ((imm << (e - r)) & mask);
1203 /* replicate the constant depending on SIMD size */
1204 switch (log_e)
1205 {
1206 case 1: imm = (imm << 2) | imm;
1a0670f3 1207 /* Fall through. */
a06ea964 1208 case 2: imm = (imm << 4) | imm;
1a0670f3 1209 /* Fall through. */
a06ea964 1210 case 3: imm = (imm << 8) | imm;
1a0670f3 1211 /* Fall through. */
a06ea964 1212 case 4: imm = (imm << 16) | imm;
1a0670f3 1213 /* Fall through. */
a06ea964 1214 case 5: imm = (imm << 32) | imm;
1a0670f3 1215 /* Fall through. */
a06ea964
NC		 1216 case 6: break;
1217 default: abort ();
1218 }
1219 simd_immediates[nb_imms].imm = imm;
1220 simd_immediates[nb_imms].encoding =
1221 encode_immediate_bitfield(is64, s | s_mask, r);
1222 nb_imms++;
1223 }
1224 }
1225 assert (nb_imms == TOTAL_IMM_NB);
1226 qsort(simd_immediates, nb_imms,
1227 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1228}
1229
1230/* Return TRUE if VALUE is a valid logical immediate, i.e. bitmask, that can
1231 be accepted by logical (immediate) instructions
1232 e.g. ORR <Xd|SP>, <Xn>, #<imm>.
1233
42408347 1234 ESIZE is the number of bytes in the decoded immediate value.
a06ea964
NC		 1235 If ENCODING is not NULL, on the return of TRUE, the standard encoding for
1236 VALUE will be returned in *ENCODING. */
1237
1238bfd_boolean
42408347 1239aarch64_logical_immediate_p (uint64_t value, int esize, aarch64_insn *encoding)
a06ea964
NC		 1240{
1241 simd_imm_encoding imm_enc;
1242 const simd_imm_encoding *imm_encoding;
1243 static bfd_boolean initialized = FALSE;
42408347
RS		 1244 uint64_t upper;
1245 int i;
a06ea964 1246
957f6b39
TC		 1247 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 "), esize: %d", value,
1248 value, esize);
a06ea964 1249
535b785f 1250 if (!initialized)
a06ea964
NC		 1251 {
1252 build_immediate_table ();
1253 initialized = TRUE;
1254 }
1255
42408347
RS		 1256 /* Allow all zeros or all ones in top bits, so that
1257 constant expressions like ~1 are permitted. */
1258 upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
1259 if ((value & ~upper) != value && (value | upper) != value)
1260 return FALSE;
7e105031 1261
42408347
RS		 1262 /* Replicate to a full 64-bit value. */
1263 value &= ~upper;
1264 for (i = esize * 8; i < 64; i *= 2)
1265 value |= (value << i);
a06ea964
NC		 1266
1267 imm_enc.imm = value;
1268 imm_encoding = (const simd_imm_encoding *)
1269 bsearch(&imm_enc, simd_immediates, TOTAL_IMM_NB,
1270 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1271 if (imm_encoding == NULL)
1272 {
1273 DEBUG_TRACE ("exit with FALSE");
1274 return FALSE;
1275 }
1276 if (encoding != NULL)
1277 *encoding = imm_encoding->encoding;
1278 DEBUG_TRACE ("exit with TRUE");
1279 return TRUE;
1280}
1281
1282/* If 64-bit immediate IMM is in the format of
1283 "aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh",
1284 where a, b, c, d, e, f, g and h are independently 0 or 1, return an integer
1285 of value "abcdefgh". Otherwise return -1. */
1286int
1287aarch64_shrink_expanded_imm8 (uint64_t imm)
1288{
1289 int i, ret;
1290 uint32_t byte;
1291
1292 ret = 0;
1293 for (i = 0; i < 8; i++)
1294 {
1295 byte = (imm >> (8 * i)) & 0xff;
1296 if (byte == 0xff)
1297 ret |= 1 << i;
1298 else if (byte != 0x00)
1299 return -1;
1300 }
1301 return ret;
1302}
1303
1304/* Utility inline functions for operand_general_constraint_met_p. */
1305
1306static inline void
1307set_error (aarch64_operand_error *mismatch_detail,
1308 enum aarch64_operand_error_kind kind, int idx,
1309 const char* error)
1310{
1311 if (mismatch_detail == NULL)
1312 return;
1313 mismatch_detail->kind = kind;
1314 mismatch_detail->index = idx;
1315 mismatch_detail->error = error;
1316}
1317
4e50d5f8
YZ		 1318static inline void
1319set_syntax_error (aarch64_operand_error *mismatch_detail, int idx,
1320 const char* error)
1321{
1322 if (mismatch_detail == NULL)
1323 return;
1324 set_error (mismatch_detail, AARCH64_OPDE_SYNTAX_ERROR, idx, error);
1325}
1326
a06ea964
NC		 1327static inline void
1328set_out_of_range_error (aarch64_operand_error *mismatch_detail,
1329 int idx, int lower_bound, int upper_bound,
1330 const char* error)
1331{
1332 if (mismatch_detail == NULL)
1333 return;
1334 set_error (mismatch_detail, AARCH64_OPDE_OUT_OF_RANGE, idx, error);
1335 mismatch_detail->data[0] = lower_bound;
1336 mismatch_detail->data[1] = upper_bound;
1337}
1338
1339static inline void
1340set_imm_out_of_range_error (aarch64_operand_error *mismatch_detail,
1341 int idx, int lower_bound, int upper_bound)
1342{
1343 if (mismatch_detail == NULL)
1344 return;
1345 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1346 _("immediate value"));
1347}
1348
1349static inline void
1350set_offset_out_of_range_error (aarch64_operand_error *mismatch_detail,
1351 int idx, int lower_bound, int upper_bound)
1352{
1353 if (mismatch_detail == NULL)
1354 return;
1355 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1356 _("immediate offset"));
1357}
1358
1359static inline void
1360set_regno_out_of_range_error (aarch64_operand_error *mismatch_detail,
1361 int idx, int lower_bound, int upper_bound)
1362{
1363 if (mismatch_detail == NULL)
1364 return;
1365 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1366 _("register number"));
1367}
1368
1369static inline void
1370set_elem_idx_out_of_range_error (aarch64_operand_error *mismatch_detail,
1371 int idx, int lower_bound, int upper_bound)
1372{
1373 if (mismatch_detail == NULL)
1374 return;
1375 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1376 _("register element index"));
1377}
1378
1379static inline void
1380set_sft_amount_out_of_range_error (aarch64_operand_error *mismatch_detail,
1381 int idx, int lower_bound, int upper_bound)
1382{
1383 if (mismatch_detail == NULL)
1384 return;
1385 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1386 _("shift amount"));
1387}
1388
2442d846
RS		 1389/* Report that the MUL modifier in operand IDX should be in the range
1390 [LOWER_BOUND, UPPER_BOUND]. */
1391static inline void
1392set_multiplier_out_of_range_error (aarch64_operand_error *mismatch_detail,
1393 int idx, int lower_bound, int upper_bound)
1394{
1395 if (mismatch_detail == NULL)
1396 return;
1397 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1398 _("multiplier"));
1399}
1400
a06ea964
NC		 1401static inline void
1402set_unaligned_error (aarch64_operand_error *mismatch_detail, int idx,
1403 int alignment)
1404{
1405 if (mismatch_detail == NULL)
1406 return;
1407 set_error (mismatch_detail, AARCH64_OPDE_UNALIGNED, idx, NULL);
1408 mismatch_detail->data[0] = alignment;
1409}
1410
1411static inline void
1412set_reg_list_error (aarch64_operand_error *mismatch_detail, int idx,
1413 int expected_num)
1414{
1415 if (mismatch_detail == NULL)
1416 return;
1417 set_error (mismatch_detail, AARCH64_OPDE_REG_LIST, idx, NULL);
1418 mismatch_detail->data[0] = expected_num;
1419}
1420
1421static inline void
1422set_other_error (aarch64_operand_error *mismatch_detail, int idx,
1423 const char* error)
1424{
1425 if (mismatch_detail == NULL)
1426 return;
1427 set_error (mismatch_detail, AARCH64_OPDE_OTHER_ERROR, idx, error);
1428}
1429
1430/* General constraint checking based on operand code.
1431
1432 Return 1 if OPNDS[IDX] meets the general constraint of operand code TYPE
1433 as the IDXth operand of opcode OPCODE. Otherwise return 0.
1434
1435 This function has to be called after the qualifiers for all operands
1436 have been resolved.
1437
1438 Mismatching error message is returned in *MISMATCH_DETAIL upon request,
1439 i.e. when MISMATCH_DETAIL is non-NULL. This avoids the generation
1440 of error message during the disassembling where error message is not
1441 wanted. We avoid the dynamic construction of strings of error messages
1442 here (i.e. in libopcodes), as it is costly and complicated; instead, we
1443 use a combination of error code, static string and some integer data to
1444 represent an error. */
1445
1446static int
1447operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
1448 enum aarch64_opnd type,
1449 const aarch64_opcode *opcode,
1450 aarch64_operand_error *mismatch_detail)
1451{
e950b345 1452 unsigned num, modifiers, shift;
a06ea964 1453 unsigned char size;
4df068de 1454 int64_t imm, min_value, max_value;
e950b345 1455 uint64_t uvalue, mask;
a06ea964
NC		 1456 const aarch64_opnd_info *opnd = opnds + idx;
1457 aarch64_opnd_qualifier_t qualifier = opnd->qualifier;
1458
1459 assert (opcode->operands[idx] == opnd->type && opnd->type == type);
1460
1461 switch (aarch64_operands[type].op_class)
1462 {
1463 case AARCH64_OPND_CLASS_INT_REG:
ee804238
JW		 1464 /* Check pair reg constraints for cas* instructions. */
1465 if (type == AARCH64_OPND_PAIRREG)
1466 {
1467 assert (idx == 1 || idx == 3);
1468 if (opnds[idx - 1].reg.regno % 2 != 0)
1469 {
1470 set_syntax_error (mismatch_detail, idx - 1,
1471 _("reg pair must start from even reg"));
1472 return 0;
1473 }
1474 if (opnds[idx].reg.regno != opnds[idx - 1].reg.regno + 1)
1475 {
1476 set_syntax_error (mismatch_detail, idx,
1477 _("reg pair must be contiguous"));
1478 return 0;
1479 }
1480 break;
1481 }
1482
a06ea964
NC		 1483 /* <Xt> may be optional in some IC and TLBI instructions. */
1484 if (type == AARCH64_OPND_Rt_SYS)
1485 {
1486 assert (idx == 1 && (aarch64_get_operand_class (opnds[0].type)
1487 == AARCH64_OPND_CLASS_SYSTEM));
ea2deeec
MW		 1488 if (opnds[1].present
1489 && !aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
a06ea964
NC		 1490 {
1491 set_other_error (mismatch_detail, idx, _("extraneous register"));
1492 return 0;
1493 }
ea2deeec
MW		 1494 if (!opnds[1].present
1495 && aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
a06ea964
NC		 1496 {
1497 set_other_error (mismatch_detail, idx, _("missing register"));
1498 return 0;
1499 }
1500 }
1501 switch (qualifier)
1502 {
1503 case AARCH64_OPND_QLF_WSP:
1504 case AARCH64_OPND_QLF_SP:
1505 if (!aarch64_stack_pointer_p (opnd))
1506 {
1507 set_other_error (mismatch_detail, idx,
1508 _("stack pointer register expected"));
1509 return 0;
1510 }
1511 break;
1512 default:
1513 break;
1514 }
1515 break;
1516
f11ad6bc
RS		 1517 case AARCH64_OPND_CLASS_SVE_REG:
1518 switch (type)
1519 {
582e12bf
RS		 1520 case AARCH64_OPND_SVE_Zm3_INDEX:
1521 case AARCH64_OPND_SVE_Zm3_22_INDEX:
116adc27 1522 case AARCH64_OPND_SVE_Zm3_11_INDEX:
31e36ab3 1523 case AARCH64_OPND_SVE_Zm4_11_INDEX:
582e12bf
RS		 1524 case AARCH64_OPND_SVE_Zm4_INDEX:
1525 size = get_operand_fields_width (get_operand_from_code (type));
1526 shift = get_operand_specific_data (&aarch64_operands[type]);
1527 mask = (1 << shift) - 1;
1528 if (opnd->reg.regno > mask)
1529 {
1530 assert (mask == 7 || mask == 15);
1531 set_other_error (mismatch_detail, idx,
1532 mask == 15
1533 ? _("z0-z15 expected")
1534 : _("z0-z7 expected"));
1535 return 0;
1536 }
1537 mask = (1 << (size - shift)) - 1;
1538 if (!value_in_range_p (opnd->reglane.index, 0, mask))
1539 {
1540 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, mask);
1541 return 0;
1542 }
1543 break;
1544
f11ad6bc
RS		 1545 case AARCH64_OPND_SVE_Zn_INDEX:
1546 size = aarch64_get_qualifier_esize (opnd->qualifier);
1547 if (!value_in_range_p (opnd->reglane.index, 0, 64 / size - 1))
1548 {
1549 set_elem_idx_out_of_range_error (mismatch_detail, idx,
1550 0, 64 / size - 1);
1551 return 0;
1552 }
1553 break;
1554
1555 case AARCH64_OPND_SVE_ZnxN:
1556 case AARCH64_OPND_SVE_ZtxN:
1557 if (opnd->reglist.num_regs != get_opcode_dependent_value (opcode))
1558 {
1559 set_other_error (mismatch_detail, idx,
1560 _("invalid register list"));
1561 return 0;
1562 }
1563 break;
1564
1565 default:
1566 break;
1567 }
1568 break;
1569
1570 case AARCH64_OPND_CLASS_PRED_REG:
1571 if (opnd->reg.regno >= 8
1572 && get_operand_fields_width (get_operand_from_code (type)) == 3)
1573 {
1574 set_other_error (mismatch_detail, idx, _("p0-p7 expected"));
1575 return 0;
1576 }
1577 break;
1578
68a64283
YZ		 1579 case AARCH64_OPND_CLASS_COND:
1580 if (type == AARCH64_OPND_COND1
1581 && (opnds[idx].cond->value & 0xe) == 0xe)
1582 {
1583 /* Not allow AL or NV. */
1584 set_syntax_error (mismatch_detail, idx, NULL);
1585 }
1586 break;
1587
a06ea964
NC		 1588 case AARCH64_OPND_CLASS_ADDRESS:
1589 /* Check writeback. */
1590 switch (opcode->iclass)
1591 {
1592 case ldst_pos:
1593 case ldst_unscaled:
1594 case ldstnapair_offs:
1595 case ldstpair_off:
1596 case ldst_unpriv:
1597 if (opnd->addr.writeback == 1)
1598 {
4e50d5f8
YZ		 1599 set_syntax_error (mismatch_detail, idx,
1600 _("unexpected address writeback"));
a06ea964
NC		 1601 return 0;
1602 }
1603 break;
3f06e550
SN		 1604 case ldst_imm10:
1605 if (opnd->addr.writeback == 1 && opnd->addr.preind != 1)
1606 {
1607 set_syntax_error (mismatch_detail, idx,
1608 _("unexpected address writeback"));
1609 return 0;
1610 }
1611 break;
a06ea964
NC		 1612 case ldst_imm9:
1613 case ldstpair_indexed:
1614 case asisdlsep:
1615 case asisdlsop:
1616 if (opnd->addr.writeback == 0)
1617 {
4e50d5f8
YZ		 1618 set_syntax_error (mismatch_detail, idx,
1619 _("address writeback expected"));
a06ea964
NC		 1620 return 0;
1621 }
1622 break;
1623 default:
1624 assert (opnd->addr.writeback == 0);
1625 break;
1626 }
1627 switch (type)
1628 {
1629 case AARCH64_OPND_ADDR_SIMM7:
1630 /* Scaled signed 7 bits immediate offset. */
1631 /* Get the size of the data element that is accessed, which may be
1632 different from that of the source register size,
1633 e.g. in strb/ldrb. */
1634 size = aarch64_get_qualifier_esize (opnd->qualifier);
1635 if (!value_in_range_p (opnd->addr.offset.imm, -64 * size, 63 * size))
1636 {
1637 set_offset_out_of_range_error (mismatch_detail, idx,
1638 -64 * size, 63 * size);
1639 return 0;
1640 }
1641 if (!value_aligned_p (opnd->addr.offset.imm, size))
1642 {
1643 set_unaligned_error (mismatch_detail, idx, size);
1644 return 0;
1645 }
1646 break;
f42f1a1d 1647 case AARCH64_OPND_ADDR_OFFSET:
a06ea964
NC		 1648 case AARCH64_OPND_ADDR_SIMM9:
1649 /* Unscaled signed 9 bits immediate offset. */
1650 if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
1651 {
1652 set_offset_out_of_range_error (mismatch_detail, idx, -256, 255);
1653 return 0;
1654 }
1655 break;
1656
1657 case AARCH64_OPND_ADDR_SIMM9_2:
1658 /* Unscaled signed 9 bits immediate offset, which has to be negative
1659 or unaligned. */
1660 size = aarch64_get_qualifier_esize (qualifier);
1661 if ((value_in_range_p (opnd->addr.offset.imm, 0, 255)
1662 && !value_aligned_p (opnd->addr.offset.imm, size))
1663 || value_in_range_p (opnd->addr.offset.imm, -256, -1))
1664 return 1;
1665 set_other_error (mismatch_detail, idx,
1666 _("negative or unaligned offset expected"));
1667 return 0;
1668
3f06e550
SN		 1669 case AARCH64_OPND_ADDR_SIMM10:
1670 /* Scaled signed 10 bits immediate offset. */
1671 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4088))
1672 {
1673 set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4088);
1674 return 0;
1675 }
1676 if (!value_aligned_p (opnd->addr.offset.imm, 8))
1677 {
1678 set_unaligned_error (mismatch_detail, idx, 8);
1679 return 0;
1680 }
1681 break;
1682
fb3265b3
SD		 1683 case AARCH64_OPND_ADDR_SIMM11:
1684 /* Signed 11 bits immediate offset (multiple of 16). */
1685 if (!value_in_range_p (opnd->addr.offset.imm, -1024, 1008))
1686 {
1687 set_offset_out_of_range_error (mismatch_detail, idx, -1024, 1008);
1688 return 0;
1689 }
1690
1691 if (!value_aligned_p (opnd->addr.offset.imm, 16))
1692 {
1693 set_unaligned_error (mismatch_detail, idx, 16);
1694 return 0;
1695 }
1696 break;
1697
1698 case AARCH64_OPND_ADDR_SIMM13:
1699 /* Signed 13 bits immediate offset (multiple of 16). */
1700 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4080))
1701 {
1702 set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4080);
1703 return 0;
1704 }
1705
1706 if (!value_aligned_p (opnd->addr.offset.imm, 16))
1707 {
1708 set_unaligned_error (mismatch_detail, idx, 16);
1709 return 0;
1710 }
1711 break;
1712
a06ea964
NC		 1713 case AARCH64_OPND_SIMD_ADDR_POST:
1714 /* AdvSIMD load/store multiple structures, post-index. */
1715 assert (idx == 1);
1716 if (opnd->addr.offset.is_reg)
1717 {
1718 if (value_in_range_p (opnd->addr.offset.regno, 0, 30))
1719 return 1;
1720 else
1721 {
1722 set_other_error (mismatch_detail, idx,
1723 _("invalid register offset"));
1724 return 0;
1725 }
1726 }
1727 else
1728 {
1729 const aarch64_opnd_info *prev = &opnds[idx-1];
1730 unsigned num_bytes; /* total number of bytes transferred. */
1731 /* The opcode dependent area stores the number of elements in
1732 each structure to be loaded/stored. */
1733 int is_ld1r = get_opcode_dependent_value (opcode) == 1;
1734 if (opcode->operands[0] == AARCH64_OPND_LVt_AL)
1735 /* Special handling of loading single structure to all lane. */
1736 num_bytes = (is_ld1r ? 1 : prev->reglist.num_regs)
1737 * aarch64_get_qualifier_esize (prev->qualifier);
1738 else
1739 num_bytes = prev->reglist.num_regs
1740 * aarch64_get_qualifier_esize (prev->qualifier)
1741 * aarch64_get_qualifier_nelem (prev->qualifier);
1742 if ((int) num_bytes != opnd->addr.offset.imm)
1743 {
1744 set_other_error (mismatch_detail, idx,
1745 _("invalid post-increment amount"));
1746 return 0;
1747 }
1748 }
1749 break;
1750
1751 case AARCH64_OPND_ADDR_REGOFF:
1752 /* Get the size of the data element that is accessed, which may be
1753 different from that of the source register size,
1754 e.g. in strb/ldrb. */
1755 size = aarch64_get_qualifier_esize (opnd->qualifier);
1756 /* It is either no shift or shift by the binary logarithm of SIZE. */
1757 if (opnd->shifter.amount != 0
1758 && opnd->shifter.amount != (int)get_logsz (size))
1759 {
1760 set_other_error (mismatch_detail, idx,
1761 _("invalid shift amount"));
1762 return 0;
1763 }
1764 /* Only UXTW, LSL, SXTW and SXTX are the accepted extending
1765 operators. */
1766 switch (opnd->shifter.kind)
1767 {
1768 case AARCH64_MOD_UXTW:
1769 case AARCH64_MOD_LSL:
1770 case AARCH64_MOD_SXTW:
1771 case AARCH64_MOD_SXTX: break;
1772 default:
1773 set_other_error (mismatch_detail, idx,
1774 _("invalid extend/shift operator"));
1775 return 0;
1776 }
1777 break;
1778
1779 case AARCH64_OPND_ADDR_UIMM12:
1780 imm = opnd->addr.offset.imm;
1781 /* Get the size of the data element that is accessed, which may be
1782 different from that of the source register size,
1783 e.g. in strb/ldrb. */
1784 size = aarch64_get_qualifier_esize (qualifier);
1785 if (!value_in_range_p (opnd->addr.offset.imm, 0, 4095 * size))
1786 {
1787 set_offset_out_of_range_error (mismatch_detail, idx,
1788 0, 4095 * size);
1789 return 0;
1790 }
9de794e1 1791 if (!value_aligned_p (opnd->addr.offset.imm, size))
a06ea964
NC		 1792 {
1793 set_unaligned_error (mismatch_detail, idx, size);
1794 return 0;
1795 }
1796 break;
1797
1798 case AARCH64_OPND_ADDR_PCREL14:
1799 case AARCH64_OPND_ADDR_PCREL19:
1800 case AARCH64_OPND_ADDR_PCREL21:
1801 case AARCH64_OPND_ADDR_PCREL26:
1802 imm = opnd->imm.value;
1803 if (operand_need_shift_by_two (get_operand_from_code (type)))
1804 {
1805 /* The offset value in a PC-relative branch instruction is alway
1806 4-byte aligned and is encoded without the lowest 2 bits. */
1807 if (!value_aligned_p (imm, 4))
1808 {
1809 set_unaligned_error (mismatch_detail, idx, 4);
1810 return 0;
1811 }
1812 /* Right shift by 2 so that we can carry out the following check
1813 canonically. */
1814 imm >>= 2;
1815 }
1816 size = get_operand_fields_width (get_operand_from_code (type));
1817 if (!value_fit_signed_field_p (imm, size))
1818 {
1819 set_other_error (mismatch_detail, idx,
1820 _("immediate out of range"));
1821 return 0;
1822 }
1823 break;
1824
98907a70
RS		 1825 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
1826 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
1827 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
1828 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
1829 min_value = -8;
1830 max_value = 7;
1831 sve_imm_offset_vl:
1832 assert (!opnd->addr.offset.is_reg);
1833 assert (opnd->addr.preind);
1834 num = 1 + get_operand_specific_data (&aarch64_operands[type]);
1835 min_value *= num;
1836 max_value *= num;
1837 if ((opnd->addr.offset.imm != 0 && !opnd->shifter.operator_present)
1838 || (opnd->shifter.operator_present
1839 && opnd->shifter.kind != AARCH64_MOD_MUL_VL))
1840 {
1841 set_other_error (mismatch_detail, idx,
1842 _("invalid addressing mode"));
1843 return 0;
1844 }
1845 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1846 {
1847 set_offset_out_of_range_error (mismatch_detail, idx,
1848 min_value, max_value);
1849 return 0;
1850 }
1851 if (!value_aligned_p (opnd->addr.offset.imm, num))
1852 {
1853 set_unaligned_error (mismatch_detail, idx, num);
1854 return 0;
1855 }
1856 break;
1857
1858 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
1859 min_value = -32;
1860 max_value = 31;
1861 goto sve_imm_offset_vl;
1862
1863 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
1864 min_value = -256;
1865 max_value = 255;
1866 goto sve_imm_offset_vl;
1867
4df068de
RS		 1868 case AARCH64_OPND_SVE_ADDR_RI_U6:
1869 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
1870 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
1871 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
1872 min_value = 0;
1873 max_value = 63;
1874 sve_imm_offset:
1875 assert (!opnd->addr.offset.is_reg);
1876 assert (opnd->addr.preind);
1877 num = 1 << get_operand_specific_data (&aarch64_operands[type]);
1878 min_value *= num;
1879 max_value *= num;
1880 if (opnd->shifter.operator_present
1881 || opnd->shifter.amount_present)
1882 {
1883 set_other_error (mismatch_detail, idx,
1884 _("invalid addressing mode"));
1885 return 0;
1886 }
1887 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1888 {
1889 set_offset_out_of_range_error (mismatch_detail, idx,
1890 min_value, max_value);
1891 return 0;
1892 }
1893 if (!value_aligned_p (opnd->addr.offset.imm, num))
1894 {
1895 set_unaligned_error (mismatch_detail, idx, num);
1896 return 0;
1897 }
1898 break;
1899
582e12bf
RS		 1900 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
1901 min_value = -8;
1902 max_value = 7;
1903 goto sve_imm_offset;
1904
c469c864
MM		 1905 case AARCH64_OPND_SVE_ADDR_ZX:
1906 /* Everything is already ensured by parse_operands or
1907 aarch64_ext_sve_addr_rr_lsl (because this is a very specific
1908 argument type). */
1909 assert (opnd->addr.offset.is_reg);
1910 assert (opnd->addr.preind);
1911 assert ((aarch64_operands[type].flags & OPD_F_NO_ZR) == 0);
1912 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
1913 assert (opnd->shifter.operator_present == 0);
1914 break;
1915
c8d59609 1916 case AARCH64_OPND_SVE_ADDR_R:
4df068de
RS		 1917 case AARCH64_OPND_SVE_ADDR_RR:
1918 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
1919 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
1920 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
1921 case AARCH64_OPND_SVE_ADDR_RX:
1922 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
1923 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
1924 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
1925 case AARCH64_OPND_SVE_ADDR_RZ:
1926 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
1927 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
1928 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
1929 modifiers = 1 << AARCH64_MOD_LSL;
1930 sve_rr_operand:
1931 assert (opnd->addr.offset.is_reg);
1932 assert (opnd->addr.preind);
1933 if ((aarch64_operands[type].flags & OPD_F_NO_ZR) != 0
1934 && opnd->addr.offset.regno == 31)
1935 {
1936 set_other_error (mismatch_detail, idx,
1937 _("index register xzr is not allowed"));
1938 return 0;
1939 }
1940 if (((1 << opnd->shifter.kind) & modifiers) == 0
1941 || (opnd->shifter.amount
1942 != get_operand_specific_data (&aarch64_operands[type])))
1943 {
1944 set_other_error (mismatch_detail, idx,
1945 _("invalid addressing mode"));
1946 return 0;
1947 }
1948 break;
1949
1950 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
1951 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
1952 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
1953 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
1954 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
1955 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
1956 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
1957 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
1958 modifiers = (1 << AARCH64_MOD_SXTW) | (1 << AARCH64_MOD_UXTW);
1959 goto sve_rr_operand;
1960
1961 case AARCH64_OPND_SVE_ADDR_ZI_U5:
1962 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
1963 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
1964 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
1965 min_value = 0;
1966 max_value = 31;
1967 goto sve_imm_offset;
1968
1969 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
1970 modifiers = 1 << AARCH64_MOD_LSL;
1971 sve_zz_operand:
1972 assert (opnd->addr.offset.is_reg);
1973 assert (opnd->addr.preind);
1974 if (((1 << opnd->shifter.kind) & modifiers) == 0
1975 || opnd->shifter.amount < 0
1976 || opnd->shifter.amount > 3)
1977 {
1978 set_other_error (mismatch_detail, idx,
1979 _("invalid addressing mode"));
1980 return 0;
1981 }
1982 break;
1983
1984 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
1985 modifiers = (1 << AARCH64_MOD_SXTW);
1986 goto sve_zz_operand;
1987
1988 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
1989 modifiers = 1 << AARCH64_MOD_UXTW;
1990 goto sve_zz_operand;
1991
a06ea964
NC		 1992 default:
1993 break;
1994 }
1995 break;
1996
1997 case AARCH64_OPND_CLASS_SIMD_REGLIST:
dab26bf4
RS		 1998 if (type == AARCH64_OPND_LEt)
1999 {
2000 /* Get the upper bound for the element index. */
2001 num = 16 / aarch64_get_qualifier_esize (qualifier) - 1;
2002 if (!value_in_range_p (opnd->reglist.index, 0, num))
2003 {
2004 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
2005 return 0;
2006 }
2007 }
a06ea964
NC		 2008 /* The opcode dependent area stores the number of elements in
2009 each structure to be loaded/stored. */
2010 num = get_opcode_dependent_value (opcode);
2011 switch (type)
2012 {
2013 case AARCH64_OPND_LVt:
2014 assert (num >= 1 && num <= 4);
2015 /* Unless LD1/ST1, the number of registers should be equal to that
2016 of the structure elements. */
2017 if (num != 1 && opnd->reglist.num_regs != num)
2018 {
2019 set_reg_list_error (mismatch_detail, idx, num);
2020 return 0;
2021 }
2022 break;
2023 case AARCH64_OPND_LVt_AL:
2024 case AARCH64_OPND_LEt:
2025 assert (num >= 1 && num <= 4);
2026 /* The number of registers should be equal to that of the structure
2027 elements. */
2028 if (opnd->reglist.num_regs != num)
2029 {
2030 set_reg_list_error (mismatch_detail, idx, num);
2031 return 0;
2032 }
2033 break;
2034 default:
2035 break;
2036 }
2037 break;
2038
2039 case AARCH64_OPND_CLASS_IMMEDIATE:
2040 /* Constraint check on immediate operand. */
2041 imm = opnd->imm.value;
2042 /* E.g. imm_0_31 constrains value to be 0..31. */
2043 if (qualifier_value_in_range_constraint_p (qualifier)
2044 && !value_in_range_p (imm, get_lower_bound (qualifier),
2045 get_upper_bound (qualifier)))
2046 {
2047 set_imm_out_of_range_error (mismatch_detail, idx,
2048 get_lower_bound (qualifier),
2049 get_upper_bound (qualifier));
2050 return 0;
2051 }
2052
2053 switch (type)
2054 {
2055 case AARCH64_OPND_AIMM:
2056 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2057 {
2058 set_other_error (mismatch_detail, idx,
2059 _("invalid shift operator"));
2060 return 0;
2061 }
2062 if (opnd->shifter.amount != 0 && opnd->shifter.amount != 12)
2063 {
2064 set_other_error (mismatch_detail, idx,
ab3b8fcf 2065 _("shift amount must be 0 or 12"));
a06ea964
NC		 2066 return 0;
2067 }
2068 if (!value_fit_unsigned_field_p (opnd->imm.value, 12))
2069 {
2070 set_other_error (mismatch_detail, idx,
2071 _("immediate out of range"));
2072 return 0;
2073 }
2074 break;
2075
2076 case AARCH64_OPND_HALF:
2077 assert (idx == 1 && opnds[0].type == AARCH64_OPND_Rd);
2078 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2079 {
2080 set_other_error (mismatch_detail, idx,
2081 _("invalid shift operator"));
2082 return 0;
2083 }
2084 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2085 if (!value_aligned_p (opnd->shifter.amount, 16))
2086 {
2087 set_other_error (mismatch_detail, idx,
ab3b8fcf 2088 _("shift amount must be a multiple of 16"));
a06ea964
NC		 2089 return 0;
2090 }
2091 if (!value_in_range_p (opnd->shifter.amount, 0, size * 8 - 16))
2092 {
2093 set_sft_amount_out_of_range_error (mismatch_detail, idx,
2094 0, size * 8 - 16);
2095 return 0;
2096 }
2097 if (opnd->imm.value < 0)
2098 {
2099 set_other_error (mismatch_detail, idx,
2100 _("negative immediate value not allowed"));
2101 return 0;
2102 }
2103 if (!value_fit_unsigned_field_p (opnd->imm.value, 16))
2104 {
2105 set_other_error (mismatch_detail, idx,
2106 _("immediate out of range"));
2107 return 0;
2108 }
2109 break;
2110
2111 case AARCH64_OPND_IMM_MOV:
2112 {
42408347 2113 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
a06ea964
NC		 2114 imm = opnd->imm.value;
2115 assert (idx == 1);
2116 switch (opcode->op)
2117 {
2118 case OP_MOV_IMM_WIDEN:
2119 imm = ~imm;
1a0670f3 2120 /* Fall through. */
a06ea964 2121 case OP_MOV_IMM_WIDE:
42408347 2122 if (!aarch64_wide_constant_p (imm, esize == 4, NULL))
a06ea964
NC		 2123 {
2124 set_other_error (mismatch_detail, idx,
2125 _("immediate out of range"));
2126 return 0;
2127 }
2128 break;
2129 case OP_MOV_IMM_LOG:
42408347 2130 if (!aarch64_logical_immediate_p (imm, esize, NULL))
a06ea964
NC		 2131 {
2132 set_other_error (mismatch_detail, idx,
2133 _("immediate out of range"));
2134 return 0;
2135 }
2136 break;
2137 default:
2138 assert (0);
2139 return 0;
2140 }
2141 }
2142 break;
2143
2144 case AARCH64_OPND_NZCV:
2145 case AARCH64_OPND_CCMP_IMM:
2146 case AARCH64_OPND_EXCEPTION:
b83b4b13 2147 case AARCH64_OPND_TME_UIMM16:
a06ea964 2148 case AARCH64_OPND_UIMM4:
193614f2 2149 case AARCH64_OPND_UIMM4_ADDG:
a06ea964
NC		 2150 case AARCH64_OPND_UIMM7:
2151 case AARCH64_OPND_UIMM3_OP1:
2152 case AARCH64_OPND_UIMM3_OP2:
e950b345
RS		 2153 case AARCH64_OPND_SVE_UIMM3:
2154 case AARCH64_OPND_SVE_UIMM7:
2155 case AARCH64_OPND_SVE_UIMM8:
2156 case AARCH64_OPND_SVE_UIMM8_53:
a06ea964
NC		 2157 size = get_operand_fields_width (get_operand_from_code (type));
2158 assert (size < 32);
2159 if (!value_fit_unsigned_field_p (opnd->imm.value, size))
2160 {
2161 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2162 (1 << size) - 1);
2163 return 0;
2164 }
2165 break;
2166
193614f2
SD		 2167 case AARCH64_OPND_UIMM10:
2168 /* Scaled unsigned 10 bits immediate offset. */
2169 if (!value_in_range_p (opnd->imm.value, 0, 1008))
2170 {
2171 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1008);
2172 return 0;
2173 }
2174
2175 if (!value_aligned_p (opnd->imm.value, 16))
2176 {
2177 set_unaligned_error (mismatch_detail, idx, 16);
2178 return 0;
2179 }
2180 break;
2181
e950b345
RS		 2182 case AARCH64_OPND_SIMM5:
2183 case AARCH64_OPND_SVE_SIMM5:
2184 case AARCH64_OPND_SVE_SIMM5B:
2185 case AARCH64_OPND_SVE_SIMM6:
2186 case AARCH64_OPND_SVE_SIMM8:
2187 size = get_operand_fields_width (get_operand_from_code (type));
2188 assert (size < 32);
2189 if (!value_fit_signed_field_p (opnd->imm.value, size))
2190 {
2191 set_imm_out_of_range_error (mismatch_detail, idx,
2192 -(1 << (size - 1)),
2193 (1 << (size - 1)) - 1);
2194 return 0;
2195 }
2196 break;
2197
a06ea964 2198 case AARCH64_OPND_WIDTH:
d685192a 2199 assert (idx > 1 && opnds[idx-1].type == AARCH64_OPND_IMM
a06ea964
NC		 2200 && opnds[0].type == AARCH64_OPND_Rd);
2201 size = get_upper_bound (qualifier);
2202 if (opnd->imm.value + opnds[idx-1].imm.value > size)
2203 /* lsb+width <= reg.size */
2204 {
2205 set_imm_out_of_range_error (mismatch_detail, idx, 1,
2206 size - opnds[idx-1].imm.value);
2207 return 0;
2208 }
2209 break;
2210
2211 case AARCH64_OPND_LIMM:
e950b345 2212 case AARCH64_OPND_SVE_LIMM:
42408347
RS		 2213 {
2214 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2215 uint64_t uimm = opnd->imm.value;
2216 if (opcode->op == OP_BIC)
2217 uimm = ~uimm;
535b785f 2218 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
42408347
RS		 2219 {
2220 set_other_error (mismatch_detail, idx,
2221 _("immediate out of range"));
2222 return 0;
2223 }
2224 }
a06ea964
NC		 2225 break;
2226
2227 case AARCH64_OPND_IMM0:
2228 case AARCH64_OPND_FPIMM0:
2229 if (opnd->imm.value != 0)
2230 {
2231 set_other_error (mismatch_detail, idx,
2232 _("immediate zero expected"));
2233 return 0;
2234 }
2235 break;
2236
c2c4ff8d
SN		 2237 case AARCH64_OPND_IMM_ROT1:
2238 case AARCH64_OPND_IMM_ROT2:
582e12bf 2239 case AARCH64_OPND_SVE_IMM_ROT2:
c2c4ff8d
SN		 2240 if (opnd->imm.value != 0
2241 && opnd->imm.value != 90
2242 && opnd->imm.value != 180
2243 && opnd->imm.value != 270)
2244 {
2245 set_other_error (mismatch_detail, idx,
2246 _("rotate expected to be 0, 90, 180 or 270"));
2247 return 0;
2248 }
2249 break;
2250
2251 case AARCH64_OPND_IMM_ROT3:
582e12bf 2252 case AARCH64_OPND_SVE_IMM_ROT1:
adccc507 2253 case AARCH64_OPND_SVE_IMM_ROT3:
c2c4ff8d
SN		 2254 if (opnd->imm.value != 90 && opnd->imm.value != 270)
2255 {
2256 set_other_error (mismatch_detail, idx,
2257 _("rotate expected to be 90 or 270"));
2258 return 0;
2259 }
2260 break;
2261
a06ea964
NC		 2262 case AARCH64_OPND_SHLL_IMM:
2263 assert (idx == 2);
2264 size = 8 * aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2265 if (opnd->imm.value != size)
2266 {
2267 set_other_error (mismatch_detail, idx,
2268 _("invalid shift amount"));
2269 return 0;
2270 }
2271 break;
2272
2273 case AARCH64_OPND_IMM_VLSL:
2274 size = aarch64_get_qualifier_esize (qualifier);
2275 if (!value_in_range_p (opnd->imm.value, 0, size * 8 - 1))
2276 {
2277 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2278 size * 8 - 1);
2279 return 0;
2280 }
2281 break;
2282
2283 case AARCH64_OPND_IMM_VLSR:
2284 size = aarch64_get_qualifier_esize (qualifier);
2285 if (!value_in_range_p (opnd->imm.value, 1, size * 8))
2286 {
2287 set_imm_out_of_range_error (mismatch_detail, idx, 1, size * 8);
2288 return 0;
2289 }
2290 break;
2291
2292 case AARCH64_OPND_SIMD_IMM:
2293 case AARCH64_OPND_SIMD_IMM_SFT:
2294 /* Qualifier check. */
2295 switch (qualifier)
2296 {
2297 case AARCH64_OPND_QLF_LSL:
2298 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2299 {
2300 set_other_error (mismatch_detail, idx,
2301 _("invalid shift operator"));
2302 return 0;
2303 }
2304 break;
2305 case AARCH64_OPND_QLF_MSL:
2306 if (opnd->shifter.kind != AARCH64_MOD_MSL)
2307 {
2308 set_other_error (mismatch_detail, idx,
2309 _("invalid shift operator"));
2310 return 0;
2311 }
2312 break;
2313 case AARCH64_OPND_QLF_NIL:
2314 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2315 {
2316 set_other_error (mismatch_detail, idx,
2317 _("shift is not permitted"));
2318 return 0;
2319 }
2320 break;
2321 default:
2322 assert (0);
2323 return 0;
2324 }
2325 /* Is the immediate valid? */
2326 assert (idx == 1);
2327 if (aarch64_get_qualifier_esize (opnds[0].qualifier) != 8)
2328 {
d2865ed3
YZ		 2329 /* uimm8 or simm8 */
2330 if (!value_in_range_p (opnd->imm.value, -128, 255))
a06ea964 2331 {
d2865ed3 2332 set_imm_out_of_range_error (mismatch_detail, idx, -128, 255);
a06ea964
NC		 2333 return 0;
2334 }
2335 }
2336 else if (aarch64_shrink_expanded_imm8 (opnd->imm.value) < 0)
2337 {
2338 /* uimm64 is not
2339 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeee
2340 ffffffffgggggggghhhhhhhh'. */
2341 set_other_error (mismatch_detail, idx,
2342 _("invalid value for immediate"));
2343 return 0;
2344 }
2345 /* Is the shift amount valid? */
2346 switch (opnd->shifter.kind)
2347 {
2348 case AARCH64_MOD_LSL:
2349 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
f5555712 2350 if (!value_in_range_p (opnd->shifter.amount, 0, (size - 1) * 8))
a06ea964 2351 {
f5555712
YZ		 2352 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0,
2353 (size - 1) * 8);
a06ea964
NC		 2354 return 0;
2355 }
f5555712 2356 if (!value_aligned_p (opnd->shifter.amount, 8))
a06ea964 2357 {
f5555712 2358 set_unaligned_error (mismatch_detail, idx, 8);
a06ea964
NC		 2359 return 0;
2360 }
2361 break;
2362 case AARCH64_MOD_MSL:
2363 /* Only 8 and 16 are valid shift amount. */
2364 if (opnd->shifter.amount != 8 && opnd->shifter.amount != 16)
2365 {
2366 set_other_error (mismatch_detail, idx,
ab3b8fcf 2367 _("shift amount must be 0 or 16"));
a06ea964
NC		 2368 return 0;
2369 }
2370 break;
2371 default:
2372 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2373 {
2374 set_other_error (mismatch_detail, idx,
2375 _("invalid shift operator"));
2376 return 0;
2377 }
2378 break;
2379 }
2380 break;
2381
2382 case AARCH64_OPND_FPIMM:
2383 case AARCH64_OPND_SIMD_FPIMM:
165d4950 2384 case AARCH64_OPND_SVE_FPIMM8:
a06ea964
NC		 2385 if (opnd->imm.is_fp == 0)
2386 {
2387 set_other_error (mismatch_detail, idx,
2388 _("floating-point immediate expected"));
2389 return 0;
2390 }
2391 /* The value is expected to be an 8-bit floating-point constant with
2392 sign, 3-bit exponent and normalized 4 bits of precision, encoded
2393 in "a:b:c:d:e:f:g:h" or FLD_imm8 (depending on the type of the
2394 instruction). */
2395 if (!value_in_range_p (opnd->imm.value, 0, 255))
2396 {
2397 set_other_error (mismatch_detail, idx,
2398 _("immediate out of range"));
2399 return 0;
2400 }
2401 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2402 {
2403 set_other_error (mismatch_detail, idx,
2404 _("invalid shift operator"));
2405 return 0;
2406 }
2407 break;
2408
e950b345
RS		 2409 case AARCH64_OPND_SVE_AIMM:
2410 min_value = 0;
2411 sve_aimm:
2412 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
2413 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2414 mask = ~((uint64_t) -1 << (size * 4) << (size * 4));
2415 uvalue = opnd->imm.value;
2416 shift = opnd->shifter.amount;
2417 if (size == 1)
2418 {
2419 if (shift != 0)
2420 {
2421 set_other_error (mismatch_detail, idx,
2422 _("no shift amount allowed for"
2423 " 8-bit constants"));
2424 return 0;
2425 }
2426 }
2427 else
2428 {
2429 if (shift != 0 && shift != 8)
2430 {
2431 set_other_error (mismatch_detail, idx,
2432 _("shift amount must be 0 or 8"));
2433 return 0;
2434 }
2435 if (shift == 0 && (uvalue & 0xff) == 0)
2436 {
2437 shift = 8;
2438 uvalue = (int64_t) uvalue / 256;
2439 }
2440 }
2441 mask >>= shift;
2442 if ((uvalue & mask) != uvalue && (uvalue | ~mask) != uvalue)
2443 {
2444 set_other_error (mismatch_detail, idx,
2445 _("immediate too big for element size"));
2446 return 0;
2447 }
2448 uvalue = (uvalue - min_value) & mask;
2449 if (uvalue > 0xff)
2450 {
2451 set_other_error (mismatch_detail, idx,
2452 _("invalid arithmetic immediate"));
2453 return 0;
2454 }
2455 break;
2456
2457 case AARCH64_OPND_SVE_ASIMM:
2458 min_value = -128;
2459 goto sve_aimm;
2460
165d4950
RS		 2461 case AARCH64_OPND_SVE_I1_HALF_ONE:
2462 assert (opnd->imm.is_fp);
2463 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x3f800000)
2464 {
2465 set_other_error (mismatch_detail, idx,
2466 _("floating-point value must be 0.5 or 1.0"));
2467 return 0;
2468 }
2469 break;
2470
2471 case AARCH64_OPND_SVE_I1_HALF_TWO:
2472 assert (opnd->imm.is_fp);
2473 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x40000000)
2474 {
2475 set_other_error (mismatch_detail, idx,
2476 _("floating-point value must be 0.5 or 2.0"));
2477 return 0;
2478 }
2479 break;
2480
2481 case AARCH64_OPND_SVE_I1_ZERO_ONE:
2482 assert (opnd->imm.is_fp);
2483 if (opnd->imm.value != 0 && opnd->imm.value != 0x3f800000)
2484 {
2485 set_other_error (mismatch_detail, idx,
2486 _("floating-point value must be 0.0 or 1.0"));
2487 return 0;
2488 }
2489 break;
2490
e950b345
RS		 2491 case AARCH64_OPND_SVE_INV_LIMM:
2492 {
2493 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2494 uint64_t uimm = ~opnd->imm.value;
2495 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2496 {
2497 set_other_error (mismatch_detail, idx,
2498 _("immediate out of range"));
2499 return 0;
2500 }
2501 }
2502 break;
2503
2504 case AARCH64_OPND_SVE_LIMM_MOV:
2505 {
2506 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2507 uint64_t uimm = opnd->imm.value;
2508 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2509 {
2510 set_other_error (mismatch_detail, idx,
2511 _("immediate out of range"));
2512 return 0;
2513 }
2514 if (!aarch64_sve_dupm_mov_immediate_p (uimm, esize))
2515 {
2516 set_other_error (mismatch_detail, idx,
2517 _("invalid replicated MOV immediate"));
2518 return 0;
2519 }
2520 }
2521 break;
2522
2442d846
RS		 2523 case AARCH64_OPND_SVE_PATTERN_SCALED:
2524 assert (opnd->shifter.kind == AARCH64_MOD_MUL);
2525 if (!value_in_range_p (opnd->shifter.amount, 1, 16))
2526 {
2527 set_multiplier_out_of_range_error (mismatch_detail, idx, 1, 16);
2528 return 0;
2529 }
2530 break;
2531
e950b345
RS		 2532 case AARCH64_OPND_SVE_SHLIMM_PRED:
2533 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
28ed815a 2534 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
e950b345
RS		 2535 size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2536 if (!value_in_range_p (opnd->imm.value, 0, 8 * size - 1))
2537 {
2538 set_imm_out_of_range_error (mismatch_detail, idx,
2539 0, 8 * size - 1);
2540 return 0;
2541 }
2542 break;
2543
2544 case AARCH64_OPND_SVE_SHRIMM_PRED:
2545 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
3c17238b 2546 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
e950b345 2547 {
3c17238b
MM		 2548 unsigned int index =
2549 (type == AARCH64_OPND_SVE_SHRIMM_UNPRED_22) ? 2 : 1;
2550 size = aarch64_get_qualifier_esize (opnds[idx - index].qualifier);
2551 if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
2552 {
2553 set_imm_out_of_range_error (mismatch_detail, idx, 1, 8*size);
2554 return 0;
2555 }
2556 break;
2557 }
e950b345 2558
a06ea964
NC		 2559 default:
2560 break;
2561 }
2562 break;
2563
a06ea964
NC		 2564 case AARCH64_OPND_CLASS_SYSTEM:
2565 switch (type)
2566 {
2567 case AARCH64_OPND_PSTATEFIELD:
2568 assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4);
0bff6e2d
MW		 2569 /* MSR UAO, #uimm4
2570 MSR PAN, #uimm4
104fefee 2571 MSR SSBS,#uimm4
c2825638 2572 The immediate must be #0 or #1. */
0bff6e2d 2573 if ((opnd->pstatefield == 0x03 /* UAO. */
793a1948 2574 || opnd->pstatefield == 0x04 /* PAN. */
104fefee 2575 || opnd->pstatefield == 0x19 /* SSBS. */
793a1948 2576 || opnd->pstatefield == 0x1a) /* DIT. */
c2825638
MW		 2577 && opnds[1].imm.value > 1)
2578 {
2579 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2580 return 0;
2581 }
a06ea964
NC		 2582 /* MSR SPSel, #uimm4
2583 Uses uimm4 as a control value to select the stack pointer: if
2584 bit 0 is set it selects the current exception level's stack
2585 pointer, if bit 0 is clear it selects shared EL0 stack pointer.
2586 Bits 1 to 3 of uimm4 are reserved and should be zero. */
2587 if (opnd->pstatefield == 0x05 /* spsel */ && opnds[1].imm.value > 1)
2588 {
2589 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2590 return 0;
2591 }
2592 break;
2593 default:
2594 break;
2595 }
2596 break;
2597
2598 case AARCH64_OPND_CLASS_SIMD_ELEMENT:
2599 /* Get the upper bound for the element index. */
c2c4ff8d
SN		 2600 if (opcode->op == OP_FCMLA_ELEM)
2601 /* FCMLA index range depends on the vector size of other operands
2602 and is halfed because complex numbers take two elements. */
2603 num = aarch64_get_qualifier_nelem (opnds[0].qualifier)
2604 * aarch64_get_qualifier_esize (opnds[0].qualifier) / 2;
2605 else
2606 num = 16;
2607 num = num / aarch64_get_qualifier_esize (qualifier) - 1;
66e6f0b7 2608 assert (aarch64_get_qualifier_nelem (qualifier) == 1);
c2c4ff8d 2609
a06ea964
NC		 2610 /* Index out-of-range. */
2611 if (!value_in_range_p (opnd->reglane.index, 0, num))
2612 {
2613 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
2614 return 0;
2615 }
2616 /* SMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>].
2617 <Vm> Is the vector register (V0-V31) or (V0-V15), whose
2618 number is encoded in "size:M:Rm":
2619 size <Vm>
2620 00 RESERVED
2621 01 0:Rm
2622 10 M:Rm
2623 11 RESERVED */
369c9167 2624 if (type == AARCH64_OPND_Em16 && qualifier == AARCH64_OPND_QLF_S_H
a06ea964
NC		 2625 && !value_in_range_p (opnd->reglane.regno, 0, 15))
2626 {
2627 set_regno_out_of_range_error (mismatch_detail, idx, 0, 15);
2628 return 0;
2629 }
2630 break;
2631
2632 case AARCH64_OPND_CLASS_MODIFIED_REG:
2633 assert (idx == 1 || idx == 2);
2634 switch (type)
2635 {
2636 case AARCH64_OPND_Rm_EXT:
535b785f 2637 if (!aarch64_extend_operator_p (opnd->shifter.kind)
a06ea964
NC		 2638 && opnd->shifter.kind != AARCH64_MOD_LSL)
2639 {
2640 set_other_error (mismatch_detail, idx,
2641 _("extend operator expected"));
2642 return 0;
2643 }
2644 /* It is not optional unless at least one of "Rd" or "Rn" is '11111'
2645 (i.e. SP), in which case it defaults to LSL. The LSL alias is
2646 only valid when "Rd" or "Rn" is '11111', and is preferred in that
2647 case. */
2648 if (!aarch64_stack_pointer_p (opnds + 0)
2649 && (idx != 2 || !aarch64_stack_pointer_p (opnds + 1)))
2650 {
2651 if (!opnd->shifter.operator_present)
2652 {
2653 set_other_error (mismatch_detail, idx,
2654 _("missing extend operator"));
2655 return 0;
2656 }
2657 else if (opnd->shifter.kind == AARCH64_MOD_LSL)
2658 {
2659 set_other_error (mismatch_detail, idx,
2660 _("'LSL' operator not allowed"));
2661 return 0;
2662 }
2663 }
2664 assert (opnd->shifter.operator_present /* Default to LSL. */
2665 || opnd->shifter.kind == AARCH64_MOD_LSL);
2666 if (!value_in_range_p (opnd->shifter.amount, 0, 4))
2667 {
2668 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, 4);
2669 return 0;
2670 }
2671 /* In the 64-bit form, the final register operand is written as Wm
2672 for all but the (possibly omitted) UXTX/LSL and SXTX
2673 operators.
2674 N.B. GAS allows X register to be used with any operator as a
2675 programming convenience. */
2676 if (qualifier == AARCH64_OPND_QLF_X
2677 && opnd->shifter.kind != AARCH64_MOD_LSL
2678 && opnd->shifter.kind != AARCH64_MOD_UXTX
2679 && opnd->shifter.kind != AARCH64_MOD_SXTX)
2680 {
2681 set_other_error (mismatch_detail, idx, _("W register expected"));
2682 return 0;
2683 }
2684 break;
2685
2686 case AARCH64_OPND_Rm_SFT:
2687 /* ROR is not available to the shifted register operand in
2688 arithmetic instructions. */
535b785f 2689 if (!aarch64_shift_operator_p (opnd->shifter.kind))
a06ea964
NC		 2690 {
2691 set_other_error (mismatch_detail, idx,
2692 _("shift operator expected"));
2693 return 0;
2694 }
2695 if (opnd->shifter.kind == AARCH64_MOD_ROR
2696 && opcode->iclass != log_shift)
2697 {
2698 set_other_error (mismatch_detail, idx,
2699 _("'ROR' operator not allowed"));
2700 return 0;
2701 }
2702 num = qualifier == AARCH64_OPND_QLF_W ? 31 : 63;
2703 if (!value_in_range_p (opnd->shifter.amount, 0, num))
2704 {
2705 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, num);
2706 return 0;
2707 }
2708 break;
2709
2710 default:
2711 break;
2712 }
2713 break;
2714
2715 default:
2716 break;
2717 }
2718
2719 return 1;
2720}
2721
2722/* Main entrypoint for the operand constraint checking.
2723
2724 Return 1 if operands of *INST meet the constraint applied by the operand
2725 codes and operand qualifiers; otherwise return 0 and if MISMATCH_DETAIL is
2726 not NULL, return the detail of the error in *MISMATCH_DETAIL. N.B. when
2727 adding more constraint checking, make sure MISMATCH_DETAIL->KIND is set
2728 with a proper error kind rather than AARCH64_OPDE_NIL (GAS asserts non-NIL
2729 error kind when it is notified that an instruction does not pass the check).
2730
2731 Un-determined operand qualifiers may get established during the process. */
2732
2733int
2734aarch64_match_operands_constraint (aarch64_inst *inst,
2735 aarch64_operand_error *mismatch_detail)
2736{
2737 int i;
2738
2739 DEBUG_TRACE ("enter");
2740
0c608d6b
RS		 2741 /* Check for cases where a source register needs to be the same as the
2742 destination register. Do this before matching qualifiers since if
2743 an instruction has both invalid tying and invalid qualifiers,
2744 the error about qualifiers would suggest several alternative
2745 instructions that also have invalid tying. */
2746 i = inst->opcode->tied_operand;
2747 if (i > 0 && (inst->operands[0].reg.regno != inst->operands[i].reg.regno))
2748 {
2749 if (mismatch_detail)
2750 {
2751 mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND;
2752 mismatch_detail->index = i;
2753 mismatch_detail->error = NULL;
2754 }
2755 return 0;
2756 }
2757
a06ea964
NC		 2758 /* Match operands' qualifier.
2759 *INST has already had qualifier establish for some, if not all, of
2760 its operands; we need to find out whether these established
2761 qualifiers match one of the qualifier sequence in
2762 INST->OPCODE->QUALIFIERS_LIST. If yes, we will assign each operand
2763 with the corresponding qualifier in such a sequence.
2764 Only basic operand constraint checking is done here; the more thorough
2765 constraint checking will carried out by operand_general_constraint_met_p,
2766 which has be to called after this in order to get all of the operands'
2767 qualifiers established. */
2768 if (match_operands_qualifier (inst, TRUE /* update_p */) == 0)
2769 {
2770 DEBUG_TRACE ("FAIL on operand qualifier matching");
2771 if (mismatch_detail)
2772 {
2773 /* Return an error type to indicate that it is the qualifier
2774 matching failure; we don't care about which operand as there
2775 are enough information in the opcode table to reproduce it. */
2776 mismatch_detail->kind = AARCH64_OPDE_INVALID_VARIANT;
2777 mismatch_detail->index = -1;
2778 mismatch_detail->error = NULL;
2779 }
2780 return 0;
2781 }
2782
2783 /* Match operands' constraint. */
2784 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2785 {
2786 enum aarch64_opnd type = inst->opcode->operands[i];
2787 if (type == AARCH64_OPND_NIL)
2788 break;
2789 if (inst->operands[i].skip)
2790 {
2791 DEBUG_TRACE ("skip the incomplete operand %d", i);
2792 continue;
2793 }
2794 if (operand_general_constraint_met_p (inst->operands, i, type,
2795 inst->opcode, mismatch_detail) == 0)
2796 {
2797 DEBUG_TRACE ("FAIL on operand %d", i);
2798 return 0;
2799 }
2800 }
2801
2802 DEBUG_TRACE ("PASS");
2803
2804 return 1;
2805}
2806
2807/* Replace INST->OPCODE with OPCODE and return the replaced OPCODE.
2808 Also updates the TYPE of each INST->OPERANDS with the corresponding
2809 value of OPCODE->OPERANDS.
2810
2811 Note that some operand qualifiers may need to be manually cleared by
2812 the caller before it further calls the aarch64_opcode_encode; by
2813 doing this, it helps the qualifier matching facilities work
2814 properly. */
2815
2816const aarch64_opcode*
2817aarch64_replace_opcode (aarch64_inst *inst, const aarch64_opcode *opcode)
2818{
2819 int i;
2820 const aarch64_opcode *old = inst->opcode;
2821
2822 inst->opcode = opcode;
2823
2824 /* Update the operand types. */
2825 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2826 {
2827 inst->operands[i].type = opcode->operands[i];
2828 if (opcode->operands[i] == AARCH64_OPND_NIL)
2829 break;
2830 }
2831
2832 DEBUG_TRACE ("replace %s with %s", old->name, opcode->name);
2833
2834 return old;
2835}
2836
2837int
2838aarch64_operand_index (const enum aarch64_opnd *operands, enum aarch64_opnd operand)
2839{
2840 int i;
2841 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2842 if (operands[i] == operand)
2843 return i;
2844 else if (operands[i] == AARCH64_OPND_NIL)
2845 break;
2846 return -1;
2847}
2848\f
72e9f319
RS		 2849/* R0...R30, followed by FOR31. */
2850#define BANK(R, FOR31) \
2851 { R (0), R (1), R (2), R (3), R (4), R (5), R (6), R (7), \
2852 R (8), R (9), R (10), R (11), R (12), R (13), R (14), R (15), \
2853 R (16), R (17), R (18), R (19), R (20), R (21), R (22), R (23), \
2854 R (24), R (25), R (26), R (27), R (28), R (29), R (30), FOR31 }
a06ea964
NC		 2855/* [0][0] 32-bit integer regs with sp Wn
2856 [0][1] 64-bit integer regs with sp Xn sf=1
2857 [1][0] 32-bit integer regs with #0 Wn
2858 [1][1] 64-bit integer regs with #0 Xn sf=1 */
2859static const char *int_reg[2][2][32] = {
72e9f319
RS		 2860#define R32(X) "w" #X
2861#define R64(X) "x" #X
2862 { BANK (R32, "wsp"), BANK (R64, "sp") },
2863 { BANK (R32, "wzr"), BANK (R64, "xzr") }
a06ea964
NC		 2864#undef R64
2865#undef R32
2866};
4df068de
RS		 2867
2868/* Names of the SVE vector registers, first with .S suffixes,
2869 then with .D suffixes. */
2870
2871static const char *sve_reg[2][32] = {
2872#define ZS(X) "z" #X ".s"
2873#define ZD(X) "z" #X ".d"
2874 BANK (ZS, ZS (31)), BANK (ZD, ZD (31))
2875#undef ZD
2876#undef ZS
2877};
72e9f319 2878#undef BANK
a06ea964
NC		 2879
2880/* Return the integer register name.
2881 if SP_REG_P is not 0, R31 is an SP reg, other R31 is the zero reg. */
2882
2883static inline const char *
2884get_int_reg_name (int regno, aarch64_opnd_qualifier_t qualifier, int sp_reg_p)
2885{
2886 const int has_zr = sp_reg_p ? 0 : 1;
2887 const int is_64 = aarch64_get_qualifier_esize (qualifier) == 4 ? 0 : 1;
2888 return int_reg[has_zr][is_64][regno];
2889}
2890
2891/* Like get_int_reg_name, but IS_64 is always 1. */
2892
2893static inline const char *
2894get_64bit_int_reg_name (int regno, int sp_reg_p)
2895{
2896 const int has_zr = sp_reg_p ? 0 : 1;
2897 return int_reg[has_zr][1][regno];
2898}
2899
01dbfe4c
RS		 2900/* Get the name of the integer offset register in OPND, using the shift type
2901 to decide whether it's a word or doubleword. */
2902
2903static inline const char *
2904get_offset_int_reg_name (const aarch64_opnd_info *opnd)
2905{
2906 switch (opnd->shifter.kind)
2907 {
2908 case AARCH64_MOD_UXTW:
2909 case AARCH64_MOD_SXTW:
2910 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_W, 0);
2911
2912 case AARCH64_MOD_LSL:
2913 case AARCH64_MOD_SXTX:
2914 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_X, 0);
2915
2916 default:
2917 abort ();
2918 }
2919}
2920
4df068de
RS		 2921/* Get the name of the SVE vector offset register in OPND, using the operand
2922 qualifier to decide whether the suffix should be .S or .D. */
2923
2924static inline const char *
2925get_addr_sve_reg_name (int regno, aarch64_opnd_qualifier_t qualifier)
2926{
2927 assert (qualifier == AARCH64_OPND_QLF_S_S
2928 || qualifier == AARCH64_OPND_QLF_S_D);
2929 return sve_reg[qualifier == AARCH64_OPND_QLF_S_D][regno];
2930}
2931
a06ea964
NC		 2932/* Types for expanding an encoded 8-bit value to a floating-point value. */
2933
2934typedef union
2935{
2936 uint64_t i;
2937 double d;
2938} double_conv_t;
2939
2940typedef union
2941{
2942 uint32_t i;
2943 float f;
2944} single_conv_t;
2945
cf86120b
MW		 2946typedef union
2947{
2948 uint32_t i;
2949 float f;
2950} half_conv_t;
2951
a06ea964
NC		 2952/* IMM8 is an 8-bit floating-point constant with sign, 3-bit exponent and
2953 normalized 4 bits of precision, encoded in "a:b:c:d:e:f:g:h" or FLD_imm8
2954 (depending on the type of the instruction). IMM8 will be expanded to a
cf86120b
MW		 2955 single-precision floating-point value (SIZE == 4) or a double-precision
2956 floating-point value (SIZE == 8). A half-precision floating-point value
2957 (SIZE == 2) is expanded to a single-precision floating-point value. The
2958 expanded value is returned. */
a06ea964
NC		 2959
2960static uint64_t
cf86120b 2961expand_fp_imm (int size, uint32_t imm8)
a06ea964 2962{
57a024f4 2963 uint64_t imm = 0;
a06ea964
NC		 2964 uint32_t imm8_7, imm8_6_0, imm8_6, imm8_6_repl4;
2965
2966 imm8_7 = (imm8 >> 7) & 0x01; /* imm8<7> */
2967 imm8_6_0 = imm8 & 0x7f; /* imm8<6:0> */
2968 imm8_6 = imm8_6_0 >> 6; /* imm8<6> */
2969 imm8_6_repl4 = (imm8_6 << 3) | (imm8_6 << 2)
2970 | (imm8_6 << 1) | imm8_6; /* Replicate(imm8<6>,4) */
cf86120b 2971 if (size == 8)
a06ea964
NC		 2972 {
2973 imm = (imm8_7 << (63-32)) /* imm8<7> */
2974 | ((imm8_6 ^ 1) << (62-32)) /* NOT(imm8<6) */
2975 | (imm8_6_repl4 << (58-32)) | (imm8_6 << (57-32))
2976 | (imm8_6 << (56-32)) | (imm8_6 << (55-32)) /* Replicate(imm8<6>,7) */
2977 | (imm8_6_0 << (48-32)); /* imm8<6>:imm8<5:0> */
2978 imm <<= 32;
2979 }
cf86120b 2980 else if (size == 4 || size == 2)
a06ea964
NC		 2981 {
2982 imm = (imm8_7 << 31) /* imm8<7> */
2983 | ((imm8_6 ^ 1) << 30) /* NOT(imm8<6>) */
2984 | (imm8_6_repl4 << 26) /* Replicate(imm8<6>,4) */
2985 | (imm8_6_0 << 19); /* imm8<6>:imm8<5:0> */
2986 }
cf86120b
MW		 2987 else
2988 {
2989 /* An unsupported size. */
2990 assert (0);
2991 }
a06ea964
NC		 2992
2993 return imm;
2994}
2995
2996/* Produce the string representation of the register list operand *OPND
8a7f0c1b
RS		 2997 in the buffer pointed by BUF of size SIZE. PREFIX is the part of
2998 the register name that comes before the register number, such as "v". */
a06ea964 2999static void
8a7f0c1b
RS		 3000print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
3001 const char *prefix)
a06ea964
NC		 3002{
3003 const int num_regs = opnd->reglist.num_regs;
3004 const int first_reg = opnd->reglist.first_regno;
3005 const int last_reg = (first_reg + num_regs - 1) & 0x1f;
3006 const char *qlf_name = aarch64_get_qualifier_name (opnd->qualifier);
3007 char tb[8]; /* Temporary buffer. */
3008
3009 assert (opnd->type != AARCH64_OPND_LEt || opnd->reglist.has_index);
3010 assert (num_regs >= 1 && num_regs <= 4);
3011
3012 /* Prepare the index if any. */
3013 if (opnd->reglist.has_index)
1b7e3d2f
NC		 3014 /* PR 21096: The %100 is to silence a warning about possible truncation. */
3015 snprintf (tb, 8, "[%" PRIi64 "]", (opnd->reglist.index % 100));
a06ea964
NC		 3016 else
3017 tb[0] = '\0';
3018
3019 /* The hyphenated form is preferred for disassembly if there are
3020 more than two registers in the list, and the register numbers
3021 are monotonically increasing in increments of one. */
3022 if (num_regs > 2 && last_reg > first_reg)
8a7f0c1b
RS		 3023 snprintf (buf, size, "{%s%d.%s-%s%d.%s}%s", prefix, first_reg, qlf_name,
3024 prefix, last_reg, qlf_name, tb);
a06ea964
NC		 3025 else
3026 {
3027 const int reg0 = first_reg;
3028 const int reg1 = (first_reg + 1) & 0x1f;
3029 const int reg2 = (first_reg + 2) & 0x1f;
3030 const int reg3 = (first_reg + 3) & 0x1f;
3031
3032 switch (num_regs)
3033 {
3034 case 1:
8a7f0c1b 3035 snprintf (buf, size, "{%s%d.%s}%s", prefix, reg0, qlf_name, tb);
a06ea964
NC		 3036 break;
3037 case 2:
8a7f0c1b
RS		 3038 snprintf (buf, size, "{%s%d.%s, %s%d.%s}%s", prefix, reg0, qlf_name,
3039 prefix, reg1, qlf_name, tb);
a06ea964
NC		 3040 break;
3041 case 3:
8a7f0c1b
RS		 3042 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s}%s",
3043 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
3044 prefix, reg2, qlf_name, tb);
a06ea964
NC		 3045 break;
3046 case 4:
8a7f0c1b
RS		 3047 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s, %s%d.%s}%s",
3048 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
3049 prefix, reg2, qlf_name, prefix, reg3, qlf_name, tb);
a06ea964
NC		 3050 break;
3051 }
3052 }
3053}
3054
01dbfe4c
RS		 3055/* Print the register+immediate address in OPND to BUF, which has SIZE
3056 characters. BASE is the name of the base register. */
3057
3058static void
3059print_immediate_offset_address (char *buf, size_t size,
3060 const aarch64_opnd_info *opnd,
3061 const char *base)
3062{
3063 if (opnd->addr.writeback)
3064 {
3065 if (opnd->addr.preind)
ad43e107 3066 snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
01dbfe4c 3067 else
ad43e107 3068 snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm);
01dbfe4c
RS		 3069 }
3070 else
3071 {
98907a70
RS		 3072 if (opnd->shifter.operator_present)
3073 {
3074 assert (opnd->shifter.kind == AARCH64_MOD_MUL_VL);
ad43e107 3075 snprintf (buf, size, "[%s, #%d, mul vl]",
98907a70
RS		 3076 base, opnd->addr.offset.imm);
3077 }
3078 else if (opnd->addr.offset.imm)
ad43e107 3079 snprintf (buf, size, "[%s, #%d]", base, opnd->addr.offset.imm);
01dbfe4c
RS		 3080 else
3081 snprintf (buf, size, "[%s]", base);
3082 }
3083}
3084
a06ea964 3085/* Produce the string representation of the register offset address operand
01dbfe4c
RS		 3086 *OPND in the buffer pointed by BUF of size SIZE. BASE and OFFSET are
3087 the names of the base and offset registers. */
a06ea964
NC		 3088static void
3089print_register_offset_address (char *buf, size_t size,
01dbfe4c
RS		 3090 const aarch64_opnd_info *opnd,
3091 const char *base, const char *offset)
a06ea964 3092{
0d2f91fe 3093 char tb[16]; /* Temporary buffer. */
a06ea964
NC		 3094 bfd_boolean print_extend_p = TRUE;
3095 bfd_boolean print_amount_p = TRUE;
3096 const char *shift_name = aarch64_operand_modifiers[opnd->shifter.kind].name;
3097
a06ea964
NC		 3098 if (!opnd->shifter.amount && (opnd->qualifier != AARCH64_OPND_QLF_S_B
3099 || !opnd->shifter.amount_present))
3100 {
3101 /* Not print the shift/extend amount when the amount is zero and
3102 when it is not the special case of 8-bit load/store instruction. */
3103 print_amount_p = FALSE;
3104 /* Likewise, no need to print the shift operator LSL in such a
3105 situation. */
01dbfe4c 3106 if (opnd->shifter.kind == AARCH64_MOD_LSL)
a06ea964
NC		 3107 print_extend_p = FALSE;
3108 }
3109
3110 /* Prepare for the extend/shift. */
3111 if (print_extend_p)
3112 {
3113 if (print_amount_p)
ad43e107 3114 snprintf (tb, sizeof (tb), ", %s #%" PRIi64, shift_name,
1b7e3d2f
NC		 3115 /* PR 21096: The %100 is to silence a warning about possible truncation. */
3116 (opnd->shifter.amount % 100));
a06ea964 3117 else
ad43e107 3118 snprintf (tb, sizeof (tb), ", %s", shift_name);
a06ea964
NC		 3119 }
3120 else
3121 tb[0] = '\0';
3122
ad43e107 3123 snprintf (buf, size, "[%s, %s%s]", base, offset, tb);
a06ea964
NC		 3124}
3125
3126/* Generate the string representation of the operand OPNDS[IDX] for OPCODE
3127 in *BUF. The caller should pass in the maximum size of *BUF in SIZE.
3128 PC, PCREL_P and ADDRESS are used to pass in and return information about
3129 the PC-relative address calculation, where the PC value is passed in
3130 PC. If the operand is pc-relative related, *PCREL_P (if PCREL_P non-NULL)
3131 will return 1 and *ADDRESS (if ADDRESS non-NULL) will return the
3132 calculated address; otherwise, *PCREL_P (if PCREL_P non-NULL) returns 0.
3133
3134 The function serves both the disassembler and the assembler diagnostics
3135 issuer, which is the reason why it lives in this file. */
3136
3137void
3138aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
3139 const aarch64_opcode *opcode,
3140 const aarch64_opnd_info *opnds, int idx, int *pcrel_p,
bde90be2 3141 bfd_vma *address, char** notes)
a06ea964 3142{
bb7eff52 3143 unsigned int i, num_conds;
a06ea964
NC		 3144 const char *name = NULL;
3145 const aarch64_opnd_info *opnd = opnds + idx;
3146 enum aarch64_modifier_kind kind;
245d2e3f 3147 uint64_t addr, enum_value;
a06ea964
NC		 3148
3149 buf[0] = '\0';
3150 if (pcrel_p)
3151 *pcrel_p = 0;
3152
3153 switch (opnd->type)
3154 {
3155 case AARCH64_OPND_Rd:
3156 case AARCH64_OPND_Rn:
3157 case AARCH64_OPND_Rm:
3158 case AARCH64_OPND_Rt:
3159 case AARCH64_OPND_Rt2:
3160 case AARCH64_OPND_Rs:
3161 case AARCH64_OPND_Ra:
3162 case AARCH64_OPND_Rt_SYS:
ee804238 3163 case AARCH64_OPND_PAIRREG:
047cd301 3164 case AARCH64_OPND_SVE_Rm:
a06ea964 3165 /* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
de194d85 3166 the <ic_op>, therefore we use opnd->present to override the
a06ea964 3167 generic optional-ness information. */
362c0c4d
JW		 3168 if (opnd->type == AARCH64_OPND_Rt_SYS)
3169 {
3170 if (!opnd->present)
3171 break;
3172 }
a06ea964 3173 /* Omit the operand, e.g. RET. */
362c0c4d
JW		 3174 else if (optional_operand_p (opcode, idx)
3175 && (opnd->reg.regno
3176 == get_optional_operand_default_value (opcode)))
a06ea964
NC		 3177 break;
3178 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3179 || opnd->qualifier == AARCH64_OPND_QLF_X);
3180 snprintf (buf, size, "%s",
3181 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3182 break;
3183
3184 case AARCH64_OPND_Rd_SP:
3185 case AARCH64_OPND_Rn_SP:
bd7ceb8d 3186 case AARCH64_OPND_Rt_SP:
047cd301 3187 case AARCH64_OPND_SVE_Rn_SP:
c84364ec 3188 case AARCH64_OPND_Rm_SP:
a06ea964
NC		 3189 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3190 || opnd->qualifier == AARCH64_OPND_QLF_WSP
3191 || opnd->qualifier == AARCH64_OPND_QLF_X
3192 || opnd->qualifier == AARCH64_OPND_QLF_SP);
3193 snprintf (buf, size, "%s",
3194 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 1));
3195 break;
3196
3197 case AARCH64_OPND_Rm_EXT:
3198 kind = opnd->shifter.kind;
3199 assert (idx == 1 || idx == 2);
3200 if ((aarch64_stack_pointer_p (opnds)
3201 || (idx == 2 && aarch64_stack_pointer_p (opnds + 1)))
3202 && ((opnd->qualifier == AARCH64_OPND_QLF_W
3203 && opnds[0].qualifier == AARCH64_OPND_QLF_W
3204 && kind == AARCH64_MOD_UXTW)
3205 || (opnd->qualifier == AARCH64_OPND_QLF_X
3206 && kind == AARCH64_MOD_UXTX)))
3207 {
3208 /* 'LSL' is the preferred form in this case. */
3209 kind = AARCH64_MOD_LSL;
3210 if (opnd->shifter.amount == 0)
3211 {
3212 /* Shifter omitted. */
3213 snprintf (buf, size, "%s",
3214 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3215 break;
3216 }
3217 }
3218 if (opnd->shifter.amount)
2442d846 3219 snprintf (buf, size, "%s, %s #%" PRIi64,
a06ea964
NC		 3220 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3221 aarch64_operand_modifiers[kind].name,
3222 opnd->shifter.amount);
3223 else
3224 snprintf (buf, size, "%s, %s",
3225 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3226 aarch64_operand_modifiers[kind].name);
3227 break;
3228
3229 case AARCH64_OPND_Rm_SFT:
3230 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3231 || opnd->qualifier == AARCH64_OPND_QLF_X);
3232 if (opnd->shifter.amount == 0 && opnd->shifter.kind == AARCH64_MOD_LSL)
3233 snprintf (buf, size, "%s",
3234 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3235 else
2442d846 3236 snprintf (buf, size, "%s, %s #%" PRIi64,
a06ea964
NC		 3237 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3238 aarch64_operand_modifiers[opnd->shifter.kind].name,
3239 opnd->shifter.amount);
3240 break;
3241
3242 case AARCH64_OPND_Fd:
3243 case AARCH64_OPND_Fn:
3244 case AARCH64_OPND_Fm:
3245 case AARCH64_OPND_Fa:
3246 case AARCH64_OPND_Ft:
3247 case AARCH64_OPND_Ft2:
3248 case AARCH64_OPND_Sd:
3249 case AARCH64_OPND_Sn:
3250 case AARCH64_OPND_Sm:
047cd301
RS		 3251 case AARCH64_OPND_SVE_VZn:
3252 case AARCH64_OPND_SVE_Vd:
3253 case AARCH64_OPND_SVE_Vm:
3254 case AARCH64_OPND_SVE_Vn:
a06ea964
NC		 3255 snprintf (buf, size, "%s%d", aarch64_get_qualifier_name (opnd->qualifier),
3256 opnd->reg.regno);
3257 break;
3258
f42f1a1d 3259 case AARCH64_OPND_Va:
a06ea964
NC		 3260 case AARCH64_OPND_Vd:
3261 case AARCH64_OPND_Vn:
3262 case AARCH64_OPND_Vm:
3263 snprintf (buf, size, "v%d.%s", opnd->reg.regno,
3264 aarch64_get_qualifier_name (opnd->qualifier));
3265 break;
3266
3267 case AARCH64_OPND_Ed:
3268 case AARCH64_OPND_En:
3269 case AARCH64_OPND_Em:
369c9167 3270 case AARCH64_OPND_Em16:
f42f1a1d 3271 case AARCH64_OPND_SM3_IMM2:
dab26bf4 3272 snprintf (buf, size, "v%d.%s[%" PRIi64 "]", opnd->reglane.regno,
a06ea964
NC		 3273 aarch64_get_qualifier_name (opnd->qualifier),
3274 opnd->reglane.index);
3275 break;
3276
3277 case AARCH64_OPND_VdD1:
3278 case AARCH64_OPND_VnD1:
3279 snprintf (buf, size, "v%d.d[1]", opnd->reg.regno);
3280 break;
3281
3282 case AARCH64_OPND_LVn:
3283 case AARCH64_OPND_LVt:
3284 case AARCH64_OPND_LVt_AL:
3285 case AARCH64_OPND_LEt:
8a7f0c1b 3286 print_register_list (buf, size, opnd, "v");
a06ea964
NC		 3287 break;
3288
f11ad6bc
RS		 3289 case AARCH64_OPND_SVE_Pd:
3290 case AARCH64_OPND_SVE_Pg3:
3291 case AARCH64_OPND_SVE_Pg4_5:
3292 case AARCH64_OPND_SVE_Pg4_10:
3293 case AARCH64_OPND_SVE_Pg4_16:
3294 case AARCH64_OPND_SVE_Pm:
3295 case AARCH64_OPND_SVE_Pn:
3296 case AARCH64_OPND_SVE_Pt:
3297 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3298 snprintf (buf, size, "p%d", opnd->reg.regno);
d50c751e
RS		 3299 else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z
3300 || opnd->qualifier == AARCH64_OPND_QLF_P_M)
3301 snprintf (buf, size, "p%d/%s", opnd->reg.regno,
3302 aarch64_get_qualifier_name (opnd->qualifier));
f11ad6bc
RS		 3303 else
3304 snprintf (buf, size, "p%d.%s", opnd->reg.regno,
3305 aarch64_get_qualifier_name (opnd->qualifier));
3306 break;
3307
3308 case AARCH64_OPND_SVE_Za_5:
3309 case AARCH64_OPND_SVE_Za_16:
3310 case AARCH64_OPND_SVE_Zd:
3311 case AARCH64_OPND_SVE_Zm_5:
3312 case AARCH64_OPND_SVE_Zm_16:
3313 case AARCH64_OPND_SVE_Zn:
3314 case AARCH64_OPND_SVE_Zt:
3315 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3316 snprintf (buf, size, "z%d", opnd->reg.regno);
3317 else
3318 snprintf (buf, size, "z%d.%s", opnd->reg.regno,
3319 aarch64_get_qualifier_name (opnd->qualifier));
3320 break;
3321
3322 case AARCH64_OPND_SVE_ZnxN:
3323 case AARCH64_OPND_SVE_ZtxN:
3324 print_register_list (buf, size, opnd, "z");
3325 break;
3326
582e12bf
RS		 3327 case AARCH64_OPND_SVE_Zm3_INDEX:
3328 case AARCH64_OPND_SVE_Zm3_22_INDEX:
116adc27 3329 case AARCH64_OPND_SVE_Zm3_11_INDEX:
31e36ab3 3330 case AARCH64_OPND_SVE_Zm4_11_INDEX:
582e12bf 3331 case AARCH64_OPND_SVE_Zm4_INDEX:
f11ad6bc
RS		 3332 case AARCH64_OPND_SVE_Zn_INDEX:
3333 snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno,
3334 aarch64_get_qualifier_name (opnd->qualifier),
3335 opnd->reglane.index);
3336 break;
3337
a6a51754
RL		 3338 case AARCH64_OPND_CRn:
3339 case AARCH64_OPND_CRm:
3340 snprintf (buf, size, "C%" PRIi64, opnd->imm.value);
a06ea964
NC		 3341 break;
3342
3343 case AARCH64_OPND_IDX:
f42f1a1d 3344 case AARCH64_OPND_MASK:
a06ea964 3345 case AARCH64_OPND_IMM:
f42f1a1d 3346 case AARCH64_OPND_IMM_2:
a06ea964
NC		 3347 case AARCH64_OPND_WIDTH:
3348 case AARCH64_OPND_UIMM3_OP1:
3349 case AARCH64_OPND_UIMM3_OP2:
3350 case AARCH64_OPND_BIT_NUM:
3351 case AARCH64_OPND_IMM_VLSL:
3352 case AARCH64_OPND_IMM_VLSR:
3353 case AARCH64_OPND_SHLL_IMM:
3354 case AARCH64_OPND_IMM0:
3355 case AARCH64_OPND_IMMR:
3356 case AARCH64_OPND_IMMS:
3357 case AARCH64_OPND_FBITS:
b83b4b13 3358 case AARCH64_OPND_TME_UIMM16:
e950b345
RS		 3359 case AARCH64_OPND_SIMM5:
3360 case AARCH64_OPND_SVE_SHLIMM_PRED:
3361 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
28ed815a 3362 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
e950b345
RS		 3363 case AARCH64_OPND_SVE_SHRIMM_PRED:
3364 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
3c17238b 3365 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
e950b345
RS		 3366 case AARCH64_OPND_SVE_SIMM5:
3367 case AARCH64_OPND_SVE_SIMM5B:
3368 case AARCH64_OPND_SVE_SIMM6:
3369 case AARCH64_OPND_SVE_SIMM8:
3370 case AARCH64_OPND_SVE_UIMM3:
3371 case AARCH64_OPND_SVE_UIMM7:
3372 case AARCH64_OPND_SVE_UIMM8:
3373 case AARCH64_OPND_SVE_UIMM8_53:
c2c4ff8d
SN		 3374 case AARCH64_OPND_IMM_ROT1:
3375 case AARCH64_OPND_IMM_ROT2:
3376 case AARCH64_OPND_IMM_ROT3:
582e12bf
RS		 3377 case AARCH64_OPND_SVE_IMM_ROT1:
3378 case AARCH64_OPND_SVE_IMM_ROT2:
adccc507 3379 case AARCH64_OPND_SVE_IMM_ROT3:
a06ea964
NC		 3380 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3381 break;
3382
165d4950
RS		 3383 case AARCH64_OPND_SVE_I1_HALF_ONE:
3384 case AARCH64_OPND_SVE_I1_HALF_TWO:
3385 case AARCH64_OPND_SVE_I1_ZERO_ONE:
3386 {
3387 single_conv_t c;
3388 c.i = opnd->imm.value;
3389 snprintf (buf, size, "#%.1f", c.f);
3390 break;
3391 }
3392
245d2e3f
RS		 3393 case AARCH64_OPND_SVE_PATTERN:
3394 if (optional_operand_p (opcode, idx)
3395 && opnd->imm.value == get_optional_operand_default_value (opcode))
3396 break;
3397 enum_value = opnd->imm.value;
3398 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3399 if (aarch64_sve_pattern_array[enum_value])
3400 snprintf (buf, size, "%s", aarch64_sve_pattern_array[enum_value]);
3401 else
3402 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3403 break;
3404
2442d846
RS		 3405 case AARCH64_OPND_SVE_PATTERN_SCALED:
3406 if (optional_operand_p (opcode, idx)
3407 && !opnd->shifter.operator_present
3408 && opnd->imm.value == get_optional_operand_default_value (opcode))
3409 break;
3410 enum_value = opnd->imm.value;
3411 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3412 if (aarch64_sve_pattern_array[opnd->imm.value])
3413 snprintf (buf, size, "%s", aarch64_sve_pattern_array[opnd->imm.value]);
3414 else
3415 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3416 if (opnd->shifter.operator_present)
3417 {
3418 size_t len = strlen (buf);
3419 snprintf (buf + len, size - len, ", %s #%" PRIi64,
3420 aarch64_operand_modifiers[opnd->shifter.kind].name,
3421 opnd->shifter.amount);
3422 }
3423 break;
3424
245d2e3f
RS		 3425 case AARCH64_OPND_SVE_PRFOP:
3426 enum_value = opnd->imm.value;
3427 assert (enum_value < ARRAY_SIZE (aarch64_sve_prfop_array));
3428 if (aarch64_sve_prfop_array[enum_value])
3429 snprintf (buf, size, "%s", aarch64_sve_prfop_array[enum_value]);
3430 else
3431 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3432 break;
3433
fb098a1e
YZ		 3434 case AARCH64_OPND_IMM_MOV:
3435 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3436 {
3437 case 4: /* e.g. MOV Wd, #<imm32>. */
3438 {
3439 int imm32 = opnd->imm.value;
3440 snprintf (buf, size, "#0x%-20x\t// #%d", imm32, imm32);
3441 }
3442 break;
3443 case 8: /* e.g. MOV Xd, #<imm64>. */
3444 snprintf (buf, size, "#0x%-20" PRIx64 "\t// #%" PRIi64,
3445 opnd->imm.value, opnd->imm.value);
3446 break;
3447 default: assert (0);
3448 }
3449 break;
3450
a06ea964
NC		 3451 case AARCH64_OPND_FPIMM0:
3452 snprintf (buf, size, "#0.0");
3453 break;
3454
3455 case AARCH64_OPND_LIMM:
3456 case AARCH64_OPND_AIMM:
3457 case AARCH64_OPND_HALF:
e950b345
RS		 3458 case AARCH64_OPND_SVE_INV_LIMM:
3459 case AARCH64_OPND_SVE_LIMM:
3460 case AARCH64_OPND_SVE_LIMM_MOV:
a06ea964 3461 if (opnd->shifter.amount)
2442d846 3462 snprintf (buf, size, "#0x%" PRIx64 ", lsl #%" PRIi64, opnd->imm.value,
a06ea964
NC		 3463 opnd->shifter.amount);
3464 else
3465 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3466 break;
3467
3468 case AARCH64_OPND_SIMD_IMM:
3469 case AARCH64_OPND_SIMD_IMM_SFT:
3470 if ((! opnd->shifter.amount && opnd->shifter.kind == AARCH64_MOD_LSL)
3471 || opnd->shifter.kind == AARCH64_MOD_NONE)
3472 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3473 else
2442d846 3474 snprintf (buf, size, "#0x%" PRIx64 ", %s #%" PRIi64, opnd->imm.value,
a06ea964
NC		 3475 aarch64_operand_modifiers[opnd->shifter.kind].name,
3476 opnd->shifter.amount);
3477 break;
3478
e950b345
RS		 3479 case AARCH64_OPND_SVE_AIMM:
3480 case AARCH64_OPND_SVE_ASIMM:
3481 if (opnd->shifter.amount)
3482 snprintf (buf, size, "#%" PRIi64 ", lsl #%" PRIi64, opnd->imm.value,
3483 opnd->shifter.amount);
3484 else
3485 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3486 break;
3487
a06ea964
NC		 3488 case AARCH64_OPND_FPIMM:
3489 case AARCH64_OPND_SIMD_FPIMM:
165d4950 3490 case AARCH64_OPND_SVE_FPIMM8:
a06ea964
NC		 3491 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3492 {
cf86120b
MW		 3493 case 2: /* e.g. FMOV <Hd>, #<imm>. */
3494 {
3495 half_conv_t c;
3496 c.i = expand_fp_imm (2, opnd->imm.value);
3497 snprintf (buf, size, "#%.18e", c.f);
3498 }
3499 break;
a06ea964
NC		 3500 case 4: /* e.g. FMOV <Vd>.4S, #<imm>. */
3501 {
3502 single_conv_t c;
cf86120b 3503 c.i = expand_fp_imm (4, opnd->imm.value);
a06ea964
NC		 3504 snprintf (buf, size, "#%.18e", c.f);
3505 }
3506 break;
3507 case 8: /* e.g. FMOV <Sd>, #<imm>. */
3508 {
3509 double_conv_t c;
cf86120b 3510 c.i = expand_fp_imm (8, opnd->imm.value);
a06ea964
NC		 3511 snprintf (buf, size, "#%.18e", c.d);
3512 }
3513 break;
3514 default: assert (0);
3515 }
3516 break;
3517
3518 case AARCH64_OPND_CCMP_IMM:
3519 case AARCH64_OPND_NZCV:
3520 case AARCH64_OPND_EXCEPTION:
3521 case AARCH64_OPND_UIMM4:
193614f2 3522 case AARCH64_OPND_UIMM4_ADDG:
a06ea964 3523 case AARCH64_OPND_UIMM7:
193614f2 3524 case AARCH64_OPND_UIMM10:
a06ea964
NC		 3525 if (optional_operand_p (opcode, idx) == TRUE
3526 && (opnd->imm.value ==
3527 (int64_t) get_optional_operand_default_value (opcode)))
3528 /* Omit the operand, e.g. DCPS1. */
3529 break;
3530 snprintf (buf, size, "#0x%x", (unsigned int)opnd->imm.value);
3531 break;
3532
3533 case AARCH64_OPND_COND:
68a64283 3534 case AARCH64_OPND_COND1:
a06ea964 3535 snprintf (buf, size, "%s", opnd->cond->names[0]);
bb7eff52
RS		 3536 num_conds = ARRAY_SIZE (opnd->cond->names);
3537 for (i = 1; i < num_conds && opnd->cond->names[i]; ++i)
3538 {
3539 size_t len = strlen (buf);
3540 if (i == 1)
3541 snprintf (buf + len, size - len, " // %s = %s",
3542 opnd->cond->names[0], opnd->cond->names[i]);
3543 else
3544 snprintf (buf + len, size - len, ", %s",
3545 opnd->cond->names[i]);
3546 }
a06ea964
NC		 3547 break;
3548
3549 case AARCH64_OPND_ADDR_ADRP:
3550 addr = ((pc + AARCH64_PCREL_OFFSET) & ~(uint64_t)0xfff)
3551 + opnd->imm.value;
3552 if (pcrel_p)
3553 *pcrel_p = 1;
3554 if (address)
3555 *address = addr;
3556 /* This is not necessary during the disassembling, as print_address_func
3557 in the disassemble_info will take care of the printing. But some
3558 other callers may be still interested in getting the string in *STR,
3559 so here we do snprintf regardless. */
3560 snprintf (buf, size, "#0x%" PRIx64, addr);
3561 break;
3562
3563 case AARCH64_OPND_ADDR_PCREL14:
3564 case AARCH64_OPND_ADDR_PCREL19:
3565 case AARCH64_OPND_ADDR_PCREL21:
3566 case AARCH64_OPND_ADDR_PCREL26:
3567 addr = pc + AARCH64_PCREL_OFFSET + opnd->imm.value;
3568 if (pcrel_p)
3569 *pcrel_p = 1;
3570 if (address)
3571 *address = addr;
3572 /* This is not necessary during the disassembling, as print_address_func
3573 in the disassemble_info will take care of the printing. But some
3574 other callers may be still interested in getting the string in *STR,
3575 so here we do snprintf regardless. */
3576 snprintf (buf, size, "#0x%" PRIx64, addr);
3577 break;
3578
3579 case AARCH64_OPND_ADDR_SIMPLE:
3580 case AARCH64_OPND_SIMD_ADDR_SIMPLE:
3581 case AARCH64_OPND_SIMD_ADDR_POST:
3582 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3583 if (opnd->type == AARCH64_OPND_SIMD_ADDR_POST)
3584 {
3585 if (opnd->addr.offset.is_reg)
3586 snprintf (buf, size, "[%s], x%d", name, opnd->addr.offset.regno);
3587 else
3588 snprintf (buf, size, "[%s], #%d", name, opnd->addr.offset.imm);
3589 }
3590 else
3591 snprintf (buf, size, "[%s]", name);
3592 break;
3593
3594 case AARCH64_OPND_ADDR_REGOFF:
c8d59609 3595 case AARCH64_OPND_SVE_ADDR_R:
4df068de
RS		 3596 case AARCH64_OPND_SVE_ADDR_RR:
3597 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
3598 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
3599 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
3600 case AARCH64_OPND_SVE_ADDR_RX:
3601 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
3602 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
3603 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
01dbfe4c
RS		 3604 print_register_offset_address
3605 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3606 get_offset_int_reg_name (opnd));
a06ea964
NC		 3607 break;
3608
c469c864
MM		 3609 case AARCH64_OPND_SVE_ADDR_ZX:
3610 print_register_offset_address
3611 (buf, size, opnd,
3612 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
3613 get_64bit_int_reg_name (opnd->addr.offset.regno, 0));
3614 break;
3615
4df068de
RS		 3616 case AARCH64_OPND_SVE_ADDR_RZ:
3617 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
3618 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
3619 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
3620 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
3621 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
3622 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
3623 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
3624 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
3625 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
3626 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
3627 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
3628 print_register_offset_address
3629 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3630 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3631 break;
3632
a06ea964
NC		 3633 case AARCH64_OPND_ADDR_SIMM7:
3634 case AARCH64_OPND_ADDR_SIMM9:
3635 case AARCH64_OPND_ADDR_SIMM9_2:
3f06e550 3636 case AARCH64_OPND_ADDR_SIMM10:
fb3265b3
SD		 3637 case AARCH64_OPND_ADDR_SIMM11:
3638 case AARCH64_OPND_ADDR_SIMM13:
f42f1a1d 3639 case AARCH64_OPND_ADDR_OFFSET:
582e12bf 3640 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
98907a70
RS		 3641 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
3642 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
3643 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
3644 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
3645 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
3646 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
4df068de
RS		 3647 case AARCH64_OPND_SVE_ADDR_RI_U6:
3648 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
3649 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
3650 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
01dbfe4c
RS		 3651 print_immediate_offset_address
3652 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1));
a06ea964
NC		 3653 break;
3654
4df068de
RS		 3655 case AARCH64_OPND_SVE_ADDR_ZI_U5:
3656 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
3657 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
3658 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
3659 print_immediate_offset_address
3660 (buf, size, opnd,
3661 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier));
3662 break;
3663
3664 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
3665 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
3666 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
3667 print_register_offset_address
3668 (buf, size, opnd,
3669 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
3670 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3671 break;
3672
a06ea964
NC		 3673 case AARCH64_OPND_ADDR_UIMM12:
3674 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3675 if (opnd->addr.offset.imm)
ad43e107 3676 snprintf (buf, size, "[%s, #%d]", name, opnd->addr.offset.imm);
a06ea964
NC		 3677 else
3678 snprintf (buf, size, "[%s]", name);
3679 break;
3680
3681 case AARCH64_OPND_SYSREG:
3682 for (i = 0; aarch64_sys_regs[i].name; ++i)
f9830ec1
TC		 3683 {
3684 bfd_boolean exact_match
3685 = (aarch64_sys_regs[i].flags & opnd->sysreg.flags)
3686 == opnd->sysreg.flags;
3687
3688 /* Try and find an exact match, But if that fails, return the first
3689 partial match that was found. */
3690 if (aarch64_sys_regs[i].value == opnd->sysreg.value
3691 && ! aarch64_sys_reg_deprecated_p (&aarch64_sys_regs[i])
3692 && (name == NULL || exact_match))
3693 {
3694 name = aarch64_sys_regs[i].name;
3695 if (exact_match)
3696 {
3697 if (notes)
3698 *notes = NULL;
3699 break;
3700 }
3701
3702 /* If we didn't match exactly, that means the presense of a flag
3703 indicates what we didn't want for this instruction. e.g. If
3704 F_REG_READ is there, that means we were looking for a write
3705 register. See aarch64_ext_sysreg. */
3706 if (aarch64_sys_regs[i].flags & F_REG_WRITE)
bde90be2 3707 *notes = _("reading from a write-only register");
f9830ec1 3708 else if (aarch64_sys_regs[i].flags & F_REG_READ)
bde90be2 3709 *notes = _("writing to a read-only register");
f9830ec1
TC		 3710 }
3711 }
3712
3713 if (name)
3714 snprintf (buf, size, "%s", name);
a06ea964
NC		 3715 else
3716 {
3717 /* Implementation defined system register. */
561a72d4 3718 unsigned int value = opnd->sysreg.value;
a06ea964
NC		 3719 snprintf (buf, size, "s%u_%u_c%u_c%u_%u", (value >> 14) & 0x3,
3720 (value >> 11) & 0x7, (value >> 7) & 0xf, (value >> 3) & 0xf,
3721 value & 0x7);
3722 }
3723 break;
3724
3725 case AARCH64_OPND_PSTATEFIELD:
3726 for (i = 0; aarch64_pstatefields[i].name; ++i)
3727 if (aarch64_pstatefields[i].value == opnd->pstatefield)
3728 break;
3729 assert (aarch64_pstatefields[i].name);
3730 snprintf (buf, size, "%s", aarch64_pstatefields[i].name);
3731 break;
3732
3733 case AARCH64_OPND_SYSREG_AT:
3734 case AARCH64_OPND_SYSREG_DC:
3735 case AARCH64_OPND_SYSREG_IC:
3736 case AARCH64_OPND_SYSREG_TLBI:
2ac435d4 3737 case AARCH64_OPND_SYSREG_SR:
875880c6 3738 snprintf (buf, size, "%s", opnd->sysins_op->name);
a06ea964
NC		 3739 break;
3740
3741 case AARCH64_OPND_BARRIER:
3742 snprintf (buf, size, "%s", opnd->barrier->name);
3743 break;
3744
3745 case AARCH64_OPND_BARRIER_ISB:
3746 /* Operand can be omitted, e.g. in DCPS1. */
3747 if (! optional_operand_p (opcode, idx)
3748 || (opnd->barrier->value
3749 != get_optional_operand_default_value (opcode)))
3750 snprintf (buf, size, "#0x%x", opnd->barrier->value);
3751 break;
3752
3753 case AARCH64_OPND_PRFOP:
a1ccaec9
YZ		 3754 if (opnd->prfop->name != NULL)
3755 snprintf (buf, size, "%s", opnd->prfop->name);
3756 else
3757 snprintf (buf, size, "#0x%02x", opnd->prfop->value);
a06ea964
NC		 3758 break;
3759
1e6f4800 3760 case AARCH64_OPND_BARRIER_PSB:
ff605452
SD		 3761 case AARCH64_OPND_BTI_TARGET:
3762 if ((HINT_FLAG (opnd->hint_option->value) & HINT_OPD_F_NOPRINT) == 0)
3763 snprintf (buf, size, "%s", opnd->hint_option->name);
1e6f4800
MW		 3764 break;
3765
a06ea964
NC		 3766 default:
3767 assert (0);
3768 }
3769}
3770\f
3771#define CPENC(op0,op1,crn,crm,op2) \
3772 ((((op0) << 19) | ((op1) << 16) | ((crn) << 12) | ((crm) << 8) | ((op2) << 5)) >> 5)
3773 /* for 3.9.3 Instructions for Accessing Special Purpose Registers */
3774#define CPEN_(op1,crm,op2) CPENC(3,(op1),4,(crm),(op2))
3775 /* for 3.9.10 System Instructions */
3776#define CPENS(op1,crn,crm,op2) CPENC(1,(op1),(crn),(crm),(op2))
3777
3778#define C0 0
3779#define C1 1
3780#define C2 2
3781#define C3 3
3782#define C4 4
3783#define C5 5
3784#define C6 6
3785#define C7 7
3786#define C8 8
3787#define C9 9
3788#define C10 10
3789#define C11 11
3790#define C12 12
3791#define C13 13
3792#define C14 14
3793#define C15 15
3794
f9830ec1
TC		 3795/* TODO there is one more issues need to be resolved
3796 1. handle cpu-implementation-defined system registers. */
49eec193
YZ		 3797const aarch64_sys_reg aarch64_sys_regs [] =
3798{
3799 { "spsr_el1", CPEN_(0,C0,0), 0 }, /* = spsr_svc */
250aafa4 3800 { "spsr_el12", CPEN_ (5, C0, 0), F_ARCHEXT },
49eec193 3801 { "elr_el1", CPEN_(0,C0,1), 0 },
250aafa4 3802 { "elr_el12", CPEN_ (5, C0, 1), F_ARCHEXT },
49eec193
YZ		 3803 { "sp_el0", CPEN_(0,C1,0), 0 },
3804 { "spsel", CPEN_(0,C2,0), 0 },
3805 { "daif", CPEN_(3,C2,1), 0 },
f9830ec1 3806 { "currentel", CPEN_(0,C2,2), F_REG_READ }, /* RO */
f21cce2c 3807 { "pan", CPEN_(0,C2,3), F_ARCHEXT },
6479e48e 3808 { "uao", CPEN_ (0, C2, 4), F_ARCHEXT },
49eec193 3809 { "nzcv", CPEN_(3,C2,0), 0 },
104fefee 3810 { "ssbs", CPEN_(3,C2,6), F_ARCHEXT },
49eec193
YZ		 3811 { "fpcr", CPEN_(3,C4,0), 0 },
3812 { "fpsr", CPEN_(3,C4,1), 0 },
3813 { "dspsr_el0", CPEN_(3,C5,0), 0 },
3814 { "dlr_el0", CPEN_(3,C5,1), 0 },
3815 { "spsr_el2", CPEN_(4,C0,0), 0 }, /* = spsr_hyp */
3816 { "elr_el2", CPEN_(4,C0,1), 0 },
3817 { "sp_el1", CPEN_(4,C1,0), 0 },
3818 { "spsr_irq", CPEN_(4,C3,0), 0 },
3819 { "spsr_abt", CPEN_(4,C3,1), 0 },
3820 { "spsr_und", CPEN_(4,C3,2), 0 },
3821 { "spsr_fiq", CPEN_(4,C3,3), 0 },
3822 { "spsr_el3", CPEN_(6,C0,0), 0 },
3823 { "elr_el3", CPEN_(6,C0,1), 0 },
3824 { "sp_el2", CPEN_(6,C1,0), 0 },
3825 { "spsr_svc", CPEN_(0,C0,0), F_DEPRECATED }, /* = spsr_el1 */
3826 { "spsr_hyp", CPEN_(4,C0,0), F_DEPRECATED }, /* = spsr_el2 */
f9830ec1
TC		 3827 { "midr_el1", CPENC(3,0,C0,C0,0), F_REG_READ }, /* RO */
3828 { "ctr_el0", CPENC(3,3,C0,C0,1), F_REG_READ }, /* RO */
3829 { "mpidr_el1", CPENC(3,0,C0,C0,5), F_REG_READ }, /* RO */
3830 { "revidr_el1", CPENC(3,0,C0,C0,6), F_REG_READ }, /* RO */
3831 { "aidr_el1", CPENC(3,1,C0,C0,7), F_REG_READ }, /* RO */
3832 { "dczid_el0", CPENC(3,3,C0,C0,7), F_REG_READ }, /* RO */
3833 { "id_dfr0_el1", CPENC(3,0,C0,C1,2), F_REG_READ }, /* RO */
3834 { "id_pfr0_el1", CPENC(3,0,C0,C1,0), F_REG_READ }, /* RO */
3835 { "id_pfr1_el1", CPENC(3,0,C0,C1,1), F_REG_READ }, /* RO */
a97330e7 3836 { "id_pfr2_el1", CPENC(3,0,C0,C3,4), F_ARCHEXT | F_REG_READ}, /* RO */
f9830ec1
TC		 3837 { "id_afr0_el1", CPENC(3,0,C0,C1,3), F_REG_READ }, /* RO */
3838 { "id_mmfr0_el1", CPENC(3,0,C0,C1,4), F_REG_READ }, /* RO */
3839 { "id_mmfr1_el1", CPENC(3,0,C0,C1,5), F_REG_READ }, /* RO */
3840 { "id_mmfr2_el1", CPENC(3,0,C0,C1,6), F_REG_READ }, /* RO */
3841 { "id_mmfr3_el1", CPENC(3,0,C0,C1,7), F_REG_READ }, /* RO */
3842 { "id_mmfr4_el1", CPENC(3,0,C0,C2,6), F_REG_READ }, /* RO */
3843 { "id_isar0_el1", CPENC(3,0,C0,C2,0), F_REG_READ }, /* RO */
3844 { "id_isar1_el1", CPENC(3,0,C0,C2,1), F_REG_READ }, /* RO */
3845 { "id_isar2_el1", CPENC(3,0,C0,C2,2), F_REG_READ }, /* RO */
3846 { "id_isar3_el1", CPENC(3,0,C0,C2,3), F_REG_READ }, /* RO */
3847 { "id_isar4_el1", CPENC(3,0,C0,C2,4), F_REG_READ }, /* RO */
3848 { "id_isar5_el1", CPENC(3,0,C0,C2,5), F_REG_READ }, /* RO */
3849 { "mvfr0_el1", CPENC(3,0,C0,C3,0), F_REG_READ }, /* RO */
3850 { "mvfr1_el1", CPENC(3,0,C0,C3,1), F_REG_READ }, /* RO */
3851 { "mvfr2_el1", CPENC(3,0,C0,C3,2), F_REG_READ }, /* RO */
3852 { "ccsidr_el1", CPENC(3,1,C0,C0,0), F_REG_READ }, /* RO */
3853 { "id_aa64pfr0_el1", CPENC(3,0,C0,C4,0), F_REG_READ }, /* RO */
3854 { "id_aa64pfr1_el1", CPENC(3,0,C0,C4,1), F_REG_READ }, /* RO */
3855 { "id_aa64dfr0_el1", CPENC(3,0,C0,C5,0), F_REG_READ }, /* RO */
3856 { "id_aa64dfr1_el1", CPENC(3,0,C0,C5,1), F_REG_READ }, /* RO */
3857 { "id_aa64isar0_el1", CPENC(3,0,C0,C6,0), F_REG_READ }, /* RO */
3858 { "id_aa64isar1_el1", CPENC(3,0,C0,C6,1), F_REG_READ }, /* RO */
3859 { "id_aa64mmfr0_el1", CPENC(3,0,C0,C7,0), F_REG_READ }, /* RO */
3860 { "id_aa64mmfr1_el1", CPENC(3,0,C0,C7,1), F_REG_READ }, /* RO */
3861 { "id_aa64mmfr2_el1", CPENC (3, 0, C0, C7, 2), F_ARCHEXT | F_REG_READ }, /* RO */
3862 { "id_aa64afr0_el1", CPENC(3,0,C0,C5,4), F_REG_READ }, /* RO */
3863 { "id_aa64afr1_el1", CPENC(3,0,C0,C5,5), F_REG_READ }, /* RO */
3864 { "id_aa64zfr0_el1", CPENC (3, 0, C0, C4, 4), F_ARCHEXT | F_REG_READ }, /* RO */
3865 { "clidr_el1", CPENC(3,1,C0,C0,1), F_REG_READ }, /* RO */
cba05feb 3866 { "csselr_el1", CPENC(3,2,C0,C0,0), 0 },
49eec193
YZ		 3867 { "vpidr_el2", CPENC(3,4,C0,C0,0), 0 },
3868 { "vmpidr_el2", CPENC(3,4,C0,C0,5), 0 },
3869 { "sctlr_el1", CPENC(3,0,C1,C0,0), 0 },
3870 { "sctlr_el2", CPENC(3,4,C1,C0,0), 0 },
3871 { "sctlr_el3", CPENC(3,6,C1,C0,0), 0 },
250aafa4 3872 { "sctlr_el12", CPENC (3, 5, C1, C0, 0), F_ARCHEXT },
49eec193
YZ		 3873 { "actlr_el1", CPENC(3,0,C1,C0,1), 0 },
3874 { "actlr_el2", CPENC(3,4,C1,C0,1), 0 },
3875 { "actlr_el3", CPENC(3,6,C1,C0,1), 0 },
3876 { "cpacr_el1", CPENC(3,0,C1,C0,2), 0 },
250aafa4 3877 { "cpacr_el12", CPENC (3, 5, C1, C0, 2), F_ARCHEXT },
49eec193
YZ		 3878 { "cptr_el2", CPENC(3,4,C1,C1,2), 0 },
3879 { "cptr_el3", CPENC(3,6,C1,C1,2), 0 },
3880 { "scr_el3", CPENC(3,6,C1,C1,0), 0 },
3881 { "hcr_el2", CPENC(3,4,C1,C1,0), 0 },
3882 { "mdcr_el2", CPENC(3,4,C1,C1,1), 0 },
3883 { "mdcr_el3", CPENC(3,6,C1,C3,1), 0 },
3884 { "hstr_el2", CPENC(3,4,C1,C1,3), 0 },
3885 { "hacr_el2", CPENC(3,4,C1,C1,7), 0 },
773fb663
RS		 3886 { "zcr_el1", CPENC (3, 0, C1, C2, 0), F_ARCHEXT },
3887 { "zcr_el12", CPENC (3, 5, C1, C2, 0), F_ARCHEXT },
3888 { "zcr_el2", CPENC (3, 4, C1, C2, 0), F_ARCHEXT },
3889 { "zcr_el3", CPENC (3, 6, C1, C2, 0), F_ARCHEXT },
3890 { "zidr_el1", CPENC (3, 0, C0, C0, 7), F_ARCHEXT },
49eec193
YZ		 3891 { "ttbr0_el1", CPENC(3,0,C2,C0,0), 0 },
3892 { "ttbr1_el1", CPENC(3,0,C2,C0,1), 0 },
3893 { "ttbr0_el2", CPENC(3,4,C2,C0,0), 0 },
250aafa4 3894 { "ttbr1_el2", CPENC (3, 4, C2, C0, 1), F_ARCHEXT },
49eec193 3895 { "ttbr0_el3", CPENC(3,6,C2,C0,0), 0 },
250aafa4
MW		 3896 { "ttbr0_el12", CPENC (3, 5, C2, C0, 0), F_ARCHEXT },
3897 { "ttbr1_el12", CPENC (3, 5, C2, C0, 1), F_ARCHEXT },
49eec193
YZ		 3898 { "vttbr_el2", CPENC(3,4,C2,C1,0), 0 },
3899 { "tcr_el1", CPENC(3,0,C2,C0,2), 0 },
3900 { "tcr_el2", CPENC(3,4,C2,C0,2), 0 },
3901 { "tcr_el3", CPENC(3,6,C2,C0,2), 0 },
250aafa4 3902 { "tcr_el12", CPENC (3, 5, C2, C0, 2), F_ARCHEXT },
49eec193 3903 { "vtcr_el2", CPENC(3,4,C2,C1,2), 0 },
b0bfa7b5
SN		 3904 { "apiakeylo_el1", CPENC (3, 0, C2, C1, 0), F_ARCHEXT },
3905 { "apiakeyhi_el1", CPENC (3, 0, C2, C1, 1), F_ARCHEXT },
3906 { "apibkeylo_el1", CPENC (3, 0, C2, C1, 2), F_ARCHEXT },
3907 { "apibkeyhi_el1", CPENC (3, 0, C2, C1, 3), F_ARCHEXT },
3908 { "apdakeylo_el1", CPENC (3, 0, C2, C2, 0), F_ARCHEXT },
3909 { "apdakeyhi_el1", CPENC (3, 0, C2, C2, 1), F_ARCHEXT },
3910 { "apdbkeylo_el1", CPENC (3, 0, C2, C2, 2), F_ARCHEXT },
3911 { "apdbkeyhi_el1", CPENC (3, 0, C2, C2, 3), F_ARCHEXT },
3912 { "apgakeylo_el1", CPENC (3, 0, C2, C3, 0), F_ARCHEXT },
3913 { "apgakeyhi_el1", CPENC (3, 0, C2, C3, 1), F_ARCHEXT },
49eec193
YZ		 3914 { "afsr0_el1", CPENC(3,0,C5,C1,0), 0 },
3915 { "afsr1_el1", CPENC(3,0,C5,C1,1), 0 },
3916 { "afsr0_el2", CPENC(3,4,C5,C1,0), 0 },
3917 { "afsr1_el2", CPENC(3,4,C5,C1,1), 0 },
3918 { "afsr0_el3", CPENC(3,6,C5,C1,0), 0 },
250aafa4 3919 { "afsr0_el12", CPENC (3, 5, C5, C1, 0), F_ARCHEXT },
49eec193 3920 { "afsr1_el3", CPENC(3,6,C5,C1,1), 0 },
250aafa4 3921 { "afsr1_el12", CPENC (3, 5, C5, C1, 1), F_ARCHEXT },
49eec193
YZ		 3922 { "esr_el1", CPENC(3,0,C5,C2,0), 0 },
3923 { "esr_el2", CPENC(3,4,C5,C2,0), 0 },
3924 { "esr_el3", CPENC(3,6,C5,C2,0), 0 },
250aafa4 3925 { "esr_el12", CPENC (3, 5, C5, C2, 0), F_ARCHEXT },
cba05feb 3926 { "vsesr_el2", CPENC (3, 4, C5, C2, 3), F_ARCHEXT },
49eec193 3927 { "fpexc32_el2", CPENC(3,4,C5,C3,0), 0 },
f9830ec1 3928 { "erridr_el1", CPENC (3, 0, C5, C3, 0), F_ARCHEXT | F_REG_READ }, /* RO */
47f81142 3929 { "errselr_el1", CPENC (3, 0, C5, C3, 1), F_ARCHEXT },
f9830ec1 3930 { "erxfr_el1", CPENC (3, 0, C5, C4, 0), F_ARCHEXT | F_REG_READ }, /* RO */
47f81142
MW		 3931 { "erxctlr_el1", CPENC (3, 0, C5, C4, 1), F_ARCHEXT },
3932 { "erxstatus_el1", CPENC (3, 0, C5, C4, 2), F_ARCHEXT },
3933 { "erxaddr_el1", CPENC (3, 0, C5, C4, 3), F_ARCHEXT },
3934 { "erxmisc0_el1", CPENC (3, 0, C5, C5, 0), F_ARCHEXT },
3935 { "erxmisc1_el1", CPENC (3, 0, C5, C5, 1), F_ARCHEXT },
49eec193
YZ		 3936 { "far_el1", CPENC(3,0,C6,C0,0), 0 },
3937 { "far_el2", CPENC(3,4,C6,C0,0), 0 },
3938 { "far_el3", CPENC(3,6,C6,C0,0), 0 },
250aafa4 3939 { "far_el12", CPENC (3, 5, C6, C0, 0), F_ARCHEXT },
49eec193
YZ		 3940 { "hpfar_el2", CPENC(3,4,C6,C0,4), 0 },
3941 { "par_el1", CPENC(3,0,C7,C4,0), 0 },
3942 { "mair_el1", CPENC(3,0,C10,C2,0), 0 },
3943 { "mair_el2", CPENC(3,4,C10,C2,0), 0 },
3944 { "mair_el3", CPENC(3,6,C10,C2,0), 0 },
250aafa4 3945 { "mair_el12", CPENC (3, 5, C10, C2, 0), F_ARCHEXT },
49eec193
YZ		 3946 { "amair_el1", CPENC(3,0,C10,C3,0), 0 },
3947 { "amair_el2", CPENC(3,4,C10,C3,0), 0 },
3948 { "amair_el3", CPENC(3,6,C10,C3,0), 0 },
250aafa4 3949 { "amair_el12", CPENC (3, 5, C10, C3, 0), F_ARCHEXT },
49eec193
YZ		 3950 { "vbar_el1", CPENC(3,0,C12,C0,0), 0 },
3951 { "vbar_el2", CPENC(3,4,C12,C0,0), 0 },
3952 { "vbar_el3", CPENC(3,6,C12,C0,0), 0 },
250aafa4 3953 { "vbar_el12", CPENC (3, 5, C12, C0, 0), F_ARCHEXT },
f9830ec1
TC		 3954 { "rvbar_el1", CPENC(3,0,C12,C0,1), F_REG_READ }, /* RO */
3955 { "rvbar_el2", CPENC(3,4,C12,C0,1), F_REG_READ }, /* RO */
3956 { "rvbar_el3", CPENC(3,6,C12,C0,1), F_REG_READ }, /* RO */
49eec193
YZ		 3957 { "rmr_el1", CPENC(3,0,C12,C0,2), 0 },
3958 { "rmr_el2", CPENC(3,4,C12,C0,2), 0 },
3959 { "rmr_el3", CPENC(3,6,C12,C0,2), 0 },
f9830ec1 3960 { "isr_el1", CPENC(3,0,C12,C1,0), F_REG_READ }, /* RO */
47f81142
MW		 3961 { "disr_el1", CPENC (3, 0, C12, C1, 1), F_ARCHEXT },
3962 { "vdisr_el2", CPENC (3, 4, C12, C1, 1), F_ARCHEXT },
49eec193 3963 { "contextidr_el1", CPENC(3,0,C13,C0,1), 0 },
250aafa4
MW		 3964 { "contextidr_el2", CPENC (3, 4, C13, C0, 1), F_ARCHEXT },
3965 { "contextidr_el12", CPENC (3, 5, C13, C0, 1), F_ARCHEXT },
af4bcb4c
SD		 3966 { "rndr", CPENC(3,3,C2,C4,0), F_ARCHEXT | F_REG_READ }, /* RO */
3967 { "rndrrs", CPENC(3,3,C2,C4,1), F_ARCHEXT | F_REG_READ }, /* RO */
70f3d23a
SD		 3968 { "tco", CPENC(3,3,C4,C2,7), F_ARCHEXT },
3969 { "tfsre0_el1", CPENC(3,0,C6,C6,1), F_ARCHEXT },
3970 { "tfsr_el1", CPENC(3,0,C6,C5,0), F_ARCHEXT },
3971 { "tfsr_el2", CPENC(3,4,C6,C5,0), F_ARCHEXT },
3972 { "tfsr_el3", CPENC(3,6,C6,C6,0), F_ARCHEXT },
3973 { "tfsr_el12", CPENC(3,5,C6,C6,0), F_ARCHEXT },
3974 { "rgsr_el1", CPENC(3,0,C1,C0,5), F_ARCHEXT },
3975 { "gcr_el1", CPENC(3,0,C1,C0,6), F_ARCHEXT },
49eec193 3976 { "tpidr_el0", CPENC(3,3,C13,C0,2), 0 },
f9830ec1 3977 { "tpidrro_el0", CPENC(3,3,C13,C0,3), 0 }, /* RW */
49eec193
YZ		 3978 { "tpidr_el1", CPENC(3,0,C13,C0,4), 0 },
3979 { "tpidr_el2", CPENC(3,4,C13,C0,2), 0 },
3980 { "tpidr_el3", CPENC(3,6,C13,C0,2), 0 },
a97330e7
SD		 3981 { "scxtnum_el0", CPENC(3,3,C13,C0,7), F_ARCHEXT },
3982 { "scxtnum_el1", CPENC(3,0,C13,C0,7), F_ARCHEXT },
3983 { "scxtnum_el2", CPENC(3,4,C13,C0,7), F_ARCHEXT },
3984 { "scxtnum_el12", CPENC(3,5,C13,C0,7), F_ARCHEXT },
3985 { "scxtnum_el3", CPENC(3,6,C13,C0,7), F_ARCHEXT },
49eec193 3986 { "teecr32_el1", CPENC(2,2,C0, C0,0), 0 }, /* See section 3.9.7.1 */
f9830ec1
TC		 3987 { "cntfrq_el0", CPENC(3,3,C14,C0,0), 0 }, /* RW */
3988 { "cntpct_el0", CPENC(3,3,C14,C0,1), F_REG_READ }, /* RO */
3989 { "cntvct_el0", CPENC(3,3,C14,C0,2), F_REG_READ }, /* RO */
49eec193
YZ		 3990 { "cntvoff_el2", CPENC(3,4,C14,C0,3), 0 },
3991 { "cntkctl_el1", CPENC(3,0,C14,C1,0), 0 },
250aafa4 3992 { "cntkctl_el12", CPENC (3, 5, C14, C1, 0), F_ARCHEXT },
49eec193
YZ		 3993 { "cnthctl_el2", CPENC(3,4,C14,C1,0), 0 },
3994 { "cntp_tval_el0", CPENC(3,3,C14,C2,0), 0 },
250aafa4 3995 { "cntp_tval_el02", CPENC (3, 5, C14, C2, 0), F_ARCHEXT },
49eec193 3996 { "cntp_ctl_el0", CPENC(3,3,C14,C2,1), 0 },
250aafa4 3997 { "cntp_ctl_el02", CPENC (3, 5, C14, C2, 1), F_ARCHEXT },
49eec193 3998 { "cntp_cval_el0", CPENC(3,3,C14,C2,2), 0 },
250aafa4 3999 { "cntp_cval_el02", CPENC (3, 5, C14, C2, 2), F_ARCHEXT },
49eec193 4000 { "cntv_tval_el0", CPENC(3,3,C14,C3,0), 0 },
250aafa4 4001 { "cntv_tval_el02", CPENC (3, 5, C14, C3, 0), F_ARCHEXT },
49eec193 4002 { "cntv_ctl_el0", CPENC(3,3,C14,C3,1), 0 },
250aafa4 4003 { "cntv_ctl_el02", CPENC (3, 5, C14, C3, 1), F_ARCHEXT },
49eec193 4004 { "cntv_cval_el0", CPENC(3,3,C14,C3,2), 0 },
250aafa4 4005 { "cntv_cval_el02", CPENC (3, 5, C14, C3, 2), F_ARCHEXT },
49eec193
YZ		 4006 { "cnthp_tval_el2", CPENC(3,4,C14,C2,0), 0 },
4007 { "cnthp_ctl_el2", CPENC(3,4,C14,C2,1), 0 },
4008 { "cnthp_cval_el2", CPENC(3,4,C14,C2,2), 0 },
4009 { "cntps_tval_el1", CPENC(3,7,C14,C2,0), 0 },
4010 { "cntps_ctl_el1", CPENC(3,7,C14,C2,1), 0 },
4011 { "cntps_cval_el1", CPENC(3,7,C14,C2,2), 0 },
250aafa4
MW		 4012 { "cnthv_tval_el2", CPENC (3, 4, C14, C3, 0), F_ARCHEXT },
4013 { "cnthv_ctl_el2", CPENC (3, 4, C14, C3, 1), F_ARCHEXT },
4014 { "cnthv_cval_el2", CPENC (3, 4, C14, C3, 2), F_ARCHEXT },
49eec193
YZ		 4015 { "dacr32_el2", CPENC(3,4,C3,C0,0), 0 },
4016 { "ifsr32_el2", CPENC(3,4,C5,C0,1), 0 },
4017 { "teehbr32_el1", CPENC(2,2,C1,C0,0), 0 },
4018 { "sder32_el3", CPENC(3,6,C1,C1,1), 0 },
4019 { "mdscr_el1", CPENC(2,0,C0, C2, 2), 0 },
f9830ec1 4020 { "mdccsr_el0", CPENC(2,3,C0, C1, 0), F_REG_READ }, /* r */
49eec193
YZ		 4021 { "mdccint_el1", CPENC(2,0,C0, C2, 0), 0 },
4022 { "dbgdtr_el0", CPENC(2,3,C0, C4, 0), 0 },
f9830ec1
TC		 4023 { "dbgdtrrx_el0", CPENC(2,3,C0, C5, 0), F_REG_READ }, /* r */
4024 { "dbgdtrtx_el0", CPENC(2,3,C0, C5, 0), F_REG_WRITE }, /* w */
cba05feb
TC		 4025 { "osdtrrx_el1", CPENC(2,0,C0, C0, 2), 0 },
4026 { "osdtrtx_el1", CPENC(2,0,C0, C3, 2), 0 },
49eec193
YZ		 4027 { "oseccr_el1", CPENC(2,0,C0, C6, 2), 0 },
4028 { "dbgvcr32_el2", CPENC(2,4,C0, C7, 0), 0 },
4029 { "dbgbvr0_el1", CPENC(2,0,C0, C0, 4), 0 },
4030 { "dbgbvr1_el1", CPENC(2,0,C0, C1, 4), 0 },
4031 { "dbgbvr2_el1", CPENC(2,0,C0, C2, 4), 0 },
4032 { "dbgbvr3_el1", CPENC(2,0,C0, C3, 4), 0 },
4033 { "dbgbvr4_el1", CPENC(2,0,C0, C4, 4), 0 },
4034 { "dbgbvr5_el1", CPENC(2,0,C0, C5, 4), 0 },
4035 { "dbgbvr6_el1", CPENC(2,0,C0, C6, 4), 0 },
4036 { "dbgbvr7_el1", CPENC(2,0,C0, C7, 4), 0 },
4037 { "dbgbvr8_el1", CPENC(2,0,C0, C8, 4), 0 },
4038 { "dbgbvr9_el1", CPENC(2,0,C0, C9, 4), 0 },
4039 { "dbgbvr10_el1", CPENC(2,0,C0, C10,4), 0 },
4040 { "dbgbvr11_el1", CPENC(2,0,C0, C11,4), 0 },
4041 { "dbgbvr12_el1", CPENC(2,0,C0, C12,4), 0 },
4042 { "dbgbvr13_el1", CPENC(2,0,C0, C13,4), 0 },
4043 { "dbgbvr14_el1", CPENC(2,0,C0, C14,4), 0 },
4044 { "dbgbvr15_el1", CPENC(2,0,C0, C15,4), 0 },
4045 { "dbgbcr0_el1", CPENC(2,0,C0, C0, 5), 0 },
4046 { "dbgbcr1_el1", CPENC(2,0,C0, C1, 5), 0 },
4047 { "dbgbcr2_el1", CPENC(2,0,C0, C2, 5), 0 },
4048 { "dbgbcr3_el1", CPENC(2,0,C0, C3, 5), 0 },
4049 { "dbgbcr4_el1", CPENC(2,0,C0, C4, 5), 0 },
4050 { "dbgbcr5_el1", CPENC(2,0,C0, C5, 5), 0 },
4051 { "dbgbcr6_el1", CPENC(2,0,C0, C6, 5), 0 },
4052 { "dbgbcr7_el1", CPENC(2,0,C0, C7, 5), 0 },
4053 { "dbgbcr8_el1", CPENC(2,0,C0, C8, 5), 0 },
4054 { "dbgbcr9_el1", CPENC(2,0,C0, C9, 5), 0 },
4055 { "dbgbcr10_el1", CPENC(2,0,C0, C10,5), 0 },
4056 { "dbgbcr11_el1", CPENC(2,0,C0, C11,5), 0 },
4057 { "dbgbcr12_el1", CPENC(2,0,C0, C12,5), 0 },
4058 { "dbgbcr13_el1", CPENC(2,0,C0, C13,5), 0 },
4059 { "dbgbcr14_el1", CPENC(2,0,C0, C14,5), 0 },
4060 { "dbgbcr15_el1", CPENC(2,0,C0, C15,5), 0 },
4061 { "dbgwvr0_el1", CPENC(2,0,C0, C0, 6), 0 },
4062 { "dbgwvr1_el1", CPENC(2,0,C0, C1, 6), 0 },
4063 { "dbgwvr2_el1", CPENC(2,0,C0, C2, 6), 0 },
4064 { "dbgwvr3_el1", CPENC(2,0,C0, C3, 6), 0 },
4065 { "dbgwvr4_el1", CPENC(2,0,C0, C4, 6), 0 },
4066 { "dbgwvr5_el1", CPENC(2,0,C0, C5, 6), 0 },
4067 { "dbgwvr6_el1", CPENC(2,0,C0, C6, 6), 0 },
4068 { "dbgwvr7_el1", CPENC(2,0,C0, C7, 6), 0 },
4069 { "dbgwvr8_el1", CPENC(2,0,C0, C8, 6), 0 },
4070 { "dbgwvr9_el1", CPENC(2,0,C0, C9, 6), 0 },
4071 { "dbgwvr10_el1", CPENC(2,0,C0, C10,6), 0 },
4072 { "dbgwvr11_el1", CPENC(2,0,C0, C11,6), 0 },
4073 { "dbgwvr12_el1", CPENC(2,0,C0, C12,6), 0 },
4074 { "dbgwvr13_el1", CPENC(2,0,C0, C13,6), 0 },
4075 { "dbgwvr14_el1", CPENC(2,0,C0, C14,6), 0 },
4076 { "dbgwvr15_el1", CPENC(2,0,C0, C15,6), 0 },
4077 { "dbgwcr0_el1", CPENC(2,0,C0, C0, 7), 0 },
4078 { "dbgwcr1_el1", CPENC(2,0,C0, C1, 7), 0 },
4079 { "dbgwcr2_el1", CPENC(2,0,C0, C2, 7), 0 },
4080 { "dbgwcr3_el1", CPENC(2,0,C0, C3, 7), 0 },
4081 { "dbgwcr4_el1", CPENC(2,0,C0, C4, 7), 0 },
4082 { "dbgwcr5_el1", CPENC(2,0,C0, C5, 7), 0 },
4083 { "dbgwcr6_el1", CPENC(2,0,C0, C6, 7), 0 },
4084 { "dbgwcr7_el1", CPENC(2,0,C0, C7, 7), 0 },
4085 { "dbgwcr8_el1", CPENC(2,0,C0, C8, 7), 0 },
4086 { "dbgwcr9_el1", CPENC(2,0,C0, C9, 7), 0 },
4087 { "dbgwcr10_el1", CPENC(2,0,C0, C10,7), 0 },
4088 { "dbgwcr11_el1", CPENC(2,0,C0, C11,7), 0 },
4089 { "dbgwcr12_el1", CPENC(2,0,C0, C12,7), 0 },
4090 { "dbgwcr13_el1", CPENC(2,0,C0, C13,7), 0 },
4091 { "dbgwcr14_el1", CPENC(2,0,C0, C14,7), 0 },
4092 { "dbgwcr15_el1", CPENC(2,0,C0, C15,7), 0 },
f9830ec1
TC		 4093 { "mdrar_el1", CPENC(2,0,C1, C0, 0), F_REG_READ }, /* r */
4094 { "oslar_el1", CPENC(2,0,C1, C0, 4), F_REG_WRITE }, /* w */
4095 { "oslsr_el1", CPENC(2,0,C1, C1, 4), F_REG_READ }, /* r */
49eec193
YZ		 4096 { "osdlr_el1", CPENC(2,0,C1, C3, 4), 0 },
4097 { "dbgprcr_el1", CPENC(2,0,C1, C4, 4), 0 },
4098 { "dbgclaimset_el1", CPENC(2,0,C7, C8, 6), 0 },
4099 { "dbgclaimclr_el1", CPENC(2,0,C7, C9, 6), 0 },
f9830ec1 4100 { "dbgauthstatus_el1", CPENC(2,0,C7, C14,6), F_REG_READ }, /* r */
55c144e6
MW		 4101 { "pmblimitr_el1", CPENC (3, 0, C9, C10, 0), F_ARCHEXT }, /* rw */
4102 { "pmbptr_el1", CPENC (3, 0, C9, C10, 1), F_ARCHEXT }, /* rw */
4103 { "pmbsr_el1", CPENC (3, 0, C9, C10, 3), F_ARCHEXT }, /* rw */
f9830ec1 4104 { "pmbidr_el1", CPENC (3, 0, C9, C10, 7), F_ARCHEXT | F_REG_READ }, /* ro */
55c144e6
MW		 4105 { "pmscr_el1", CPENC (3, 0, C9, C9, 0), F_ARCHEXT }, /* rw */
4106 { "pmsicr_el1", CPENC (3, 0, C9, C9, 2), F_ARCHEXT }, /* rw */
4107 { "pmsirr_el1", CPENC (3, 0, C9, C9, 3), F_ARCHEXT }, /* rw */
4108 { "pmsfcr_el1", CPENC (3, 0, C9, C9, 4), F_ARCHEXT }, /* rw */
4109 { "pmsevfr_el1", CPENC (3, 0, C9, C9, 5), F_ARCHEXT }, /* rw */
4110 { "pmslatfr_el1", CPENC (3, 0, C9, C9, 6), F_ARCHEXT }, /* rw */
cba05feb 4111 { "pmsidr_el1", CPENC (3, 0, C9, C9, 7), F_ARCHEXT }, /* rw */
55c144e6
MW		 4112 { "pmscr_el2", CPENC (3, 4, C9, C9, 0), F_ARCHEXT }, /* rw */
4113 { "pmscr_el12", CPENC (3, 5, C9, C9, 0), F_ARCHEXT }, /* rw */
49eec193
YZ		 4114 { "pmcr_el0", CPENC(3,3,C9,C12, 0), 0 },
4115 { "pmcntenset_el0", CPENC(3,3,C9,C12, 1), 0 },
4116 { "pmcntenclr_el0", CPENC(3,3,C9,C12, 2), 0 },
4117 { "pmovsclr_el0", CPENC(3,3,C9,C12, 3), 0 },
f9830ec1 4118 { "pmswinc_el0", CPENC(3,3,C9,C12, 4), F_REG_WRITE }, /* w */
49eec193 4119 { "pmselr_el0", CPENC(3,3,C9,C12, 5), 0 },
f9830ec1
TC		 4120 { "pmceid0_el0", CPENC(3,3,C9,C12, 6), F_REG_READ }, /* r */
4121 { "pmceid1_el0", CPENC(3,3,C9,C12, 7), F_REG_READ }, /* r */
49eec193
YZ		 4122 { "pmccntr_el0", CPENC(3,3,C9,C13, 0), 0 },
4123 { "pmxevtyper_el0", CPENC(3,3,C9,C13, 1), 0 },
4124 { "pmxevcntr_el0", CPENC(3,3,C9,C13, 2), 0 },
4125 { "pmuserenr_el0", CPENC(3,3,C9,C14, 0), 0 },
4126 { "pmintenset_el1", CPENC(3,0,C9,C14, 1), 0 },
4127 { "pmintenclr_el1", CPENC(3,0,C9,C14, 2), 0 },
4128 { "pmovsset_el0", CPENC(3,3,C9,C14, 3), 0 },
4129 { "pmevcntr0_el0", CPENC(3,3,C14,C8, 0), 0 },
4130 { "pmevcntr1_el0", CPENC(3,3,C14,C8, 1), 0 },
4131 { "pmevcntr2_el0", CPENC(3,3,C14,C8, 2), 0 },
4132 { "pmevcntr3_el0", CPENC(3,3,C14,C8, 3), 0 },
4133 { "pmevcntr4_el0", CPENC(3,3,C14,C8, 4), 0 },
4134 { "pmevcntr5_el0", CPENC(3,3,C14,C8, 5), 0 },
4135 { "pmevcntr6_el0", CPENC(3,3,C14,C8, 6), 0 },
4136 { "pmevcntr7_el0", CPENC(3,3,C14,C8, 7), 0 },
4137 { "pmevcntr8_el0", CPENC(3,3,C14,C9, 0), 0 },
4138 { "pmevcntr9_el0", CPENC(3,3,C14,C9, 1), 0 },
4139 { "pmevcntr10_el0", CPENC(3,3,C14,C9, 2), 0 },
4140 { "pmevcntr11_el0", CPENC(3,3,C14,C9, 3), 0 },
4141 { "pmevcntr12_el0", CPENC(3,3,C14,C9, 4), 0 },
4142 { "pmevcntr13_el0", CPENC(3,3,C14,C9, 5), 0 },
4143 { "pmevcntr14_el0", CPENC(3,3,C14,C9, 6), 0 },
4144 { "pmevcntr15_el0", CPENC(3,3,C14,C9, 7), 0 },
4145 { "pmevcntr16_el0", CPENC(3,3,C14,C10,0), 0 },
4146 { "pmevcntr17_el0", CPENC(3,3,C14,C10,1), 0 },
4147 { "pmevcntr18_el0", CPENC(3,3,C14,C10,2), 0 },
4148 { "pmevcntr19_el0", CPENC(3,3,C14,C10,3), 0 },
4149 { "pmevcntr20_el0", CPENC(3,3,C14,C10,4), 0 },
4150 { "pmevcntr21_el0", CPENC(3,3,C14,C10,5), 0 },
4151 { "pmevcntr22_el0", CPENC(3,3,C14,C10,6), 0 },
4152 { "pmevcntr23_el0", CPENC(3,3,C14,C10,7), 0 },
4153 { "pmevcntr24_el0", CPENC(3,3,C14,C11,0), 0 },
4154 { "pmevcntr25_el0", CPENC(3,3,C14,C11,1), 0 },
4155 { "pmevcntr26_el0", CPENC(3,3,C14,C11,2), 0 },
4156 { "pmevcntr27_el0", CPENC(3,3,C14,C11,3), 0 },
4157 { "pmevcntr28_el0", CPENC(3,3,C14,C11,4), 0 },
4158 { "pmevcntr29_el0", CPENC(3,3,C14,C11,5), 0 },
4159 { "pmevcntr30_el0", CPENC(3,3,C14,C11,6), 0 },
4160 { "pmevtyper0_el0", CPENC(3,3,C14,C12,0), 0 },
4161 { "pmevtyper1_el0", CPENC(3,3,C14,C12,1), 0 },
4162 { "pmevtyper2_el0", CPENC(3,3,C14,C12,2), 0 },
4163 { "pmevtyper3_el0", CPENC(3,3,C14,C12,3), 0 },
4164 { "pmevtyper4_el0", CPENC(3,3,C14,C12,4), 0 },
4165 { "pmevtyper5_el0", CPENC(3,3,C14,C12,5), 0 },
4166 { "pmevtyper6_el0", CPENC(3,3,C14,C12,6), 0 },
4167 { "pmevtyper7_el0", CPENC(3,3,C14,C12,7), 0 },
4168 { "pmevtyper8_el0", CPENC(3,3,C14,C13,0), 0 },
4169 { "pmevtyper9_el0", CPENC(3,3,C14,C13,1), 0 },
4170 { "pmevtyper10_el0", CPENC(3,3,C14,C13,2), 0 },
4171 { "pmevtyper11_el0", CPENC(3,3,C14,C13,3), 0 },
4172 { "pmevtyper12_el0", CPENC(3,3,C14,C13,4), 0 },
4173 { "pmevtyper13_el0", CPENC(3,3,C14,C13,5), 0 },
4174 { "pmevtyper14_el0", CPENC(3,3,C14,C13,6), 0 },
4175 { "pmevtyper15_el0", CPENC(3,3,C14,C13,7), 0 },
4176 { "pmevtyper16_el0", CPENC(3,3,C14,C14,0), 0 },
4177 { "pmevtyper17_el0", CPENC(3,3,C14,C14,1), 0 },
4178 { "pmevtyper18_el0", CPENC(3,3,C14,C14,2), 0 },
4179 { "pmevtyper19_el0", CPENC(3,3,C14,C14,3), 0 },
4180 { "pmevtyper20_el0", CPENC(3,3,C14,C14,4), 0 },
4181 { "pmevtyper21_el0", CPENC(3,3,C14,C14,5), 0 },
4182 { "pmevtyper22_el0", CPENC(3,3,C14,C14,6), 0 },
4183 { "pmevtyper23_el0", CPENC(3,3,C14,C14,7), 0 },
4184 { "pmevtyper24_el0", CPENC(3,3,C14,C15,0), 0 },
4185 { "pmevtyper25_el0", CPENC(3,3,C14,C15,1), 0 },
4186 { "pmevtyper26_el0", CPENC(3,3,C14,C15,2), 0 },
4187 { "pmevtyper27_el0", CPENC(3,3,C14,C15,3), 0 },
4188 { "pmevtyper28_el0", CPENC(3,3,C14,C15,4), 0 },
4189 { "pmevtyper29_el0", CPENC(3,3,C14,C15,5), 0 },
4190 { "pmevtyper30_el0", CPENC(3,3,C14,C15,6), 0 },
4191 { "pmccfiltr_el0", CPENC(3,3,C14,C15,7), 0 },
793a1948
TC		 4192
4193 { "dit", CPEN_ (3, C2, 5), F_ARCHEXT },
4194 { "vstcr_el2", CPENC(3, 4, C2, C6, 2), F_ARCHEXT },
4195 { "vsttbr_el2", CPENC(3, 4, C2, C6, 0), F_ARCHEXT },
4196 { "cnthvs_tval_el2", CPENC(3, 4, C14, C4, 0), F_ARCHEXT },
4197 { "cnthvs_cval_el2", CPENC(3, 4, C14, C4, 2), F_ARCHEXT },
4198 { "cnthvs_ctl_el2", CPENC(3, 4, C14, C4, 1), F_ARCHEXT },
4199 { "cnthps_tval_el2", CPENC(3, 4, C14, C5, 0), F_ARCHEXT },
4200 { "cnthps_cval_el2", CPENC(3, 4, C14, C5, 2), F_ARCHEXT },
4201 { "cnthps_ctl_el2", CPENC(3, 4, C14, C5, 1), F_ARCHEXT },
4202 { "sder32_el2", CPENC(3, 4, C1, C3, 1), F_ARCHEXT },
4203 { "vncr_el2", CPENC(3, 4, C2, C2, 0), F_ARCHEXT },
49eec193 4204 { 0, CPENC(0,0,0,0,0), 0 },
a06ea964
NC		 4205};
4206
49eec193
YZ		 4207bfd_boolean
4208aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *reg)
4209{
4210 return (reg->flags & F_DEPRECATED) != 0;
4211}
4212
f21cce2c
MW		 4213bfd_boolean
4214aarch64_sys_reg_supported_p (const aarch64_feature_set features,
4215 const aarch64_sys_reg *reg)
4216{
4217 if (!(reg->flags & F_ARCHEXT))
4218 return TRUE;
4219
4220 /* PAN. Values are from aarch64_sys_regs. */
4221 if (reg->value == CPEN_(0,C2,3)
4222 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
4223 return FALSE;
4224
a97330e7
SD		 4225 /* SCXTNUM_ELx registers. */
4226 if ((reg->value == CPENC (3, 3, C13, C0, 7)
4227 || reg->value == CPENC (3, 0, C13, C0, 7)
4228 || reg->value == CPENC (3, 4, C13, C0, 7)
4229 || reg->value == CPENC (3, 6, C13, C0, 7)
4230 || reg->value == CPENC (3, 5, C13, C0, 7))
4231 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SCXTNUM))
4232 return FALSE;
4233
4234 /* ID_PFR2_EL1 register. */
4235 if (reg->value == CPENC(3, 0, C0, C3, 4)
4236 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_ID_PFR2))
4237 return FALSE;
4238
104fefee
SD		 4239 /* SSBS. Values are from aarch64_sys_regs. */
4240 if (reg->value == CPEN_(3,C2,6)
4241 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS))
4242 return FALSE;
4243
250aafa4
MW		 4244 /* Virtualization host extensions: system registers. */
4245 if ((reg->value == CPENC (3, 4, C2, C0, 1)
4246 || reg->value == CPENC (3, 4, C13, C0, 1)
4247 || reg->value == CPENC (3, 4, C14, C3, 0)
4248 || reg->value == CPENC (3, 4, C14, C3, 1)
4249 || reg->value == CPENC (3, 4, C14, C3, 2))
4250 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4251 return FALSE;
4252
4253 /* Virtualization host extensions: *_el12 names of *_el1 registers. */
4254 if ((reg->value == CPEN_ (5, C0, 0)
4255 || reg->value == CPEN_ (5, C0, 1)
4256 || reg->value == CPENC (3, 5, C1, C0, 0)
4257 || reg->value == CPENC (3, 5, C1, C0, 2)
4258 || reg->value == CPENC (3, 5, C2, C0, 0)
4259 || reg->value == CPENC (3, 5, C2, C0, 1)
4260 || reg->value == CPENC (3, 5, C2, C0, 2)
4261 || reg->value == CPENC (3, 5, C5, C1, 0)
4262 || reg->value == CPENC (3, 5, C5, C1, 1)
4263 || reg->value == CPENC (3, 5, C5, C2, 0)
4264 || reg->value == CPENC (3, 5, C6, C0, 0)
4265 || reg->value == CPENC (3, 5, C10, C2, 0)
4266 || reg->value == CPENC (3, 5, C10, C3, 0)
4267 || reg->value == CPENC (3, 5, C12, C0, 0)
4268 || reg->value == CPENC (3, 5, C13, C0, 1)
4269 || reg->value == CPENC (3, 5, C14, C1, 0))
4270 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4271 return FALSE;
4272
4273 /* Virtualization host extensions: *_el02 names of *_el0 registers. */
4274 if ((reg->value == CPENC (3, 5, C14, C2, 0)
4275 || reg->value == CPENC (3, 5, C14, C2, 1)
4276 || reg->value == CPENC (3, 5, C14, C2, 2)
4277 || reg->value == CPENC (3, 5, C14, C3, 0)
4278 || reg->value == CPENC (3, 5, C14, C3, 1)
4279 || reg->value == CPENC (3, 5, C14, C3, 2))
4280 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
63511907 4281 return FALSE;
1a04d1a7
MW		 4282
4283 /* ARMv8.2 features. */
6479e48e
MW		 4284
4285 /* ID_AA64MMFR2_EL1. */
1a04d1a7
MW		 4286 if (reg->value == CPENC (3, 0, C0, C7, 2)
4287 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
250aafa4
MW		 4288 return FALSE;
4289
6479e48e
MW		 4290 /* PSTATE.UAO. */
4291 if (reg->value == CPEN_ (0, C2, 4)
4292 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4293 return FALSE;
4294
47f81142
MW		 4295 /* RAS extension. */
4296
651657fa
MW		 4297 /* ERRIDR_EL1, ERRSELR_EL1, ERXFR_EL1, ERXCTLR_EL1, ERXSTATUS_EL, ERXADDR_EL1,
4298 ERXMISC0_EL1 AND ERXMISC1_EL1. */
47f81142 4299 if ((reg->value == CPENC (3, 0, C5, C3, 0)
651657fa 4300 || reg->value == CPENC (3, 0, C5, C3, 1)
47f81142
MW		 4301 || reg->value == CPENC (3, 0, C5, C3, 2)
4302 || reg->value == CPENC (3, 0, C5, C3, 3)
651657fa
MW		 4303 || reg->value == CPENC (3, 0, C5, C4, 0)
4304 || reg->value == CPENC (3, 0, C5, C4, 1)
4305 || reg->value == CPENC (3, 0, C5, C4, 2)
4306 || reg->value == CPENC (3, 0, C5, C4, 3)
47f81142
MW		 4307 || reg->value == CPENC (3, 0, C5, C5, 0)
4308 || reg->value == CPENC (3, 0, C5, C5, 1))
4309 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
4310 return FALSE;
4311
4312 /* VSESR_EL2, DISR_EL1 and VDISR_EL2. */
4313 if ((reg->value == CPENC (3, 4, C5, C2, 3)
4314 || reg->value == CPENC (3, 0, C12, C1, 1)
4315 || reg->value == CPENC (3, 4, C12, C1, 1))
4316 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
4317 return FALSE;
4318
55c144e6
MW		 4319 /* Statistical Profiling extension. */
4320 if ((reg->value == CPENC (3, 0, C9, C10, 0)
4321 || reg->value == CPENC (3, 0, C9, C10, 1)
4322 || reg->value == CPENC (3, 0, C9, C10, 3)
4323 || reg->value == CPENC (3, 0, C9, C10, 7)
4324 || reg->value == CPENC (3, 0, C9, C9, 0)
4325 || reg->value == CPENC (3, 0, C9, C9, 2)
4326 || reg->value == CPENC (3, 0, C9, C9, 3)
4327 || reg->value == CPENC (3, 0, C9, C9, 4)
4328 || reg->value == CPENC (3, 0, C9, C9, 5)
4329 || reg->value == CPENC (3, 0, C9, C9, 6)
4330 || reg->value == CPENC (3, 0, C9, C9, 7)
4331 || reg->value == CPENC (3, 4, C9, C9, 0)
4332 || reg->value == CPENC (3, 5, C9, C9, 0))
4333 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PROFILE))
4334 return FALSE;
4335
b0bfa7b5
SN		 4336 /* ARMv8.3 Pointer authentication keys. */
4337 if ((reg->value == CPENC (3, 0, C2, C1, 0)
4338 || reg->value == CPENC (3, 0, C2, C1, 1)
4339 || reg->value == CPENC (3, 0, C2, C1, 2)
4340 || reg->value == CPENC (3, 0, C2, C1, 3)
4341 || reg->value == CPENC (3, 0, C2, C2, 0)
4342 || reg->value == CPENC (3, 0, C2, C2, 1)
4343 || reg->value == CPENC (3, 0, C2, C2, 2)
4344 || reg->value == CPENC (3, 0, C2, C2, 3)
4345 || reg->value == CPENC (3, 0, C2, C3, 0)
4346 || reg->value == CPENC (3, 0, C2, C3, 1))
4347 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_3))
4348 return FALSE;
4349
773fb663
RS		 4350 /* SVE. */
4351 if ((reg->value == CPENC (3, 0, C0, C4, 4)
4352 || reg->value == CPENC (3, 0, C1, C2, 0)
4353 || reg->value == CPENC (3, 4, C1, C2, 0)
4354 || reg->value == CPENC (3, 6, C1, C2, 0)
4355 || reg->value == CPENC (3, 5, C1, C2, 0)
4356 || reg->value == CPENC (3, 0, C0, C0, 7))
4357 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SVE))
4358 return FALSE;
4359
793a1948
TC		 4360 /* ARMv8.4 features. */
4361
4362 /* PSTATE.DIT. */
4363 if (reg->value == CPEN_ (3, C2, 5)
4364 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4365 return FALSE;
4366
4367 /* Virtualization extensions. */
4368 if ((reg->value == CPENC(3, 4, C2, C6, 2)
4369 || reg->value == CPENC(3, 4, C2, C6, 0)
4370 || reg->value == CPENC(3, 4, C14, C4, 0)
4371 || reg->value == CPENC(3, 4, C14, C4, 2)
4372 || reg->value == CPENC(3, 4, C14, C4, 1)
4373 || reg->value == CPENC(3, 4, C14, C5, 0)
4374 || reg->value == CPENC(3, 4, C14, C5, 2)
4375 || reg->value == CPENC(3, 4, C14, C5, 1)
4376 || reg->value == CPENC(3, 4, C1, C3, 1)
4377 || reg->value == CPENC(3, 4, C2, C2, 0))
4378 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4379 return FALSE;
4380
4381 /* ARMv8.4 TLB instructions. */
4382 if ((reg->value == CPENS (0, C8, C1, 0)
4383 || reg->value == CPENS (0, C8, C1, 1)
4384 || reg->value == CPENS (0, C8, C1, 2)
4385 || reg->value == CPENS (0, C8, C1, 3)
4386 || reg->value == CPENS (0, C8, C1, 5)
4387 || reg->value == CPENS (0, C8, C1, 7)
4388 || reg->value == CPENS (4, C8, C4, 0)
4389 || reg->value == CPENS (4, C8, C4, 4)
4390 || reg->value == CPENS (4, C8, C1, 1)
4391 || reg->value == CPENS (4, C8, C1, 5)
4392 || reg->value == CPENS (4, C8, C1, 6)
4393 || reg->value == CPENS (6, C8, C1, 1)
4394 || reg->value == CPENS (6, C8, C1, 5)
4395 || reg->value == CPENS (4, C8, C1, 0)
4396 || reg->value == CPENS (4, C8, C1, 4)
4397 || reg->value == CPENS (6, C8, C1, 0)
4398 || reg->value == CPENS (0, C8, C6, 1)
4399 || reg->value == CPENS (0, C8, C6, 3)
4400 || reg->value == CPENS (0, C8, C6, 5)
4401 || reg->value == CPENS (0, C8, C6, 7)
4402 || reg->value == CPENS (0, C8, C2, 1)
4403 || reg->value == CPENS (0, C8, C2, 3)
4404 || reg->value == CPENS (0, C8, C2, 5)
4405 || reg->value == CPENS (0, C8, C2, 7)
4406 || reg->value == CPENS (0, C8, C5, 1)
4407 || reg->value == CPENS (0, C8, C5, 3)
4408 || reg->value == CPENS (0, C8, C5, 5)
4409 || reg->value == CPENS (0, C8, C5, 7)
4410 || reg->value == CPENS (4, C8, C0, 2)
4411 || reg->value == CPENS (4, C8, C0, 6)
4412 || reg->value == CPENS (4, C8, C4, 2)
4413 || reg->value == CPENS (4, C8, C4, 6)
4414 || reg->value == CPENS (4, C8, C4, 3)
4415 || reg->value == CPENS (4, C8, C4, 7)
4416 || reg->value == CPENS (4, C8, C6, 1)
4417 || reg->value == CPENS (4, C8, C6, 5)
4418 || reg->value == CPENS (4, C8, C2, 1)
4419 || reg->value == CPENS (4, C8, C2, 5)
4420 || reg->value == CPENS (4, C8, C5, 1)
4421 || reg->value == CPENS (4, C8, C5, 5)
4422 || reg->value == CPENS (6, C8, C6, 1)
4423 || reg->value == CPENS (6, C8, C6, 5)
4424 || reg->value == CPENS (6, C8, C2, 1)
4425 || reg->value == CPENS (6, C8, C2, 5)
4426 || reg->value == CPENS (6, C8, C5, 1)
4427 || reg->value == CPENS (6, C8, C5, 5))
4428 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4429 return FALSE;
4430
af4bcb4c
SD		 4431 /* Random Number Instructions. For now they are available
4432 (and optional) only with ARMv8.5-A. */
4433 if ((reg->value == CPENC (3, 3, C2, C4, 0)
4434 || reg->value == CPENC (3, 3, C2, C4, 1))
4435 && !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RNG)
4436 && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_5)))
4437 return FALSE;
4438
70f3d23a
SD		 4439 /* System Registers in ARMv8.5-A with AARCH64_FEATURE_MEMTAG. */
4440 if ((reg->value == CPENC (3, 3, C4, C2, 7)
4441 || reg->value == CPENC (3, 0, C6, C6, 1)
4442 || reg->value == CPENC (3, 0, C6, C5, 0)
4443 || reg->value == CPENC (3, 4, C6, C5, 0)
4444 || reg->value == CPENC (3, 6, C6, C6, 0)
4445 || reg->value == CPENC (3, 5, C6, C6, 0)
4446 || reg->value == CPENC (3, 0, C1, C0, 5)
4447 || reg->value == CPENC (3, 0, C1, C0, 6))
4448 && !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG)))
4449 return FALSE;
4450
f21cce2c
MW		 4451 return TRUE;
4452}
4453
793a1948
TC		 4454/* The CPENC below is fairly misleading, the fields
4455 here are not in CPENC form. They are in op2op1 form. The fields are encoded
4456 by ins_pstatefield, which just shifts the value by the width of the fields
4457 in a loop. So if you CPENC them only the first value will be set, the rest
4458 are masked out to 0. As an example. op2 = 3, op1=2. CPENC would produce a
4459 value of 0b110000000001000000 (0x30040) while what you want is
4460 0b011010 (0x1a). */
87b8eed7 4461const aarch64_sys_reg aarch64_pstatefields [] =
a06ea964 4462{
87b8eed7
YZ		 4463 { "spsel", 0x05, 0 },
4464 { "daifset", 0x1e, 0 },
4465 { "daifclr", 0x1f, 0 },
f21cce2c 4466 { "pan", 0x04, F_ARCHEXT },
6479e48e 4467 { "uao", 0x03, F_ARCHEXT },
104fefee 4468 { "ssbs", 0x19, F_ARCHEXT },
793a1948 4469 { "dit", 0x1a, F_ARCHEXT },
70f3d23a 4470 { "tco", 0x1c, F_ARCHEXT },
87b8eed7 4471 { 0, CPENC(0,0,0,0,0), 0 },
a06ea964
NC		 4472};
4473
f21cce2c
MW		 4474bfd_boolean
4475aarch64_pstatefield_supported_p (const aarch64_feature_set features,
4476 const aarch64_sys_reg *reg)
4477{
4478 if (!(reg->flags & F_ARCHEXT))
4479 return TRUE;
4480
4481 /* PAN. Values are from aarch64_pstatefields. */
4482 if (reg->value == 0x04
4483 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
4484 return FALSE;
4485
6479e48e
MW		 4486 /* UAO. Values are from aarch64_pstatefields. */
4487 if (reg->value == 0x03
4488 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4489 return FALSE;
4490
104fefee
SD		 4491 /* SSBS. Values are from aarch64_pstatefields. */
4492 if (reg->value == 0x19
4493 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS))
4494 return FALSE;
4495
793a1948
TC		 4496 /* DIT. Values are from aarch64_pstatefields. */
4497 if (reg->value == 0x1a
4498 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4499 return FALSE;
4500
70f3d23a
SD		 4501 /* TCO. Values are from aarch64_pstatefields. */
4502 if (reg->value == 0x1c
4503 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG))
4504 return FALSE;
4505
f21cce2c
MW		 4506 return TRUE;
4507}
4508
a06ea964
NC		 4509const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =
4510{
4511 { "ialluis", CPENS(0,C7,C1,0), 0 },
4512 { "iallu", CPENS(0,C7,C5,0), 0 },
ea2deeec 4513 { "ivau", CPENS (3, C7, C5, 1), F_HASXT },
a06ea964
NC		 4514 { 0, CPENS(0,0,0,0), 0 }
4515};
4516
4517const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
4518{
ea2deeec 4519 { "zva", CPENS (3, C7, C4, 1), F_HASXT },
3a0f69be
SD		 4520 { "gva", CPENS (3, C7, C4, 3), F_HASXT | F_ARCHEXT },
4521 { "gzva", CPENS (3, C7, C4, 4), F_HASXT | F_ARCHEXT },
ea2deeec 4522 { "ivac", CPENS (0, C7, C6, 1), F_HASXT },
3a0f69be
SD		 4523 { "igvac", CPENS (0, C7, C6, 3), F_HASXT | F_ARCHEXT },
4524 { "igsw", CPENS (0, C7, C6, 4), F_HASXT | F_ARCHEXT },
ea2deeec 4525 { "isw", CPENS (0, C7, C6, 2), F_HASXT },
3a0f69be
SD		 4526 { "igdvac", CPENS (0, C7, C6, 5), F_HASXT | F_ARCHEXT },
4527 { "igdsw", CPENS (0, C7, C6, 6), F_HASXT | F_ARCHEXT },
ea2deeec 4528 { "cvac", CPENS (3, C7, C10, 1), F_HASXT },
3a0f69be
SD		 4529 { "cgvac", CPENS (3, C7, C10, 3), F_HASXT | F_ARCHEXT },
4530 { "cgdvac", CPENS (3, C7, C10, 5), F_HASXT | F_ARCHEXT },
ea2deeec 4531 { "csw", CPENS (0, C7, C10, 2), F_HASXT },
3a0f69be
SD		 4532 { "cgsw", CPENS (0, C7, C10, 4), F_HASXT | F_ARCHEXT },
4533 { "cgdsw", CPENS (0, C7, C10, 6), F_HASXT | F_ARCHEXT },
ea2deeec 4534 { "cvau", CPENS (3, C7, C11, 1), F_HASXT },
d6bf7ce6 4535 { "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
3a0f69be
SD		 4536 { "cgvap", CPENS (3, C7, C12, 3), F_HASXT | F_ARCHEXT },
4537 { "cgdvap", CPENS (3, C7, C12, 5), F_HASXT | F_ARCHEXT },
3fd229a4 4538 { "cvadp", CPENS (3, C7, C13, 1), F_HASXT | F_ARCHEXT },
3a0f69be
SD		 4539 { "cgvadp", CPENS (3, C7, C13, 3), F_HASXT | F_ARCHEXT },
4540 { "cgdvadp", CPENS (3, C7, C13, 5), F_HASXT | F_ARCHEXT },
ea2deeec 4541 { "civac", CPENS (3, C7, C14, 1), F_HASXT },
3a0f69be
SD		 4542 { "cigvac", CPENS (3, C7, C14, 3), F_HASXT | F_ARCHEXT },
4543 { "cigdvac", CPENS (3, C7, C14, 5), F_HASXT | F_ARCHEXT },
ea2deeec 4544 { "cisw", CPENS (0, C7, C14, 2), F_HASXT },
3a0f69be
SD		 4545 { "cigsw", CPENS (0, C7, C14, 4), F_HASXT | F_ARCHEXT },
4546 { "cigdsw", CPENS (0, C7, C14, 6), F_HASXT | F_ARCHEXT },
a06ea964
NC		 4547 { 0, CPENS(0,0,0,0), 0 }
4548};
4549
4550const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
4551{
ea2deeec
MW		 4552 { "s1e1r", CPENS (0, C7, C8, 0), F_HASXT },
4553 { "s1e1w", CPENS (0, C7, C8, 1), F_HASXT },
4554 { "s1e0r", CPENS (0, C7, C8, 2), F_HASXT },
4555 { "s1e0w", CPENS (0, C7, C8, 3), F_HASXT },
4556 { "s12e1r", CPENS (4, C7, C8, 4), F_HASXT },
4557 { "s12e1w", CPENS (4, C7, C8, 5), F_HASXT },
4558 { "s12e0r", CPENS (4, C7, C8, 6), F_HASXT },
4559 { "s12e0w", CPENS (4, C7, C8, 7), F_HASXT },
4560 { "s1e2r", CPENS (4, C7, C8, 0), F_HASXT },
4561 { "s1e2w", CPENS (4, C7, C8, 1), F_HASXT },
4562 { "s1e3r", CPENS (6, C7, C8, 0), F_HASXT },
4563 { "s1e3w", CPENS (6, C7, C8, 1), F_HASXT },
22a5455c
MW		 4564 { "s1e1rp", CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT },
4565 { "s1e1wp", CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT },
a06ea964
NC		 4566 { 0, CPENS(0,0,0,0), 0 }
4567};
4568
4569const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
4570{
4571 { "vmalle1", CPENS(0,C8,C7,0), 0 },
ea2deeec
MW		 4572 { "vae1", CPENS (0, C8, C7, 1), F_HASXT },
4573 { "aside1", CPENS (0, C8, C7, 2), F_HASXT },
4574 { "vaae1", CPENS (0, C8, C7, 3), F_HASXT },
a06ea964 4575 { "vmalle1is", CPENS(0,C8,C3,0), 0 },
ea2deeec
MW		 4576 { "vae1is", CPENS (0, C8, C3, 1), F_HASXT },
4577 { "aside1is", CPENS (0, C8, C3, 2), F_HASXT },
4578 { "vaae1is", CPENS (0, C8, C3, 3), F_HASXT },
4579 { "ipas2e1is", CPENS (4, C8, C0, 1), F_HASXT },
4580 { "ipas2le1is",CPENS (4, C8, C0, 5), F_HASXT },
4581 { "ipas2e1", CPENS (4, C8, C4, 1), F_HASXT },
4582 { "ipas2le1", CPENS (4, C8, C4, 5), F_HASXT },
4583 { "vae2", CPENS (4, C8, C7, 1), F_HASXT },
4584 { "vae2is", CPENS (4, C8, C3, 1), F_HASXT },
a06ea964
NC		 4585 { "vmalls12e1",CPENS(4,C8,C7,6), 0 },
4586 { "vmalls12e1is",CPENS(4,C8,C3,6), 0 },
ea2deeec
MW		 4587 { "vae3", CPENS (6, C8, C7, 1), F_HASXT },
4588 { "vae3is", CPENS (6, C8, C3, 1), F_HASXT },
a06ea964
NC		 4589 { "alle2", CPENS(4,C8,C7,0), 0 },
4590 { "alle2is", CPENS(4,C8,C3,0), 0 },
4591 { "alle1", CPENS(4,C8,C7,4), 0 },
4592 { "alle1is", CPENS(4,C8,C3,4), 0 },
4593 { "alle3", CPENS(6,C8,C7,0), 0 },
4594 { "alle3is", CPENS(6,C8,C3,0), 0 },
ea2deeec
MW		 4595 { "vale1is", CPENS (0, C8, C3, 5), F_HASXT },
4596 { "vale2is", CPENS (4, C8, C3, 5), F_HASXT },
4597 { "vale3is", CPENS (6, C8, C3, 5), F_HASXT },
4598 { "vaale1is", CPENS (0, C8, C3, 7), F_HASXT },
4599 { "vale1", CPENS (0, C8, C7, 5), F_HASXT },
4600 { "vale2", CPENS (4, C8, C7, 5), F_HASXT },
4601 { "vale3", CPENS (6, C8, C7, 5), F_HASXT },
4602 { "vaale1", CPENS (0, C8, C7, 7), F_HASXT },
793a1948
TC		 4603
4604 { "vmalle1os", CPENS (0, C8, C1, 0), F_ARCHEXT },
4605 { "vae1os", CPENS (0, C8, C1, 1), F_HASXT | F_ARCHEXT },
4606 { "aside1os", CPENS (0, C8, C1, 2), F_HASXT | F_ARCHEXT },
4607 { "vaae1os", CPENS (0, C8, C1, 3), F_HASXT | F_ARCHEXT },
4608 { "vale1os", CPENS (0, C8, C1, 5), F_HASXT | F_ARCHEXT },
4609 { "vaale1os", CPENS (0, C8, C1, 7), F_HASXT | F_ARCHEXT },
4610 { "ipas2e1os", CPENS (4, C8, C4, 0), F_HASXT | F_ARCHEXT },
4611 { "ipas2le1os", CPENS (4, C8, C4, 4), F_HASXT | F_ARCHEXT },
4612 { "vae2os", CPENS (4, C8, C1, 1), F_HASXT | F_ARCHEXT },
4613 { "vale2os", CPENS (4, C8, C1, 5), F_HASXT | F_ARCHEXT },
4614 { "vmalls12e1os", CPENS (4, C8, C1, 6), F_ARCHEXT },
4615 { "vae3os", CPENS (6, C8, C1, 1), F_HASXT | F_ARCHEXT },
4616 { "vale3os", CPENS (6, C8, C1, 5), F_HASXT | F_ARCHEXT },
4617 { "alle2os", CPENS (4, C8, C1, 0), F_ARCHEXT },
4618 { "alle1os", CPENS (4, C8, C1, 4), F_ARCHEXT },
4619 { "alle3os", CPENS (6, C8, C1, 0), F_ARCHEXT },
4620
4621 { "rvae1", CPENS (0, C8, C6, 1), F_HASXT | F_ARCHEXT },
4622 { "rvaae1", CPENS (0, C8, C6, 3), F_HASXT | F_ARCHEXT },
4623 { "rvale1", CPENS (0, C8, C6, 5), F_HASXT | F_ARCHEXT },
4624 { "rvaale1", CPENS (0, C8, C6, 7), F_HASXT | F_ARCHEXT },
4625 { "rvae1is", CPENS (0, C8, C2, 1), F_HASXT | F_ARCHEXT },
4626 { "rvaae1is", CPENS (0, C8, C2, 3), F_HASXT | F_ARCHEXT },
4627 { "rvale1is", CPENS (0, C8, C2, 5), F_HASXT | F_ARCHEXT },
4628 { "rvaale1is", CPENS (0, C8, C2, 7), F_HASXT | F_ARCHEXT },
4629 { "rvae1os", CPENS (0, C8, C5, 1), F_HASXT | F_ARCHEXT },
4630 { "rvaae1os", CPENS (0, C8, C5, 3), F_HASXT | F_ARCHEXT },
4631 { "rvale1os", CPENS (0, C8, C5, 5), F_HASXT | F_ARCHEXT },
4632 { "rvaale1os", CPENS (0, C8, C5, 7), F_HASXT | F_ARCHEXT },
4633 { "ripas2e1is", CPENS (4, C8, C0, 2), F_HASXT | F_ARCHEXT },
4634 { "ripas2le1is",CPENS (4, C8, C0, 6), F_HASXT | F_ARCHEXT },
4635 { "ripas2e1", CPENS (4, C8, C4, 2), F_HASXT | F_ARCHEXT },
4636 { "ripas2le1", CPENS (4, C8, C4, 6), F_HASXT | F_ARCHEXT },
4637 { "ripas2e1os", CPENS (4, C8, C4, 3), F_HASXT | F_ARCHEXT },
4638 { "ripas2le1os",CPENS (4, C8, C4, 7), F_HASXT | F_ARCHEXT },
4639 { "rvae2", CPENS (4, C8, C6, 1), F_HASXT | F_ARCHEXT },
4640 { "rvale2", CPENS (4, C8, C6, 5), F_HASXT | F_ARCHEXT },
4641 { "rvae2is", CPENS (4, C8, C2, 1), F_HASXT | F_ARCHEXT },
4642 { "rvale2is", CPENS (4, C8, C2, 5), F_HASXT | F_ARCHEXT },
4643 { "rvae2os", CPENS (4, C8, C5, 1), F_HASXT | F_ARCHEXT },
4644 { "rvale2os", CPENS (4, C8, C5, 5), F_HASXT | F_ARCHEXT },
4645 { "rvae3", CPENS (6, C8, C6, 1), F_HASXT | F_ARCHEXT },
4646 { "rvale3", CPENS (6, C8, C6, 5), F_HASXT | F_ARCHEXT },
4647 { "rvae3is", CPENS (6, C8, C2, 1), F_HASXT | F_ARCHEXT },
4648 { "rvale3is", CPENS (6, C8, C2, 5), F_HASXT | F_ARCHEXT },
4649 { "rvae3os", CPENS (6, C8, C5, 1), F_HASXT | F_ARCHEXT },
4650 { "rvale3os", CPENS (6, C8, C5, 5), F_HASXT | F_ARCHEXT },
4651
a06ea964
NC		 4652 { 0, CPENS(0,0,0,0), 0 }
4653};
4654
2ac435d4
SD		 4655const aarch64_sys_ins_reg aarch64_sys_regs_sr[] =
4656{
4657 /* RCTX is somewhat unique in a way that it has different values
4658 (op2) based on the instruction in which it is used (cfp/dvp/cpp).
4659 Thus op2 is masked out and instead encoded directly in the
4660 aarch64_opcode_table entries for the respective instructions. */
4661 { "rctx", CPENS(3,C7,C3,0), F_HASXT | F_ARCHEXT | F_REG_WRITE}, /* WO */
4662
4663 { 0, CPENS(0,0,0,0), 0 }
4664};
4665
ea2deeec
MW		 4666bfd_boolean
4667aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
4668{
4669 return (sys_ins_reg->flags & F_HASXT) != 0;
4670}
4671
d6bf7ce6
MW		 4672extern bfd_boolean
4673aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
4674 const aarch64_sys_ins_reg *reg)
4675{
4676 if (!(reg->flags & F_ARCHEXT))
4677 return TRUE;
4678
4679 /* DC CVAP. Values are from aarch64_sys_regs_dc. */
4680 if (reg->value == CPENS (3, C7, C12, 1)
4681 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4682 return FALSE;
4683
3fd229a4
SD		 4684 /* DC CVADP. Values are from aarch64_sys_regs_dc. */
4685 if (reg->value == CPENS (3, C7, C13, 1)
4686 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_CVADP))
4687 return FALSE;
4688
3a0f69be
SD		 4689 /* DC <dc_op> for ARMv8.5-A Memory Tagging Extension. */
4690 if ((reg->value == CPENS (0, C7, C6, 3)
4691 || reg->value == CPENS (0, C7, C6, 4)
4692 || reg->value == CPENS (0, C7, C10, 4)
4693 || reg->value == CPENS (0, C7, C14, 4)
4694 || reg->value == CPENS (3, C7, C10, 3)
4695 || reg->value == CPENS (3, C7, C12, 3)
4696 || reg->value == CPENS (3, C7, C13, 3)
4697 || reg->value == CPENS (3, C7, C14, 3)
4698 || reg->value == CPENS (3, C7, C4, 3)
4699 || reg->value == CPENS (0, C7, C6, 5)
4700 || reg->value == CPENS (0, C7, C6, 6)
4701 || reg->value == CPENS (0, C7, C10, 6)
4702 || reg->value == CPENS (0, C7, C14, 6)
4703 || reg->value == CPENS (3, C7, C10, 5)
4704 || reg->value == CPENS (3, C7, C12, 5)
4705 || reg->value == CPENS (3, C7, C13, 5)
4706 || reg->value == CPENS (3, C7, C14, 5)
4707 || reg->value == CPENS (3, C7, C4, 4))
4708 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG))
4709 return FALSE;
4710
63511907
MW		 4711 /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
4712 if ((reg->value == CPENS (0, C7, C9, 0)
4713 || reg->value == CPENS (0, C7, C9, 1))
4714 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4715 return FALSE;
4716
2ac435d4
SD		 4717 /* CFP/DVP/CPP RCTX : Value are from aarch64_sys_regs_sr. */
4718 if (reg->value == CPENS (3, C7, C3, 0)
4719 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PREDRES))
4720 return FALSE;
4721
d6bf7ce6
MW		 4722 return TRUE;
4723}
4724
a06ea964
NC		 4725#undef C0
4726#undef C1
4727#undef C2
4728#undef C3
4729#undef C4
4730#undef C5
4731#undef C6
4732#undef C7
4733#undef C8
4734#undef C9
4735#undef C10
4736#undef C11
4737#undef C12
4738#undef C13
4739#undef C14
4740#undef C15
4741
4bd13cde
NC		 4742#define BIT(INSN,BT) (((INSN) >> (BT)) & 1)
4743#define BITS(INSN,HI,LO) (((INSN) >> (LO)) & ((1 << (((HI) - (LO)) + 1)) - 1))
4744
755b748f
TC		 4745static enum err_type
4746verify_ldpsw (const struct aarch64_inst *inst ATTRIBUTE_UNUSED,
4747 const aarch64_insn insn, bfd_vma pc ATTRIBUTE_UNUSED,
4748 bfd_boolean encoding ATTRIBUTE_UNUSED,
4749 aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
a68f4cd2 4750 aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
4bd13cde
NC		 4751{
4752 int t = BITS (insn, 4, 0);
4753 int n = BITS (insn, 9, 5);
4754 int t2 = BITS (insn, 14, 10);
4755
4756 if (BIT (insn, 23))
4757 {
4758 /* Write back enabled. */
4759 if ((t == n || t2 == n) && n != 31)
755b748f 4760 return ERR_UND;
4bd13cde
NC		 4761 }
4762
4763 if (BIT (insn, 22))
4764 {
4765 /* Load */
4766 if (t == t2)
755b748f 4767 return ERR_UND;
4bd13cde
NC		 4768 }
4769
755b748f 4770 return ERR_OK;
4bd13cde
NC		 4771}
4772
6456d318
TC		 4773/* Verifier for vector by element 3 operands functions where the
4774 conditions `if sz:L == 11 then UNDEFINED` holds. */
4775
4776static enum err_type
4777verify_elem_sd (const struct aarch64_inst *inst, const aarch64_insn insn,
4778 bfd_vma pc ATTRIBUTE_UNUSED, bfd_boolean encoding,
4779 aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
4780 aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
4781{
4782 const aarch64_insn undef_pattern = 0x3;
4783 aarch64_insn value;
4784
4785 assert (inst->opcode);
4786 assert (inst->opcode->operands[2] == AARCH64_OPND_Em);
4787 value = encoding ? inst->value : insn;
4788 assert (value);
4789
4790 if (undef_pattern == extract_fields (value, 0, 2, FLD_sz, FLD_L))
4791 return ERR_UND;
4792
4793 return ERR_OK;
4794}
4795
a68f4cd2
TC		 4796/* Initialize an instruction sequence insn_sequence with the instruction INST.
4797 If INST is NULL the given insn_sequence is cleared and the sequence is left
4798 uninitialized. */
4799
4800void
4801init_insn_sequence (const struct aarch64_inst *inst,
4802 aarch64_instr_sequence *insn_sequence)
4803{
4804 int num_req_entries = 0;
4805 insn_sequence->next_insn = 0;
4806 insn_sequence->num_insns = num_req_entries;
4807 if (insn_sequence->instr)
4808 XDELETE (insn_sequence->instr);
4809 insn_sequence->instr = NULL;
4810
4811 if (inst)
4812 {
4813 insn_sequence->instr = XNEW (aarch64_inst);
4814 memcpy (insn_sequence->instr, inst, sizeof (aarch64_inst));
4815 }
4816
4817 /* Handle all the cases here. May need to think of something smarter than
4818 a giant if/else chain if this grows. At that time, a lookup table may be
4819 best. */
4820 if (inst && inst->opcode->constraints & C_SCAN_MOVPRFX)
4821 num_req_entries = 1;
4822
4823 if (insn_sequence->current_insns)
4824 XDELETEVEC (insn_sequence->current_insns);
4825 insn_sequence->current_insns = NULL;
4826
4827 if (num_req_entries != 0)
4828 {
4829 size_t size = num_req_entries * sizeof (aarch64_inst);
4830 insn_sequence->current_insns
4831 = (aarch64_inst**) XNEWVEC (aarch64_inst, num_req_entries);
4832 memset (insn_sequence->current_insns, 0, size);
4833 }
4834}
4835
4836
4837/* This function verifies that the instruction INST adheres to its specified
4838 constraints. If it does then ERR_OK is returned, if not then ERR_VFI is
4839 returned and MISMATCH_DETAIL contains the reason why verification failed.
4840
4841 The function is called both during assembly and disassembly. If assembling
4842 then ENCODING will be TRUE, else FALSE. If dissassembling PC will be set
4843 and will contain the PC of the current instruction w.r.t to the section.
4844
4845 If ENCODING and PC=0 then you are at a start of a section. The constraints
4846 are verified against the given state insn_sequence which is updated as it
4847 transitions through the verification. */
4848
4849enum err_type
4850verify_constraints (const struct aarch64_inst *inst,
4851 const aarch64_insn insn ATTRIBUTE_UNUSED,
4852 bfd_vma pc,
4853 bfd_boolean encoding,
4854 aarch64_operand_error *mismatch_detail,
4855 aarch64_instr_sequence *insn_sequence)
4856{
4857 assert (inst);
4858 assert (inst->opcode);
4859
4860 const struct aarch64_opcode *opcode = inst->opcode;
4861 if (!opcode->constraints && !insn_sequence->instr)
4862 return ERR_OK;
4863
4864 assert (insn_sequence);
4865
4866 enum err_type res = ERR_OK;
4867
4868 /* This instruction puts a constraint on the insn_sequence. */
4869 if (opcode->flags & F_SCAN)
4870 {
4871 if (insn_sequence->instr)
4872 {
4873 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4874 mismatch_detail->error = _("instruction opens new dependency "
4875 "sequence without ending previous one");
4876 mismatch_detail->index = -1;
4877 mismatch_detail->non_fatal = TRUE;
4878 res = ERR_VFI;
4879 }
4880
4881 init_insn_sequence (inst, insn_sequence);
4882 return res;
4883 }
4884
4885 /* Verify constraints on an existing sequence. */
4886 if (insn_sequence->instr)
4887 {
4888 const struct aarch64_opcode* inst_opcode = insn_sequence->instr->opcode;
4889 /* If we're decoding and we hit PC=0 with an open sequence then we haven't
4890 closed a previous one that we should have. */
4891 if (!encoding && pc == 0)
4892 {
4893 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4894 mismatch_detail->error = _("previous `movprfx' sequence not closed");
4895 mismatch_detail->index = -1;
4896 mismatch_detail->non_fatal = TRUE;
4897 res = ERR_VFI;
4898 /* Reset the sequence. */
4899 init_insn_sequence (NULL, insn_sequence);
4900 return res;
4901 }
4902
4903 /* Validate C_SCAN_MOVPRFX constraints. Move this to a lookup table. */
4904 if (inst_opcode->constraints & C_SCAN_MOVPRFX)
4905 {
4906 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4907 instruction for better error messages. */
5cd99750
MM		 4908 if (!opcode->avariant
4909 || !(*opcode->avariant &
4910 (AARCH64_FEATURE_SVE | AARCH64_FEATURE_SVE2)))
a68f4cd2
TC		 4911 {
4912 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4913 mismatch_detail->error = _("SVE instruction expected after "
4914 "`movprfx'");
4915 mismatch_detail->index = -1;
4916 mismatch_detail->non_fatal = TRUE;
4917 res = ERR_VFI;
4918 goto done;
4919 }
4920
4921 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4922 instruction that is allowed to be used with a MOVPRFX. */
4923 if (!(opcode->constraints & C_SCAN_MOVPRFX))
4924 {
4925 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4926 mismatch_detail->error = _("SVE `movprfx' compatible instruction "
4927 "expected");
4928 mismatch_detail->index = -1;
4929 mismatch_detail->non_fatal = TRUE;
4930 res = ERR_VFI;
4931 goto done;
4932 }
4933
4934 /* Next check for usage of the predicate register. */
4935 aarch64_opnd_info blk_dest = insn_sequence->instr->operands[0];
780f601c
TC		 4936 aarch64_opnd_info blk_pred, inst_pred;
4937 memset (&blk_pred, 0, sizeof (aarch64_opnd_info));
4938 memset (&inst_pred, 0, sizeof (aarch64_opnd_info));
a68f4cd2
TC		 4939 bfd_boolean predicated = FALSE;
4940 assert (blk_dest.type == AARCH64_OPND_SVE_Zd);
4941
4942 /* Determine if the movprfx instruction used is predicated or not. */
4943 if (insn_sequence->instr->operands[1].type == AARCH64_OPND_SVE_Pg3)
4944 {
4945 predicated = TRUE;
4946 blk_pred = insn_sequence->instr->operands[1];
4947 }
4948
4949 unsigned char max_elem_size = 0;
4950 unsigned char current_elem_size;
4951 int num_op_used = 0, last_op_usage = 0;
4952 int i, inst_pred_idx = -1;
4953 int num_ops = aarch64_num_of_operands (opcode);
4954 for (i = 0; i < num_ops; i++)
4955 {
4956 aarch64_opnd_info inst_op = inst->operands[i];
4957 switch (inst_op.type)
4958 {
4959 case AARCH64_OPND_SVE_Zd:
4960 case AARCH64_OPND_SVE_Zm_5:
4961 case AARCH64_OPND_SVE_Zm_16:
4962 case AARCH64_OPND_SVE_Zn:
4963 case AARCH64_OPND_SVE_Zt:
4964 case AARCH64_OPND_SVE_Vm:
4965 case AARCH64_OPND_SVE_Vn:
4966 case AARCH64_OPND_Va:
4967 case AARCH64_OPND_Vn:
4968 case AARCH64_OPND_Vm:
4969 case AARCH64_OPND_Sn:
4970 case AARCH64_OPND_Sm:
a68f4cd2
TC		 4971 if (inst_op.reg.regno == blk_dest.reg.regno)
4972 {
4973 num_op_used++;
4974 last_op_usage = i;
4975 }
4976 current_elem_size
4977 = aarch64_get_qualifier_esize (inst_op.qualifier);
4978 if (current_elem_size > max_elem_size)
4979 max_elem_size = current_elem_size;
4980 break;
4981 case AARCH64_OPND_SVE_Pd:
4982 case AARCH64_OPND_SVE_Pg3:
4983 case AARCH64_OPND_SVE_Pg4_5:
4984 case AARCH64_OPND_SVE_Pg4_10:
4985 case AARCH64_OPND_SVE_Pg4_16:
4986 case AARCH64_OPND_SVE_Pm:
4987 case AARCH64_OPND_SVE_Pn:
4988 case AARCH64_OPND_SVE_Pt:
4989 inst_pred = inst_op;
4990 inst_pred_idx = i;
4991 break;
4992 default:
4993 break;
4994 }
4995 }
4996
4997 assert (max_elem_size != 0);
4998 aarch64_opnd_info inst_dest = inst->operands[0];
4999 /* Determine the size that should be used to compare against the
5000 movprfx size. */
5001 current_elem_size
5002 = opcode->constraints & C_MAX_ELEM
5003 ? max_elem_size
5004 : aarch64_get_qualifier_esize (inst_dest.qualifier);
5005
5006 /* If movprfx is predicated do some extra checks. */
5007 if (predicated)
5008 {
5009 /* The instruction must be predicated. */
5010 if (inst_pred_idx < 0)
5011 {
5012 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5013 mismatch_detail->error = _("predicated instruction expected "
5014 "after `movprfx'");
5015 mismatch_detail->index = -1;
5016 mismatch_detail->non_fatal = TRUE;
5017 res = ERR_VFI;
5018 goto done;
5019 }
5020
5021 /* The instruction must have a merging predicate. */
5022 if (inst_pred.qualifier != AARCH64_OPND_QLF_P_M)
5023 {
5024 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5025 mismatch_detail->error = _("merging predicate expected due "
5026 "to preceding `movprfx'");
5027 mismatch_detail->index = inst_pred_idx;
5028 mismatch_detail->non_fatal = TRUE;
5029 res = ERR_VFI;
5030 goto done;
5031 }
5032
5033 /* The same register must be used in instruction. */
5034 if (blk_pred.reg.regno != inst_pred.reg.regno)
5035 {
5036 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5037 mismatch_detail->error = _("predicate register differs "
5038 "from that in preceding "
5039 "`movprfx'");
5040 mismatch_detail->index = inst_pred_idx;
5041 mismatch_detail->non_fatal = TRUE;
5042 res = ERR_VFI;
5043 goto done;
5044 }
5045 }
5046
5047 /* Destructive operations by definition must allow one usage of the
5048 same register. */
5049 int allowed_usage
5050 = aarch64_is_destructive_by_operands (opcode) ? 2 : 1;
5051
5052 /* Operand is not used at all. */
5053 if (num_op_used == 0)
5054 {
5055 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5056 mismatch_detail->error = _("output register of preceding "
5057 "`movprfx' not used in current "
5058 "instruction");
5059 mismatch_detail->index = 0;
5060 mismatch_detail->non_fatal = TRUE;
5061 res = ERR_VFI;
5062 goto done;
5063 }
5064
5065 /* We now know it's used, now determine exactly where it's used. */
5066 if (blk_dest.reg.regno != inst_dest.reg.regno)
5067 {
5068 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5069 mismatch_detail->error = _("output register of preceding "
5070 "`movprfx' expected as output");
5071 mismatch_detail->index = 0;
5072 mismatch_detail->non_fatal = TRUE;
5073 res = ERR_VFI;
5074 goto done;
5075 }
5076
5077 /* Operand used more than allowed for the specific opcode type. */
5078 if (num_op_used > allowed_usage)
5079 {
5080 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5081 mismatch_detail->error = _("output register of preceding "
5082 "`movprfx' used as input");
5083 mismatch_detail->index = last_op_usage;
5084 mismatch_detail->non_fatal = TRUE;
5085 res = ERR_VFI;
5086 goto done;
5087 }
5088
5089 /* Now the only thing left is the qualifiers checks. The register
5090 must have the same maximum element size. */
5091 if (inst_dest.qualifier
5092 && blk_dest.qualifier
5093 && current_elem_size
5094 != aarch64_get_qualifier_esize (blk_dest.qualifier))
5095 {
5096 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5097 mismatch_detail->error = _("register size not compatible with "
5098 "previous `movprfx'");
5099 mismatch_detail->index = 0;
5100 mismatch_detail->non_fatal = TRUE;
5101 res = ERR_VFI;
5102 goto done;
5103 }
5104 }
5105
5106done:
5107 /* Add the new instruction to the sequence. */
5108 memcpy (insn_sequence->current_insns + insn_sequence->next_insn++,
5109 inst, sizeof (aarch64_inst));
5110
5111 /* Check if sequence is now full. */
5112 if (insn_sequence->next_insn >= insn_sequence->num_insns)
5113 {
5114 /* Sequence is full, but we don't have anything special to do for now,
5115 so clear and reset it. */
5116 init_insn_sequence (NULL, insn_sequence);
5117 }
5118 }
5119
5120 return res;
5121}
5122
5123
e950b345
RS		 5124/* Return true if VALUE cannot be moved into an SVE register using DUP
5125 (with any element size, not just ESIZE) and if using DUPM would
5126 therefore be OK. ESIZE is the number of bytes in the immediate. */
5127
5128bfd_boolean
5129aarch64_sve_dupm_mov_immediate_p (uint64_t uvalue, int esize)
5130{
5131 int64_t svalue = uvalue;
5132 uint64_t upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
5133
5134 if ((uvalue & ~upper) != uvalue && (uvalue | upper) != uvalue)
5135 return FALSE;
5136 if (esize <= 4 || (uint32_t) uvalue == (uint32_t) (uvalue >> 32))
5137 {
5138 svalue = (int32_t) uvalue;
5139 if (esize <= 2 || (uint16_t) uvalue == (uint16_t) (uvalue >> 16))
5140 {
5141 svalue = (int16_t) uvalue;
5142 if (esize == 1 || (uint8_t) uvalue == (uint8_t) (uvalue >> 8))
5143 return FALSE;
5144 }
5145 }
5146 if ((svalue & 0xff) == 0)
5147 svalue /= 256;
5148 return svalue < -128 || svalue >= 128;
5149}
5150
a06ea964
NC		 5151/* Include the opcode description table as well as the operand description
5152 table. */
20f55f38 5153#define VERIFIER(x) verify_##x
a06ea964 5154#include "aarch64-tbl.h"
GDB Binutils - Deliverables
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