projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| a06ea964 NC |
1 | /* aarch64-tbl.h -- AArch64 opcode description table and instruction |
| 2 | operand description table. | |
| b90efa5b | 3 | Copyright (C) 2012-2015 Free Software Foundation, Inc. |
| a06ea964 NC |
4 | |
| 5 | This file is part of the GNU opcodes library. | |
| 6 | ||
| 7 | This library is free software; you can redistribute it and/or modify | |
| 8 | it under the terms of the GNU General Public License as published by | |
| 9 | the Free Software Foundation; either version 3, or (at your option) | |
| 10 | any later version. | |
| 11 | ||
| 12 | It is distributed in the hope that it will be useful, but WITHOUT | |
| 13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 15 | License for more details. | |
| 16 | ||
| 17 | You should have received a copy of the GNU General Public License | |
| 18 | along with this file; see the file COPYING. If not, write to the | |
| 19 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
| 20 | MA 02110-1301, USA. */ | |
| 21 | ||
| 22 | #include "aarch64-opc.h" | |
| 23 | ||
| 24 | /* Operand type. */ | |
| 25 | ||
| 26 | #define OPND(x) AARCH64_OPND_##x | |
| 27 | #define OP0() {} | |
| 28 | #define OP1(a) {OPND(a)} | |
| 29 | #define OP2(a,b) {OPND(a), OPND(b)} | |
| 30 | #define OP3(a,b,c) {OPND(a), OPND(b), OPND(c)} | |
| 31 | #define OP4(a,b,c,d) {OPND(a), OPND(b), OPND(c), OPND(d)} | |
| 32 | #define OP5(a,b,c,d,e) {OPND(a), OPND(b), OPND(c), OPND(d), OPND(e)} | |
| 33 | ||
| 34 | #define QLF(x) AARCH64_OPND_QLF_##x | |
| 35 | #define QLF1(a) {QLF(a)} | |
| 36 | #define QLF2(a,b) {QLF(a), QLF(b)} | |
| 37 | #define QLF3(a,b,c) {QLF(a), QLF(b), QLF(c)} | |
| 38 | #define QLF4(a,b,c,d) {QLF(a), QLF(b), QLF(c), QLF(d)} | |
| 39 | #define QLF5(a,b,c,d,e) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e)} | |
| 40 | ||
| 41 | /* Qualifiers list. */ | |
| 42 | ||
| 43 | /* e.g. MSR <systemreg>, <Xt>. */ | |
| 44 | #define QL_SRC_X \ | |
| 45 | { \ | |
| 46 | QLF2(NIL,X), \ | |
| 47 | } | |
| 48 | ||
| 49 | /* e.g. MRS <Xt>, <systemreg>. */ | |
| 50 | #define QL_DST_X \ | |
| 51 | { \ | |
| 52 | QLF2(X,NIL), \ | |
| 53 | } | |
| 54 | ||
| 55 | /* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */ | |
| 56 | #define QL_SYS \ | |
| 57 | { \ | |
| 58 | QLF5(NIL,NIL,NIL,NIL,X), \ | |
| 59 | } | |
| 60 | ||
| 61 | /* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>. */ | |
| 62 | #define QL_SYSL \ | |
| 63 | { \ | |
| 64 | QLF5(X,NIL,NIL,NIL,NIL), \ | |
| 65 | } | |
| 66 | ||
| 67 | /* e.g. ADRP <Xd>, <label>. */ | |
| 68 | #define QL_ADRP \ | |
| 69 | { \ | |
| 70 | QLF2(X,NIL), \ | |
| 71 | } | |
| 72 | ||
| 73 | /* e.g. B.<cond> <label>. */ | |
| 74 | #define QL_PCREL_NIL \ | |
| 75 | { \ | |
| 76 | QLF1(NIL), \ | |
| 77 | } | |
| 78 | ||
| 79 | /* e.g. TBZ <Xt>, #<imm>, <label>. */ | |
| 80 | #define QL_PCREL_14 \ | |
| 81 | { \ | |
| 82 | QLF3(X,imm_0_63,NIL), \ | |
| 83 | } | |
| 84 | ||
| 85 | /* e.g. BL <label>. */ | |
| 86 | #define QL_PCREL_26 \ | |
| 87 | { \ | |
| 88 | QLF1(NIL), \ | |
| 89 | } | |
| 90 | ||
| 91 | /* e.g. LDRSW <Xt>, <label>. */ | |
| 92 | #define QL_X_PCREL \ | |
| 93 | { \ | |
| 94 | QLF2(X,NIL), \ | |
| 95 | } | |
| 96 | ||
| 97 | /* e.g. LDR <Wt>, <label>. */ | |
| 98 | #define QL_R_PCREL \ | |
| 99 | { \ | |
| 100 | QLF2(W,NIL), \ | |
| 101 | QLF2(X,NIL), \ | |
| 102 | } | |
| 103 | ||
| 104 | /* e.g. LDR <Dt>, <label>. */ | |
| 105 | #define QL_FP_PCREL \ | |
| 106 | { \ | |
| 107 | QLF2(S_S,NIL), \ | |
| 108 | QLF2(S_D,NIL), \ | |
| 109 | QLF2(S_Q,NIL), \ | |
| 110 | } | |
| 111 | ||
| 112 | /* e.g. PRFM <prfop>, <label>. */ | |
| 113 | #define QL_PRFM_PCREL \ | |
| 114 | { \ | |
| 115 | QLF2(NIL,NIL), \ | |
| 116 | } | |
| 117 | ||
| 118 | /* e.g. BR <Xn>. */ | |
| 119 | #define QL_I1X \ | |
| 120 | { \ | |
| 121 | QLF1(X), \ | |
| 122 | } | |
| 123 | ||
| 124 | /* e.g. RBIT <Wd>, <Wn>. */ | |
| 125 | #define QL_I2SAME \ | |
| 126 | { \ | |
| 127 | QLF2(W,W), \ | |
| 128 | QLF2(X,X), \ | |
| 129 | } | |
| 130 | ||
| 131 | /* e.g. CMN <Wn|WSP>, <Wm>{, <extend> {#<amount>}}. */ | |
| 132 | #define QL_I2_EXT \ | |
| 133 | { \ | |
| 134 | QLF2(W,W), \ | |
| 135 | QLF2(X,W), \ | |
| 136 | QLF2(X,X), \ | |
| 137 | } | |
| 138 | ||
| 139 | /* e.g. MOV <Wd|WSP>, <Wn|WSP>, at least one SP. */ | |
| 140 | #define QL_I2SP \ | |
| 141 | { \ | |
| 142 | QLF2(WSP,W), \ | |
| 143 | QLF2(W,WSP), \ | |
| 144 | QLF2(SP,X), \ | |
| 145 | QLF2(X,SP), \ | |
| 146 | } | |
| 147 | ||
| 148 | /* e.g. REV <Wd>, <Wn>. */ | |
| 149 | #define QL_I2SAMEW \ | |
| 150 | { \ | |
| 151 | QLF2(W,W), \ | |
| 152 | } | |
| 153 | ||
| 154 | /* e.g. REV32 <Xd>, <Xn>. */ | |
| 155 | #define QL_I2SAMEX \ | |
| 156 | { \ | |
| 157 | QLF2(X,X), \ | |
| 158 | } | |
| 159 | ||
| 160 | #define QL_I2SAMER \ | |
| 161 | { \ | |
| 162 | QLF2(W,W), \ | |
| 163 | QLF2(X,X), \ | |
| 164 | } | |
| 165 | ||
| e60bb1dd YZ |
166 | /* e.g. CRC32B <Wd>, <Wn>, <Wm>. */ |
| 167 | #define QL_I3SAMEW \ | |
| 168 | { \ | |
| 169 | QLF3(W,W,W), \ | |
| 170 | } | |
| 171 | ||
| a06ea964 NC |
172 | /* e.g. SMULH <Xd>, <Xn>, <Xm>. */ |
| 173 | #define QL_I3SAMEX \ | |
| 174 | { \ | |
| 175 | QLF3(X,X,X), \ | |
| 176 | } | |
| 177 | ||
| e60bb1dd YZ |
178 | /* e.g. CRC32X <Wd>, <Wn>, <Xm>. */ |
| 179 | #define QL_I3WWX \ | |
| 180 | { \ | |
| 181 | QLF3(W,W,X), \ | |
| 182 | } | |
| 183 | ||
| a06ea964 NC |
184 | /* e.g. UDIV <Xd>, <Xn>, <Xm>. */ |
| 185 | #define QL_I3SAMER \ | |
| 186 | { \ | |
| 187 | QLF3(W,W,W), \ | |
| 188 | QLF3(X,X,X), \ | |
| 189 | } | |
| 190 | ||
| 191 | /* e.g. ADDS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}. */ | |
| 192 | #define QL_I3_EXT \ | |
| 193 | { \ | |
| 194 | QLF3(W,W,W), \ | |
| 195 | QLF3(X,X,W), \ | |
| 196 | QLF3(X,X,X), \ | |
| 197 | } | |
| 198 | ||
| 199 | /* e.g. MADD <Xd>, <Xn>, <Xm>, <Xa>. */ | |
| 200 | #define QL_I4SAMER \ | |
| 201 | { \ | |
| 202 | QLF4(W,W,W,W), \ | |
| 203 | QLF4(X,X,X,X), \ | |
| 204 | } | |
| 205 | ||
| 206 | /* e.g. SMADDL <Xd>, <Wn>, <Wm>, <Xa>. */ | |
| 207 | #define QL_I3SAMEL \ | |
| 208 | { \ | |
| 209 | QLF3(X,W,W), \ | |
| 210 | } | |
| 211 | ||
| 212 | /* e.g. SMADDL <Xd>, <Wn>, <Wm>, <Xa>. */ | |
| 213 | #define QL_I4SAMEL \ | |
| 214 | { \ | |
| 215 | QLF4(X,W,W,X), \ | |
| 216 | } | |
| 217 | ||
| 218 | /* e.g. CSINC <Xd>, <Xn>, <Xm>, <cond>. */ | |
| 219 | #define QL_CSEL \ | |
| 220 | { \ | |
| 221 | QLF4(W, W, W, NIL), \ | |
| 222 | QLF4(X, X, X, NIL), \ | |
| 223 | } | |
| 224 | ||
| 225 | /* e.g. CSET <Wd>, <cond>. */ | |
| 226 | #define QL_DST_R \ | |
| 227 | { \ | |
| 228 | QLF2(W, NIL), \ | |
| 229 | QLF2(X, NIL), \ | |
| 230 | } | |
| 231 | ||
| 232 | /* e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>. */ | |
| 233 | #define QL_BF \ | |
| 234 | { \ | |
| 235 | QLF4(W,W,imm_0_31,imm_0_31), \ | |
| 236 | QLF4(X,X,imm_0_63,imm_0_63), \ | |
| 237 | } | |
| 238 | ||
| 239 | /* e.g. UBFIZ <Wd>, <Wn>, #<lsb>, #<width>. */ | |
| 240 | #define QL_BF2 \ | |
| 241 | { \ | |
| 242 | QLF4(W,W,imm_0_31,imm_1_32), \ | |
| 243 | QLF4(X,X,imm_0_63,imm_1_64), \ | |
| 244 | } | |
| 245 | ||
| 246 | /* e.g. SCVTF <Sd>, <Xn>, #<fbits>. */ | |
| 247 | #define QL_FIX2FP \ | |
| 248 | { \ | |
| 249 | QLF3(S_D,W,imm_1_32), \ | |
| 250 | QLF3(S_S,W,imm_1_32), \ | |
| 251 | QLF3(S_D,X,imm_1_64), \ | |
| 252 | QLF3(S_S,X,imm_1_64), \ | |
| 253 | } | |
| 254 | ||
| 255 | /* e.g. FCVTZS <Wd>, <Dn>, #<fbits>. */ | |
| 256 | #define QL_FP2FIX \ | |
| 257 | { \ | |
| 258 | QLF3(W,S_D,imm_1_32), \ | |
| 259 | QLF3(W,S_S,imm_1_32), \ | |
| 260 | QLF3(X,S_D,imm_1_64), \ | |
| 261 | QLF3(X,S_S,imm_1_64), \ | |
| 262 | } | |
| 263 | ||
| 264 | /* e.g. SCVTF <Dd>, <Wn>. */ | |
| 265 | #define QL_INT2FP \ | |
| 266 | { \ | |
| 267 | QLF2(S_D,W), \ | |
| 268 | QLF2(S_S,W), \ | |
| 269 | QLF2(S_D,X), \ | |
| 270 | QLF2(S_S,X), \ | |
| 271 | } | |
| 272 | ||
| 273 | /* e.g. FCVTNS <Xd>, <Dn>. */ | |
| 274 | #define QL_FP2INT \ | |
| 275 | { \ | |
| 276 | QLF2(W,S_D), \ | |
| 277 | QLF2(W,S_S), \ | |
| 278 | QLF2(X,S_D), \ | |
| 279 | QLF2(X,S_S), \ | |
| 280 | } | |
| 281 | ||
| 282 | /* e.g. FMOV <Xd>, <Vn>.D[1]. */ | |
| 283 | #define QL_XVD1 \ | |
| 284 | { \ | |
| 285 | QLF2(X,S_D), \ | |
| 286 | } | |
| 287 | ||
| 288 | /* e.g. FMOV <Vd>.D[1], <Xn>. */ | |
| 289 | #define QL_VD1X \ | |
| 290 | { \ | |
| 291 | QLF2(S_D,X), \ | |
| 292 | } | |
| 293 | ||
| 294 | /* e.g. EXTR <Xd>, <Xn>, <Xm>, #<lsb>. */ | |
| 295 | #define QL_EXTR \ | |
| 296 | { \ | |
| 297 | QLF4(W,W,W,imm_0_31), \ | |
| 298 | QLF4(X,X,X,imm_0_63), \ | |
| 299 | } | |
| 300 | ||
| 301 | /* e.g. LSL <Wd>, <Wn>, #<uimm>. */ | |
| 302 | #define QL_SHIFT \ | |
| 303 | { \ | |
| 304 | QLF3(W,W,imm_0_31), \ | |
| 305 | QLF3(X,X,imm_0_63), \ | |
| 306 | } | |
| 307 | ||
| 308 | /* e.g. UXTH <Xd>, <Wn>. */ | |
| 309 | #define QL_EXT \ | |
| 310 | { \ | |
| 311 | QLF2(W,W), \ | |
| 312 | QLF2(X,W), \ | |
| 313 | } | |
| 314 | ||
| 315 | /* e.g. UXTW <Xd>, <Wn>. */ | |
| 316 | #define QL_EXT_W \ | |
| 317 | { \ | |
| 318 | QLF2(X,W), \ | |
| 319 | } | |
| 320 | ||
| 321 | /* e.g. SQSHL <V><d>, <V><n>, #<shift>. */ | |
| 322 | #define QL_SSHIFT \ | |
| 323 | { \ | |
| 324 | QLF3(S_B , S_B , S_B ), \ | |
| 325 | QLF3(S_H , S_H , S_H ), \ | |
| 326 | QLF3(S_S , S_S , S_S ), \ | |
| 327 | QLF3(S_D , S_D , S_D ) \ | |
| 328 | } | |
| 329 | ||
| 330 | /* e.g. SSHR <V><d>, <V><n>, #<shift>. */ | |
| 331 | #define QL_SSHIFT_D \ | |
| 332 | { \ | |
| 333 | QLF3(S_D , S_D , S_D ) \ | |
| 334 | } | |
| 335 | ||
| 336 | /* e.g. UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */ | |
| 337 | #define QL_SSHIFT_SD \ | |
| 338 | { \ | |
| 339 | QLF3(S_S , S_S , S_S ), \ | |
| 340 | QLF3(S_D , S_D , S_D ) \ | |
| 341 | } | |
| 342 | ||
| 343 | /* e.g. SQSHRUN <Vb><d>, <Va><n>, #<shift>. */ | |
| 344 | #define QL_SSHIFTN \ | |
| 345 | { \ | |
| 346 | QLF3(S_B , S_H , S_B ), \ | |
| 347 | QLF3(S_H , S_S , S_H ), \ | |
| 348 | QLF3(S_S , S_D , S_S ), \ | |
| 349 | } | |
| 350 | ||
| 351 | /* e.g. SSHR <Vd>.<T>, <Vn>.<T>, #<shift>. | |
| 352 | The register operand variant qualifiers are deliberately used for the | |
| 353 | immediate operand to ease the operand encoding/decoding and qualifier | |
| 354 | sequence matching. */ | |
| 355 | #define QL_VSHIFT \ | |
| 356 | { \ | |
| 357 | QLF3(V_8B , V_8B , V_8B ), \ | |
| 358 | QLF3(V_16B, V_16B, V_16B), \ | |
| 359 | QLF3(V_4H , V_4H , V_4H ), \ | |
| 360 | QLF3(V_8H , V_8H , V_8H ), \ | |
| 361 | QLF3(V_2S , V_2S , V_2S ), \ | |
| 362 | QLF3(V_4S , V_4S , V_4S ), \ | |
| 363 | QLF3(V_2D , V_2D , V_2D ) \ | |
| 364 | } | |
| 365 | ||
| 366 | /* e.g. SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */ | |
| 367 | #define QL_VSHIFT_SD \ | |
| 368 | { \ | |
| 369 | QLF3(V_2S , V_2S , V_2S ), \ | |
| 370 | QLF3(V_4S , V_4S , V_4S ), \ | |
| 371 | QLF3(V_2D , V_2D , V_2D ) \ | |
| 372 | } | |
| 373 | ||
| 374 | /* e.g. SHRN<Q> <Vd>.<Tb>, <Vn>.<Ta>, #<shift>. */ | |
| 375 | #define QL_VSHIFTN \ | |
| 376 | { \ | |
| 377 | QLF3(V_8B , V_8H , V_8B ), \ | |
| 378 | QLF3(V_4H , V_4S , V_4H ), \ | |
| 379 | QLF3(V_2S , V_2D , V_2S ), \ | |
| 380 | } | |
| 381 | ||
| 382 | /* e.g. SHRN<Q> <Vd>.<Tb>, <Vn>.<Ta>, #<shift>. */ | |
| 383 | #define QL_VSHIFTN2 \ | |
| 384 | { \ | |
| 385 | QLF3(V_16B, V_8H, V_16B), \ | |
| 386 | QLF3(V_8H , V_4S , V_8H ), \ | |
| 387 | QLF3(V_4S , V_2D , V_4S ), \ | |
| 388 | } | |
| 389 | ||
| 390 | /* e.g. SSHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. | |
| 391 | the 3rd qualifier is used to help the encoding. */ | |
| 392 | #define QL_VSHIFTL \ | |
| 393 | { \ | |
| 394 | QLF3(V_8H , V_8B , V_8B ), \ | |
| 395 | QLF3(V_4S , V_4H , V_4H ), \ | |
| 396 | QLF3(V_2D , V_2S , V_2S ), \ | |
| 397 | } | |
| 398 | ||
| 399 | /* e.g. SSHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */ | |
| 400 | #define QL_VSHIFTL2 \ | |
| 401 | { \ | |
| 402 | QLF3(V_8H , V_16B, V_16B), \ | |
| 403 | QLF3(V_4S , V_8H , V_8H ), \ | |
| 404 | QLF3(V_2D , V_4S , V_4S ), \ | |
| 405 | } | |
| 406 | ||
| 407 | /* e.g. TBL. */ | |
| 408 | #define QL_TABLE \ | |
| 409 | { \ | |
| 410 | QLF3(V_8B , V_16B, V_8B ), \ | |
| 411 | QLF3(V_16B, V_16B, V_16B), \ | |
| 412 | } | |
| 413 | ||
| 414 | /* e.g. SHA1H. */ | |
| 415 | #define QL_2SAMES \ | |
| 416 | { \ | |
| 417 | QLF2(S_S, S_S), \ | |
| 418 | } | |
| 419 | ||
| 420 | /* e.g. ABS <V><d>, <V><n>. */ | |
| 421 | #define QL_2SAMED \ | |
| 422 | { \ | |
| 423 | QLF2(S_D, S_D), \ | |
| 424 | } | |
| 425 | ||
| 426 | /* e.g. CMGT <V><d>, <V><n>, #0. */ | |
| 427 | #define QL_SISD_CMP_0 \ | |
| 428 | { \ | |
| 429 | QLF3(S_D, S_D, NIL), \ | |
| 430 | } | |
| 431 | ||
| 432 | /* e.g. FCMEQ <V><d>, <V><n>, #0. */ | |
| 433 | #define QL_SISD_FCMP_0 \ | |
| 434 | { \ | |
| 435 | QLF3(S_S, S_S, NIL), \ | |
| 436 | QLF3(S_D, S_D, NIL), \ | |
| 437 | } | |
| 438 | ||
| 439 | /* e.g. FMAXNMP <V><d>, <Vn>.<T>. */ | |
| 440 | #define QL_SISD_PAIR \ | |
| 441 | { \ | |
| 442 | QLF2(S_S, V_2S), \ | |
| 443 | QLF2(S_D, V_2D), \ | |
| 444 | } | |
| 445 | ||
| 446 | /* e.g. ADDP <V><d>, <Vn>.<T>. */ | |
| 447 | #define QL_SISD_PAIR_D \ | |
| 448 | { \ | |
| 449 | QLF2(S_D, V_2D), \ | |
| 450 | } | |
| 451 | ||
| 452 | /* e.g. DUP <V><d>, <Vn>.<T>[<index>]. */ | |
| 453 | #define QL_S_2SAME \ | |
| 454 | { \ | |
| 455 | QLF2(S_B, S_B), \ | |
| 456 | QLF2(S_H, S_H), \ | |
| 457 | QLF2(S_S, S_S), \ | |
| 458 | QLF2(S_D, S_D), \ | |
| 459 | } | |
| 460 | ||
| 461 | /* e.g. FCVTNS <V><d>, <V><n>. */ | |
| 462 | #define QL_S_2SAMESD \ | |
| 463 | { \ | |
| 464 | QLF2(S_S, S_S), \ | |
| 465 | QLF2(S_D, S_D), \ | |
| 466 | } | |
| 467 | ||
| 468 | /* e.g. SQXTN <Vb><d>, <Va><n>. */ | |
| 469 | #define QL_SISD_NARROW \ | |
| 470 | { \ | |
| 471 | QLF2(S_B, S_H), \ | |
| 472 | QLF2(S_H, S_S), \ | |
| 473 | QLF2(S_S, S_D), \ | |
| 474 | } | |
| 475 | ||
| 476 | /* e.g. FCVTXN <Vb><d>, <Va><n>. */ | |
| 477 | #define QL_SISD_NARROW_S \ | |
| 478 | { \ | |
| 479 | QLF2(S_S, S_D), \ | |
| 480 | } | |
| 481 | ||
| 482 | /* e.g. FCVT. */ | |
| 483 | #define QL_FCVT \ | |
| 484 | { \ | |
| 485 | QLF2(S_S, S_H), \ | |
| 486 | QLF2(S_S, S_D), \ | |
| 487 | QLF2(S_D, S_H), \ | |
| 488 | QLF2(S_D, S_S), \ | |
| 489 | QLF2(S_H, S_S), \ | |
| 490 | QLF2(S_H, S_D), \ | |
| 491 | } | |
| 492 | ||
| 493 | /* FMOV <Dd>, <Dn>. */ | |
| 494 | #define QL_FP2 \ | |
| 495 | { \ | |
| 496 | QLF2(S_S, S_S), \ | |
| 497 | QLF2(S_D, S_D), \ | |
| 498 | } | |
| 499 | ||
| 500 | /* e.g. SQADD <V><d>, <V><n>, <V><m>. */ | |
| 501 | #define QL_S_3SAME \ | |
| 502 | { \ | |
| 503 | QLF3(S_B, S_B, S_B), \ | |
| 504 | QLF3(S_H, S_H, S_H), \ | |
| 505 | QLF3(S_S, S_S, S_S), \ | |
| 506 | QLF3(S_D, S_D, S_D), \ | |
| 507 | } | |
| 508 | ||
| 509 | /* e.g. CMGE <V><d>, <V><n>, <V><m>. */ | |
| 510 | #define QL_S_3SAMED \ | |
| 511 | { \ | |
| 512 | QLF3(S_D, S_D, S_D), \ | |
| 513 | } | |
| 514 | ||
| 515 | /* e.g. SQDMULH <V><d>, <V><n>, <V><m>. */ | |
| 516 | #define QL_SISD_HS \ | |
| 517 | { \ | |
| 518 | QLF3(S_H, S_H, S_H), \ | |
| 519 | QLF3(S_S, S_S, S_S), \ | |
| 520 | } | |
| 521 | ||
| 522 | /* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vb><m>. */ | |
| 523 | #define QL_SISDL_HS \ | |
| 524 | { \ | |
| 525 | QLF3(S_S, S_H, S_H), \ | |
| 526 | QLF3(S_D, S_S, S_S), \ | |
| 527 | } | |
| 528 | ||
| 529 | /* FMUL <Sd>, <Sn>, <Sm>. */ | |
| 530 | #define QL_FP3 \ | |
| 531 | { \ | |
| 532 | QLF3(S_S, S_S, S_S), \ | |
| 533 | QLF3(S_D, S_D, S_D), \ | |
| 534 | } | |
| 535 | ||
| 536 | /* FMADD <Dd>, <Dn>, <Dm>, <Da>. */ | |
| 537 | #define QL_FP4 \ | |
| 538 | { \ | |
| 539 | QLF4(S_S, S_S, S_S, S_S), \ | |
| 540 | QLF4(S_D, S_D, S_D, S_D), \ | |
| 541 | } | |
| 542 | ||
| 543 | /* e.g. FCMP <Dn>, #0.0. */ | |
| 544 | #define QL_DST_SD \ | |
| 545 | { \ | |
| 546 | QLF2(S_S, NIL), \ | |
| 547 | QLF2(S_D, NIL), \ | |
| 548 | } | |
| 549 | ||
| 550 | /* FCSEL <Sd>, <Sn>, <Sm>, <cond>. */ | |
| 551 | #define QL_FP_COND \ | |
| 552 | { \ | |
| 553 | QLF4(S_S, S_S, S_S, NIL), \ | |
| 554 | QLF4(S_D, S_D, S_D, NIL), \ | |
| 555 | } | |
| 556 | ||
| 557 | /* e.g. CCMN <Xn>, <Xm>, #<nzcv>, <cond>. */ | |
| 558 | #define QL_CCMP \ | |
| 559 | { \ | |
| 560 | QLF4(W, W, NIL, NIL), \ | |
| 561 | QLF4(X, X, NIL, NIL), \ | |
| 562 | } | |
| 563 | ||
| 564 | /* e.g. CCMN <Xn>, #<imm>, #<nzcv>, <cond>, */ | |
| 565 | #define QL_CCMP_IMM \ | |
| 566 | { \ | |
| 567 | QLF4(W, NIL, NIL, NIL), \ | |
| 568 | QLF4(X, NIL, NIL, NIL), \ | |
| 569 | } | |
| 570 | ||
| 571 | /* e.g. FCCMP <Sn>, <Sm>, #<nzcv>, <cond>. */ | |
| 572 | #define QL_FCCMP \ | |
| 573 | { \ | |
| 574 | QLF4(S_S, S_S, NIL, NIL), \ | |
| 575 | QLF4(S_D, S_D, NIL, NIL), \ | |
| 576 | } | |
| 577 | ||
| 578 | /* e.g. DUP <Vd>.<T>, <Vn>.<Ts>[<index>]. */ | |
| 579 | #define QL_DUP_VX \ | |
| 580 | { \ | |
| 581 | QLF2(V_8B , S_B ), \ | |
| 582 | QLF2(V_16B, S_B ), \ | |
| 583 | QLF2(V_4H , S_H ), \ | |
| 584 | QLF2(V_8H , S_H ), \ | |
| 585 | QLF2(V_2S , S_S ), \ | |
| 586 | QLF2(V_4S , S_S ), \ | |
| 587 | QLF2(V_2D , S_D ), \ | |
| 588 | } | |
| 589 | ||
| 590 | /* e.g. DUP <Vd>.<T>, <Wn>. */ | |
| 591 | #define QL_DUP_VR \ | |
| 592 | { \ | |
| 593 | QLF2(V_8B , W ), \ | |
| 594 | QLF2(V_16B, W ), \ | |
| 595 | QLF2(V_4H , W ), \ | |
| 596 | QLF2(V_8H , W ), \ | |
| 597 | QLF2(V_2S , W ), \ | |
| 598 | QLF2(V_4S , W ), \ | |
| 599 | QLF2(V_2D , X ), \ | |
| 600 | } | |
| 601 | ||
| 602 | /* e.g. INS <Vd>.<Ts>[<index>], <Wn>. */ | |
| 603 | #define QL_INS_XR \ | |
| 604 | { \ | |
| 605 | QLF2(S_H , W ), \ | |
| 606 | QLF2(S_S , W ), \ | |
| 607 | QLF2(S_D , X ), \ | |
| 608 | QLF2(S_B , W ), \ | |
| 609 | } | |
| 610 | ||
| 611 | /* e.g. SMOV <Wd>, <Vn>.<Ts>[<index>]. */ | |
| 612 | #define QL_SMOV \ | |
| 613 | { \ | |
| 614 | QLF2(W , S_H), \ | |
| 615 | QLF2(X , S_H), \ | |
| 616 | QLF2(X , S_S), \ | |
| 617 | QLF2(W , S_B), \ | |
| 618 | QLF2(X , S_B), \ | |
| 619 | } | |
| 620 | ||
| 621 | /* e.g. UMOV <Wd>, <Vn>.<Ts>[<index>]. */ | |
| 622 | #define QL_UMOV \ | |
| 623 | { \ | |
| 624 | QLF2(W , S_H), \ | |
| 625 | QLF2(W , S_S), \ | |
| 626 | QLF2(X , S_D), \ | |
| 627 | QLF2(W , S_B), \ | |
| 628 | } | |
| 629 | ||
| 630 | /* e.g. MOV <Wd>, <Vn>.<Ts>[<index>]. */ | |
| 631 | #define QL_MOV \ | |
| 632 | { \ | |
| 633 | QLF2(W , S_S), \ | |
| 634 | QLF2(X , S_D), \ | |
| 635 | } | |
| 636 | ||
| 637 | /* e.g. SUQADD <Vd>.<T>, <Vn>.<T>. */ | |
| 638 | #define QL_V2SAME \ | |
| 639 | { \ | |
| 640 | QLF2(V_8B , V_8B ), \ | |
| 641 | QLF2(V_16B, V_16B), \ | |
| 642 | QLF2(V_4H , V_4H ), \ | |
| 643 | QLF2(V_8H , V_8H ), \ | |
| 644 | QLF2(V_2S , V_2S ), \ | |
| 645 | QLF2(V_4S , V_4S ), \ | |
| 646 | QLF2(V_2D , V_2D ), \ | |
| 647 | } | |
| 648 | ||
| 649 | /* e.g. URSQRTE <Vd>.<T>, <Vn>.<T>. */ | |
| 650 | #define QL_V2SAMES \ | |
| 651 | { \ | |
| 652 | QLF2(V_2S , V_2S ), \ | |
| 653 | QLF2(V_4S , V_4S ), \ | |
| 654 | } | |
| 655 | ||
| 656 | /* e.g. REV32 <Vd>.<T>, <Vn>.<T>. */ | |
| 657 | #define QL_V2SAMEBH \ | |
| 658 | { \ | |
| 659 | QLF2(V_8B , V_8B ), \ | |
| 660 | QLF2(V_16B, V_16B), \ | |
| 661 | QLF2(V_4H , V_4H ), \ | |
| 662 | QLF2(V_8H , V_8H ), \ | |
| 663 | } | |
| 664 | ||
| 665 | /* e.g. FRINTN <Vd>.<T>, <Vn>.<T>. */ | |
| 666 | #define QL_V2SAMESD \ | |
| 667 | { \ | |
| 668 | QLF2(V_2S , V_2S ), \ | |
| 669 | QLF2(V_4S , V_4S ), \ | |
| 670 | QLF2(V_2D , V_2D ), \ | |
| 671 | } | |
| 672 | ||
| 673 | /* e.g. REV64 <Vd>.<T>, <Vn>.<T>. */ | |
| 674 | #define QL_V2SAMEBHS \ | |
| 675 | { \ | |
| 676 | QLF2(V_8B , V_8B ), \ | |
| 677 | QLF2(V_16B, V_16B), \ | |
| 678 | QLF2(V_4H , V_4H ), \ | |
| 679 | QLF2(V_8H , V_8H ), \ | |
| 680 | QLF2(V_2S , V_2S ), \ | |
| 681 | QLF2(V_4S , V_4S ), \ | |
| 682 | } | |
| 683 | ||
| 684 | /* e.g. REV16 <Vd>.<T>, <Vn>.<T>. */ | |
| 685 | #define QL_V2SAMEB \ | |
| 686 | { \ | |
| 687 | QLF2(V_8B , V_8B ), \ | |
| 688 | QLF2(V_16B, V_16B), \ | |
| 689 | } | |
| 690 | ||
| 691 | /* e.g. SADDLP <Vd>.<Ta>, <Vn>.<Tb>. */ | |
| 692 | #define QL_V2PAIRWISELONGBHS \ | |
| 693 | { \ | |
| 694 | QLF2(V_4H , V_8B ), \ | |
| 695 | QLF2(V_8H , V_16B), \ | |
| 696 | QLF2(V_2S , V_4H ), \ | |
| 697 | QLF2(V_4S , V_8H ), \ | |
| 698 | QLF2(V_1D , V_2S ), \ | |
| 699 | QLF2(V_2D , V_4S ), \ | |
| 700 | } | |
| 701 | ||
| 702 | /* e.g. SHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */ | |
| 703 | #define QL_V2LONGBHS \ | |
| 704 | { \ | |
| 705 | QLF2(V_8H , V_8B ), \ | |
| 706 | QLF2(V_4S , V_4H ), \ | |
| 707 | QLF2(V_2D , V_2S ), \ | |
| 708 | } | |
| 709 | ||
| 710 | /* e.g. SHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */ | |
| 711 | #define QL_V2LONGBHS2 \ | |
| 712 | { \ | |
| 713 | QLF2(V_8H , V_16B), \ | |
| 714 | QLF2(V_4S , V_8H ), \ | |
| 715 | QLF2(V_2D , V_4S ), \ | |
| 716 | } | |
| 717 | ||
| 718 | /* */ | |
| 719 | #define QL_V3SAME \ | |
| 720 | { \ | |
| 721 | QLF3(V_8B , V_8B , V_8B ), \ | |
| 722 | QLF3(V_16B, V_16B, V_16B), \ | |
| 723 | QLF3(V_4H , V_4H , V_4H ), \ | |
| 724 | QLF3(V_8H , V_8H , V_8H ), \ | |
| 725 | QLF3(V_2S , V_2S , V_2S ), \ | |
| 726 | QLF3(V_4S , V_4S , V_4S ), \ | |
| 727 | QLF3(V_2D , V_2D , V_2D ) \ | |
| 728 | } | |
| 729 | ||
| 730 | /* e.g. SHADD. */ | |
| 731 | #define QL_V3SAMEBHS \ | |
| 732 | { \ | |
| 733 | QLF3(V_8B , V_8B , V_8B ), \ | |
| 734 | QLF3(V_16B, V_16B, V_16B), \ | |
| 735 | QLF3(V_4H , V_4H , V_4H ), \ | |
| 736 | QLF3(V_8H , V_8H , V_8H ), \ | |
| 737 | QLF3(V_2S , V_2S , V_2S ), \ | |
| 738 | QLF3(V_4S , V_4S , V_4S ), \ | |
| 739 | } | |
| 740 | ||
| 741 | /* e.g. FCVTXN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
| 742 | #define QL_V2NARRS \ | |
| 743 | { \ | |
| 744 | QLF2(V_2S , V_2D ), \ | |
| 745 | } | |
| 746 | ||
| 747 | /* e.g. FCVTXN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
| 748 | #define QL_V2NARRS2 \ | |
| 749 | { \ | |
| 750 | QLF2(V_4S , V_2D ), \ | |
| 751 | } | |
| 752 | ||
| 753 | /* e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
| 754 | #define QL_V2NARRHS \ | |
| 755 | { \ | |
| 756 | QLF2(V_4H , V_4S ), \ | |
| 757 | QLF2(V_2S , V_2D ), \ | |
| 758 | } | |
| 759 | ||
| 760 | /* e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
| 761 | #define QL_V2NARRHS2 \ | |
| 762 | { \ | |
| 763 | QLF2(V_8H , V_4S ), \ | |
| 764 | QLF2(V_4S , V_2D ), \ | |
| 765 | } | |
| 766 | ||
| 767 | /* e.g. FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */ | |
| 768 | #define QL_V2LONGHS \ | |
| 769 | { \ | |
| 770 | QLF2(V_4S , V_4H ), \ | |
| 771 | QLF2(V_2D , V_2S ), \ | |
| 772 | } | |
| 773 | ||
| 774 | /* e.g. FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */ | |
| 775 | #define QL_V2LONGHS2 \ | |
| 776 | { \ | |
| 777 | QLF2(V_4S , V_8H ), \ | |
| 778 | QLF2(V_2D , V_4S ), \ | |
| 779 | } | |
| 780 | ||
| 781 | /* e.g. XTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
| 782 | #define QL_V2NARRBHS \ | |
| 783 | { \ | |
| 784 | QLF2(V_8B , V_8H ), \ | |
| 785 | QLF2(V_4H , V_4S ), \ | |
| 786 | QLF2(V_2S , V_2D ), \ | |
| 787 | } | |
| 788 | ||
| 789 | /* e.g. XTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
| 790 | #define QL_V2NARRBHS2 \ | |
| 791 | { \ | |
| 792 | QLF2(V_16B, V_8H ), \ | |
| 793 | QLF2(V_8H , V_4S ), \ | |
| 794 | QLF2(V_4S , V_2D ), \ | |
| 795 | } | |
| 796 | ||
| 797 | /* e.g. ORR. */ | |
| 798 | #define QL_V2SAMEB \ | |
| 799 | { \ | |
| 800 | QLF2(V_8B , V_8B ), \ | |
| 801 | QLF2(V_16B, V_16B), \ | |
| 802 | } | |
| 803 | ||
| 804 | /* e.g. AESE. */ | |
| 805 | #define QL_V2SAME16B \ | |
| 806 | { \ | |
| 807 | QLF2(V_16B, V_16B), \ | |
| 808 | } | |
| 809 | ||
| 810 | /* e.g. SHA1SU1. */ | |
| 811 | #define QL_V2SAME4S \ | |
| 812 | { \ | |
| 813 | QLF2(V_4S, V_4S), \ | |
| 814 | } | |
| 815 | ||
| 816 | /* e.g. SHA1SU0. */ | |
| 817 | #define QL_V3SAME4S \ | |
| 818 | { \ | |
| 819 | QLF3(V_4S, V_4S, V_4S), \ | |
| 820 | } | |
| 821 | ||
| 822 | /* e.g. SHADD. */ | |
| 823 | #define QL_V3SAMEB \ | |
| 824 | { \ | |
| 825 | QLF3(V_8B , V_8B , V_8B ), \ | |
| 826 | QLF3(V_16B, V_16B, V_16B), \ | |
| 827 | } | |
| 828 | ||
| 829 | /* e.g. EXT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index>. */ | |
| 830 | #define QL_VEXT \ | |
| 831 | { \ | |
| 832 | QLF4(V_8B , V_8B , V_8B , imm_0_7), \ | |
| 833 | QLF4(V_16B, V_16B, V_16B, imm_0_15), \ | |
| 834 | } | |
| 835 | ||
| 836 | /* e.g. . */ | |
| 837 | #define QL_V3SAMEHS \ | |
| 838 | { \ | |
| 839 | QLF3(V_4H , V_4H , V_4H ), \ | |
| 840 | QLF3(V_8H , V_8H , V_8H ), \ | |
| 841 | QLF3(V_2S , V_2S , V_2S ), \ | |
| 842 | QLF3(V_4S , V_4S , V_4S ), \ | |
| 843 | } | |
| 844 | ||
| 845 | /* */ | |
| 846 | #define QL_V3SAMESD \ | |
| 847 | { \ | |
| 848 | QLF3(V_2S , V_2S , V_2S ), \ | |
| 849 | QLF3(V_4S , V_4S , V_4S ), \ | |
| 850 | QLF3(V_2D , V_2D , V_2D ) \ | |
| 851 | } | |
| 852 | ||
| 853 | /* e.g. SQDMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ | |
| 854 | #define QL_V3LONGHS \ | |
| 855 | { \ | |
| 856 | QLF3(V_4S , V_4H , V_4H ), \ | |
| 857 | QLF3(V_2D , V_2S , V_2S ), \ | |
| 858 | } | |
| 859 | ||
| 860 | /* e.g. SQDMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ | |
| 861 | #define QL_V3LONGHS2 \ | |
| 862 | { \ | |
| 863 | QLF3(V_4S , V_8H , V_8H ), \ | |
| 864 | QLF3(V_2D , V_4S , V_4S ), \ | |
| 865 | } | |
| 866 | ||
| 867 | /* e.g. SADDL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ | |
| 868 | #define QL_V3LONGBHS \ | |
| 869 | { \ | |
| 870 | QLF3(V_8H , V_8B , V_8B ), \ | |
| 871 | QLF3(V_4S , V_4H , V_4H ), \ | |
| 872 | QLF3(V_2D , V_2S , V_2S ), \ | |
| 873 | } | |
| 874 | ||
| 875 | /* e.g. SADDL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ | |
| 876 | #define QL_V3LONGBHS2 \ | |
| 877 | { \ | |
| 878 | QLF3(V_8H , V_16B , V_16B ), \ | |
| 879 | QLF3(V_4S , V_8H , V_8H ), \ | |
| 880 | QLF3(V_2D , V_4S , V_4S ), \ | |
| 881 | } | |
| 882 | ||
| 883 | /* e.g. SADDW<Q> <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>. */ | |
| 884 | #define QL_V3WIDEBHS \ | |
| 885 | { \ | |
| 886 | QLF3(V_8H , V_8H , V_8B ), \ | |
| 887 | QLF3(V_4S , V_4S , V_4H ), \ | |
| 888 | QLF3(V_2D , V_2D , V_2S ), \ | |
| 889 | } | |
| 890 | ||
| 891 | /* e.g. SADDW<Q> <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>. */ | |
| 892 | #define QL_V3WIDEBHS2 \ | |
| 893 | { \ | |
| 894 | QLF3(V_8H , V_8H , V_16B ), \ | |
| 895 | QLF3(V_4S , V_4S , V_8H ), \ | |
| 896 | QLF3(V_2D , V_2D , V_4S ), \ | |
| 897 | } | |
| 898 | ||
| 899 | /* e.g. ADDHN<Q> <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>. */ | |
| 900 | #define QL_V3NARRBHS \ | |
| 901 | { \ | |
| 902 | QLF3(V_8B , V_8H , V_8H ), \ | |
| 903 | QLF3(V_4H , V_4S , V_4S ), \ | |
| 904 | QLF3(V_2S , V_2D , V_2D ), \ | |
| 905 | } | |
| 906 | ||
| 907 | /* e.g. ADDHN<Q> <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>. */ | |
| 908 | #define QL_V3NARRBHS2 \ | |
| 909 | { \ | |
| 910 | QLF3(V_16B , V_8H , V_8H ), \ | |
| 911 | QLF3(V_8H , V_4S , V_4S ), \ | |
| 912 | QLF3(V_4S , V_2D , V_2D ), \ | |
| 913 | } | |
| 914 | ||
| 915 | /* e.g. PMULL. */ | |
| 916 | #define QL_V3LONGB \ | |
| 917 | { \ | |
| 918 | QLF3(V_8H , V_8B , V_8B ), \ | |
| 919 | } | |
| 920 | ||
| 921 | /* e.g. PMULL crypto. */ | |
| 922 | #define QL_V3LONGD \ | |
| 923 | { \ | |
| 924 | QLF3(V_1Q , V_1D , V_1D ), \ | |
| 925 | } | |
| 926 | ||
| 927 | /* e.g. PMULL2. */ | |
| 928 | #define QL_V3LONGB2 \ | |
| 929 | { \ | |
| 930 | QLF3(V_8H , V_16B, V_16B), \ | |
| 931 | } | |
| 932 | ||
| 933 | /* e.g. PMULL2 crypto. */ | |
| 934 | #define QL_V3LONGD2 \ | |
| 935 | { \ | |
| 936 | QLF3(V_1Q , V_2D , V_2D ), \ | |
| 937 | } | |
| 938 | ||
| 939 | /* e.g. SHA1C. */ | |
| 940 | #define QL_SHAUPT \ | |
| 941 | { \ | |
| 942 | QLF3(S_Q, S_S, V_4S), \ | |
| 943 | } | |
| 944 | ||
| 945 | /* e.g. SHA256H2. */ | |
| 946 | #define QL_SHA256UPT \ | |
| 947 | { \ | |
| 948 | QLF3(S_Q, S_Q, V_4S), \ | |
| 949 | } | |
| 950 | ||
| 951 | /* e.g. LDXRB <Wt>, [<Xn|SP>{,#0}]. */ | |
| 952 | #define QL_W1_LDST_EXC \ | |
| 953 | { \ | |
| 954 | QLF2(W, NIL), \ | |
| 955 | } | |
| 956 | ||
| 957 | /* e.g. LDXR <Xt>, [<Xn|SP>{,#0}]. */ | |
| 958 | #define QL_R1NIL \ | |
| 959 | { \ | |
| 960 | QLF2(W, NIL), \ | |
| 961 | QLF2(X, NIL), \ | |
| 962 | } | |
| 963 | ||
| 964 | /* e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */ | |
| 965 | #define QL_W2_LDST_EXC \ | |
| 966 | { \ | |
| 967 | QLF3(W, W, NIL), \ | |
| 968 | } | |
| 969 | ||
| 970 | /* e.g. STXR <Ws>, <Xt>, [<Xn|SP>{,#0}]. */ | |
| 971 | #define QL_R2_LDST_EXC \ | |
| 972 | { \ | |
| 973 | QLF3(W, W, NIL), \ | |
| 974 | QLF3(W, X, NIL), \ | |
| 975 | } | |
| 976 | ||
| 977 | /* e.g. LDXP <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */ | |
| 978 | #define QL_R2NIL \ | |
| 979 | { \ | |
| 980 | QLF3(W, W, NIL), \ | |
| 981 | QLF3(X, X, NIL), \ | |
| 982 | } | |
| 983 | ||
| ee804238 JW |
984 | /* e.g. CASP <Xt1>, <Xt1+1>, <Xt2>, <Xt2+1>, [<Xn|SP>{,#0}]. */ |
| 985 | #define QL_R4NIL \ | |
| 986 | { \ | |
| 987 | QLF5(W, W, W, W, NIL), \ | |
| 988 | QLF5(X, X, X, X, NIL), \ | |
| 989 | } | |
| 990 | ||
| a06ea964 NC |
991 | /* e.g. STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */ |
| 992 | #define QL_R3_LDST_EXC \ | |
| 993 | { \ | |
| 994 | QLF4(W, W, W, NIL), \ | |
| 995 | QLF4(W, X, X, NIL), \ | |
| 996 | } | |
| 997 | ||
| 998 | /* e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 999 | #define QL_LDST_FP \ | |
| 1000 | { \ | |
| 1001 | QLF2(S_B, S_B), \ | |
| 1002 | QLF2(S_H, S_H), \ | |
| 1003 | QLF2(S_S, S_S), \ | |
| 1004 | QLF2(S_D, S_D), \ | |
| 1005 | QLF2(S_Q, S_Q), \ | |
| 1006 | } | |
| 1007 | ||
| 1008 | /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 1009 | #define QL_LDST_R \ | |
| 1010 | { \ | |
| 1011 | QLF2(W, S_S), \ | |
| 1012 | QLF2(X, S_D), \ | |
| 1013 | } | |
| 1014 | ||
| 1015 | /* e.g. STRB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 1016 | #define QL_LDST_W8 \ | |
| 1017 | { \ | |
| 1018 | QLF2(W, S_B), \ | |
| 1019 | } | |
| 1020 | ||
| 1021 | /* e.g. LDRSB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 1022 | #define QL_LDST_R8 \ | |
| 1023 | { \ | |
| 1024 | QLF2(W, S_B), \ | |
| 1025 | QLF2(X, S_B), \ | |
| 1026 | } | |
| 1027 | ||
| 1028 | /* e.g. STRH <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 1029 | #define QL_LDST_W16 \ | |
| 1030 | { \ | |
| 1031 | QLF2(W, S_H), \ | |
| 1032 | } | |
| 1033 | ||
| 1034 | /* e.g. LDRSW <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 1035 | #define QL_LDST_X32 \ | |
| 1036 | { \ | |
| 1037 | QLF2(X, S_S), \ | |
| 1038 | } | |
| 1039 | ||
| 1040 | /* e.g. LDRSH <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 1041 | #define QL_LDST_R16 \ | |
| 1042 | { \ | |
| 1043 | QLF2(W, S_H), \ | |
| 1044 | QLF2(X, S_H), \ | |
| 1045 | } | |
| 1046 | ||
| 1047 | /* e.g. PRFM <prfop>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 1048 | #define QL_LDST_PRFM \ | |
| 1049 | { \ | |
| 1050 | QLF2(NIL, S_D), \ | |
| 1051 | } | |
| 1052 | ||
| 1053 | /* e.g. LDPSW <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]. */ | |
| 1054 | #define QL_LDST_PAIR_X32 \ | |
| 1055 | { \ | |
| 1056 | QLF3(X, X, S_S), \ | |
| 1057 | } | |
| 1058 | ||
| 1059 | /* e.g. STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!. */ | |
| 1060 | #define QL_LDST_PAIR_R \ | |
| 1061 | { \ | |
| 1062 | QLF3(W, W, S_S), \ | |
| 1063 | QLF3(X, X, S_D), \ | |
| 1064 | } | |
| 1065 | ||
| 1066 | /* e.g. STNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */ | |
| 1067 | #define QL_LDST_PAIR_FP \ | |
| 1068 | { \ | |
| 1069 | QLF3(S_S, S_S, S_S), \ | |
| 1070 | QLF3(S_D, S_D, S_D), \ | |
| 1071 | QLF3(S_Q, S_Q, S_Q), \ | |
| 1072 | } | |
| 1073 | ||
| 1074 | /* e.g. LD3 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>]. */ | |
| 1075 | #define QL_SIMD_LDST \ | |
| 1076 | { \ | |
| 1077 | QLF2(V_8B, NIL), \ | |
| 1078 | QLF2(V_16B, NIL), \ | |
| 1079 | QLF2(V_4H, NIL), \ | |
| 1080 | QLF2(V_8H, NIL), \ | |
| 1081 | QLF2(V_2S, NIL), \ | |
| 1082 | QLF2(V_4S, NIL), \ | |
| 1083 | QLF2(V_2D, NIL), \ | |
| 1084 | } | |
| 1085 | ||
| 1086 | /* e.g. LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>]. */ | |
| 1087 | #define QL_SIMD_LDST_ANY \ | |
| 1088 | { \ | |
| 1089 | QLF2(V_8B, NIL), \ | |
| 1090 | QLF2(V_16B, NIL), \ | |
| 1091 | QLF2(V_4H, NIL), \ | |
| 1092 | QLF2(V_8H, NIL), \ | |
| 1093 | QLF2(V_2S, NIL), \ | |
| 1094 | QLF2(V_4S, NIL), \ | |
| 1095 | QLF2(V_1D, NIL), \ | |
| 1096 | QLF2(V_2D, NIL), \ | |
| 1097 | } | |
| 1098 | ||
| 1099 | /* e.g. LD4 {<Vt>.<T>, <Vt2a>.<T>, <Vt3a>.<T>, <Vt4a>.<T>}[<index>], [<Xn|SP>]. */ | |
| 1100 | #define QL_SIMD_LDSTONE \ | |
| 1101 | { \ | |
| 1102 | QLF2(S_B, NIL), \ | |
| 1103 | QLF2(S_H, NIL), \ | |
| 1104 | QLF2(S_S, NIL), \ | |
| 1105 | QLF2(S_D, NIL), \ | |
| 1106 | } | |
| 1107 | ||
| 1108 | /* e.g. ADDV <V><d>, <Vn>.<T>. */ | |
| 1109 | #define QL_XLANES \ | |
| 1110 | { \ | |
| 1111 | QLF2(S_B, V_8B), \ | |
| 1112 | QLF2(S_B, V_16B), \ | |
| 1113 | QLF2(S_H, V_4H), \ | |
| 1114 | QLF2(S_H, V_8H), \ | |
| 1115 | QLF2(S_S, V_4S), \ | |
| 1116 | } | |
| 1117 | ||
| 1118 | /* e.g. FMINV <V><d>, <Vn>.<T>. */ | |
| 1119 | #define QL_XLANES_FP \ | |
| 1120 | { \ | |
| 1121 | QLF2(S_S, V_4S), \ | |
| 1122 | } | |
| 1123 | ||
| 1124 | /* e.g. SADDLV <V><d>, <Vn>.<T>. */ | |
| 1125 | #define QL_XLANES_L \ | |
| 1126 | { \ | |
| 1127 | QLF2(S_H, V_8B), \ | |
| 1128 | QLF2(S_H, V_16B), \ | |
| 1129 | QLF2(S_S, V_4H), \ | |
| 1130 | QLF2(S_S, V_8H), \ | |
| 1131 | QLF2(S_D, V_4S), \ | |
| 1132 | } | |
| 1133 | ||
| 1134 | /* e.g. MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]. */ | |
| 1135 | #define QL_ELEMENT \ | |
| 1136 | { \ | |
| 1137 | QLF3(V_4H, V_4H, S_H), \ | |
| 1138 | QLF3(V_8H, V_8H, S_H), \ | |
| 1139 | QLF3(V_2S, V_2S, S_S), \ | |
| 1140 | QLF3(V_4S, V_4S, S_S), \ | |
| 1141 | } | |
| 1142 | ||
| 1143 | /* e.g. SMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]. */ | |
| 1144 | #define QL_ELEMENT_L \ | |
| 1145 | { \ | |
| 1146 | QLF3(V_4S, V_4H, S_H), \ | |
| 1147 | QLF3(V_2D, V_2S, S_S), \ | |
| 1148 | } | |
| 1149 | ||
| 1150 | /* e.g. SMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]. */ | |
| 1151 | #define QL_ELEMENT_L2 \ | |
| 1152 | { \ | |
| 1153 | QLF3(V_4S, V_8H, S_H), \ | |
| 1154 | QLF3(V_2D, V_4S, S_S), \ | |
| 1155 | } | |
| 1156 | ||
| 1157 | /* e.g. FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>]. */ | |
| 1158 | #define QL_ELEMENT_FP \ | |
| 1159 | { \ | |
| 1160 | QLF3(V_2S, V_2S, S_S), \ | |
| 1161 | QLF3(V_4S, V_4S, S_S), \ | |
| 1162 | QLF3(V_2D, V_2D, S_D), \ | |
| 1163 | } | |
| 1164 | ||
| 1165 | /* e.g. MOVI <Vd>.4S, #<imm8> {, LSL #<amount>}. */ | |
| 1166 | #define QL_SIMD_IMM_S0W \ | |
| 1167 | { \ | |
| 1168 | QLF2(V_2S, LSL), \ | |
| 1169 | QLF2(V_4S, LSL), \ | |
| 1170 | } | |
| 1171 | ||
| 1172 | /* e.g. MOVI <Vd>.4S, #<imm8>, MSL #<amount>. */ | |
| 1173 | #define QL_SIMD_IMM_S1W \ | |
| 1174 | { \ | |
| 1175 | QLF2(V_2S, MSL), \ | |
| 1176 | QLF2(V_4S, MSL), \ | |
| 1177 | } | |
| 1178 | ||
| 1179 | /* e.g. MOVI <Vd>.4H, #<imm8> {, LSL #<amount>}. */ | |
| 1180 | #define QL_SIMD_IMM_S0H \ | |
| 1181 | { \ | |
| 1182 | QLF2(V_4H, LSL), \ | |
| 1183 | QLF2(V_8H, LSL), \ | |
| 1184 | } | |
| 1185 | ||
| 1186 | /* e.g. FMOV <Vd>.<T>, #<imm>. */ | |
| 1187 | #define QL_SIMD_IMM_S \ | |
| 1188 | { \ | |
| 1189 | QLF2(V_2S, NIL), \ | |
| 1190 | QLF2(V_4S, NIL), \ | |
| 1191 | } | |
| 1192 | ||
| f5555712 | 1193 | /* e.g. MOVI <Vd>.8B, #<imm8> {, LSL #<amount>}. */ |
| a06ea964 NC |
1194 | #define QL_SIMD_IMM_B \ |
| 1195 | { \ | |
| f5555712 YZ |
1196 | QLF2(V_8B, LSL), \ |
| 1197 | QLF2(V_16B, LSL), \ | |
| a06ea964 NC |
1198 | } |
| 1199 | /* e.g. MOVI <Dd>, #<imm>. */ | |
| 1200 | #define QL_SIMD_IMM_D \ | |
| 1201 | { \ | |
| 1202 | QLF2(S_D, NIL), \ | |
| 1203 | } | |
| 1204 | ||
| 1205 | /* e.g. MOVI <Vd>.2D, #<imm>. */ | |
| 1206 | #define QL_SIMD_IMM_V2D \ | |
| 1207 | { \ | |
| 1208 | QLF2(V_2D, NIL), \ | |
| 1209 | } | |
| 1210 | \f | |
| 1211 | /* Opcode table. */ | |
| 1212 | ||
| 1213 | static const aarch64_feature_set aarch64_feature_v8 = | |
| 1214 | AARCH64_FEATURE (AARCH64_FEATURE_V8, 0); | |
| 1215 | static const aarch64_feature_set aarch64_feature_fp = | |
| 1216 | AARCH64_FEATURE (AARCH64_FEATURE_FP, 0); | |
| 1217 | static const aarch64_feature_set aarch64_feature_simd = | |
| 1218 | AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0); | |
| 1219 | static const aarch64_feature_set aarch64_feature_crypto = | |
| 1220 | AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0); | |
| e60bb1dd YZ |
1221 | static const aarch64_feature_set aarch64_feature_crc = |
| 1222 | AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0); | |
| ee804238 JW |
1223 | static const aarch64_feature_set aarch64_feature_lse = |
| 1224 | AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0); | |
| 290806fd MW |
1225 | static const aarch64_feature_set aarch64_feature_lor = |
| 1226 | AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0); | |
| 9e1f0fa7 MW |
1227 | static const aarch64_feature_set aarch64_feature_rdma = |
| 1228 | AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0); | |
| a06ea964 NC |
1229 | |
| 1230 | #define CORE &aarch64_feature_v8 | |
| 1231 | #define FP &aarch64_feature_fp | |
| 1232 | #define SIMD &aarch64_feature_simd | |
| 1233 | #define CRYPTO &aarch64_feature_crypto | |
| e60bb1dd | 1234 | #define CRC &aarch64_feature_crc |
| ee804238 | 1235 | #define LSE &aarch64_feature_lse |
| 290806fd | 1236 | #define LOR &aarch64_feature_lor |
| 9e1f0fa7 | 1237 | #define RDMA &aarch64_feature_rdma |
| a06ea964 NC |
1238 | |
| 1239 | struct aarch64_opcode aarch64_opcode_table[] = | |
| 1240 | { | |
| 1241 | /* Add/subtract (with carry). */ | |
| 1242 | {"adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF}, | |
| 1243 | {"adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF}, | |
| 1244 | {"sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF}, | |
| 1245 | {"ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, CORE, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF}, | |
| 1246 | {"sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF}, | |
| 1247 | {"ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, CORE, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF}, | |
| 1248 | /* Add/subtract (extended register). */ | |
| 1249 | {"add", 0x0b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF}, | |
| 1250 | {"adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF}, | |
| 1251 | {"cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, CORE, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF}, | |
| 1252 | {"sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF}, | |
| 1253 | {"subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF}, | |
| 1254 | {"cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, CORE, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF}, | |
| 1255 | /* Add/subtract (immediate). */ | |
| 1256 | {"add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, CORE, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF}, | |
| 1257 | {"mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, CORE, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF}, | |
| 1258 | {"adds", 0x31000000, 0x7f000000, addsub_imm, 0, CORE, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF}, | |
| 1259 | {"cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, CORE, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF}, | |
| 1260 | {"sub", 0x51000000, 0x7f000000, addsub_imm, 0, CORE, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF}, | |
| 1261 | {"subs", 0x71000000, 0x7f000000, addsub_imm, 0, CORE, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF}, | |
| 1262 | {"cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, CORE, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF}, | |
| 1263 | /* Add/subtract (shifted register). */ | |
| 1264 | {"add", 0xb000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF}, | |
| 1265 | {"adds", 0x2b000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF}, | |
| 1266 | {"cmn", 0x2b00001f, 0x7f20001f, addsub_shift, 0, CORE, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF}, | |
| 1267 | {"sub", 0x4b000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF}, | |
| 1268 | {"neg", 0x4b0003e0, 0x7f2003e0, addsub_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF}, | |
| 1269 | {"subs", 0x6b000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF}, | |
| 1270 | {"cmp", 0x6b00001f, 0x7f20001f, addsub_shift, 0, CORE, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF}, | |
| 1271 | {"negs", 0x6b0003e0, 0x7f2003e0, addsub_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF}, | |
| 1272 | /* AdvSIMD across lanes. */ | |
| 1273 | {"saddlv", 0xe303800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ}, | |
| 1274 | {"smaxv", 0xe30a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ}, | |
| 1275 | {"sminv", 0xe31a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ}, | |
| 1276 | {"addv", 0xe31b800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ}, | |
| 1277 | {"uaddlv", 0x2e303800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ}, | |
| 1278 | {"umaxv", 0x2e30a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ}, | |
| 1279 | {"uminv", 0x2e31a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ}, | |
| 1280 | {"fmaxnmv", 0x2e30c800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ}, | |
| 1281 | {"fmaxv", 0x2e30f800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ}, | |
| 1282 | {"fminnmv", 0x2eb0c800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ}, | |
| 1283 | {"fminv", 0x2eb0f800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ}, | |
| 1284 | /* AdvSIMD three different. */ | |
| 1285 | {"saddl", 0x0e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ}, | |
| 1286 | {"saddl2", 0x4e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ}, | |
| 1287 | {"saddw", 0x0e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ}, | |
| 1288 | {"saddw2", 0x4e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ}, | |
| 1289 | {"ssubl", 0x0e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ}, | |
| 1290 | {"ssubl2", 0x4e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ}, | |
| 1291 | {"ssubw", 0x0e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ}, | |
| 1292 | {"ssubw2", 0x4e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ}, | |
| 1293 | {"addhn", 0x0e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ}, | |
| 1294 | {"addhn2", 0x4e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ}, | |
| 1295 | {"sabal", 0x0e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ}, | |
| 1296 | {"sabal2", 0x4e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ}, | |
| 1297 | {"subhn", 0x0e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ}, | |
| 1298 | {"subhn2", 0x4e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ}, | |
| 1299 | {"sabdl", 0x0e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ}, | |
| 1300 | {"sabdl2", 0x4e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ}, | |
| 1301 | {"smlal", 0x0e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ}, | |
| 1302 | {"smlal2", 0x4e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ}, | |
| 1303 | {"sqdmlal", 0x0e209000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ}, | |
| 1304 | {"sqdmlal2", 0x4e209000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ}, | |
| 1305 | {"smlsl", 0x0e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ}, | |
| 1306 | {"smlsl2", 0x4e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ}, | |
| 1307 | {"sqdmlsl", 0x0e20b000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ}, | |
| 1308 | {"sqdmlsl2", 0x4e20b000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ}, | |
| 1309 | {"smull", 0x0e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ}, | |
| 1310 | {"smull2", 0x4e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ}, | |
| 1311 | {"sqdmull", 0x0e20d000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ}, | |
| 1312 | {"sqdmull2", 0x4e20d000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ}, | |
| 1313 | {"pmull", 0x0e20e000, 0xffe0fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGB, 0}, | |
| 1314 | {"pmull", 0x0ee0e000, 0xffe0fc00, asimddiff, 0, CRYPTO, OP3 (Vd, Vn, Vm), QL_V3LONGD, 0}, | |
| 1315 | {"pmull2", 0x4e20e000, 0xffe0fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGB2, 0}, | |
| 1316 | {"pmull2", 0x4ee0e000, 0xffe0fc00, asimddiff, 0, CRYPTO, OP3 (Vd, Vn, Vm), QL_V3LONGD2, 0}, | |
| 1317 | {"uaddl", 0x2e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ}, | |
| 1318 | {"uaddl2", 0x6e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ}, | |
| 1319 | {"uaddw", 0x2e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ}, | |
| 1320 | {"uaddw2", 0x6e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ}, | |
| 1321 | {"usubl", 0x2e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ}, | |
| 1322 | {"usubl2", 0x6e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ}, | |
| 1323 | {"usubw", 0x2e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ}, | |
| 1324 | {"usubw2", 0x6e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ}, | |
| 1325 | {"raddhn", 0x2e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ}, | |
| 1326 | {"raddhn2", 0x6e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ}, | |
| 1327 | {"uabal", 0x2e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ}, | |
| 1328 | {"uabal2", 0x6e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ}, | |
| 1329 | {"rsubhn", 0x2e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ}, | |
| 1330 | {"rsubhn2", 0x6e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ}, | |
| 1331 | {"uabdl", 0x2e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ}, | |
| 1332 | {"uabdl2", 0x6e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ}, | |
| 1333 | {"umlal", 0x2e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ}, | |
| 1334 | {"umlal2", 0x6e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ}, | |
| 1335 | {"umlsl", 0x2e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ}, | |
| 1336 | {"umlsl2", 0x6e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ}, | |
| 1337 | {"umull", 0x2e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ}, | |
| 1338 | {"umull2", 0x6e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ}, | |
| 1339 | /* AdvSIMD vector x indexed element. */ | |
| 1340 | {"smlal", 0x0f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ}, | |
| 1341 | {"smlal2", 0x4f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ}, | |
| 1342 | {"sqdmlal", 0x0f003000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ}, | |
| 1343 | {"sqdmlal2", 0x4f003000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ}, | |
| 1344 | {"smlsl", 0x0f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ}, | |
| 1345 | {"smlsl2", 0x4f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ}, | |
| 1346 | {"sqdmlsl", 0x0f007000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ}, | |
| 1347 | {"sqdmlsl2", 0x4f007000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ}, | |
| 1348 | {"mul", 0xf008000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ}, | |
| 1349 | {"smull", 0x0f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ}, | |
| 1350 | {"smull2", 0x4f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ}, | |
| 1351 | {"sqdmull", 0x0f00b000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ}, | |
| 1352 | {"sqdmull2", 0x4f00b000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ}, | |
| 1353 | {"sqdmulh", 0xf00c000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ}, | |
| 1354 | {"sqrdmulh", 0xf00d000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ}, | |
| 1355 | {"fmla", 0xf801000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ}, | |
| 1356 | {"fmls", 0xf805000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ}, | |
| 1357 | {"fmul", 0xf809000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ}, | |
| 1358 | {"mla", 0x2f000000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ}, | |
| 1359 | {"umlal", 0x2f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ}, | |
| 1360 | {"umlal2", 0x6f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ}, | |
| 1361 | {"mls", 0x2f004000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ}, | |
| 1362 | {"umlsl", 0x2f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ}, | |
| 1363 | {"umlsl2", 0x6f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ}, | |
| 1364 | {"umull", 0x2f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ}, | |
| 1365 | {"umull2", 0x6f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ}, | |
| 1366 | {"fmulx", 0x2f809000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ}, | |
| 9e1f0fa7 MW |
1367 | {"sqrdmlah", 0x2f00d000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ}, |
| 1368 | {"sqrdmlsh", 0x2f00f000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ}, | |
| a06ea964 | 1369 | /* AdvSIMD EXT. */ |
| 922c5db5 | 1370 | {"ext", 0x2e000000, 0xbfe08400, asimdext, 0, SIMD, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ}, |
| a06ea964 NC |
1371 | /* AdvSIMD modified immediate. */ |
| 1372 | {"movi", 0xf000400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ}, | |
| 1373 | {"orr", 0xf001400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ}, | |
| 1374 | {"movi", 0xf008400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ}, | |
| 1375 | {"orr", 0xf009400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ}, | |
| 1376 | {"movi", 0xf00c400, 0xbff8ec00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ}, | |
| f5555712 | 1377 | {"movi", 0xf00e400, 0xbff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_B, F_SIZEQ}, |
| a06ea964 NC |
1378 | {"fmov", 0xf00f400, 0xbff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_S, F_SIZEQ}, |
| 1379 | {"mvni", 0x2f000400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ}, | |
| 1380 | {"bic", 0x2f001400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ}, | |
| 1381 | {"mvni", 0x2f008400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ}, | |
| 1382 | {"bic", 0x2f009400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ}, | |
| 1383 | {"mvni", 0x2f00c400, 0xbff8ec00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ}, | |
| 1384 | {"movi", 0x2f00e400, 0xfff8fc00, asimdimm, 0, SIMD, OP2 (Sd, SIMD_IMM), QL_SIMD_IMM_D, F_SIZEQ}, | |
| 1385 | {"movi", 0x6f00e400, 0xfff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM), QL_SIMD_IMM_V2D, F_SIZEQ}, | |
| 1386 | {"fmov", 0x6f00f400, 0xfff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_V2D, F_SIZEQ}, | |
| 1387 | /* AdvSIMD copy. */ | |
| 1388 | {"dup", 0xe000400, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Vd, En), QL_DUP_VX, F_T}, | |
| 1389 | {"dup", 0xe000c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Vd, Rn), QL_DUP_VR, F_T}, | |
| 1390 | {"smov", 0xe002c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Rd, En), QL_SMOV, F_GPRSIZE_IN_Q}, | |
| 1391 | {"umov", 0xe003c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Rd, En), QL_UMOV, F_HAS_ALIAS | F_GPRSIZE_IN_Q}, | |
| 1392 | {"mov", 0xe003c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Rd, En), QL_MOV, F_ALIAS | F_GPRSIZE_IN_Q}, | |
| 1393 | {"ins", 0x4e001c00, 0xffe0fc00, asimdins, 0, SIMD, OP2 (Ed, Rn), QL_INS_XR, F_HAS_ALIAS}, | |
| 1394 | {"mov", 0x4e001c00, 0xffe0fc00, asimdins, 0, SIMD, OP2 (Ed, Rn), QL_INS_XR, F_ALIAS}, | |
| 1395 | {"ins", 0x6e000400, 0xffe08400, asimdins, 0, SIMD, OP2 (Ed, En), QL_S_2SAME, F_HAS_ALIAS}, | |
| 1396 | {"mov", 0x6e000400, 0xffe08400, asimdins, 0, SIMD, OP2 (Ed, En), QL_S_2SAME, F_ALIAS}, | |
| 1397 | /* AdvSIMD two-reg misc. */ | |
| 1398 | {"rev64", 0xe200800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ}, | |
| 1399 | {"rev16", 0xe201800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ}, | |
| 1400 | {"saddlp", 0xe202800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ}, | |
| 1401 | {"suqadd", 0xe203800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ}, | |
| 1402 | {"cls", 0xe204800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ}, | |
| 1403 | {"cnt", 0xe205800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ}, | |
| 1404 | {"sadalp", 0xe206800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ}, | |
| 1405 | {"sqabs", 0xe207800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ}, | |
| 1406 | {"cmgt", 0xe208800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ}, | |
| 1407 | {"cmeq", 0xe209800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ}, | |
| 1408 | {"cmlt", 0xe20a800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ}, | |
| 1409 | {"abs", 0xe20b800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ}, | |
| 1410 | {"xtn", 0xe212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ}, | |
| 1411 | {"xtn2", 0x4e212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ}, | |
| 1412 | {"sqxtn", 0xe214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ}, | |
| 1413 | {"sqxtn2", 0x4e214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ}, | |
| 1414 | {"fcvtn", 0xe216800, 0xffbffc00, asimdmisc, OP_FCVTN, SIMD, OP2 (Vd, Vn), QL_V2NARRHS, F_MISC}, | |
| 1415 | {"fcvtn2", 0x4e216800, 0xffbffc00, asimdmisc, OP_FCVTN2, SIMD, OP2 (Vd, Vn), QL_V2NARRHS2, F_MISC}, | |
| 1416 | {"fcvtl", 0xe217800, 0xffbffc00, asimdmisc, OP_FCVTL, SIMD, OP2 (Vd, Vn), QL_V2LONGHS, F_MISC}, | |
| 1417 | {"fcvtl2", 0x4e217800, 0xffbffc00, asimdmisc, OP_FCVTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGHS2, F_MISC}, | |
| 1418 | {"frintn", 0xe218800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, | |
| 1419 | {"frintm", 0xe219800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, | |
| 1420 | {"fcvtns", 0xe21a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, | |
| 1421 | {"fcvtms", 0xe21b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, | |
| 1422 | {"fcvtas", 0xe21c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, | |
| 1423 | {"scvtf", 0xe21d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, | |
| f17c8bfc YZ |
1424 | {"fcmgt", 0xea0c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ}, |
| 1425 | {"fcmeq", 0xea0d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ}, | |
| 1426 | {"fcmlt", 0xea0e800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ}, | |
| a06ea964 NC |
1427 | {"fabs", 0xea0f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, |
| 1428 | {"frintp", 0xea18800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, | |
| 1429 | {"frintz", 0xea19800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, | |
| 1430 | {"fcvtps", 0xea1a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, | |
| 1431 | {"fcvtzs", 0xea1b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, | |
| 1432 | {"urecpe", 0xea1c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ}, | |
| 1433 | {"frecpe", 0xea1d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, | |
| 1434 | {"rev32", 0x2e200800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBH, F_SIZEQ}, | |
| 1435 | {"uaddlp", 0x2e202800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ}, | |
| 1436 | {"usqadd", 0x2e203800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ}, | |
| 1437 | {"clz", 0x2e204800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ}, | |
| 1438 | {"uadalp", 0x2e206800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ}, | |
| 1439 | {"sqneg", 0x2e207800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ}, | |
| 1440 | {"cmge", 0x2e208800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ}, | |
| 1441 | {"cmle", 0x2e209800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ}, | |
| 1442 | {"neg", 0x2e20b800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ}, | |
| 1443 | {"sqxtun", 0x2e212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ}, | |
| 1444 | {"sqxtun2", 0x6e212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ}, | |
| 1445 | {"shll", 0x2e213800, 0xff3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS, F_SIZEQ}, | |
| 1446 | {"shll2", 0x6e213800, 0xff3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS2, F_SIZEQ}, | |
| 1447 | {"uqxtn", 0x2e214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ}, | |
| 1448 | {"uqxtn2", 0x6e214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ}, | |
| 1449 | {"fcvtxn", 0x2e616800, 0xfffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRS, 0}, | |
| 1450 | {"fcvtxn2", 0x6e616800, 0xfffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRS2, 0}, | |
| 1451 | {"frinta", 0x2e218800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, | |
| 1452 | {"frintx", 0x2e219800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, | |
| 1453 | {"fcvtnu", 0x2e21a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, | |
| 1454 | {"fcvtmu", 0x2e21b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, | |
| 1455 | {"fcvtau", 0x2e21c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, | |
| 1456 | {"ucvtf", 0x2e21d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, | |
| 1457 | {"not", 0x2e205800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_HAS_ALIAS}, | |
| 1458 | {"mvn", 0x2e205800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_ALIAS}, | |
| 1459 | {"rbit", 0x2e605800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ}, | |
| f17c8bfc YZ |
1460 | {"fcmge", 0x2ea0c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ}, |
| 1461 | {"fcmle", 0x2ea0d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ}, | |
| a06ea964 NC |
1462 | {"fneg", 0x2ea0f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, |
| 1463 | {"frinti", 0x2ea19800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, | |
| 1464 | {"fcvtpu", 0x2ea1a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, | |
| 1465 | {"fcvtzu", 0x2ea1b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, | |
| 1466 | {"ursqrte", 0x2ea1c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ}, | |
| 1467 | {"frsqrte", 0x2ea1d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, | |
| 1468 | {"fsqrt", 0x2ea1f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, | |
| 1469 | /* AdvSIMD ZIP/UZP/TRN. */ | |
| 1470 | {"uzp1", 0xe001800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1471 | {"trn1", 0xe002800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1472 | {"zip1", 0xe003800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1473 | {"uzp2", 0xe005800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1474 | {"trn2", 0xe006800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1475 | {"zip2", 0xe007800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1476 | /* AdvSIMD three same. */ | |
| 1477 | {"shadd", 0xe200400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ}, | |
| 1478 | {"sqadd", 0xe200c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1479 | {"srhadd", 0xe201400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ}, | |
| 1480 | {"shsub", 0xe202400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ}, | |
| 1481 | {"sqsub", 0xe202c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1482 | {"cmgt", 0xe203400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1483 | {"cmge", 0xe203c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1484 | {"sshl", 0xe204400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1485 | {"sqshl", 0xe204c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1486 | {"srshl", 0xe205400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1487 | {"sqrshl", 0xe205c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1488 | {"smax", 0xe206400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ}, | |
| 1489 | {"smin", 0xe206c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ}, | |
| 1490 | {"sabd", 0xe207400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ}, | |
| 1491 | {"saba", 0xe207c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ}, | |
| 1492 | {"add", 0xe208400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1493 | {"cmtst", 0xe208c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1494 | {"mla", 0xe209400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ}, | |
| 1495 | {"mul", 0xe209c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ}, | |
| 1496 | {"smaxp", 0xe20a400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ}, | |
| 1497 | {"sminp", 0xe20ac00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ}, | |
| 1498 | {"sqdmulh", 0xe20b400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ}, | |
| 1499 | {"addp", 0xe20bc00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1500 | {"fmaxnm", 0xe20c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1501 | {"fmla", 0xe20cc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1502 | {"fadd", 0xe20d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1503 | {"fmulx", 0xe20dc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1504 | {"fcmeq", 0xe20e400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1505 | {"fmax", 0xe20f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1506 | {"frecps", 0xe20fc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1507 | {"and", 0xe201c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ}, | |
| 1508 | {"bic", 0xe601c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ}, | |
| 1509 | {"fminnm", 0xea0c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1510 | {"fmls", 0xea0cc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1511 | {"fsub", 0xea0d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1512 | {"fmin", 0xea0f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1513 | {"frsqrts", 0xea0fc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1514 | {"orr", 0xea01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_HAS_ALIAS | F_SIZEQ}, | |
| 1515 | {"mov", 0xea01c00, 0xbfe0fc00, asimdsame, OP_MOV_V, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_ALIAS | F_CONV}, | |
| 1516 | {"orn", 0xee01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ}, | |
| 1517 | {"uhadd", 0x2e200400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ}, | |
| 1518 | {"uqadd", 0x2e200c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1519 | {"urhadd", 0x2e201400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ}, | |
| 1520 | {"uhsub", 0x2e202400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ}, | |
| 1521 | {"uqsub", 0x2e202c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1522 | {"cmhi", 0x2e203400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1523 | {"cmhs", 0x2e203c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1524 | {"ushl", 0x2e204400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1525 | {"uqshl", 0x2e204c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1526 | {"urshl", 0x2e205400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1527 | {"uqrshl", 0x2e205c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1528 | {"umax", 0x2e206400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ}, | |
| 1529 | {"umin", 0x2e206c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ}, | |
| 1530 | {"uabd", 0x2e207400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ}, | |
| 1531 | {"uaba", 0x2e207c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ}, | |
| 1532 | {"sub", 0x2e208400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1533 | {"cmeq", 0x2e208c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, | |
| 1534 | {"mls", 0x2e209400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ}, | |
| 1535 | {"pmul", 0x2e209c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ}, | |
| 1536 | {"umaxp", 0x2e20a400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ}, | |
| 1537 | {"uminp", 0x2e20ac00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ}, | |
| 1538 | {"sqrdmulh", 0x2e20b400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ}, | |
| 1539 | {"fmaxnmp", 0x2e20c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1540 | {"faddp", 0x2e20d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1541 | {"fmul", 0x2e20dc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1542 | {"fcmge", 0x2e20e400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1543 | {"facge", 0x2e20ec00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1544 | {"fmaxp", 0x2e20f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1545 | {"fdiv", 0x2e20fc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1546 | {"eor", 0x2e201c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ}, | |
| 1547 | {"bsl", 0x2e601c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ}, | |
| 1548 | {"fminnmp", 0x2ea0c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1549 | {"fabd", 0x2ea0d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1550 | {"fcmgt", 0x2ea0e400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1551 | {"facgt", 0x2ea0ec00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1552 | {"fminp", 0x2ea0f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ}, | |
| 1553 | {"bit", 0x2ea01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ}, | |
| 1554 | {"bif", 0x2ee01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ}, | |
| 9e1f0fa7 MW |
1555 | /* AdvSIMD three same extension. */ |
| 1556 | {"sqrdmlah", 0x2e008400, 0xbf20fe00, asimdsame, 0, RDMA, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ}, | |
| 1557 | {"sqrdmlsh", 0x2e008c00, 0xbf20fe00, asimdsame, 0, RDMA, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ}, | |
| a06ea964 NC |
1558 | /* AdvSIMD shift by immediate. */ |
| 1559 | {"sshr", 0xf000400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0}, | |
| 1560 | {"ssra", 0xf001400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0}, | |
| 1561 | {"srshr", 0xf002400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0}, | |
| 1562 | {"srsra", 0xf003400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0}, | |
| 1563 | {"shl", 0xf005400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0}, | |
| 1564 | {"sqshl", 0xf007400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0}, | |
| 1565 | {"shrn", 0xf008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0}, | |
| 1566 | {"shrn2", 0x4f008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0}, | |
| 1567 | {"rshrn", 0xf008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0}, | |
| 1568 | {"rshrn2", 0x4f008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0}, | |
| 1569 | {"sqshrn", 0xf009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0}, | |
| 1570 | {"sqshrn2", 0x4f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0}, | |
| 1571 | {"sqrshrn", 0xf009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0}, | |
| 1572 | {"sqrshrn2", 0x4f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0}, | |
| e30181a5 YZ |
1573 | {"sshll", 0xf00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS}, |
| 1574 | {"sxtl", 0xf00a400, 0xff87fc00, asimdshf, OP_SXTL, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV}, | |
| 1575 | {"sshll2", 0x4f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS}, | |
| 1576 | {"sxtl2", 0x4f00a400, 0xff87fc00, asimdshf, OP_SXTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV}, | |
| a06ea964 NC |
1577 | {"scvtf", 0xf00e400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0}, |
| 1578 | {"fcvtzs", 0xf00fc00, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0}, | |
| 1579 | {"ushr", 0x2f000400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0}, | |
| 1580 | {"usra", 0x2f001400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0}, | |
| 1581 | {"urshr", 0x2f002400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0}, | |
| 1582 | {"ursra", 0x2f003400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0}, | |
| 1583 | {"sri", 0x2f004400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0}, | |
| 1584 | {"sli", 0x2f005400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0}, | |
| 1585 | {"sqshlu", 0x2f006400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0}, | |
| 1586 | {"uqshl", 0x2f007400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0}, | |
| 1587 | {"sqshrun", 0x2f008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0}, | |
| 1588 | {"sqshrun2", 0x6f008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0}, | |
| 1589 | {"sqrshrun", 0x2f008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0}, | |
| 1590 | {"sqrshrun2", 0x6f008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0}, | |
| 1591 | {"uqshrn", 0x2f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0}, | |
| 1592 | {"uqshrn2", 0x6f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0}, | |
| 1593 | {"uqrshrn", 0x2f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0}, | |
| 1594 | {"uqrshrn2", 0x6f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0}, | |
| e30181a5 YZ |
1595 | {"ushll", 0x2f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS}, |
| 1596 | {"uxtl", 0x2f00a400, 0xff87fc00, asimdshf, OP_UXTL, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV}, | |
| 1597 | {"ushll2", 0x6f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS}, | |
| 1598 | {"uxtl2", 0x6f00a400, 0xff87fc00, asimdshf, OP_UXTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV}, | |
| a06ea964 NC |
1599 | {"ucvtf", 0x2f00e400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0}, |
| 1600 | {"fcvtzu", 0x2f00fc00, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0}, | |
| 1601 | /* AdvSIMD TBL/TBX. */ | |
| 1602 | {"tbl", 0xe000000, 0xbfe09c00, asimdtbl, 0, SIMD, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ}, | |
| 1603 | {"tbx", 0xe001000, 0xbfe09c00, asimdtbl, 0, SIMD, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ}, | |
| 1604 | /* AdvSIMD scalar three different. */ | |
| 1605 | {"sqdmlal", 0x5e209000, 0xff20fc00, asisddiff, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE}, | |
| 1606 | {"sqdmlsl", 0x5e20b000, 0xff20fc00, asisddiff, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE}, | |
| 1607 | {"sqdmull", 0x5e20d000, 0xff20fc00, asisddiff, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE}, | |
| 1608 | /* AdvSIMD scalar x indexed element. */ | |
| 1609 | {"sqdmlal", 0x5f003000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE}, | |
| 1610 | {"sqdmlsl", 0x5f007000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE}, | |
| 1611 | {"sqdmull", 0x5f00b000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE}, | |
| 1612 | {"sqdmulh", 0x5f00c000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE}, | |
| 1613 | {"sqrdmulh", 0x5f00d000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE}, | |
| 1614 | {"fmla", 0x5f801000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE}, | |
| 1615 | {"fmls", 0x5f805000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE}, | |
| 1616 | {"fmul", 0x5f809000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE}, | |
| 1617 | {"fmulx", 0x7f809000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE}, | |
| 9e1f0fa7 MW |
1618 | {"sqrdmlah", 0x7f00d000, 0xff00f400, asisdelem, 0, RDMA, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE}, |
| 1619 | {"sqrdmlsh", 0x7f00f000, 0xff00f400, asisdelem, 0, RDMA, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE}, | |
| a06ea964 NC |
1620 | /* AdvSIMD load/store multiple structures. */ |
| 1621 | {"st4", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)}, | |
| 1622 | {"st1", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)}, | |
| 1623 | {"st2", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(2)}, | |
| 1624 | {"st3", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(3)}, | |
| 1625 | {"ld4", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)}, | |
| 1626 | {"ld1", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)}, | |
| 1627 | {"ld2", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(2)}, | |
| 1628 | {"ld3", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(3)}, | |
| 1629 | /* AdvSIMD load/store multiple structures (post-indexed). */ | |
| 1630 | {"st4", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(4)}, | |
| 1631 | {"st1", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)}, | |
| 1632 | {"st2", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(2)}, | |
| 1633 | {"st3", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(3)}, | |
| 1634 | {"ld4", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(4)}, | |
| 1635 | {"ld1", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)}, | |
| 1636 | {"ld2", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(2)}, | |
| 1637 | {"ld3", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(3)}, | |
| 1638 | /* AdvSIMD load/store single structure. */ | |
| 1639 | {"st1", 0xd000000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(1)}, | |
| 1640 | {"st3", 0xd002000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(3)}, | |
| 1641 | {"st2", 0xd200000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(2)}, | |
| 1642 | {"st4", 0xd202000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(4)}, | |
| 1643 | {"ld1", 0xd400000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(1)}, | |
| 1644 | {"ld3", 0xd402000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(3)}, | |
| 1645 | {"ld1r", 0xd40c000, 0xbfffe000, asisdlso, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)}, | |
| 1646 | {"ld3r", 0xd40e000, 0xbfffe000, asisdlso, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(3)}, | |
| 1647 | {"ld2", 0xd600000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(2)}, | |
| 1648 | {"ld4", 0xd602000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(4)}, | |
| 1649 | {"ld2r", 0xd60c000, 0xbfffe000, asisdlso, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(2)}, | |
| 1650 | {"ld4r", 0xd60e000, 0xbfffe000, asisdlso, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(4)}, | |
| 1651 | /* AdvSIMD load/store single structure (post-indexed). */ | |
| 1652 | {"st1", 0xd800000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(1)}, | |
| 1653 | {"st3", 0xd802000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(3)}, | |
| 1654 | {"st2", 0xda00000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(2)}, | |
| 1655 | {"st4", 0xda02000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(4)}, | |
| 1656 | {"ld1", 0xdc00000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(1)}, | |
| 1657 | {"ld3", 0xdc02000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(3)}, | |
| 1658 | {"ld1r", 0xdc0c000, 0xbfe0e000, asisdlsop, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)}, | |
| 1659 | {"ld3r", 0xdc0e000, 0xbfe0e000, asisdlsop, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(3)}, | |
| 1660 | {"ld2", 0xde00000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(2)}, | |
| 1661 | {"ld4", 0xde02000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(4)}, | |
| 1662 | {"ld2r", 0xde0c000, 0xbfe0e000, asisdlsop, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(2)}, | |
| 1663 | {"ld4r", 0xde0e000, 0xbfe0e000, asisdlsop, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(4)}, | |
| 1664 | /* AdvSIMD scalar two-reg misc. */ | |
| 1665 | {"suqadd", 0x5e203800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE}, | |
| 1666 | {"sqabs", 0x5e207800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE}, | |
| 1667 | {"cmgt", 0x5e208800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE}, | |
| 1668 | {"cmeq", 0x5e209800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE}, | |
| 1669 | {"cmlt", 0x5e20a800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE}, | |
| 1670 | {"abs", 0x5e20b800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_2SAMED, F_SSIZE}, | |
| 1671 | {"sqxtn", 0x5e214800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE}, | |
| 1672 | {"fcvtns", 0x5e21a800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE}, | |
| 1673 | {"fcvtms", 0x5e21b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE}, | |
| 1674 | {"fcvtas", 0x5e21c800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE}, | |
| 1675 | {"scvtf", 0x5e21d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE}, | |
| f17c8bfc YZ |
1676 | {"fcmgt", 0x5ea0c800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE}, |
| 1677 | {"fcmeq", 0x5ea0d800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE}, | |
| 1678 | {"fcmlt", 0x5ea0e800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE}, | |
| a06ea964 NC |
1679 | {"fcvtps", 0x5ea1a800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE}, |
| 1680 | {"fcvtzs", 0x5ea1b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE}, | |
| 1681 | {"frecpe", 0x5ea1d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE}, | |
| 1682 | {"frecpx", 0x5ea1f800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE}, | |
| 1683 | {"usqadd", 0x7e203800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE}, | |
| 1684 | {"sqneg", 0x7e207800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE}, | |
| 1685 | {"cmge", 0x7e208800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE}, | |
| 1686 | {"cmle", 0x7e209800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE}, | |
| 1687 | {"neg", 0x7e20b800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_2SAMED, F_SSIZE}, | |
| 1688 | {"sqxtun", 0x7e212800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE}, | |
| 1689 | {"uqxtn", 0x7e214800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE}, | |
| 1690 | {"fcvtxn", 0x7e216800, 0xffbffc00, asisdmisc, OP_FCVTXN_S, SIMD, OP2 (Sd, Sn), QL_SISD_NARROW_S, F_MISC}, | |
| 1691 | {"fcvtnu", 0x7e21a800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE}, | |
| 1692 | {"fcvtmu", 0x7e21b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE}, | |
| 1693 | {"fcvtau", 0x7e21c800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE}, | |
| 1694 | {"ucvtf", 0x7e21d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE}, | |
| f17c8bfc YZ |
1695 | {"fcmge", 0x7ea0c800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE}, |
| 1696 | {"fcmle", 0x7ea0d800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE}, | |
| a06ea964 NC |
1697 | {"fcvtpu", 0x7ea1a800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE}, |
| 1698 | {"fcvtzu", 0x7ea1b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE}, | |
| 1699 | {"frsqrte", 0x7ea1d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE}, | |
| 1700 | /* AdvSIMD scalar copy. */ | |
| 1701 | {"dup", 0x5e000400, 0xffe0fc00, asisdone, 0, SIMD, OP2 (Sd, En), QL_S_2SAME, F_HAS_ALIAS}, | |
| 1702 | {"mov", 0x5e000400, 0xffe0fc00, asisdone, 0, SIMD, OP2 (Sd, En), QL_S_2SAME, F_ALIAS}, | |
| 1703 | /* AdvSIMD scalar pairwise. */ | |
| 1704 | {"addp", 0x5e31b800, 0xff3ffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR_D, F_SIZEQ}, | |
| 1705 | {"fmaxnmp", 0x7e30c800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ}, | |
| 1706 | {"faddp", 0x7e30d800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ}, | |
| 1707 | {"fmaxp", 0x7e30f800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ}, | |
| 1708 | {"fminnmp", 0x7eb0c800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ}, | |
| 1709 | {"fminp", 0x7eb0f800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ}, | |
| 1710 | /* AdvSIMD scalar three same. */ | |
| 1711 | {"sqadd", 0x5e200c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE}, | |
| 1712 | {"sqsub", 0x5e202c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE}, | |
| 1713 | {"sqshl", 0x5e204c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE}, | |
| 1714 | {"sqrshl", 0x5e205c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE}, | |
| 1715 | {"sqdmulh", 0x5e20b400, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE}, | |
| 1716 | {"fmulx", 0x5e20dc00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE}, | |
| 1717 | {"fcmeq", 0x5e20e400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE}, | |
| 1718 | {"frecps", 0x5e20fc00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE}, | |
| 1719 | {"frsqrts", 0x5ea0fc00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE}, | |
| 1720 | {"cmgt", 0x5ee03400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE}, | |
| 1721 | {"cmge", 0x5ee03c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE}, | |
| 1722 | {"sshl", 0x5ee04400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE}, | |
| 1723 | {"srshl", 0x5ee05400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE}, | |
| 1724 | {"add", 0x5ee08400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE}, | |
| 1725 | {"cmtst", 0x5ee08c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE}, | |
| 1726 | {"uqadd", 0x7e200c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE}, | |
| 1727 | {"uqsub", 0x7e202c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE}, | |
| 1728 | {"uqshl", 0x7e204c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE}, | |
| 1729 | {"uqrshl", 0x7e205c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE}, | |
| 1730 | {"sqrdmulh", 0x7e20b400, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE}, | |
| 1731 | {"fcmge", 0x7e20e400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE}, | |
| 1732 | {"facge", 0x7e20ec00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE}, | |
| 1733 | {"fabd", 0x7ea0d400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE}, | |
| 1734 | {"fcmgt", 0x7ea0e400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE}, | |
| 1735 | {"facgt", 0x7ea0ec00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE}, | |
| 1736 | {"cmhi", 0x7ee03400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE}, | |
| 1737 | {"cmhs", 0x7ee03c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE}, | |
| 1738 | {"ushl", 0x7ee04400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE}, | |
| 1739 | {"urshl", 0x7ee05400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE}, | |
| 1740 | {"sub", 0x7ee08400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE}, | |
| 1741 | {"cmeq", 0x7ee08c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE}, | |
| 9e1f0fa7 MW |
1742 | /* AdvSIMDs scalar three same extension. */ |
| 1743 | {"sqrdmlah", 0x7e008400, 0xff20fc00, asimdsame, 0, RDMA, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE}, | |
| 1744 | {"sqrdmlsh", 0x7e008c00, 0xff20fc00, asimdsame, 0, RDMA, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE}, | |
| a06ea964 NC |
1745 | /* AdvSIMD scalar shift by immediate. */ |
| 1746 | {"sshr", 0x5f000400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0}, | |
| 1747 | {"ssra", 0x5f001400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0}, | |
| 1748 | {"srshr", 0x5f002400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0}, | |
| 1749 | {"srsra", 0x5f003400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0}, | |
| 1750 | {"shl", 0x5f005400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT_D, 0}, | |
| 1751 | {"sqshl", 0x5f007400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0}, | |
| 1752 | {"sqshrn", 0x5f009400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0}, | |
| 1753 | {"sqrshrn", 0x5f009c00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0}, | |
| 1754 | {"scvtf", 0x5f00e400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0}, | |
| 1755 | {"fcvtzs", 0x5f00fc00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0}, | |
| 1756 | {"ushr", 0x7f000400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0}, | |
| 1757 | {"usra", 0x7f001400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0}, | |
| 1758 | {"urshr", 0x7f002400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0}, | |
| 1759 | {"ursra", 0x7f003400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0}, | |
| 1760 | {"sri", 0x7f004400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0}, | |
| 1761 | {"sli", 0x7f005400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT_D, 0}, | |
| 1762 | {"sqshlu", 0x7f006400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0}, | |
| 1763 | {"uqshl", 0x7f007400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0}, | |
| 1764 | {"sqshrun", 0x7f008400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0}, | |
| 1765 | {"sqrshrun", 0x7f008c00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0}, | |
| 1766 | {"uqshrn", 0x7f009400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0}, | |
| 1767 | {"uqrshrn", 0x7f009c00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0}, | |
| 1768 | {"ucvtf", 0x7f00e400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0}, | |
| 1769 | {"fcvtzu", 0x7f00fc00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0}, | |
| 1770 | /* Bitfield. */ | |
| 1771 | {"sbfm", 0x13000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N}, | |
| 1772 | {"sbfiz", 0x13000000, 0x7f800000, bitfield, OP_SBFIZ, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV}, | |
| 1773 | {"sbfx", 0x13000000, 0x7f800000, bitfield, OP_SBFX, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV}, | |
| 1774 | {"sxtb", 0x13001c00, 0x7fbffc00, bitfield, 0, CORE, OP2 (Rd, Rn), QL_EXT, F_ALIAS | F_P3 | F_SF | F_N}, | |
| 1775 | {"sxth", 0x13003c00, 0x7fbffc00, bitfield, 0, CORE, OP2 (Rd, Rn), QL_EXT, F_ALIAS | F_P3 | F_SF | F_N}, | |
| 1776 | {"sxtw", 0x93407c00, 0xfffffc00, bitfield, 0, CORE, OP2 (Rd, Rn), QL_EXT_W, F_ALIAS | F_P3}, | |
| 1777 | {"asr", 0x13000000, 0x7f800000, bitfield, OP_ASR_IMM, CORE, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV}, | |
| 1778 | {"bfm", 0x33000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N}, | |
| 1779 | {"bfi", 0x33000000, 0x7f800000, bitfield, OP_BFI, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV}, | |
| 1780 | {"bfxil", 0x33000000, 0x7f800000, bitfield, OP_BFXIL, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV}, | |
| 1781 | {"ubfm", 0x53000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N}, | |
| 1782 | {"ubfiz", 0x53000000, 0x7f800000, bitfield, OP_UBFIZ, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV}, | |
| 1783 | {"ubfx", 0x53000000, 0x7f800000, bitfield, OP_UBFX, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV}, | |
| 1784 | {"uxtb", 0x53001c00, 0xfffffc00, bitfield, OP_UXTB, CORE, OP2 (Rd, Rn), QL_I2SAMEW, F_ALIAS | F_P3}, | |
| 1785 | {"uxth", 0x53003c00, 0xfffffc00, bitfield, OP_UXTH, CORE, OP2 (Rd, Rn), QL_I2SAMEW, F_ALIAS | F_P3}, | |
| 1786 | {"lsl", 0x53000000, 0x7f800000, bitfield, OP_LSL_IMM, CORE, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV}, | |
| 1787 | {"lsr", 0x53000000, 0x7f800000, bitfield, OP_LSR_IMM, CORE, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV}, | |
| 1788 | /* Unconditional branch (immediate). */ | |
| 1789 | {"b", 0x14000000, 0xfc000000, branch_imm, OP_B, CORE, OP1 (ADDR_PCREL26), QL_PCREL_26, 0}, | |
| 1790 | {"bl", 0x94000000, 0xfc000000, branch_imm, OP_BL, CORE, OP1 (ADDR_PCREL26), QL_PCREL_26, 0}, | |
| 1791 | /* Unconditional branch (register). */ | |
| 1792 | {"br", 0xd61f0000, 0xfffffc1f, branch_reg, 0, CORE, OP1 (Rn), QL_I1X, 0}, | |
| 1793 | {"blr", 0xd63f0000, 0xfffffc1f, branch_reg, 0, CORE, OP1 (Rn), QL_I1X, 0}, | |
| 1794 | {"ret", 0xd65f0000, 0xfffffc1f, branch_reg, 0, CORE, OP1 (Rn), QL_I1X, F_OPD0_OPT | F_DEFAULT (30)}, | |
| 1795 | {"eret", 0xd69f03e0, 0xffffffff, branch_reg, 0, CORE, OP0 (), {}, 0}, | |
| 1796 | {"drps", 0xd6bf03e0, 0xffffffff, branch_reg, 0, CORE, OP0 (), {}, 0}, | |
| 1797 | /* Compare & branch (immediate). */ | |
| 1798 | {"cbz", 0x34000000, 0x7f000000, compbranch, 0, CORE, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF}, | |
| 1799 | {"cbnz", 0x35000000, 0x7f000000, compbranch, 0, CORE, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF}, | |
| 1800 | /* Conditional branch (immediate). */ | |
| 1801 | {"b.c", 0x54000000, 0xff000010, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_COND}, | |
| 1802 | /* Conditional compare (immediate). */ | |
| 1803 | {"ccmn", 0x3a400800, 0x7fe00c10, condcmp_imm, 0, CORE, OP4 (Rn, CCMP_IMM, NZCV, COND), QL_CCMP_IMM, F_SF}, | |
| 1804 | {"ccmp", 0x7a400800, 0x7fe00c10, condcmp_imm, 0, CORE, OP4 (Rn, CCMP_IMM, NZCV, COND), QL_CCMP_IMM, F_SF}, | |
| 1805 | /* Conditional compare (register). */ | |
| 1806 | {"ccmn", 0x3a400000, 0x7fe00c10, condcmp_reg, 0, CORE, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF}, | |
| 1807 | {"ccmp", 0x7a400000, 0x7fe00c10, condcmp_reg, 0, CORE, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF}, | |
| 1808 | /* Conditional select. */ | |
| 1809 | {"csel", 0x1a800000, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_SF}, | |
| 1810 | {"csinc", 0x1a800400, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF}, | |
| 68a64283 YZ |
1811 | {"cinc", 0x1a800400, 0x7fe00c00, condsel, OP_CINC, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV}, |
| 1812 | {"cset", 0x1a9f07e0, 0x7fff0fe0, condsel, OP_CSET, CORE, OP2 (Rd, COND1), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV}, | |
| a06ea964 | 1813 | {"csinv", 0x5a800000, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF}, |
| 68a64283 YZ |
1814 | {"cinv", 0x5a800000, 0x7fe00c00, condsel, OP_CINV, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV}, |
| 1815 | {"csetm", 0x5a9f03e0, 0x7fff0fe0, condsel, OP_CSETM, CORE, OP2 (Rd, COND1), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV}, | |
| a06ea964 | 1816 | {"csneg", 0x5a800400, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF}, |
| 68a64283 | 1817 | {"cneg", 0x5a800400, 0x7fe00c00, condsel, OP_CNEG, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV}, |
| a06ea964 NC |
1818 | /* Crypto AES. */ |
| 1819 | {"aese", 0x4e284800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0}, | |
| 1820 | {"aesd", 0x4e285800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0}, | |
| 1821 | {"aesmc", 0x4e286800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0}, | |
| 1822 | {"aesimc", 0x4e287800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0}, | |
| 1823 | /* Crypto two-reg SHA. */ | |
| 1824 | {"sha1h", 0x5e280800, 0xfffffc00, cryptosha2, 0, CRYPTO, OP2 (Fd, Fn), QL_2SAMES, 0}, | |
| 1825 | {"sha1su1", 0x5e281800, 0xfffffc00, cryptosha2, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME4S, 0}, | |
| 1826 | {"sha256su0", 0x5e282800, 0xfffffc00, cryptosha2, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME4S, 0}, | |
| 1827 | /* Crypto three-reg SHA. */ | |
| 1828 | {"sha1c", 0x5e000000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0}, | |
| 1829 | {"sha1p", 0x5e001000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0}, | |
| 1830 | {"sha1m", 0x5e002000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0}, | |
| 1831 | {"sha1su0", 0x5e003000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0}, | |
| 1832 | {"sha256h", 0x5e004000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHA256UPT, 0}, | |
| 1833 | {"sha256h2", 0x5e005000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHA256UPT, 0}, | |
| 1834 | {"sha256su1", 0x5e006000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0}, | |
| 1835 | /* Data-processing (1 source). */ | |
| 1836 | {"rbit", 0x5ac00000, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF}, | |
| 1837 | {"rev16", 0x5ac00400, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF}, | |
| 1838 | {"rev", 0x5ac00800, 0xfffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAMEW, 0}, | |
| 1839 | {"rev", 0xdac00c00, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAMEX, 0}, | |
| 1840 | {"clz", 0x5ac01000, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF}, | |
| 1841 | {"cls", 0x5ac01400, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF}, | |
| 1842 | {"rev32", 0xdac00800, 0xfffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAMEX, 0}, | |
| 1843 | /* Data-processing (2 source). */ | |
| 1844 | {"udiv", 0x1ac00800, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF}, | |
| 1845 | {"sdiv", 0x1ac00c00, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF}, | |
| 1846 | {"lslv", 0x1ac02000, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS}, | |
| 1847 | {"lsl", 0x1ac02000, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS}, | |
| 1848 | {"lsrv", 0x1ac02400, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS}, | |
| 1849 | {"lsr", 0x1ac02400, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS}, | |
| 1850 | {"asrv", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS}, | |
| 1851 | {"asr", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS}, | |
| 1852 | {"rorv", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS}, | |
| 1853 | {"ror", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS}, | |
| e60bb1dd YZ |
1854 | /* CRC instructions. */ |
| 1855 | {"crc32b", 0x1ac04000, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0}, | |
| 1856 | {"crc32h", 0x1ac04400, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0}, | |
| 1857 | {"crc32w", 0x1ac04800, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0}, | |
| 1858 | {"crc32x", 0x9ac04c00, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3WWX, 0}, | |
| 1859 | {"crc32cb", 0x1ac05000, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0}, | |
| 1860 | {"crc32ch", 0x1ac05400, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0}, | |
| 1861 | {"crc32cw", 0x1ac05800, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0}, | |
| 1862 | {"crc32cx", 0x9ac05c00, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3WWX, 0}, | |
| a06ea964 NC |
1863 | /* Data-processing (3 source). */ |
| 1864 | {"madd", 0x1b000000, 0x7fe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF}, | |
| 1865 | {"mul", 0x1b007c00, 0x7fe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_ALIAS | F_SF}, | |
| 1866 | {"msub", 0x1b008000, 0x7fe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF}, | |
| 1867 | {"mneg", 0x1b00fc00, 0x7fe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_ALIAS | F_SF}, | |
| 1868 | {"smaddl", 0x9b200000, 0xffe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS}, | |
| 1869 | {"smull", 0x9b207c00, 0xffe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS}, | |
| 1870 | {"smsubl", 0x9b208000, 0xffe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS}, | |
| 1871 | {"smnegl", 0x9b20fc00, 0xffe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS}, | |
| 1872 | {"smulh", 0x9b407c00, 0xffe08000, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEX, 0}, | |
| 1873 | {"umaddl", 0x9ba00000, 0xffe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS}, | |
| 1874 | {"umull", 0x9ba07c00, 0xffe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS}, | |
| 1875 | {"umsubl", 0x9ba08000, 0xffe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS}, | |
| 1876 | {"umnegl", 0x9ba0fc00, 0xffe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS}, | |
| 1877 | {"umulh", 0x9bc07c00, 0xffe08000, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEX, 0}, | |
| 1878 | /* Excep'n generation. */ | |
| 1879 | {"svc", 0xd4000001, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0}, | |
| 1880 | {"hvc", 0xd4000002, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0}, | |
| 1881 | {"smc", 0xd4000003, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0}, | |
| 1882 | {"brk", 0xd4200000, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0}, | |
| 1883 | {"hlt", 0xd4400000, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0}, | |
| 1884 | {"dcps1", 0xd4a00001, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)}, | |
| 1885 | {"dcps2", 0xd4a00002, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)}, | |
| 1886 | {"dcps3", 0xd4a00003, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)}, | |
| 1887 | /* Extract. */ | |
| 1888 | {"extr", 0x13800000, 0x7fa00000, extract, 0, CORE, OP4 (Rd, Rn, Rm, IMMS), QL_EXTR, F_HAS_ALIAS | F_SF | F_N}, | |
| 1889 | {"ror", 0x13800000, 0x7fa00000, extract, OP_ROR_IMM, CORE, OP3 (Rd, Rm, IMMS), QL_SHIFT, F_ALIAS | F_CONV}, | |
| 1890 | /* Floating-point<->fixed-point conversions. */ | |
| 1891 | {"scvtf", 0x1e020000, 0x7f3f0000, float2fix, 0, FP, OP3 (Fd, Rn, FBITS), QL_FIX2FP, F_FPTYPE | F_SF}, | |
| 1892 | {"ucvtf", 0x1e030000, 0x7f3f0000, float2fix, 0, FP, OP3 (Fd, Rn, FBITS), QL_FIX2FP, F_FPTYPE | F_SF}, | |
| 1893 | {"fcvtzs", 0x1e180000, 0x7f3f0000, float2fix, 0, FP, OP3 (Rd, Fn, FBITS), QL_FP2FIX, F_FPTYPE | F_SF}, | |
| 1894 | {"fcvtzu", 0x1e190000, 0x7f3f0000, float2fix, 0, FP, OP3 (Rd, Fn, FBITS), QL_FP2FIX, F_FPTYPE | F_SF}, | |
| 1895 | /* Floating-point<->integer conversions. */ | |
| 1896 | {"fcvtns", 0x1e200000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF}, | |
| 1897 | {"fcvtnu", 0x1e210000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF}, | |
| 1898 | {"scvtf", 0x1e220000, 0x7f3ffc00, float2int, 0, FP, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF}, | |
| 1899 | {"ucvtf", 0x1e230000, 0x7f3ffc00, float2int, 0, FP, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF}, | |
| 1900 | {"fcvtas", 0x1e240000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF}, | |
| 1901 | {"fcvtau", 0x1e250000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF}, | |
| 1902 | {"fmov", 0x1e260000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF}, | |
| 1903 | {"fmov", 0x1e270000, 0x7f3ffc00, float2int, 0, FP, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF}, | |
| 1904 | {"fcvtps", 0x1e280000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF}, | |
| 1905 | {"fcvtpu", 0x1e290000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF}, | |
| 1906 | {"fcvtms", 0x1e300000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF}, | |
| 1907 | {"fcvtmu", 0x1e310000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF}, | |
| 1908 | {"fcvtzs", 0x1e380000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF}, | |
| 1909 | {"fcvtzu", 0x1e390000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF}, | |
| 1910 | {"fmov", 0x9eae0000, 0xfffffc00, float2int, 0, FP, OP2 (Rd, VnD1), QL_XVD1, 0}, | |
| 1911 | {"fmov", 0x9eaf0000, 0xfffffc00, float2int, 0, FP, OP2 (VdD1, Rn), QL_VD1X, 0}, | |
| 1912 | /* Floating-point conditional compare. */ | |
| 1913 | {"fccmp", 0x1e200400, 0xff200c10, floatccmp, 0, FP, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE}, | |
| 1914 | {"fccmpe", 0x1e200410, 0xff200c10, floatccmp, 0, FP, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE}, | |
| 1915 | /* Floating-point compare. */ | |
| 1916 | {"fcmp", 0x1e202000, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, Fm), QL_FP2, F_FPTYPE}, | |
| 1917 | {"fcmpe", 0x1e202010, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, Fm), QL_FP2, F_FPTYPE}, | |
| 1918 | {"fcmp", 0x1e202008, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, FPIMM0), QL_DST_SD, F_FPTYPE}, | |
| 1919 | {"fcmpe", 0x1e202018, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, FPIMM0), QL_DST_SD, F_FPTYPE}, | |
| 1920 | /* Floating-point data-processing (1 source). */ | |
| 1921 | {"fmov", 0x1e204000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE}, | |
| 1922 | {"fabs", 0x1e20c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE}, | |
| 1923 | {"fneg", 0x1e214000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE}, | |
| 1924 | {"fsqrt", 0x1e21c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE}, | |
| 1925 | {"fcvt", 0x1e224000, 0xff3e7c00, floatdp1, OP_FCVT, FP, OP2 (Fd, Fn), QL_FCVT, F_FPTYPE | F_MISC}, | |
| 1926 | {"frintn", 0x1e244000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE}, | |
| 1927 | {"frintp", 0x1e24c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE}, | |
| 1928 | {"frintm", 0x1e254000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE}, | |
| 1929 | {"frintz", 0x1e25c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE}, | |
| 1930 | {"frinta", 0x1e264000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE}, | |
| 1931 | {"frintx", 0x1e274000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE}, | |
| 1932 | {"frinti", 0x1e27c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE}, | |
| 1933 | /* Floating-point data-processing (2 source). */ | |
| 1934 | {"fmul", 0x1e200800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE}, | |
| 1935 | {"fdiv", 0x1e201800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE}, | |
| 1936 | {"fadd", 0x1e202800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE}, | |
| 1937 | {"fsub", 0x1e203800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE}, | |
| 1938 | {"fmax", 0x1e204800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE}, | |
| 1939 | {"fmin", 0x1e205800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE}, | |
| 1940 | {"fmaxnm", 0x1e206800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE}, | |
| 1941 | {"fminnm", 0x1e207800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE}, | |
| 1942 | {"fnmul", 0x1e208800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE}, | |
| 1943 | /* Floating-point data-processing (3 source). */ | |
| 1944 | {"fmadd", 0x1f000000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE}, | |
| 1945 | {"fmsub", 0x1f008000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE}, | |
| 1946 | {"fnmadd", 0x1f200000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE}, | |
| 1947 | {"fnmsub", 0x1f208000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE}, | |
| 1948 | /* Floating-point immediate. */ | |
| 1949 | {"fmov", 0x1e201000, 0xff201fe0, floatimm, 0, FP, OP2 (Fd, FPIMM), QL_DST_SD, F_FPTYPE}, | |
| 1950 | /* Floating-point conditional select. */ | |
| 1951 | {"fcsel", 0x1e200c00, 0xff200c00, floatsel, 0, FP, OP4 (Fd, Fn, Fm, COND), QL_FP_COND, F_FPTYPE}, | |
| 1952 | /* Load/store register (immediate indexed). */ | |
| 1953 | {"strb", 0x38000400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0}, | |
| 1954 | {"ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0}, | |
| 1955 | {"ldrsb", 0x38800400, 0xffa00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE}, | |
| 1956 | {"str", 0x3c000400, 0x3f600400, ldst_imm9, 0, CORE, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0}, | |
| 1957 | {"ldr", 0x3c400400, 0x3f600400, ldst_imm9, 0, CORE, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0}, | |
| 1958 | {"strh", 0x78000400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0}, | |
| 1959 | {"ldrh", 0x78400400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0}, | |
| 1960 | {"ldrsh", 0x78800400, 0xffa00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE}, | |
| 1961 | {"str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q}, | |
| 1962 | {"ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q}, | |
| 1963 | {"ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0}, | |
| 1964 | /* Load/store register (unsigned immediate). */ | |
| 1965 | {"strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0}, | |
| 1966 | {"ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0}, | |
| 1967 | {"ldrsb", 0x39800000, 0xff800000, ldst_pos, OP_LDRSB_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R8, F_LDS_SIZE}, | |
| 1968 | {"str", 0x3d000000, 0x3f400000, ldst_pos, OP_STRF_POS, CORE, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0}, | |
| 1969 | {"ldr", 0x3d400000, 0x3f400000, ldst_pos, OP_LDRF_POS, CORE, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0}, | |
| 1970 | {"strh", 0x79000000, 0xffc00000, ldst_pos, OP_STRH_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0}, | |
| 1971 | {"ldrh", 0x79400000, 0xffc00000, ldst_pos, OP_LDRH_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0}, | |
| 1972 | {"ldrsh", 0x79800000, 0xff800000, ldst_pos, OP_LDRSH_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R16, F_LDS_SIZE}, | |
| 1973 | {"str", 0xb9000000, 0xbfc00000, ldst_pos, OP_STR_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q}, | |
| 1974 | {"ldr", 0xb9400000, 0xbfc00000, ldst_pos, OP_LDR_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q}, | |
| 1975 | {"ldrsw", 0xb9800000, 0xffc00000, ldst_pos, OP_LDRSW_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, 0}, | |
| 1976 | {"prfm", 0xf9800000, 0xffc00000, ldst_pos, OP_PRFM_POS, CORE, OP2 (PRFOP, ADDR_UIMM12), QL_LDST_PRFM, 0}, | |
| 1977 | /* Load/store register (register offset). */ | |
| 1978 | {"strb", 0x38200800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0}, | |
| 1979 | {"ldrb", 0x38600800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0}, | |
| 1980 | {"ldrsb", 0x38a00800, 0xffa00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_R8, F_LDS_SIZE}, | |
| 1981 | {"str", 0x3c200800, 0x3f600c00, ldst_regoff, 0, CORE, OP2 (Ft, ADDR_REGOFF), QL_LDST_FP, 0}, | |
| 1982 | {"ldr", 0x3c600800, 0x3f600c00, ldst_regoff, 0, CORE, OP2 (Ft, ADDR_REGOFF), QL_LDST_FP, 0}, | |
| 1983 | {"strh", 0x78200800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_W16, 0}, | |
| 1984 | {"ldrh", 0x78600800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_W16, 0}, | |
| 1985 | {"ldrsh", 0x78a00800, 0xffa00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_R16, F_LDS_SIZE}, | |
| 1986 | {"str", 0xb8200800, 0xbfe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_R, F_GPRSIZE_IN_Q}, | |
| 1987 | {"ldr", 0xb8600800, 0xbfe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_R, F_GPRSIZE_IN_Q}, | |
| 1988 | {"ldrsw", 0xb8a00800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_X32, 0}, | |
| 1989 | {"prfm", 0xf8a00800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (PRFOP, ADDR_REGOFF), QL_LDST_PRFM, 0}, | |
| 1990 | /* Load/store register (unprivileged). */ | |
| 1991 | {"sttrb", 0x38000800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0}, | |
| 1992 | {"ldtrb", 0x38400800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0}, | |
| 1993 | {"ldtrsb", 0x38800800, 0xffa00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE}, | |
| 1994 | {"sttrh", 0x78000800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0}, | |
| 1995 | {"ldtrh", 0x78400800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0}, | |
| 1996 | {"ldtrsh", 0x78800800, 0xffa00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE}, | |
| 1997 | {"sttr", 0xb8000800, 0xbfe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q}, | |
| 1998 | {"ldtr", 0xb8400800, 0xbfe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q}, | |
| 1999 | {"ldtrsw", 0xb8800800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0}, | |
| 2000 | /* Load/store register (unscaled immediate). */ | |
| c8f89a34 JW |
2001 | {"sturb", 0x38000000, 0xffe00c00, ldst_unscaled, OP_STURB, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0}, |
| 2002 | {"ldurb", 0x38400000, 0xffe00c00, ldst_unscaled, OP_LDURB, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0}, | |
| 2003 | {"ldursb", 0x38800000, 0xffa00c00, ldst_unscaled, OP_LDURSB, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE}, | |
| 2004 | {"stur", 0x3c000000, 0x3f600c00, ldst_unscaled, OP_STURV, CORE, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0}, | |
| 2005 | {"ldur", 0x3c400000, 0x3f600c00, ldst_unscaled, OP_LDURV, CORE, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0}, | |
| 2006 | {"sturh", 0x78000000, 0xffe00c00, ldst_unscaled, OP_STURH, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0}, | |
| 2007 | {"ldurh", 0x78400000, 0xffe00c00, ldst_unscaled, OP_LDURH, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0}, | |
| 2008 | {"ldursh", 0x78800000, 0xffa00c00, ldst_unscaled, OP_LDURSH, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE}, | |
| 2009 | {"stur", 0xb8000000, 0xbfe00c00, ldst_unscaled, OP_STUR, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q}, | |
| 2010 | {"ldur", 0xb8400000, 0xbfe00c00, ldst_unscaled, OP_LDUR, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q}, | |
| 2011 | {"ldursw", 0xb8800000, 0xffe00c00, ldst_unscaled, OP_LDURSW, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0}, | |
| 2012 | {"prfum", 0xf8800000, 0xffe00c00, ldst_unscaled, OP_PRFUM, CORE, OP2 (PRFOP, ADDR_SIMM9), QL_LDST_PRFM, 0}, | |
| a06ea964 NC |
2013 | /* Load/store exclusive. */ |
| 2014 | {"stxrb", 0x8007c00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2015 | {"stlxrb", 0x800fc00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2016 | {"ldxrb", 0x85f7c00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0}, | |
| 2017 | {"ldaxrb", 0x85ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0}, | |
| 2018 | {"stlrb", 0x89ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0}, | |
| ee804238 | 2019 | {"ldarb", 0x8dffc00, 0xffeffc00, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0}, |
| a06ea964 NC |
2020 | {"stxrh", 0x48007c00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, |
| 2021 | {"stlxrh", 0x4800fc00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2022 | {"ldxrh", 0x485f7c00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0}, | |
| 2023 | {"ldaxrh", 0x485ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0}, | |
| 2024 | {"stlrh", 0x489ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0}, | |
| ee804238 | 2025 | {"ldarh", 0x48dffc00, 0xffeffc00, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0}, |
| a06ea964 NC |
2026 | {"stxr", 0x88007c00, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q}, |
| 2027 | {"stlxr", 0x8800fc00, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q}, | |
| 2028 | {"stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, CORE, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q}, | |
| 2029 | {"stlxp", 0x88208000, 0xbfe08000, ldstexcl, 0, CORE, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q}, | |
| 2030 | {"ldxr", 0x885f7c00, 0xbfe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q}, | |
| 2031 | {"ldaxr", 0x885ffc00, 0xbfe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q}, | |
| 2032 | {"ldxp", 0x887f0000, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q}, | |
| 2033 | {"ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q}, | |
| 2034 | {"stlr", 0x889ffc00, 0xbfe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q}, | |
| ee804238 | 2035 | {"ldar", 0x88dffc00, 0xbfeffc00, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q}, |
| 290806fd MW |
2036 | /* Limited Ordering Regions load/store instructions. */ |
| 2037 | {"ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q}, | |
| 2038 | {"ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0}, | |
| 2039 | {"ldlarh", 0x48df7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0}, | |
| 2040 | {"stllr", 0x889f7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q}, | |
| 2041 | {"stllrb", 0x089f7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0}, | |
| 2042 | {"stllrh", 0x489f7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0}, | |
| a06ea964 NC |
2043 | /* Load/store no-allocate pair (offset). */ |
| 2044 | {"stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF}, | |
| 2045 | {"ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF}, | |
| 2046 | {"stnp", 0x2c000000, 0x3fc00000, ldstnapair_offs, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0}, | |
| 2047 | {"ldnp", 0x2c400000, 0x3fc00000, ldstnapair_offs, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0}, | |
| 2048 | /* Load/store register pair (offset). */ | |
| 2049 | {"stp", 0x29000000, 0x7ec00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF}, | |
| 2050 | {"ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF}, | |
| 2051 | {"stp", 0x2d000000, 0x3fc00000, ldstpair_off, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0}, | |
| 2052 | {"ldp", 0x2d400000, 0x3fc00000, ldstpair_off, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0}, | |
| 2053 | {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0}, | |
| 2054 | /* Load/store register pair (indexed). */ | |
| 2055 | {"stp", 0x28800000, 0x7ec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF}, | |
| 2056 | {"ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF}, | |
| 2057 | {"stp", 0x2c800000, 0x3ec00000, ldstpair_indexed, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0}, | |
| 2058 | {"ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0}, | |
| 2059 | {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0}, | |
| 2060 | /* Load register (literal). */ | |
| 2061 | {"ldr", 0x18000000, 0xbf000000, loadlit, OP_LDR_LIT, CORE, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_GPRSIZE_IN_Q}, | |
| 2062 | {"ldr", 0x1c000000, 0x3f000000, loadlit, OP_LDRV_LIT, CORE, OP2 (Ft, ADDR_PCREL19), QL_FP_PCREL, 0}, | |
| 2063 | {"ldrsw", 0x98000000, 0xff000000, loadlit, OP_LDRSW_LIT, CORE, OP2 (Rt, ADDR_PCREL19), QL_X_PCREL, 0}, | |
| 2064 | {"prfm", 0xd8000000, 0xff000000, loadlit, OP_PRFM_LIT, CORE, OP2 (PRFOP, ADDR_PCREL19), QL_PRFM_PCREL, 0}, | |
| 2065 | /* Logical (immediate). */ | |
| 2066 | {"and", 0x12000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF}, | |
| 2067 | {"bic", 0x12000000, 0x7f800000, log_imm, OP_BIC, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_ALIAS | F_PSEUDO | F_SF}, | |
| 2068 | {"orr", 0x32000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF}, | |
| fb098a1e | 2069 | {"mov", 0x320003e0, 0x7f8003e0, log_imm, OP_MOV_IMM_LOG, CORE, OP2 (Rd_SP, IMM_MOV), QL_R1NIL, F_ALIAS | F_P1 | F_SF | F_CONV}, |
| a06ea964 NC |
2070 | {"eor", 0x52000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_SF}, |
| 2071 | {"ands", 0x72000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF}, | |
| 2072 | {"tst", 0x7200001f, 0x7f80001f, log_imm, 0, CORE, OP2 (Rn, LIMM), QL_R1NIL, F_ALIAS | F_SF}, | |
| 2073 | /* Logical (shifted register). */ | |
| 2074 | {"and", 0xa000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF}, | |
| 2075 | {"bic", 0xa200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF}, | |
| 2076 | {"orr", 0x2a000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF}, | |
| 2077 | {"mov", 0x2a0003e0, 0x7f2003e0, log_shift, 0, CORE, OP2 (Rd, Rm), QL_I2SAMER, F_ALIAS | F_SF}, | |
| 2078 | {"uxtw", 0x2a0003e0, 0x7f2003e0, log_shift, OP_UXTW, CORE, OP2 (Rd, Rm), QL_I2SAMEW, F_ALIAS | F_PSEUDO}, | |
| 2079 | {"orn", 0x2a200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF}, | |
| 2080 | {"mvn", 0x2a2003e0, 0x7f2003e0, log_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF}, | |
| 2081 | {"eor", 0x4a000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF}, | |
| 2082 | {"eon", 0x4a200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF}, | |
| 2083 | {"ands", 0x6a000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF}, | |
| 2084 | {"tst", 0x6a00001f, 0x7f20001f, log_shift, 0, CORE, OP2 (Rn, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF}, | |
| 2085 | {"bics", 0x6a200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF}, | |
| ee804238 JW |
2086 | /* LSE extension (atomic). */ |
| 2087 | {"casb", 0x8a07c00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2088 | {"cash", 0x48a07c00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2089 | {"cas", 0x88a07c00, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2090 | {"casab", 0x8e07c00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2091 | {"caslb", 0x8a0fc00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2092 | {"casalb", 0x8e0fc00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2093 | {"casah", 0x48e07c00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2094 | {"caslh", 0x48a0fc00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2095 | {"casalh", 0x48e0fc00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2096 | {"casa", 0x88e07c00, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2097 | {"casl", 0x88a0fc00, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2098 | {"casal", 0x88e0fc00, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2099 | {"casp", 0x8207c00, 0xbfe0fc00, lse_atomic, 0, LSE, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ}, | |
| 2100 | {"caspa", 0x8607c00, 0xbfe0fc00, lse_atomic, 0, LSE, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ}, | |
| 2101 | {"caspl", 0x820fc00, 0xbfe0fc00, lse_atomic, 0, LSE, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ}, | |
| 2102 | {"caspal", 0x860fc00, 0xbfe0fc00, lse_atomic, 0, LSE, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ}, | |
| 2103 | {"swpb", 0x38208000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2104 | {"swph", 0x78208000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2105 | {"swp", 0xb8208000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2106 | {"swpab", 0x38a08000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2107 | {"swplb", 0x38608000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2108 | {"swpalb", 0x38e08000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2109 | {"swpah", 0x78a08000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2110 | {"swplh", 0x78608000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2111 | {"swpalh", 0x78e08000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2112 | {"swpa", 0xb8a08000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2113 | {"swpl", 0xb8608000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2114 | {"swpal", 0xb8e08000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2115 | {"ldaddb", 0x38200000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2116 | {"ldaddh", 0x78200000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2117 | {"ldadd", 0xb8200000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS}, | |
| 2118 | {"ldaddab", 0x38a00000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2119 | {"ldaddlb", 0x38600000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2120 | {"ldaddalb", 0x38e00000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2121 | {"ldaddah", 0x78a00000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2122 | {"ldaddlh", 0x78600000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2123 | {"ldaddalh", 0x78e00000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2124 | {"ldadda", 0xb8a00000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2125 | {"ldaddl", 0xb8600000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS}, | |
| 2126 | {"ldaddal", 0xb8e00000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2127 | {"ldclrb", 0x38201000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2128 | {"ldclrh", 0x78201000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2129 | {"ldclr", 0xb8201000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS}, | |
| 2130 | {"ldclrab", 0x38a01000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2131 | {"ldclrlb", 0x38601000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2132 | {"ldclralb", 0x38e01000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2133 | {"ldclrah", 0x78a01000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2134 | {"ldclrlh", 0x78601000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2135 | {"ldclralh", 0x78e01000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2136 | {"ldclra", 0xb8a01000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2137 | {"ldclrl", 0xb8601000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS}, | |
| 2138 | {"ldclral", 0xb8e01000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2139 | {"ldeorb", 0x38202000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2140 | {"ldeorh", 0x78202000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2141 | {"ldeor", 0xb8202000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS}, | |
| 2142 | {"ldeorab", 0x38a02000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2143 | {"ldeorlb", 0x38602000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2144 | {"ldeoralb", 0x38e02000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2145 | {"ldeorah", 0x78a02000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2146 | {"ldeorlh", 0x78602000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2147 | {"ldeoralh", 0x78e02000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2148 | {"ldeora", 0xb8a02000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2149 | {"ldeorl", 0xb8602000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS}, | |
| 2150 | {"ldeoral", 0xb8e02000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2151 | {"ldsetb", 0x38203000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2152 | {"ldseth", 0x78203000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2153 | {"ldset", 0xb8203000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS}, | |
| 2154 | {"ldsetab", 0x38a03000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2155 | {"ldsetlb", 0x38603000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2156 | {"ldsetalb", 0x38e03000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2157 | {"ldsetah", 0x78a03000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2158 | {"ldsetlh", 0x78603000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2159 | {"ldsetalh", 0x78e03000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2160 | {"ldseta", 0xb8a03000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2161 | {"ldsetl", 0xb8603000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS}, | |
| 2162 | {"ldsetal", 0xb8e03000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2163 | {"ldsmaxb", 0x38204000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2164 | {"ldsmaxh", 0x78204000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2165 | {"ldsmax", 0xb8204000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS}, | |
| 2166 | {"ldsmaxab", 0x38a04000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2167 | {"ldsmaxlb", 0x38604000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2168 | {"ldsmaxalb", 0x38e04000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2169 | {"ldsmaxah", 0x78a04000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2170 | {"ldsmaxlh", 0x78604000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2171 | {"ldsmaxalh", 0x78e04000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2172 | {"ldsmaxa", 0xb8a04000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2173 | {"ldsmaxl", 0xb8604000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS}, | |
| 2174 | {"ldsmaxal", 0xb8e04000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2175 | {"ldsminb", 0x38205000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2176 | {"ldsminh", 0x78205000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2177 | {"ldsmin", 0xb8205000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS}, | |
| 2178 | {"ldsminab", 0x38a05000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2179 | {"ldsminlb", 0x38605000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2180 | {"ldsminalb", 0x38e05000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2181 | {"ldsminah", 0x78a05000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2182 | {"ldsminlh", 0x78605000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2183 | {"ldsminalh", 0x78e05000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2184 | {"ldsmina", 0xb8a05000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2185 | {"ldsminl", 0xb8605000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS}, | |
| 2186 | {"ldsminal", 0xb8e05000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2187 | {"ldumaxb", 0x38206000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2188 | {"ldumaxh", 0x78206000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2189 | {"ldumax", 0xb8206000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS}, | |
| 2190 | {"ldumaxab", 0x38a06000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2191 | {"ldumaxlb", 0x38606000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2192 | {"ldumaxalb", 0x38e06000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2193 | {"ldumaxah", 0x78a06000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2194 | {"ldumaxlh", 0x78606000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2195 | {"ldumaxalh", 0x78e06000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2196 | {"ldumaxa", 0xb8a06000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2197 | {"ldumaxl", 0xb8606000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS}, | |
| 2198 | {"ldumaxal", 0xb8e06000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2199 | {"lduminb", 0x38207000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2200 | {"lduminh", 0x78207000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2201 | {"ldumin", 0xb8207000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS}, | |
| 2202 | {"lduminab", 0x38a07000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2203 | {"lduminlb", 0x38607000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2204 | {"lduminalb", 0x38e07000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2205 | {"lduminah", 0x78a07000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2206 | {"lduminlh", 0x78607000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS}, | |
| 2207 | {"lduminalh", 0x78e07000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0}, | |
| 2208 | {"ldumina", 0xb8a07000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2209 | {"lduminl", 0xb8607000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS}, | |
| 2210 | {"lduminal", 0xb8e07000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ}, | |
| 2211 | {"staddb", 0x3820001f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2212 | {"staddh", 0x7820001f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2213 | {"stadd", 0xb820001f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS}, | |
| 2214 | {"staddlb", 0x3860001f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2215 | {"staddlh", 0x7860001f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2216 | {"staddl", 0xb860001f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS}, | |
| 2217 | {"stclrb", 0x3820101f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2218 | {"stclrh", 0x7820101f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2219 | {"stclr", 0xb820101f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS}, | |
| 2220 | {"stclrlb", 0x3860101f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2221 | {"stclrlh", 0x7860101f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2222 | {"stclrl", 0xb860101f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS}, | |
| 2223 | {"steorb", 0x3820201f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2224 | {"steorh", 0x7820201f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2225 | {"steor", 0xb820201f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS}, | |
| 2226 | {"steorlb", 0x3860201f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2227 | {"steorlh", 0x7860201f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2228 | {"steorl", 0xb860201f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS}, | |
| 2229 | {"stsetb", 0x3820301f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2230 | {"stseth", 0x7820301f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2231 | {"stset", 0xb820301f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS}, | |
| 2232 | {"stsetlb", 0x3860301f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2233 | {"stsetlh", 0x7860301f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2234 | {"stsetl", 0xb860301f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS}, | |
| 2235 | {"stsmaxb", 0x3820401f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2236 | {"stsmaxh", 0x7820401f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2237 | {"stsmax", 0xb820401f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS}, | |
| 2238 | {"stsmaxlb", 0x3860401f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2239 | {"stsmaxlh", 0x7860401f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2240 | {"stsmaxl", 0xb860401f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS}, | |
| 2241 | {"stsminb", 0x3820501f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2242 | {"stsminh", 0x7820501f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2243 | {"stsmin", 0xb820501f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS}, | |
| 2244 | {"stsminlb", 0x3860501f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2245 | {"stsminlh", 0x7860501f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2246 | {"stsminl", 0xb860501f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS}, | |
| 2247 | {"stumaxb", 0x3820601f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2248 | {"stumaxh", 0x7820601f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2249 | {"stumax", 0xb820601f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS}, | |
| 2250 | {"stumaxlb", 0x3860601f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2251 | {"stumaxlh", 0x7860601f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2252 | {"stumaxl", 0xb860601f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS}, | |
| 2253 | {"stuminb", 0x3820701f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2254 | {"stuminh", 0x7820701f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2255 | {"stumin", 0xb820701f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS}, | |
| 2256 | {"stuminlb", 0x3860701f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2257 | {"stuminlh", 0x7860701f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS}, | |
| 2258 | {"stuminl", 0xb860701f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS}, | |
| a06ea964 NC |
2259 | /* Move wide (immediate). */ |
| 2260 | {"movn", 0x12800000, 0x7f800000, movewide, OP_MOVN, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS}, | |
| fb098a1e | 2261 | {"mov", 0x12800000, 0x7f800000, movewide, OP_MOV_IMM_WIDEN, CORE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV}, |
| a06ea964 | 2262 | {"movz", 0x52800000, 0x7f800000, movewide, OP_MOVZ, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS}, |
| fb098a1e | 2263 | {"mov", 0x52800000, 0x7f800000, movewide, OP_MOV_IMM_WIDE, CORE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV}, |
| a06ea964 NC |
2264 | {"movk", 0x72800000, 0x7f800000, movewide, OP_MOVK, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF}, |
| 2265 | /* PC-rel. addressing. */ | |
| 2266 | {"adr", 0x10000000, 0x9f000000, pcreladdr, 0, CORE, OP2 (Rd, ADDR_PCREL21), QL_ADRP, 0}, | |
| 2267 | {"adrp", 0x90000000, 0x9f000000, pcreladdr, 0, CORE, OP2 (Rd, ADDR_ADRP), QL_ADRP, 0}, | |
| 2268 | /* System. */ | |
| 2269 | {"msr", 0xd500401f, 0xfff8f01f, ic_system, 0, CORE, OP2 (PSTATEFIELD, UIMM4), {}, 0}, | |
| 2270 | {"hint", 0xd503201f, 0xfffff01f, ic_system, 0, CORE, OP1 (UIMM7), {}, F_HAS_ALIAS}, | |
| 2271 | {"nop", 0xd503201f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS}, | |
| 2272 | {"yield", 0xd503203f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS}, | |
| 2273 | {"wfe", 0xd503205f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS}, | |
| 2274 | {"wfi", 0xd503207f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS}, | |
| 2275 | {"sev", 0xd503209f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS}, | |
| 2276 | {"sevl", 0xd50320bf, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS}, | |
| 2277 | {"clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, CORE, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)}, | |
| 2278 | {"dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, CORE, OP1 (BARRIER), {}, 0}, | |
| 2279 | {"dmb", 0xd50330bf, 0xfffff0ff, ic_system, 0, CORE, OP1 (BARRIER), {}, 0}, | |
| 2280 | {"isb", 0xd50330df, 0xfffff0ff, ic_system, 0, CORE, OP1 (BARRIER_ISB), {}, F_OPD0_OPT | F_DEFAULT (0xF)}, | |
| 2281 | {"sys", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP5 (UIMM3_OP1, Cn, Cm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)}, | |
| 2282 | {"at", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_AT, Rt), QL_SRC_X, F_ALIAS}, | |
| 2283 | {"dc", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS}, | |
| 2284 | {"ic", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)}, | |
| 2285 | {"tlbi", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)}, | |
| df7b4545 | 2286 | {"msr", 0xd5000000, 0xffe00000, ic_system, 0, CORE, OP2 (SYSREG, Rt), QL_SRC_X, 0}, |
| a06ea964 | 2287 | {"sysl", 0xd5280000, 0xfff80000, ic_system, 0, CORE, OP5 (Rt, UIMM3_OP1, Cn, Cm, UIMM3_OP2), QL_SYSL, 0}, |
| df7b4545 | 2288 | {"mrs", 0xd5200000, 0xffe00000, ic_system, 0, CORE, OP2 (Rt, SYSREG), QL_DST_X, 0}, |
| a06ea964 NC |
2289 | /* Test & branch (immediate). */ |
| 2290 | {"tbz", 0x36000000, 0x7f000000, testbranch, 0, CORE, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0}, | |
| 2291 | {"tbnz", 0x37000000, 0x7f000000, testbranch, 0, CORE, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0}, | |
| 2292 | /* The old UAL conditional branch mnemonics (to aid portability). */ | |
| 2293 | {"beq", 0x54000000, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO}, | |
| 2294 | {"bne", 0x54000001, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO}, | |
| 2295 | {"bcs", 0x54000002, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO}, | |
| 2296 | {"bhs", 0x54000002, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO}, | |
| 2297 | {"bcc", 0x54000003, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO}, | |
| 2298 | {"blo", 0x54000003, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO}, | |
| 2299 | {"bmi", 0x54000004, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO}, | |
| 2300 | {"bpl", 0x54000005, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO}, | |
| 2301 | {"bvs", 0x54000006, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO}, | |
| 2302 | {"bvc", 0x54000007, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO}, | |
| 2303 | {"bhi", 0x54000008, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO}, | |
| 2304 | {"bls", 0x54000009, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO}, | |
| 2305 | {"bge", 0x5400000a, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO}, | |
| 2306 | {"blt", 0x5400000b, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO}, | |
| 2307 | {"bgt", 0x5400000c, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO}, | |
| 2308 | {"ble", 0x5400000d, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO}, | |
| 2309 | ||
| 2310 | {0, 0, 0, 0, 0, 0, {}, {}, 0}, | |
| 2311 | }; | |
| 2312 | ||
| 2313 | #ifdef AARCH64_OPERANDS | |
| 2314 | #undef AARCH64_OPERANDS | |
| 2315 | #endif | |
| 2316 | ||
| 2317 | /* Macro-based operand decription; this will be fed into aarch64-gen for it | |
| 2318 | to generate the structure aarch64_operands and the function | |
| 2319 | aarch64_insert_operand and aarch64_extract_operand. | |
| 2320 | ||
| 2321 | These inserters and extracters in the description execute the conversion | |
| 2322 | between the aarch64_opnd_info and value in the operand-related instruction | |
| 2323 | field(s). */ | |
| 2324 | ||
| 2325 | /* Y expects arguments (left to right) to be operand class, inserter/extractor | |
| 2326 | name suffix, operand name, flags, related bitfield(s) and description. | |
| 2327 | X only differs from Y by having the operand inserter and extractor names | |
| 2328 | listed separately. */ | |
| 2329 | ||
| 2330 | #define AARCH64_OPERANDS \ | |
| 2331 | Y(INT_REG, regno, "Rd", 0, F(FLD_Rd), "an integer register") \ | |
| 2332 | Y(INT_REG, regno, "Rn", 0, F(FLD_Rn), "an integer register") \ | |
| 2333 | Y(INT_REG, regno, "Rm", 0, F(FLD_Rm), "an integer register") \ | |
| 2334 | Y(INT_REG, regno, "Rt", 0, F(FLD_Rt), "an integer register") \ | |
| 2335 | Y(INT_REG, regno, "Rt2", 0, F(FLD_Rt2), "an integer register") \ | |
| 2336 | Y(INT_REG, regno, "Rs", 0, F(FLD_Rs), "an integer register") \ | |
| 2337 | Y(INT_REG, regno, "Ra", 0, F(FLD_Ra), "an integer register") \ | |
| 2338 | X(INT_REG, ins_regno, ext_regrt_sysins, "Rt_SYS", 0, F(FLD_Rt), \ | |
| 2339 | "an integer register") \ | |
| 2340 | Y(INT_REG, regno, "Rd_SP", OPD_F_MAYBE_SP, F(FLD_Rd), \ | |
| 2341 | "an integer or stack pointer register") \ | |
| 2342 | Y(INT_REG, regno, "Rn_SP", OPD_F_MAYBE_SP, F(FLD_Rn), \ | |
| 2343 | "an integer or stack pointer register") \ | |
| ee804238 JW |
2344 | X(INT_REG, 0, ext_regno_pair, "PAIRREG", 0, F(), \ |
| 2345 | "the second reg of a pair") \ | |
| a06ea964 NC |
2346 | Y(MODIFIED_REG, reg_extended, "Rm_EXT", 0, F(), \ |
| 2347 | "an integer register with optional extension") \ | |
| 2348 | Y(MODIFIED_REG, reg_shifted, "Rm_SFT", 0, F(), \ | |
| 2349 | "an integer register with optional shift") \ | |
| 2350 | Y(FP_REG, regno, "Fd", 0, F(FLD_Rd), "a floating-point register") \ | |
| 2351 | Y(FP_REG, regno, "Fn", 0, F(FLD_Rn), "a floating-point register") \ | |
| 2352 | Y(FP_REG, regno, "Fm", 0, F(FLD_Rm), "a floating-point register") \ | |
| 2353 | Y(FP_REG, regno, "Fa", 0, F(FLD_Ra), "a floating-point register") \ | |
| 2354 | Y(FP_REG, ft, "Ft", 0, F(FLD_Rt), "a floating-point register") \ | |
| 2355 | Y(FP_REG, regno, "Ft2", 0, F(FLD_Rt2), "a floating-point register") \ | |
| 2356 | Y(SISD_REG, regno, "Sd", 0, F(FLD_Rd), "a SIMD scalar register") \ | |
| 2357 | Y(SISD_REG, regno, "Sn", 0, F(FLD_Rn), "a SIMD scalar register") \ | |
| 2358 | Y(SISD_REG, regno, "Sm", 0, F(FLD_Rm), "a SIMD scalar register") \ | |
| 2359 | Y(SIMD_REG, regno, "Vd", 0, F(FLD_Rd), "a SIMD vector register") \ | |
| 2360 | Y(SIMD_REG, regno, "Vn", 0, F(FLD_Rn), "a SIMD vector register") \ | |
| 2361 | Y(SIMD_REG, regno, "Vm", 0, F(FLD_Rm), "a SIMD vector register") \ | |
| 2362 | Y(FP_REG, regno, "VdD1", 0, F(FLD_Rd), \ | |
| 2363 | "the top half of a 128-bit FP/SIMD register") \ | |
| 2364 | Y(FP_REG, regno, "VnD1", 0, F(FLD_Rn), \ | |
| 2365 | "the top half of a 128-bit FP/SIMD register") \ | |
| 2366 | Y(SIMD_ELEMENT, reglane, "Ed", 0, F(FLD_Rd), \ | |
| 2367 | "a SIMD vector element") \ | |
| 2368 | Y(SIMD_ELEMENT, reglane, "En", 0, F(FLD_Rn), \ | |
| 2369 | "a SIMD vector element") \ | |
| 2370 | Y(SIMD_ELEMENT, reglane, "Em", 0, F(FLD_Rm), \ | |
| 2371 | "a SIMD vector element") \ | |
| 2372 | Y(SIMD_REGLIST, reglist, "LVn", 0, F(FLD_Rn), \ | |
| 2373 | "a SIMD vector register list") \ | |
| 2374 | Y(SIMD_REGLIST, ldst_reglist, "LVt", 0, F(), \ | |
| 2375 | "a SIMD vector register list") \ | |
| 2376 | Y(SIMD_REGLIST, ldst_reglist_r, "LVt_AL", 0, F(), \ | |
| 2377 | "a SIMD vector register list") \ | |
| 2378 | Y(SIMD_REGLIST, ldst_elemlist, "LEt", 0, F(), \ | |
| 2379 | "a SIMD vector element list") \ | |
| 2380 | Y(CP_REG, regno, "Cn", 0, F(FLD_CRn), \ | |
| 2381 | "a 4-bit opcode field named for historical reasons C0 - C15") \ | |
| 2382 | Y(CP_REG, regno, "Cm", 0, F(FLD_CRm), \ | |
| 2383 | "a 4-bit opcode field named for historical reasons C0 - C15") \ | |
| 2384 | Y(IMMEDIATE, imm, "IDX", 0, F(FLD_imm4), \ | |
| 2385 | "an immediate as the index of the least significant byte") \ | |
| 2386 | Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSL", 0, F(), \ | |
| 2387 | "a left shift amount for an AdvSIMD register") \ | |
| 2388 | Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSR", 0, F(), \ | |
| 2389 | "a right shift amount for an AdvSIMD register") \ | |
| 2390 | Y(IMMEDIATE, advsimd_imm_modified, "SIMD_IMM", 0, F(), \ | |
| 2391 | "an immediate") \ | |
| 2392 | Y(IMMEDIATE, advsimd_imm_modified, "SIMD_IMM_SFT", 0, F(), \ | |
| 2393 | "an 8-bit unsigned immediate with optional shift") \ | |
| 2394 | Y(IMMEDIATE, advsimd_imm_modified, "SIMD_FPIMM", 0, F(), \ | |
| 2395 | "an 8-bit floating-point constant") \ | |
| 2396 | X(IMMEDIATE, 0, ext_shll_imm, "SHLL_IMM", 0, F(), \ | |
| 2397 | "an immediate shift amount of 8, 16 or 32") \ | |
| 2398 | X(IMMEDIATE, 0, 0, "IMM0", 0, F(), "0") \ | |
| 2399 | X(IMMEDIATE, 0, 0, "FPIMM0", 0, F(), "0.0") \ | |
| 2400 | Y(IMMEDIATE, imm, "FPIMM", 0, F(FLD_imm8), \ | |
| 2401 | "an 8-bit floating-point constant") \ | |
| 2402 | Y(IMMEDIATE, imm, "IMMR", 0, F(FLD_immr), \ | |
| 2403 | "the right rotate amount") \ | |
| 2404 | Y(IMMEDIATE, imm, "IMMS", 0, F(FLD_imm6), \ | |
| 2405 | "the leftmost bit number to be moved from the source") \ | |
| 2406 | Y(IMMEDIATE, imm, "WIDTH", 0, F(FLD_imm6), \ | |
| 2407 | "the width of the bit-field") \ | |
| 2408 | Y(IMMEDIATE, imm, "IMM", 0, F(FLD_imm6), "an immediate") \ | |
| 2409 | Y(IMMEDIATE, imm, "UIMM3_OP1", 0, F(FLD_op1), \ | |
| 2410 | "a 3-bit unsigned immediate") \ | |
| 2411 | Y(IMMEDIATE, imm, "UIMM3_OP2", 0, F(FLD_op2), \ | |
| 2412 | "a 3-bit unsigned immediate") \ | |
| 2413 | Y(IMMEDIATE, imm, "UIMM4", 0, F(FLD_CRm), \ | |
| 2414 | "a 4-bit unsigned immediate") \ | |
| 2415 | Y(IMMEDIATE, imm, "UIMM7", 0, F(FLD_CRm, FLD_op2), \ | |
| 2416 | "a 7-bit unsigned immediate") \ | |
| 2417 | Y(IMMEDIATE, imm, "BIT_NUM", 0, F(FLD_b5, FLD_b40), \ | |
| 2418 | "the bit number to be tested") \ | |
| 2419 | Y(IMMEDIATE, imm, "EXCEPTION", 0, F(FLD_imm16), \ | |
| 2420 | "a 16-bit unsigned immediate") \ | |
| 2421 | Y(IMMEDIATE, imm, "CCMP_IMM", 0, F(FLD_imm5), \ | |
| 2422 | "a 5-bit unsigned immediate") \ | |
| 2423 | Y(IMMEDIATE, imm, "NZCV", 0, F(FLD_nzcv), \ | |
| 2424 | "a flag bit specifier giving an alternative value for each flag") \ | |
| 2425 | Y(IMMEDIATE, limm, "LIMM", 0, F(FLD_N,FLD_immr,FLD_imms), \ | |
| 2426 | "Logical immediate") \ | |
| 2427 | Y(IMMEDIATE, aimm, "AIMM", 0, F(FLD_shift,FLD_imm12), \ | |
| 2428 | "a 12-bit unsigned immediate with optional left shift of 12 bits")\ | |
| 2429 | Y(IMMEDIATE, imm_half, "HALF", 0, F(FLD_imm16), \ | |
| 2430 | "a 16-bit immediate with optional left shift") \ | |
| 2431 | Y(IMMEDIATE, fbits, "FBITS", 0, F(FLD_scale), \ | |
| 2432 | "the number of bits after the binary point in the fixed-point value")\ | |
| 2433 | X(IMMEDIATE, 0, 0, "IMM_MOV", 0, F(), "an immediate") \ | |
| 68a64283 YZ |
2434 | Y(COND, cond, "COND", 0, F(), "a condition") \ |
| 2435 | Y(COND, cond, "COND1", 0, F(), \ | |
| 2436 | "one of the standard conditions, excluding AL and NV.") \ | |
| a06ea964 NC |
2437 | X(ADDRESS, 0, ext_imm, "ADDR_ADRP", OPD_F_SEXT, F(FLD_immhi, FLD_immlo),\ |
| 2438 | "21-bit PC-relative address of a 4KB page") \ | |
| 2439 | Y(ADDRESS, imm, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \ | |
| 2440 | F(FLD_imm14), "14-bit PC-relative address") \ | |
| 2441 | Y(ADDRESS, imm, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \ | |
| 2442 | F(FLD_imm19), "19-bit PC-relative address") \ | |
| 2443 | Y(ADDRESS, imm, "ADDR_PCREL21", OPD_F_SEXT, F(FLD_immhi,FLD_immlo), \ | |
| 2444 | "21-bit PC-relative address") \ | |
| 2445 | Y(ADDRESS, imm, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \ | |
| 2446 | F(FLD_imm26), "26-bit PC-relative address") \ | |
| 2447 | Y(ADDRESS, addr_simple, "ADDR_SIMPLE", 0, F(), \ | |
| 2448 | "an address with base register (no offset)") \ | |
| 2449 | Y(ADDRESS, addr_regoff, "ADDR_REGOFF", 0, F(), \ | |
| 2450 | "an address with register offset") \ | |
| 2451 | Y(ADDRESS, addr_simm, "ADDR_SIMM7", 0, F(FLD_imm7,FLD_index2), \ | |
| 2452 | "an address with 7-bit signed immediate offset") \ | |
| 2453 | Y(ADDRESS, addr_simm, "ADDR_SIMM9", 0, F(FLD_imm9,FLD_index), \ | |
| 2454 | "an address with 9-bit signed immediate offset") \ | |
| 2455 | Y(ADDRESS, addr_simm, "ADDR_SIMM9_2", 0, F(FLD_imm9,FLD_index), \ | |
| 2456 | "an address with 9-bit negative or unaligned immediate offset") \ | |
| 2457 | Y(ADDRESS, addr_uimm12, "ADDR_UIMM12", 0, F(FLD_Rn,FLD_imm12), \ | |
| 2458 | "an address with scaled, unsigned immediate offset") \ | |
| 2459 | Y(ADDRESS, addr_simple, "SIMD_ADDR_SIMPLE", 0, F(), \ | |
| 2460 | "an address with base register (no offset)") \ | |
| 2461 | Y(ADDRESS, simd_addr_post, "SIMD_ADDR_POST", 0, F(), \ | |
| 2462 | "a post-indexed address with immediate or register increment") \ | |
| 2463 | Y(SYSTEM, sysreg, "SYSREG", 0, F(), "a system register") \ | |
| 2464 | Y(SYSTEM, pstatefield, "PSTATEFIELD", 0, F(), \ | |
| 2465 | "a PSTATE field name") \ | |
| 2466 | Y(SYSTEM, sysins_op, "SYSREG_AT", 0, F(), \ | |
| 2467 | "an address translation operation specifier") \ | |
| 2468 | Y(SYSTEM, sysins_op, "SYSREG_DC", 0, F(), \ | |
| 2469 | "a data cache maintenance operation specifier") \ | |
| 2470 | Y(SYSTEM, sysins_op, "SYSREG_IC", 0, F(), \ | |
| 2471 | "an instructin cache maintenance operation specifier") \ | |
| 2472 | Y(SYSTEM, sysins_op, "SYSREG_TLBI", 0, F(), \ | |
| 2473 | "a TBL invalidation operation specifier") \ | |
| 2474 | Y(SYSTEM, barrier, "BARRIER", 0, F(), \ | |
| 2475 | "a barrier option name") \ | |
| 2476 | Y(SYSTEM, barrier, "BARRIER_ISB", 0, F(), \ | |
| 2477 | "the ISB option name SY or an optional 4-bit unsigned immediate") \ | |
| 2478 | Y(SYSTEM, prfop, "PRFOP", 0, F(), \ | |
| 2479 | "an prefetch operation specifier") |