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[deliverable/binutils-gdb.git] / opcodes / arc-opc.c
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252b5132 1/* Opcode table for the ARC.
6f2750fe 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
bcee8eb8 5
9b201bb5
NC		 6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
252b5132 9 it under the terms of the GNU General Public License as published by
9b201bb5 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132
RH		 17
18 You should have received a copy of the GNU General Public License
0d2bcfaf 19 along with this program; if not, write to the Free Software Foundation,
f4321104 20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
252b5132 21
5bd67f35 22#include "sysdep.h"
252b5132 23#include <stdio.h>
d943fe33 24#include "bfd.h"
252b5132 25#include "opcode/arc.h"
47b0e7ad 26#include "opintl.h"
886a2506 27#include "libiberty.h"
252b5132 28
e23e8ebe 29/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
ce440d63 30 instructions. All NPS400 features are built into all ARC target builds as
e23e8ebe
AB		 31 this reduces the chances that regressions might creep in. */
32
886a2506
NC		 33/* Insert RB register into a 32-bit opcode. */
34static unsigned
35insert_rb (unsigned insn,
36 int value,
37 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 38{
886a2506
NC		 39 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
40}
0d2bcfaf 41
886a2506
NC		 42static int
43extract_rb (unsigned insn ATTRIBUTE_UNUSED,
44 bfd_boolean * invalid ATTRIBUTE_UNUSED)
45{
46 int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
0d2bcfaf 47
886a2506
NC		 48 if (value == 0x3e && invalid)
49 *invalid = TRUE; /* A limm operand, it should be extracted in a
50 different way. */
252b5132 51
886a2506
NC		 52 return value;
53}
252b5132 54
886a2506
NC		 55static unsigned
56insert_rad (unsigned insn,
57 int value,
58 const char **errmsg ATTRIBUTE_UNUSED)
59{
60 if (value & 0x01)
61 *errmsg = _("Improper register value.");
0d2bcfaf 62
886a2506
NC		 63 return insn | (value & 0x3F);
64}
0d2bcfaf 65
886a2506
NC		 66static unsigned
67insert_rcd (unsigned insn,
68 int value,
69 const char **errmsg ATTRIBUTE_UNUSED)
70{
71 if (value & 0x01)
72 *errmsg = _("Improper register value.");
0d2bcfaf 73
886a2506
NC		 74 return insn | ((value & 0x3F) << 6);
75}
252b5132 76
886a2506 77/* Dummy insert ZERO operand function. */
252b5132 78
886a2506
NC		 79static unsigned
80insert_za (unsigned insn,
81 int value,
82 const char **errmsg)
83{
84 if (value)
85 *errmsg = _("operand is not zero");
86 return insn;
87}
252b5132 88
886a2506
NC		 89/* Insert Y-bit in bbit/br instructions. This function is called only
90 when solving fixups. */
252b5132 91
886a2506
NC		 92static unsigned
93insert_Ybit (unsigned insn,
94 int value,
95 const char **errmsg ATTRIBUTE_UNUSED)
96{
97 if (value > 0)
98 insn |= 0x08;
252b5132 99
886a2506
NC		 100 return insn;
101}
252b5132 102
886a2506
NC		 103/* Insert Y-bit in bbit/br instructions. This function is called only
104 when solving fixups. */
252b5132 105
886a2506
NC		 106static unsigned
107insert_NYbit (unsigned insn,
108 int value,
109 const char **errmsg ATTRIBUTE_UNUSED)
110{
111 if (value < 0)
112 insn |= 0x08;
0d2bcfaf 113
886a2506
NC		 114 return insn;
115}
252b5132 116
886a2506 117/* Insert H register into a 16-bit opcode. */
252b5132 118
886a2506
NC		 119static unsigned
120insert_rhv1 (unsigned insn,
121 int value,
122 const char **errmsg ATTRIBUTE_UNUSED)
123{
124 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
125}
252b5132 126
886a2506
NC		 127static int
128extract_rhv1 (unsigned insn ATTRIBUTE_UNUSED,
129 bfd_boolean * invalid ATTRIBUTE_UNUSED)
130{
02f3be19 131 int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7);
252b5132 132
886a2506
NC		 133 return value;
134}
252b5132 135
886a2506 136/* Insert H register into a 16-bit opcode. */
252b5132 137
886a2506
NC		 138static unsigned
139insert_rhv2 (unsigned insn,
140 int value,
141 const char **errmsg)
0d2bcfaf 142{
886a2506
NC		 143 if (value == 0x1E)
144 *errmsg =
145 _("Register R30 is a limm indicator for this type of instruction.");
146 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
147}
252b5132 148
886a2506
NC		 149static int
150extract_rhv2 (unsigned insn ATTRIBUTE_UNUSED,
151 bfd_boolean * invalid ATTRIBUTE_UNUSED)
152{
153 int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
0d2bcfaf 154
886a2506
NC		 155 return value;
156}
0d2bcfaf 157
886a2506
NC		 158static unsigned
159insert_r0 (unsigned insn,
160 int value,
161 const char **errmsg ATTRIBUTE_UNUSED)
162{
163 if (value != 0)
164 *errmsg = _("Register must be R0.");
47b0e7ad
NC		 165 return insn;
166}
252b5132 167
886a2506
NC		 168static int
169extract_r0 (unsigned insn ATTRIBUTE_UNUSED,
170 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 171{
886a2506 172 return 0;
47b0e7ad 173}
252b5132 174
252b5132 175
886a2506
NC		 176static unsigned
177insert_r1 (unsigned insn,
178 int value,
179 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 180{
886a2506
NC		 181 if (value != 1)
182 *errmsg = _("Register must be R1.");
47b0e7ad 183 return insn;
252b5132
RH		 184}
185
886a2506
NC		 186static int
187extract_r1 (unsigned insn ATTRIBUTE_UNUSED,
188 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 189{
886a2506 190 return 1;
252b5132
RH		 191}
192
886a2506
NC		 193static unsigned
194insert_r2 (unsigned insn,
195 int value,
196 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 197{
886a2506
NC		 198 if (value != 2)
199 *errmsg = _("Register must be R2.");
47b0e7ad 200 return insn;
252b5132
RH		 201}
202
886a2506
NC		 203static int
204extract_r2 (unsigned insn ATTRIBUTE_UNUSED,
205 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 206{
886a2506 207 return 2;
252b5132
RH		 208}
209
886a2506
NC		 210static unsigned
211insert_r3 (unsigned insn,
212 int value,
213 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 214{
886a2506
NC		 215 if (value != 3)
216 *errmsg = _("Register must be R3.");
47b0e7ad 217 return insn;
0d2bcfaf
NC		 218}
219
886a2506
NC		 220static int
221extract_r3 (unsigned insn ATTRIBUTE_UNUSED,
222 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 223{
886a2506 224 return 3;
0d2bcfaf
NC		 225}
226
886a2506
NC		 227static unsigned
228insert_sp (unsigned insn,
229 int value,
230 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 231{
886a2506
NC		 232 if (value != 28)
233 *errmsg = _("Register must be SP.");
252b5132
RH		 234 return insn;
235}
236
886a2506
NC		 237static int
238extract_sp (unsigned insn ATTRIBUTE_UNUSED,
239 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 240{
886a2506 241 return 28;
0d2bcfaf
NC		 242}
243
886a2506
NC		 244static unsigned
245insert_gp (unsigned insn,
246 int value,
247 const char **errmsg ATTRIBUTE_UNUSED)
0d2bcfaf 248{
886a2506
NC		 249 if (value != 26)
250 *errmsg = _("Register must be GP.");
251 return insn;
0d2bcfaf
NC		 252}
253
886a2506
NC		 254static int
255extract_gp (unsigned insn ATTRIBUTE_UNUSED,
256 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 257{
886a2506 258 return 26;
0d2bcfaf
NC		 259}
260
886a2506
NC		 261static unsigned
262insert_pcl (unsigned insn,
263 int value,
264 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 265{
886a2506
NC		 266 if (value != 63)
267 *errmsg = _("Register must be PCL.");
252b5132
RH		 268 return insn;
269}
270
886a2506
NC		 271static int
272extract_pcl (unsigned insn ATTRIBUTE_UNUSED,
273 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 274{
886a2506 275 return 63;
0d2bcfaf
NC		 276}
277
886a2506
NC		 278static unsigned
279insert_blink (unsigned insn,
280 int value,
281 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 282{
886a2506
NC		 283 if (value != 31)
284 *errmsg = _("Register must be BLINK.");
252b5132
RH		 285 return insn;
286}
287
886a2506
NC		 288static int
289extract_blink (unsigned insn ATTRIBUTE_UNUSED,
290 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 291{
886a2506 292 return 31;
0d2bcfaf
NC		 293}
294
886a2506
NC		 295static unsigned
296insert_ilink1 (unsigned insn,
297 int value,
298 const char **errmsg ATTRIBUTE_UNUSED)
0d2bcfaf 299{
886a2506
NC		 300 if (value != 29)
301 *errmsg = _("Register must be ILINK1.");
252b5132
RH		 302 return insn;
303}
304
886a2506
NC		 305static int
306extract_ilink1 (unsigned insn ATTRIBUTE_UNUSED,
307 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 308{
886a2506 309 return 29;
252b5132
RH		 310}
311
886a2506
NC		 312static unsigned
313insert_ilink2 (unsigned insn,
314 int value,
315 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 316{
886a2506
NC		 317 if (value != 30)
318 *errmsg = _("Register must be ILINK2.");
252b5132
RH		 319 return insn;
320}
321
886a2506
NC		 322static int
323extract_ilink2 (unsigned insn ATTRIBUTE_UNUSED,
324 bfd_boolean * invalid ATTRIBUTE_UNUSED)
325{
326 return 30;
327}
252b5132 328
886a2506
NC		 329static unsigned
330insert_ras (unsigned insn,
331 int value,
332 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 333{
886a2506 334 switch (value)
0d2bcfaf 335 {
886a2506
NC		 336 case 0:
337 case 1:
338 case 2:
339 case 3:
340 insn |= value;
341 break;
342 case 12:
343 case 13:
344 case 14:
345 case 15:
346 insn |= (value - 8);
347 break;
348 default:
349 *errmsg = _("Register must be either r0-r3 or r12-r15.");
350 break;
0d2bcfaf 351 }
252b5132
RH		 352 return insn;
353}
252b5132 354
886a2506
NC		 355static int
356extract_ras (unsigned insn ATTRIBUTE_UNUSED,
357 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 358{
886a2506
NC		 359 int value = insn & 0x07;
360 if (value > 3)
361 return (value + 8);
362 else
363 return value;
47b0e7ad
NC		 364}
365
886a2506
NC		 366static unsigned
367insert_rbs (unsigned insn,
368 int value,
369 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 370{
886a2506 371 switch (value)
47b0e7ad 372 {
886a2506
NC		 373 case 0:
374 case 1:
375 case 2:
376 case 3:
377 insn |= value << 8;
378 break;
379 case 12:
380 case 13:
381 case 14:
382 case 15:
383 insn |= ((value - 8)) << 8;
384 break;
385 default:
386 *errmsg = _("Register must be either r0-r3 or r12-r15.");
387 break;
47b0e7ad 388 }
886a2506 389 return insn;
252b5132
RH		 390}
391
886a2506
NC		 392static int
393extract_rbs (unsigned insn ATTRIBUTE_UNUSED,
394 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 395{
886a2506
NC		 396 int value = (insn >> 8) & 0x07;
397 if (value > 3)
398 return (value + 8);
399 else
400 return value;
401}
252b5132 402
886a2506
NC		 403static unsigned
404insert_rcs (unsigned insn,
405 int value,
406 const char **errmsg ATTRIBUTE_UNUSED)
407{
408 switch (value)
252b5132 409 {
886a2506
NC		 410 case 0:
411 case 1:
412 case 2:
413 case 3:
414 insn |= value << 5;
415 break;
416 case 12:
417 case 13:
418 case 14:
419 case 15:
420 insn |= ((value - 8)) << 5;
421 break;
422 default:
423 *errmsg = _("Register must be either r0-r3 or r12-r15.");
424 break;
252b5132 425 }
886a2506
NC		 426 return insn;
427}
47b0e7ad 428
886a2506
NC		 429static int
430extract_rcs (unsigned insn ATTRIBUTE_UNUSED,
431 bfd_boolean * invalid ATTRIBUTE_UNUSED)
432{
433 int value = (insn >> 5) & 0x07;
434 if (value > 3)
435 return (value + 8);
252b5132 436 else
886a2506
NC		 437 return value;
438}
47b0e7ad 439
886a2506
NC		 440static unsigned
441insert_simm3s (unsigned insn,
442 int value,
443 const char **errmsg ATTRIBUTE_UNUSED)
444{
445 int tmp = 0;
446 switch (value)
47b0e7ad 447 {
886a2506
NC		 448 case -1:
449 tmp = 0x07;
47b0e7ad 450 break;
886a2506
NC		 451 case 0:
452 tmp = 0x00;
453 break;
454 case 1:
455 tmp = 0x01;
47b0e7ad 456 break;
886a2506
NC		 457 case 2:
458 tmp = 0x02;
47b0e7ad 459 break;
886a2506
NC		 460 case 3:
461 tmp = 0x03;
462 break;
463 case 4:
464 tmp = 0x04;
465 break;
466 case 5:
467 tmp = 0x05;
468 break;
469 case 6:
470 tmp = 0x06;
471 break;
472 default:
473 *errmsg = _("Accepted values are from -1 to 6.");
47b0e7ad
NC		 474 break;
475 }
476
886a2506
NC		 477 insn |= tmp << 8;
478 return insn;
47b0e7ad
NC		 479}
480
886a2506
NC		 481static int
482extract_simm3s (unsigned insn ATTRIBUTE_UNUSED,
483 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 484{
886a2506
NC		 485 int value = (insn >> 8) & 0x07;
486 if (value == 7)
487 return -1;
47b0e7ad 488 else
886a2506 489 return value;
47b0e7ad
NC		 490}
491
886a2506
NC		 492static unsigned
493insert_rrange (unsigned insn,
494 int value,
495 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 496{
886a2506
NC		 497 int reg1 = (value >> 16) & 0xFFFF;
498 int reg2 = value & 0xFFFF;
499 if (reg1 != 13)
500 {
501 *errmsg = _("First register of the range should be r13.");
502 return insn;
503 }
504 if (reg2 < 13 || reg2 > 26)
505 {
506 *errmsg = _("Last register of the range doesn't fit.");
507 return insn;
508 }
509 insn |= ((reg2 - 12) & 0x0F) << 1;
510 return insn;
47b0e7ad
NC		 511}
512
886a2506
NC		 513static int
514extract_rrange (unsigned insn ATTRIBUTE_UNUSED,
515 bfd_boolean * invalid ATTRIBUTE_UNUSED)
516{
517 return (insn >> 1) & 0x0F;
518}
47b0e7ad 519
886a2506
NC		 520static unsigned
521insert_fpel (unsigned insn,
522 int value,
523 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 524{
886a2506
NC		 525 if (value != 27)
526 {
527 *errmsg = _("Invalid register number, should be fp.");
528 return insn;
529 }
47b0e7ad 530
886a2506
NC		 531 insn |= 0x0100;
532 return insn;
47b0e7ad
NC		 533}
534
886a2506
NC		 535static int
536extract_fpel (unsigned insn ATTRIBUTE_UNUSED,
537 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 538{
886a2506 539 return (insn & 0x0100) ? 27 : -1;
47b0e7ad
NC		 540}
541
886a2506
NC		 542static unsigned
543insert_blinkel (unsigned insn,
544 int value,
545 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 546{
886a2506 547 if (value != 31)
47b0e7ad 548 {
886a2506
NC		 549 *errmsg = _("Invalid register number, should be blink.");
550 return insn;
47b0e7ad 551 }
47b0e7ad 552
886a2506
NC		 553 insn |= 0x0200;
554 return insn;
47b0e7ad
NC		 555}
556
886a2506
NC		 557static int
558extract_blinkel (unsigned insn ATTRIBUTE_UNUSED,
559 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 560{
886a2506
NC		 561 return (insn & 0x0200) ? 31 : -1;
562}
47b0e7ad 563
886a2506
NC		 564static unsigned
565insert_pclel (unsigned insn,
566 int value,
567 const char **errmsg ATTRIBUTE_UNUSED)
568{
569 if (value != 63)
47b0e7ad 570 {
886a2506
NC		 571 *errmsg = _("Invalid register number, should be pcl.");
572 return insn;
47b0e7ad 573 }
47b0e7ad 574
886a2506
NC		 575 insn |= 0x0400;
576 return insn;
577}
47b0e7ad 578
886a2506
NC		 579static int
580extract_pclel (unsigned insn ATTRIBUTE_UNUSED,
581 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 582{
886a2506 583 return (insn & 0x0400) ? 63 : -1;
47b0e7ad 584}
47b0e7ad 585
886a2506
NC		 586#define INSERT_W6
587/* mask = 00000000000000000000111111000000
588 insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
589static unsigned
590insert_w6 (unsigned insn ATTRIBUTE_UNUSED,
591 int value ATTRIBUTE_UNUSED,
592 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 593{
886a2506 594 insn |= ((value >> 0) & 0x003f) << 6;
47b0e7ad 595
886a2506
NC		 596 return insn;
597}
47b0e7ad 598
886a2506
NC		 599#define EXTRACT_W6
600/* mask = 00000000000000000000111111000000. */
601static int
602extract_w6 (unsigned insn ATTRIBUTE_UNUSED,
603 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 604{
886a2506 605 unsigned value = 0;
47b0e7ad 606
886a2506 607 value |= ((insn >> 6) & 0x003f) << 0;
47b0e7ad 608
886a2506
NC		 609 return value;
610}
47b0e7ad 611
886a2506
NC		 612#define INSERT_G_S
613/* mask = 0000011100022000
614 insn = 01000ggghhhGG0HH. */
615static unsigned
616insert_g_s (unsigned insn ATTRIBUTE_UNUSED,
617 int value ATTRIBUTE_UNUSED,
618 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 619{
886a2506
NC		 620 insn |= ((value >> 0) & 0x0007) << 8;
621 insn |= ((value >> 3) & 0x0003) << 3;
252b5132 622
886a2506
NC		 623 return insn;
624}
252b5132 625
886a2506
NC		 626#define EXTRACT_G_S
627/* mask = 0000011100022000. */
628static int
629extract_g_s (unsigned insn ATTRIBUTE_UNUSED,
630 bfd_boolean * invalid ATTRIBUTE_UNUSED)
631{
632 int value = 0;
252b5132 633
886a2506
NC		 634 value |= ((insn >> 8) & 0x0007) << 0;
635 value |= ((insn >> 3) & 0x0003) << 3;
252b5132 636
886a2506
NC		 637 /* Extend the sign. */
638 int signbit = 1 << (6 - 1);
639 value = (value ^ signbit) - signbit;
252b5132 640
886a2506 641 return value;
252b5132
RH		 642}
643
e23e8ebe
AB		 644/* ARC NPS400 Support: See comment near head of file. */
645static unsigned
646insert_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
647 int value ATTRIBUTE_UNUSED,
648 const char **errmsg ATTRIBUTE_UNUSED)
649{
650 switch (value)
651 {
652 case 0:
653 case 1:
654 case 2:
655 case 3:
656 insn |= value << 24;
657 break;
658 case 12:
659 case 13:
660 case 14:
661 case 15:
662 insn |= (value - 8) << 24;
663 break;
664 default:
665 *errmsg = _("Register must be either r0-r3 or r12-r15.");
666 break;
667 }
668 return insn;
669}
670
671static int
672extract_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
673 bfd_boolean * invalid ATTRIBUTE_UNUSED)
674{
675 int value = (insn >> 24) & 0x07;
676 if (value > 3)
677 return (value + 8);
678 else
679 return value;
680}
681
4eb6f892
AB		 682static unsigned
683insert_nps_3bit_dst_short (unsigned insn ATTRIBUTE_UNUSED,
684 int value ATTRIBUTE_UNUSED,
685 const char **errmsg ATTRIBUTE_UNUSED)
686{
687 switch (value)
688 {
689 case 0:
690 case 1:
691 case 2:
692 case 3:
693 insn |= value << 8;
694 break;
695 case 12:
696 case 13:
697 case 14:
698 case 15:
699 insn |= (value - 8) << 8;
700 break;
701 default:
702 *errmsg = _("Register must be either r0-r3 or r12-r15.");
703 break;
704 }
705 return insn;
706}
707
708static int
709extract_nps_3bit_dst_short (unsigned insn ATTRIBUTE_UNUSED,
710 bfd_boolean * invalid ATTRIBUTE_UNUSED)
711{
712 int value = (insn >> 8) & 0x07;
713 if (value > 3)
714 return (value + 8);
715 else
716 return value;
717}
718
e23e8ebe
AB		 719static unsigned
720insert_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
721 int value ATTRIBUTE_UNUSED,
722 const char **errmsg ATTRIBUTE_UNUSED)
723{
724 switch (value)
725 {
726 case 0:
727 case 1:
728 case 2:
729 case 3:
730 insn |= value << 21;
731 break;
732 case 12:
733 case 13:
734 case 14:
735 case 15:
736 insn |= (value - 8) << 21;
737 break;
738 default:
739 *errmsg = _("Register must be either r0-r3 or r12-r15.");
740 break;
741 }
742 return insn;
743}
744
745static int
746extract_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
747 bfd_boolean * invalid ATTRIBUTE_UNUSED)
748{
749 int value = (insn >> 21) & 0x07;
750 if (value > 3)
751 return (value + 8);
752 else
753 return value;
754}
755
4eb6f892
AB		 756static unsigned
757insert_nps_3bit_src2_short (unsigned insn ATTRIBUTE_UNUSED,
758 int value ATTRIBUTE_UNUSED,
759 const char **errmsg ATTRIBUTE_UNUSED)
760{
761 switch (value)
762 {
763 case 0:
764 case 1:
765 case 2:
766 case 3:
767 insn |= value << 5;
768 break;
769 case 12:
770 case 13:
771 case 14:
772 case 15:
773 insn |= (value - 8) << 5;
774 break;
775 default:
776 *errmsg = _("Register must be either r0-r3 or r12-r15.");
777 break;
778 }
779 return insn;
780}
781
782static int
783extract_nps_3bit_src2_short (unsigned insn ATTRIBUTE_UNUSED,
784 bfd_boolean * invalid ATTRIBUTE_UNUSED)
785{
786 int value = (insn >> 5) & 0x07;
787 if (value > 3)
788 return (value + 8);
789 else
790 return value;
791}
792
820f03ff
AB		 793static unsigned
794insert_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED,
795 int value ATTRIBUTE_UNUSED,
796 const char **errmsg ATTRIBUTE_UNUSED)
797{
798 switch (value)
799 {
800 case 1:
801 value = 0;
802 break;
803 case 2:
804 value = 1;
805 break;
806 case 4:
807 value = 2;
808 break;
809 case 8:
810 value = 3;
811 break;
812 default:
813 value = 0;
814 *errmsg = _("Invalid size, should be 1, 2, 4, or 8.");
815 break;
816 }
817
818 insn |= value << 10;
819 return insn;
820}
821
822static int
823extract_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED,
824 bfd_boolean * invalid ATTRIBUTE_UNUSED)
825{
826 return 1 << ((insn >> 10) & 0x3);
827}
828
829static unsigned
830insert_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED,
831 int value ATTRIBUTE_UNUSED,
832 const char **errmsg ATTRIBUTE_UNUSED)
833{
834 insn |= ((value >> 5) & 7) << 12;
835 insn |= (value & 0x1f);
836 return insn;
837}
838
839static int
840extract_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED,
841 bfd_boolean * invalid ATTRIBUTE_UNUSED)
842{
843 return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
844}
845
846static unsigned
847insert_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED,
848 int value ATTRIBUTE_UNUSED,
849 const char **errmsg ATTRIBUTE_UNUSED)
850{
851 switch (value)
852 {
853 case 1:
854 case 2:
855 case 4:
856 break;
857
858 default:
859 *errmsg = _("invalid immediate, must be 1, 2, or 4");
860 value = 0;
861 }
862
863 insn |= (value << 6);
864 return insn;
865}
866
867static int
868extract_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED,
869 bfd_boolean * invalid ATTRIBUTE_UNUSED)
870{
871 return (insn >> 6) & 0x3f;
872}
873
874static unsigned
875insert_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED,
876 int value ATTRIBUTE_UNUSED,
877 const char **errmsg ATTRIBUTE_UNUSED)
878{
879 insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10));
880 return insn;
881}
882
883static int
884extract_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED,
885 bfd_boolean * invalid ATTRIBUTE_UNUSED)
886{
887 return (insn & 0x1f);
888}
889
4b0c052e
AB		 890static unsigned
891insert_nps_cmem_uimm16 (unsigned insn ATTRIBUTE_UNUSED,
892 int value ATTRIBUTE_UNUSED,
893 const char **errmsg ATTRIBUTE_UNUSED)
894{
895 int top = (value >> 16) & 0xffff;
896 if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE)
897 *errmsg = _("invalid value for CMEM ld/st immediate");
898 insn |= (value & 0xffff);
899 return insn;
900}
901
902static int
903extract_nps_cmem_uimm16 (unsigned insn ATTRIBUTE_UNUSED,
904 bfd_boolean * invalid ATTRIBUTE_UNUSED)
905{
906 return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff);
907}
908
537aefaf
AB		 909#define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \
910static unsigned \
911insert_nps_##NAME##_pos (unsigned insn ATTRIBUTE_UNUSED, \
912 int value ATTRIBUTE_UNUSED, \
913 const char **errmsg ATTRIBUTE_UNUSED) \
914{ \
915 switch (value) \
916 { \
917 case 0: \
918 case 8: \
919 case 16: \
920 case 24: \
921 value = value / 8; \
922 break; \
923 default: \
924 *errmsg = _("Invalid position, should be 0, 8, 16, or 24."); \
925 value = 0; \
926 } \
927 insn |= (value << SHIFT); \
928 return insn; \
929} \
930 \
931static int \
932extract_nps_##NAME##_pos (unsigned insn ATTRIBUTE_UNUSED, \
933 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
934{ \
935 return ((insn >> SHIFT) & 0x3) * 8; \
936}
937
938MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12)
939MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10)
940
9ba75c88 941#define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT)\
537aefaf 942static unsigned \
9ba75c88
GM		 943insert_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \
944 int value ATTRIBUTE_UNUSED, \
945 const char **errmsg ATTRIBUTE_UNUSED) \
537aefaf 946 { \
9ba75c88 947 if (value < LOWER || value > UPPER) \
537aefaf
AB		 948 { \
949 *errmsg = _("Invalid size, value must be " \
950 #LOWER " to " #UPPER "."); \
951 return insn; \
952 } \
953 value -= BIAS; \
954 insn |= (value << SHIFT); \
955 return insn; \
956 } \
957 \
958static int \
9ba75c88
GM		 959extract_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \
960 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
537aefaf
AB		 961{ \
962 return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \
963}
964
db18dbab
GM		 965MAKE_BIAS_INSERT_EXTRACT_FUNCS (addb_size,2,32,5,1,5)
966MAKE_BIAS_INSERT_EXTRACT_FUNCS (andb_size,1,32,5,1,5)
967MAKE_BIAS_INSERT_EXTRACT_FUNCS (fxorb_size,8,32,5,8,5)
968MAKE_BIAS_INSERT_EXTRACT_FUNCS (wxorb_size,16,32,5,16,5)
969MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop_size,1,32,5,1,10)
970MAKE_BIAS_INSERT_EXTRACT_FUNCS (qcmp_size,1,8,3,1,9)
971MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop1_size,1,32,5,1,20)
972MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop2_size,1,32,5,1,25)
973MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_width,1,32,5,1,6)
974MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_len,1,8,3,1,2)
975MAKE_BIAS_INSERT_EXTRACT_FUNCS (index3,4,7,2,4,0)
537aefaf
AB		 976
977static int
978extract_nps_qcmp_m3 (unsigned insn ATTRIBUTE_UNUSED,
979 bfd_boolean * invalid ATTRIBUTE_UNUSED)
980{
981 int m3 = (insn >> 5) & 0xf;
982 if (m3 == 0xf)
983 *invalid = TRUE;
984 return m3;
985}
986
987static int
988extract_nps_qcmp_m2 (unsigned insn ATTRIBUTE_UNUSED,
989 bfd_boolean * invalid ATTRIBUTE_UNUSED)
990{
991 bfd_boolean tmp_invalid = FALSE;
992 int m2 = (insn >> 15) & 0x1;
993 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
994
995 if (m2 == 0 && m3 == 0xf)
996 *invalid = TRUE;
997 return m2;
998}
999
1000static int
1001extract_nps_qcmp_m1 (unsigned insn ATTRIBUTE_UNUSED,
1002 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1003{
1004 bfd_boolean tmp_invalid = FALSE;
1005 int m1 = (insn >> 14) & 0x1;
1006 int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid);
1007 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
1008
1009 if (m1 == 0 && m2 == 0 && m3 == 0xf)
1010 *invalid = TRUE;
1011 return m1;
1012}
1013
1014static unsigned
1015insert_nps_calc_entry_size (unsigned insn ATTRIBUTE_UNUSED,
1016 int value ATTRIBUTE_UNUSED,
1017 const char **errmsg ATTRIBUTE_UNUSED)
1018{
1019 unsigned pwr;
1020
1021 if (value < 1 || value > 256)
1022 {
1023 *errmsg = _("value out of range 1 - 256");
1024 return 0;
1025 }
1026
1027 for (pwr = 0; (value & 1) == 0; value >>= 1)
1028 ++pwr;
1029
1030 if (value != 1)
1031 {
1032 *errmsg = _("value must be power of 2");
1033 return 0;
1034 }
1035
1036 return insn | (pwr << 8);
1037}
1038
1039static int
1040extract_nps_calc_entry_size (unsigned insn ATTRIBUTE_UNUSED,
1041 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1042{
1043 unsigned entry_size = (insn >> 8) & 0xf;
1044 return 1 << entry_size;
1045}
1046
4eb6f892
AB		 1047static unsigned
1048insert_nps_bitop_mod4_msb (unsigned insn ATTRIBUTE_UNUSED,
1049 int value ATTRIBUTE_UNUSED,
1050 const char **errmsg ATTRIBUTE_UNUSED)
1051{
1052 return insn | ((value & 0x2) << 30);
1053}
1054
1055static int
1056extract_nps_bitop_mod4_msb (unsigned insn ATTRIBUTE_UNUSED,
1057 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1058{
1059 return (insn >> 30) & 0x2;
1060}
1061
1062static unsigned
1063insert_nps_bitop_mod4_lsb (unsigned insn ATTRIBUTE_UNUSED,
1064 int value ATTRIBUTE_UNUSED,
1065 const char **errmsg ATTRIBUTE_UNUSED)
1066{
1067 return insn | ((value & 0x1) << 15);
1068}
1069
1070static int
1071extract_nps_bitop_mod4_lsb (unsigned insn ATTRIBUTE_UNUSED,
1072 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1073{
1074 return (insn >> 15) & 0x1;
1075}
1076
1077static unsigned
1078insert_nps_bitop_dst_pos3_pos4 (unsigned insn ATTRIBUTE_UNUSED,
1079 int value ATTRIBUTE_UNUSED,
1080 const char **errmsg ATTRIBUTE_UNUSED)
1081{
1082 return insn | (value << 10) | (value << 5);
1083}
1084
1085static int
1086extract_nps_bitop_dst_pos3_pos4 (unsigned insn ATTRIBUTE_UNUSED,
1087 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1088{
1089 if (((insn >> 10) & 0x1f) != ((insn >> 5) & 0x1f))
1090 *invalid = TRUE;
1091 return ((insn >> 5) & 0x1f);
1092}
1093
1094static unsigned
1095insert_nps_bitop_ins_ext (unsigned insn ATTRIBUTE_UNUSED,
1096 int value ATTRIBUTE_UNUSED,
1097 const char **errmsg ATTRIBUTE_UNUSED)
1098{
1099 if (value < 0 || value > 28)
1100 *errmsg = _("Value must be in the range 0 to 28");
1101 return insn | (value << 20);
1102}
1103
1104static int
1105extract_nps_bitop_ins_ext (unsigned insn ATTRIBUTE_UNUSED,
1106 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1107{
1108 int value = (insn >> 20) & 0x1f;
1109 if (value > 28)
1110 *invalid = TRUE;
1111 return value;
1112}
1113
14053c19
GM		 1114#define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \
1115static unsigned \
1116insert_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \
1117 int value ATTRIBUTE_UNUSED, \
1118 const char **errmsg ATTRIBUTE_UNUSED) \
1119{ \
1120 if (value < 1 || value > UPPER) \
1121 *errmsg = _("Value must be in the range 1 to " #UPPER); \
1122 if (value == UPPER) \
1123 value = 0; \
1124 return insn | (value << SHIFT); \
1125} \
1126 \
1127static int \
1128extract_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \
1129 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
1130{ \
1131 int value = (insn >> SHIFT) & ((1 << BITS) - 1); \
1132 if (value == 0) \
1133 value = UPPER; \
1134 return value; \
1135}
1136
db18dbab
GM		 1137MAKE_1BASED_INSERT_EXTRACT_FUNCS (field_size, 6, 8, 3)
1138MAKE_1BASED_INSERT_EXTRACT_FUNCS (shift_factor, 9, 8, 3)
1139MAKE_1BASED_INSERT_EXTRACT_FUNCS (bits_to_scramble, 12, 8, 3)
1140MAKE_1BASED_INSERT_EXTRACT_FUNCS (bdlen_max_len, 5, 256, 8)
1141MAKE_1BASED_INSERT_EXTRACT_FUNCS (bd_num_buff, 6, 8, 3)
1142MAKE_1BASED_INSERT_EXTRACT_FUNCS (pmu_num_job, 6, 4, 2)
14053c19
GM		 1143
1144static unsigned
1145insert_nps_min_hofs (unsigned insn ATTRIBUTE_UNUSED,
1146 int value ATTRIBUTE_UNUSED,
1147 const char **errmsg ATTRIBUTE_UNUSED)
1148{
1149 if (value < 0 || value > 240)
1150 *errmsg = _("Value must be in the range 0 to 240");
1151 if ((value % 16) != 0)
1152 *errmsg = _("Value must be a multiple of 16");
1153 value = value / 16;
1154 return insn | (value << 6);
1155}
1156
1157static int
1158extract_nps_min_hofs (unsigned insn ATTRIBUTE_UNUSED,
1159 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1160{
1161 int value = (insn >> 6) & 0xF;
1162 return value * 16;
1163}
1164
db18dbab
GM		 1165#define MAKE_INSERT_NPS_ADDRTYPE(NAME,VALUE) \
1166static unsigned \
1167insert_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \
1168 int value ATTRIBUTE_UNUSED, \
1169 const char **errmsg ATTRIBUTE_UNUSED) \
1170{ \
1171 if (value != ARC_NPS400_ADDRTYPE_##VALUE) \
1172 *errmsg = _("Invalid address type for operand"); \
1173 return insn; \
1174} \
1175 \
1176static int \
1177extract_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \
1178 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
1179{ \
1180 return ARC_NPS400_ADDRTYPE_##VALUE; \
1181}
1182
1183MAKE_INSERT_NPS_ADDRTYPE (bd, BD)
1184MAKE_INSERT_NPS_ADDRTYPE (jid, JID)
1185MAKE_INSERT_NPS_ADDRTYPE (lbd, LBD)
1186MAKE_INSERT_NPS_ADDRTYPE (mbd, MBD)
1187MAKE_INSERT_NPS_ADDRTYPE (sd, SD)
1188MAKE_INSERT_NPS_ADDRTYPE (sm, SM)
1189MAKE_INSERT_NPS_ADDRTYPE (xa, XA)
1190MAKE_INSERT_NPS_ADDRTYPE (xd, XD)
1191MAKE_INSERT_NPS_ADDRTYPE (cd, CD)
1192MAKE_INSERT_NPS_ADDRTYPE (cbd, CBD)
1193MAKE_INSERT_NPS_ADDRTYPE (cjid, CJID)
1194MAKE_INSERT_NPS_ADDRTYPE (clbd, CLBD)
1195MAKE_INSERT_NPS_ADDRTYPE (cm, CM)
1196MAKE_INSERT_NPS_ADDRTYPE (csd, CSD)
1197MAKE_INSERT_NPS_ADDRTYPE (cxa, CXA)
1198MAKE_INSERT_NPS_ADDRTYPE (cxd, CXD)
1199
1200
886a2506
NC		 1201/* Include the generic extract/insert functions. Order is important
1202 as some of the functions present in the .h may be disabled via
1203 defines. */
1204#include "arc-fxi.h"
252b5132 1205
886a2506 1206/* The flag operands table.
252b5132 1207
886a2506
NC		 1208 The format of the table is
1209 NAME CODE BITS SHIFT FAVAIL. */
1210const struct arc_flag_operand arc_flag_operands[] =
1211{
1212#define F_NULL 0
1213 { 0, 0, 0, 0, 0},
1214#define F_ALWAYS (F_NULL + 1)
1215 { "al", 0, 0, 0, 0 },
1216#define F_RA (F_ALWAYS + 1)
1217 { "ra", 0, 0, 0, 0 },
1218#define F_EQUAL (F_RA + 1)
1219 { "eq", 1, 5, 0, 1 },
1220#define F_ZERO (F_EQUAL + 1)
1221 { "z", 1, 5, 0, 0 },
1222#define F_NOTEQUAL (F_ZERO + 1)
1223 { "ne", 2, 5, 0, 1 },
1224#define F_NOTZERO (F_NOTEQUAL + 1)
1225 { "nz", 2, 5, 0, 0 },
1226#define F_POZITIVE (F_NOTZERO + 1)
1227 { "p", 3, 5, 0, 1 },
1228#define F_PL (F_POZITIVE + 1)
1229 { "pl", 3, 5, 0, 0 },
1230#define F_NEGATIVE (F_PL + 1)
1231 { "n", 4, 5, 0, 1 },
1232#define F_MINUS (F_NEGATIVE + 1)
1233 { "mi", 4, 5, 0, 0 },
1234#define F_CARRY (F_MINUS + 1)
1235 { "c", 5, 5, 0, 1 },
1236#define F_CARRYSET (F_CARRY + 1)
1237 { "cs", 5, 5, 0, 0 },
1238#define F_LOWER (F_CARRYSET + 1)
1239 { "lo", 5, 5, 0, 0 },
1240#define F_CARRYCLR (F_LOWER + 1)
1241 { "cc", 6, 5, 0, 0 },
1242#define F_NOTCARRY (F_CARRYCLR + 1)
1243 { "nc", 6, 5, 0, 1 },
1244#define F_HIGHER (F_NOTCARRY + 1)
1245 { "hs", 6, 5, 0, 0 },
1246#define F_OVERFLOWSET (F_HIGHER + 1)
1247 { "vs", 7, 5, 0, 0 },
1248#define F_OVERFLOW (F_OVERFLOWSET + 1)
1249 { "v", 7, 5, 0, 1 },
1250#define F_NOTOVERFLOW (F_OVERFLOW + 1)
1251 { "nv", 8, 5, 0, 1 },
1252#define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
1253 { "vc", 8, 5, 0, 0 },
1254#define F_GT (F_OVERFLOWCLR + 1)
1255 { "gt", 9, 5, 0, 1 },
1256#define F_GE (F_GT + 1)
1257 { "ge", 10, 5, 0, 1 },
1258#define F_LT (F_GE + 1)
1259 { "lt", 11, 5, 0, 1 },
1260#define F_LE (F_LT + 1)
1261 { "le", 12, 5, 0, 1 },
1262#define F_HI (F_LE + 1)
1263 { "hi", 13, 5, 0, 1 },
1264#define F_LS (F_HI + 1)
1265 { "ls", 14, 5, 0, 1 },
1266#define F_PNZ (F_LS + 1)
1267 { "pnz", 15, 5, 0, 1 },
1268
1269 /* FLAG. */
1270#define F_FLAG (F_PNZ + 1)
1271 { "f", 1, 1, 15, 1 },
1272#define F_FFAKE (F_FLAG + 1)
1273 { "f", 0, 0, 0, 1 },
1274
1275 /* Delay slot. */
1276#define F_ND (F_FFAKE + 1)
1277 { "nd", 0, 1, 5, 0 },
1278#define F_D (F_ND + 1)
1279 { "d", 1, 1, 5, 1 },
1280#define F_DFAKE (F_D + 1)
1281 { "d", 0, 0, 0, 1 },
1282
1283 /* Data size. */
1284#define F_SIZEB1 (F_DFAKE + 1)
1285 { "b", 1, 2, 1, 1 },
1286#define F_SIZEB7 (F_SIZEB1 + 1)
1287 { "b", 1, 2, 7, 1 },
1288#define F_SIZEB17 (F_SIZEB7 + 1)
1289 { "b", 1, 2, 17, 1 },
1290#define F_SIZEW1 (F_SIZEB17 + 1)
1291 { "w", 2, 2, 1, 0 },
1292#define F_SIZEW7 (F_SIZEW1 + 1)
1293 { "w", 2, 2, 7, 0 },
1294#define F_SIZEW17 (F_SIZEW7 + 1)
1295 { "w", 2, 2, 17, 0 },
1296
1297 /* Sign extension. */
1298#define F_SIGN6 (F_SIZEW17 + 1)
1299 { "x", 1, 1, 6, 1 },
1300#define F_SIGN16 (F_SIGN6 + 1)
1301 { "x", 1, 1, 16, 1 },
1302#define F_SIGNX (F_SIGN16 + 1)
1303 { "x", 0, 0, 0, 1 },
1304
1305 /* Address write-back modes. */
1306#define F_A3 (F_SIGNX + 1)
1307 { "a", 1, 2, 3, 0 },
1308#define F_A9 (F_A3 + 1)
1309 { "a", 1, 2, 9, 0 },
1310#define F_A22 (F_A9 + 1)
1311 { "a", 1, 2, 22, 0 },
1312#define F_AW3 (F_A22 + 1)
1313 { "aw", 1, 2, 3, 1 },
1314#define F_AW9 (F_AW3 + 1)
1315 { "aw", 1, 2, 9, 1 },
1316#define F_AW22 (F_AW9 + 1)
1317 { "aw", 1, 2, 22, 1 },
1318#define F_AB3 (F_AW22 + 1)
1319 { "ab", 2, 2, 3, 1 },
1320#define F_AB9 (F_AB3 + 1)
1321 { "ab", 2, 2, 9, 1 },
1322#define F_AB22 (F_AB9 + 1)
1323 { "ab", 2, 2, 22, 1 },
1324#define F_AS3 (F_AB22 + 1)
1325 { "as", 3, 2, 3, 1 },
1326#define F_AS9 (F_AS3 + 1)
1327 { "as", 3, 2, 9, 1 },
1328#define F_AS22 (F_AS9 + 1)
1329 { "as", 3, 2, 22, 1 },
1330#define F_ASFAKE (F_AS22 + 1)
1331 { "as", 0, 0, 0, 1 },
1332
1333 /* Cache bypass. */
1334#define F_DI5 (F_ASFAKE + 1)
1335 { "di", 1, 1, 5, 1 },
1336#define F_DI11 (F_DI5 + 1)
1337 { "di", 1, 1, 11, 1 },
1338#define F_DI15 (F_DI11 + 1)
1339 { "di", 1, 1, 15, 1 },
1340
1341 /* ARCv2 specific. */
1342#define F_NT (F_DI15 + 1)
1343 { "nt", 0, 1, 3, 1},
1344#define F_T (F_NT + 1)
1345 { "t", 1, 1, 3, 1},
1346#define F_H1 (F_T + 1)
1347 { "h", 2, 2, 1, 1 },
1348#define F_H7 (F_H1 + 1)
1349 { "h", 2, 2, 7, 1 },
1350#define F_H17 (F_H7 + 1)
1351 { "h", 2, 2, 17, 1 },
1352
1353 /* Fake Flags. */
1354#define F_NE (F_H17 + 1)
1355 { "ne", 0, 0, 0, 1 },
e23e8ebe
AB		 1356
1357 /* ARC NPS400 Support: See comment near head of file. */
1358#define F_NPS_CL (F_NE + 1)
1359 { "cl", 0, 0, 0, 1 },
1360
1361#define F_NPS_FLAG (F_NPS_CL + 1)
1362 { "f", 1, 1, 20, 1 },
820f03ff
AB		 1363
1364#define F_NPS_R (F_NPS_FLAG + 1)
1365 { "r", 1, 1, 15, 1 },
a42a4f84
AB		 1366
1367#define F_NPS_RW (F_NPS_R + 1)
1368 { "rw", 0, 1, 7, 1 },
1369
1370#define F_NPS_RD (F_NPS_RW + 1)
1371 { "rd", 1, 1, 7, 1 },
1372
1373#define F_NPS_WFT (F_NPS_RD + 1)
1374 { "wft", 0, 0, 0, 1 },
1375
1376#define F_NPS_IE1 (F_NPS_WFT + 1)
1377 { "ie1", 1, 2, 8, 1 },
1378
1379#define F_NPS_IE2 (F_NPS_IE1 + 1)
1380 { "ie2", 2, 2, 8, 1 },
1381
1382#define F_NPS_IE12 (F_NPS_IE2 + 1)
1383 { "ie12", 3, 2, 8, 1 },
1384
1385#define F_NPS_SYNC_RD (F_NPS_IE12 + 1)
1386 { "rd", 0, 1, 6, 1 },
1387
1388#define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1)
1389 { "wr", 1, 1, 6, 1 },
1390
1391#define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1)
1392 { "off", 0, 0, 0, 1 },
1393
1394#define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1)
1395 { "restore", 0, 0, 0, 1 },
1396
537aefaf
AB		 1397#define F_NPS_SX (F_NPS_HWS_RESTORE + 1)
1398 { "sx", 1, 1, 14, 1 },
1399
1400#define F_NPS_AR (F_NPS_SX + 1)
1401 { "ar", 0, 1, 0, 1 },
1402
1403#define F_NPS_AL (F_NPS_AR + 1)
1404 { "al", 1, 1, 0, 1 },
14053c19
GM		 1405
1406#define F_NPS_S (F_NPS_AL + 1)
1407 { "s", 0, 0, 0, 1 },
1408
1409#define F_NPS_ZNCV_RD (F_NPS_S + 1)
1410 { "rd", 0, 1, 15, 1 },
1411
1412#define F_NPS_ZNCV_WR (F_NPS_ZNCV_RD + 1)
1413 { "wr", 1, 1, 15, 1 },
9ba75c88
GM		 1414
1415#define F_NPS_P0 (F_NPS_ZNCV_WR + 1)
1416 { "p0", 0, 0, 0, 1 },
1417
1418#define F_NPS_P1 (F_NPS_P0 + 1)
1419 { "p1", 0, 0, 0, 1 },
1420
1421#define F_NPS_P2 (F_NPS_P1 + 1)
1422 { "p2", 0, 0, 0, 1 },
1423
1424#define F_NPS_P3 (F_NPS_P2 + 1)
1425 { "p3", 0, 0, 0, 1 },
28215275
GM		 1426
1427#define F_NPS_LDBIT_DI (F_NPS_P3 + 1)
1428 { "di", 0, 0, 0, 1 },
1429
1430#define F_NPS_LDBIT_CL1 (F_NPS_LDBIT_DI + 1)
1431 { "cl", 1, 1, 6, 1 },
1432
1433#define F_NPS_LDBIT_CL2 (F_NPS_LDBIT_CL1 + 1)
1434 { "cl", 1, 1, 16, 1 },
1435
1436#define F_NPS_LDBIT_X2_1 (F_NPS_LDBIT_CL2 + 1)
1437 { "x2", 1, 2, 9, 1 },
1438
1439#define F_NPS_LDBIT_X2_2 (F_NPS_LDBIT_X2_1 + 1)
1440 { "x2", 1, 2, 22, 1 },
1441
1442#define F_NPS_LDBIT_X4_1 (F_NPS_LDBIT_X2_2 + 1)
1443 { "x4", 2, 2, 9, 1 },
1444
1445#define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1)
1446 { "x4", 2, 2, 22, 1 },
886a2506 1447};
252b5132 1448
886a2506 1449const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
252b5132 1450
886a2506 1451/* Table of the flag classes.
252b5132 1452
886a2506
NC		 1453 The format of the table is
1454 CLASS {FLAG_CODE}. */
1455const struct arc_flag_class arc_flag_classes[] =
1456{
1457#define C_EMPTY 0
1ae8ab47 1458 { F_CLASS_NONE, { F_NULL } },
886a2506
NC		 1459
1460#define C_CC (C_EMPTY + 1)
d9eca1df 1461 { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND,
f36e33da
CZ		 1462 { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
1463 F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
1464 F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1465 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
1466 F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
1467 F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
886a2506
NC		 1468
1469#define C_AA_ADDR3 (C_CC + 1)
1470#define C_AA27 (C_CC + 1)
1ae8ab47 1471 { F_CLASS_OPTIONAL, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
886a2506
NC		 1472#define C_AA_ADDR9 (C_AA_ADDR3 + 1)
1473#define C_AA21 (C_AA_ADDR3 + 1)
1ae8ab47 1474 { F_CLASS_OPTIONAL, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
886a2506
NC		 1475#define C_AA_ADDR22 (C_AA_ADDR9 + 1)
1476#define C_AA8 (C_AA_ADDR9 + 1)
1ae8ab47 1477 { F_CLASS_OPTIONAL, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
886a2506
NC		 1478
1479#define C_F (C_AA_ADDR22 + 1)
1ae8ab47 1480 { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
886a2506 1481#define C_FHARD (C_F + 1)
1ae8ab47 1482 { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
886a2506
NC		 1483
1484#define C_T (C_FHARD + 1)
1ae8ab47 1485 { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
886a2506 1486#define C_D (C_T + 1)
1ae8ab47 1487 { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
886a2506
NC		 1488
1489#define C_DHARD (C_D + 1)
1ae8ab47 1490 { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
886a2506
NC		 1491
1492#define C_DI20 (C_DHARD + 1)
1ae8ab47 1493 { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
886a2506 1494#define C_DI16 (C_DI20 + 1)
1ae8ab47 1495 { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
886a2506 1496#define C_DI26 (C_DI16 + 1)
1ae8ab47 1497 { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
886a2506
NC		 1498
1499#define C_X25 (C_DI26 + 1)
1ae8ab47 1500 { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
886a2506 1501#define C_X15 (C_X25 + 1)
1ae8ab47 1502 { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
886a2506
NC		 1503#define C_XHARD (C_X15 + 1)
1504#define C_X (C_X15 + 1)
1ae8ab47 1505 { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
886a2506
NC		 1506
1507#define C_ZZ13 (C_X + 1)
1ae8ab47 1508 { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
886a2506 1509#define C_ZZ23 (C_ZZ13 + 1)
1ae8ab47 1510 { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
886a2506 1511#define C_ZZ29 (C_ZZ23 + 1)
1ae8ab47 1512 { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
886a2506
NC		 1513
1514#define C_AS (C_ZZ29 + 1)
1ae8ab47 1515 { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
886a2506
NC		 1516
1517#define C_NE (C_AS + 1)
1ae8ab47 1518 { F_CLASS_OPTIONAL, { F_NE, F_NULL}},
e23e8ebe
AB		 1519
1520 /* ARC NPS400 Support: See comment near head of file. */
1521#define C_NPS_CL (C_NE + 1)
1522 { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
1523
1524#define C_NPS_F (C_NPS_CL + 1)
1525 { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
820f03ff
AB		 1526
1527#define C_NPS_R (C_NPS_F + 1)
1528 { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}},
a42a4f84
AB		 1529
1530#define C_NPS_SCHD_RW (C_NPS_R + 1)
1531 { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}},
1532
1533#define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1)
1534 { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}},
1535
1536#define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1)
1537 { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}},
1538
1539#define C_NPS_SYNC (C_NPS_SCHD_IE + 1)
1540 { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}},
1541
1542#define C_NPS_HWS_OFF (C_NPS_SYNC + 1)
1543 { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}},
1544
1545#define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1)
1546 { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}},
1547
537aefaf
AB		 1548#define C_NPS_SX (C_NPS_HWS_RESTORE + 1)
1549 { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}},
1550
1551#define C_NPS_AR_AL (C_NPS_SX + 1)
1552 { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}},
14053c19
GM		 1553
1554#define C_NPS_S (C_NPS_AR_AL + 1)
1555 { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}},
1556
1557#define C_NPS_ZNCV (C_NPS_S + 1)
1558 { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}},
9ba75c88
GM		 1559
1560#define C_NPS_P0 (C_NPS_ZNCV + 1)
1561 { F_CLASS_REQUIRED, { F_NPS_P0, F_NULL }},
1562
1563#define C_NPS_P1 (C_NPS_P0 + 1)
1564 { F_CLASS_REQUIRED, { F_NPS_P1, F_NULL }},
1565
1566#define C_NPS_P2 (C_NPS_P1 + 1)
1567 { F_CLASS_REQUIRED, { F_NPS_P2, F_NULL }},
1568
1569#define C_NPS_P3 (C_NPS_P2 + 1)
1570 { F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }},
28215275
GM		 1571
1572#define C_NPS_LDBIT_DI (C_NPS_P3 + 1)
1573 { F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }},
1574
1575#define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1)
1576 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }},
1577
1578#define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1)
1579 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }},
1580
1581#define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1)
1582 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }},
1583
1584#define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1)
1585 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }},
886a2506 1586};
252b5132 1587
b99747ae
CZ		 1588const unsigned char flags_none[] = { 0 };
1589const unsigned char flags_f[] = { C_F };
1590const unsigned char flags_cc[] = { C_CC };
1591const unsigned char flags_ccf[] = { C_CC, C_F };
1592
886a2506 1593/* The operands table.
252b5132 1594
886a2506 1595 The format of the operands table is:
47b0e7ad 1596
886a2506
NC		 1597 BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
1598const struct arc_operand arc_operands[] =
0d2bcfaf 1599{
886a2506
NC		 1600 /* The fields are bits, shift, insert, extract, flags. The zero
1601 index is used to indicate end-of-list. */
1602#define UNUSED 0
1603 { 0, 0, 0, 0, 0, 0 },
4eb6f892
AB		 1604
1605#define IGNORED (UNUSED + 1)
1606 { 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0 },
1607
886a2506
NC		 1608 /* The plain integer register fields. Used by 32 bit
1609 instructions. */
4eb6f892 1610#define RA (IGNORED + 1)
886a2506
NC		 1611 { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
1612#define RB (RA + 1)
1613 { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
1614#define RC (RB + 1)
1615 { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
1616#define RBdup (RC + 1)
1617 { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
1618
1619#define RAD (RBdup + 1)
1620 { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
1621#define RCD (RAD + 1)
1622 { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
1623
1624 /* The plain integer register fields. Used by short
1625 instructions. */
1626#define RA16 (RCD + 1)
1627#define RA_S (RCD + 1)
1628 { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
1629#define RB16 (RA16 + 1)
1630#define RB_S (RA16 + 1)
1631 { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
1632#define RB16dup (RB16 + 1)
1633#define RB_Sdup (RB16 + 1)
1634 { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
1635#define RC16 (RB16dup + 1)
1636#define RC_S (RB16dup + 1)
1637 { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
1638#define R6H (RC16 + 1) /* 6bit register field 'h' used
1639 by V1 cpus. */
1640 { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
1641#define R5H (R6H + 1) /* 5bit register field 'h' used
1642 by V2 cpus. */
1643#define RH_S (R6H + 1) /* 5bit register field 'h' used
1644 by V2 cpus. */
1645 { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
1646#define R5Hdup (R5H + 1)
1647#define RH_Sdup (R5H + 1)
1648 { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
1649 insert_rhv2, extract_rhv2 },
1650
1651#define RG (R5Hdup + 1)
1652#define G_S (R5Hdup + 1)
1653 { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
1654
1655 /* Fix registers. */
1656#define R0 (RG + 1)
1657#define R0_S (RG + 1)
1658 { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
1659#define R1 (R0 + 1)
1660#define R1_S (R0 + 1)
1661 { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
1662#define R2 (R1 + 1)
1663#define R2_S (R1 + 1)
1664 { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
1665#define R3 (R2 + 1)
1666#define R3_S (R2 + 1)
1667 { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
8ddf6b2a 1668#define RSP (R3 + 1)
886a2506
NC		 1669#define SP_S (R3 + 1)
1670 { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
8ddf6b2a
CZ		 1671#define SPdup (RSP + 1)
1672#define SP_Sdup (RSP + 1)
886a2506
NC		 1673 { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
1674#define GP (SPdup + 1)
1675#define GP_S (SPdup + 1)
1676 { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
1677
1678#define PCL_S (GP + 1)
1679 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
1680
1681#define BLINK (PCL_S + 1)
1682#define BLINK_S (PCL_S + 1)
1683 { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
1684
1685#define ILINK1 (BLINK + 1)
1686 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
1687#define ILINK2 (ILINK1 + 1)
1688 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
1689
1690 /* Long immediate. */
1691#define LIMM (ILINK2 + 1)
1692#define LIMM_S (ILINK2 + 1)
1693 { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
1694#define LIMMdup (LIMM + 1)
1695 { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
1696
1697 /* Special operands. */
1698#define ZA (LIMMdup + 1)
1699#define ZB (LIMMdup + 1)
1700#define ZA_S (LIMMdup + 1)
1701#define ZB_S (LIMMdup + 1)
1702#define ZC_S (LIMMdup + 1)
1703 { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
1704
1705#define RRANGE_EL (ZA + 1)
1706 { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
1707 insert_rrange, extract_rrange},
1708#define FP_EL (RRANGE_EL + 1)
1709 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1710 insert_fpel, extract_fpel },
1711#define BLINK_EL (FP_EL + 1)
1712 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1713 insert_blinkel, extract_blinkel },
1714#define PCL_EL (BLINK_EL + 1)
1715 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1716 insert_pclel, extract_pclel },
1717
1718 /* Fake operand to handle the T flag. */
1719#define BRAKET (PCL_EL + 1)
1720#define BRAKETdup (PCL_EL + 1)
1721 { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
1722
1723 /* Fake operand to handle the T flag. */
1724#define FKT_T (BRAKET + 1)
1725 { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
1726 /* Fake operand to handle the T flag. */
1727#define FKT_NT (FKT_T + 1)
1728 { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
1729
1730 /* UIMM6_20 mask = 00000000000000000000111111000000. */
1731#define UIMM6_20 (FKT_NT + 1)
1732 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
1733
1734 /* SIMM12_20 mask = 00000000000000000000111111222222. */
1735#define SIMM12_20 (UIMM6_20 + 1)
1736 {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
1737
1738 /* SIMM3_5_S mask = 0000011100000000. */
1739#define SIMM3_5_S (SIMM12_20 + 1)
1740 {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
1741 insert_simm3s, extract_simm3s},
1742
1743 /* UIMM7_A32_11_S mask = 0000000000011111. */
1744#define UIMM7_A32_11_S (SIMM3_5_S + 1)
1745 {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1746 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
1747 extract_uimm7_a32_11_s},
1748
1749 /* UIMM7_9_S mask = 0000000001111111. */
1750#define UIMM7_9_S (UIMM7_A32_11_S + 1)
1751 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
1752
1753 /* UIMM3_13_S mask = 0000000000000111. */
1754#define UIMM3_13_S (UIMM7_9_S + 1)
1755 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
1756
1757 /* SIMM11_A32_7_S mask = 0000000111111111. */
1758#define SIMM11_A32_7_S (UIMM3_13_S + 1)
1759 {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1760 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
1761
1762 /* UIMM6_13_S mask = 0000000002220111. */
1763#define UIMM6_13_S (SIMM11_A32_7_S + 1)
1764 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
1765 /* UIMM5_11_S mask = 0000000000011111. */
1766#define UIMM5_11_S (UIMM6_13_S + 1)
1767 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
1768 extract_uimm5_11_s},
1769
1770 /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
1771#define SIMM9_A16_8 (UIMM5_11_S + 1)
1772 {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1773 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
1774 extract_simm9_a16_8},
1775
1776 /* UIMM6_8 mask = 00000000000000000000111111000000. */
1777#define UIMM6_8 (SIMM9_A16_8 + 1)
1778 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
1779
1780 /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
1781#define SIMM21_A16_5 (UIMM6_8 + 1)
1782 {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
1783 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE,
1784 insert_simm21_a16_5, extract_simm21_a16_5},
1785
1786 /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
1787#define SIMM25_A16_5 (SIMM21_A16_5 + 1)
1788 {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
1789 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
1790 insert_simm25_a16_5, extract_simm25_a16_5},
1791
1792 /* SIMM10_A16_7_S mask = 0000000111111111. */
1793#define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
1794 {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1795 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
1796 extract_simm10_a16_7_s},
1797
1798#define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1)
1799 {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1800 | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
1801
1802 /* SIMM7_A16_10_S mask = 0000000000111111. */
1803#define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
1804 {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1805 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
1806 extract_simm7_a16_10_s},
1807
1808 /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
1809#define SIMM21_A32_5 (SIMM7_A16_10_S + 1)
1810 {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1811 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
1812 extract_simm21_a32_5},
1813
1814 /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
1815#define SIMM25_A32_5 (SIMM21_A32_5 + 1)
1816 {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1817 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
1818 extract_simm25_a32_5},
1819
1820 /* SIMM13_A32_5_S mask = 0000011111111111. */
1821#define SIMM13_A32_5_S (SIMM25_A32_5 + 1)
1822 {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1823 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
1824 extract_simm13_a32_5_s},
1825
1826 /* SIMM8_A16_9_S mask = 0000000001111111. */
1827#define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
1828 {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1829 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
1830 extract_simm8_a16_9_s},
1831
1832 /* UIMM3_23 mask = 00000000000000000000000111000000. */
1833#define UIMM3_23 (SIMM8_A16_9_S + 1)
1834 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
1835
1836 /* UIMM10_6_S mask = 0000001111111111. */
1837#define UIMM10_6_S (UIMM3_23 + 1)
1838 {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
1839
1840 /* UIMM6_11_S mask = 0000002200011110. */
1841#define UIMM6_11_S (UIMM10_6_S + 1)
1842 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
1843
1844 /* SIMM9_8 mask = 00000000111111112000000000000000. */
1845#define SIMM9_8 (UIMM6_11_S + 1)
1846 {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
1847 insert_simm9_8, extract_simm9_8},
1848
1849 /* UIMM10_A32_8_S mask = 0000000011111111. */
1850#define UIMM10_A32_8_S (SIMM9_8 + 1)
1851 {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1852 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
1853 extract_uimm10_a32_8_s},
1854
1855 /* SIMM9_7_S mask = 0000000111111111. */
1856#define SIMM9_7_S (UIMM10_A32_8_S + 1)
1857 {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
1858 extract_simm9_7_s},
1859
1860 /* UIMM6_A16_11_S mask = 0000000000011111. */
1861#define UIMM6_A16_11_S (SIMM9_7_S + 1)
1862 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1863 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
1864 extract_uimm6_a16_11_s},
1865
1866 /* UIMM5_A32_11_S mask = 0000020000011000. */
1867#define UIMM5_A32_11_S (UIMM6_A16_11_S + 1)
1868 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1869 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
1870 extract_uimm5_a32_11_s},
1871
1872 /* SIMM11_A32_13_S mask = 0000022222200111. */
1873#define SIMM11_A32_13_S (UIMM5_A32_11_S + 1)
1874 {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1875 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
1876
1877 /* UIMM7_13_S mask = 0000000022220111. */
1878#define UIMM7_13_S (SIMM11_A32_13_S + 1)
1879 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
1880
1881 /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
1882#define UIMM6_A16_21 (UIMM7_13_S + 1)
1883 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1884 | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
1885
1886 /* UIMM7_11_S mask = 0000022200011110. */
1887#define UIMM7_11_S (UIMM6_A16_21 + 1)
1888 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
1889
1890 /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
1891#define UIMM7_A16_20 (UIMM7_11_S + 1)
1892 {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1893 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
1894 extract_uimm7_a16_20},
1895
1896 /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
1897#define SIMM13_A16_20 (UIMM7_A16_20 + 1)
1898 {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1899 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
1900 extract_simm13_a16_20},
1901
1902 /* UIMM8_8_S mask = 0000000011111111. */
1903#define UIMM8_8_S (SIMM13_A16_20 + 1)
1904 {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
1905
1906 /* W6 mask = 00000000000000000000111111000000. */
1907#define W6 (UIMM8_8_S + 1)
1908 {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
1909
1910 /* UIMM6_5_S mask = 0000011111100000. */
1911#define UIMM6_5_S (W6 + 1)
1912 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
e23e8ebe
AB		 1913
1914 /* ARC NPS400 Support: See comment near head of file. */
1915#define NPS_R_DST_3B (UIMM6_5_S + 1)
1916 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
1917
1918#define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
1919 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
1920
1921#define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
1922 { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_src2, extract_nps_3bit_src2 },
1923
1924#define NPS_R_DST (NPS_R_SRC2_3B + 1)
2cce10e7 1925 { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL },
e23e8ebe
AB		 1926
1927#define NPS_R_SRC1 (NPS_R_DST + 1)
2cce10e7 1928 { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
e23e8ebe
AB		 1929
1930#define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1)
1931 { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1932
1933#define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
1934 { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1935
1936#define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
820f03ff 1937 { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size, extract_nps_bitop_size },
e23e8ebe 1938
820f03ff
AB		 1939#define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1)
1940 { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size },
1941
1942#define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1)
1943 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size_2b, extract_nps_bitop_size_2b },
1944
1945#define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1)
1946 { 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 },
1947
1948#define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1)
e23e8ebe 1949 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
820f03ff 1950
14053c19
GM		 1951#define NPS_SIMM16 (NPS_UIMM16 + 1)
1952 { 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL },
1953
1954#define NPS_RFLT_UIMM6 (NPS_SIMM16 + 1)
820f03ff 1955 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
4b0c052e
AB		 1956
1957#define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1)
1958 { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 },
537aefaf
AB		 1959
1960#define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1)
1961 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src2_pos, extract_nps_src2_pos },
1962
1963#define NPS_SRC1_POS (NPS_SRC2_POS + 1)
1964 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src1_pos, extract_nps_src1_pos },
1965
1966#define NPS_ADDB_SIZE (NPS_SRC1_POS + 1)
1967 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_addb_size, extract_nps_addb_size },
1968
1969#define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1)
1970 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_andb_size, extract_nps_andb_size },
1971
1972#define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1)
1973 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_fxorb_size, extract_nps_fxorb_size },
1974
1975#define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1)
1976 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_wxorb_size, extract_nps_wxorb_size },
1977
1978#define NPS_R_XLDST (NPS_WXORB_SIZE + 1)
1979 { 6, 5, 0, ARC_OPERAND_IR, NULL, NULL },
1980
1981#define NPS_DIV_UIMM4 (NPS_R_XLDST + 1)
1982 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1983
1984#define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1)
1985 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_qcmp_size, extract_nps_qcmp_size },
1986
1987#define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1)
1988 { 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1 },
1989
1990#define NPS_QCMP_M2 (NPS_QCMP_M1 + 1)
1991 { 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2 },
1992
1993#define NPS_QCMP_M3 (NPS_QCMP_M2 + 1)
1994 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3 },
1995
1996#define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1)
1997 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_calc_entry_size, extract_nps_calc_entry_size },
4eb6f892
AB		 1998
1999#define NPS_R_DST_3B_SHORT (NPS_CALC_ENTRY_SIZE + 1)
2000 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst_short, extract_nps_3bit_dst_short },
2001
2002#define NPS_R_SRC1_3B_SHORT (NPS_R_DST_3B_SHORT + 1)
2003 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_dst_short, extract_nps_3bit_dst_short },
2004
2005#define NPS_R_SRC2_3B_SHORT (NPS_R_SRC1_3B_SHORT + 1)
2006 { 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_src2_short, extract_nps_3bit_src2_short },
2007
2008#define NPS_BITOP_SIZE2 (NPS_R_SRC2_3B_SHORT + 1)
2009 { 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop2_size, extract_nps_bitop2_size },
2010
2011#define NPS_BITOP_SIZE1 (NPS_BITOP_SIZE2 + 1)
2012 { 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop1_size, extract_nps_bitop1_size },
2013
2014#define NPS_BITOP_DST_POS3_POS4 (NPS_BITOP_SIZE1 + 1)
2015 { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4 },
2016
2017#define NPS_BITOP_DST_POS4 (NPS_BITOP_DST_POS3_POS4 + 1)
2018 { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2019
2020#define NPS_BITOP_DST_POS3 (NPS_BITOP_DST_POS4 + 1)
2021 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2022
2023#define NPS_BITOP_DST_POS2 (NPS_BITOP_DST_POS3 + 1)
2024 { 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2025
2026#define NPS_BITOP_DST_POS1 (NPS_BITOP_DST_POS2 + 1)
2027 { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2028
2029#define NPS_BITOP_SRC_POS4 (NPS_BITOP_DST_POS1 + 1)
2030 { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2031
2032#define NPS_BITOP_SRC_POS3 (NPS_BITOP_SRC_POS4 + 1)
2033 { 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2034
2035#define NPS_BITOP_SRC_POS2 (NPS_BITOP_SRC_POS3 + 1)
2036 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2037
2038#define NPS_BITOP_SRC_POS1 (NPS_BITOP_SRC_POS2 + 1)
2039 { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2040
2041#define NPS_BITOP_MOD4_MSB (NPS_BITOP_SRC_POS1 + 1)
2042 { 2, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_mod4_msb, extract_nps_bitop_mod4_msb },
2043
2044#define NPS_BITOP_MOD4_LSB (NPS_BITOP_MOD4_MSB + 1)
2045 { 2, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_mod4_lsb, extract_nps_bitop_mod4_lsb },
2046
2047#define NPS_BITOP_MOD3 (NPS_BITOP_MOD4_LSB + 1)
2048 { 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2049
2050#define NPS_BITOP_MOD2 (NPS_BITOP_MOD3 + 1)
2051 { 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2052
2053#define NPS_BITOP_MOD1 (NPS_BITOP_MOD2 + 1)
2054 { 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2055
2056#define NPS_BITOP_INS_EXT (NPS_BITOP_MOD1 + 1)
2057 { 5, 20, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext },
14053c19
GM		 2058
2059#define NPS_FIELD_START_POS (NPS_BITOP_INS_EXT + 1)
2060 { 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2061
2062#define NPS_FIELD_SIZE (NPS_FIELD_START_POS + 1)
2063 { 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_field_size, extract_nps_field_size },
2064
2065#define NPS_SHIFT_FACTOR (NPS_FIELD_SIZE + 1)
2066 { 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_shift_factor, extract_nps_shift_factor },
2067
2068#define NPS_BITS_TO_SCRAMBLE (NPS_SHIFT_FACTOR + 1)
2069 { 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bits_to_scramble, extract_nps_bits_to_scramble },
2070
2071#define NPS_SRC2_POS_5B (NPS_BITS_TO_SCRAMBLE + 1)
2072 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2073
2074#define NPS_BDLEN_MAX_LEN (NPS_SRC2_POS_5B + 1)
2075 { 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bdlen_max_len, extract_nps_bdlen_max_len },
2076
2077#define NPS_MIN_HOFS (NPS_BDLEN_MAX_LEN + 1)
2078 { 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_min_hofs, extract_nps_min_hofs },
2079
2080#define NPS_PSBC (NPS_MIN_HOFS + 1)
2081 { 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
9ba75c88
GM		 2082
2083#define NPS_DPI_DST (NPS_PSBC + 1)
2084 { 5, 11, 0, ARC_OPERAND_IR, NULL, NULL },
2085
2086 /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B but doesn't duplicate an operand */
2087#define NPS_DPI_SRC1_3B (NPS_DPI_DST + 1)
2088 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
2089
2090#define NPS_HASH_WIDTH (NPS_DPI_SRC1_3B + 1)
2091 { 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_width, extract_nps_hash_width },
2092
2093#define NPS_HASH_PERM (NPS_HASH_WIDTH + 1)
2094 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2095
2096#define NPS_HASH_NONLINEAR (NPS_HASH_PERM + 1)
2097 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2098
2099#define NPS_HASH_BASEMAT (NPS_HASH_NONLINEAR + 1)
2100 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2101
2102#define NPS_HASH_LEN (NPS_HASH_BASEMAT + 1)
2103 { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_len, extract_nps_hash_len },
2104
2105#define NPS_HASH_OFS (NPS_HASH_LEN + 1)
2106 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2107
2108#define NPS_HASH_BASEMAT2 (NPS_HASH_OFS + 1)
2109 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2110
2111#define NPS_E4BY_INDEX0 (NPS_HASH_BASEMAT2 + 1)
2112 { 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2113
2114#define NPS_E4BY_INDEX1 (NPS_E4BY_INDEX0 + 1)
2115 { 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2116
2117#define NPS_E4BY_INDEX2 (NPS_E4BY_INDEX1 + 1)
2118 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2119
2120#define NPS_E4BY_INDEX3 (NPS_E4BY_INDEX2 + 1)
2121 { 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_index3, extract_nps_index3 },
db18dbab
GM		 2122
2123#define COLON (NPS_E4BY_INDEX3 + 1)
2124 { 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL },
2125
2126#define NPS_BD (COLON + 1)
2127 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_bd, extract_nps_bd },
2128
2129#define NPS_JID (NPS_BD + 1)
2130 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_jid, extract_nps_jid },
2131
2132#define NPS_LBD (NPS_JID + 1)
2133 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_lbd, extract_nps_lbd },
2134
2135#define NPS_MBD (NPS_LBD + 1)
2136 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_mbd, extract_nps_mbd },
2137
2138#define NPS_SD (NPS_MBD + 1)
2139 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sd, extract_nps_sd },
2140
2141#define NPS_SM (NPS_SD + 1)
2142 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sm, extract_nps_sm },
2143
2144#define NPS_XA (NPS_SM + 1)
2145 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xa, extract_nps_xa },
2146
2147#define NPS_XD (NPS_XA + 1)
2148 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xd, extract_nps_xd },
2149
2150#define NPS_CD (NPS_XD + 1)
2151 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cd, extract_nps_cd },
2152
2153#define NPS_CBD (NPS_CD + 1)
2154 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cbd, extract_nps_cbd },
2155
2156#define NPS_CJID (NPS_CBD + 1)
2157 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cjid, extract_nps_cjid },
2158
2159#define NPS_CLBD (NPS_CJID + 1)
2160 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_clbd, extract_nps_clbd },
2161
2162#define NPS_CM (NPS_CLBD + 1)
2163 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cm, extract_nps_cm },
2164
2165#define NPS_CSD (NPS_CM + 1)
2166 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_csd, extract_nps_csd },
2167
2168#define NPS_CXA (NPS_CSD + 1)
2169 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxa, extract_nps_cxa },
2170
2171#define NPS_CXD (NPS_CXA + 1)
2172 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxd, extract_nps_cxd },
2173
2174#define NPS_BD_TYPE (NPS_CXD + 1)
2175 { 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2176
2177#define NPS_BMU_NUM (NPS_BD_TYPE + 1)
2178 { 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bd_num_buff, extract_nps_bd_num_buff },
2179
2180#define NPS_PMU_NXT_DST (NPS_BMU_NUM + 1)
2181 { 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2182
2183#define NPS_PMU_NUM_JOB (NPS_PMU_NXT_DST + 1)
2184 { 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_pmu_num_job, extract_nps_pmu_num_job },
886a2506 2185};
0d2bcfaf 2186
886a2506 2187const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
0d2bcfaf 2188
886a2506
NC		 2189const unsigned arc_Toperand = FKT_T;
2190const unsigned arc_NToperand = FKT_NT;
47b0e7ad 2191
b99747ae
CZ		 2192const unsigned char arg_none[] = { 0 };
2193const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC };
2194const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC };
2195const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC };
2196const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 };
2197const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 };
2198const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 };
2199const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 };
2200const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC };
2201const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM };
2202const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC };
2203const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM };
2204
2205const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM };
2206const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 };
2207const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 };
2208
2209const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 };
2210const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup };
2211const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup };
2212
2213const unsigned char arg_32bit_rbrc[] = { RB, RC };
2214const unsigned char arg_32bit_zarc[] = { ZA, RC };
2215const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 };
2216const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 };
2217const unsigned char arg_32bit_rblimm[] = { RB, LIMM };
2218const unsigned char arg_32bit_zalimm[] = { ZA, LIMM };
2219
2220const unsigned char arg_32bit_limmrc[] = { LIMM, RC };
2221const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 };
2222const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 };
2223const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup };
2224
945e0f82
CZ		 2225const unsigned char arg_32bit_rc[] = { RC };
2226const unsigned char arg_32bit_u6[] = { UIMM6_20 };
2227const unsigned char arg_32bit_limm[] = { LIMM };
2228
886a2506 2229/* The opcode table.
0d2bcfaf 2230
886a2506 2231 The format of the opcode table is:
0d2bcfaf 2232
1328504b
AB		 2233 NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }.
2234
2235 The table is organised such that, where possible, all instructions with
2236 the same mnemonic are together in a block. When the assembler searches
2237 for a suitable instruction the entries are checked in table order, so
2238 more specific, or specialised cases should appear earlier in the table.
2239
2240 As an example, consider two instructions 'add a,b,u6' and 'add
2241 a,b,limm'. The first takes a 6-bit immediate that is encoded within the
2242 32-bit instruction, while the second takes a 32-bit immediate that is
2243 encoded in a follow-on 32-bit, making the total instruction length
2244 64-bits. In this case the u6 variant must appear first in the table, as
2245 all u6 immediates could also be encoded using the 'limm' extension,
2246 however, we want to use the shorter instruction wherever possible.
2247
2248 It is possible though to split instructions with the same mnemonic into
2249 multiple groups. However, the instructions are still checked in table
2250 order, even across groups. The only time that instructions with the
2251 same mnemonic should be split into different groups is when different
2252 variants of the instruction appear in different architectures, in which
2253 case, grouping all instructions from a particular architecture together
2254 might be preferable to merging the instruction into the main instruction
2255 table.
2256
2257 An example of this split instruction groups can be found with the 'sync'
2258 instruction. The core arc architecture provides a 'sync' instruction,
2259 while the nps instruction set extension provides 'sync.rd' and
2260 'sync.wr'. The rd/wr flags are instruction flags, not part of the
2261 mnemonic, so we end up with two groups for the sync instruction, the
2262 first within the core arc instruction table, and the second within the
2263 nps extension instructions. */
886a2506 2264const struct arc_opcode arc_opcodes[] =
0d2bcfaf 2265{
886a2506 2266#include "arc-tbl.h"
e23e8ebe 2267#include "arc-nps400-tbl.h"
f2dd8838 2268#include "arc-ext-tbl.h"
0d2bcfaf 2269
b99747ae
CZ		 2270 { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } }
2271};
252b5132 2272
886a2506
NC		 2273/* List with special cases instructions and the applicable flags. */
2274const struct arc_flag_special arc_flag_special_cases[] =
252b5132 2275{
886a2506
NC		 2276 { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2277 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2278 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2279 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2280 { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2281 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2282 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2283 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2284 { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2285 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2286 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2287 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2288 { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2289 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2290 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2291 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2292 { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2293 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2294 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2295 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2296 { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2297 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2298 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2299 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2300 { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2301 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2302 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2303 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2304 { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
2305 { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
2306};
252b5132 2307
886a2506 2308const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
252b5132 2309
886a2506 2310/* Relocations. */
886a2506
NC		 2311const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
2312{
24b368f8
CZ		 2313 { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
2314 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2315 { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
2316 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2317 { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
2318 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2319 { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
2320 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2321
2322 /* Next two entries will cover the undefined behavior ldb/stb with
2323 address scaling. */
2324 { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
2325 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2326 { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
2327 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
2328
2329 { "sda", "ld", { F_ASFAKE, F_NULL },
2330 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2331 { "sda", "st", { F_ASFAKE, F_NULL },
2332 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
2333 { "sda", "ldd", { F_ASFAKE, F_NULL },
2334 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2335 { "sda", "std", { F_ASFAKE, F_NULL },
2336 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
886a2506
NC		 2337
2338 /* Short instructions. */
24b368f8
CZ		 2339 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
2340 { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
2341 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
2342 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
2343
2344 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
2345 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2346
2347 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
2348 BFD_RELOC_ARC_S25H_PCREL_PLT },
2349 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
2350 BFD_RELOC_ARC_S21H_PCREL_PLT },
2351 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
2352 BFD_RELOC_ARC_S25W_PCREL_PLT },
2353 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
2354 BFD_RELOC_ARC_S21W_PCREL_PLT },
2355
2356 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
886a2506 2357};
252b5132 2358
886a2506 2359const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
252b5132 2360
886a2506 2361const struct arc_pseudo_insn arc_pseudo_insns[] =
0d2bcfaf 2362{
886a2506
NC		 2363 { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2364 { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
2365 { BRAKETdup, 1, 0, 4} } },
2366 { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2367 { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
2368 { BRAKETdup, 1, 0, 4} } },
2369
2370 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2371 { SIMM9_A16_8, 0, 0, 2 } } },
2372 { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2373 { SIMM9_A16_8, 0, 0, 2 } } },
2374 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2375 { SIMM9_A16_8, 0, 0, 2 } } },
2376 { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2377 { SIMM9_A16_8, 0, 0, 2 } } },
2378 { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2379 { SIMM9_A16_8, 0, 0, 2 } } },
2380
2381 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2382 { SIMM9_A16_8, 0, 0, 2 } } },
2383 { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2384 { SIMM9_A16_8, 0, 0, 2 } } },
2385 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2386 { SIMM9_A16_8, 0, 0, 2 } } },
2387 { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2388 { SIMM9_A16_8, 0, 0, 2 } } },
2389 { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2390 { SIMM9_A16_8, 0, 0, 2 } } },
2391
2392 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2393 { SIMM9_A16_8, 0, 0, 2 } } },
2394 { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2395 { SIMM9_A16_8, 0, 0, 2 } } },
2396 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2397 { SIMM9_A16_8, 0, 0, 2 } } },
2398 { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2399 { SIMM9_A16_8, 0, 0, 2 } } },
2400 { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2401 { SIMM9_A16_8, 0, 0, 2 } } },
2402
2403 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2404 { SIMM9_A16_8, 0, 0, 2 } } },
2405 { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2406 { SIMM9_A16_8, 0, 0, 2 } } },
2407 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2408 { SIMM9_A16_8, 0, 0, 2 } } },
2409 { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2410 { SIMM9_A16_8, 0, 0, 2 } } },
2411 { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2412 { SIMM9_A16_8, 0, 0, 2 } } },
2413};
0d2bcfaf 2414
886a2506
NC		 2415const unsigned arc_num_pseudo_insn =
2416 sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
0d2bcfaf 2417
886a2506 2418const struct arc_aux_reg arc_aux_regs[] =
0d2bcfaf 2419{
886a2506 2420#undef DEF
f36e33da
CZ		 2421#define DEF(ADDR, CPU, SUBCLASS, NAME) \
2422 { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 },
0d2bcfaf 2423
886a2506 2424#include "arc-regs.h"
0d2bcfaf 2425
886a2506
NC		 2426#undef DEF
2427};
0d2bcfaf 2428
886a2506 2429const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
4670103e
CZ		 2430
2431/* NOTE: The order of this array MUST be consistent with 'enum
2432 arc_rlx_types' located in tc-arc.h! */
2433const struct arc_opcode arc_relax_opcodes[] =
2434{
2435 { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
2436
2437 /* bl_s s13 11111sssssssssss. */
2438 { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2439 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2440 { SIMM13_A32_5_S }, { 0 }},
2441
2442 /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
2443 { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2444 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2445 { SIMM25_A32_5 }, { C_D }},
2446
2447 /* b_s s10 1111000sssssssss. */
2448 { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2449 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2450 { SIMM10_A16_7_S }, { 0 }},
2451
2452 /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
2453 { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2454 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2455 { SIMM25_A16_5 }, { C_D }},
2456
2457 /* add_s c,b,u3 01101bbbccc00uuu. Wants UIMM3_13_S_PCREL. */
2458 { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2459 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2460 { RC_S, RB_S, UIMM3_13_S }, { 0 }},
2461
2462 /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. Wants
2463 UIMM6_20_PCREL. */
2464 { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2465 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2466 { RA, RB, UIMM6_20 }, { C_F }},
2467
2468 /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
2469 { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2470 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2471 { RA, RB, LIMM }, { C_F }},
2472
2473 /* ld_s c,b,u7 10000bbbcccuuuuu. Wants UIMM7_A32_11_S_PCREL. */
2474 { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2475 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2476 { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
2477
2478 /* ld<.di><.aa><.x><zz> a,b,s9
2479 00010bbbssssssssSBBBDaaZZXAAAAAA. Wants SIMM9_8_PCREL. */
2480 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2481 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2482 { RA, BRAKET, RB, SIMM9_8, BRAKETdup },
2483 { C_ZZ23, C_DI20, C_AA21, C_X25 }},
2484
2485 /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
2486 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2487 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2488 { RA, BRAKET, RB, LIMM, BRAKETdup },
2489 { C_ZZ13, C_DI16, C_AA8, C_X15 }},
2490
2491 /* mov_s b,u8 11011bbbuuuuuuuu. Wants UIMM8_8_S_PCREL. */
2492 { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2493 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2494 { RB_S, UIMM8_8_S }, { 0 }},
2495
2496 /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. Wants
2497 SIMM12_20_PCREL. */
2498 { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2499 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2500 { RB, SIMM12_20 }, { C_F }},
2501
2502 /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
2503 { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2504 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2505 { RB, LIMM }, { C_F }},
2506
2507 /* sub_s c,b,u3 01101bbbccc01uuu. UIMM3_13_S_PCREL. */
2508 { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2509 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2510 { RC_S, RB_S, UIMM3_13_S }, { 0 }},
2511
2512 /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA.
2513 UIMM6_20_PCREL. */
2514 { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2515 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2516 { RA, RB, UIMM6_20 }, { C_F }},
2517
2518 /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
2519 { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2520 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2521 { RA, RB, LIMM }, { C_F }},
2522
2523 /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA.
2524 UIMM6_20_PCREL. */
2525 { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2526 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }},
2527
2528 /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
2529 { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2530 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
2531
2532 /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ.
2533 UIMM6_20_PCREL. */
2534 { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2535 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2536 { RB, UIMM6_20 }, { C_F, C_CC }},
2537
2538 /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
2539 { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2540 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2541 { RB, LIMM }, { C_F, C_CC }},
2542
2543 /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ.
2544 UIMM6_20_PCREL. */
2545 { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2546 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2547 { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
2548
2549 /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
2550 { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2551 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2552 { RB, RBdup, LIMM }, { C_F, C_CC }}
2553};
2554
2555const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);
4eb6f892
AB		 2556
2557/* The following instructions are all either 48 or 64 bits long, and
2558 require special handling in the assembler and disassembler.
2559
2560 The first part of each ARC_LONG_OPCODE is the base ARC_OPCODE, this is
2561 either the 16 or 32 bit base instruction, and its opcode list will
2562 always end in a LIMM.
2563
2564 The rest of the ARC_LONG_OPCODE describes how to build the LIMM from the
2565 instruction operands. There are therefore two lists of operands for
2566 each ARC_LONG_OPCODE, the second list contains operands that are merged
2567 into the limm template, in the same way that a standard 32-bit
2568 instruction is built. This generated limm is then added to the list of
2569 tokens that is passed to the standard instruction encoder, along with
2570 the first list of operands (from the base arc_opcode).
2571
2572 The first list of operands then, describes how to build the base
2573 instruction, and includes the 32-bit limm that was previously generated
2574 as the last operand.
2575
2576 In most cases operands are either encoded into the base instruction or
2577 into the limm. When this happens the operand slot will be filled with
2578 an operand identifier in one list, and will be IGNORED in the other
2579 list, this special operand value causes the operand to be ignored,
2580 without being encoded at this point.
2581
2582 However, in some cases, an operand is split between the base instruction
2583 and the 32-bit limm, in this case the operand slot will be filled in
2584 both operand lists (see mov4b for one example of this). */
2585const struct arc_long_opcode arc_long_opcodes[] =
2586 {
2587 /* mrgb - (48 bit instruction). */
bdd582db 2588 { { "mrgb", 0x5803, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }},
4eb6f892
AB		 2589 0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_SRC_POS1, NPS_BITOP_SIZE1, NPS_BITOP_DST_POS2, NPS_BITOP_SRC_POS2, NPS_BITOP_SIZE2 }},
2590
2591 /* mrgb.cl - (48 bit instruction). */
bdd582db 2592 { { "mrgb", 0x5803, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
4eb6f892
AB		 2593 0x80000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_SRC_POS1, NPS_BITOP_SIZE1, NPS_BITOP_DST_POS2, NPS_BITOP_SRC_POS2, NPS_BITOP_SIZE2 }},
2594
2595 /* mov2b - (48 bit instruction). */
bdd582db 2596 { { "mov2b", 0x5800, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }},
4eb6f892
AB		 2597 0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2 }},
2598
2599 /* mov2b.cl - (48 bit instruction). */
bdd582db 2600 { { "mov2b", 0x5800, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
4eb6f892
AB		 2601 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2 }},
2602
2603 /* ext4 - (48 bit instruction). */
bdd582db 2604 { { "ext4b", 0x5801, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }},
4eb6f892
AB		 2605 0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_INS_EXT, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2 }},
2606
2607 /* ext4.cl - (48 bit instruction). */
bdd582db 2608 { { "ext4b", 0x5801, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
4eb6f892
AB		 2609 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_INS_EXT, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2 }},
2610
2611 /* ins4 - (48 bit instruction). */
bdd582db 2612 { { "ins4b", 0x5802, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }},
4eb6f892
AB		 2613 0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_INS_EXT }},
2614
2615 /* ins4.cl - (48 bit instruction). */
bdd582db 2616 { { "ins4b", 0x5802, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
4eb6f892
AB		 2617 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_INS_EXT }},
2618
2619 /* mov3b - (64 bit instruction). */
bdd582db 2620 { { "mov3b", 0x58100000, 0xf81f801f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3_POS4, IGNORED, IGNORED, LIMM }, { 0 }},
4eb6f892
AB		 2621 0x80000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3 }},
2622
2623 /* mov4b - (64 bit instruction). */
bdd582db 2624 { { "mov4b", 0x58100000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3, IGNORED, IGNORED, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4_LSB, NPS_BITOP_SRC_POS4, LIMM }, { 0 }},
4eb6f892
AB		 2625 0x00000000, 0x00000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3, IGNORED, NPS_BITOP_MOD4_MSB, IGNORED}},
2626
2627 /* mov3bcl - (64 bit instruction). */
bdd582db 2628 { { "mov3bcl", 0x58110000, 0xf81f801f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3_POS4, IGNORED, IGNORED, LIMM }, { 0 }},
4eb6f892
AB		 2629 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3 }},
2630
2631 /* mov4bcl - (64 bit instruction). */
bdd582db 2632 { { "mov4bcl", 0x58110000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3, IGNORED, IGNORED, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4_LSB, NPS_BITOP_SRC_POS4, LIMM }, { 0 }},
4eb6f892
AB		 2633 0x00000000, 0x00000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3, IGNORED, NPS_BITOP_MOD4_MSB, IGNORED}},
2634
2635 /* mov3b.cl - (64 bit instruction). */
bdd582db 2636 { { "mov3b", 0x58110000, 0xf81f801f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3_POS4, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
4eb6f892
AB		 2637 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3 }},
2638
2639 /* mov4b.cl - (64 bit instruction). */
bdd582db 2640 { { "mov4b", 0x58110000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3, IGNORED, IGNORED, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4_LSB, NPS_BITOP_SRC_POS4, LIMM }, { C_NPS_CL }},
4eb6f892
AB		 2641 0x00000000, 0x00000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3, IGNORED, NPS_BITOP_MOD4_MSB, IGNORED}},
2642};
2643
2644const unsigned arc_num_long_opcodes = ARRAY_SIZE (arc_long_opcodes);
GDB Binutils - Deliverables
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