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[ARC] PLT content endianess awareness.
[deliverable/binutils-gdb.git] / opcodes / arc-opc.c
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252b5132 1/* Opcode table for the ARC.
6f2750fe 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
bcee8eb8 5
9b201bb5
NC		 6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
252b5132 9 it under the terms of the GNU General Public License as published by
9b201bb5 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132
RH		 17
18 You should have received a copy of the GNU General Public License
0d2bcfaf 19 along with this program; if not, write to the Free Software Foundation,
f4321104 20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
252b5132 21
5bd67f35 22#include "sysdep.h"
252b5132 23#include <stdio.h>
d943fe33 24#include "bfd.h"
252b5132 25#include "opcode/arc.h"
47b0e7ad 26#include "opintl.h"
886a2506 27#include "libiberty.h"
252b5132 28
e23e8ebe
AB		 29/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
30 instructions. Support for this target is available when binutils is
31 configured and built for the 'arc*-mellanox-*-*' target. As far as
32 possible all ARC NPS400 features are built into all ARC target builds as
33 this reduces the chances that regressions might creep in. */
34
886a2506
NC		 35/* Insert RB register into a 32-bit opcode. */
36static unsigned
37insert_rb (unsigned insn,
38 int value,
39 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 40{
886a2506
NC		 41 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
42}
0d2bcfaf 43
886a2506
NC		 44static int
45extract_rb (unsigned insn ATTRIBUTE_UNUSED,
46 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47{
48 int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
0d2bcfaf 49
886a2506
NC		 50 if (value == 0x3e && invalid)
51 *invalid = TRUE; /* A limm operand, it should be extracted in a
52 different way. */
252b5132 53
886a2506
NC		 54 return value;
55}
252b5132 56
886a2506
NC		 57static unsigned
58insert_rad (unsigned insn,
59 int value,
60 const char **errmsg ATTRIBUTE_UNUSED)
61{
62 if (value & 0x01)
63 *errmsg = _("Improper register value.");
0d2bcfaf 64
886a2506
NC		 65 return insn | (value & 0x3F);
66}
0d2bcfaf 67
886a2506
NC		 68static unsigned
69insert_rcd (unsigned insn,
70 int value,
71 const char **errmsg ATTRIBUTE_UNUSED)
72{
73 if (value & 0x01)
74 *errmsg = _("Improper register value.");
0d2bcfaf 75
886a2506
NC		 76 return insn | ((value & 0x3F) << 6);
77}
252b5132 78
886a2506 79/* Dummy insert ZERO operand function. */
252b5132 80
886a2506
NC		 81static unsigned
82insert_za (unsigned insn,
83 int value,
84 const char **errmsg)
85{
86 if (value)
87 *errmsg = _("operand is not zero");
88 return insn;
89}
252b5132 90
886a2506
NC		 91/* Insert Y-bit in bbit/br instructions. This function is called only
92 when solving fixups. */
252b5132 93
886a2506
NC		 94static unsigned
95insert_Ybit (unsigned insn,
96 int value,
97 const char **errmsg ATTRIBUTE_UNUSED)
98{
99 if (value > 0)
100 insn |= 0x08;
252b5132 101
886a2506
NC		 102 return insn;
103}
252b5132 104
886a2506
NC		 105/* Insert Y-bit in bbit/br instructions. This function is called only
106 when solving fixups. */
252b5132 107
886a2506
NC		 108static unsigned
109insert_NYbit (unsigned insn,
110 int value,
111 const char **errmsg ATTRIBUTE_UNUSED)
112{
113 if (value < 0)
114 insn |= 0x08;
0d2bcfaf 115
886a2506
NC		 116 return insn;
117}
252b5132 118
886a2506 119/* Insert H register into a 16-bit opcode. */
252b5132 120
886a2506
NC		 121static unsigned
122insert_rhv1 (unsigned insn,
123 int value,
124 const char **errmsg ATTRIBUTE_UNUSED)
125{
126 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
127}
252b5132 128
886a2506
NC		 129static int
130extract_rhv1 (unsigned insn ATTRIBUTE_UNUSED,
131 bfd_boolean * invalid ATTRIBUTE_UNUSED)
132{
133 int value = 0;
252b5132 134
886a2506
NC		 135 return value;
136}
252b5132 137
886a2506 138/* Insert H register into a 16-bit opcode. */
252b5132 139
886a2506
NC		 140static unsigned
141insert_rhv2 (unsigned insn,
142 int value,
143 const char **errmsg)
0d2bcfaf 144{
886a2506
NC		 145 if (value == 0x1E)
146 *errmsg =
147 _("Register R30 is a limm indicator for this type of instruction.");
148 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
149}
252b5132 150
886a2506
NC		 151static int
152extract_rhv2 (unsigned insn ATTRIBUTE_UNUSED,
153 bfd_boolean * invalid ATTRIBUTE_UNUSED)
154{
155 int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
0d2bcfaf 156
886a2506
NC		 157 return value;
158}
0d2bcfaf 159
886a2506
NC		 160static unsigned
161insert_r0 (unsigned insn,
162 int value,
163 const char **errmsg ATTRIBUTE_UNUSED)
164{
165 if (value != 0)
166 *errmsg = _("Register must be R0.");
47b0e7ad
NC		 167 return insn;
168}
252b5132 169
886a2506
NC		 170static int
171extract_r0 (unsigned insn ATTRIBUTE_UNUSED,
172 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 173{
886a2506 174 return 0;
47b0e7ad 175}
252b5132 176
252b5132 177
886a2506
NC		 178static unsigned
179insert_r1 (unsigned insn,
180 int value,
181 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 182{
886a2506
NC		 183 if (value != 1)
184 *errmsg = _("Register must be R1.");
47b0e7ad 185 return insn;
252b5132
RH		 186}
187
886a2506
NC		 188static int
189extract_r1 (unsigned insn ATTRIBUTE_UNUSED,
190 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 191{
886a2506 192 return 1;
252b5132
RH		 193}
194
886a2506
NC		 195static unsigned
196insert_r2 (unsigned insn,
197 int value,
198 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 199{
886a2506
NC		 200 if (value != 2)
201 *errmsg = _("Register must be R2.");
47b0e7ad 202 return insn;
252b5132
RH		 203}
204
886a2506
NC		 205static int
206extract_r2 (unsigned insn ATTRIBUTE_UNUSED,
207 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 208{
886a2506 209 return 2;
252b5132
RH		 210}
211
886a2506
NC		 212static unsigned
213insert_r3 (unsigned insn,
214 int value,
215 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 216{
886a2506
NC		 217 if (value != 3)
218 *errmsg = _("Register must be R3.");
47b0e7ad 219 return insn;
0d2bcfaf
NC		 220}
221
886a2506
NC		 222static int
223extract_r3 (unsigned insn ATTRIBUTE_UNUSED,
224 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 225{
886a2506 226 return 3;
0d2bcfaf
NC		 227}
228
886a2506
NC		 229static unsigned
230insert_sp (unsigned insn,
231 int value,
232 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 233{
886a2506
NC		 234 if (value != 28)
235 *errmsg = _("Register must be SP.");
252b5132
RH		 236 return insn;
237}
238
886a2506
NC		 239static int
240extract_sp (unsigned insn ATTRIBUTE_UNUSED,
241 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 242{
886a2506 243 return 28;
0d2bcfaf
NC		 244}
245
886a2506
NC		 246static unsigned
247insert_gp (unsigned insn,
248 int value,
249 const char **errmsg ATTRIBUTE_UNUSED)
0d2bcfaf 250{
886a2506
NC		 251 if (value != 26)
252 *errmsg = _("Register must be GP.");
253 return insn;
0d2bcfaf
NC		 254}
255
886a2506
NC		 256static int
257extract_gp (unsigned insn ATTRIBUTE_UNUSED,
258 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 259{
886a2506 260 return 26;
0d2bcfaf
NC		 261}
262
886a2506
NC		 263static unsigned
264insert_pcl (unsigned insn,
265 int value,
266 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 267{
886a2506
NC		 268 if (value != 63)
269 *errmsg = _("Register must be PCL.");
252b5132
RH		 270 return insn;
271}
272
886a2506
NC		 273static int
274extract_pcl (unsigned insn ATTRIBUTE_UNUSED,
275 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 276{
886a2506 277 return 63;
0d2bcfaf
NC		 278}
279
886a2506
NC		 280static unsigned
281insert_blink (unsigned insn,
282 int value,
283 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 284{
886a2506
NC		 285 if (value != 31)
286 *errmsg = _("Register must be BLINK.");
252b5132
RH		 287 return insn;
288}
289
886a2506
NC		 290static int
291extract_blink (unsigned insn ATTRIBUTE_UNUSED,
292 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 293{
886a2506 294 return 31;
0d2bcfaf
NC		 295}
296
886a2506
NC		 297static unsigned
298insert_ilink1 (unsigned insn,
299 int value,
300 const char **errmsg ATTRIBUTE_UNUSED)
0d2bcfaf 301{
886a2506
NC		 302 if (value != 29)
303 *errmsg = _("Register must be ILINK1.");
252b5132
RH		 304 return insn;
305}
306
886a2506
NC		 307static int
308extract_ilink1 (unsigned insn ATTRIBUTE_UNUSED,
309 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 310{
886a2506 311 return 29;
252b5132
RH		 312}
313
886a2506
NC		 314static unsigned
315insert_ilink2 (unsigned insn,
316 int value,
317 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 318{
886a2506
NC		 319 if (value != 30)
320 *errmsg = _("Register must be ILINK2.");
252b5132
RH		 321 return insn;
322}
323
886a2506
NC		 324static int
325extract_ilink2 (unsigned insn ATTRIBUTE_UNUSED,
326 bfd_boolean * invalid ATTRIBUTE_UNUSED)
327{
328 return 30;
329}
252b5132 330
886a2506
NC		 331static unsigned
332insert_ras (unsigned insn,
333 int value,
334 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 335{
886a2506 336 switch (value)
0d2bcfaf 337 {
886a2506
NC		 338 case 0:
339 case 1:
340 case 2:
341 case 3:
342 insn |= value;
343 break;
344 case 12:
345 case 13:
346 case 14:
347 case 15:
348 insn |= (value - 8);
349 break;
350 default:
351 *errmsg = _("Register must be either r0-r3 or r12-r15.");
352 break;
0d2bcfaf 353 }
252b5132
RH		 354 return insn;
355}
252b5132 356
886a2506
NC		 357static int
358extract_ras (unsigned insn ATTRIBUTE_UNUSED,
359 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 360{
886a2506
NC		 361 int value = insn & 0x07;
362 if (value > 3)
363 return (value + 8);
364 else
365 return value;
47b0e7ad
NC		 366}
367
886a2506
NC		 368static unsigned
369insert_rbs (unsigned insn,
370 int value,
371 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 372{
886a2506 373 switch (value)
47b0e7ad 374 {
886a2506
NC		 375 case 0:
376 case 1:
377 case 2:
378 case 3:
379 insn |= value << 8;
380 break;
381 case 12:
382 case 13:
383 case 14:
384 case 15:
385 insn |= ((value - 8)) << 8;
386 break;
387 default:
388 *errmsg = _("Register must be either r0-r3 or r12-r15.");
389 break;
47b0e7ad 390 }
886a2506 391 return insn;
252b5132
RH		 392}
393
886a2506
NC		 394static int
395extract_rbs (unsigned insn ATTRIBUTE_UNUSED,
396 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 397{
886a2506
NC		 398 int value = (insn >> 8) & 0x07;
399 if (value > 3)
400 return (value + 8);
401 else
402 return value;
403}
252b5132 404
886a2506
NC		 405static unsigned
406insert_rcs (unsigned insn,
407 int value,
408 const char **errmsg ATTRIBUTE_UNUSED)
409{
410 switch (value)
252b5132 411 {
886a2506
NC		 412 case 0:
413 case 1:
414 case 2:
415 case 3:
416 insn |= value << 5;
417 break;
418 case 12:
419 case 13:
420 case 14:
421 case 15:
422 insn |= ((value - 8)) << 5;
423 break;
424 default:
425 *errmsg = _("Register must be either r0-r3 or r12-r15.");
426 break;
252b5132 427 }
886a2506
NC		 428 return insn;
429}
47b0e7ad 430
886a2506
NC		 431static int
432extract_rcs (unsigned insn ATTRIBUTE_UNUSED,
433 bfd_boolean * invalid ATTRIBUTE_UNUSED)
434{
435 int value = (insn >> 5) & 0x07;
436 if (value > 3)
437 return (value + 8);
252b5132 438 else
886a2506
NC		 439 return value;
440}
47b0e7ad 441
886a2506
NC		 442static unsigned
443insert_simm3s (unsigned insn,
444 int value,
445 const char **errmsg ATTRIBUTE_UNUSED)
446{
447 int tmp = 0;
448 switch (value)
47b0e7ad 449 {
886a2506
NC		 450 case -1:
451 tmp = 0x07;
47b0e7ad 452 break;
886a2506
NC		 453 case 0:
454 tmp = 0x00;
455 break;
456 case 1:
457 tmp = 0x01;
47b0e7ad 458 break;
886a2506
NC		 459 case 2:
460 tmp = 0x02;
47b0e7ad 461 break;
886a2506
NC		 462 case 3:
463 tmp = 0x03;
464 break;
465 case 4:
466 tmp = 0x04;
467 break;
468 case 5:
469 tmp = 0x05;
470 break;
471 case 6:
472 tmp = 0x06;
473 break;
474 default:
475 *errmsg = _("Accepted values are from -1 to 6.");
47b0e7ad
NC		 476 break;
477 }
478
886a2506
NC		 479 insn |= tmp << 8;
480 return insn;
47b0e7ad
NC		 481}
482
886a2506
NC		 483static int
484extract_simm3s (unsigned insn ATTRIBUTE_UNUSED,
485 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 486{
886a2506
NC		 487 int value = (insn >> 8) & 0x07;
488 if (value == 7)
489 return -1;
47b0e7ad 490 else
886a2506 491 return value;
47b0e7ad
NC		 492}
493
886a2506
NC		 494static unsigned
495insert_rrange (unsigned insn,
496 int value,
497 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 498{
886a2506
NC		 499 int reg1 = (value >> 16) & 0xFFFF;
500 int reg2 = value & 0xFFFF;
501 if (reg1 != 13)
502 {
503 *errmsg = _("First register of the range should be r13.");
504 return insn;
505 }
506 if (reg2 < 13 || reg2 > 26)
507 {
508 *errmsg = _("Last register of the range doesn't fit.");
509 return insn;
510 }
511 insn |= ((reg2 - 12) & 0x0F) << 1;
512 return insn;
47b0e7ad
NC		 513}
514
886a2506
NC		 515static int
516extract_rrange (unsigned insn ATTRIBUTE_UNUSED,
517 bfd_boolean * invalid ATTRIBUTE_UNUSED)
518{
519 return (insn >> 1) & 0x0F;
520}
47b0e7ad 521
886a2506
NC		 522static unsigned
523insert_fpel (unsigned insn,
524 int value,
525 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 526{
886a2506
NC		 527 if (value != 27)
528 {
529 *errmsg = _("Invalid register number, should be fp.");
530 return insn;
531 }
47b0e7ad 532
886a2506
NC		 533 insn |= 0x0100;
534 return insn;
47b0e7ad
NC		 535}
536
886a2506
NC		 537static int
538extract_fpel (unsigned insn ATTRIBUTE_UNUSED,
539 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 540{
886a2506 541 return (insn & 0x0100) ? 27 : -1;
47b0e7ad
NC		 542}
543
886a2506
NC		 544static unsigned
545insert_blinkel (unsigned insn,
546 int value,
547 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 548{
886a2506 549 if (value != 31)
47b0e7ad 550 {
886a2506
NC		 551 *errmsg = _("Invalid register number, should be blink.");
552 return insn;
47b0e7ad 553 }
47b0e7ad 554
886a2506
NC		 555 insn |= 0x0200;
556 return insn;
47b0e7ad
NC		 557}
558
886a2506
NC		 559static int
560extract_blinkel (unsigned insn ATTRIBUTE_UNUSED,
561 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 562{
886a2506
NC		 563 return (insn & 0x0200) ? 31 : -1;
564}
47b0e7ad 565
886a2506
NC		 566static unsigned
567insert_pclel (unsigned insn,
568 int value,
569 const char **errmsg ATTRIBUTE_UNUSED)
570{
571 if (value != 63)
47b0e7ad 572 {
886a2506
NC		 573 *errmsg = _("Invalid register number, should be pcl.");
574 return insn;
47b0e7ad 575 }
47b0e7ad 576
886a2506
NC		 577 insn |= 0x0400;
578 return insn;
579}
47b0e7ad 580
886a2506
NC		 581static int
582extract_pclel (unsigned insn ATTRIBUTE_UNUSED,
583 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 584{
886a2506 585 return (insn & 0x0400) ? 63 : -1;
47b0e7ad 586}
47b0e7ad 587
886a2506
NC		 588#define INSERT_W6
589/* mask = 00000000000000000000111111000000
590 insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
591static unsigned
592insert_w6 (unsigned insn ATTRIBUTE_UNUSED,
593 int value ATTRIBUTE_UNUSED,
594 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 595{
886a2506 596 insn |= ((value >> 0) & 0x003f) << 6;
47b0e7ad 597
886a2506
NC		 598 return insn;
599}
47b0e7ad 600
886a2506
NC		 601#define EXTRACT_W6
602/* mask = 00000000000000000000111111000000. */
603static int
604extract_w6 (unsigned insn ATTRIBUTE_UNUSED,
605 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 606{
886a2506 607 unsigned value = 0;
47b0e7ad 608
886a2506 609 value |= ((insn >> 6) & 0x003f) << 0;
47b0e7ad 610
886a2506
NC		 611 return value;
612}
47b0e7ad 613
886a2506
NC		 614#define INSERT_G_S
615/* mask = 0000011100022000
616 insn = 01000ggghhhGG0HH. */
617static unsigned
618insert_g_s (unsigned insn ATTRIBUTE_UNUSED,
619 int value ATTRIBUTE_UNUSED,
620 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 621{
886a2506
NC		 622 insn |= ((value >> 0) & 0x0007) << 8;
623 insn |= ((value >> 3) & 0x0003) << 3;
252b5132 624
886a2506
NC		 625 return insn;
626}
252b5132 627
886a2506
NC		 628#define EXTRACT_G_S
629/* mask = 0000011100022000. */
630static int
631extract_g_s (unsigned insn ATTRIBUTE_UNUSED,
632 bfd_boolean * invalid ATTRIBUTE_UNUSED)
633{
634 int value = 0;
252b5132 635
886a2506
NC		 636 value |= ((insn >> 8) & 0x0007) << 0;
637 value |= ((insn >> 3) & 0x0003) << 3;
252b5132 638
886a2506
NC		 639 /* Extend the sign. */
640 int signbit = 1 << (6 - 1);
641 value = (value ^ signbit) - signbit;
252b5132 642
886a2506 643 return value;
252b5132
RH		 644}
645
e23e8ebe
AB		 646/* ARC NPS400 Support: See comment near head of file. */
647static unsigned
648insert_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
649 int value ATTRIBUTE_UNUSED,
650 const char **errmsg ATTRIBUTE_UNUSED)
651{
652 switch (value)
653 {
654 case 0:
655 case 1:
656 case 2:
657 case 3:
658 insn |= value << 24;
659 break;
660 case 12:
661 case 13:
662 case 14:
663 case 15:
664 insn |= (value - 8) << 24;
665 break;
666 default:
667 *errmsg = _("Register must be either r0-r3 or r12-r15.");
668 break;
669 }
670 return insn;
671}
672
673static int
674extract_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
675 bfd_boolean * invalid ATTRIBUTE_UNUSED)
676{
677 int value = (insn >> 24) & 0x07;
678 if (value > 3)
679 return (value + 8);
680 else
681 return value;
682}
683
684static unsigned
685insert_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
686 int value ATTRIBUTE_UNUSED,
687 const char **errmsg ATTRIBUTE_UNUSED)
688{
689 switch (value)
690 {
691 case 0:
692 case 1:
693 case 2:
694 case 3:
695 insn |= value << 21;
696 break;
697 case 12:
698 case 13:
699 case 14:
700 case 15:
701 insn |= (value - 8) << 21;
702 break;
703 default:
704 *errmsg = _("Register must be either r0-r3 or r12-r15.");
705 break;
706 }
707 return insn;
708}
709
710static int
711extract_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
712 bfd_boolean * invalid ATTRIBUTE_UNUSED)
713{
714 int value = (insn >> 21) & 0x07;
715 if (value > 3)
716 return (value + 8);
717 else
718 return value;
719}
720
721static unsigned
722insert_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
723 int value ATTRIBUTE_UNUSED,
724 const char **errmsg ATTRIBUTE_UNUSED)
725{
726 if (value < 1 || value > 32)
727 {
728 *errmsg = _("Invalid bit size, should be between 1 and 32 inclusive.");
729 return insn;
730 }
731
732 --value;
733 insn |= ((value & 0x1f) << 10);
734 return insn;
735}
736
737static int
738extract_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
739 bfd_boolean * invalid ATTRIBUTE_UNUSED)
740{
741 return ((insn >> 10) & 0x1f) + 1;
742}
743
886a2506
NC		 744/* Include the generic extract/insert functions. Order is important
745 as some of the functions present in the .h may be disabled via
746 defines. */
747#include "arc-fxi.h"
252b5132 748
886a2506 749/* The flag operands table.
252b5132 750
886a2506
NC		 751 The format of the table is
752 NAME CODE BITS SHIFT FAVAIL. */
753const struct arc_flag_operand arc_flag_operands[] =
754{
755#define F_NULL 0
756 { 0, 0, 0, 0, 0},
757#define F_ALWAYS (F_NULL + 1)
758 { "al", 0, 0, 0, 0 },
759#define F_RA (F_ALWAYS + 1)
760 { "ra", 0, 0, 0, 0 },
761#define F_EQUAL (F_RA + 1)
762 { "eq", 1, 5, 0, 1 },
763#define F_ZERO (F_EQUAL + 1)
764 { "z", 1, 5, 0, 0 },
765#define F_NOTEQUAL (F_ZERO + 1)
766 { "ne", 2, 5, 0, 1 },
767#define F_NOTZERO (F_NOTEQUAL + 1)
768 { "nz", 2, 5, 0, 0 },
769#define F_POZITIVE (F_NOTZERO + 1)
770 { "p", 3, 5, 0, 1 },
771#define F_PL (F_POZITIVE + 1)
772 { "pl", 3, 5, 0, 0 },
773#define F_NEGATIVE (F_PL + 1)
774 { "n", 4, 5, 0, 1 },
775#define F_MINUS (F_NEGATIVE + 1)
776 { "mi", 4, 5, 0, 0 },
777#define F_CARRY (F_MINUS + 1)
778 { "c", 5, 5, 0, 1 },
779#define F_CARRYSET (F_CARRY + 1)
780 { "cs", 5, 5, 0, 0 },
781#define F_LOWER (F_CARRYSET + 1)
782 { "lo", 5, 5, 0, 0 },
783#define F_CARRYCLR (F_LOWER + 1)
784 { "cc", 6, 5, 0, 0 },
785#define F_NOTCARRY (F_CARRYCLR + 1)
786 { "nc", 6, 5, 0, 1 },
787#define F_HIGHER (F_NOTCARRY + 1)
788 { "hs", 6, 5, 0, 0 },
789#define F_OVERFLOWSET (F_HIGHER + 1)
790 { "vs", 7, 5, 0, 0 },
791#define F_OVERFLOW (F_OVERFLOWSET + 1)
792 { "v", 7, 5, 0, 1 },
793#define F_NOTOVERFLOW (F_OVERFLOW + 1)
794 { "nv", 8, 5, 0, 1 },
795#define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
796 { "vc", 8, 5, 0, 0 },
797#define F_GT (F_OVERFLOWCLR + 1)
798 { "gt", 9, 5, 0, 1 },
799#define F_GE (F_GT + 1)
800 { "ge", 10, 5, 0, 1 },
801#define F_LT (F_GE + 1)
802 { "lt", 11, 5, 0, 1 },
803#define F_LE (F_LT + 1)
804 { "le", 12, 5, 0, 1 },
805#define F_HI (F_LE + 1)
806 { "hi", 13, 5, 0, 1 },
807#define F_LS (F_HI + 1)
808 { "ls", 14, 5, 0, 1 },
809#define F_PNZ (F_LS + 1)
810 { "pnz", 15, 5, 0, 1 },
811
812 /* FLAG. */
813#define F_FLAG (F_PNZ + 1)
814 { "f", 1, 1, 15, 1 },
815#define F_FFAKE (F_FLAG + 1)
816 { "f", 0, 0, 0, 1 },
817
818 /* Delay slot. */
819#define F_ND (F_FFAKE + 1)
820 { "nd", 0, 1, 5, 0 },
821#define F_D (F_ND + 1)
822 { "d", 1, 1, 5, 1 },
823#define F_DFAKE (F_D + 1)
824 { "d", 0, 0, 0, 1 },
825
826 /* Data size. */
827#define F_SIZEB1 (F_DFAKE + 1)
828 { "b", 1, 2, 1, 1 },
829#define F_SIZEB7 (F_SIZEB1 + 1)
830 { "b", 1, 2, 7, 1 },
831#define F_SIZEB17 (F_SIZEB7 + 1)
832 { "b", 1, 2, 17, 1 },
833#define F_SIZEW1 (F_SIZEB17 + 1)
834 { "w", 2, 2, 1, 0 },
835#define F_SIZEW7 (F_SIZEW1 + 1)
836 { "w", 2, 2, 7, 0 },
837#define F_SIZEW17 (F_SIZEW7 + 1)
838 { "w", 2, 2, 17, 0 },
839
840 /* Sign extension. */
841#define F_SIGN6 (F_SIZEW17 + 1)
842 { "x", 1, 1, 6, 1 },
843#define F_SIGN16 (F_SIGN6 + 1)
844 { "x", 1, 1, 16, 1 },
845#define F_SIGNX (F_SIGN16 + 1)
846 { "x", 0, 0, 0, 1 },
847
848 /* Address write-back modes. */
849#define F_A3 (F_SIGNX + 1)
850 { "a", 1, 2, 3, 0 },
851#define F_A9 (F_A3 + 1)
852 { "a", 1, 2, 9, 0 },
853#define F_A22 (F_A9 + 1)
854 { "a", 1, 2, 22, 0 },
855#define F_AW3 (F_A22 + 1)
856 { "aw", 1, 2, 3, 1 },
857#define F_AW9 (F_AW3 + 1)
858 { "aw", 1, 2, 9, 1 },
859#define F_AW22 (F_AW9 + 1)
860 { "aw", 1, 2, 22, 1 },
861#define F_AB3 (F_AW22 + 1)
862 { "ab", 2, 2, 3, 1 },
863#define F_AB9 (F_AB3 + 1)
864 { "ab", 2, 2, 9, 1 },
865#define F_AB22 (F_AB9 + 1)
866 { "ab", 2, 2, 22, 1 },
867#define F_AS3 (F_AB22 + 1)
868 { "as", 3, 2, 3, 1 },
869#define F_AS9 (F_AS3 + 1)
870 { "as", 3, 2, 9, 1 },
871#define F_AS22 (F_AS9 + 1)
872 { "as", 3, 2, 22, 1 },
873#define F_ASFAKE (F_AS22 + 1)
874 { "as", 0, 0, 0, 1 },
875
876 /* Cache bypass. */
877#define F_DI5 (F_ASFAKE + 1)
878 { "di", 1, 1, 5, 1 },
879#define F_DI11 (F_DI5 + 1)
880 { "di", 1, 1, 11, 1 },
881#define F_DI15 (F_DI11 + 1)
882 { "di", 1, 1, 15, 1 },
883
884 /* ARCv2 specific. */
885#define F_NT (F_DI15 + 1)
886 { "nt", 0, 1, 3, 1},
887#define F_T (F_NT + 1)
888 { "t", 1, 1, 3, 1},
889#define F_H1 (F_T + 1)
890 { "h", 2, 2, 1, 1 },
891#define F_H7 (F_H1 + 1)
892 { "h", 2, 2, 7, 1 },
893#define F_H17 (F_H7 + 1)
894 { "h", 2, 2, 17, 1 },
895
896 /* Fake Flags. */
897#define F_NE (F_H17 + 1)
898 { "ne", 0, 0, 0, 1 },
e23e8ebe
AB		 899
900 /* ARC NPS400 Support: See comment near head of file. */
901#define F_NPS_CL (F_NE + 1)
902 { "cl", 0, 0, 0, 1 },
903
904#define F_NPS_FLAG (F_NPS_CL + 1)
905 { "f", 1, 1, 20, 1 },
886a2506 906};
252b5132 907
886a2506 908const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
252b5132 909
886a2506 910/* Table of the flag classes.
252b5132 911
886a2506
NC		 912 The format of the table is
913 CLASS {FLAG_CODE}. */
914const struct arc_flag_class arc_flag_classes[] =
915{
916#define C_EMPTY 0
1ae8ab47 917 { F_CLASS_NONE, { F_NULL } },
886a2506
NC		 918
919#define C_CC (C_EMPTY + 1)
1ae8ab47
AB		 920 { F_CLASS_OPTIONAL, { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
921 F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
922 F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
923 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
924 F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
925 F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
886a2506
NC		 926
927#define C_AA_ADDR3 (C_CC + 1)
928#define C_AA27 (C_CC + 1)
1ae8ab47 929 { F_CLASS_OPTIONAL, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
886a2506
NC		 930#define C_AA_ADDR9 (C_AA_ADDR3 + 1)
931#define C_AA21 (C_AA_ADDR3 + 1)
1ae8ab47 932 { F_CLASS_OPTIONAL, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
886a2506
NC		 933#define C_AA_ADDR22 (C_AA_ADDR9 + 1)
934#define C_AA8 (C_AA_ADDR9 + 1)
1ae8ab47 935 { F_CLASS_OPTIONAL, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
886a2506
NC		 936
937#define C_F (C_AA_ADDR22 + 1)
1ae8ab47 938 { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
886a2506 939#define C_FHARD (C_F + 1)
1ae8ab47 940 { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
886a2506
NC		 941
942#define C_T (C_FHARD + 1)
1ae8ab47 943 { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
886a2506 944#define C_D (C_T + 1)
1ae8ab47 945 { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
886a2506
NC		 946
947#define C_DHARD (C_D + 1)
1ae8ab47 948 { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
886a2506
NC		 949
950#define C_DI20 (C_DHARD + 1)
1ae8ab47 951 { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
886a2506 952#define C_DI16 (C_DI20 + 1)
1ae8ab47 953 { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
886a2506 954#define C_DI26 (C_DI16 + 1)
1ae8ab47 955 { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
886a2506
NC		 956
957#define C_X25 (C_DI26 + 1)
1ae8ab47 958 { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
886a2506 959#define C_X15 (C_X25 + 1)
1ae8ab47 960 { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
886a2506
NC		 961#define C_XHARD (C_X15 + 1)
962#define C_X (C_X15 + 1)
1ae8ab47 963 { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
886a2506
NC		 964
965#define C_ZZ13 (C_X + 1)
1ae8ab47 966 { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
886a2506 967#define C_ZZ23 (C_ZZ13 + 1)
1ae8ab47 968 { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
886a2506 969#define C_ZZ29 (C_ZZ23 + 1)
1ae8ab47 970 { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
886a2506
NC		 971
972#define C_AS (C_ZZ29 + 1)
1ae8ab47 973 { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
886a2506
NC		 974
975#define C_NE (C_AS + 1)
1ae8ab47 976 { F_CLASS_OPTIONAL, { F_NE, F_NULL}},
e23e8ebe
AB		 977
978 /* ARC NPS400 Support: See comment near head of file. */
979#define C_NPS_CL (C_NE + 1)
980 { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
981
982#define C_NPS_F (C_NPS_CL + 1)
983 { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
886a2506 984};
252b5132 985
886a2506 986/* The operands table.
252b5132 987
886a2506 988 The format of the operands table is:
47b0e7ad 989
886a2506
NC		 990 BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
991const struct arc_operand arc_operands[] =
0d2bcfaf 992{
886a2506
NC		 993 /* The fields are bits, shift, insert, extract, flags. The zero
994 index is used to indicate end-of-list. */
995#define UNUSED 0
996 { 0, 0, 0, 0, 0, 0 },
997 /* The plain integer register fields. Used by 32 bit
998 instructions. */
999#define RA (UNUSED + 1)
1000 { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
1001#define RB (RA + 1)
1002 { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
1003#define RC (RB + 1)
1004 { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
1005#define RBdup (RC + 1)
1006 { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
1007
1008#define RAD (RBdup + 1)
1009 { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
1010#define RCD (RAD + 1)
1011 { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
1012
1013 /* The plain integer register fields. Used by short
1014 instructions. */
1015#define RA16 (RCD + 1)
1016#define RA_S (RCD + 1)
1017 { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
1018#define RB16 (RA16 + 1)
1019#define RB_S (RA16 + 1)
1020 { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
1021#define RB16dup (RB16 + 1)
1022#define RB_Sdup (RB16 + 1)
1023 { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
1024#define RC16 (RB16dup + 1)
1025#define RC_S (RB16dup + 1)
1026 { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
1027#define R6H (RC16 + 1) /* 6bit register field 'h' used
1028 by V1 cpus. */
1029 { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
1030#define R5H (R6H + 1) /* 5bit register field 'h' used
1031 by V2 cpus. */
1032#define RH_S (R6H + 1) /* 5bit register field 'h' used
1033 by V2 cpus. */
1034 { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
1035#define R5Hdup (R5H + 1)
1036#define RH_Sdup (R5H + 1)
1037 { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
1038 insert_rhv2, extract_rhv2 },
1039
1040#define RG (R5Hdup + 1)
1041#define G_S (R5Hdup + 1)
1042 { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
1043
1044 /* Fix registers. */
1045#define R0 (RG + 1)
1046#define R0_S (RG + 1)
1047 { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
1048#define R1 (R0 + 1)
1049#define R1_S (R0 + 1)
1050 { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
1051#define R2 (R1 + 1)
1052#define R2_S (R1 + 1)
1053 { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
1054#define R3 (R2 + 1)
1055#define R3_S (R2 + 1)
1056 { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
1057#define SP (R3 + 1)
1058#define SP_S (R3 + 1)
1059 { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
1060#define SPdup (SP + 1)
1061#define SP_Sdup (SP + 1)
1062 { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
1063#define GP (SPdup + 1)
1064#define GP_S (SPdup + 1)
1065 { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
1066
1067#define PCL_S (GP + 1)
1068 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
1069
1070#define BLINK (PCL_S + 1)
1071#define BLINK_S (PCL_S + 1)
1072 { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
1073
1074#define ILINK1 (BLINK + 1)
1075 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
1076#define ILINK2 (ILINK1 + 1)
1077 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
1078
1079 /* Long immediate. */
1080#define LIMM (ILINK2 + 1)
1081#define LIMM_S (ILINK2 + 1)
1082 { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
1083#define LIMMdup (LIMM + 1)
1084 { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
1085
1086 /* Special operands. */
1087#define ZA (LIMMdup + 1)
1088#define ZB (LIMMdup + 1)
1089#define ZA_S (LIMMdup + 1)
1090#define ZB_S (LIMMdup + 1)
1091#define ZC_S (LIMMdup + 1)
1092 { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
1093
1094#define RRANGE_EL (ZA + 1)
1095 { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
1096 insert_rrange, extract_rrange},
1097#define FP_EL (RRANGE_EL + 1)
1098 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1099 insert_fpel, extract_fpel },
1100#define BLINK_EL (FP_EL + 1)
1101 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1102 insert_blinkel, extract_blinkel },
1103#define PCL_EL (BLINK_EL + 1)
1104 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1105 insert_pclel, extract_pclel },
1106
1107 /* Fake operand to handle the T flag. */
1108#define BRAKET (PCL_EL + 1)
1109#define BRAKETdup (PCL_EL + 1)
1110 { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
1111
1112 /* Fake operand to handle the T flag. */
1113#define FKT_T (BRAKET + 1)
1114 { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
1115 /* Fake operand to handle the T flag. */
1116#define FKT_NT (FKT_T + 1)
1117 { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
1118
1119 /* UIMM6_20 mask = 00000000000000000000111111000000. */
1120#define UIMM6_20 (FKT_NT + 1)
1121 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
1122
1123 /* SIMM12_20 mask = 00000000000000000000111111222222. */
1124#define SIMM12_20 (UIMM6_20 + 1)
1125 {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
1126
1127 /* SIMM3_5_S mask = 0000011100000000. */
1128#define SIMM3_5_S (SIMM12_20 + 1)
1129 {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
1130 insert_simm3s, extract_simm3s},
1131
1132 /* UIMM7_A32_11_S mask = 0000000000011111. */
1133#define UIMM7_A32_11_S (SIMM3_5_S + 1)
1134 {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1135 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
1136 extract_uimm7_a32_11_s},
1137
1138 /* UIMM7_9_S mask = 0000000001111111. */
1139#define UIMM7_9_S (UIMM7_A32_11_S + 1)
1140 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
1141
1142 /* UIMM3_13_S mask = 0000000000000111. */
1143#define UIMM3_13_S (UIMM7_9_S + 1)
1144 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
1145
1146 /* SIMM11_A32_7_S mask = 0000000111111111. */
1147#define SIMM11_A32_7_S (UIMM3_13_S + 1)
1148 {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1149 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
1150
1151 /* UIMM6_13_S mask = 0000000002220111. */
1152#define UIMM6_13_S (SIMM11_A32_7_S + 1)
1153 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
1154 /* UIMM5_11_S mask = 0000000000011111. */
1155#define UIMM5_11_S (UIMM6_13_S + 1)
1156 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
1157 extract_uimm5_11_s},
1158
1159 /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
1160#define SIMM9_A16_8 (UIMM5_11_S + 1)
1161 {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1162 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
1163 extract_simm9_a16_8},
1164
1165 /* UIMM6_8 mask = 00000000000000000000111111000000. */
1166#define UIMM6_8 (SIMM9_A16_8 + 1)
1167 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
1168
1169 /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
1170#define SIMM21_A16_5 (UIMM6_8 + 1)
1171 {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
1172 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE,
1173 insert_simm21_a16_5, extract_simm21_a16_5},
1174
1175 /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
1176#define SIMM25_A16_5 (SIMM21_A16_5 + 1)
1177 {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
1178 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
1179 insert_simm25_a16_5, extract_simm25_a16_5},
1180
1181 /* SIMM10_A16_7_S mask = 0000000111111111. */
1182#define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
1183 {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1184 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
1185 extract_simm10_a16_7_s},
1186
1187#define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1)
1188 {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1189 | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
1190
1191 /* SIMM7_A16_10_S mask = 0000000000111111. */
1192#define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
1193 {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1194 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
1195 extract_simm7_a16_10_s},
1196
1197 /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
1198#define SIMM21_A32_5 (SIMM7_A16_10_S + 1)
1199 {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1200 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
1201 extract_simm21_a32_5},
1202
1203 /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
1204#define SIMM25_A32_5 (SIMM21_A32_5 + 1)
1205 {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1206 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
1207 extract_simm25_a32_5},
1208
1209 /* SIMM13_A32_5_S mask = 0000011111111111. */
1210#define SIMM13_A32_5_S (SIMM25_A32_5 + 1)
1211 {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1212 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
1213 extract_simm13_a32_5_s},
1214
1215 /* SIMM8_A16_9_S mask = 0000000001111111. */
1216#define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
1217 {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1218 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
1219 extract_simm8_a16_9_s},
1220
1221 /* UIMM3_23 mask = 00000000000000000000000111000000. */
1222#define UIMM3_23 (SIMM8_A16_9_S + 1)
1223 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
1224
1225 /* UIMM10_6_S mask = 0000001111111111. */
1226#define UIMM10_6_S (UIMM3_23 + 1)
1227 {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
1228
1229 /* UIMM6_11_S mask = 0000002200011110. */
1230#define UIMM6_11_S (UIMM10_6_S + 1)
1231 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
1232
1233 /* SIMM9_8 mask = 00000000111111112000000000000000. */
1234#define SIMM9_8 (UIMM6_11_S + 1)
1235 {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
1236 insert_simm9_8, extract_simm9_8},
1237
1238 /* UIMM10_A32_8_S mask = 0000000011111111. */
1239#define UIMM10_A32_8_S (SIMM9_8 + 1)
1240 {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1241 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
1242 extract_uimm10_a32_8_s},
1243
1244 /* SIMM9_7_S mask = 0000000111111111. */
1245#define SIMM9_7_S (UIMM10_A32_8_S + 1)
1246 {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
1247 extract_simm9_7_s},
1248
1249 /* UIMM6_A16_11_S mask = 0000000000011111. */
1250#define UIMM6_A16_11_S (SIMM9_7_S + 1)
1251 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1252 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
1253 extract_uimm6_a16_11_s},
1254
1255 /* UIMM5_A32_11_S mask = 0000020000011000. */
1256#define UIMM5_A32_11_S (UIMM6_A16_11_S + 1)
1257 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1258 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
1259 extract_uimm5_a32_11_s},
1260
1261 /* SIMM11_A32_13_S mask = 0000022222200111. */
1262#define SIMM11_A32_13_S (UIMM5_A32_11_S + 1)
1263 {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1264 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
1265
1266 /* UIMM7_13_S mask = 0000000022220111. */
1267#define UIMM7_13_S (SIMM11_A32_13_S + 1)
1268 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
1269
1270 /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
1271#define UIMM6_A16_21 (UIMM7_13_S + 1)
1272 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1273 | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
1274
1275 /* UIMM7_11_S mask = 0000022200011110. */
1276#define UIMM7_11_S (UIMM6_A16_21 + 1)
1277 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
1278
1279 /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
1280#define UIMM7_A16_20 (UIMM7_11_S + 1)
1281 {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1282 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
1283 extract_uimm7_a16_20},
1284
1285 /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
1286#define SIMM13_A16_20 (UIMM7_A16_20 + 1)
1287 {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1288 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
1289 extract_simm13_a16_20},
1290
1291 /* UIMM8_8_S mask = 0000000011111111. */
1292#define UIMM8_8_S (SIMM13_A16_20 + 1)
1293 {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
1294
1295 /* W6 mask = 00000000000000000000111111000000. */
1296#define W6 (UIMM8_8_S + 1)
1297 {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
1298
1299 /* UIMM6_5_S mask = 0000011111100000. */
1300#define UIMM6_5_S (W6 + 1)
1301 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
e23e8ebe
AB		 1302
1303 /* ARC NPS400 Support: See comment near head of file. */
1304#define NPS_R_DST_3B (UIMM6_5_S + 1)
1305 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
1306
1307#define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
1308 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
1309
1310#define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
1311 { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_src2, extract_nps_3bit_src2 },
1312
1313#define NPS_R_DST (NPS_R_SRC2_3B + 1)
2cce10e7 1314 { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL },
e23e8ebe
AB		 1315
1316#define NPS_R_SRC1 (NPS_R_DST + 1)
2cce10e7 1317 { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
e23e8ebe
AB		 1318
1319#define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1)
1320 { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1321
1322#define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
1323 { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1324
1325#define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
1326 { 5, 10, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_size, extract_nps_bitop_size },
1327
1328#define NPS_UIMM16 (NPS_BITOP_SIZE + 1)
1329 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
886a2506 1330};
0d2bcfaf 1331
886a2506 1332const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
0d2bcfaf 1333
886a2506
NC		 1334const unsigned arc_Toperand = FKT_T;
1335const unsigned arc_NToperand = FKT_NT;
47b0e7ad 1336
886a2506 1337/* The opcode table.
0d2bcfaf 1338
886a2506 1339 The format of the opcode table is:
0d2bcfaf 1340
886a2506
NC		 1341 NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }. */
1342const struct arc_opcode arc_opcodes[] =
0d2bcfaf 1343{
886a2506 1344#include "arc-tbl.h"
e23e8ebe 1345#include "arc-nps400-tbl.h"
f2dd8838 1346#include "arc-ext-tbl.h"
886a2506 1347};
0d2bcfaf 1348
886a2506 1349const unsigned arc_num_opcodes = ARRAY_SIZE (arc_opcodes);
252b5132 1350
886a2506
NC		 1351/* List with special cases instructions and the applicable flags. */
1352const struct arc_flag_special arc_flag_special_cases[] =
252b5132 1353{
886a2506
NC		 1354 { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1355 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1356 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1357 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1358 { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1359 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1360 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1361 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1362 { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1363 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1364 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1365 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1366 { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1367 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1368 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1369 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1370 { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1371 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1372 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1373 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1374 { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1375 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1376 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1377 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1378 { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1379 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1380 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1381 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1382 { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
1383 { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
1384};
252b5132 1385
886a2506 1386const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
252b5132 1387
886a2506 1388/* Relocations. */
886a2506
NC		 1389const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
1390{
24b368f8
CZ		 1391 { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
1392 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1393 { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
1394 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1395 { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
1396 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1397 { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
1398 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1399
1400 /* Next two entries will cover the undefined behavior ldb/stb with
1401 address scaling. */
1402 { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
1403 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
1404 { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
1405 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
1406
1407 { "sda", "ld", { F_ASFAKE, F_NULL },
1408 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
1409 { "sda", "st", { F_ASFAKE, F_NULL },
1410 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
1411 { "sda", "ldd", { F_ASFAKE, F_NULL },
1412 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
1413 { "sda", "std", { F_ASFAKE, F_NULL },
1414 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
886a2506
NC		 1415
1416 /* Short instructions. */
24b368f8
CZ		 1417 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
1418 { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
1419 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
1420 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
1421
1422 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
1423 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
1424
1425 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
1426 BFD_RELOC_ARC_S25H_PCREL_PLT },
1427 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
1428 BFD_RELOC_ARC_S21H_PCREL_PLT },
1429 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
1430 BFD_RELOC_ARC_S25W_PCREL_PLT },
1431 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
1432 BFD_RELOC_ARC_S21W_PCREL_PLT },
1433
1434 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
886a2506 1435};
252b5132 1436
886a2506 1437const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
252b5132 1438
886a2506 1439const struct arc_pseudo_insn arc_pseudo_insns[] =
0d2bcfaf 1440{
886a2506
NC		 1441 { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
1442 { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
1443 { BRAKETdup, 1, 0, 4} } },
1444 { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
1445 { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
1446 { BRAKETdup, 1, 0, 4} } },
1447
1448 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1449 { SIMM9_A16_8, 0, 0, 2 } } },
1450 { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1451 { SIMM9_A16_8, 0, 0, 2 } } },
1452 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1453 { SIMM9_A16_8, 0, 0, 2 } } },
1454 { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1455 { SIMM9_A16_8, 0, 0, 2 } } },
1456 { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1457 { SIMM9_A16_8, 0, 0, 2 } } },
1458
1459 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1460 { SIMM9_A16_8, 0, 0, 2 } } },
1461 { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1462 { SIMM9_A16_8, 0, 0, 2 } } },
1463 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1464 { SIMM9_A16_8, 0, 0, 2 } } },
1465 { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1466 { SIMM9_A16_8, 0, 0, 2 } } },
1467 { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1468 { SIMM9_A16_8, 0, 0, 2 } } },
1469
1470 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1471 { SIMM9_A16_8, 0, 0, 2 } } },
1472 { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1473 { SIMM9_A16_8, 0, 0, 2 } } },
1474 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1475 { SIMM9_A16_8, 0, 0, 2 } } },
1476 { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1477 { SIMM9_A16_8, 0, 0, 2 } } },
1478 { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1479 { SIMM9_A16_8, 0, 0, 2 } } },
1480
1481 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1482 { SIMM9_A16_8, 0, 0, 2 } } },
1483 { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1484 { SIMM9_A16_8, 0, 0, 2 } } },
1485 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1486 { SIMM9_A16_8, 0, 0, 2 } } },
1487 { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1488 { SIMM9_A16_8, 0, 0, 2 } } },
1489 { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1490 { SIMM9_A16_8, 0, 0, 2 } } },
1491};
0d2bcfaf 1492
886a2506
NC		 1493const unsigned arc_num_pseudo_insn =
1494 sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
0d2bcfaf 1495
886a2506 1496const struct arc_aux_reg arc_aux_regs[] =
0d2bcfaf 1497{
886a2506
NC		 1498#undef DEF
1499#define DEF(ADDR, NAME) \
1500 { ADDR, #NAME, sizeof (#NAME)-1 },
0d2bcfaf 1501
886a2506 1502#include "arc-regs.h"
0d2bcfaf 1503
886a2506
NC		 1504#undef DEF
1505};
0d2bcfaf 1506
886a2506 1507const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
4670103e
CZ		 1508
1509/* NOTE: The order of this array MUST be consistent with 'enum
1510 arc_rlx_types' located in tc-arc.h! */
1511const struct arc_opcode arc_relax_opcodes[] =
1512{
1513 { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
1514
1515 /* bl_s s13 11111sssssssssss. */
1516 { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1517 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1518 { SIMM13_A32_5_S }, { 0 }},
1519
1520 /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
1521 { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1522 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1523 { SIMM25_A32_5 }, { C_D }},
1524
1525 /* b_s s10 1111000sssssssss. */
1526 { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1527 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1528 { SIMM10_A16_7_S }, { 0 }},
1529
1530 /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
1531 { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1532 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1533 { SIMM25_A16_5 }, { C_D }},
1534
1535 /* add_s c,b,u3 01101bbbccc00uuu. Wants UIMM3_13_S_PCREL. */
1536 { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1537 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1538 { RC_S, RB_S, UIMM3_13_S }, { 0 }},
1539
1540 /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. Wants
1541 UIMM6_20_PCREL. */
1542 { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1543 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1544 { RA, RB, UIMM6_20 }, { C_F }},
1545
1546 /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
1547 { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1548 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1549 { RA, RB, LIMM }, { C_F }},
1550
1551 /* ld_s c,b,u7 10000bbbcccuuuuu. Wants UIMM7_A32_11_S_PCREL. */
1552 { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1553 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1554 { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
1555
1556 /* ld<.di><.aa><.x><zz> a,b,s9
1557 00010bbbssssssssSBBBDaaZZXAAAAAA. Wants SIMM9_8_PCREL. */
1558 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1559 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1560 { RA, BRAKET, RB, SIMM9_8, BRAKETdup },
1561 { C_ZZ23, C_DI20, C_AA21, C_X25 }},
1562
1563 /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
1564 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1565 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1566 { RA, BRAKET, RB, LIMM, BRAKETdup },
1567 { C_ZZ13, C_DI16, C_AA8, C_X15 }},
1568
1569 /* mov_s b,u8 11011bbbuuuuuuuu. Wants UIMM8_8_S_PCREL. */
1570 { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1571 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1572 { RB_S, UIMM8_8_S }, { 0 }},
1573
1574 /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. Wants
1575 SIMM12_20_PCREL. */
1576 { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1577 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1578 { RB, SIMM12_20 }, { C_F }},
1579
1580 /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
1581 { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1582 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1583 { RB, LIMM }, { C_F }},
1584
1585 /* sub_s c,b,u3 01101bbbccc01uuu. UIMM3_13_S_PCREL. */
1586 { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1587 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1588 { RC_S, RB_S, UIMM3_13_S }, { 0 }},
1589
1590 /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA.
1591 UIMM6_20_PCREL. */
1592 { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1593 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1594 { RA, RB, UIMM6_20 }, { C_F }},
1595
1596 /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
1597 { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1598 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1599 { RA, RB, LIMM }, { C_F }},
1600
1601 /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA.
1602 UIMM6_20_PCREL. */
1603 { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
1604 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }},
1605
1606 /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
1607 { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
1608 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
1609
1610 /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ.
1611 UIMM6_20_PCREL. */
1612 { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1613 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1614 { RB, UIMM6_20 }, { C_F, C_CC }},
1615
1616 /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
1617 { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1618 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1619 { RB, LIMM }, { C_F, C_CC }},
1620
1621 /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ.
1622 UIMM6_20_PCREL. */
1623 { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1624 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1625 { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
1626
1627 /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
1628 { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1629 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1630 { RB, RBdup, LIMM }, { C_F, C_CC }}
1631};
1632
1633const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);
GDB Binutils - Deliverables
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