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[BZ 21005] Add support for Intel 64 rdrand and rdseed record/replay
[deliverable/binutils-gdb.git] / opcodes / arc-opc.c
CommitLineData
252b5132 1/* Opcode table for the ARC.
2571583a 2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
bcee8eb8 5
9b201bb5
NC		 6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
252b5132 9 it under the terms of the GNU General Public License as published by
9b201bb5 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132
RH		 17
18 You should have received a copy of the GNU General Public License
0d2bcfaf 19 along with this program; if not, write to the Free Software Foundation,
f4321104 20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
252b5132 21
5bd67f35 22#include "sysdep.h"
252b5132 23#include <stdio.h>
d943fe33 24#include "bfd.h"
252b5132 25#include "opcode/arc.h"
47b0e7ad 26#include "opintl.h"
886a2506 27#include "libiberty.h"
252b5132 28
e23e8ebe 29/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
ce440d63 30 instructions. All NPS400 features are built into all ARC target builds as
e23e8ebe
AB		 31 this reduces the chances that regressions might creep in. */
32
abe7c33b
CZ		 33/* Insert RA register into a 32-bit opcode, with checks. */
34static unsigned long long
35insert_ra_chk (unsigned long long insn,
36 long long int value,
37 const char **errmsg ATTRIBUTE_UNUSED)
38{
39 if (value == 60)
40 *errmsg = _("LP_COUNT register cannot be used as destination register");
41
42 return insn | (value & 0x3F);
43}
886a2506 44/* Insert RB register into a 32-bit opcode. */
bdfe53e3
AB		 45static unsigned long long
46insert_rb (unsigned long long insn,
47 long long int value,
886a2506 48 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 49{
886a2506
NC		 50 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
51}
0d2bcfaf 52
abe7c33b
CZ		 53/* Insert RB register with checks. */
54static unsigned long long
55insert_rb_chk (unsigned long long insn,
56 long long int value,
57 const char **errmsg ATTRIBUTE_UNUSED)
58{
59 if (value == 60)
60 *errmsg = _("LP_COUNT register cannot be used as destination register");
61
62 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
63}
64
bdfe53e3
AB		 65static long long int
66extract_rb (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506
NC		 67 bfd_boolean * invalid ATTRIBUTE_UNUSED)
68{
69 int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
0d2bcfaf 70
886a2506
NC		 71 if (value == 0x3e && invalid)
72 *invalid = TRUE; /* A limm operand, it should be extracted in a
73 different way. */
252b5132 74
886a2506
NC		 75 return value;
76}
252b5132 77
bdfe53e3
AB		 78static unsigned long long
79insert_rad (unsigned long long insn,
80 long long int value,
886a2506
NC		 81 const char **errmsg ATTRIBUTE_UNUSED)
82{
83 if (value & 0x01)
abe7c33b
CZ		 84 *errmsg = _("cannot use odd number destination register");
85 if (value == 60)
86 *errmsg = _("LP_COUNT register cannot be used as destination register");
0d2bcfaf 87
886a2506
NC		 88 return insn | (value & 0x3F);
89}
0d2bcfaf 90
bdfe53e3
AB		 91static unsigned long long
92insert_rcd (unsigned long long insn,
93 long long int value,
886a2506
NC		 94 const char **errmsg ATTRIBUTE_UNUSED)
95{
96 if (value & 0x01)
abe7c33b 97 *errmsg = _("cannot use odd number source register");
0d2bcfaf 98
886a2506
NC		 99 return insn | ((value & 0x3F) << 6);
100}
252b5132 101
886a2506 102/* Dummy insert ZERO operand function. */
252b5132 103
bdfe53e3
AB		 104static unsigned long long
105insert_za (unsigned long long insn,
106 long long int value,
886a2506
NC		 107 const char **errmsg)
108{
109 if (value)
110 *errmsg = _("operand is not zero");
111 return insn;
112}
252b5132 113
886a2506
NC		 114/* Insert Y-bit in bbit/br instructions. This function is called only
115 when solving fixups. */
252b5132 116
bdfe53e3
AB		 117static unsigned long long
118insert_Ybit (unsigned long long insn,
119 long long int value,
886a2506
NC		 120 const char **errmsg ATTRIBUTE_UNUSED)
121{
122 if (value > 0)
123 insn |= 0x08;
252b5132 124
886a2506
NC		 125 return insn;
126}
252b5132 127
886a2506
NC		 128/* Insert Y-bit in bbit/br instructions. This function is called only
129 when solving fixups. */
252b5132 130
bdfe53e3
AB		 131static unsigned long long
132insert_NYbit (unsigned long long insn,
133 long long int value,
886a2506
NC		 134 const char **errmsg ATTRIBUTE_UNUSED)
135{
136 if (value < 0)
137 insn |= 0x08;
0d2bcfaf 138
886a2506
NC		 139 return insn;
140}
252b5132 141
886a2506 142/* Insert H register into a 16-bit opcode. */
252b5132 143
bdfe53e3
AB		 144static unsigned long long
145insert_rhv1 (unsigned long long insn,
146 long long int value,
886a2506
NC		 147 const char **errmsg ATTRIBUTE_UNUSED)
148{
149 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
150}
252b5132 151
bdfe53e3
AB		 152static long long int
153extract_rhv1 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506
NC		 154 bfd_boolean * invalid ATTRIBUTE_UNUSED)
155{
02f3be19 156 int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7);
252b5132 157
886a2506
NC		 158 return value;
159}
252b5132 160
886a2506 161/* Insert H register into a 16-bit opcode. */
252b5132 162
bdfe53e3
AB		 163static unsigned long long
164insert_rhv2 (unsigned long long insn,
165 long long int value,
886a2506 166 const char **errmsg)
0d2bcfaf 167{
886a2506
NC		 168 if (value == 0x1E)
169 *errmsg =
abe7c33b 170 _("Register R30 is a limm indicator");
886a2506
NC		 171 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
172}
252b5132 173
bdfe53e3
AB		 174static long long int
175extract_rhv2 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506
NC		 176 bfd_boolean * invalid ATTRIBUTE_UNUSED)
177{
178 int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
0d2bcfaf 179
886a2506
NC		 180 return value;
181}
0d2bcfaf 182
bdfe53e3
AB		 183static unsigned long long
184insert_r0 (unsigned long long insn,
185 long long int value,
886a2506
NC		 186 const char **errmsg ATTRIBUTE_UNUSED)
187{
188 if (value != 0)
abe7c33b 189 *errmsg = _("Register must be R0");
47b0e7ad
NC		 190 return insn;
191}
252b5132 192
bdfe53e3
AB		 193static long long int
194extract_r0 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 195 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 196{
886a2506 197 return 0;
47b0e7ad 198}
252b5132 199
252b5132 200
bdfe53e3
AB		 201static unsigned long long
202insert_r1 (unsigned long long insn,
203 long long int value,
886a2506 204 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 205{
886a2506 206 if (value != 1)
abe7c33b 207 *errmsg = _("Register must be R1");
47b0e7ad 208 return insn;
252b5132
RH		 209}
210
bdfe53e3
AB		 211static long long int
212extract_r1 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 213 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 214{
886a2506 215 return 1;
252b5132
RH		 216}
217
bdfe53e3
AB		 218static unsigned long long
219insert_r2 (unsigned long long insn,
220 long long int value,
886a2506 221 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 222{
886a2506 223 if (value != 2)
abe7c33b 224 *errmsg = _("Register must be R2");
47b0e7ad 225 return insn;
252b5132
RH		 226}
227
bdfe53e3
AB		 228static long long int
229extract_r2 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 230 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 231{
886a2506 232 return 2;
252b5132
RH		 233}
234
bdfe53e3
AB		 235static unsigned long long
236insert_r3 (unsigned long long insn,
237 long long int value,
886a2506 238 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 239{
886a2506 240 if (value != 3)
abe7c33b 241 *errmsg = _("Register must be R3");
47b0e7ad 242 return insn;
0d2bcfaf
NC		 243}
244
bdfe53e3
AB		 245static long long int
246extract_r3 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 247 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 248{
886a2506 249 return 3;
0d2bcfaf
NC		 250}
251
bdfe53e3
AB		 252static unsigned long long
253insert_sp (unsigned long long insn,
254 long long int value,
886a2506 255 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 256{
886a2506 257 if (value != 28)
abe7c33b 258 *errmsg = _("Register must be SP");
252b5132
RH		 259 return insn;
260}
261
bdfe53e3
AB		 262static long long int
263extract_sp (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 264 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 265{
886a2506 266 return 28;
0d2bcfaf
NC		 267}
268
bdfe53e3
AB		 269static unsigned long long
270insert_gp (unsigned long long insn,
271 long long int value,
886a2506 272 const char **errmsg ATTRIBUTE_UNUSED)
0d2bcfaf 273{
886a2506 274 if (value != 26)
abe7c33b 275 *errmsg = _("Register must be GP");
886a2506 276 return insn;
0d2bcfaf
NC		 277}
278
bdfe53e3
AB		 279static long long int
280extract_gp (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 281 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 282{
886a2506 283 return 26;
0d2bcfaf
NC		 284}
285
bdfe53e3
AB		 286static unsigned long long
287insert_pcl (unsigned long long insn,
288 long long int value,
886a2506 289 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 290{
886a2506 291 if (value != 63)
abe7c33b 292 *errmsg = _("Register must be PCL");
252b5132
RH		 293 return insn;
294}
295
bdfe53e3
AB		 296static long long int
297extract_pcl (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 298 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 299{
886a2506 300 return 63;
0d2bcfaf
NC		 301}
302
bdfe53e3
AB		 303static unsigned long long
304insert_blink (unsigned long long insn,
305 long long int value,
886a2506 306 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 307{
886a2506 308 if (value != 31)
abe7c33b 309 *errmsg = _("Register must be BLINK");
252b5132
RH		 310 return insn;
311}
312
bdfe53e3
AB		 313static long long int
314extract_blink (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 315 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 316{
886a2506 317 return 31;
0d2bcfaf
NC		 318}
319
bdfe53e3
AB		 320static unsigned long long
321insert_ilink1 (unsigned long long insn,
322 long long int value,
886a2506 323 const char **errmsg ATTRIBUTE_UNUSED)
0d2bcfaf 324{
886a2506 325 if (value != 29)
abe7c33b 326 *errmsg = _("Register must be ILINK1");
252b5132
RH		 327 return insn;
328}
329
bdfe53e3
AB		 330static long long int
331extract_ilink1 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 332 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 333{
886a2506 334 return 29;
252b5132
RH		 335}
336
bdfe53e3
AB		 337static unsigned long long
338insert_ilink2 (unsigned long long insn,
339 long long int value,
886a2506 340 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 341{
886a2506 342 if (value != 30)
abe7c33b 343 *errmsg = _("Register must be ILINK2");
252b5132
RH		 344 return insn;
345}
346
bdfe53e3
AB		 347static long long int
348extract_ilink2 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506
NC		 349 bfd_boolean * invalid ATTRIBUTE_UNUSED)
350{
351 return 30;
352}
252b5132 353
bdfe53e3
AB		 354static unsigned long long
355insert_ras (unsigned long long insn,
356 long long int value,
886a2506 357 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 358{
886a2506 359 switch (value)
0d2bcfaf 360 {
886a2506
NC		 361 case 0:
362 case 1:
363 case 2:
364 case 3:
365 insn |= value;
366 break;
367 case 12:
368 case 13:
369 case 14:
370 case 15:
371 insn |= (value - 8);
372 break;
373 default:
abe7c33b 374 *errmsg = _("Register must be either r0-r3 or r12-r15");
886a2506 375 break;
0d2bcfaf 376 }
252b5132
RH		 377 return insn;
378}
252b5132 379
bdfe53e3
AB		 380static long long int
381extract_ras (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 382 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 383{
886a2506
NC		 384 int value = insn & 0x07;
385 if (value > 3)
386 return (value + 8);
387 else
388 return value;
47b0e7ad
NC		 389}
390
bdfe53e3
AB		 391static unsigned long long
392insert_rbs (unsigned long long insn,
393 long long int value,
886a2506 394 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 395{
886a2506 396 switch (value)
47b0e7ad 397 {
886a2506
NC		 398 case 0:
399 case 1:
400 case 2:
401 case 3:
402 insn |= value << 8;
403 break;
404 case 12:
405 case 13:
406 case 14:
407 case 15:
408 insn |= ((value - 8)) << 8;
409 break;
410 default:
abe7c33b 411 *errmsg = _("Register must be either r0-r3 or r12-r15");
886a2506 412 break;
47b0e7ad 413 }
886a2506 414 return insn;
252b5132
RH		 415}
416
bdfe53e3
AB		 417static long long int
418extract_rbs (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 419 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 420{
886a2506
NC		 421 int value = (insn >> 8) & 0x07;
422 if (value > 3)
423 return (value + 8);
424 else
425 return value;
426}
252b5132 427
bdfe53e3
AB		 428static unsigned long long
429insert_rcs (unsigned long long insn,
430 long long int value,
886a2506
NC		 431 const char **errmsg ATTRIBUTE_UNUSED)
432{
433 switch (value)
252b5132 434 {
886a2506
NC		 435 case 0:
436 case 1:
437 case 2:
438 case 3:
439 insn |= value << 5;
440 break;
441 case 12:
442 case 13:
443 case 14:
444 case 15:
445 insn |= ((value - 8)) << 5;
446 break;
447 default:
abe7c33b 448 *errmsg = _("Register must be either r0-r3 or r12-r15");
886a2506 449 break;
252b5132 450 }
886a2506
NC		 451 return insn;
452}
47b0e7ad 453
bdfe53e3
AB		 454static long long int
455extract_rcs (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506
NC		 456 bfd_boolean * invalid ATTRIBUTE_UNUSED)
457{
458 int value = (insn >> 5) & 0x07;
459 if (value > 3)
460 return (value + 8);
252b5132 461 else
886a2506
NC		 462 return value;
463}
47b0e7ad 464
bdfe53e3
AB		 465static unsigned long long
466insert_simm3s (unsigned long long insn,
467 long long int value,
886a2506
NC		 468 const char **errmsg ATTRIBUTE_UNUSED)
469{
470 int tmp = 0;
471 switch (value)
47b0e7ad 472 {
886a2506
NC		 473 case -1:
474 tmp = 0x07;
47b0e7ad 475 break;
886a2506
NC		 476 case 0:
477 tmp = 0x00;
478 break;
479 case 1:
480 tmp = 0x01;
47b0e7ad 481 break;
886a2506
NC		 482 case 2:
483 tmp = 0x02;
47b0e7ad 484 break;
886a2506
NC		 485 case 3:
486 tmp = 0x03;
487 break;
488 case 4:
489 tmp = 0x04;
490 break;
491 case 5:
492 tmp = 0x05;
493 break;
494 case 6:
495 tmp = 0x06;
496 break;
497 default:
abe7c33b 498 *errmsg = _("Accepted values are from -1 to 6");
47b0e7ad
NC		 499 break;
500 }
501
886a2506
NC		 502 insn |= tmp << 8;
503 return insn;
47b0e7ad
NC		 504}
505
bdfe53e3
AB		 506static long long int
507extract_simm3s (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 508 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 509{
886a2506
NC		 510 int value = (insn >> 8) & 0x07;
511 if (value == 7)
512 return -1;
47b0e7ad 513 else
886a2506 514 return value;
47b0e7ad
NC		 515}
516
bdfe53e3
AB		 517static unsigned long long
518insert_rrange (unsigned long long insn,
519 long long int value,
886a2506 520 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 521{
886a2506
NC		 522 int reg1 = (value >> 16) & 0xFFFF;
523 int reg2 = value & 0xFFFF;
524 if (reg1 != 13)
525 {
abe7c33b 526 *errmsg = _("First register of the range should be r13");
886a2506
NC		 527 return insn;
528 }
529 if (reg2 < 13 || reg2 > 26)
530 {
abe7c33b 531 *errmsg = _("Last register of the range doesn't fit");
886a2506
NC		 532 return insn;
533 }
534 insn |= ((reg2 - 12) & 0x0F) << 1;
535 return insn;
47b0e7ad
NC		 536}
537
bdfe53e3
AB		 538static long long int
539extract_rrange (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506
NC		 540 bfd_boolean * invalid ATTRIBUTE_UNUSED)
541{
542 return (insn >> 1) & 0x0F;
543}
47b0e7ad 544
bdfe53e3
AB		 545static unsigned long long
546insert_fpel (unsigned long long insn,
547 long long int value,
886a2506 548 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 549{
886a2506
NC		 550 if (value != 27)
551 {
abe7c33b 552 *errmsg = _("Invalid register number, should be fp");
886a2506
NC		 553 return insn;
554 }
47b0e7ad 555
886a2506
NC		 556 insn |= 0x0100;
557 return insn;
47b0e7ad
NC		 558}
559
bdfe53e3
AB		 560static long long int
561extract_fpel (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 562 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 563{
886a2506 564 return (insn & 0x0100) ? 27 : -1;
47b0e7ad
NC		 565}
566
bdfe53e3
AB		 567static unsigned long long
568insert_blinkel (unsigned long long insn,
569 long long int value,
886a2506 570 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 571{
886a2506 572 if (value != 31)
47b0e7ad 573 {
abe7c33b 574 *errmsg = _("Invalid register number, should be blink");
886a2506 575 return insn;
47b0e7ad 576 }
47b0e7ad 577
886a2506
NC		 578 insn |= 0x0200;
579 return insn;
47b0e7ad
NC		 580}
581
bdfe53e3
AB		 582static long long int
583extract_blinkel (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 584 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 585{
886a2506
NC		 586 return (insn & 0x0200) ? 31 : -1;
587}
47b0e7ad 588
bdfe53e3
AB		 589static unsigned long long
590insert_pclel (unsigned long long insn,
591 long long int value,
886a2506
NC		 592 const char **errmsg ATTRIBUTE_UNUSED)
593{
594 if (value != 63)
47b0e7ad 595 {
abe7c33b 596 *errmsg = _("Invalid register number, should be pcl");
886a2506 597 return insn;
47b0e7ad 598 }
47b0e7ad 599
886a2506
NC		 600 insn |= 0x0400;
601 return insn;
602}
47b0e7ad 603
bdfe53e3
AB		 604static long long int
605extract_pclel (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 606 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 607{
886a2506 608 return (insn & 0x0400) ? 63 : -1;
47b0e7ad 609}
47b0e7ad 610
886a2506
NC		 611#define INSERT_W6
612/* mask = 00000000000000000000111111000000
613 insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
bdfe53e3
AB		 614static unsigned long long
615insert_w6 (unsigned long long insn ATTRIBUTE_UNUSED,
616 long long int value ATTRIBUTE_UNUSED,
886a2506 617 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 618{
886a2506 619 insn |= ((value >> 0) & 0x003f) << 6;
47b0e7ad 620
886a2506
NC		 621 return insn;
622}
47b0e7ad 623
886a2506
NC		 624#define EXTRACT_W6
625/* mask = 00000000000000000000111111000000. */
bdfe53e3
AB		 626static long long int
627extract_w6 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 628 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 629{
886a2506 630 unsigned value = 0;
47b0e7ad 631
886a2506 632 value |= ((insn >> 6) & 0x003f) << 0;
47b0e7ad 633
886a2506
NC		 634 return value;
635}
47b0e7ad 636
886a2506
NC		 637#define INSERT_G_S
638/* mask = 0000011100022000
639 insn = 01000ggghhhGG0HH. */
bdfe53e3
AB		 640static unsigned long long
641insert_g_s (unsigned long long insn ATTRIBUTE_UNUSED,
642 long long int value ATTRIBUTE_UNUSED,
886a2506 643 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 644{
886a2506
NC		 645 insn |= ((value >> 0) & 0x0007) << 8;
646 insn |= ((value >> 3) & 0x0003) << 3;
252b5132 647
886a2506
NC		 648 return insn;
649}
252b5132 650
886a2506
NC		 651#define EXTRACT_G_S
652/* mask = 0000011100022000. */
bdfe53e3
AB		 653static long long int
654extract_g_s (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506
NC		 655 bfd_boolean * invalid ATTRIBUTE_UNUSED)
656{
657 int value = 0;
252b5132 658
886a2506
NC		 659 value |= ((insn >> 8) & 0x0007) << 0;
660 value |= ((insn >> 3) & 0x0003) << 3;
252b5132 661
886a2506
NC		 662 /* Extend the sign. */
663 int signbit = 1 << (6 - 1);
664 value = (value ^ signbit) - signbit;
252b5132 665
886a2506 666 return value;
252b5132
RH		 667}
668
e23e8ebe 669/* ARC NPS400 Support: See comment near head of file. */
bdfe53e3
AB		 670#define MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(NAME,OFFSET) \
671static unsigned long long \
672insert_nps_3bit_reg_at_##OFFSET##_##NAME \
673 (unsigned long long insn ATTRIBUTE_UNUSED, \
674 long long int value ATTRIBUTE_UNUSED, \
675 const char **errmsg ATTRIBUTE_UNUSED) \
676{ \
677 switch (value) \
678 { \
679 case 0: \
680 case 1: \
681 case 2: \
682 case 3: \
683 insn |= value << (OFFSET); \
684 break; \
685 case 12: \
686 case 13: \
687 case 14: \
688 case 15: \
689 insn |= (value - 8) << (OFFSET); \
690 break; \
691 default: \
abe7c33b 692 *errmsg = _("Register must be either r0-r3 or r12-r15"); \
bdfe53e3
AB		 693 break; \
694 } \
695 return insn; \
696} \
697 \
698static long long int \
699extract_nps_3bit_reg_at_##OFFSET##_##NAME \
700 (unsigned long long insn ATTRIBUTE_UNUSED, \
701 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
702{ \
703 int value = (insn >> (OFFSET)) & 0x07; \
704 if (value > 3) \
705 value += 8; \
706 return value; \
707} \
708
709MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,8)
710MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,24)
711MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,40)
712MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,56)
713
714MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,5)
715MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,21)
716MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,37)
717MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,53)
718
719static unsigned long long
720insert_nps_bitop_size_2b (unsigned long long insn ATTRIBUTE_UNUSED,
721 long long int value ATTRIBUTE_UNUSED,
820f03ff
AB		 722 const char **errmsg ATTRIBUTE_UNUSED)
723{
724 switch (value)
725 {
726 case 1:
727 value = 0;
728 break;
729 case 2:
730 value = 1;
731 break;
732 case 4:
733 value = 2;
734 break;
735 case 8:
736 value = 3;
737 break;
738 default:
739 value = 0;
abe7c33b 740 *errmsg = _("Invalid size, should be 1, 2, 4, or 8");
820f03ff
AB		 741 break;
742 }
743
744 insn |= value << 10;
745 return insn;
746}
747
bdfe53e3
AB		 748static long long int
749extract_nps_bitop_size_2b (unsigned long long insn ATTRIBUTE_UNUSED,
820f03ff
AB		 750 bfd_boolean * invalid ATTRIBUTE_UNUSED)
751{
752 return 1 << ((insn >> 10) & 0x3);
753}
754
bdfe53e3
AB		 755static unsigned long long
756insert_nps_bitop_uimm8 (unsigned long long insn ATTRIBUTE_UNUSED,
757 long long int value ATTRIBUTE_UNUSED,
820f03ff
AB		 758 const char **errmsg ATTRIBUTE_UNUSED)
759{
760 insn |= ((value >> 5) & 7) << 12;
761 insn |= (value & 0x1f);
762 return insn;
763}
764
bdfe53e3
AB		 765static long long int
766extract_nps_bitop_uimm8 (unsigned long long insn ATTRIBUTE_UNUSED,
820f03ff
AB		 767 bfd_boolean * invalid ATTRIBUTE_UNUSED)
768{
769 return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
770}
771
bdfe53e3
AB		 772static unsigned long long
773insert_nps_rflt_uimm6 (unsigned long long insn ATTRIBUTE_UNUSED,
774 long long int value ATTRIBUTE_UNUSED,
820f03ff
AB		 775 const char **errmsg ATTRIBUTE_UNUSED)
776{
777 switch (value)
778 {
779 case 1:
780 case 2:
781 case 4:
782 break;
783
784 default:
785 *errmsg = _("invalid immediate, must be 1, 2, or 4");
786 value = 0;
787 }
788
789 insn |= (value << 6);
790 return insn;
791}
792
bdfe53e3
AB		 793static long long int
794extract_nps_rflt_uimm6 (unsigned long long insn ATTRIBUTE_UNUSED,
820f03ff
AB		 795 bfd_boolean * invalid ATTRIBUTE_UNUSED)
796{
797 return (insn >> 6) & 0x3f;
798}
799
bdfe53e3
AB		 800static unsigned long long
801insert_nps_dst_pos_and_size (unsigned long long insn ATTRIBUTE_UNUSED,
802 long long int value ATTRIBUTE_UNUSED,
820f03ff
AB		 803 const char **errmsg ATTRIBUTE_UNUSED)
804{
805 insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10));
806 return insn;
807}
808
bdfe53e3
AB		 809static long long int
810extract_nps_dst_pos_and_size (unsigned long long insn ATTRIBUTE_UNUSED,
820f03ff
AB		 811 bfd_boolean * invalid ATTRIBUTE_UNUSED)
812{
813 return (insn & 0x1f);
814}
815
bdfe53e3
AB		 816static unsigned long long
817insert_nps_cmem_uimm16 (unsigned long long insn ATTRIBUTE_UNUSED,
818 long long int value ATTRIBUTE_UNUSED,
4b0c052e
AB		 819 const char **errmsg ATTRIBUTE_UNUSED)
820{
821 int top = (value >> 16) & 0xffff;
822 if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE)
823 *errmsg = _("invalid value for CMEM ld/st immediate");
824 insn |= (value & 0xffff);
825 return insn;
826}
827
bdfe53e3
AB		 828static long long int
829extract_nps_cmem_uimm16 (unsigned long long insn ATTRIBUTE_UNUSED,
4b0c052e
AB		 830 bfd_boolean * invalid ATTRIBUTE_UNUSED)
831{
832 return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff);
833}
834
537aefaf 835#define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \
bdfe53e3
AB		 836static unsigned long long \
837insert_nps_##NAME##_pos (unsigned long long insn ATTRIBUTE_UNUSED, \
838 long long int value ATTRIBUTE_UNUSED, \
537aefaf
AB		 839 const char **errmsg ATTRIBUTE_UNUSED) \
840{ \
841 switch (value) \
842 { \
843 case 0: \
844 case 8: \
845 case 16: \
846 case 24: \
847 value = value / 8; \
848 break; \
849 default: \
abe7c33b 850 *errmsg = _("Invalid position, should be 0, 8, 16, or 24"); \
537aefaf
AB		 851 value = 0; \
852 } \
853 insn |= (value << SHIFT); \
854 return insn; \
855} \
856 \
bdfe53e3
AB		 857static long long int \
858extract_nps_##NAME##_pos (unsigned long long insn ATTRIBUTE_UNUSED, \
537aefaf
AB		 859 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
860{ \
861 return ((insn >> SHIFT) & 0x3) * 8; \
862}
863
864MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12)
865MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10)
866
9ba75c88 867#define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT)\
bdfe53e3
AB		 868static unsigned long long \
869insert_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
870 long long int value ATTRIBUTE_UNUSED, \
9ba75c88 871 const char **errmsg ATTRIBUTE_UNUSED) \
537aefaf 872 { \
9ba75c88 873 if (value < LOWER || value > UPPER) \
537aefaf
AB		 874 { \
875 *errmsg = _("Invalid size, value must be " \
876 #LOWER " to " #UPPER "."); \
877 return insn; \
878 } \
879 value -= BIAS; \
880 insn |= (value << SHIFT); \
881 return insn; \
882 } \
883 \
bdfe53e3
AB		 884static long long int \
885extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
9ba75c88 886 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
537aefaf
AB		 887{ \
888 return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \
889}
890
db18dbab
GM		 891MAKE_BIAS_INSERT_EXTRACT_FUNCS (addb_size,2,32,5,1,5)
892MAKE_BIAS_INSERT_EXTRACT_FUNCS (andb_size,1,32,5,1,5)
893MAKE_BIAS_INSERT_EXTRACT_FUNCS (fxorb_size,8,32,5,8,5)
894MAKE_BIAS_INSERT_EXTRACT_FUNCS (wxorb_size,16,32,5,16,5)
895MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop_size,1,32,5,1,10)
896MAKE_BIAS_INSERT_EXTRACT_FUNCS (qcmp_size,1,8,3,1,9)
897MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop1_size,1,32,5,1,20)
898MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop2_size,1,32,5,1,25)
899MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_width,1,32,5,1,6)
900MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_len,1,8,3,1,2)
901MAKE_BIAS_INSERT_EXTRACT_FUNCS (index3,4,7,2,4,0)
537aefaf 902
bdfe53e3
AB		 903static long long int
904extract_nps_qcmp_m3 (unsigned long long insn ATTRIBUTE_UNUSED,
537aefaf
AB		 905 bfd_boolean * invalid ATTRIBUTE_UNUSED)
906{
907 int m3 = (insn >> 5) & 0xf;
908 if (m3 == 0xf)
909 *invalid = TRUE;
910 return m3;
911}
912
bdfe53e3
AB		 913static long long int
914extract_nps_qcmp_m2 (unsigned long long insn ATTRIBUTE_UNUSED,
537aefaf
AB		 915 bfd_boolean * invalid ATTRIBUTE_UNUSED)
916{
917 bfd_boolean tmp_invalid = FALSE;
918 int m2 = (insn >> 15) & 0x1;
919 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
920
921 if (m2 == 0 && m3 == 0xf)
922 *invalid = TRUE;
923 return m2;
924}
925
bdfe53e3
AB		 926static long long int
927extract_nps_qcmp_m1 (unsigned long long insn ATTRIBUTE_UNUSED,
537aefaf
AB		 928 bfd_boolean * invalid ATTRIBUTE_UNUSED)
929{
930 bfd_boolean tmp_invalid = FALSE;
931 int m1 = (insn >> 14) & 0x1;
932 int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid);
933 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
934
935 if (m1 == 0 && m2 == 0 && m3 == 0xf)
936 *invalid = TRUE;
937 return m1;
938}
939
bdfe53e3
AB		 940static unsigned long long
941insert_nps_calc_entry_size (unsigned long long insn ATTRIBUTE_UNUSED,
942 long long int value ATTRIBUTE_UNUSED,
537aefaf
AB		 943 const char **errmsg ATTRIBUTE_UNUSED)
944{
945 unsigned pwr;
946
947 if (value < 1 || value > 256)
948 {
949 *errmsg = _("value out of range 1 - 256");
950 return 0;
951 }
952
953 for (pwr = 0; (value & 1) == 0; value >>= 1)
954 ++pwr;
955
956 if (value != 1)
957 {
958 *errmsg = _("value must be power of 2");
959 return 0;
960 }
961
962 return insn | (pwr << 8);
963}
964
bdfe53e3
AB		 965static long long int
966extract_nps_calc_entry_size (unsigned long long insn ATTRIBUTE_UNUSED,
537aefaf
AB		 967 bfd_boolean * invalid ATTRIBUTE_UNUSED)
968{
969 unsigned entry_size = (insn >> 8) & 0xf;
970 return 1 << entry_size;
971}
972
bdfe53e3
AB		 973static unsigned long long
974insert_nps_bitop_mod4 (unsigned long long insn ATTRIBUTE_UNUSED,
975 long long int value ATTRIBUTE_UNUSED,
4eb6f892
AB		 976 const char **errmsg ATTRIBUTE_UNUSED)
977{
bdfe53e3 978 return insn | ((value & 0x2) << 30) | ((value & 0x1) << 47);
4eb6f892
AB		 979}
980
bdfe53e3
AB		 981static long long int
982extract_nps_bitop_mod4 (unsigned long long insn ATTRIBUTE_UNUSED,
4eb6f892
AB		 983 bfd_boolean * invalid ATTRIBUTE_UNUSED)
984{
bdfe53e3 985 return ((insn >> 30) & 0x2) | ((insn >> 47) & 0x1);
4eb6f892
AB		 986}
987
bdfe53e3
AB		 988static unsigned long long
989insert_nps_bitop_dst_pos3_pos4 (unsigned long long insn ATTRIBUTE_UNUSED,
990 long long int value ATTRIBUTE_UNUSED,
4eb6f892
AB		 991 const char **errmsg ATTRIBUTE_UNUSED)
992{
bdfe53e3 993 return insn | (value << 42) | (value << 37);
4eb6f892
AB		 994}
995
bdfe53e3
AB		 996static long long int
997extract_nps_bitop_dst_pos3_pos4 (unsigned long long insn ATTRIBUTE_UNUSED,
4eb6f892
AB		 998 bfd_boolean * invalid ATTRIBUTE_UNUSED)
999{
bdfe53e3 1000 if (((insn >> 42) & 0x1f) != ((insn >> 37) & 0x1f))
4eb6f892 1001 *invalid = TRUE;
bdfe53e3 1002 return ((insn >> 37) & 0x1f);
4eb6f892
AB		 1003}
1004
bdfe53e3
AB		 1005static unsigned long long
1006insert_nps_bitop_ins_ext (unsigned long long insn ATTRIBUTE_UNUSED,
1007 long long int value ATTRIBUTE_UNUSED,
4eb6f892
AB		 1008 const char **errmsg ATTRIBUTE_UNUSED)
1009{
1010 if (value < 0 || value > 28)
1011 *errmsg = _("Value must be in the range 0 to 28");
1012 return insn | (value << 20);
1013}
1014
bdfe53e3
AB		 1015static long long int
1016extract_nps_bitop_ins_ext (unsigned long long insn ATTRIBUTE_UNUSED,
4eb6f892
AB		 1017 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1018{
1019 int value = (insn >> 20) & 0x1f;
1020 if (value > 28)
1021 *invalid = TRUE;
1022 return value;
1023}
1024
14053c19 1025#define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \
bdfe53e3
AB		 1026static unsigned long long \
1027insert_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
1028 long long int value ATTRIBUTE_UNUSED, \
14053c19
GM		 1029 const char **errmsg ATTRIBUTE_UNUSED) \
1030{ \
1031 if (value < 1 || value > UPPER) \
1032 *errmsg = _("Value must be in the range 1 to " #UPPER); \
1033 if (value == UPPER) \
1034 value = 0; \
1035 return insn | (value << SHIFT); \
1036} \
1037 \
bdfe53e3
AB		 1038static long long int \
1039extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
14053c19
GM		 1040 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
1041{ \
1042 int value = (insn >> SHIFT) & ((1 << BITS) - 1); \
1043 if (value == 0) \
1044 value = UPPER; \
1045 return value; \
1046}
1047
db18dbab
GM		 1048MAKE_1BASED_INSERT_EXTRACT_FUNCS (field_size, 6, 8, 3)
1049MAKE_1BASED_INSERT_EXTRACT_FUNCS (shift_factor, 9, 8, 3)
1050MAKE_1BASED_INSERT_EXTRACT_FUNCS (bits_to_scramble, 12, 8, 3)
1051MAKE_1BASED_INSERT_EXTRACT_FUNCS (bdlen_max_len, 5, 256, 8)
1052MAKE_1BASED_INSERT_EXTRACT_FUNCS (bd_num_buff, 6, 8, 3)
1053MAKE_1BASED_INSERT_EXTRACT_FUNCS (pmu_num_job, 6, 4, 2)
5a736821 1054MAKE_1BASED_INSERT_EXTRACT_FUNCS (proto_size, 16, 64, 6)
14053c19 1055
bdfe53e3
AB		 1056static unsigned long long
1057insert_nps_min_hofs (unsigned long long insn ATTRIBUTE_UNUSED,
1058 long long int value ATTRIBUTE_UNUSED,
14053c19
GM		 1059 const char **errmsg ATTRIBUTE_UNUSED)
1060{
1061 if (value < 0 || value > 240)
1062 *errmsg = _("Value must be in the range 0 to 240");
1063 if ((value % 16) != 0)
1064 *errmsg = _("Value must be a multiple of 16");
1065 value = value / 16;
1066 return insn | (value << 6);
1067}
1068
bdfe53e3
AB		 1069static long long int
1070extract_nps_min_hofs (unsigned long long insn ATTRIBUTE_UNUSED,
14053c19
GM		 1071 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1072{
1073 int value = (insn >> 6) & 0xF;
1074 return value * 16;
1075}
1076
db18dbab 1077#define MAKE_INSERT_NPS_ADDRTYPE(NAME,VALUE) \
bdfe53e3
AB		 1078static unsigned long long \
1079insert_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
1080 long long int value ATTRIBUTE_UNUSED, \
db18dbab
GM		 1081 const char **errmsg ATTRIBUTE_UNUSED) \
1082{ \
1083 if (value != ARC_NPS400_ADDRTYPE_##VALUE) \
1084 *errmsg = _("Invalid address type for operand"); \
1085 return insn; \
1086} \
1087 \
bdfe53e3
AB		 1088static long long int \
1089extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
db18dbab
GM		 1090 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
1091{ \
1092 return ARC_NPS400_ADDRTYPE_##VALUE; \
1093}
1094
1095MAKE_INSERT_NPS_ADDRTYPE (bd, BD)
1096MAKE_INSERT_NPS_ADDRTYPE (jid, JID)
1097MAKE_INSERT_NPS_ADDRTYPE (lbd, LBD)
1098MAKE_INSERT_NPS_ADDRTYPE (mbd, MBD)
1099MAKE_INSERT_NPS_ADDRTYPE (sd, SD)
1100MAKE_INSERT_NPS_ADDRTYPE (sm, SM)
1101MAKE_INSERT_NPS_ADDRTYPE (xa, XA)
1102MAKE_INSERT_NPS_ADDRTYPE (xd, XD)
1103MAKE_INSERT_NPS_ADDRTYPE (cd, CD)
1104MAKE_INSERT_NPS_ADDRTYPE (cbd, CBD)
1105MAKE_INSERT_NPS_ADDRTYPE (cjid, CJID)
1106MAKE_INSERT_NPS_ADDRTYPE (clbd, CLBD)
1107MAKE_INSERT_NPS_ADDRTYPE (cm, CM)
1108MAKE_INSERT_NPS_ADDRTYPE (csd, CSD)
1109MAKE_INSERT_NPS_ADDRTYPE (cxa, CXA)
1110MAKE_INSERT_NPS_ADDRTYPE (cxd, CXD)
1111
5a736821
GM		 1112static unsigned long long
1113insert_nps_rbdouble_64 (unsigned long long insn ATTRIBUTE_UNUSED,
1114 long long int value ATTRIBUTE_UNUSED,
1115 const char **errmsg ATTRIBUTE_UNUSED)
1116{
1117 if (value < 0 || value > 31)
1118 *errmsg = _("Value must be in the range 0 to 31");
1119 return insn | (value << 43) | (value << 48);
1120}
1121
1122
1123static long long int
1124extract_nps_rbdouble_64 (unsigned long long insn ATTRIBUTE_UNUSED,
1125 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1126{
1127 int value1 = (insn >> 43) & 0x1F;
1128 int value2 = (insn >> 48) & 0x1F;
1129
1130 if (value1 != value2)
1131 *invalid = TRUE;
1132
1133 return value1;
1134}
1135
886a2506
NC		 1136/* Include the generic extract/insert functions. Order is important
1137 as some of the functions present in the .h may be disabled via
1138 defines. */
1139#include "arc-fxi.h"
252b5132 1140
886a2506 1141/* The flag operands table.
252b5132 1142
886a2506
NC		 1143 The format of the table is
1144 NAME CODE BITS SHIFT FAVAIL. */
1145const struct arc_flag_operand arc_flag_operands[] =
1146{
1147#define F_NULL 0
1148 { 0, 0, 0, 0, 0},
1149#define F_ALWAYS (F_NULL + 1)
1150 { "al", 0, 0, 0, 0 },
1151#define F_RA (F_ALWAYS + 1)
1152 { "ra", 0, 0, 0, 0 },
1153#define F_EQUAL (F_RA + 1)
1154 { "eq", 1, 5, 0, 1 },
1155#define F_ZERO (F_EQUAL + 1)
1156 { "z", 1, 5, 0, 0 },
1157#define F_NOTEQUAL (F_ZERO + 1)
1158 { "ne", 2, 5, 0, 1 },
1159#define F_NOTZERO (F_NOTEQUAL + 1)
1160 { "nz", 2, 5, 0, 0 },
1161#define F_POZITIVE (F_NOTZERO + 1)
1162 { "p", 3, 5, 0, 1 },
1163#define F_PL (F_POZITIVE + 1)
1164 { "pl", 3, 5, 0, 0 },
1165#define F_NEGATIVE (F_PL + 1)
1166 { "n", 4, 5, 0, 1 },
1167#define F_MINUS (F_NEGATIVE + 1)
1168 { "mi", 4, 5, 0, 0 },
1169#define F_CARRY (F_MINUS + 1)
1170 { "c", 5, 5, 0, 1 },
1171#define F_CARRYSET (F_CARRY + 1)
1172 { "cs", 5, 5, 0, 0 },
1173#define F_LOWER (F_CARRYSET + 1)
1174 { "lo", 5, 5, 0, 0 },
1175#define F_CARRYCLR (F_LOWER + 1)
1176 { "cc", 6, 5, 0, 0 },
1177#define F_NOTCARRY (F_CARRYCLR + 1)
1178 { "nc", 6, 5, 0, 1 },
1179#define F_HIGHER (F_NOTCARRY + 1)
1180 { "hs", 6, 5, 0, 0 },
1181#define F_OVERFLOWSET (F_HIGHER + 1)
1182 { "vs", 7, 5, 0, 0 },
1183#define F_OVERFLOW (F_OVERFLOWSET + 1)
1184 { "v", 7, 5, 0, 1 },
1185#define F_NOTOVERFLOW (F_OVERFLOW + 1)
1186 { "nv", 8, 5, 0, 1 },
1187#define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
1188 { "vc", 8, 5, 0, 0 },
1189#define F_GT (F_OVERFLOWCLR + 1)
1190 { "gt", 9, 5, 0, 1 },
1191#define F_GE (F_GT + 1)
1192 { "ge", 10, 5, 0, 1 },
1193#define F_LT (F_GE + 1)
1194 { "lt", 11, 5, 0, 1 },
1195#define F_LE (F_LT + 1)
1196 { "le", 12, 5, 0, 1 },
1197#define F_HI (F_LE + 1)
1198 { "hi", 13, 5, 0, 1 },
1199#define F_LS (F_HI + 1)
1200 { "ls", 14, 5, 0, 1 },
1201#define F_PNZ (F_LS + 1)
1202 { "pnz", 15, 5, 0, 1 },
1203
1204 /* FLAG. */
1205#define F_FLAG (F_PNZ + 1)
1206 { "f", 1, 1, 15, 1 },
1207#define F_FFAKE (F_FLAG + 1)
1208 { "f", 0, 0, 0, 1 },
1209
1210 /* Delay slot. */
1211#define F_ND (F_FFAKE + 1)
1212 { "nd", 0, 1, 5, 0 },
1213#define F_D (F_ND + 1)
1214 { "d", 1, 1, 5, 1 },
1215#define F_DFAKE (F_D + 1)
1216 { "d", 0, 0, 0, 1 },
2b848ebd
CZ		 1217#define F_DNZ_ND (F_DFAKE + 1)
1218 { "nd", 0, 1, 16, 0 },
1219#define F_DNZ_D (F_DNZ_ND + 1)
1220 { "d", 1, 1, 16, 1 },
886a2506
NC		 1221
1222 /* Data size. */
2b848ebd 1223#define F_SIZEB1 (F_DNZ_D + 1)
886a2506
NC		 1224 { "b", 1, 2, 1, 1 },
1225#define F_SIZEB7 (F_SIZEB1 + 1)
1226 { "b", 1, 2, 7, 1 },
1227#define F_SIZEB17 (F_SIZEB7 + 1)
1228 { "b", 1, 2, 17, 1 },
1229#define F_SIZEW1 (F_SIZEB17 + 1)
1230 { "w", 2, 2, 1, 0 },
1231#define F_SIZEW7 (F_SIZEW1 + 1)
1232 { "w", 2, 2, 7, 0 },
1233#define F_SIZEW17 (F_SIZEW7 + 1)
1234 { "w", 2, 2, 17, 0 },
1235
1236 /* Sign extension. */
1237#define F_SIGN6 (F_SIZEW17 + 1)
1238 { "x", 1, 1, 6, 1 },
1239#define F_SIGN16 (F_SIGN6 + 1)
1240 { "x", 1, 1, 16, 1 },
1241#define F_SIGNX (F_SIGN16 + 1)
1242 { "x", 0, 0, 0, 1 },
1243
1244 /* Address write-back modes. */
1245#define F_A3 (F_SIGNX + 1)
1246 { "a", 1, 2, 3, 0 },
1247#define F_A9 (F_A3 + 1)
1248 { "a", 1, 2, 9, 0 },
1249#define F_A22 (F_A9 + 1)
1250 { "a", 1, 2, 22, 0 },
1251#define F_AW3 (F_A22 + 1)
1252 { "aw", 1, 2, 3, 1 },
1253#define F_AW9 (F_AW3 + 1)
1254 { "aw", 1, 2, 9, 1 },
1255#define F_AW22 (F_AW9 + 1)
1256 { "aw", 1, 2, 22, 1 },
1257#define F_AB3 (F_AW22 + 1)
1258 { "ab", 2, 2, 3, 1 },
1259#define F_AB9 (F_AB3 + 1)
1260 { "ab", 2, 2, 9, 1 },
1261#define F_AB22 (F_AB9 + 1)
1262 { "ab", 2, 2, 22, 1 },
1263#define F_AS3 (F_AB22 + 1)
1264 { "as", 3, 2, 3, 1 },
1265#define F_AS9 (F_AS3 + 1)
1266 { "as", 3, 2, 9, 1 },
1267#define F_AS22 (F_AS9 + 1)
1268 { "as", 3, 2, 22, 1 },
1269#define F_ASFAKE (F_AS22 + 1)
1270 { "as", 0, 0, 0, 1 },
1271
1272 /* Cache bypass. */
1273#define F_DI5 (F_ASFAKE + 1)
1274 { "di", 1, 1, 5, 1 },
1275#define F_DI11 (F_DI5 + 1)
1276 { "di", 1, 1, 11, 1 },
b437d035
AB		 1277#define F_DI14 (F_DI11 + 1)
1278 { "di", 1, 1, 14, 1 },
1279#define F_DI15 (F_DI14 + 1)
886a2506
NC		 1280 { "di", 1, 1, 15, 1 },
1281
1282 /* ARCv2 specific. */
1283#define F_NT (F_DI15 + 1)
1284 { "nt", 0, 1, 3, 1},
1285#define F_T (F_NT + 1)
1286 { "t", 1, 1, 3, 1},
1287#define F_H1 (F_T + 1)
1288 { "h", 2, 2, 1, 1 },
1289#define F_H7 (F_H1 + 1)
1290 { "h", 2, 2, 7, 1 },
1291#define F_H17 (F_H7 + 1)
1292 { "h", 2, 2, 17, 1 },
1293
1294 /* Fake Flags. */
1295#define F_NE (F_H17 + 1)
1296 { "ne", 0, 0, 0, 1 },
e23e8ebe
AB		 1297
1298 /* ARC NPS400 Support: See comment near head of file. */
1299#define F_NPS_CL (F_NE + 1)
1300 { "cl", 0, 0, 0, 1 },
1301
1302#define F_NPS_FLAG (F_NPS_CL + 1)
1303 { "f", 1, 1, 20, 1 },
820f03ff
AB		 1304
1305#define F_NPS_R (F_NPS_FLAG + 1)
1306 { "r", 1, 1, 15, 1 },
a42a4f84
AB		 1307
1308#define F_NPS_RW (F_NPS_R + 1)
1309 { "rw", 0, 1, 7, 1 },
1310
1311#define F_NPS_RD (F_NPS_RW + 1)
1312 { "rd", 1, 1, 7, 1 },
1313
1314#define F_NPS_WFT (F_NPS_RD + 1)
1315 { "wft", 0, 0, 0, 1 },
1316
1317#define F_NPS_IE1 (F_NPS_WFT + 1)
1318 { "ie1", 1, 2, 8, 1 },
1319
1320#define F_NPS_IE2 (F_NPS_IE1 + 1)
1321 { "ie2", 2, 2, 8, 1 },
1322
1323#define F_NPS_IE12 (F_NPS_IE2 + 1)
1324 { "ie12", 3, 2, 8, 1 },
1325
1326#define F_NPS_SYNC_RD (F_NPS_IE12 + 1)
1327 { "rd", 0, 1, 6, 1 },
1328
1329#define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1)
1330 { "wr", 1, 1, 6, 1 },
1331
1332#define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1)
1333 { "off", 0, 0, 0, 1 },
1334
1335#define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1)
1336 { "restore", 0, 0, 0, 1 },
1337
537aefaf
AB		 1338#define F_NPS_SX (F_NPS_HWS_RESTORE + 1)
1339 { "sx", 1, 1, 14, 1 },
1340
1341#define F_NPS_AR (F_NPS_SX + 1)
1342 { "ar", 0, 1, 0, 1 },
1343
1344#define F_NPS_AL (F_NPS_AR + 1)
1345 { "al", 1, 1, 0, 1 },
14053c19
GM		 1346
1347#define F_NPS_S (F_NPS_AL + 1)
1348 { "s", 0, 0, 0, 1 },
1349
1350#define F_NPS_ZNCV_RD (F_NPS_S + 1)
1351 { "rd", 0, 1, 15, 1 },
1352
1353#define F_NPS_ZNCV_WR (F_NPS_ZNCV_RD + 1)
1354 { "wr", 1, 1, 15, 1 },
9ba75c88
GM		 1355
1356#define F_NPS_P0 (F_NPS_ZNCV_WR + 1)
1357 { "p0", 0, 0, 0, 1 },
1358
1359#define F_NPS_P1 (F_NPS_P0 + 1)
1360 { "p1", 0, 0, 0, 1 },
1361
1362#define F_NPS_P2 (F_NPS_P1 + 1)
1363 { "p2", 0, 0, 0, 1 },
1364
1365#define F_NPS_P3 (F_NPS_P2 + 1)
1366 { "p3", 0, 0, 0, 1 },
28215275
GM		 1367
1368#define F_NPS_LDBIT_DI (F_NPS_P3 + 1)
1369 { "di", 0, 0, 0, 1 },
1370
1371#define F_NPS_LDBIT_CL1 (F_NPS_LDBIT_DI + 1)
1372 { "cl", 1, 1, 6, 1 },
1373
1374#define F_NPS_LDBIT_CL2 (F_NPS_LDBIT_CL1 + 1)
1375 { "cl", 1, 1, 16, 1 },
1376
1377#define F_NPS_LDBIT_X2_1 (F_NPS_LDBIT_CL2 + 1)
1378 { "x2", 1, 2, 9, 1 },
1379
1380#define F_NPS_LDBIT_X2_2 (F_NPS_LDBIT_X2_1 + 1)
1381 { "x2", 1, 2, 22, 1 },
1382
1383#define F_NPS_LDBIT_X4_1 (F_NPS_LDBIT_X2_2 + 1)
1384 { "x4", 2, 2, 9, 1 },
1385
1386#define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1)
1387 { "x4", 2, 2, 22, 1 },
886a2506 1388};
252b5132 1389
886a2506 1390const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
252b5132 1391
886a2506 1392/* Table of the flag classes.
252b5132 1393
886a2506
NC		 1394 The format of the table is
1395 CLASS {FLAG_CODE}. */
1396const struct arc_flag_class arc_flag_classes[] =
1397{
1398#define C_EMPTY 0
1ae8ab47 1399 { F_CLASS_NONE, { F_NULL } },
886a2506
NC		 1400
1401#define C_CC (C_EMPTY + 1)
d9eca1df 1402 { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND,
f36e33da
CZ		 1403 { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
1404 F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
1405 F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1406 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
1407 F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
1408 F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
886a2506
NC		 1409
1410#define C_AA_ADDR3 (C_CC + 1)
1411#define C_AA27 (C_CC + 1)
1ae8ab47 1412 { F_CLASS_OPTIONAL, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
886a2506
NC		 1413#define C_AA_ADDR9 (C_AA_ADDR3 + 1)
1414#define C_AA21 (C_AA_ADDR3 + 1)
1ae8ab47 1415 { F_CLASS_OPTIONAL, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
886a2506
NC		 1416#define C_AA_ADDR22 (C_AA_ADDR9 + 1)
1417#define C_AA8 (C_AA_ADDR9 + 1)
1ae8ab47 1418 { F_CLASS_OPTIONAL, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
886a2506
NC		 1419
1420#define C_F (C_AA_ADDR22 + 1)
1ae8ab47 1421 { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
886a2506 1422#define C_FHARD (C_F + 1)
1ae8ab47 1423 { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
886a2506
NC		 1424
1425#define C_T (C_FHARD + 1)
1ae8ab47 1426 { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
886a2506 1427#define C_D (C_T + 1)
1ae8ab47 1428 { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
2b848ebd
CZ		 1429#define C_DNZ_D (C_D + 1)
1430 { F_CLASS_OPTIONAL, { F_DNZ_ND, F_DNZ_D, F_NULL } },
886a2506 1431
2b848ebd 1432#define C_DHARD (C_DNZ_D + 1)
1ae8ab47 1433 { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
886a2506
NC		 1434
1435#define C_DI20 (C_DHARD + 1)
1ae8ab47 1436 { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
b437d035
AB		 1437#define C_DI14 (C_DI20 + 1)
1438 { F_CLASS_OPTIONAL, { F_DI14, F_NULL }},
1439#define C_DI16 (C_DI14 + 1)
1ae8ab47 1440 { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
886a2506 1441#define C_DI26 (C_DI16 + 1)
1ae8ab47 1442 { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
886a2506
NC		 1443
1444#define C_X25 (C_DI26 + 1)
1ae8ab47 1445 { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
886a2506 1446#define C_X15 (C_X25 + 1)
1ae8ab47 1447 { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
886a2506
NC		 1448#define C_XHARD (C_X15 + 1)
1449#define C_X (C_X15 + 1)
1ae8ab47 1450 { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
886a2506
NC		 1451
1452#define C_ZZ13 (C_X + 1)
1ae8ab47 1453 { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
886a2506 1454#define C_ZZ23 (C_ZZ13 + 1)
1ae8ab47 1455 { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
886a2506 1456#define C_ZZ29 (C_ZZ23 + 1)
1ae8ab47 1457 { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
886a2506
NC		 1458
1459#define C_AS (C_ZZ29 + 1)
1ae8ab47 1460 { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
886a2506
NC		 1461
1462#define C_NE (C_AS + 1)
1ae8ab47 1463 { F_CLASS_OPTIONAL, { F_NE, F_NULL}},
e23e8ebe
AB		 1464
1465 /* ARC NPS400 Support: See comment near head of file. */
1466#define C_NPS_CL (C_NE + 1)
1467 { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
1468
1469#define C_NPS_F (C_NPS_CL + 1)
1470 { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
820f03ff
AB		 1471
1472#define C_NPS_R (C_NPS_F + 1)
1473 { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}},
a42a4f84
AB		 1474
1475#define C_NPS_SCHD_RW (C_NPS_R + 1)
1476 { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}},
1477
1478#define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1)
1479 { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}},
1480
1481#define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1)
1482 { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}},
1483
1484#define C_NPS_SYNC (C_NPS_SCHD_IE + 1)
1485 { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}},
1486
1487#define C_NPS_HWS_OFF (C_NPS_SYNC + 1)
1488 { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}},
1489
1490#define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1)
1491 { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}},
1492
537aefaf
AB		 1493#define C_NPS_SX (C_NPS_HWS_RESTORE + 1)
1494 { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}},
1495
1496#define C_NPS_AR_AL (C_NPS_SX + 1)
1497 { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}},
14053c19
GM		 1498
1499#define C_NPS_S (C_NPS_AR_AL + 1)
1500 { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}},
1501
1502#define C_NPS_ZNCV (C_NPS_S + 1)
1503 { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}},
9ba75c88
GM		 1504
1505#define C_NPS_P0 (C_NPS_ZNCV + 1)
1506 { F_CLASS_REQUIRED, { F_NPS_P0, F_NULL }},
1507
1508#define C_NPS_P1 (C_NPS_P0 + 1)
1509 { F_CLASS_REQUIRED, { F_NPS_P1, F_NULL }},
1510
1511#define C_NPS_P2 (C_NPS_P1 + 1)
1512 { F_CLASS_REQUIRED, { F_NPS_P2, F_NULL }},
1513
1514#define C_NPS_P3 (C_NPS_P2 + 1)
1515 { F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }},
28215275
GM		 1516
1517#define C_NPS_LDBIT_DI (C_NPS_P3 + 1)
1518 { F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }},
1519
1520#define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1)
1521 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }},
1522
1523#define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1)
1524 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }},
1525
1526#define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1)
1527 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }},
1528
1529#define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1)
1530 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }},
886a2506 1531};
252b5132 1532
b99747ae
CZ		 1533const unsigned char flags_none[] = { 0 };
1534const unsigned char flags_f[] = { C_F };
1535const unsigned char flags_cc[] = { C_CC };
1536const unsigned char flags_ccf[] = { C_CC, C_F };
1537
886a2506 1538/* The operands table.
252b5132 1539
886a2506 1540 The format of the operands table is:
47b0e7ad 1541
886a2506
NC		 1542 BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
1543const struct arc_operand arc_operands[] =
0d2bcfaf 1544{
886a2506
NC		 1545 /* The fields are bits, shift, insert, extract, flags. The zero
1546 index is used to indicate end-of-list. */
1547#define UNUSED 0
1548 { 0, 0, 0, 0, 0, 0 },
4eb6f892
AB		 1549
1550#define IGNORED (UNUSED + 1)
1551 { 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0 },
1552
886a2506
NC		 1553 /* The plain integer register fields. Used by 32 bit
1554 instructions. */
4eb6f892 1555#define RA (IGNORED + 1)
886a2506 1556 { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
abe7c33b
CZ		 1557#define RA_CHK (RA + 1)
1558 { 6, 0, 0, ARC_OPERAND_IR, insert_ra_chk, 0 },
1559#define RB (RA_CHK + 1)
886a2506 1560 { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
abe7c33b
CZ		 1561#define RB_CHK (RB + 1)
1562 { 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb },
1563#define RC (RB_CHK + 1)
886a2506
NC		 1564 { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
1565#define RBdup (RC + 1)
1566 { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
1567
1568#define RAD (RBdup + 1)
1569 { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
1570#define RCD (RAD + 1)
1571 { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
1572
1573 /* The plain integer register fields. Used by short
1574 instructions. */
1575#define RA16 (RCD + 1)
1576#define RA_S (RCD + 1)
1577 { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
1578#define RB16 (RA16 + 1)
1579#define RB_S (RA16 + 1)
1580 { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
1581#define RB16dup (RB16 + 1)
1582#define RB_Sdup (RB16 + 1)
1583 { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
1584#define RC16 (RB16dup + 1)
1585#define RC_S (RB16dup + 1)
1586 { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
1587#define R6H (RC16 + 1) /* 6bit register field 'h' used
1588 by V1 cpus. */
1589 { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
1590#define R5H (R6H + 1) /* 5bit register field 'h' used
1591 by V2 cpus. */
1592#define RH_S (R6H + 1) /* 5bit register field 'h' used
1593 by V2 cpus. */
1594 { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
1595#define R5Hdup (R5H + 1)
1596#define RH_Sdup (R5H + 1)
1597 { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
1598 insert_rhv2, extract_rhv2 },
1599
1600#define RG (R5Hdup + 1)
1601#define G_S (R5Hdup + 1)
1602 { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
1603
1604 /* Fix registers. */
1605#define R0 (RG + 1)
1606#define R0_S (RG + 1)
1607 { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
1608#define R1 (R0 + 1)
1609#define R1_S (R0 + 1)
1610 { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
1611#define R2 (R1 + 1)
1612#define R2_S (R1 + 1)
1613 { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
1614#define R3 (R2 + 1)
1615#define R3_S (R2 + 1)
1616 { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
8ddf6b2a 1617#define RSP (R3 + 1)
886a2506
NC		 1618#define SP_S (R3 + 1)
1619 { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
8ddf6b2a
CZ		 1620#define SPdup (RSP + 1)
1621#define SP_Sdup (RSP + 1)
886a2506
NC		 1622 { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
1623#define GP (SPdup + 1)
1624#define GP_S (SPdup + 1)
1625 { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
1626
1627#define PCL_S (GP + 1)
1628 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
1629
1630#define BLINK (PCL_S + 1)
1631#define BLINK_S (PCL_S + 1)
1632 { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
1633
1634#define ILINK1 (BLINK + 1)
1635 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
1636#define ILINK2 (ILINK1 + 1)
1637 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
1638
1639 /* Long immediate. */
1640#define LIMM (ILINK2 + 1)
1641#define LIMM_S (ILINK2 + 1)
1642 { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
1643#define LIMMdup (LIMM + 1)
1644 { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
1645
1646 /* Special operands. */
1647#define ZA (LIMMdup + 1)
1648#define ZB (LIMMdup + 1)
1649#define ZA_S (LIMMdup + 1)
1650#define ZB_S (LIMMdup + 1)
1651#define ZC_S (LIMMdup + 1)
1652 { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
1653
1654#define RRANGE_EL (ZA + 1)
1655 { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
1656 insert_rrange, extract_rrange},
1657#define FP_EL (RRANGE_EL + 1)
1658 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1659 insert_fpel, extract_fpel },
1660#define BLINK_EL (FP_EL + 1)
1661 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1662 insert_blinkel, extract_blinkel },
1663#define PCL_EL (BLINK_EL + 1)
1664 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1665 insert_pclel, extract_pclel },
1666
1667 /* Fake operand to handle the T flag. */
1668#define BRAKET (PCL_EL + 1)
1669#define BRAKETdup (PCL_EL + 1)
1670 { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
1671
1672 /* Fake operand to handle the T flag. */
1673#define FKT_T (BRAKET + 1)
1674 { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
1675 /* Fake operand to handle the T flag. */
1676#define FKT_NT (FKT_T + 1)
1677 { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
1678
1679 /* UIMM6_20 mask = 00000000000000000000111111000000. */
1680#define UIMM6_20 (FKT_NT + 1)
1681 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
1682
1683 /* SIMM12_20 mask = 00000000000000000000111111222222. */
1684#define SIMM12_20 (UIMM6_20 + 1)
1685 {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
1686
1687 /* SIMM3_5_S mask = 0000011100000000. */
1688#define SIMM3_5_S (SIMM12_20 + 1)
1689 {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
1690 insert_simm3s, extract_simm3s},
1691
1692 /* UIMM7_A32_11_S mask = 0000000000011111. */
1693#define UIMM7_A32_11_S (SIMM3_5_S + 1)
1694 {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1695 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
1696 extract_uimm7_a32_11_s},
1697
1698 /* UIMM7_9_S mask = 0000000001111111. */
1699#define UIMM7_9_S (UIMM7_A32_11_S + 1)
1700 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
1701
1702 /* UIMM3_13_S mask = 0000000000000111. */
1703#define UIMM3_13_S (UIMM7_9_S + 1)
1704 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
1705
1706 /* SIMM11_A32_7_S mask = 0000000111111111. */
1707#define SIMM11_A32_7_S (UIMM3_13_S + 1)
1708 {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1709 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
1710
1711 /* UIMM6_13_S mask = 0000000002220111. */
1712#define UIMM6_13_S (SIMM11_A32_7_S + 1)
1713 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
1714 /* UIMM5_11_S mask = 0000000000011111. */
1715#define UIMM5_11_S (UIMM6_13_S + 1)
1716 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
1717 extract_uimm5_11_s},
1718
1719 /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
1720#define SIMM9_A16_8 (UIMM5_11_S + 1)
1721 {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1722 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
1723 extract_simm9_a16_8},
1724
1725 /* UIMM6_8 mask = 00000000000000000000111111000000. */
1726#define UIMM6_8 (SIMM9_A16_8 + 1)
1727 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
1728
1729 /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
1730#define SIMM21_A16_5 (UIMM6_8 + 1)
1731 {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
1732 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE,
1733 insert_simm21_a16_5, extract_simm21_a16_5},
1734
1735 /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
1736#define SIMM25_A16_5 (SIMM21_A16_5 + 1)
1737 {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
1738 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
1739 insert_simm25_a16_5, extract_simm25_a16_5},
1740
1741 /* SIMM10_A16_7_S mask = 0000000111111111. */
1742#define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
1743 {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1744 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
1745 extract_simm10_a16_7_s},
1746
1747#define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1)
1748 {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1749 | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
1750
1751 /* SIMM7_A16_10_S mask = 0000000000111111. */
1752#define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
1753 {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1754 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
1755 extract_simm7_a16_10_s},
1756
1757 /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
1758#define SIMM21_A32_5 (SIMM7_A16_10_S + 1)
1759 {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1760 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
1761 extract_simm21_a32_5},
1762
1763 /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
1764#define SIMM25_A32_5 (SIMM21_A32_5 + 1)
1765 {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1766 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
1767 extract_simm25_a32_5},
1768
1769 /* SIMM13_A32_5_S mask = 0000011111111111. */
1770#define SIMM13_A32_5_S (SIMM25_A32_5 + 1)
1771 {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1772 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
1773 extract_simm13_a32_5_s},
1774
1775 /* SIMM8_A16_9_S mask = 0000000001111111. */
1776#define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
1777 {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1778 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
1779 extract_simm8_a16_9_s},
1780
1781 /* UIMM3_23 mask = 00000000000000000000000111000000. */
1782#define UIMM3_23 (SIMM8_A16_9_S + 1)
1783 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
1784
1785 /* UIMM10_6_S mask = 0000001111111111. */
1786#define UIMM10_6_S (UIMM3_23 + 1)
1787 {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
1788
1789 /* UIMM6_11_S mask = 0000002200011110. */
1790#define UIMM6_11_S (UIMM10_6_S + 1)
1791 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
1792
1793 /* SIMM9_8 mask = 00000000111111112000000000000000. */
1794#define SIMM9_8 (UIMM6_11_S + 1)
1795 {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
1796 insert_simm9_8, extract_simm9_8},
1797
1798 /* UIMM10_A32_8_S mask = 0000000011111111. */
1799#define UIMM10_A32_8_S (SIMM9_8 + 1)
1800 {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1801 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
1802 extract_uimm10_a32_8_s},
1803
1804 /* SIMM9_7_S mask = 0000000111111111. */
1805#define SIMM9_7_S (UIMM10_A32_8_S + 1)
1806 {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
1807 extract_simm9_7_s},
1808
1809 /* UIMM6_A16_11_S mask = 0000000000011111. */
1810#define UIMM6_A16_11_S (SIMM9_7_S + 1)
1811 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1812 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
1813 extract_uimm6_a16_11_s},
1814
1815 /* UIMM5_A32_11_S mask = 0000020000011000. */
1816#define UIMM5_A32_11_S (UIMM6_A16_11_S + 1)
1817 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1818 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
1819 extract_uimm5_a32_11_s},
1820
1821 /* SIMM11_A32_13_S mask = 0000022222200111. */
1822#define SIMM11_A32_13_S (UIMM5_A32_11_S + 1)
1823 {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1824 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
1825
1826 /* UIMM7_13_S mask = 0000000022220111. */
1827#define UIMM7_13_S (SIMM11_A32_13_S + 1)
1828 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
1829
1830 /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
1831#define UIMM6_A16_21 (UIMM7_13_S + 1)
1832 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1833 | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
1834
1835 /* UIMM7_11_S mask = 0000022200011110. */
1836#define UIMM7_11_S (UIMM6_A16_21 + 1)
1837 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
1838
1839 /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
1840#define UIMM7_A16_20 (UIMM7_11_S + 1)
1841 {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1842 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
1843 extract_uimm7_a16_20},
1844
1845 /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
1846#define SIMM13_A16_20 (UIMM7_A16_20 + 1)
1847 {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1848 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
1849 extract_simm13_a16_20},
1850
1851 /* UIMM8_8_S mask = 0000000011111111. */
1852#define UIMM8_8_S (SIMM13_A16_20 + 1)
1853 {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
1854
1855 /* W6 mask = 00000000000000000000111111000000. */
1856#define W6 (UIMM8_8_S + 1)
1857 {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
1858
1859 /* UIMM6_5_S mask = 0000011111100000. */
1860#define UIMM6_5_S (W6 + 1)
1861 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
e23e8ebe
AB		 1862
1863 /* ARC NPS400 Support: See comment near head of file. */
1864#define NPS_R_DST_3B (UIMM6_5_S + 1)
bdfe53e3 1865 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
e23e8ebe
AB		 1866
1867#define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
bdfe53e3 1868 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
e23e8ebe
AB		 1869
1870#define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
bdfe53e3 1871 { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_21_src2, extract_nps_3bit_reg_at_21_src2 },
e23e8ebe
AB		 1872
1873#define NPS_R_DST (NPS_R_SRC2_3B + 1)
2cce10e7 1874 { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL },
e23e8ebe
AB		 1875
1876#define NPS_R_SRC1 (NPS_R_DST + 1)
2cce10e7 1877 { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
e23e8ebe
AB		 1878
1879#define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1)
1880 { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1881
1882#define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
1883 { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1884
1885#define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
820f03ff 1886 { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size, extract_nps_bitop_size },
e23e8ebe 1887
820f03ff
AB		 1888#define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1)
1889 { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size },
1890
1891#define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1)
1892 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size_2b, extract_nps_bitop_size_2b },
1893
1894#define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1)
1895 { 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 },
1896
1897#define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1)
e23e8ebe 1898 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
820f03ff 1899
14053c19
GM		 1900#define NPS_SIMM16 (NPS_UIMM16 + 1)
1901 { 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL },
1902
1903#define NPS_RFLT_UIMM6 (NPS_SIMM16 + 1)
820f03ff 1904 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
4b0c052e
AB		 1905
1906#define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1)
1907 { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 },
537aefaf
AB		 1908
1909#define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1)
1910 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src2_pos, extract_nps_src2_pos },
1911
1912#define NPS_SRC1_POS (NPS_SRC2_POS + 1)
1913 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src1_pos, extract_nps_src1_pos },
1914
1915#define NPS_ADDB_SIZE (NPS_SRC1_POS + 1)
1916 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_addb_size, extract_nps_addb_size },
1917
1918#define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1)
1919 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_andb_size, extract_nps_andb_size },
1920
1921#define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1)
1922 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_fxorb_size, extract_nps_fxorb_size },
1923
1924#define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1)
1925 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_wxorb_size, extract_nps_wxorb_size },
1926
1927#define NPS_R_XLDST (NPS_WXORB_SIZE + 1)
1928 { 6, 5, 0, ARC_OPERAND_IR, NULL, NULL },
1929
1930#define NPS_DIV_UIMM4 (NPS_R_XLDST + 1)
1931 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1932
1933#define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1)
1934 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_qcmp_size, extract_nps_qcmp_size },
1935
1936#define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1)
1937 { 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1 },
1938
1939#define NPS_QCMP_M2 (NPS_QCMP_M1 + 1)
1940 { 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2 },
1941
1942#define NPS_QCMP_M3 (NPS_QCMP_M2 + 1)
1943 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3 },
1944
1945#define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1)
1946 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_calc_entry_size, extract_nps_calc_entry_size },
4eb6f892
AB		 1947
1948#define NPS_R_DST_3B_SHORT (NPS_CALC_ENTRY_SIZE + 1)
bdfe53e3 1949 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
4eb6f892
AB		 1950
1951#define NPS_R_SRC1_3B_SHORT (NPS_R_DST_3B_SHORT + 1)
bdfe53e3 1952 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
4eb6f892
AB		 1953
1954#define NPS_R_SRC2_3B_SHORT (NPS_R_SRC1_3B_SHORT + 1)
bdfe53e3 1955 { 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_5_src2, extract_nps_3bit_reg_at_5_src2 },
4eb6f892
AB		 1956
1957#define NPS_BITOP_SIZE2 (NPS_R_SRC2_3B_SHORT + 1)
1958 { 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop2_size, extract_nps_bitop2_size },
1959
1960#define NPS_BITOP_SIZE1 (NPS_BITOP_SIZE2 + 1)
1961 { 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop1_size, extract_nps_bitop1_size },
1962
1963#define NPS_BITOP_DST_POS3_POS4 (NPS_BITOP_SIZE1 + 1)
1964 { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4 },
1965
1966#define NPS_BITOP_DST_POS4 (NPS_BITOP_DST_POS3_POS4 + 1)
bdfe53e3 1967 { 5, 42, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
4eb6f892
AB		 1968
1969#define NPS_BITOP_DST_POS3 (NPS_BITOP_DST_POS4 + 1)
bdfe53e3 1970 { 5, 37, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
4eb6f892
AB		 1971
1972#define NPS_BITOP_DST_POS2 (NPS_BITOP_DST_POS3 + 1)
1973 { 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1974
1975#define NPS_BITOP_DST_POS1 (NPS_BITOP_DST_POS2 + 1)
1976 { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1977
1978#define NPS_BITOP_SRC_POS4 (NPS_BITOP_DST_POS1 + 1)
bdfe53e3 1979 { 5, 32, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
4eb6f892
AB		 1980
1981#define NPS_BITOP_SRC_POS3 (NPS_BITOP_SRC_POS4 + 1)
1982 { 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1983
1984#define NPS_BITOP_SRC_POS2 (NPS_BITOP_SRC_POS3 + 1)
1985 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1986
1987#define NPS_BITOP_SRC_POS1 (NPS_BITOP_SRC_POS2 + 1)
1988 { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1989
bdfe53e3
AB		 1990#define NPS_BITOP_MOD4 (NPS_BITOP_SRC_POS1 + 1)
1991 { 2, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_mod4, extract_nps_bitop_mod4 },
4eb6f892 1992
bdfe53e3 1993#define NPS_BITOP_MOD3 (NPS_BITOP_MOD4 + 1)
4eb6f892
AB		 1994 { 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1995
1996#define NPS_BITOP_MOD2 (NPS_BITOP_MOD3 + 1)
1997 { 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1998
1999#define NPS_BITOP_MOD1 (NPS_BITOP_MOD2 + 1)
2000 { 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2001
2002#define NPS_BITOP_INS_EXT (NPS_BITOP_MOD1 + 1)
2003 { 5, 20, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext },
14053c19
GM		 2004
2005#define NPS_FIELD_START_POS (NPS_BITOP_INS_EXT + 1)
2006 { 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2007
2008#define NPS_FIELD_SIZE (NPS_FIELD_START_POS + 1)
2009 { 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_field_size, extract_nps_field_size },
2010
2011#define NPS_SHIFT_FACTOR (NPS_FIELD_SIZE + 1)
2012 { 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_shift_factor, extract_nps_shift_factor },
2013
2014#define NPS_BITS_TO_SCRAMBLE (NPS_SHIFT_FACTOR + 1)
2015 { 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bits_to_scramble, extract_nps_bits_to_scramble },
2016
2017#define NPS_SRC2_POS_5B (NPS_BITS_TO_SCRAMBLE + 1)
2018 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2019
2020#define NPS_BDLEN_MAX_LEN (NPS_SRC2_POS_5B + 1)
2021 { 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bdlen_max_len, extract_nps_bdlen_max_len },
2022
2023#define NPS_MIN_HOFS (NPS_BDLEN_MAX_LEN + 1)
2024 { 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_min_hofs, extract_nps_min_hofs },
2025
2026#define NPS_PSBC (NPS_MIN_HOFS + 1)
2027 { 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
9ba75c88
GM		 2028
2029#define NPS_DPI_DST (NPS_PSBC + 1)
2030 { 5, 11, 0, ARC_OPERAND_IR, NULL, NULL },
2031
2032 /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B but doesn't duplicate an operand */
2033#define NPS_DPI_SRC1_3B (NPS_DPI_DST + 1)
bdfe53e3 2034 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
9ba75c88
GM		 2035
2036#define NPS_HASH_WIDTH (NPS_DPI_SRC1_3B + 1)
2037 { 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_width, extract_nps_hash_width },
2038
2039#define NPS_HASH_PERM (NPS_HASH_WIDTH + 1)
2040 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2041
2042#define NPS_HASH_NONLINEAR (NPS_HASH_PERM + 1)
2043 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2044
2045#define NPS_HASH_BASEMAT (NPS_HASH_NONLINEAR + 1)
2046 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2047
2048#define NPS_HASH_LEN (NPS_HASH_BASEMAT + 1)
2049 { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_len, extract_nps_hash_len },
2050
2051#define NPS_HASH_OFS (NPS_HASH_LEN + 1)
2052 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2053
2054#define NPS_HASH_BASEMAT2 (NPS_HASH_OFS + 1)
2055 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2056
2057#define NPS_E4BY_INDEX0 (NPS_HASH_BASEMAT2 + 1)
2058 { 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2059
2060#define NPS_E4BY_INDEX1 (NPS_E4BY_INDEX0 + 1)
2061 { 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2062
2063#define NPS_E4BY_INDEX2 (NPS_E4BY_INDEX1 + 1)
2064 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2065
2066#define NPS_E4BY_INDEX3 (NPS_E4BY_INDEX2 + 1)
2067 { 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_index3, extract_nps_index3 },
db18dbab
GM		 2068
2069#define COLON (NPS_E4BY_INDEX3 + 1)
2070 { 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL },
2071
2072#define NPS_BD (COLON + 1)
2073 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_bd, extract_nps_bd },
2074
2075#define NPS_JID (NPS_BD + 1)
2076 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_jid, extract_nps_jid },
2077
2078#define NPS_LBD (NPS_JID + 1)
2079 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_lbd, extract_nps_lbd },
2080
2081#define NPS_MBD (NPS_LBD + 1)
2082 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_mbd, extract_nps_mbd },
2083
2084#define NPS_SD (NPS_MBD + 1)
2085 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sd, extract_nps_sd },
2086
2087#define NPS_SM (NPS_SD + 1)
2088 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sm, extract_nps_sm },
2089
2090#define NPS_XA (NPS_SM + 1)
2091 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xa, extract_nps_xa },
2092
2093#define NPS_XD (NPS_XA + 1)
2094 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xd, extract_nps_xd },
2095
2096#define NPS_CD (NPS_XD + 1)
2097 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cd, extract_nps_cd },
2098
2099#define NPS_CBD (NPS_CD + 1)
2100 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cbd, extract_nps_cbd },
2101
2102#define NPS_CJID (NPS_CBD + 1)
2103 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cjid, extract_nps_cjid },
2104
2105#define NPS_CLBD (NPS_CJID + 1)
2106 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_clbd, extract_nps_clbd },
2107
2108#define NPS_CM (NPS_CLBD + 1)
2109 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cm, extract_nps_cm },
2110
2111#define NPS_CSD (NPS_CM + 1)
2112 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_csd, extract_nps_csd },
2113
2114#define NPS_CXA (NPS_CSD + 1)
2115 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxa, extract_nps_cxa },
2116
2117#define NPS_CXD (NPS_CXA + 1)
2118 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxd, extract_nps_cxd },
2119
2120#define NPS_BD_TYPE (NPS_CXD + 1)
2121 { 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2122
2123#define NPS_BMU_NUM (NPS_BD_TYPE + 1)
2124 { 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bd_num_buff, extract_nps_bd_num_buff },
2125
2126#define NPS_PMU_NXT_DST (NPS_BMU_NUM + 1)
2127 { 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2128
2129#define NPS_PMU_NUM_JOB (NPS_PMU_NXT_DST + 1)
2130 { 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_pmu_num_job, extract_nps_pmu_num_job },
bdfe53e3
AB		 2131
2132#define NPS_R_DST_3B_48 (NPS_PMU_NUM_JOB + 1)
2133 { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
2134
2135#define NPS_R_SRC1_3B_48 (NPS_R_DST_3B_48 + 1)
2136 { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
2137
2138#define NPS_R_SRC2_3B_48 (NPS_R_SRC1_3B_48 + 1)
2139 { 3, 37, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_37_src2, extract_nps_3bit_reg_at_37_src2 },
2140
2141#define NPS_R_DST_3B_64 (NPS_R_SRC2_3B_48 + 1)
2142 { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
2143
2144#define NPS_R_SRC1_3B_64 (NPS_R_DST_3B_64 + 1)
2145 { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
2146
2147#define NPS_R_SRC2_3B_64 (NPS_R_SRC1_3B_64 + 1)
2148 { 3, 53, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_53_src2, extract_nps_3bit_reg_at_53_src2 },
0d2bcfaf 2149
5a736821
GM		 2150#define NPS_RA_64 (NPS_R_SRC2_3B_64 + 1)
2151 { 6, 53, 0, ARC_OPERAND_IR, NULL, NULL },
2152
2153#define NPS_RB_64 (NPS_RA_64 + 1)
2154 { 5, 48, 0, ARC_OPERAND_IR, NULL, NULL },
2155
2156#define NPS_RBdup_64 (NPS_RB_64 + 1)
2157 { 5, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
2158
2159#define NPS_RBdouble_64 (NPS_RBdup_64 + 1)
2160 { 10, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_rbdouble_64, extract_nps_rbdouble_64 },
2161
2162#define NPS_RC_64 (NPS_RBdouble_64 + 1)
2163 { 5, 43, 0, ARC_OPERAND_IR, NULL, NULL },
2164
2165#define NPS_UIMM16_0_64 (NPS_RC_64 + 1)
2166 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2167
2168#define NPS_PROTO_SIZE (NPS_UIMM16_0_64 + 1)
2169 { 6, 16, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_proto_size, extract_nps_proto_size }
2170};
886a2506 2171const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
0d2bcfaf 2172
886a2506
NC		 2173const unsigned arc_Toperand = FKT_T;
2174const unsigned arc_NToperand = FKT_NT;
47b0e7ad 2175
b99747ae
CZ		 2176const unsigned char arg_none[] = { 0 };
2177const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC };
2178const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC };
2179const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC };
2180const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 };
2181const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 };
2182const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 };
2183const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 };
2184const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC };
2185const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM };
2186const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC };
2187const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM };
2188
2189const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM };
2190const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 };
2191const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 };
2192
2193const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 };
2194const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup };
2195const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup };
2196
2197const unsigned char arg_32bit_rbrc[] = { RB, RC };
2198const unsigned char arg_32bit_zarc[] = { ZA, RC };
2199const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 };
2200const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 };
2201const unsigned char arg_32bit_rblimm[] = { RB, LIMM };
2202const unsigned char arg_32bit_zalimm[] = { ZA, LIMM };
2203
2204const unsigned char arg_32bit_limmrc[] = { LIMM, RC };
2205const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 };
2206const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 };
2207const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup };
2208
945e0f82
CZ		 2209const unsigned char arg_32bit_rc[] = { RC };
2210const unsigned char arg_32bit_u6[] = { UIMM6_20 };
2211const unsigned char arg_32bit_limm[] = { LIMM };
2212
886a2506 2213/* The opcode table.
0d2bcfaf 2214
886a2506 2215 The format of the opcode table is:
0d2bcfaf 2216
1328504b
AB		 2217 NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }.
2218
2219 The table is organised such that, where possible, all instructions with
2220 the same mnemonic are together in a block. When the assembler searches
2221 for a suitable instruction the entries are checked in table order, so
2222 more specific, or specialised cases should appear earlier in the table.
2223
2224 As an example, consider two instructions 'add a,b,u6' and 'add
2225 a,b,limm'. The first takes a 6-bit immediate that is encoded within the
2226 32-bit instruction, while the second takes a 32-bit immediate that is
2227 encoded in a follow-on 32-bit, making the total instruction length
2228 64-bits. In this case the u6 variant must appear first in the table, as
2229 all u6 immediates could also be encoded using the 'limm' extension,
2230 however, we want to use the shorter instruction wherever possible.
2231
2232 It is possible though to split instructions with the same mnemonic into
2233 multiple groups. However, the instructions are still checked in table
2234 order, even across groups. The only time that instructions with the
2235 same mnemonic should be split into different groups is when different
2236 variants of the instruction appear in different architectures, in which
2237 case, grouping all instructions from a particular architecture together
2238 might be preferable to merging the instruction into the main instruction
2239 table.
2240
2241 An example of this split instruction groups can be found with the 'sync'
2242 instruction. The core arc architecture provides a 'sync' instruction,
2243 while the nps instruction set extension provides 'sync.rd' and
2244 'sync.wr'. The rd/wr flags are instruction flags, not part of the
2245 mnemonic, so we end up with two groups for the sync instruction, the
2246 first within the core arc instruction table, and the second within the
2247 nps extension instructions. */
886a2506 2248const struct arc_opcode arc_opcodes[] =
0d2bcfaf 2249{
886a2506 2250#include "arc-tbl.h"
e23e8ebe 2251#include "arc-nps400-tbl.h"
f2dd8838 2252#include "arc-ext-tbl.h"
0d2bcfaf 2253
b99747ae
CZ		 2254 { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } }
2255};
252b5132 2256
886a2506
NC		 2257/* List with special cases instructions and the applicable flags. */
2258const struct arc_flag_special arc_flag_special_cases[] =
252b5132 2259{
886a2506
NC		 2260 { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2261 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2262 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2263 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2264 { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2265 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2266 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2267 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2268 { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2269 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2270 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2271 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2272 { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2273 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2274 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2275 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2276 { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2277 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2278 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2279 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2280 { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2281 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2282 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2283 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2284 { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2285 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2286 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2287 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2288 { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
2289 { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
2290};
252b5132 2291
886a2506 2292const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
252b5132 2293
886a2506 2294/* Relocations. */
886a2506
NC		 2295const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
2296{
24b368f8
CZ		 2297 { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
2298 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2299 { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
2300 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2301 { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
2302 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2303 { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
2304 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2305
2306 /* Next two entries will cover the undefined behavior ldb/stb with
2307 address scaling. */
2308 { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
2309 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2310 { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
2311 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
2312
2313 { "sda", "ld", { F_ASFAKE, F_NULL },
2314 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2315 { "sda", "st", { F_ASFAKE, F_NULL },
2316 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
2317 { "sda", "ldd", { F_ASFAKE, F_NULL },
2318 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2319 { "sda", "std", { F_ASFAKE, F_NULL },
2320 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
886a2506
NC		 2321
2322 /* Short instructions. */
24b368f8
CZ		 2323 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
2324 { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
2325 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
2326 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
2327
2328 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
2329 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2330
2331 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
2332 BFD_RELOC_ARC_S25H_PCREL_PLT },
2333 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
2334 BFD_RELOC_ARC_S21H_PCREL_PLT },
2335 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
2336 BFD_RELOC_ARC_S25W_PCREL_PLT },
2337 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
2338 BFD_RELOC_ARC_S21W_PCREL_PLT },
2339
2340 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
886a2506 2341};
252b5132 2342
886a2506 2343const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
252b5132 2344
886a2506 2345const struct arc_pseudo_insn arc_pseudo_insns[] =
0d2bcfaf 2346{
886a2506
NC		 2347 { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2348 { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
2349 { BRAKETdup, 1, 0, 4} } },
2350 { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2351 { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
2352 { BRAKETdup, 1, 0, 4} } },
2353
2354 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2355 { SIMM9_A16_8, 0, 0, 2 } } },
2356 { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2357 { SIMM9_A16_8, 0, 0, 2 } } },
2358 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2359 { SIMM9_A16_8, 0, 0, 2 } } },
2360 { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2361 { SIMM9_A16_8, 0, 0, 2 } } },
2362 { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2363 { SIMM9_A16_8, 0, 0, 2 } } },
2364
2365 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2366 { SIMM9_A16_8, 0, 0, 2 } } },
2367 { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2368 { SIMM9_A16_8, 0, 0, 2 } } },
2369 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2370 { SIMM9_A16_8, 0, 0, 2 } } },
2371 { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2372 { SIMM9_A16_8, 0, 0, 2 } } },
2373 { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2374 { SIMM9_A16_8, 0, 0, 2 } } },
2375
2376 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2377 { SIMM9_A16_8, 0, 0, 2 } } },
2378 { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2379 { SIMM9_A16_8, 0, 0, 2 } } },
2380 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2381 { SIMM9_A16_8, 0, 0, 2 } } },
2382 { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2383 { SIMM9_A16_8, 0, 0, 2 } } },
2384 { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2385 { SIMM9_A16_8, 0, 0, 2 } } },
2386
2387 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2388 { SIMM9_A16_8, 0, 0, 2 } } },
2389 { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2390 { SIMM9_A16_8, 0, 0, 2 } } },
2391 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2392 { SIMM9_A16_8, 0, 0, 2 } } },
2393 { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2394 { SIMM9_A16_8, 0, 0, 2 } } },
2395 { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2396 { SIMM9_A16_8, 0, 0, 2 } } },
2397};
0d2bcfaf 2398
886a2506
NC		 2399const unsigned arc_num_pseudo_insn =
2400 sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
0d2bcfaf 2401
886a2506 2402const struct arc_aux_reg arc_aux_regs[] =
0d2bcfaf 2403{
886a2506 2404#undef DEF
f36e33da
CZ		 2405#define DEF(ADDR, CPU, SUBCLASS, NAME) \
2406 { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 },
0d2bcfaf 2407
886a2506 2408#include "arc-regs.h"
0d2bcfaf 2409
886a2506
NC		 2410#undef DEF
2411};
0d2bcfaf 2412
886a2506 2413const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
4670103e
CZ		 2414
2415/* NOTE: The order of this array MUST be consistent with 'enum
2416 arc_rlx_types' located in tc-arc.h! */
2417const struct arc_opcode arc_relax_opcodes[] =
2418{
2419 { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
2420
2421 /* bl_s s13 11111sssssssssss. */
2422 { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2423 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2424 { SIMM13_A32_5_S }, { 0 }},
2425
2426 /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
2427 { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2428 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2429 { SIMM25_A32_5 }, { C_D }},
2430
2431 /* b_s s10 1111000sssssssss. */
2432 { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2433 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2434 { SIMM10_A16_7_S }, { 0 }},
2435
2436 /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
2437 { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2438 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2439 { SIMM25_A16_5 }, { C_D }},
2440
2441 /* add_s c,b,u3 01101bbbccc00uuu. Wants UIMM3_13_S_PCREL. */
2442 { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2443 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2444 { RC_S, RB_S, UIMM3_13_S }, { 0 }},
2445
2446 /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. Wants
2447 UIMM6_20_PCREL. */
2448 { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2449 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2450 { RA, RB, UIMM6_20 }, { C_F }},
2451
2452 /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
2453 { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2454 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2455 { RA, RB, LIMM }, { C_F }},
2456
2457 /* ld_s c,b,u7 10000bbbcccuuuuu. Wants UIMM7_A32_11_S_PCREL. */
2458 { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2459 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2460 { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
2461
2462 /* ld<.di><.aa><.x><zz> a,b,s9
2463 00010bbbssssssssSBBBDaaZZXAAAAAA. Wants SIMM9_8_PCREL. */
2464 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2465 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2466 { RA, BRAKET, RB, SIMM9_8, BRAKETdup },
2467 { C_ZZ23, C_DI20, C_AA21, C_X25 }},
2468
2469 /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
2470 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2471 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2472 { RA, BRAKET, RB, LIMM, BRAKETdup },
2473 { C_ZZ13, C_DI16, C_AA8, C_X15 }},
2474
2475 /* mov_s b,u8 11011bbbuuuuuuuu. Wants UIMM8_8_S_PCREL. */
2476 { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2477 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2478 { RB_S, UIMM8_8_S }, { 0 }},
2479
2480 /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. Wants
2481 SIMM12_20_PCREL. */
2482 { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2483 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2484 { RB, SIMM12_20 }, { C_F }},
2485
2486 /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
2487 { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2488 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2489 { RB, LIMM }, { C_F }},
2490
2491 /* sub_s c,b,u3 01101bbbccc01uuu. UIMM3_13_S_PCREL. */
2492 { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2493 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2494 { RC_S, RB_S, UIMM3_13_S }, { 0 }},
2495
2496 /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA.
2497 UIMM6_20_PCREL. */
2498 { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2499 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2500 { RA, RB, UIMM6_20 }, { C_F }},
2501
2502 /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
2503 { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2504 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2505 { RA, RB, LIMM }, { C_F }},
2506
2507 /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA.
2508 UIMM6_20_PCREL. */
2509 { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2510 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }},
2511
2512 /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
2513 { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2514 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
2515
2516 /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ.
2517 UIMM6_20_PCREL. */
2518 { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2519 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2520 { RB, UIMM6_20 }, { C_F, C_CC }},
2521
2522 /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
2523 { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2524 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2525 { RB, LIMM }, { C_F, C_CC }},
2526
2527 /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ.
2528 UIMM6_20_PCREL. */
2529 { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2530 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2531 { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
2532
2533 /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
2534 { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2535 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2536 { RB, RBdup, LIMM }, { C_F, C_CC }}
2537};
2538
2539const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);
4eb6f892 2540
bdfe53e3 2541/* Return length of an opcode in bytes. */
06fe285f
GM		 2542
2543int
2544arc_opcode_len (const struct arc_opcode *opcode)
2545{
2546 if (opcode->mask < 0x10000ull)
2547 return 2;
bdfe53e3
AB		 2548
2549 if (opcode->mask < 0x100000000ull)
2550 return 4;
2551
2552 if (opcode->mask < 0x1000000000000ull)
2553 return 6;
2554
2555 return 8;
06fe285f 2556}
GDB Binutils - Deliverables
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