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Remove unneeded AUX register symbols.
[deliverable/binutils-gdb.git] / opcodes / arc-opc.c
CommitLineData
252b5132 1/* Opcode table for the ARC.
6f2750fe 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
bcee8eb8 5
9b201bb5
NC		 6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
252b5132 9 it under the terms of the GNU General Public License as published by
9b201bb5 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132
RH		 17
18 You should have received a copy of the GNU General Public License
0d2bcfaf 19 along with this program; if not, write to the Free Software Foundation,
f4321104 20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
252b5132 21
5bd67f35 22#include "sysdep.h"
252b5132 23#include <stdio.h>
d943fe33 24#include "bfd.h"
252b5132 25#include "opcode/arc.h"
47b0e7ad 26#include "opintl.h"
886a2506 27#include "libiberty.h"
252b5132 28
e23e8ebe
AB		 29/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
30 instructions. Support for this target is available when binutils is
31 configured and built for the 'arc*-mellanox-*-*' target. As far as
32 possible all ARC NPS400 features are built into all ARC target builds as
33 this reduces the chances that regressions might creep in. */
34
886a2506
NC		 35/* Insert RB register into a 32-bit opcode. */
36static unsigned
37insert_rb (unsigned insn,
38 int value,
39 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 40{
886a2506
NC		 41 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
42}
0d2bcfaf 43
886a2506
NC		 44static int
45extract_rb (unsigned insn ATTRIBUTE_UNUSED,
46 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47{
48 int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
0d2bcfaf 49
886a2506
NC		 50 if (value == 0x3e && invalid)
51 *invalid = TRUE; /* A limm operand, it should be extracted in a
52 different way. */
252b5132 53
886a2506
NC		 54 return value;
55}
252b5132 56
886a2506
NC		 57static unsigned
58insert_rad (unsigned insn,
59 int value,
60 const char **errmsg ATTRIBUTE_UNUSED)
61{
62 if (value & 0x01)
63 *errmsg = _("Improper register value.");
0d2bcfaf 64
886a2506
NC		 65 return insn | (value & 0x3F);
66}
0d2bcfaf 67
886a2506
NC		 68static unsigned
69insert_rcd (unsigned insn,
70 int value,
71 const char **errmsg ATTRIBUTE_UNUSED)
72{
73 if (value & 0x01)
74 *errmsg = _("Improper register value.");
0d2bcfaf 75
886a2506
NC		 76 return insn | ((value & 0x3F) << 6);
77}
252b5132 78
886a2506 79/* Dummy insert ZERO operand function. */
252b5132 80
886a2506
NC		 81static unsigned
82insert_za (unsigned insn,
83 int value,
84 const char **errmsg)
85{
86 if (value)
87 *errmsg = _("operand is not zero");
88 return insn;
89}
252b5132 90
886a2506
NC		 91/* Insert Y-bit in bbit/br instructions. This function is called only
92 when solving fixups. */
252b5132 93
886a2506
NC		 94static unsigned
95insert_Ybit (unsigned insn,
96 int value,
97 const char **errmsg ATTRIBUTE_UNUSED)
98{
99 if (value > 0)
100 insn |= 0x08;
252b5132 101
886a2506
NC		 102 return insn;
103}
252b5132 104
886a2506
NC		 105/* Insert Y-bit in bbit/br instructions. This function is called only
106 when solving fixups. */
252b5132 107
886a2506
NC		 108static unsigned
109insert_NYbit (unsigned insn,
110 int value,
111 const char **errmsg ATTRIBUTE_UNUSED)
112{
113 if (value < 0)
114 insn |= 0x08;
0d2bcfaf 115
886a2506
NC		 116 return insn;
117}
252b5132 118
886a2506 119/* Insert H register into a 16-bit opcode. */
252b5132 120
886a2506
NC		 121static unsigned
122insert_rhv1 (unsigned insn,
123 int value,
124 const char **errmsg ATTRIBUTE_UNUSED)
125{
126 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
127}
252b5132 128
886a2506
NC		 129static int
130extract_rhv1 (unsigned insn ATTRIBUTE_UNUSED,
131 bfd_boolean * invalid ATTRIBUTE_UNUSED)
132{
133 int value = 0;
252b5132 134
886a2506
NC		 135 return value;
136}
252b5132 137
886a2506 138/* Insert H register into a 16-bit opcode. */
252b5132 139
886a2506
NC		 140static unsigned
141insert_rhv2 (unsigned insn,
142 int value,
143 const char **errmsg)
0d2bcfaf 144{
886a2506
NC		 145 if (value == 0x1E)
146 *errmsg =
147 _("Register R30 is a limm indicator for this type of instruction.");
148 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
149}
252b5132 150
886a2506
NC		 151static int
152extract_rhv2 (unsigned insn ATTRIBUTE_UNUSED,
153 bfd_boolean * invalid ATTRIBUTE_UNUSED)
154{
155 int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
0d2bcfaf 156
886a2506
NC		 157 return value;
158}
0d2bcfaf 159
886a2506
NC		 160static unsigned
161insert_r0 (unsigned insn,
162 int value,
163 const char **errmsg ATTRIBUTE_UNUSED)
164{
165 if (value != 0)
166 *errmsg = _("Register must be R0.");
47b0e7ad
NC		 167 return insn;
168}
252b5132 169
886a2506
NC		 170static int
171extract_r0 (unsigned insn ATTRIBUTE_UNUSED,
172 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 173{
886a2506 174 return 0;
47b0e7ad 175}
252b5132 176
252b5132 177
886a2506
NC		 178static unsigned
179insert_r1 (unsigned insn,
180 int value,
181 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 182{
886a2506
NC		 183 if (value != 1)
184 *errmsg = _("Register must be R1.");
47b0e7ad 185 return insn;
252b5132
RH		 186}
187
886a2506
NC		 188static int
189extract_r1 (unsigned insn ATTRIBUTE_UNUSED,
190 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 191{
886a2506 192 return 1;
252b5132
RH		 193}
194
886a2506
NC		 195static unsigned
196insert_r2 (unsigned insn,
197 int value,
198 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 199{
886a2506
NC		 200 if (value != 2)
201 *errmsg = _("Register must be R2.");
47b0e7ad 202 return insn;
252b5132
RH		 203}
204
886a2506
NC		 205static int
206extract_r2 (unsigned insn ATTRIBUTE_UNUSED,
207 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 208{
886a2506 209 return 2;
252b5132
RH		 210}
211
886a2506
NC		 212static unsigned
213insert_r3 (unsigned insn,
214 int value,
215 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 216{
886a2506
NC		 217 if (value != 3)
218 *errmsg = _("Register must be R3.");
47b0e7ad 219 return insn;
0d2bcfaf
NC		 220}
221
886a2506
NC		 222static int
223extract_r3 (unsigned insn ATTRIBUTE_UNUSED,
224 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 225{
886a2506 226 return 3;
0d2bcfaf
NC		 227}
228
886a2506
NC		 229static unsigned
230insert_sp (unsigned insn,
231 int value,
232 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 233{
886a2506
NC		 234 if (value != 28)
235 *errmsg = _("Register must be SP.");
252b5132
RH		 236 return insn;
237}
238
886a2506
NC		 239static int
240extract_sp (unsigned insn ATTRIBUTE_UNUSED,
241 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 242{
886a2506 243 return 28;
0d2bcfaf
NC		 244}
245
886a2506
NC		 246static unsigned
247insert_gp (unsigned insn,
248 int value,
249 const char **errmsg ATTRIBUTE_UNUSED)
0d2bcfaf 250{
886a2506
NC		 251 if (value != 26)
252 *errmsg = _("Register must be GP.");
253 return insn;
0d2bcfaf
NC		 254}
255
886a2506
NC		 256static int
257extract_gp (unsigned insn ATTRIBUTE_UNUSED,
258 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 259{
886a2506 260 return 26;
0d2bcfaf
NC		 261}
262
886a2506
NC		 263static unsigned
264insert_pcl (unsigned insn,
265 int value,
266 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 267{
886a2506
NC		 268 if (value != 63)
269 *errmsg = _("Register must be PCL.");
252b5132
RH		 270 return insn;
271}
272
886a2506
NC		 273static int
274extract_pcl (unsigned insn ATTRIBUTE_UNUSED,
275 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 276{
886a2506 277 return 63;
0d2bcfaf
NC		 278}
279
886a2506
NC		 280static unsigned
281insert_blink (unsigned insn,
282 int value,
283 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 284{
886a2506
NC		 285 if (value != 31)
286 *errmsg = _("Register must be BLINK.");
252b5132
RH		 287 return insn;
288}
289
886a2506
NC		 290static int
291extract_blink (unsigned insn ATTRIBUTE_UNUSED,
292 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 293{
886a2506 294 return 31;
0d2bcfaf
NC		 295}
296
886a2506
NC		 297static unsigned
298insert_ilink1 (unsigned insn,
299 int value,
300 const char **errmsg ATTRIBUTE_UNUSED)
0d2bcfaf 301{
886a2506
NC		 302 if (value != 29)
303 *errmsg = _("Register must be ILINK1.");
252b5132
RH		 304 return insn;
305}
306
886a2506
NC		 307static int
308extract_ilink1 (unsigned insn ATTRIBUTE_UNUSED,
309 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 310{
886a2506 311 return 29;
252b5132
RH		 312}
313
886a2506
NC		 314static unsigned
315insert_ilink2 (unsigned insn,
316 int value,
317 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 318{
886a2506
NC		 319 if (value != 30)
320 *errmsg = _("Register must be ILINK2.");
252b5132
RH		 321 return insn;
322}
323
886a2506
NC		 324static int
325extract_ilink2 (unsigned insn ATTRIBUTE_UNUSED,
326 bfd_boolean * invalid ATTRIBUTE_UNUSED)
327{
328 return 30;
329}
252b5132 330
886a2506
NC		 331static unsigned
332insert_ras (unsigned insn,
333 int value,
334 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 335{
886a2506 336 switch (value)
0d2bcfaf 337 {
886a2506
NC		 338 case 0:
339 case 1:
340 case 2:
341 case 3:
342 insn |= value;
343 break;
344 case 12:
345 case 13:
346 case 14:
347 case 15:
348 insn |= (value - 8);
349 break;
350 default:
351 *errmsg = _("Register must be either r0-r3 or r12-r15.");
352 break;
0d2bcfaf 353 }
252b5132
RH		 354 return insn;
355}
252b5132 356
886a2506
NC		 357static int
358extract_ras (unsigned insn ATTRIBUTE_UNUSED,
359 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 360{
886a2506
NC		 361 int value = insn & 0x07;
362 if (value > 3)
363 return (value + 8);
364 else
365 return value;
47b0e7ad
NC		 366}
367
886a2506
NC		 368static unsigned
369insert_rbs (unsigned insn,
370 int value,
371 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 372{
886a2506 373 switch (value)
47b0e7ad 374 {
886a2506
NC		 375 case 0:
376 case 1:
377 case 2:
378 case 3:
379 insn |= value << 8;
380 break;
381 case 12:
382 case 13:
383 case 14:
384 case 15:
385 insn |= ((value - 8)) << 8;
386 break;
387 default:
388 *errmsg = _("Register must be either r0-r3 or r12-r15.");
389 break;
47b0e7ad 390 }
886a2506 391 return insn;
252b5132
RH		 392}
393
886a2506
NC		 394static int
395extract_rbs (unsigned insn ATTRIBUTE_UNUSED,
396 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 397{
886a2506
NC		 398 int value = (insn >> 8) & 0x07;
399 if (value > 3)
400 return (value + 8);
401 else
402 return value;
403}
252b5132 404
886a2506
NC		 405static unsigned
406insert_rcs (unsigned insn,
407 int value,
408 const char **errmsg ATTRIBUTE_UNUSED)
409{
410 switch (value)
252b5132 411 {
886a2506
NC		 412 case 0:
413 case 1:
414 case 2:
415 case 3:
416 insn |= value << 5;
417 break;
418 case 12:
419 case 13:
420 case 14:
421 case 15:
422 insn |= ((value - 8)) << 5;
423 break;
424 default:
425 *errmsg = _("Register must be either r0-r3 or r12-r15.");
426 break;
252b5132 427 }
886a2506
NC		 428 return insn;
429}
47b0e7ad 430
886a2506
NC		 431static int
432extract_rcs (unsigned insn ATTRIBUTE_UNUSED,
433 bfd_boolean * invalid ATTRIBUTE_UNUSED)
434{
435 int value = (insn >> 5) & 0x07;
436 if (value > 3)
437 return (value + 8);
252b5132 438 else
886a2506
NC		 439 return value;
440}
47b0e7ad 441
886a2506
NC		 442static unsigned
443insert_simm3s (unsigned insn,
444 int value,
445 const char **errmsg ATTRIBUTE_UNUSED)
446{
447 int tmp = 0;
448 switch (value)
47b0e7ad 449 {
886a2506
NC		 450 case -1:
451 tmp = 0x07;
47b0e7ad 452 break;
886a2506
NC		 453 case 0:
454 tmp = 0x00;
455 break;
456 case 1:
457 tmp = 0x01;
47b0e7ad 458 break;
886a2506
NC		 459 case 2:
460 tmp = 0x02;
47b0e7ad 461 break;
886a2506
NC		 462 case 3:
463 tmp = 0x03;
464 break;
465 case 4:
466 tmp = 0x04;
467 break;
468 case 5:
469 tmp = 0x05;
470 break;
471 case 6:
472 tmp = 0x06;
473 break;
474 default:
475 *errmsg = _("Accepted values are from -1 to 6.");
47b0e7ad
NC		 476 break;
477 }
478
886a2506
NC		 479 insn |= tmp << 8;
480 return insn;
47b0e7ad
NC		 481}
482
886a2506
NC		 483static int
484extract_simm3s (unsigned insn ATTRIBUTE_UNUSED,
485 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 486{
886a2506
NC		 487 int value = (insn >> 8) & 0x07;
488 if (value == 7)
489 return -1;
47b0e7ad 490 else
886a2506 491 return value;
47b0e7ad
NC		 492}
493
886a2506
NC		 494static unsigned
495insert_rrange (unsigned insn,
496 int value,
497 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 498{
886a2506
NC		 499 int reg1 = (value >> 16) & 0xFFFF;
500 int reg2 = value & 0xFFFF;
501 if (reg1 != 13)
502 {
503 *errmsg = _("First register of the range should be r13.");
504 return insn;
505 }
506 if (reg2 < 13 || reg2 > 26)
507 {
508 *errmsg = _("Last register of the range doesn't fit.");
509 return insn;
510 }
511 insn |= ((reg2 - 12) & 0x0F) << 1;
512 return insn;
47b0e7ad
NC		 513}
514
886a2506
NC		 515static int
516extract_rrange (unsigned insn ATTRIBUTE_UNUSED,
517 bfd_boolean * invalid ATTRIBUTE_UNUSED)
518{
519 return (insn >> 1) & 0x0F;
520}
47b0e7ad 521
886a2506
NC		 522static unsigned
523insert_fpel (unsigned insn,
524 int value,
525 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 526{
886a2506
NC		 527 if (value != 27)
528 {
529 *errmsg = _("Invalid register number, should be fp.");
530 return insn;
531 }
47b0e7ad 532
886a2506
NC		 533 insn |= 0x0100;
534 return insn;
47b0e7ad
NC		 535}
536
886a2506
NC		 537static int
538extract_fpel (unsigned insn ATTRIBUTE_UNUSED,
539 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 540{
886a2506 541 return (insn & 0x0100) ? 27 : -1;
47b0e7ad
NC		 542}
543
886a2506
NC		 544static unsigned
545insert_blinkel (unsigned insn,
546 int value,
547 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 548{
886a2506 549 if (value != 31)
47b0e7ad 550 {
886a2506
NC		 551 *errmsg = _("Invalid register number, should be blink.");
552 return insn;
47b0e7ad 553 }
47b0e7ad 554
886a2506
NC		 555 insn |= 0x0200;
556 return insn;
47b0e7ad
NC		 557}
558
886a2506
NC		 559static int
560extract_blinkel (unsigned insn ATTRIBUTE_UNUSED,
561 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 562{
886a2506
NC		 563 return (insn & 0x0200) ? 31 : -1;
564}
47b0e7ad 565
886a2506
NC		 566static unsigned
567insert_pclel (unsigned insn,
568 int value,
569 const char **errmsg ATTRIBUTE_UNUSED)
570{
571 if (value != 63)
47b0e7ad 572 {
886a2506
NC		 573 *errmsg = _("Invalid register number, should be pcl.");
574 return insn;
47b0e7ad 575 }
47b0e7ad 576
886a2506
NC		 577 insn |= 0x0400;
578 return insn;
579}
47b0e7ad 580
886a2506
NC		 581static int
582extract_pclel (unsigned insn ATTRIBUTE_UNUSED,
583 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 584{
886a2506 585 return (insn & 0x0400) ? 63 : -1;
47b0e7ad 586}
47b0e7ad 587
886a2506
NC		 588#define INSERT_W6
589/* mask = 00000000000000000000111111000000
590 insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
591static unsigned
592insert_w6 (unsigned insn ATTRIBUTE_UNUSED,
593 int value ATTRIBUTE_UNUSED,
594 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 595{
886a2506 596 insn |= ((value >> 0) & 0x003f) << 6;
47b0e7ad 597
886a2506
NC		 598 return insn;
599}
47b0e7ad 600
886a2506
NC		 601#define EXTRACT_W6
602/* mask = 00000000000000000000111111000000. */
603static int
604extract_w6 (unsigned insn ATTRIBUTE_UNUSED,
605 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 606{
886a2506 607 unsigned value = 0;
47b0e7ad 608
886a2506 609 value |= ((insn >> 6) & 0x003f) << 0;
47b0e7ad 610
886a2506
NC		 611 return value;
612}
47b0e7ad 613
886a2506
NC		 614#define INSERT_G_S
615/* mask = 0000011100022000
616 insn = 01000ggghhhGG0HH. */
617static unsigned
618insert_g_s (unsigned insn ATTRIBUTE_UNUSED,
619 int value ATTRIBUTE_UNUSED,
620 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 621{
886a2506
NC		 622 insn |= ((value >> 0) & 0x0007) << 8;
623 insn |= ((value >> 3) & 0x0003) << 3;
252b5132 624
886a2506
NC		 625 return insn;
626}
252b5132 627
886a2506
NC		 628#define EXTRACT_G_S
629/* mask = 0000011100022000. */
630static int
631extract_g_s (unsigned insn ATTRIBUTE_UNUSED,
632 bfd_boolean * invalid ATTRIBUTE_UNUSED)
633{
634 int value = 0;
252b5132 635
886a2506
NC		 636 value |= ((insn >> 8) & 0x0007) << 0;
637 value |= ((insn >> 3) & 0x0003) << 3;
252b5132 638
886a2506
NC		 639 /* Extend the sign. */
640 int signbit = 1 << (6 - 1);
641 value = (value ^ signbit) - signbit;
252b5132 642
886a2506 643 return value;
252b5132
RH		 644}
645
e23e8ebe
AB		 646/* ARC NPS400 Support: See comment near head of file. */
647static unsigned
648insert_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
649 int value ATTRIBUTE_UNUSED,
650 const char **errmsg ATTRIBUTE_UNUSED)
651{
652 switch (value)
653 {
654 case 0:
655 case 1:
656 case 2:
657 case 3:
658 insn |= value << 24;
659 break;
660 case 12:
661 case 13:
662 case 14:
663 case 15:
664 insn |= (value - 8) << 24;
665 break;
666 default:
667 *errmsg = _("Register must be either r0-r3 or r12-r15.");
668 break;
669 }
670 return insn;
671}
672
673static int
674extract_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
675 bfd_boolean * invalid ATTRIBUTE_UNUSED)
676{
677 int value = (insn >> 24) & 0x07;
678 if (value > 3)
679 return (value + 8);
680 else
681 return value;
682}
683
684static unsigned
685insert_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
686 int value ATTRIBUTE_UNUSED,
687 const char **errmsg ATTRIBUTE_UNUSED)
688{
689 switch (value)
690 {
691 case 0:
692 case 1:
693 case 2:
694 case 3:
695 insn |= value << 21;
696 break;
697 case 12:
698 case 13:
699 case 14:
700 case 15:
701 insn |= (value - 8) << 21;
702 break;
703 default:
704 *errmsg = _("Register must be either r0-r3 or r12-r15.");
705 break;
706 }
707 return insn;
708}
709
710static int
711extract_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
712 bfd_boolean * invalid ATTRIBUTE_UNUSED)
713{
714 int value = (insn >> 21) & 0x07;
715 if (value > 3)
716 return (value + 8);
717 else
718 return value;
719}
720
721static unsigned
722insert_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
723 int value ATTRIBUTE_UNUSED,
724 const char **errmsg ATTRIBUTE_UNUSED)
725{
726 if (value < 1 || value > 32)
727 {
728 *errmsg = _("Invalid bit size, should be between 1 and 32 inclusive.");
729 return insn;
730 }
731
732 --value;
733 insn |= ((value & 0x1f) << 10);
734 return insn;
735}
736
737static int
738extract_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
739 bfd_boolean * invalid ATTRIBUTE_UNUSED)
740{
741 return ((insn >> 10) & 0x1f) + 1;
742}
743
820f03ff
AB		 744static unsigned
745insert_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED,
746 int value ATTRIBUTE_UNUSED,
747 const char **errmsg ATTRIBUTE_UNUSED)
748{
749 switch (value)
750 {
751 case 1:
752 value = 0;
753 break;
754 case 2:
755 value = 1;
756 break;
757 case 4:
758 value = 2;
759 break;
760 case 8:
761 value = 3;
762 break;
763 default:
764 value = 0;
765 *errmsg = _("Invalid size, should be 1, 2, 4, or 8.");
766 break;
767 }
768
769 insn |= value << 10;
770 return insn;
771}
772
773static int
774extract_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED,
775 bfd_boolean * invalid ATTRIBUTE_UNUSED)
776{
777 return 1 << ((insn >> 10) & 0x3);
778}
779
780static unsigned
781insert_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED,
782 int value ATTRIBUTE_UNUSED,
783 const char **errmsg ATTRIBUTE_UNUSED)
784{
785 insn |= ((value >> 5) & 7) << 12;
786 insn |= (value & 0x1f);
787 return insn;
788}
789
790static int
791extract_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED,
792 bfd_boolean * invalid ATTRIBUTE_UNUSED)
793{
794 return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
795}
796
797static unsigned
798insert_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED,
799 int value ATTRIBUTE_UNUSED,
800 const char **errmsg ATTRIBUTE_UNUSED)
801{
802 switch (value)
803 {
804 case 1:
805 case 2:
806 case 4:
807 break;
808
809 default:
810 *errmsg = _("invalid immediate, must be 1, 2, or 4");
811 value = 0;
812 }
813
814 insn |= (value << 6);
815 return insn;
816}
817
818static int
819extract_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED,
820 bfd_boolean * invalid ATTRIBUTE_UNUSED)
821{
822 return (insn >> 6) & 0x3f;
823}
824
825static unsigned
826insert_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED,
827 int value ATTRIBUTE_UNUSED,
828 const char **errmsg ATTRIBUTE_UNUSED)
829{
830 insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10));
831 return insn;
832}
833
834static int
835extract_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED,
836 bfd_boolean * invalid ATTRIBUTE_UNUSED)
837{
838 return (insn & 0x1f);
839}
840
886a2506
NC		 841/* Include the generic extract/insert functions. Order is important
842 as some of the functions present in the .h may be disabled via
843 defines. */
844#include "arc-fxi.h"
252b5132 845
886a2506 846/* The flag operands table.
252b5132 847
886a2506
NC		 848 The format of the table is
849 NAME CODE BITS SHIFT FAVAIL. */
850const struct arc_flag_operand arc_flag_operands[] =
851{
852#define F_NULL 0
853 { 0, 0, 0, 0, 0},
854#define F_ALWAYS (F_NULL + 1)
855 { "al", 0, 0, 0, 0 },
856#define F_RA (F_ALWAYS + 1)
857 { "ra", 0, 0, 0, 0 },
858#define F_EQUAL (F_RA + 1)
859 { "eq", 1, 5, 0, 1 },
860#define F_ZERO (F_EQUAL + 1)
861 { "z", 1, 5, 0, 0 },
862#define F_NOTEQUAL (F_ZERO + 1)
863 { "ne", 2, 5, 0, 1 },
864#define F_NOTZERO (F_NOTEQUAL + 1)
865 { "nz", 2, 5, 0, 0 },
866#define F_POZITIVE (F_NOTZERO + 1)
867 { "p", 3, 5, 0, 1 },
868#define F_PL (F_POZITIVE + 1)
869 { "pl", 3, 5, 0, 0 },
870#define F_NEGATIVE (F_PL + 1)
871 { "n", 4, 5, 0, 1 },
872#define F_MINUS (F_NEGATIVE + 1)
873 { "mi", 4, 5, 0, 0 },
874#define F_CARRY (F_MINUS + 1)
875 { "c", 5, 5, 0, 1 },
876#define F_CARRYSET (F_CARRY + 1)
877 { "cs", 5, 5, 0, 0 },
878#define F_LOWER (F_CARRYSET + 1)
879 { "lo", 5, 5, 0, 0 },
880#define F_CARRYCLR (F_LOWER + 1)
881 { "cc", 6, 5, 0, 0 },
882#define F_NOTCARRY (F_CARRYCLR + 1)
883 { "nc", 6, 5, 0, 1 },
884#define F_HIGHER (F_NOTCARRY + 1)
885 { "hs", 6, 5, 0, 0 },
886#define F_OVERFLOWSET (F_HIGHER + 1)
887 { "vs", 7, 5, 0, 0 },
888#define F_OVERFLOW (F_OVERFLOWSET + 1)
889 { "v", 7, 5, 0, 1 },
890#define F_NOTOVERFLOW (F_OVERFLOW + 1)
891 { "nv", 8, 5, 0, 1 },
892#define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
893 { "vc", 8, 5, 0, 0 },
894#define F_GT (F_OVERFLOWCLR + 1)
895 { "gt", 9, 5, 0, 1 },
896#define F_GE (F_GT + 1)
897 { "ge", 10, 5, 0, 1 },
898#define F_LT (F_GE + 1)
899 { "lt", 11, 5, 0, 1 },
900#define F_LE (F_LT + 1)
901 { "le", 12, 5, 0, 1 },
902#define F_HI (F_LE + 1)
903 { "hi", 13, 5, 0, 1 },
904#define F_LS (F_HI + 1)
905 { "ls", 14, 5, 0, 1 },
906#define F_PNZ (F_LS + 1)
907 { "pnz", 15, 5, 0, 1 },
908
909 /* FLAG. */
910#define F_FLAG (F_PNZ + 1)
911 { "f", 1, 1, 15, 1 },
912#define F_FFAKE (F_FLAG + 1)
913 { "f", 0, 0, 0, 1 },
914
915 /* Delay slot. */
916#define F_ND (F_FFAKE + 1)
917 { "nd", 0, 1, 5, 0 },
918#define F_D (F_ND + 1)
919 { "d", 1, 1, 5, 1 },
920#define F_DFAKE (F_D + 1)
921 { "d", 0, 0, 0, 1 },
922
923 /* Data size. */
924#define F_SIZEB1 (F_DFAKE + 1)
925 { "b", 1, 2, 1, 1 },
926#define F_SIZEB7 (F_SIZEB1 + 1)
927 { "b", 1, 2, 7, 1 },
928#define F_SIZEB17 (F_SIZEB7 + 1)
929 { "b", 1, 2, 17, 1 },
930#define F_SIZEW1 (F_SIZEB17 + 1)
931 { "w", 2, 2, 1, 0 },
932#define F_SIZEW7 (F_SIZEW1 + 1)
933 { "w", 2, 2, 7, 0 },
934#define F_SIZEW17 (F_SIZEW7 + 1)
935 { "w", 2, 2, 17, 0 },
936
937 /* Sign extension. */
938#define F_SIGN6 (F_SIZEW17 + 1)
939 { "x", 1, 1, 6, 1 },
940#define F_SIGN16 (F_SIGN6 + 1)
941 { "x", 1, 1, 16, 1 },
942#define F_SIGNX (F_SIGN16 + 1)
943 { "x", 0, 0, 0, 1 },
944
945 /* Address write-back modes. */
946#define F_A3 (F_SIGNX + 1)
947 { "a", 1, 2, 3, 0 },
948#define F_A9 (F_A3 + 1)
949 { "a", 1, 2, 9, 0 },
950#define F_A22 (F_A9 + 1)
951 { "a", 1, 2, 22, 0 },
952#define F_AW3 (F_A22 + 1)
953 { "aw", 1, 2, 3, 1 },
954#define F_AW9 (F_AW3 + 1)
955 { "aw", 1, 2, 9, 1 },
956#define F_AW22 (F_AW9 + 1)
957 { "aw", 1, 2, 22, 1 },
958#define F_AB3 (F_AW22 + 1)
959 { "ab", 2, 2, 3, 1 },
960#define F_AB9 (F_AB3 + 1)
961 { "ab", 2, 2, 9, 1 },
962#define F_AB22 (F_AB9 + 1)
963 { "ab", 2, 2, 22, 1 },
964#define F_AS3 (F_AB22 + 1)
965 { "as", 3, 2, 3, 1 },
966#define F_AS9 (F_AS3 + 1)
967 { "as", 3, 2, 9, 1 },
968#define F_AS22 (F_AS9 + 1)
969 { "as", 3, 2, 22, 1 },
970#define F_ASFAKE (F_AS22 + 1)
971 { "as", 0, 0, 0, 1 },
972
973 /* Cache bypass. */
974#define F_DI5 (F_ASFAKE + 1)
975 { "di", 1, 1, 5, 1 },
976#define F_DI11 (F_DI5 + 1)
977 { "di", 1, 1, 11, 1 },
978#define F_DI15 (F_DI11 + 1)
979 { "di", 1, 1, 15, 1 },
980
981 /* ARCv2 specific. */
982#define F_NT (F_DI15 + 1)
983 { "nt", 0, 1, 3, 1},
984#define F_T (F_NT + 1)
985 { "t", 1, 1, 3, 1},
986#define F_H1 (F_T + 1)
987 { "h", 2, 2, 1, 1 },
988#define F_H7 (F_H1 + 1)
989 { "h", 2, 2, 7, 1 },
990#define F_H17 (F_H7 + 1)
991 { "h", 2, 2, 17, 1 },
992
993 /* Fake Flags. */
994#define F_NE (F_H17 + 1)
995 { "ne", 0, 0, 0, 1 },
e23e8ebe
AB		 996
997 /* ARC NPS400 Support: See comment near head of file. */
998#define F_NPS_CL (F_NE + 1)
999 { "cl", 0, 0, 0, 1 },
1000
1001#define F_NPS_FLAG (F_NPS_CL + 1)
1002 { "f", 1, 1, 20, 1 },
820f03ff
AB		 1003
1004#define F_NPS_R (F_NPS_FLAG + 1)
1005 { "r", 1, 1, 15, 1 },
a42a4f84
AB		 1006
1007#define F_NPS_RW (F_NPS_R + 1)
1008 { "rw", 0, 1, 7, 1 },
1009
1010#define F_NPS_RD (F_NPS_RW + 1)
1011 { "rd", 1, 1, 7, 1 },
1012
1013#define F_NPS_WFT (F_NPS_RD + 1)
1014 { "wft", 0, 0, 0, 1 },
1015
1016#define F_NPS_IE1 (F_NPS_WFT + 1)
1017 { "ie1", 1, 2, 8, 1 },
1018
1019#define F_NPS_IE2 (F_NPS_IE1 + 1)
1020 { "ie2", 2, 2, 8, 1 },
1021
1022#define F_NPS_IE12 (F_NPS_IE2 + 1)
1023 { "ie12", 3, 2, 8, 1 },
1024
1025#define F_NPS_SYNC_RD (F_NPS_IE12 + 1)
1026 { "rd", 0, 1, 6, 1 },
1027
1028#define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1)
1029 { "wr", 1, 1, 6, 1 },
1030
1031#define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1)
1032 { "off", 0, 0, 0, 1 },
1033
1034#define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1)
1035 { "restore", 0, 0, 0, 1 },
1036
886a2506 1037};
252b5132 1038
886a2506 1039const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
252b5132 1040
886a2506 1041/* Table of the flag classes.
252b5132 1042
886a2506
NC		 1043 The format of the table is
1044 CLASS {FLAG_CODE}. */
1045const struct arc_flag_class arc_flag_classes[] =
1046{
1047#define C_EMPTY 0
1ae8ab47 1048 { F_CLASS_NONE, { F_NULL } },
886a2506
NC		 1049
1050#define C_CC (C_EMPTY + 1)
1ae8ab47
AB		 1051 { F_CLASS_OPTIONAL, { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
1052 F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
1053 F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1054 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
1055 F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
1056 F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
886a2506
NC		 1057
1058#define C_AA_ADDR3 (C_CC + 1)
1059#define C_AA27 (C_CC + 1)
1ae8ab47 1060 { F_CLASS_OPTIONAL, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
886a2506
NC		 1061#define C_AA_ADDR9 (C_AA_ADDR3 + 1)
1062#define C_AA21 (C_AA_ADDR3 + 1)
1ae8ab47 1063 { F_CLASS_OPTIONAL, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
886a2506
NC		 1064#define C_AA_ADDR22 (C_AA_ADDR9 + 1)
1065#define C_AA8 (C_AA_ADDR9 + 1)
1ae8ab47 1066 { F_CLASS_OPTIONAL, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
886a2506
NC		 1067
1068#define C_F (C_AA_ADDR22 + 1)
1ae8ab47 1069 { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
886a2506 1070#define C_FHARD (C_F + 1)
1ae8ab47 1071 { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
886a2506
NC		 1072
1073#define C_T (C_FHARD + 1)
1ae8ab47 1074 { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
886a2506 1075#define C_D (C_T + 1)
1ae8ab47 1076 { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
886a2506
NC		 1077
1078#define C_DHARD (C_D + 1)
1ae8ab47 1079 { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
886a2506
NC		 1080
1081#define C_DI20 (C_DHARD + 1)
1ae8ab47 1082 { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
886a2506 1083#define C_DI16 (C_DI20 + 1)
1ae8ab47 1084 { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
886a2506 1085#define C_DI26 (C_DI16 + 1)
1ae8ab47 1086 { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
886a2506
NC		 1087
1088#define C_X25 (C_DI26 + 1)
1ae8ab47 1089 { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
886a2506 1090#define C_X15 (C_X25 + 1)
1ae8ab47 1091 { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
886a2506
NC		 1092#define C_XHARD (C_X15 + 1)
1093#define C_X (C_X15 + 1)
1ae8ab47 1094 { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
886a2506
NC		 1095
1096#define C_ZZ13 (C_X + 1)
1ae8ab47 1097 { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
886a2506 1098#define C_ZZ23 (C_ZZ13 + 1)
1ae8ab47 1099 { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
886a2506 1100#define C_ZZ29 (C_ZZ23 + 1)
1ae8ab47 1101 { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
886a2506
NC		 1102
1103#define C_AS (C_ZZ29 + 1)
1ae8ab47 1104 { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
886a2506
NC		 1105
1106#define C_NE (C_AS + 1)
1ae8ab47 1107 { F_CLASS_OPTIONAL, { F_NE, F_NULL}},
e23e8ebe
AB		 1108
1109 /* ARC NPS400 Support: See comment near head of file. */
1110#define C_NPS_CL (C_NE + 1)
1111 { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
1112
1113#define C_NPS_F (C_NPS_CL + 1)
1114 { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
820f03ff
AB		 1115
1116#define C_NPS_R (C_NPS_F + 1)
1117 { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}},
a42a4f84
AB		 1118
1119#define C_NPS_SCHD_RW (C_NPS_R + 1)
1120 { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}},
1121
1122#define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1)
1123 { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}},
1124
1125#define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1)
1126 { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}},
1127
1128#define C_NPS_SYNC (C_NPS_SCHD_IE + 1)
1129 { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}},
1130
1131#define C_NPS_HWS_OFF (C_NPS_SYNC + 1)
1132 { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}},
1133
1134#define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1)
1135 { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}},
1136
886a2506 1137};
252b5132 1138
886a2506 1139/* The operands table.
252b5132 1140
886a2506 1141 The format of the operands table is:
47b0e7ad 1142
886a2506
NC		 1143 BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
1144const struct arc_operand arc_operands[] =
0d2bcfaf 1145{
886a2506
NC		 1146 /* The fields are bits, shift, insert, extract, flags. The zero
1147 index is used to indicate end-of-list. */
1148#define UNUSED 0
1149 { 0, 0, 0, 0, 0, 0 },
1150 /* The plain integer register fields. Used by 32 bit
1151 instructions. */
1152#define RA (UNUSED + 1)
1153 { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
1154#define RB (RA + 1)
1155 { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
1156#define RC (RB + 1)
1157 { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
1158#define RBdup (RC + 1)
1159 { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
1160
1161#define RAD (RBdup + 1)
1162 { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
1163#define RCD (RAD + 1)
1164 { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
1165
1166 /* The plain integer register fields. Used by short
1167 instructions. */
1168#define RA16 (RCD + 1)
1169#define RA_S (RCD + 1)
1170 { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
1171#define RB16 (RA16 + 1)
1172#define RB_S (RA16 + 1)
1173 { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
1174#define RB16dup (RB16 + 1)
1175#define RB_Sdup (RB16 + 1)
1176 { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
1177#define RC16 (RB16dup + 1)
1178#define RC_S (RB16dup + 1)
1179 { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
1180#define R6H (RC16 + 1) /* 6bit register field 'h' used
1181 by V1 cpus. */
1182 { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
1183#define R5H (R6H + 1) /* 5bit register field 'h' used
1184 by V2 cpus. */
1185#define RH_S (R6H + 1) /* 5bit register field 'h' used
1186 by V2 cpus. */
1187 { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
1188#define R5Hdup (R5H + 1)
1189#define RH_Sdup (R5H + 1)
1190 { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
1191 insert_rhv2, extract_rhv2 },
1192
1193#define RG (R5Hdup + 1)
1194#define G_S (R5Hdup + 1)
1195 { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
1196
1197 /* Fix registers. */
1198#define R0 (RG + 1)
1199#define R0_S (RG + 1)
1200 { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
1201#define R1 (R0 + 1)
1202#define R1_S (R0 + 1)
1203 { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
1204#define R2 (R1 + 1)
1205#define R2_S (R1 + 1)
1206 { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
1207#define R3 (R2 + 1)
1208#define R3_S (R2 + 1)
1209 { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
8ddf6b2a 1210#define RSP (R3 + 1)
886a2506
NC		 1211#define SP_S (R3 + 1)
1212 { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
8ddf6b2a
CZ		 1213#define SPdup (RSP + 1)
1214#define SP_Sdup (RSP + 1)
886a2506
NC		 1215 { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
1216#define GP (SPdup + 1)
1217#define GP_S (SPdup + 1)
1218 { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
1219
1220#define PCL_S (GP + 1)
1221 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
1222
1223#define BLINK (PCL_S + 1)
1224#define BLINK_S (PCL_S + 1)
1225 { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
1226
1227#define ILINK1 (BLINK + 1)
1228 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
1229#define ILINK2 (ILINK1 + 1)
1230 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
1231
1232 /* Long immediate. */
1233#define LIMM (ILINK2 + 1)
1234#define LIMM_S (ILINK2 + 1)
1235 { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
1236#define LIMMdup (LIMM + 1)
1237 { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
1238
1239 /* Special operands. */
1240#define ZA (LIMMdup + 1)
1241#define ZB (LIMMdup + 1)
1242#define ZA_S (LIMMdup + 1)
1243#define ZB_S (LIMMdup + 1)
1244#define ZC_S (LIMMdup + 1)
1245 { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
1246
1247#define RRANGE_EL (ZA + 1)
1248 { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
1249 insert_rrange, extract_rrange},
1250#define FP_EL (RRANGE_EL + 1)
1251 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1252 insert_fpel, extract_fpel },
1253#define BLINK_EL (FP_EL + 1)
1254 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1255 insert_blinkel, extract_blinkel },
1256#define PCL_EL (BLINK_EL + 1)
1257 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1258 insert_pclel, extract_pclel },
1259
1260 /* Fake operand to handle the T flag. */
1261#define BRAKET (PCL_EL + 1)
1262#define BRAKETdup (PCL_EL + 1)
1263 { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
1264
1265 /* Fake operand to handle the T flag. */
1266#define FKT_T (BRAKET + 1)
1267 { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
1268 /* Fake operand to handle the T flag. */
1269#define FKT_NT (FKT_T + 1)
1270 { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
1271
1272 /* UIMM6_20 mask = 00000000000000000000111111000000. */
1273#define UIMM6_20 (FKT_NT + 1)
1274 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
1275
1276 /* SIMM12_20 mask = 00000000000000000000111111222222. */
1277#define SIMM12_20 (UIMM6_20 + 1)
1278 {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
1279
1280 /* SIMM3_5_S mask = 0000011100000000. */
1281#define SIMM3_5_S (SIMM12_20 + 1)
1282 {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
1283 insert_simm3s, extract_simm3s},
1284
1285 /* UIMM7_A32_11_S mask = 0000000000011111. */
1286#define UIMM7_A32_11_S (SIMM3_5_S + 1)
1287 {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1288 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
1289 extract_uimm7_a32_11_s},
1290
1291 /* UIMM7_9_S mask = 0000000001111111. */
1292#define UIMM7_9_S (UIMM7_A32_11_S + 1)
1293 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
1294
1295 /* UIMM3_13_S mask = 0000000000000111. */
1296#define UIMM3_13_S (UIMM7_9_S + 1)
1297 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
1298
1299 /* SIMM11_A32_7_S mask = 0000000111111111. */
1300#define SIMM11_A32_7_S (UIMM3_13_S + 1)
1301 {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1302 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
1303
1304 /* UIMM6_13_S mask = 0000000002220111. */
1305#define UIMM6_13_S (SIMM11_A32_7_S + 1)
1306 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
1307 /* UIMM5_11_S mask = 0000000000011111. */
1308#define UIMM5_11_S (UIMM6_13_S + 1)
1309 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
1310 extract_uimm5_11_s},
1311
1312 /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
1313#define SIMM9_A16_8 (UIMM5_11_S + 1)
1314 {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1315 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
1316 extract_simm9_a16_8},
1317
1318 /* UIMM6_8 mask = 00000000000000000000111111000000. */
1319#define UIMM6_8 (SIMM9_A16_8 + 1)
1320 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
1321
1322 /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
1323#define SIMM21_A16_5 (UIMM6_8 + 1)
1324 {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
1325 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE,
1326 insert_simm21_a16_5, extract_simm21_a16_5},
1327
1328 /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
1329#define SIMM25_A16_5 (SIMM21_A16_5 + 1)
1330 {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
1331 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
1332 insert_simm25_a16_5, extract_simm25_a16_5},
1333
1334 /* SIMM10_A16_7_S mask = 0000000111111111. */
1335#define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
1336 {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1337 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
1338 extract_simm10_a16_7_s},
1339
1340#define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1)
1341 {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1342 | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
1343
1344 /* SIMM7_A16_10_S mask = 0000000000111111. */
1345#define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
1346 {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1347 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
1348 extract_simm7_a16_10_s},
1349
1350 /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
1351#define SIMM21_A32_5 (SIMM7_A16_10_S + 1)
1352 {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1353 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
1354 extract_simm21_a32_5},
1355
1356 /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
1357#define SIMM25_A32_5 (SIMM21_A32_5 + 1)
1358 {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1359 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
1360 extract_simm25_a32_5},
1361
1362 /* SIMM13_A32_5_S mask = 0000011111111111. */
1363#define SIMM13_A32_5_S (SIMM25_A32_5 + 1)
1364 {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1365 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
1366 extract_simm13_a32_5_s},
1367
1368 /* SIMM8_A16_9_S mask = 0000000001111111. */
1369#define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
1370 {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1371 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
1372 extract_simm8_a16_9_s},
1373
1374 /* UIMM3_23 mask = 00000000000000000000000111000000. */
1375#define UIMM3_23 (SIMM8_A16_9_S + 1)
1376 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
1377
1378 /* UIMM10_6_S mask = 0000001111111111. */
1379#define UIMM10_6_S (UIMM3_23 + 1)
1380 {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
1381
1382 /* UIMM6_11_S mask = 0000002200011110. */
1383#define UIMM6_11_S (UIMM10_6_S + 1)
1384 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
1385
1386 /* SIMM9_8 mask = 00000000111111112000000000000000. */
1387#define SIMM9_8 (UIMM6_11_S + 1)
1388 {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
1389 insert_simm9_8, extract_simm9_8},
1390
1391 /* UIMM10_A32_8_S mask = 0000000011111111. */
1392#define UIMM10_A32_8_S (SIMM9_8 + 1)
1393 {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1394 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
1395 extract_uimm10_a32_8_s},
1396
1397 /* SIMM9_7_S mask = 0000000111111111. */
1398#define SIMM9_7_S (UIMM10_A32_8_S + 1)
1399 {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
1400 extract_simm9_7_s},
1401
1402 /* UIMM6_A16_11_S mask = 0000000000011111. */
1403#define UIMM6_A16_11_S (SIMM9_7_S + 1)
1404 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1405 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
1406 extract_uimm6_a16_11_s},
1407
1408 /* UIMM5_A32_11_S mask = 0000020000011000. */
1409#define UIMM5_A32_11_S (UIMM6_A16_11_S + 1)
1410 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1411 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
1412 extract_uimm5_a32_11_s},
1413
1414 /* SIMM11_A32_13_S mask = 0000022222200111. */
1415#define SIMM11_A32_13_S (UIMM5_A32_11_S + 1)
1416 {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1417 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
1418
1419 /* UIMM7_13_S mask = 0000000022220111. */
1420#define UIMM7_13_S (SIMM11_A32_13_S + 1)
1421 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
1422
1423 /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
1424#define UIMM6_A16_21 (UIMM7_13_S + 1)
1425 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1426 | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
1427
1428 /* UIMM7_11_S mask = 0000022200011110. */
1429#define UIMM7_11_S (UIMM6_A16_21 + 1)
1430 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
1431
1432 /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
1433#define UIMM7_A16_20 (UIMM7_11_S + 1)
1434 {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1435 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
1436 extract_uimm7_a16_20},
1437
1438 /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
1439#define SIMM13_A16_20 (UIMM7_A16_20 + 1)
1440 {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1441 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
1442 extract_simm13_a16_20},
1443
1444 /* UIMM8_8_S mask = 0000000011111111. */
1445#define UIMM8_8_S (SIMM13_A16_20 + 1)
1446 {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
1447
1448 /* W6 mask = 00000000000000000000111111000000. */
1449#define W6 (UIMM8_8_S + 1)
1450 {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
1451
1452 /* UIMM6_5_S mask = 0000011111100000. */
1453#define UIMM6_5_S (W6 + 1)
1454 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
e23e8ebe
AB		 1455
1456 /* ARC NPS400 Support: See comment near head of file. */
1457#define NPS_R_DST_3B (UIMM6_5_S + 1)
1458 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
1459
1460#define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
1461 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
1462
1463#define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
1464 { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_src2, extract_nps_3bit_src2 },
1465
1466#define NPS_R_DST (NPS_R_SRC2_3B + 1)
2cce10e7 1467 { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL },
e23e8ebe
AB		 1468
1469#define NPS_R_SRC1 (NPS_R_DST + 1)
2cce10e7 1470 { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
e23e8ebe
AB		 1471
1472#define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1)
1473 { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1474
1475#define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
1476 { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1477
1478#define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
820f03ff 1479 { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size, extract_nps_bitop_size },
e23e8ebe 1480
820f03ff
AB		 1481#define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1)
1482 { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size },
1483
1484#define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1)
1485 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size_2b, extract_nps_bitop_size_2b },
1486
1487#define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1)
1488 { 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 },
1489
1490#define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1)
e23e8ebe 1491 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
820f03ff
AB		 1492
1493#define NPS_RFLT_UIMM6 (NPS_UIMM16 + 1)
1494 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
886a2506 1495};
0d2bcfaf 1496
886a2506 1497const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
0d2bcfaf 1498
886a2506
NC		 1499const unsigned arc_Toperand = FKT_T;
1500const unsigned arc_NToperand = FKT_NT;
47b0e7ad 1501
886a2506 1502/* The opcode table.
0d2bcfaf 1503
886a2506 1504 The format of the opcode table is:
0d2bcfaf 1505
1328504b
AB		 1506 NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }.
1507
1508 The table is organised such that, where possible, all instructions with
1509 the same mnemonic are together in a block. When the assembler searches
1510 for a suitable instruction the entries are checked in table order, so
1511 more specific, or specialised cases should appear earlier in the table.
1512
1513 As an example, consider two instructions 'add a,b,u6' and 'add
1514 a,b,limm'. The first takes a 6-bit immediate that is encoded within the
1515 32-bit instruction, while the second takes a 32-bit immediate that is
1516 encoded in a follow-on 32-bit, making the total instruction length
1517 64-bits. In this case the u6 variant must appear first in the table, as
1518 all u6 immediates could also be encoded using the 'limm' extension,
1519 however, we want to use the shorter instruction wherever possible.
1520
1521 It is possible though to split instructions with the same mnemonic into
1522 multiple groups. However, the instructions are still checked in table
1523 order, even across groups. The only time that instructions with the
1524 same mnemonic should be split into different groups is when different
1525 variants of the instruction appear in different architectures, in which
1526 case, grouping all instructions from a particular architecture together
1527 might be preferable to merging the instruction into the main instruction
1528 table.
1529
1530 An example of this split instruction groups can be found with the 'sync'
1531 instruction. The core arc architecture provides a 'sync' instruction,
1532 while the nps instruction set extension provides 'sync.rd' and
1533 'sync.wr'. The rd/wr flags are instruction flags, not part of the
1534 mnemonic, so we end up with two groups for the sync instruction, the
1535 first within the core arc instruction table, and the second within the
1536 nps extension instructions. */
886a2506 1537const struct arc_opcode arc_opcodes[] =
0d2bcfaf 1538{
886a2506 1539#include "arc-tbl.h"
e23e8ebe 1540#include "arc-nps400-tbl.h"
f2dd8838 1541#include "arc-ext-tbl.h"
886a2506 1542};
0d2bcfaf 1543
886a2506 1544const unsigned arc_num_opcodes = ARRAY_SIZE (arc_opcodes);
252b5132 1545
886a2506
NC		 1546/* List with special cases instructions and the applicable flags. */
1547const struct arc_flag_special arc_flag_special_cases[] =
252b5132 1548{
886a2506
NC		 1549 { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1550 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1551 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1552 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1553 { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1554 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1555 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1556 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1557 { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1558 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1559 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1560 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1561 { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1562 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1563 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1564 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1565 { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1566 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1567 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1568 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1569 { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1570 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1571 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1572 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1573 { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1574 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1575 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1576 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1577 { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
1578 { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
1579};
252b5132 1580
886a2506 1581const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
252b5132 1582
886a2506 1583/* Relocations. */
886a2506
NC		 1584const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
1585{
24b368f8
CZ		 1586 { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
1587 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1588 { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
1589 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1590 { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
1591 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1592 { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
1593 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1594
1595 /* Next two entries will cover the undefined behavior ldb/stb with
1596 address scaling. */
1597 { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
1598 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
1599 { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
1600 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
1601
1602 { "sda", "ld", { F_ASFAKE, F_NULL },
1603 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
1604 { "sda", "st", { F_ASFAKE, F_NULL },
1605 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
1606 { "sda", "ldd", { F_ASFAKE, F_NULL },
1607 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
1608 { "sda", "std", { F_ASFAKE, F_NULL },
1609 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
886a2506
NC		 1610
1611 /* Short instructions. */
24b368f8
CZ		 1612 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
1613 { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
1614 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
1615 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
1616
1617 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
1618 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
1619
1620 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
1621 BFD_RELOC_ARC_S25H_PCREL_PLT },
1622 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
1623 BFD_RELOC_ARC_S21H_PCREL_PLT },
1624 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
1625 BFD_RELOC_ARC_S25W_PCREL_PLT },
1626 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
1627 BFD_RELOC_ARC_S21W_PCREL_PLT },
1628
1629 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
886a2506 1630};
252b5132 1631
886a2506 1632const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
252b5132 1633
886a2506 1634const struct arc_pseudo_insn arc_pseudo_insns[] =
0d2bcfaf 1635{
886a2506
NC		 1636 { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
1637 { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
1638 { BRAKETdup, 1, 0, 4} } },
1639 { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
1640 { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
1641 { BRAKETdup, 1, 0, 4} } },
1642
1643 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1644 { SIMM9_A16_8, 0, 0, 2 } } },
1645 { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1646 { SIMM9_A16_8, 0, 0, 2 } } },
1647 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1648 { SIMM9_A16_8, 0, 0, 2 } } },
1649 { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1650 { SIMM9_A16_8, 0, 0, 2 } } },
1651 { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1652 { SIMM9_A16_8, 0, 0, 2 } } },
1653
1654 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1655 { SIMM9_A16_8, 0, 0, 2 } } },
1656 { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1657 { SIMM9_A16_8, 0, 0, 2 } } },
1658 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1659 { SIMM9_A16_8, 0, 0, 2 } } },
1660 { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1661 { SIMM9_A16_8, 0, 0, 2 } } },
1662 { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1663 { SIMM9_A16_8, 0, 0, 2 } } },
1664
1665 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1666 { SIMM9_A16_8, 0, 0, 2 } } },
1667 { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1668 { SIMM9_A16_8, 0, 0, 2 } } },
1669 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1670 { SIMM9_A16_8, 0, 0, 2 } } },
1671 { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1672 { SIMM9_A16_8, 0, 0, 2 } } },
1673 { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1674 { SIMM9_A16_8, 0, 0, 2 } } },
1675
1676 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1677 { SIMM9_A16_8, 0, 0, 2 } } },
1678 { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1679 { SIMM9_A16_8, 0, 0, 2 } } },
1680 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1681 { SIMM9_A16_8, 0, 0, 2 } } },
1682 { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1683 { SIMM9_A16_8, 0, 0, 2 } } },
1684 { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1685 { SIMM9_A16_8, 0, 0, 2 } } },
1686};
0d2bcfaf 1687
886a2506
NC		 1688const unsigned arc_num_pseudo_insn =
1689 sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
0d2bcfaf 1690
886a2506 1691const struct arc_aux_reg arc_aux_regs[] =
0d2bcfaf 1692{
886a2506 1693#undef DEF
8ddf6b2a
CZ		 1694#define DEF(ADDR, SUBCLASS, NAME) \
1695 { ADDR, SUBCLASS, #NAME, sizeof (#NAME)-1 },
0d2bcfaf 1696
886a2506 1697#include "arc-regs.h"
0d2bcfaf 1698
886a2506
NC		 1699#undef DEF
1700};
0d2bcfaf 1701
886a2506 1702const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
4670103e
CZ		 1703
1704/* NOTE: The order of this array MUST be consistent with 'enum
1705 arc_rlx_types' located in tc-arc.h! */
1706const struct arc_opcode arc_relax_opcodes[] =
1707{
1708 { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
1709
1710 /* bl_s s13 11111sssssssssss. */
1711 { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1712 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1713 { SIMM13_A32_5_S }, { 0 }},
1714
1715 /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
1716 { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1717 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1718 { SIMM25_A32_5 }, { C_D }},
1719
1720 /* b_s s10 1111000sssssssss. */
1721 { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1722 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1723 { SIMM10_A16_7_S }, { 0 }},
1724
1725 /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
1726 { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1727 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1728 { SIMM25_A16_5 }, { C_D }},
1729
1730 /* add_s c,b,u3 01101bbbccc00uuu. Wants UIMM3_13_S_PCREL. */
1731 { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1732 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1733 { RC_S, RB_S, UIMM3_13_S }, { 0 }},
1734
1735 /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. Wants
1736 UIMM6_20_PCREL. */
1737 { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1738 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1739 { RA, RB, UIMM6_20 }, { C_F }},
1740
1741 /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
1742 { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1743 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1744 { RA, RB, LIMM }, { C_F }},
1745
1746 /* ld_s c,b,u7 10000bbbcccuuuuu. Wants UIMM7_A32_11_S_PCREL. */
1747 { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1748 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1749 { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
1750
1751 /* ld<.di><.aa><.x><zz> a,b,s9
1752 00010bbbssssssssSBBBDaaZZXAAAAAA. Wants SIMM9_8_PCREL. */
1753 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1754 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1755 { RA, BRAKET, RB, SIMM9_8, BRAKETdup },
1756 { C_ZZ23, C_DI20, C_AA21, C_X25 }},
1757
1758 /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
1759 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1760 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1761 { RA, BRAKET, RB, LIMM, BRAKETdup },
1762 { C_ZZ13, C_DI16, C_AA8, C_X15 }},
1763
1764 /* mov_s b,u8 11011bbbuuuuuuuu. Wants UIMM8_8_S_PCREL. */
1765 { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1766 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1767 { RB_S, UIMM8_8_S }, { 0 }},
1768
1769 /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. Wants
1770 SIMM12_20_PCREL. */
1771 { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1772 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1773 { RB, SIMM12_20 }, { C_F }},
1774
1775 /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
1776 { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1777 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1778 { RB, LIMM }, { C_F }},
1779
1780 /* sub_s c,b,u3 01101bbbccc01uuu. UIMM3_13_S_PCREL. */
1781 { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1782 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1783 { RC_S, RB_S, UIMM3_13_S }, { 0 }},
1784
1785 /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA.
1786 UIMM6_20_PCREL. */
1787 { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1788 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1789 { RA, RB, UIMM6_20 }, { C_F }},
1790
1791 /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
1792 { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1793 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1794 { RA, RB, LIMM }, { C_F }},
1795
1796 /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA.
1797 UIMM6_20_PCREL. */
1798 { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
1799 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }},
1800
1801 /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
1802 { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
1803 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
1804
1805 /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ.
1806 UIMM6_20_PCREL. */
1807 { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1808 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1809 { RB, UIMM6_20 }, { C_F, C_CC }},
1810
1811 /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
1812 { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1813 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1814 { RB, LIMM }, { C_F, C_CC }},
1815
1816 /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ.
1817 UIMM6_20_PCREL. */
1818 { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1819 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1820 { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
1821
1822 /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
1823 { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1824 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1825 { RB, RBdup, LIMM }, { C_F, C_CC }}
1826};
1827
1828const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);
GDB Binutils - Deliverables
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