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Fix compile time warning building gas for the NDS32 with gcc v6.1.1
[deliverable/binutils-gdb.git] / opcodes / arc-opc.c
CommitLineData
252b5132 1/* Opcode table for the ARC.
6f2750fe 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
bcee8eb8 5
9b201bb5
NC		 6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
252b5132 9 it under the terms of the GNU General Public License as published by
9b201bb5 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132
RH		 17
18 You should have received a copy of the GNU General Public License
0d2bcfaf 19 along with this program; if not, write to the Free Software Foundation,
f4321104 20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
252b5132 21
5bd67f35 22#include "sysdep.h"
252b5132 23#include <stdio.h>
d943fe33 24#include "bfd.h"
252b5132 25#include "opcode/arc.h"
47b0e7ad 26#include "opintl.h"
886a2506 27#include "libiberty.h"
252b5132 28
e23e8ebe
AB		 29/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
30 instructions. Support for this target is available when binutils is
31 configured and built for the 'arc*-mellanox-*-*' target. As far as
32 possible all ARC NPS400 features are built into all ARC target builds as
33 this reduces the chances that regressions might creep in. */
34
886a2506
NC		 35/* Insert RB register into a 32-bit opcode. */
36static unsigned
37insert_rb (unsigned insn,
38 int value,
39 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 40{
886a2506
NC		 41 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
42}
0d2bcfaf 43
886a2506
NC		 44static int
45extract_rb (unsigned insn ATTRIBUTE_UNUSED,
46 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47{
48 int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
0d2bcfaf 49
886a2506
NC		 50 if (value == 0x3e && invalid)
51 *invalid = TRUE; /* A limm operand, it should be extracted in a
52 different way. */
252b5132 53
886a2506
NC		 54 return value;
55}
252b5132 56
886a2506
NC		 57static unsigned
58insert_rad (unsigned insn,
59 int value,
60 const char **errmsg ATTRIBUTE_UNUSED)
61{
62 if (value & 0x01)
63 *errmsg = _("Improper register value.");
0d2bcfaf 64
886a2506
NC		 65 return insn | (value & 0x3F);
66}
0d2bcfaf 67
886a2506
NC		 68static unsigned
69insert_rcd (unsigned insn,
70 int value,
71 const char **errmsg ATTRIBUTE_UNUSED)
72{
73 if (value & 0x01)
74 *errmsg = _("Improper register value.");
0d2bcfaf 75
886a2506
NC		 76 return insn | ((value & 0x3F) << 6);
77}
252b5132 78
886a2506 79/* Dummy insert ZERO operand function. */
252b5132 80
886a2506
NC		 81static unsigned
82insert_za (unsigned insn,
83 int value,
84 const char **errmsg)
85{
86 if (value)
87 *errmsg = _("operand is not zero");
88 return insn;
89}
252b5132 90
886a2506
NC		 91/* Insert Y-bit in bbit/br instructions. This function is called only
92 when solving fixups. */
252b5132 93
886a2506
NC		 94static unsigned
95insert_Ybit (unsigned insn,
96 int value,
97 const char **errmsg ATTRIBUTE_UNUSED)
98{
99 if (value > 0)
100 insn |= 0x08;
252b5132 101
886a2506
NC		 102 return insn;
103}
252b5132 104
886a2506
NC		 105/* Insert Y-bit in bbit/br instructions. This function is called only
106 when solving fixups. */
252b5132 107
886a2506
NC		 108static unsigned
109insert_NYbit (unsigned insn,
110 int value,
111 const char **errmsg ATTRIBUTE_UNUSED)
112{
113 if (value < 0)
114 insn |= 0x08;
0d2bcfaf 115
886a2506
NC		 116 return insn;
117}
252b5132 118
886a2506 119/* Insert H register into a 16-bit opcode. */
252b5132 120
886a2506
NC		 121static unsigned
122insert_rhv1 (unsigned insn,
123 int value,
124 const char **errmsg ATTRIBUTE_UNUSED)
125{
126 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
127}
252b5132 128
886a2506
NC		 129static int
130extract_rhv1 (unsigned insn ATTRIBUTE_UNUSED,
131 bfd_boolean * invalid ATTRIBUTE_UNUSED)
132{
133 int value = 0;
252b5132 134
886a2506
NC		 135 return value;
136}
252b5132 137
886a2506 138/* Insert H register into a 16-bit opcode. */
252b5132 139
886a2506
NC		 140static unsigned
141insert_rhv2 (unsigned insn,
142 int value,
143 const char **errmsg)
0d2bcfaf 144{
886a2506
NC		 145 if (value == 0x1E)
146 *errmsg =
147 _("Register R30 is a limm indicator for this type of instruction.");
148 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
149}
252b5132 150
886a2506
NC		 151static int
152extract_rhv2 (unsigned insn ATTRIBUTE_UNUSED,
153 bfd_boolean * invalid ATTRIBUTE_UNUSED)
154{
155 int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
0d2bcfaf 156
886a2506
NC		 157 return value;
158}
0d2bcfaf 159
886a2506
NC		 160static unsigned
161insert_r0 (unsigned insn,
162 int value,
163 const char **errmsg ATTRIBUTE_UNUSED)
164{
165 if (value != 0)
166 *errmsg = _("Register must be R0.");
47b0e7ad
NC		 167 return insn;
168}
252b5132 169
886a2506
NC		 170static int
171extract_r0 (unsigned insn ATTRIBUTE_UNUSED,
172 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 173{
886a2506 174 return 0;
47b0e7ad 175}
252b5132 176
252b5132 177
886a2506
NC		 178static unsigned
179insert_r1 (unsigned insn,
180 int value,
181 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 182{
886a2506
NC		 183 if (value != 1)
184 *errmsg = _("Register must be R1.");
47b0e7ad 185 return insn;
252b5132
RH		 186}
187
886a2506
NC		 188static int
189extract_r1 (unsigned insn ATTRIBUTE_UNUSED,
190 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 191{
886a2506 192 return 1;
252b5132
RH		 193}
194
886a2506
NC		 195static unsigned
196insert_r2 (unsigned insn,
197 int value,
198 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 199{
886a2506
NC		 200 if (value != 2)
201 *errmsg = _("Register must be R2.");
47b0e7ad 202 return insn;
252b5132
RH		 203}
204
886a2506
NC		 205static int
206extract_r2 (unsigned insn ATTRIBUTE_UNUSED,
207 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 208{
886a2506 209 return 2;
252b5132
RH		 210}
211
886a2506
NC		 212static unsigned
213insert_r3 (unsigned insn,
214 int value,
215 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 216{
886a2506
NC		 217 if (value != 3)
218 *errmsg = _("Register must be R3.");
47b0e7ad 219 return insn;
0d2bcfaf
NC		 220}
221
886a2506
NC		 222static int
223extract_r3 (unsigned insn ATTRIBUTE_UNUSED,
224 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 225{
886a2506 226 return 3;
0d2bcfaf
NC		 227}
228
886a2506
NC		 229static unsigned
230insert_sp (unsigned insn,
231 int value,
232 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 233{
886a2506
NC		 234 if (value != 28)
235 *errmsg = _("Register must be SP.");
252b5132
RH		 236 return insn;
237}
238
886a2506
NC		 239static int
240extract_sp (unsigned insn ATTRIBUTE_UNUSED,
241 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 242{
886a2506 243 return 28;
0d2bcfaf
NC		 244}
245
886a2506
NC		 246static unsigned
247insert_gp (unsigned insn,
248 int value,
249 const char **errmsg ATTRIBUTE_UNUSED)
0d2bcfaf 250{
886a2506
NC		 251 if (value != 26)
252 *errmsg = _("Register must be GP.");
253 return insn;
0d2bcfaf
NC		 254}
255
886a2506
NC		 256static int
257extract_gp (unsigned insn ATTRIBUTE_UNUSED,
258 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 259{
886a2506 260 return 26;
0d2bcfaf
NC		 261}
262
886a2506
NC		 263static unsigned
264insert_pcl (unsigned insn,
265 int value,
266 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 267{
886a2506
NC		 268 if (value != 63)
269 *errmsg = _("Register must be PCL.");
252b5132
RH		 270 return insn;
271}
272
886a2506
NC		 273static int
274extract_pcl (unsigned insn ATTRIBUTE_UNUSED,
275 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 276{
886a2506 277 return 63;
0d2bcfaf
NC		 278}
279
886a2506
NC		 280static unsigned
281insert_blink (unsigned insn,
282 int value,
283 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 284{
886a2506
NC		 285 if (value != 31)
286 *errmsg = _("Register must be BLINK.");
252b5132
RH		 287 return insn;
288}
289
886a2506
NC		 290static int
291extract_blink (unsigned insn ATTRIBUTE_UNUSED,
292 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 293{
886a2506 294 return 31;
0d2bcfaf
NC		 295}
296
886a2506
NC		 297static unsigned
298insert_ilink1 (unsigned insn,
299 int value,
300 const char **errmsg ATTRIBUTE_UNUSED)
0d2bcfaf 301{
886a2506
NC		 302 if (value != 29)
303 *errmsg = _("Register must be ILINK1.");
252b5132
RH		 304 return insn;
305}
306
886a2506
NC		 307static int
308extract_ilink1 (unsigned insn ATTRIBUTE_UNUSED,
309 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 310{
886a2506 311 return 29;
252b5132
RH		 312}
313
886a2506
NC		 314static unsigned
315insert_ilink2 (unsigned insn,
316 int value,
317 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 318{
886a2506
NC		 319 if (value != 30)
320 *errmsg = _("Register must be ILINK2.");
252b5132
RH		 321 return insn;
322}
323
886a2506
NC		 324static int
325extract_ilink2 (unsigned insn ATTRIBUTE_UNUSED,
326 bfd_boolean * invalid ATTRIBUTE_UNUSED)
327{
328 return 30;
329}
252b5132 330
886a2506
NC		 331static unsigned
332insert_ras (unsigned insn,
333 int value,
334 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 335{
886a2506 336 switch (value)
0d2bcfaf 337 {
886a2506
NC		 338 case 0:
339 case 1:
340 case 2:
341 case 3:
342 insn |= value;
343 break;
344 case 12:
345 case 13:
346 case 14:
347 case 15:
348 insn |= (value - 8);
349 break;
350 default:
351 *errmsg = _("Register must be either r0-r3 or r12-r15.");
352 break;
0d2bcfaf 353 }
252b5132
RH		 354 return insn;
355}
252b5132 356
886a2506
NC		 357static int
358extract_ras (unsigned insn ATTRIBUTE_UNUSED,
359 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 360{
886a2506
NC		 361 int value = insn & 0x07;
362 if (value > 3)
363 return (value + 8);
364 else
365 return value;
47b0e7ad
NC		 366}
367
886a2506
NC		 368static unsigned
369insert_rbs (unsigned insn,
370 int value,
371 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 372{
886a2506 373 switch (value)
47b0e7ad 374 {
886a2506
NC		 375 case 0:
376 case 1:
377 case 2:
378 case 3:
379 insn |= value << 8;
380 break;
381 case 12:
382 case 13:
383 case 14:
384 case 15:
385 insn |= ((value - 8)) << 8;
386 break;
387 default:
388 *errmsg = _("Register must be either r0-r3 or r12-r15.");
389 break;
47b0e7ad 390 }
886a2506 391 return insn;
252b5132
RH		 392}
393
886a2506
NC		 394static int
395extract_rbs (unsigned insn ATTRIBUTE_UNUSED,
396 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 397{
886a2506
NC		 398 int value = (insn >> 8) & 0x07;
399 if (value > 3)
400 return (value + 8);
401 else
402 return value;
403}
252b5132 404
886a2506
NC		 405static unsigned
406insert_rcs (unsigned insn,
407 int value,
408 const char **errmsg ATTRIBUTE_UNUSED)
409{
410 switch (value)
252b5132 411 {
886a2506
NC		 412 case 0:
413 case 1:
414 case 2:
415 case 3:
416 insn |= value << 5;
417 break;
418 case 12:
419 case 13:
420 case 14:
421 case 15:
422 insn |= ((value - 8)) << 5;
423 break;
424 default:
425 *errmsg = _("Register must be either r0-r3 or r12-r15.");
426 break;
252b5132 427 }
886a2506
NC		 428 return insn;
429}
47b0e7ad 430
886a2506
NC		 431static int
432extract_rcs (unsigned insn ATTRIBUTE_UNUSED,
433 bfd_boolean * invalid ATTRIBUTE_UNUSED)
434{
435 int value = (insn >> 5) & 0x07;
436 if (value > 3)
437 return (value + 8);
252b5132 438 else
886a2506
NC		 439 return value;
440}
47b0e7ad 441
886a2506
NC		 442static unsigned
443insert_simm3s (unsigned insn,
444 int value,
445 const char **errmsg ATTRIBUTE_UNUSED)
446{
447 int tmp = 0;
448 switch (value)
47b0e7ad 449 {
886a2506
NC		 450 case -1:
451 tmp = 0x07;
47b0e7ad 452 break;
886a2506
NC		 453 case 0:
454 tmp = 0x00;
455 break;
456 case 1:
457 tmp = 0x01;
47b0e7ad 458 break;
886a2506
NC		 459 case 2:
460 tmp = 0x02;
47b0e7ad 461 break;
886a2506
NC		 462 case 3:
463 tmp = 0x03;
464 break;
465 case 4:
466 tmp = 0x04;
467 break;
468 case 5:
469 tmp = 0x05;
470 break;
471 case 6:
472 tmp = 0x06;
473 break;
474 default:
475 *errmsg = _("Accepted values are from -1 to 6.");
47b0e7ad
NC		 476 break;
477 }
478
886a2506
NC		 479 insn |= tmp << 8;
480 return insn;
47b0e7ad
NC		 481}
482
886a2506
NC		 483static int
484extract_simm3s (unsigned insn ATTRIBUTE_UNUSED,
485 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 486{
886a2506
NC		 487 int value = (insn >> 8) & 0x07;
488 if (value == 7)
489 return -1;
47b0e7ad 490 else
886a2506 491 return value;
47b0e7ad
NC		 492}
493
886a2506
NC		 494static unsigned
495insert_rrange (unsigned insn,
496 int value,
497 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 498{
886a2506
NC		 499 int reg1 = (value >> 16) & 0xFFFF;
500 int reg2 = value & 0xFFFF;
501 if (reg1 != 13)
502 {
503 *errmsg = _("First register of the range should be r13.");
504 return insn;
505 }
506 if (reg2 < 13 || reg2 > 26)
507 {
508 *errmsg = _("Last register of the range doesn't fit.");
509 return insn;
510 }
511 insn |= ((reg2 - 12) & 0x0F) << 1;
512 return insn;
47b0e7ad
NC		 513}
514
886a2506
NC		 515static int
516extract_rrange (unsigned insn ATTRIBUTE_UNUSED,
517 bfd_boolean * invalid ATTRIBUTE_UNUSED)
518{
519 return (insn >> 1) & 0x0F;
520}
47b0e7ad 521
886a2506
NC		 522static unsigned
523insert_fpel (unsigned insn,
524 int value,
525 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 526{
886a2506
NC		 527 if (value != 27)
528 {
529 *errmsg = _("Invalid register number, should be fp.");
530 return insn;
531 }
47b0e7ad 532
886a2506
NC		 533 insn |= 0x0100;
534 return insn;
47b0e7ad
NC		 535}
536
886a2506
NC		 537static int
538extract_fpel (unsigned insn ATTRIBUTE_UNUSED,
539 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 540{
886a2506 541 return (insn & 0x0100) ? 27 : -1;
47b0e7ad
NC		 542}
543
886a2506
NC		 544static unsigned
545insert_blinkel (unsigned insn,
546 int value,
547 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 548{
886a2506 549 if (value != 31)
47b0e7ad 550 {
886a2506
NC		 551 *errmsg = _("Invalid register number, should be blink.");
552 return insn;
47b0e7ad 553 }
47b0e7ad 554
886a2506
NC		 555 insn |= 0x0200;
556 return insn;
47b0e7ad
NC		 557}
558
886a2506
NC		 559static int
560extract_blinkel (unsigned insn ATTRIBUTE_UNUSED,
561 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 562{
886a2506
NC		 563 return (insn & 0x0200) ? 31 : -1;
564}
47b0e7ad 565
886a2506
NC		 566static unsigned
567insert_pclel (unsigned insn,
568 int value,
569 const char **errmsg ATTRIBUTE_UNUSED)
570{
571 if (value != 63)
47b0e7ad 572 {
886a2506
NC		 573 *errmsg = _("Invalid register number, should be pcl.");
574 return insn;
47b0e7ad 575 }
47b0e7ad 576
886a2506
NC		 577 insn |= 0x0400;
578 return insn;
579}
47b0e7ad 580
886a2506
NC		 581static int
582extract_pclel (unsigned insn ATTRIBUTE_UNUSED,
583 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 584{
886a2506 585 return (insn & 0x0400) ? 63 : -1;
47b0e7ad 586}
47b0e7ad 587
886a2506
NC		 588#define INSERT_W6
589/* mask = 00000000000000000000111111000000
590 insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
591static unsigned
592insert_w6 (unsigned insn ATTRIBUTE_UNUSED,
593 int value ATTRIBUTE_UNUSED,
594 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 595{
886a2506 596 insn |= ((value >> 0) & 0x003f) << 6;
47b0e7ad 597
886a2506
NC		 598 return insn;
599}
47b0e7ad 600
886a2506
NC		 601#define EXTRACT_W6
602/* mask = 00000000000000000000111111000000. */
603static int
604extract_w6 (unsigned insn ATTRIBUTE_UNUSED,
605 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 606{
886a2506 607 unsigned value = 0;
47b0e7ad 608
886a2506 609 value |= ((insn >> 6) & 0x003f) << 0;
47b0e7ad 610
886a2506
NC		 611 return value;
612}
47b0e7ad 613
886a2506
NC		 614#define INSERT_G_S
615/* mask = 0000011100022000
616 insn = 01000ggghhhGG0HH. */
617static unsigned
618insert_g_s (unsigned insn ATTRIBUTE_UNUSED,
619 int value ATTRIBUTE_UNUSED,
620 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 621{
886a2506
NC		 622 insn |= ((value >> 0) & 0x0007) << 8;
623 insn |= ((value >> 3) & 0x0003) << 3;
252b5132 624
886a2506
NC		 625 return insn;
626}
252b5132 627
886a2506
NC		 628#define EXTRACT_G_S
629/* mask = 0000011100022000. */
630static int
631extract_g_s (unsigned insn ATTRIBUTE_UNUSED,
632 bfd_boolean * invalid ATTRIBUTE_UNUSED)
633{
634 int value = 0;
252b5132 635
886a2506
NC		 636 value |= ((insn >> 8) & 0x0007) << 0;
637 value |= ((insn >> 3) & 0x0003) << 3;
252b5132 638
886a2506
NC		 639 /* Extend the sign. */
640 int signbit = 1 << (6 - 1);
641 value = (value ^ signbit) - signbit;
252b5132 642
886a2506 643 return value;
252b5132
RH		 644}
645
e23e8ebe
AB		 646/* ARC NPS400 Support: See comment near head of file. */
647static unsigned
648insert_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
649 int value ATTRIBUTE_UNUSED,
650 const char **errmsg ATTRIBUTE_UNUSED)
651{
652 switch (value)
653 {
654 case 0:
655 case 1:
656 case 2:
657 case 3:
658 insn |= value << 24;
659 break;
660 case 12:
661 case 13:
662 case 14:
663 case 15:
664 insn |= (value - 8) << 24;
665 break;
666 default:
667 *errmsg = _("Register must be either r0-r3 or r12-r15.");
668 break;
669 }
670 return insn;
671}
672
673static int
674extract_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
675 bfd_boolean * invalid ATTRIBUTE_UNUSED)
676{
677 int value = (insn >> 24) & 0x07;
678 if (value > 3)
679 return (value + 8);
680 else
681 return value;
682}
683
4eb6f892
AB		 684static unsigned
685insert_nps_3bit_dst_short (unsigned insn ATTRIBUTE_UNUSED,
686 int value ATTRIBUTE_UNUSED,
687 const char **errmsg ATTRIBUTE_UNUSED)
688{
689 switch (value)
690 {
691 case 0:
692 case 1:
693 case 2:
694 case 3:
695 insn |= value << 8;
696 break;
697 case 12:
698 case 13:
699 case 14:
700 case 15:
701 insn |= (value - 8) << 8;
702 break;
703 default:
704 *errmsg = _("Register must be either r0-r3 or r12-r15.");
705 break;
706 }
707 return insn;
708}
709
710static int
711extract_nps_3bit_dst_short (unsigned insn ATTRIBUTE_UNUSED,
712 bfd_boolean * invalid ATTRIBUTE_UNUSED)
713{
714 int value = (insn >> 8) & 0x07;
715 if (value > 3)
716 return (value + 8);
717 else
718 return value;
719}
720
e23e8ebe
AB		 721static unsigned
722insert_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
723 int value ATTRIBUTE_UNUSED,
724 const char **errmsg ATTRIBUTE_UNUSED)
725{
726 switch (value)
727 {
728 case 0:
729 case 1:
730 case 2:
731 case 3:
732 insn |= value << 21;
733 break;
734 case 12:
735 case 13:
736 case 14:
737 case 15:
738 insn |= (value - 8) << 21;
739 break;
740 default:
741 *errmsg = _("Register must be either r0-r3 or r12-r15.");
742 break;
743 }
744 return insn;
745}
746
747static int
748extract_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
749 bfd_boolean * invalid ATTRIBUTE_UNUSED)
750{
751 int value = (insn >> 21) & 0x07;
752 if (value > 3)
753 return (value + 8);
754 else
755 return value;
756}
757
4eb6f892
AB		 758static unsigned
759insert_nps_3bit_src2_short (unsigned insn ATTRIBUTE_UNUSED,
760 int value ATTRIBUTE_UNUSED,
761 const char **errmsg ATTRIBUTE_UNUSED)
762{
763 switch (value)
764 {
765 case 0:
766 case 1:
767 case 2:
768 case 3:
769 insn |= value << 5;
770 break;
771 case 12:
772 case 13:
773 case 14:
774 case 15:
775 insn |= (value - 8) << 5;
776 break;
777 default:
778 *errmsg = _("Register must be either r0-r3 or r12-r15.");
779 break;
780 }
781 return insn;
782}
783
784static int
785extract_nps_3bit_src2_short (unsigned insn ATTRIBUTE_UNUSED,
786 bfd_boolean * invalid ATTRIBUTE_UNUSED)
787{
788 int value = (insn >> 5) & 0x07;
789 if (value > 3)
790 return (value + 8);
791 else
792 return value;
793}
794
820f03ff
AB		 795static unsigned
796insert_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED,
797 int value ATTRIBUTE_UNUSED,
798 const char **errmsg ATTRIBUTE_UNUSED)
799{
800 switch (value)
801 {
802 case 1:
803 value = 0;
804 break;
805 case 2:
806 value = 1;
807 break;
808 case 4:
809 value = 2;
810 break;
811 case 8:
812 value = 3;
813 break;
814 default:
815 value = 0;
816 *errmsg = _("Invalid size, should be 1, 2, 4, or 8.");
817 break;
818 }
819
820 insn |= value << 10;
821 return insn;
822}
823
824static int
825extract_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED,
826 bfd_boolean * invalid ATTRIBUTE_UNUSED)
827{
828 return 1 << ((insn >> 10) & 0x3);
829}
830
831static unsigned
832insert_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED,
833 int value ATTRIBUTE_UNUSED,
834 const char **errmsg ATTRIBUTE_UNUSED)
835{
836 insn |= ((value >> 5) & 7) << 12;
837 insn |= (value & 0x1f);
838 return insn;
839}
840
841static int
842extract_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED,
843 bfd_boolean * invalid ATTRIBUTE_UNUSED)
844{
845 return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
846}
847
848static unsigned
849insert_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED,
850 int value ATTRIBUTE_UNUSED,
851 const char **errmsg ATTRIBUTE_UNUSED)
852{
853 switch (value)
854 {
855 case 1:
856 case 2:
857 case 4:
858 break;
859
860 default:
861 *errmsg = _("invalid immediate, must be 1, 2, or 4");
862 value = 0;
863 }
864
865 insn |= (value << 6);
866 return insn;
867}
868
869static int
870extract_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED,
871 bfd_boolean * invalid ATTRIBUTE_UNUSED)
872{
873 return (insn >> 6) & 0x3f;
874}
875
876static unsigned
877insert_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED,
878 int value ATTRIBUTE_UNUSED,
879 const char **errmsg ATTRIBUTE_UNUSED)
880{
881 insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10));
882 return insn;
883}
884
885static int
886extract_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED,
887 bfd_boolean * invalid ATTRIBUTE_UNUSED)
888{
889 return (insn & 0x1f);
890}
891
4b0c052e
AB		 892static unsigned
893insert_nps_cmem_uimm16 (unsigned insn ATTRIBUTE_UNUSED,
894 int value ATTRIBUTE_UNUSED,
895 const char **errmsg ATTRIBUTE_UNUSED)
896{
897 int top = (value >> 16) & 0xffff;
898 if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE)
899 *errmsg = _("invalid value for CMEM ld/st immediate");
900 insn |= (value & 0xffff);
901 return insn;
902}
903
904static int
905extract_nps_cmem_uimm16 (unsigned insn ATTRIBUTE_UNUSED,
906 bfd_boolean * invalid ATTRIBUTE_UNUSED)
907{
908 return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff);
909}
910
537aefaf
AB		 911#define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \
912static unsigned \
913insert_nps_##NAME##_pos (unsigned insn ATTRIBUTE_UNUSED, \
914 int value ATTRIBUTE_UNUSED, \
915 const char **errmsg ATTRIBUTE_UNUSED) \
916{ \
917 switch (value) \
918 { \
919 case 0: \
920 case 8: \
921 case 16: \
922 case 24: \
923 value = value / 8; \
924 break; \
925 default: \
926 *errmsg = _("Invalid position, should be 0, 8, 16, or 24."); \
927 value = 0; \
928 } \
929 insn |= (value << SHIFT); \
930 return insn; \
931} \
932 \
933static int \
934extract_nps_##NAME##_pos (unsigned insn ATTRIBUTE_UNUSED, \
935 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
936{ \
937 return ((insn >> SHIFT) & 0x3) * 8; \
938}
939
940MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12)
941MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10)
942
943#define MAKE_SIZE_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT)\
944static unsigned \
945insert_nps_##NAME##_size (unsigned insn ATTRIBUTE_UNUSED, \
946 int value ATTRIBUTE_UNUSED, \
947 const char **errmsg ATTRIBUTE_UNUSED) \
948 { \
949 if (value < LOWER || value > 32) \
950 { \
951 *errmsg = _("Invalid size, value must be " \
952 #LOWER " to " #UPPER "."); \
953 return insn; \
954 } \
955 value -= BIAS; \
956 insn |= (value << SHIFT); \
957 return insn; \
958 } \
959 \
960static int \
961extract_nps_##NAME##_size (unsigned insn ATTRIBUTE_UNUSED, \
962 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
963{ \
964 return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \
965}
966
967MAKE_SIZE_INSERT_EXTRACT_FUNCS(addb,2,32,5,1,5)
968MAKE_SIZE_INSERT_EXTRACT_FUNCS(andb,1,32,5,1,5)
969MAKE_SIZE_INSERT_EXTRACT_FUNCS(fxorb,8,32,5,8,5)
970MAKE_SIZE_INSERT_EXTRACT_FUNCS(wxorb,16,32,5,16,5)
971MAKE_SIZE_INSERT_EXTRACT_FUNCS(bitop,1,32,5,1,10)
972MAKE_SIZE_INSERT_EXTRACT_FUNCS(qcmp,1,8,3,1,9)
4eb6f892
AB		 973MAKE_SIZE_INSERT_EXTRACT_FUNCS(bitop1,1,32,5,1,20)
974MAKE_SIZE_INSERT_EXTRACT_FUNCS(bitop2,1,32,5,1,25)
537aefaf
AB		 975
976static int
977extract_nps_qcmp_m3 (unsigned insn ATTRIBUTE_UNUSED,
978 bfd_boolean * invalid ATTRIBUTE_UNUSED)
979{
980 int m3 = (insn >> 5) & 0xf;
981 if (m3 == 0xf)
982 *invalid = TRUE;
983 return m3;
984}
985
986static int
987extract_nps_qcmp_m2 (unsigned insn ATTRIBUTE_UNUSED,
988 bfd_boolean * invalid ATTRIBUTE_UNUSED)
989{
990 bfd_boolean tmp_invalid = FALSE;
991 int m2 = (insn >> 15) & 0x1;
992 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
993
994 if (m2 == 0 && m3 == 0xf)
995 *invalid = TRUE;
996 return m2;
997}
998
999static int
1000extract_nps_qcmp_m1 (unsigned insn ATTRIBUTE_UNUSED,
1001 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1002{
1003 bfd_boolean tmp_invalid = FALSE;
1004 int m1 = (insn >> 14) & 0x1;
1005 int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid);
1006 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
1007
1008 if (m1 == 0 && m2 == 0 && m3 == 0xf)
1009 *invalid = TRUE;
1010 return m1;
1011}
1012
1013static unsigned
1014insert_nps_calc_entry_size (unsigned insn ATTRIBUTE_UNUSED,
1015 int value ATTRIBUTE_UNUSED,
1016 const char **errmsg ATTRIBUTE_UNUSED)
1017{
1018 unsigned pwr;
1019
1020 if (value < 1 || value > 256)
1021 {
1022 *errmsg = _("value out of range 1 - 256");
1023 return 0;
1024 }
1025
1026 for (pwr = 0; (value & 1) == 0; value >>= 1)
1027 ++pwr;
1028
1029 if (value != 1)
1030 {
1031 *errmsg = _("value must be power of 2");
1032 return 0;
1033 }
1034
1035 return insn | (pwr << 8);
1036}
1037
1038static int
1039extract_nps_calc_entry_size (unsigned insn ATTRIBUTE_UNUSED,
1040 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1041{
1042 unsigned entry_size = (insn >> 8) & 0xf;
1043 return 1 << entry_size;
1044}
1045
4eb6f892
AB		 1046static unsigned
1047insert_nps_bitop_mod4_msb (unsigned insn ATTRIBUTE_UNUSED,
1048 int value ATTRIBUTE_UNUSED,
1049 const char **errmsg ATTRIBUTE_UNUSED)
1050{
1051 return insn | ((value & 0x2) << 30);
1052}
1053
1054static int
1055extract_nps_bitop_mod4_msb (unsigned insn ATTRIBUTE_UNUSED,
1056 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1057{
1058 return (insn >> 30) & 0x2;
1059}
1060
1061static unsigned
1062insert_nps_bitop_mod4_lsb (unsigned insn ATTRIBUTE_UNUSED,
1063 int value ATTRIBUTE_UNUSED,
1064 const char **errmsg ATTRIBUTE_UNUSED)
1065{
1066 return insn | ((value & 0x1) << 15);
1067}
1068
1069static int
1070extract_nps_bitop_mod4_lsb (unsigned insn ATTRIBUTE_UNUSED,
1071 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1072{
1073 return (insn >> 15) & 0x1;
1074}
1075
1076static unsigned
1077insert_nps_bitop_dst_pos3_pos4 (unsigned insn ATTRIBUTE_UNUSED,
1078 int value ATTRIBUTE_UNUSED,
1079 const char **errmsg ATTRIBUTE_UNUSED)
1080{
1081 return insn | (value << 10) | (value << 5);
1082}
1083
1084static int
1085extract_nps_bitop_dst_pos3_pos4 (unsigned insn ATTRIBUTE_UNUSED,
1086 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1087{
1088 if (((insn >> 10) & 0x1f) != ((insn >> 5) & 0x1f))
1089 *invalid = TRUE;
1090 return ((insn >> 5) & 0x1f);
1091}
1092
1093static unsigned
1094insert_nps_bitop_ins_ext (unsigned insn ATTRIBUTE_UNUSED,
1095 int value ATTRIBUTE_UNUSED,
1096 const char **errmsg ATTRIBUTE_UNUSED)
1097{
1098 if (value < 0 || value > 28)
1099 *errmsg = _("Value must be in the range 0 to 28");
1100 return insn | (value << 20);
1101}
1102
1103static int
1104extract_nps_bitop_ins_ext (unsigned insn ATTRIBUTE_UNUSED,
1105 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1106{
1107 int value = (insn >> 20) & 0x1f;
1108 if (value > 28)
1109 *invalid = TRUE;
1110 return value;
1111}
1112
886a2506
NC		 1113/* Include the generic extract/insert functions. Order is important
1114 as some of the functions present in the .h may be disabled via
1115 defines. */
1116#include "arc-fxi.h"
252b5132 1117
886a2506 1118/* The flag operands table.
252b5132 1119
886a2506
NC		 1120 The format of the table is
1121 NAME CODE BITS SHIFT FAVAIL. */
1122const struct arc_flag_operand arc_flag_operands[] =
1123{
1124#define F_NULL 0
1125 { 0, 0, 0, 0, 0},
1126#define F_ALWAYS (F_NULL + 1)
1127 { "al", 0, 0, 0, 0 },
1128#define F_RA (F_ALWAYS + 1)
1129 { "ra", 0, 0, 0, 0 },
1130#define F_EQUAL (F_RA + 1)
1131 { "eq", 1, 5, 0, 1 },
1132#define F_ZERO (F_EQUAL + 1)
1133 { "z", 1, 5, 0, 0 },
1134#define F_NOTEQUAL (F_ZERO + 1)
1135 { "ne", 2, 5, 0, 1 },
1136#define F_NOTZERO (F_NOTEQUAL + 1)
1137 { "nz", 2, 5, 0, 0 },
1138#define F_POZITIVE (F_NOTZERO + 1)
1139 { "p", 3, 5, 0, 1 },
1140#define F_PL (F_POZITIVE + 1)
1141 { "pl", 3, 5, 0, 0 },
1142#define F_NEGATIVE (F_PL + 1)
1143 { "n", 4, 5, 0, 1 },
1144#define F_MINUS (F_NEGATIVE + 1)
1145 { "mi", 4, 5, 0, 0 },
1146#define F_CARRY (F_MINUS + 1)
1147 { "c", 5, 5, 0, 1 },
1148#define F_CARRYSET (F_CARRY + 1)
1149 { "cs", 5, 5, 0, 0 },
1150#define F_LOWER (F_CARRYSET + 1)
1151 { "lo", 5, 5, 0, 0 },
1152#define F_CARRYCLR (F_LOWER + 1)
1153 { "cc", 6, 5, 0, 0 },
1154#define F_NOTCARRY (F_CARRYCLR + 1)
1155 { "nc", 6, 5, 0, 1 },
1156#define F_HIGHER (F_NOTCARRY + 1)
1157 { "hs", 6, 5, 0, 0 },
1158#define F_OVERFLOWSET (F_HIGHER + 1)
1159 { "vs", 7, 5, 0, 0 },
1160#define F_OVERFLOW (F_OVERFLOWSET + 1)
1161 { "v", 7, 5, 0, 1 },
1162#define F_NOTOVERFLOW (F_OVERFLOW + 1)
1163 { "nv", 8, 5, 0, 1 },
1164#define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
1165 { "vc", 8, 5, 0, 0 },
1166#define F_GT (F_OVERFLOWCLR + 1)
1167 { "gt", 9, 5, 0, 1 },
1168#define F_GE (F_GT + 1)
1169 { "ge", 10, 5, 0, 1 },
1170#define F_LT (F_GE + 1)
1171 { "lt", 11, 5, 0, 1 },
1172#define F_LE (F_LT + 1)
1173 { "le", 12, 5, 0, 1 },
1174#define F_HI (F_LE + 1)
1175 { "hi", 13, 5, 0, 1 },
1176#define F_LS (F_HI + 1)
1177 { "ls", 14, 5, 0, 1 },
1178#define F_PNZ (F_LS + 1)
1179 { "pnz", 15, 5, 0, 1 },
1180
1181 /* FLAG. */
1182#define F_FLAG (F_PNZ + 1)
1183 { "f", 1, 1, 15, 1 },
1184#define F_FFAKE (F_FLAG + 1)
1185 { "f", 0, 0, 0, 1 },
1186
1187 /* Delay slot. */
1188#define F_ND (F_FFAKE + 1)
1189 { "nd", 0, 1, 5, 0 },
1190#define F_D (F_ND + 1)
1191 { "d", 1, 1, 5, 1 },
1192#define F_DFAKE (F_D + 1)
1193 { "d", 0, 0, 0, 1 },
1194
1195 /* Data size. */
1196#define F_SIZEB1 (F_DFAKE + 1)
1197 { "b", 1, 2, 1, 1 },
1198#define F_SIZEB7 (F_SIZEB1 + 1)
1199 { "b", 1, 2, 7, 1 },
1200#define F_SIZEB17 (F_SIZEB7 + 1)
1201 { "b", 1, 2, 17, 1 },
1202#define F_SIZEW1 (F_SIZEB17 + 1)
1203 { "w", 2, 2, 1, 0 },
1204#define F_SIZEW7 (F_SIZEW1 + 1)
1205 { "w", 2, 2, 7, 0 },
1206#define F_SIZEW17 (F_SIZEW7 + 1)
1207 { "w", 2, 2, 17, 0 },
1208
1209 /* Sign extension. */
1210#define F_SIGN6 (F_SIZEW17 + 1)
1211 { "x", 1, 1, 6, 1 },
1212#define F_SIGN16 (F_SIGN6 + 1)
1213 { "x", 1, 1, 16, 1 },
1214#define F_SIGNX (F_SIGN16 + 1)
1215 { "x", 0, 0, 0, 1 },
1216
1217 /* Address write-back modes. */
1218#define F_A3 (F_SIGNX + 1)
1219 { "a", 1, 2, 3, 0 },
1220#define F_A9 (F_A3 + 1)
1221 { "a", 1, 2, 9, 0 },
1222#define F_A22 (F_A9 + 1)
1223 { "a", 1, 2, 22, 0 },
1224#define F_AW3 (F_A22 + 1)
1225 { "aw", 1, 2, 3, 1 },
1226#define F_AW9 (F_AW3 + 1)
1227 { "aw", 1, 2, 9, 1 },
1228#define F_AW22 (F_AW9 + 1)
1229 { "aw", 1, 2, 22, 1 },
1230#define F_AB3 (F_AW22 + 1)
1231 { "ab", 2, 2, 3, 1 },
1232#define F_AB9 (F_AB3 + 1)
1233 { "ab", 2, 2, 9, 1 },
1234#define F_AB22 (F_AB9 + 1)
1235 { "ab", 2, 2, 22, 1 },
1236#define F_AS3 (F_AB22 + 1)
1237 { "as", 3, 2, 3, 1 },
1238#define F_AS9 (F_AS3 + 1)
1239 { "as", 3, 2, 9, 1 },
1240#define F_AS22 (F_AS9 + 1)
1241 { "as", 3, 2, 22, 1 },
1242#define F_ASFAKE (F_AS22 + 1)
1243 { "as", 0, 0, 0, 1 },
1244
1245 /* Cache bypass. */
1246#define F_DI5 (F_ASFAKE + 1)
1247 { "di", 1, 1, 5, 1 },
1248#define F_DI11 (F_DI5 + 1)
1249 { "di", 1, 1, 11, 1 },
1250#define F_DI15 (F_DI11 + 1)
1251 { "di", 1, 1, 15, 1 },
1252
1253 /* ARCv2 specific. */
1254#define F_NT (F_DI15 + 1)
1255 { "nt", 0, 1, 3, 1},
1256#define F_T (F_NT + 1)
1257 { "t", 1, 1, 3, 1},
1258#define F_H1 (F_T + 1)
1259 { "h", 2, 2, 1, 1 },
1260#define F_H7 (F_H1 + 1)
1261 { "h", 2, 2, 7, 1 },
1262#define F_H17 (F_H7 + 1)
1263 { "h", 2, 2, 17, 1 },
1264
1265 /* Fake Flags. */
1266#define F_NE (F_H17 + 1)
1267 { "ne", 0, 0, 0, 1 },
e23e8ebe
AB		 1268
1269 /* ARC NPS400 Support: See comment near head of file. */
1270#define F_NPS_CL (F_NE + 1)
1271 { "cl", 0, 0, 0, 1 },
1272
1273#define F_NPS_FLAG (F_NPS_CL + 1)
1274 { "f", 1, 1, 20, 1 },
820f03ff
AB		 1275
1276#define F_NPS_R (F_NPS_FLAG + 1)
1277 { "r", 1, 1, 15, 1 },
a42a4f84
AB		 1278
1279#define F_NPS_RW (F_NPS_R + 1)
1280 { "rw", 0, 1, 7, 1 },
1281
1282#define F_NPS_RD (F_NPS_RW + 1)
1283 { "rd", 1, 1, 7, 1 },
1284
1285#define F_NPS_WFT (F_NPS_RD + 1)
1286 { "wft", 0, 0, 0, 1 },
1287
1288#define F_NPS_IE1 (F_NPS_WFT + 1)
1289 { "ie1", 1, 2, 8, 1 },
1290
1291#define F_NPS_IE2 (F_NPS_IE1 + 1)
1292 { "ie2", 2, 2, 8, 1 },
1293
1294#define F_NPS_IE12 (F_NPS_IE2 + 1)
1295 { "ie12", 3, 2, 8, 1 },
1296
1297#define F_NPS_SYNC_RD (F_NPS_IE12 + 1)
1298 { "rd", 0, 1, 6, 1 },
1299
1300#define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1)
1301 { "wr", 1, 1, 6, 1 },
1302
1303#define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1)
1304 { "off", 0, 0, 0, 1 },
1305
1306#define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1)
1307 { "restore", 0, 0, 0, 1 },
1308
537aefaf
AB		 1309#define F_NPS_SX (F_NPS_HWS_RESTORE + 1)
1310 { "sx", 1, 1, 14, 1 },
1311
1312#define F_NPS_AR (F_NPS_SX + 1)
1313 { "ar", 0, 1, 0, 1 },
1314
1315#define F_NPS_AL (F_NPS_AR + 1)
1316 { "al", 1, 1, 0, 1 },
886a2506 1317};
252b5132 1318
886a2506 1319const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
252b5132 1320
886a2506 1321/* Table of the flag classes.
252b5132 1322
886a2506
NC		 1323 The format of the table is
1324 CLASS {FLAG_CODE}. */
1325const struct arc_flag_class arc_flag_classes[] =
1326{
1327#define C_EMPTY 0
1ae8ab47 1328 { F_CLASS_NONE, { F_NULL } },
886a2506
NC		 1329
1330#define C_CC (C_EMPTY + 1)
d9eca1df 1331 { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND,
f36e33da
CZ		 1332 { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
1333 F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
1334 F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1335 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
1336 F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
1337 F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
886a2506
NC		 1338
1339#define C_AA_ADDR3 (C_CC + 1)
1340#define C_AA27 (C_CC + 1)
1ae8ab47 1341 { F_CLASS_OPTIONAL, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
886a2506
NC		 1342#define C_AA_ADDR9 (C_AA_ADDR3 + 1)
1343#define C_AA21 (C_AA_ADDR3 + 1)
1ae8ab47 1344 { F_CLASS_OPTIONAL, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
886a2506
NC		 1345#define C_AA_ADDR22 (C_AA_ADDR9 + 1)
1346#define C_AA8 (C_AA_ADDR9 + 1)
1ae8ab47 1347 { F_CLASS_OPTIONAL, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
886a2506
NC		 1348
1349#define C_F (C_AA_ADDR22 + 1)
1ae8ab47 1350 { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
886a2506 1351#define C_FHARD (C_F + 1)
1ae8ab47 1352 { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
886a2506
NC		 1353
1354#define C_T (C_FHARD + 1)
1ae8ab47 1355 { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
886a2506 1356#define C_D (C_T + 1)
1ae8ab47 1357 { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
886a2506
NC		 1358
1359#define C_DHARD (C_D + 1)
1ae8ab47 1360 { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
886a2506
NC		 1361
1362#define C_DI20 (C_DHARD + 1)
1ae8ab47 1363 { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
886a2506 1364#define C_DI16 (C_DI20 + 1)
1ae8ab47 1365 { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
886a2506 1366#define C_DI26 (C_DI16 + 1)
1ae8ab47 1367 { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
886a2506
NC		 1368
1369#define C_X25 (C_DI26 + 1)
1ae8ab47 1370 { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
886a2506 1371#define C_X15 (C_X25 + 1)
1ae8ab47 1372 { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
886a2506
NC		 1373#define C_XHARD (C_X15 + 1)
1374#define C_X (C_X15 + 1)
1ae8ab47 1375 { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
886a2506
NC		 1376
1377#define C_ZZ13 (C_X + 1)
1ae8ab47 1378 { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
886a2506 1379#define C_ZZ23 (C_ZZ13 + 1)
1ae8ab47 1380 { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
886a2506 1381#define C_ZZ29 (C_ZZ23 + 1)
1ae8ab47 1382 { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
886a2506
NC		 1383
1384#define C_AS (C_ZZ29 + 1)
1ae8ab47 1385 { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
886a2506
NC		 1386
1387#define C_NE (C_AS + 1)
1ae8ab47 1388 { F_CLASS_OPTIONAL, { F_NE, F_NULL}},
e23e8ebe
AB		 1389
1390 /* ARC NPS400 Support: See comment near head of file. */
1391#define C_NPS_CL (C_NE + 1)
1392 { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
1393
1394#define C_NPS_F (C_NPS_CL + 1)
1395 { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
820f03ff
AB		 1396
1397#define C_NPS_R (C_NPS_F + 1)
1398 { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}},
a42a4f84
AB		 1399
1400#define C_NPS_SCHD_RW (C_NPS_R + 1)
1401 { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}},
1402
1403#define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1)
1404 { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}},
1405
1406#define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1)
1407 { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}},
1408
1409#define C_NPS_SYNC (C_NPS_SCHD_IE + 1)
1410 { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}},
1411
1412#define C_NPS_HWS_OFF (C_NPS_SYNC + 1)
1413 { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}},
1414
1415#define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1)
1416 { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}},
1417
537aefaf
AB		 1418#define C_NPS_SX (C_NPS_HWS_RESTORE + 1)
1419 { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}},
1420
1421#define C_NPS_AR_AL (C_NPS_SX + 1)
1422 { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}},
886a2506 1423};
252b5132 1424
b99747ae
CZ		 1425const unsigned char flags_none[] = { 0 };
1426const unsigned char flags_f[] = { C_F };
1427const unsigned char flags_cc[] = { C_CC };
1428const unsigned char flags_ccf[] = { C_CC, C_F };
1429
886a2506 1430/* The operands table.
252b5132 1431
886a2506 1432 The format of the operands table is:
47b0e7ad 1433
886a2506
NC		 1434 BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
1435const struct arc_operand arc_operands[] =
0d2bcfaf 1436{
886a2506
NC		 1437 /* The fields are bits, shift, insert, extract, flags. The zero
1438 index is used to indicate end-of-list. */
1439#define UNUSED 0
1440 { 0, 0, 0, 0, 0, 0 },
4eb6f892
AB		 1441
1442#define IGNORED (UNUSED + 1)
1443 { 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0 },
1444
886a2506
NC		 1445 /* The plain integer register fields. Used by 32 bit
1446 instructions. */
4eb6f892 1447#define RA (IGNORED + 1)
886a2506
NC		 1448 { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
1449#define RB (RA + 1)
1450 { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
1451#define RC (RB + 1)
1452 { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
1453#define RBdup (RC + 1)
1454 { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
1455
1456#define RAD (RBdup + 1)
1457 { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
1458#define RCD (RAD + 1)
1459 { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
1460
1461 /* The plain integer register fields. Used by short
1462 instructions. */
1463#define RA16 (RCD + 1)
1464#define RA_S (RCD + 1)
1465 { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
1466#define RB16 (RA16 + 1)
1467#define RB_S (RA16 + 1)
1468 { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
1469#define RB16dup (RB16 + 1)
1470#define RB_Sdup (RB16 + 1)
1471 { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
1472#define RC16 (RB16dup + 1)
1473#define RC_S (RB16dup + 1)
1474 { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
1475#define R6H (RC16 + 1) /* 6bit register field 'h' used
1476 by V1 cpus. */
1477 { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
1478#define R5H (R6H + 1) /* 5bit register field 'h' used
1479 by V2 cpus. */
1480#define RH_S (R6H + 1) /* 5bit register field 'h' used
1481 by V2 cpus. */
1482 { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
1483#define R5Hdup (R5H + 1)
1484#define RH_Sdup (R5H + 1)
1485 { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
1486 insert_rhv2, extract_rhv2 },
1487
1488#define RG (R5Hdup + 1)
1489#define G_S (R5Hdup + 1)
1490 { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
1491
1492 /* Fix registers. */
1493#define R0 (RG + 1)
1494#define R0_S (RG + 1)
1495 { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
1496#define R1 (R0 + 1)
1497#define R1_S (R0 + 1)
1498 { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
1499#define R2 (R1 + 1)
1500#define R2_S (R1 + 1)
1501 { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
1502#define R3 (R2 + 1)
1503#define R3_S (R2 + 1)
1504 { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
8ddf6b2a 1505#define RSP (R3 + 1)
886a2506
NC		 1506#define SP_S (R3 + 1)
1507 { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
8ddf6b2a
CZ		 1508#define SPdup (RSP + 1)
1509#define SP_Sdup (RSP + 1)
886a2506
NC		 1510 { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
1511#define GP (SPdup + 1)
1512#define GP_S (SPdup + 1)
1513 { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
1514
1515#define PCL_S (GP + 1)
1516 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
1517
1518#define BLINK (PCL_S + 1)
1519#define BLINK_S (PCL_S + 1)
1520 { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
1521
1522#define ILINK1 (BLINK + 1)
1523 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
1524#define ILINK2 (ILINK1 + 1)
1525 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
1526
1527 /* Long immediate. */
1528#define LIMM (ILINK2 + 1)
1529#define LIMM_S (ILINK2 + 1)
1530 { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
1531#define LIMMdup (LIMM + 1)
1532 { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
1533
1534 /* Special operands. */
1535#define ZA (LIMMdup + 1)
1536#define ZB (LIMMdup + 1)
1537#define ZA_S (LIMMdup + 1)
1538#define ZB_S (LIMMdup + 1)
1539#define ZC_S (LIMMdup + 1)
1540 { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
1541
1542#define RRANGE_EL (ZA + 1)
1543 { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
1544 insert_rrange, extract_rrange},
1545#define FP_EL (RRANGE_EL + 1)
1546 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1547 insert_fpel, extract_fpel },
1548#define BLINK_EL (FP_EL + 1)
1549 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1550 insert_blinkel, extract_blinkel },
1551#define PCL_EL (BLINK_EL + 1)
1552 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1553 insert_pclel, extract_pclel },
1554
1555 /* Fake operand to handle the T flag. */
1556#define BRAKET (PCL_EL + 1)
1557#define BRAKETdup (PCL_EL + 1)
1558 { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
1559
1560 /* Fake operand to handle the T flag. */
1561#define FKT_T (BRAKET + 1)
1562 { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
1563 /* Fake operand to handle the T flag. */
1564#define FKT_NT (FKT_T + 1)
1565 { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
1566
1567 /* UIMM6_20 mask = 00000000000000000000111111000000. */
1568#define UIMM6_20 (FKT_NT + 1)
1569 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
1570
1571 /* SIMM12_20 mask = 00000000000000000000111111222222. */
1572#define SIMM12_20 (UIMM6_20 + 1)
1573 {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
1574
1575 /* SIMM3_5_S mask = 0000011100000000. */
1576#define SIMM3_5_S (SIMM12_20 + 1)
1577 {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
1578 insert_simm3s, extract_simm3s},
1579
1580 /* UIMM7_A32_11_S mask = 0000000000011111. */
1581#define UIMM7_A32_11_S (SIMM3_5_S + 1)
1582 {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1583 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
1584 extract_uimm7_a32_11_s},
1585
1586 /* UIMM7_9_S mask = 0000000001111111. */
1587#define UIMM7_9_S (UIMM7_A32_11_S + 1)
1588 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
1589
1590 /* UIMM3_13_S mask = 0000000000000111. */
1591#define UIMM3_13_S (UIMM7_9_S + 1)
1592 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
1593
1594 /* SIMM11_A32_7_S mask = 0000000111111111. */
1595#define SIMM11_A32_7_S (UIMM3_13_S + 1)
1596 {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1597 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
1598
1599 /* UIMM6_13_S mask = 0000000002220111. */
1600#define UIMM6_13_S (SIMM11_A32_7_S + 1)
1601 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
1602 /* UIMM5_11_S mask = 0000000000011111. */
1603#define UIMM5_11_S (UIMM6_13_S + 1)
1604 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
1605 extract_uimm5_11_s},
1606
1607 /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
1608#define SIMM9_A16_8 (UIMM5_11_S + 1)
1609 {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1610 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
1611 extract_simm9_a16_8},
1612
1613 /* UIMM6_8 mask = 00000000000000000000111111000000. */
1614#define UIMM6_8 (SIMM9_A16_8 + 1)
1615 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
1616
1617 /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
1618#define SIMM21_A16_5 (UIMM6_8 + 1)
1619 {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
1620 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE,
1621 insert_simm21_a16_5, extract_simm21_a16_5},
1622
1623 /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
1624#define SIMM25_A16_5 (SIMM21_A16_5 + 1)
1625 {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
1626 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
1627 insert_simm25_a16_5, extract_simm25_a16_5},
1628
1629 /* SIMM10_A16_7_S mask = 0000000111111111. */
1630#define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
1631 {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1632 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
1633 extract_simm10_a16_7_s},
1634
1635#define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1)
1636 {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1637 | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
1638
1639 /* SIMM7_A16_10_S mask = 0000000000111111. */
1640#define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
1641 {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1642 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
1643 extract_simm7_a16_10_s},
1644
1645 /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
1646#define SIMM21_A32_5 (SIMM7_A16_10_S + 1)
1647 {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1648 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
1649 extract_simm21_a32_5},
1650
1651 /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
1652#define SIMM25_A32_5 (SIMM21_A32_5 + 1)
1653 {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1654 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
1655 extract_simm25_a32_5},
1656
1657 /* SIMM13_A32_5_S mask = 0000011111111111. */
1658#define SIMM13_A32_5_S (SIMM25_A32_5 + 1)
1659 {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1660 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
1661 extract_simm13_a32_5_s},
1662
1663 /* SIMM8_A16_9_S mask = 0000000001111111. */
1664#define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
1665 {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1666 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
1667 extract_simm8_a16_9_s},
1668
1669 /* UIMM3_23 mask = 00000000000000000000000111000000. */
1670#define UIMM3_23 (SIMM8_A16_9_S + 1)
1671 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
1672
1673 /* UIMM10_6_S mask = 0000001111111111. */
1674#define UIMM10_6_S (UIMM3_23 + 1)
1675 {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
1676
1677 /* UIMM6_11_S mask = 0000002200011110. */
1678#define UIMM6_11_S (UIMM10_6_S + 1)
1679 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
1680
1681 /* SIMM9_8 mask = 00000000111111112000000000000000. */
1682#define SIMM9_8 (UIMM6_11_S + 1)
1683 {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
1684 insert_simm9_8, extract_simm9_8},
1685
1686 /* UIMM10_A32_8_S mask = 0000000011111111. */
1687#define UIMM10_A32_8_S (SIMM9_8 + 1)
1688 {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1689 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
1690 extract_uimm10_a32_8_s},
1691
1692 /* SIMM9_7_S mask = 0000000111111111. */
1693#define SIMM9_7_S (UIMM10_A32_8_S + 1)
1694 {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
1695 extract_simm9_7_s},
1696
1697 /* UIMM6_A16_11_S mask = 0000000000011111. */
1698#define UIMM6_A16_11_S (SIMM9_7_S + 1)
1699 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1700 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
1701 extract_uimm6_a16_11_s},
1702
1703 /* UIMM5_A32_11_S mask = 0000020000011000. */
1704#define UIMM5_A32_11_S (UIMM6_A16_11_S + 1)
1705 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1706 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
1707 extract_uimm5_a32_11_s},
1708
1709 /* SIMM11_A32_13_S mask = 0000022222200111. */
1710#define SIMM11_A32_13_S (UIMM5_A32_11_S + 1)
1711 {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1712 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
1713
1714 /* UIMM7_13_S mask = 0000000022220111. */
1715#define UIMM7_13_S (SIMM11_A32_13_S + 1)
1716 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
1717
1718 /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
1719#define UIMM6_A16_21 (UIMM7_13_S + 1)
1720 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1721 | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
1722
1723 /* UIMM7_11_S mask = 0000022200011110. */
1724#define UIMM7_11_S (UIMM6_A16_21 + 1)
1725 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
1726
1727 /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
1728#define UIMM7_A16_20 (UIMM7_11_S + 1)
1729 {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1730 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
1731 extract_uimm7_a16_20},
1732
1733 /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
1734#define SIMM13_A16_20 (UIMM7_A16_20 + 1)
1735 {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1736 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
1737 extract_simm13_a16_20},
1738
1739 /* UIMM8_8_S mask = 0000000011111111. */
1740#define UIMM8_8_S (SIMM13_A16_20 + 1)
1741 {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
1742
1743 /* W6 mask = 00000000000000000000111111000000. */
1744#define W6 (UIMM8_8_S + 1)
1745 {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
1746
1747 /* UIMM6_5_S mask = 0000011111100000. */
1748#define UIMM6_5_S (W6 + 1)
1749 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
e23e8ebe
AB		 1750
1751 /* ARC NPS400 Support: See comment near head of file. */
1752#define NPS_R_DST_3B (UIMM6_5_S + 1)
1753 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
1754
1755#define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
1756 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
1757
1758#define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
1759 { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_src2, extract_nps_3bit_src2 },
1760
1761#define NPS_R_DST (NPS_R_SRC2_3B + 1)
2cce10e7 1762 { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL },
e23e8ebe
AB		 1763
1764#define NPS_R_SRC1 (NPS_R_DST + 1)
2cce10e7 1765 { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
e23e8ebe
AB		 1766
1767#define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1)
1768 { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1769
1770#define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
1771 { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1772
1773#define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
820f03ff 1774 { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size, extract_nps_bitop_size },
e23e8ebe 1775
820f03ff
AB		 1776#define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1)
1777 { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size },
1778
1779#define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1)
1780 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size_2b, extract_nps_bitop_size_2b },
1781
1782#define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1)
1783 { 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 },
1784
1785#define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1)
e23e8ebe 1786 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
820f03ff
AB		 1787
1788#define NPS_RFLT_UIMM6 (NPS_UIMM16 + 1)
1789 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
4b0c052e
AB		 1790
1791#define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1)
1792 { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 },
537aefaf
AB		 1793
1794#define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1)
1795 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src2_pos, extract_nps_src2_pos },
1796
1797#define NPS_SRC1_POS (NPS_SRC2_POS + 1)
1798 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src1_pos, extract_nps_src1_pos },
1799
1800#define NPS_ADDB_SIZE (NPS_SRC1_POS + 1)
1801 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_addb_size, extract_nps_addb_size },
1802
1803#define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1)
1804 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_andb_size, extract_nps_andb_size },
1805
1806#define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1)
1807 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_fxorb_size, extract_nps_fxorb_size },
1808
1809#define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1)
1810 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_wxorb_size, extract_nps_wxorb_size },
1811
1812#define NPS_R_XLDST (NPS_WXORB_SIZE + 1)
1813 { 6, 5, 0, ARC_OPERAND_IR, NULL, NULL },
1814
1815#define NPS_DIV_UIMM4 (NPS_R_XLDST + 1)
1816 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1817
1818#define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1)
1819 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_qcmp_size, extract_nps_qcmp_size },
1820
1821#define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1)
1822 { 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1 },
1823
1824#define NPS_QCMP_M2 (NPS_QCMP_M1 + 1)
1825 { 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2 },
1826
1827#define NPS_QCMP_M3 (NPS_QCMP_M2 + 1)
1828 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3 },
1829
1830#define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1)
1831 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_calc_entry_size, extract_nps_calc_entry_size },
4eb6f892
AB		 1832
1833#define NPS_R_DST_3B_SHORT (NPS_CALC_ENTRY_SIZE + 1)
1834 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst_short, extract_nps_3bit_dst_short },
1835
1836#define NPS_R_SRC1_3B_SHORT (NPS_R_DST_3B_SHORT + 1)
1837 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_dst_short, extract_nps_3bit_dst_short },
1838
1839#define NPS_R_SRC2_3B_SHORT (NPS_R_SRC1_3B_SHORT + 1)
1840 { 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_src2_short, extract_nps_3bit_src2_short },
1841
1842#define NPS_BITOP_SIZE2 (NPS_R_SRC2_3B_SHORT + 1)
1843 { 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop2_size, extract_nps_bitop2_size },
1844
1845#define NPS_BITOP_SIZE1 (NPS_BITOP_SIZE2 + 1)
1846 { 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop1_size, extract_nps_bitop1_size },
1847
1848#define NPS_BITOP_DST_POS3_POS4 (NPS_BITOP_SIZE1 + 1)
1849 { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4 },
1850
1851#define NPS_BITOP_DST_POS4 (NPS_BITOP_DST_POS3_POS4 + 1)
1852 { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1853
1854#define NPS_BITOP_DST_POS3 (NPS_BITOP_DST_POS4 + 1)
1855 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1856
1857#define NPS_BITOP_DST_POS2 (NPS_BITOP_DST_POS3 + 1)
1858 { 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1859
1860#define NPS_BITOP_DST_POS1 (NPS_BITOP_DST_POS2 + 1)
1861 { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1862
1863#define NPS_BITOP_SRC_POS4 (NPS_BITOP_DST_POS1 + 1)
1864 { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1865
1866#define NPS_BITOP_SRC_POS3 (NPS_BITOP_SRC_POS4 + 1)
1867 { 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1868
1869#define NPS_BITOP_SRC_POS2 (NPS_BITOP_SRC_POS3 + 1)
1870 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1871
1872#define NPS_BITOP_SRC_POS1 (NPS_BITOP_SRC_POS2 + 1)
1873 { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1874
1875#define NPS_BITOP_MOD4_MSB (NPS_BITOP_SRC_POS1 + 1)
1876 { 2, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_mod4_msb, extract_nps_bitop_mod4_msb },
1877
1878#define NPS_BITOP_MOD4_LSB (NPS_BITOP_MOD4_MSB + 1)
1879 { 2, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_mod4_lsb, extract_nps_bitop_mod4_lsb },
1880
1881#define NPS_BITOP_MOD3 (NPS_BITOP_MOD4_LSB + 1)
1882 { 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1883
1884#define NPS_BITOP_MOD2 (NPS_BITOP_MOD3 + 1)
1885 { 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1886
1887#define NPS_BITOP_MOD1 (NPS_BITOP_MOD2 + 1)
1888 { 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1889
1890#define NPS_BITOP_INS_EXT (NPS_BITOP_MOD1 + 1)
1891 { 5, 20, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext },
886a2506 1892};
0d2bcfaf 1893
886a2506 1894const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
0d2bcfaf 1895
886a2506
NC		 1896const unsigned arc_Toperand = FKT_T;
1897const unsigned arc_NToperand = FKT_NT;
47b0e7ad 1898
b99747ae
CZ		 1899const unsigned char arg_none[] = { 0 };
1900const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC };
1901const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC };
1902const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC };
1903const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 };
1904const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 };
1905const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 };
1906const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 };
1907const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC };
1908const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM };
1909const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC };
1910const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM };
1911
1912const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM };
1913const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 };
1914const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 };
1915
1916const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 };
1917const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup };
1918const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup };
1919
1920const unsigned char arg_32bit_rbrc[] = { RB, RC };
1921const unsigned char arg_32bit_zarc[] = { ZA, RC };
1922const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 };
1923const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 };
1924const unsigned char arg_32bit_rblimm[] = { RB, LIMM };
1925const unsigned char arg_32bit_zalimm[] = { ZA, LIMM };
1926
1927const unsigned char arg_32bit_limmrc[] = { LIMM, RC };
1928const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 };
1929const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 };
1930const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup };
1931
945e0f82
CZ		 1932const unsigned char arg_32bit_rc[] = { RC };
1933const unsigned char arg_32bit_u6[] = { UIMM6_20 };
1934const unsigned char arg_32bit_limm[] = { LIMM };
1935
886a2506 1936/* The opcode table.
0d2bcfaf 1937
886a2506 1938 The format of the opcode table is:
0d2bcfaf 1939
1328504b
AB		 1940 NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }.
1941
1942 The table is organised such that, where possible, all instructions with
1943 the same mnemonic are together in a block. When the assembler searches
1944 for a suitable instruction the entries are checked in table order, so
1945 more specific, or specialised cases should appear earlier in the table.
1946
1947 As an example, consider two instructions 'add a,b,u6' and 'add
1948 a,b,limm'. The first takes a 6-bit immediate that is encoded within the
1949 32-bit instruction, while the second takes a 32-bit immediate that is
1950 encoded in a follow-on 32-bit, making the total instruction length
1951 64-bits. In this case the u6 variant must appear first in the table, as
1952 all u6 immediates could also be encoded using the 'limm' extension,
1953 however, we want to use the shorter instruction wherever possible.
1954
1955 It is possible though to split instructions with the same mnemonic into
1956 multiple groups. However, the instructions are still checked in table
1957 order, even across groups. The only time that instructions with the
1958 same mnemonic should be split into different groups is when different
1959 variants of the instruction appear in different architectures, in which
1960 case, grouping all instructions from a particular architecture together
1961 might be preferable to merging the instruction into the main instruction
1962 table.
1963
1964 An example of this split instruction groups can be found with the 'sync'
1965 instruction. The core arc architecture provides a 'sync' instruction,
1966 while the nps instruction set extension provides 'sync.rd' and
1967 'sync.wr'. The rd/wr flags are instruction flags, not part of the
1968 mnemonic, so we end up with two groups for the sync instruction, the
1969 first within the core arc instruction table, and the second within the
1970 nps extension instructions. */
886a2506 1971const struct arc_opcode arc_opcodes[] =
0d2bcfaf 1972{
886a2506 1973#include "arc-tbl.h"
e23e8ebe 1974#include "arc-nps400-tbl.h"
f2dd8838 1975#include "arc-ext-tbl.h"
0d2bcfaf 1976
b99747ae
CZ		 1977 { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } }
1978};
252b5132 1979
886a2506
NC		 1980/* List with special cases instructions and the applicable flags. */
1981const struct arc_flag_special arc_flag_special_cases[] =
252b5132 1982{
886a2506
NC		 1983 { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1984 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1985 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1986 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1987 { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1988 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1989 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1990 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1991 { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1992 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1993 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1994 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1995 { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1996 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1997 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1998 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1999 { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2000 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2001 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2002 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2003 { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2004 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2005 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2006 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2007 { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2008 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2009 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2010 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2011 { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
2012 { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
2013};
252b5132 2014
886a2506 2015const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
252b5132 2016
886a2506 2017/* Relocations. */
886a2506
NC		 2018const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
2019{
24b368f8
CZ		 2020 { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
2021 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2022 { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
2023 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2024 { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
2025 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2026 { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
2027 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2028
2029 /* Next two entries will cover the undefined behavior ldb/stb with
2030 address scaling. */
2031 { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
2032 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2033 { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
2034 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
2035
2036 { "sda", "ld", { F_ASFAKE, F_NULL },
2037 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2038 { "sda", "st", { F_ASFAKE, F_NULL },
2039 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
2040 { "sda", "ldd", { F_ASFAKE, F_NULL },
2041 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2042 { "sda", "std", { F_ASFAKE, F_NULL },
2043 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
886a2506
NC		 2044
2045 /* Short instructions. */
24b368f8
CZ		 2046 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
2047 { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
2048 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
2049 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
2050
2051 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
2052 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2053
2054 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
2055 BFD_RELOC_ARC_S25H_PCREL_PLT },
2056 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
2057 BFD_RELOC_ARC_S21H_PCREL_PLT },
2058 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
2059 BFD_RELOC_ARC_S25W_PCREL_PLT },
2060 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
2061 BFD_RELOC_ARC_S21W_PCREL_PLT },
2062
2063 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
886a2506 2064};
252b5132 2065
886a2506 2066const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
252b5132 2067
886a2506 2068const struct arc_pseudo_insn arc_pseudo_insns[] =
0d2bcfaf 2069{
886a2506
NC		 2070 { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2071 { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
2072 { BRAKETdup, 1, 0, 4} } },
2073 { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2074 { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
2075 { BRAKETdup, 1, 0, 4} } },
2076
2077 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2078 { SIMM9_A16_8, 0, 0, 2 } } },
2079 { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2080 { SIMM9_A16_8, 0, 0, 2 } } },
2081 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2082 { SIMM9_A16_8, 0, 0, 2 } } },
2083 { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2084 { SIMM9_A16_8, 0, 0, 2 } } },
2085 { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2086 { SIMM9_A16_8, 0, 0, 2 } } },
2087
2088 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2089 { SIMM9_A16_8, 0, 0, 2 } } },
2090 { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2091 { SIMM9_A16_8, 0, 0, 2 } } },
2092 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2093 { SIMM9_A16_8, 0, 0, 2 } } },
2094 { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2095 { SIMM9_A16_8, 0, 0, 2 } } },
2096 { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2097 { SIMM9_A16_8, 0, 0, 2 } } },
2098
2099 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2100 { SIMM9_A16_8, 0, 0, 2 } } },
2101 { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2102 { SIMM9_A16_8, 0, 0, 2 } } },
2103 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2104 { SIMM9_A16_8, 0, 0, 2 } } },
2105 { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2106 { SIMM9_A16_8, 0, 0, 2 } } },
2107 { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2108 { SIMM9_A16_8, 0, 0, 2 } } },
2109
2110 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2111 { SIMM9_A16_8, 0, 0, 2 } } },
2112 { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2113 { SIMM9_A16_8, 0, 0, 2 } } },
2114 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2115 { SIMM9_A16_8, 0, 0, 2 } } },
2116 { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2117 { SIMM9_A16_8, 0, 0, 2 } } },
2118 { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2119 { SIMM9_A16_8, 0, 0, 2 } } },
2120};
0d2bcfaf 2121
886a2506
NC		 2122const unsigned arc_num_pseudo_insn =
2123 sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
0d2bcfaf 2124
886a2506 2125const struct arc_aux_reg arc_aux_regs[] =
0d2bcfaf 2126{
886a2506 2127#undef DEF
f36e33da
CZ		 2128#define DEF(ADDR, CPU, SUBCLASS, NAME) \
2129 { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 },
0d2bcfaf 2130
886a2506 2131#include "arc-regs.h"
0d2bcfaf 2132
886a2506
NC		 2133#undef DEF
2134};
0d2bcfaf 2135
886a2506 2136const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
4670103e
CZ		 2137
2138/* NOTE: The order of this array MUST be consistent with 'enum
2139 arc_rlx_types' located in tc-arc.h! */
2140const struct arc_opcode arc_relax_opcodes[] =
2141{
2142 { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
2143
2144 /* bl_s s13 11111sssssssssss. */
2145 { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2146 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2147 { SIMM13_A32_5_S }, { 0 }},
2148
2149 /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
2150 { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2151 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2152 { SIMM25_A32_5 }, { C_D }},
2153
2154 /* b_s s10 1111000sssssssss. */
2155 { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2156 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2157 { SIMM10_A16_7_S }, { 0 }},
2158
2159 /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
2160 { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2161 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2162 { SIMM25_A16_5 }, { C_D }},
2163
2164 /* add_s c,b,u3 01101bbbccc00uuu. Wants UIMM3_13_S_PCREL. */
2165 { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2166 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2167 { RC_S, RB_S, UIMM3_13_S }, { 0 }},
2168
2169 /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. Wants
2170 UIMM6_20_PCREL. */
2171 { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2172 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2173 { RA, RB, UIMM6_20 }, { C_F }},
2174
2175 /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
2176 { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2177 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2178 { RA, RB, LIMM }, { C_F }},
2179
2180 /* ld_s c,b,u7 10000bbbcccuuuuu. Wants UIMM7_A32_11_S_PCREL. */
2181 { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2182 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2183 { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
2184
2185 /* ld<.di><.aa><.x><zz> a,b,s9
2186 00010bbbssssssssSBBBDaaZZXAAAAAA. Wants SIMM9_8_PCREL. */
2187 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2188 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2189 { RA, BRAKET, RB, SIMM9_8, BRAKETdup },
2190 { C_ZZ23, C_DI20, C_AA21, C_X25 }},
2191
2192 /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
2193 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2194 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2195 { RA, BRAKET, RB, LIMM, BRAKETdup },
2196 { C_ZZ13, C_DI16, C_AA8, C_X15 }},
2197
2198 /* mov_s b,u8 11011bbbuuuuuuuu. Wants UIMM8_8_S_PCREL. */
2199 { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2200 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2201 { RB_S, UIMM8_8_S }, { 0 }},
2202
2203 /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. Wants
2204 SIMM12_20_PCREL. */
2205 { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2206 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2207 { RB, SIMM12_20 }, { C_F }},
2208
2209 /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
2210 { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2211 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2212 { RB, LIMM }, { C_F }},
2213
2214 /* sub_s c,b,u3 01101bbbccc01uuu. UIMM3_13_S_PCREL. */
2215 { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2216 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2217 { RC_S, RB_S, UIMM3_13_S }, { 0 }},
2218
2219 /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA.
2220 UIMM6_20_PCREL. */
2221 { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2222 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2223 { RA, RB, UIMM6_20 }, { C_F }},
2224
2225 /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
2226 { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2227 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2228 { RA, RB, LIMM }, { C_F }},
2229
2230 /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA.
2231 UIMM6_20_PCREL. */
2232 { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2233 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }},
2234
2235 /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
2236 { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2237 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
2238
2239 /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ.
2240 UIMM6_20_PCREL. */
2241 { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2242 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2243 { RB, UIMM6_20 }, { C_F, C_CC }},
2244
2245 /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
2246 { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2247 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2248 { RB, LIMM }, { C_F, C_CC }},
2249
2250 /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ.
2251 UIMM6_20_PCREL. */
2252 { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2253 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2254 { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
2255
2256 /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
2257 { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2258 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2259 { RB, RBdup, LIMM }, { C_F, C_CC }}
2260};
2261
2262const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);
4eb6f892
AB		 2263
2264/* The following instructions are all either 48 or 64 bits long, and
2265 require special handling in the assembler and disassembler.
2266
2267 The first part of each ARC_LONG_OPCODE is the base ARC_OPCODE, this is
2268 either the 16 or 32 bit base instruction, and its opcode list will
2269 always end in a LIMM.
2270
2271 The rest of the ARC_LONG_OPCODE describes how to build the LIMM from the
2272 instruction operands. There are therefore two lists of operands for
2273 each ARC_LONG_OPCODE, the second list contains operands that are merged
2274 into the limm template, in the same way that a standard 32-bit
2275 instruction is built. This generated limm is then added to the list of
2276 tokens that is passed to the standard instruction encoder, along with
2277 the first list of operands (from the base arc_opcode).
2278
2279 The first list of operands then, describes how to build the base
2280 instruction, and includes the 32-bit limm that was previously generated
2281 as the last operand.
2282
2283 In most cases operands are either encoded into the base instruction or
2284 into the limm. When this happens the operand slot will be filled with
2285 an operand identifier in one list, and will be IGNORED in the other
2286 list, this special operand value causes the operand to be ignored,
2287 without being encoded at this point.
2288
2289 However, in some cases, an operand is split between the base instruction
2290 and the 32-bit limm, in this case the operand slot will be filled in
2291 both operand lists (see mov4b for one example of this). */
2292const struct arc_long_opcode arc_long_opcodes[] =
2293 {
2294 /* mrgb - (48 bit instruction). */
2295 { { "mrgb", 0x5803, 0xf81f, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }},
2296 0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_SRC_POS1, NPS_BITOP_SIZE1, NPS_BITOP_DST_POS2, NPS_BITOP_SRC_POS2, NPS_BITOP_SIZE2 }},
2297
2298 /* mrgb.cl - (48 bit instruction). */
2299 { { "mrgb", 0x5803, 0xf81f, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
2300 0x80000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_SRC_POS1, NPS_BITOP_SIZE1, NPS_BITOP_DST_POS2, NPS_BITOP_SRC_POS2, NPS_BITOP_SIZE2 }},
2301
2302 /* mov2b - (48 bit instruction). */
2303 { { "mov2b", 0x5800, 0xf81f, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }},
2304 0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2 }},
2305
2306 /* mov2b.cl - (48 bit instruction). */
2307 { { "mov2b", 0x5800, 0xf81f, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
2308 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2 }},
2309
2310 /* ext4 - (48 bit instruction). */
2311 { { "ext4b", 0x5801, 0xf81f, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }},
2312 0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_INS_EXT, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2 }},
2313
2314 /* ext4.cl - (48 bit instruction). */
2315 { { "ext4b", 0x5801, 0xf81f, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
2316 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_INS_EXT, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2 }},
2317
2318 /* ins4 - (48 bit instruction). */
2319 { { "ins4b", 0x5802, 0xf81f, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }},
2320 0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_INS_EXT }},
2321
2322 /* ins4.cl - (48 bit instruction). */
2323 { { "ins4b", 0x5802, 0xf81f, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
2324 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_INS_EXT }},
2325
2326 /* mov3b - (64 bit instruction). */
2327 { { "mov3b", 0x58100000, 0xf81f801f, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3_POS4, IGNORED, IGNORED, LIMM }, { 0 }},
2328 0x80000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3 }},
2329
2330 /* mov4b - (64 bit instruction). */
2331 { { "mov4b", 0x58100000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3, IGNORED, IGNORED, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4_LSB, NPS_BITOP_SRC_POS4, LIMM }, { 0 }},
2332 0x00000000, 0x00000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3, IGNORED, NPS_BITOP_MOD4_MSB, IGNORED}},
2333
2334 /* mov3bcl - (64 bit instruction). */
2335 { { "mov3bcl", 0x58110000, 0xf81f801f, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3_POS4, IGNORED, IGNORED, LIMM }, { 0 }},
2336 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3 }},
2337
2338 /* mov4bcl - (64 bit instruction). */
2339 { { "mov4bcl", 0x58110000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3, IGNORED, IGNORED, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4_LSB, NPS_BITOP_SRC_POS4, LIMM }, { 0 }},
2340 0x00000000, 0x00000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3, IGNORED, NPS_BITOP_MOD4_MSB, IGNORED}},
2341
2342 /* mov3b.cl - (64 bit instruction). */
2343 { { "mov3b", 0x58110000, 0xf81f801f, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3_POS4, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
2344 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3 }},
2345
2346 /* mov4b.cl - (64 bit instruction). */
2347 { { "mov4b", 0x58110000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3, IGNORED, IGNORED, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4_LSB, NPS_BITOP_SRC_POS4, LIMM }, { C_NPS_CL }},
2348 0x00000000, 0x00000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3, IGNORED, NPS_BITOP_MOD4_MSB, IGNORED}},
2349};
2350
2351const unsigned arc_num_long_opcodes = ARRAY_SIZE (arc_long_opcodes);
GDB Binutils - Deliverables
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