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opcodes: handle mach-o for thumb/arm disambiguation.
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
b90efa5b 2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
2fbad815 24
252b5132 25#include "dis-asm.h"
2fbad815 26#include "opcode/arm.h"
252b5132 27#include "opintl.h"
31e0f3cd 28#include "safe-ctype.h"
0dbde4cf 29#include "floatformat.h"
252b5132 30
baf0cc5e 31/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 32#include "coff/internal.h"
33#include "libcoff.h"
252b5132
RH		 34#include "elf-bfd.h"
35#include "elf/internal.h"
36#include "elf/arm.h"
e49d43ff 37#include "mach-o.h"
252b5132 38
6b5d3a4d 39/* FIXME: Belongs in global header. */
01c7f630 40#ifndef strneq
58efb6c0
NC		 41#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
42#endif
43
44#ifndef NUM_ELEM
45#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
01c7f630
NC		 46#endif
47
1fbaefec
PB		 48/* Cached mapping symbol state. */
49enum map_type
50{
51 MAP_ARM,
52 MAP_THUMB,
53 MAP_DATA
54};
55
b0e28b39
DJ		 56struct arm_private_data
57{
58 /* The features to use when disassembling optional instructions. */
59 arm_feature_set features;
60
61 /* Whether any mapping symbols are present in the provided symbol
62 table. -1 if we do not know yet, otherwise 0 or 1. */
63 int has_mapping_symbols;
1fbaefec
PB		 64
65 /* Track the last type (although this doesn't seem to be useful) */
66 enum map_type last_type;
67
68 /* Tracking symbol table information */
69 int last_mapping_sym;
70 bfd_vma last_mapping_addr;
b0e28b39
DJ		 71};
72
6b5d3a4d
ZW		 73struct opcode32
74{
823d2571
TG		 75 arm_feature_set arch; /* Architecture defining this insn. */
76 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 77 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 78 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 79};
80
81struct opcode16
82{
823d2571 83 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 84 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 85 const char *assembler; /* How to disassemble this insn. */
86};
b7693d02 87
8f06b2d8 88/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 89
2fbad815 90 %% %
4a5329c6 91
c22aaad1 92 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 93 %q print shifter argument
e2efe87d
MGD		 94 %u print condition code (unconditional in ARM mode,
95 UNPREDICTABLE if not AL in Thumb)
4a5329c6 96 %A print address for ldc/stc/ldf/stf instruction
16980d0b 97 %B print vstm/vldm register list
4a5329c6 98 %I print cirrus signed shift immediate: bits 0..3|4..6
4a5329c6
ZW		 99 %F print the COUNT field of a LFM/SFM instruction.
100 %P print floating point precision in arithmetic insn
101 %Q print floating point precision in ldf/stf insn
102 %R print floating point rounding mode
103
33399f07 104 %<bitfield>c print as a condition code (for vsel)
4a5329c6 105 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 106 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
107 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 108 %<bitfield>d print the bitfield in decimal
16980d0b 109 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 110 %<bitfield>x print the bitfield in hex
111 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 112 %<bitfield>f print a floating point constant if >7 else a
113 floating point register
4a5329c6
ZW		 114 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
115 %<bitfield>g print as an iWMMXt 64-bit register
116 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 117 %<bitfield>D print as a NEON D register
118 %<bitfield>Q print as a NEON Q register
6f1c2142 119 %<bitfield>E print a quarter-float immediate value
4a5329c6 120
16980d0b 121 %y<code> print a single precision VFP reg.
2fbad815 122 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 123 %z<code> print a double precision VFP reg
2fbad815 124 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 125
16980d0b
JB		 126 %<bitfield>'c print specified char iff bitfield is all ones
127 %<bitfield>`c print specified char iff bitfield is all zeroes
128 %<bitfield>?ab... select from array of values in big endian order
43e65147 129
2fbad815 130 %L print as an iWMMXt N/M width field.
4a5329c6 131 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 132 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 133 versions.
134 %i print 5-bit immediate in bits 8,3..0
135 (print "32" when 0)
fe56b6ce 136 %r print register offset address for wldt/wstr instruction. */
2fbad815 137
21d799b5 138enum opcode_sentinel_enum
05413229
NC		 139{
140 SENTINEL_IWMMXT_START = 1,
141 SENTINEL_IWMMXT_END,
142 SENTINEL_GENERIC_START
143} opcode_sentinels;
144
aefd8a40 145#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
c1e26897 146#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 147
8f06b2d8 148/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 149
8f06b2d8 150static const struct opcode32 coprocessor_opcodes[] =
2fbad815 151{
2fbad815 152 /* XScale instructions. */
823d2571
TG		 153 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
154 0x0e200010, 0x0fff0ff0,
155 "mia%c\tacc0, %0-3r, %12-15r"},
156 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
157 0x0e280010, 0x0fff0ff0,
158 "miaph%c\tacc0, %0-3r, %12-15r"},
159 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
160 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
161 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
162 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
163 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
164 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 165
2fbad815 166 /* Intel Wireless MMX technology instructions. */
823d2571
TG		 167 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
168 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
169 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
170 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
171 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
172 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
173 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
174 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
175 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
176 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
177 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
178 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
179 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
180 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
181 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
182 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
183 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
184 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
185 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
186 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
187 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
188 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
189 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
190 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
191 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
192 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
193 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
194 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
195 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
196 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
197 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
198 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
199 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
200 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
201 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
202 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
203 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
204 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
205 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
206 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
207 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
208 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
209 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
210 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
211 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
212 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
213 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
214 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
215 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
216 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
217 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
218 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
219 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
220 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
221 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
222 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
223 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
224 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
225 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
226 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
227 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
228 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
229 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
230 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
231 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
232 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
233 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
234 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
235 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
236 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
237 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
238 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
239 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
240 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
241 0x0e800120, 0x0f800ff0,
242 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
243 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
244 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
245 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
246 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
247 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
248 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
249 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
250 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
251 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
252 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
253 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
254 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
255 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
256 0x0e8000a0, 0x0f800ff0,
257 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
258 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
259 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
260 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
261 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
262 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
263 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
264 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
265 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
266 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
267 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
268 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
269 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
270 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
271 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
272 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
273 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
274 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
275 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
276 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
277 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
278 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
279 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
280 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
281 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
282 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
283 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
284 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
285 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
286 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
287 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
288 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
289 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
290 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
291 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
292 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
293 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
294 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
295 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
296 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
297 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
298 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
299 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
300 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
301 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
302 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
303 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
304 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
305 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
306 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
307 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
308 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
309 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
310 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
311 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
312 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
313 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
314 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
315 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
316 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
317 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
318 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
319 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
320 {ARM_FEATURE_CORE_LOW (0),
321 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 322
fe56b6ce 323 /* Floating point coprocessor (FPA) instructions. */
823d2571
TG		 324 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
325 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
326 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
327 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
328 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
329 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
330 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
331 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
332 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
333 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
334 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
335 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
336 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
337 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
338 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
339 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
340 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
341 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
342 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
343 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
344 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
345 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
346 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
347 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
348 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
349 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
350 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
351 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
352 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
353 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
354 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
355 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
356 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
357 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
358 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
359 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
360 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
361 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
362 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
363 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
364 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
365 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
366 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
367 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
368 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
369 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
370 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
371 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
372 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
373 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
374 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
375 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
376 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
377 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
378 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
379 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
380 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
381 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
382 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
383 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
384 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
385 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
386 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
387 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
388 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
389 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
390 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
391 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
392 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
393 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
394 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
395 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
396 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
397 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
398 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
399 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
400 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
401 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
402 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
403 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
404 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
405 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
406 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
407 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
408 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
409 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 410
fe56b6ce 411 /* Register load/store. */
823d2571
TG		 412 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
413 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
414 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
415 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
416 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
417 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
418 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
419 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
420 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
421 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
422 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
423 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
424 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
425 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
426 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
427 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
428 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
429 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
430 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
431 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
433 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
435 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
436 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
437 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
438 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
439 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
440 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
441 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
442 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
443 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
444
445 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
446 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
447 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
448 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
449 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
450 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
451 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
452 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 453
fe56b6ce 454 /* Data transfer between ARM and NEON registers. */
823d2571
TG		 455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
456 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
458 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
460 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
462 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
464 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
466 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
468 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
470 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
472 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
474 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
476 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
478 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
480 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
482 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 483 /* Half-precision conversion instructions. */
823d2571
TG		 484 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
485 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
486 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
487 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
488 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
489 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
490 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
491 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 492
fe56b6ce 493 /* Floating point coprocessor (VFP) instructions. */
823d2571
TG		 494 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
495 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
496 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
497 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
498 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
499 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
500 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
501 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
502 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
503 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
504 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
505 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
506 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
507 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
508 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
509 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
510 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
511 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
512 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
513 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
514 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
515 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
516 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
517 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
518 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
519 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
520 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
521 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
522 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
523 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
525 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
527 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
528 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
529 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
530 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
531 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
532 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
533 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
534 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
535 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
536 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
537 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
538 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
539 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
540 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
541 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
542 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
543 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
544 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
545 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
546 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
547 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
548 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
549 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
550 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
551 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
552 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
553 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
554 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
555 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
556 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
557 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
558 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
559 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
560 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
561 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
562 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
563 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
564 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
565 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
566 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
567 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
568 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
569 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
570 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
571 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
572 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
573 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
574 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
575 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
576 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
577 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
578 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
579 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
580 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
581 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
582 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 583 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
823d2571 584 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 585 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
823d2571
TG		 586 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
587 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
588 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
589 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
590 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
591 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
592 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
593 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
594 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
595 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
596 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
597 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
598 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
599 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
600 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
601 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
602 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
603 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
604 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
605 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
606 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
607 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
608 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
609 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
610 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
611 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
612 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
613 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
614 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
615 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
616 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
617 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
618 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
619 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
620 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
621 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
622 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
623 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
624 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
625 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
626 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
627 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 628
629 /* Cirrus coprocessor instructions. */
823d2571
TG		 630 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
631 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
632 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
633 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
634 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
635 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
636 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
637 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
638 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
639 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
640 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
641 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
642 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
643 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
644 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
645 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
646 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
647 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
648 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
649 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
650 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
651 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
652 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
653 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
654 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
655 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
656 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
657 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
658 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
659 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
660 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
661 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
662 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
663 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
664 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
665 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
666 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
667 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
668 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
669 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
670 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
671 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
672 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
673 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
674 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
675 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
676 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
677 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
678 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
679 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
680 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
681 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
682 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
683 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
684 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
685 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
686 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
687 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
688 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
689 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
690 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
691 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
692 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
693 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
694 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
695 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
696 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
697 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
698 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
699 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
700 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
701 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
702 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
703 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
704 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
705 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
706 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
707 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
708 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
709 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
710 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
711 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
712 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
713 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
714 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
715 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
716 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
717 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
718 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
719 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
720 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
721 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
722 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
723 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
724 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
725 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
726 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
727 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
728 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
729 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
730 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
731 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
732 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
733 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
734 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
735 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
736 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
737 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
738 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
739 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
740 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
741 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
742 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
743 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
744 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
745 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
746 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
747 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
748 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
749 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
750 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
751 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
752 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
753 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
754 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
755 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
756 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
757 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
758 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
759 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
760 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
761 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
762 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
763 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
764 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
765 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
766 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
767 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
768 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
769 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
770 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
771 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
772 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
773 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
774 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
775 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
776 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
777 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
778 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
779 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
780 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
781 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
782 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
783 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
784 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
785 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
786 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
787 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
788 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
789 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
790 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
791 0x0e000600, 0x0ff00f10,
792 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
793 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
794 0x0e100600, 0x0ff00f10,
795 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
796 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
797 0x0e200600, 0x0ff00f10,
798 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
799 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
800 0x0e300600, 0x0ff00f10,
801 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 802
62f3b8c8 803 /* VFP Fused multiply add instructions. */
823d2571
TG		 804 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
805 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
806 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
807 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
808 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
809 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
810 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
811 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
812 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
813 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
814 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
815 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
816 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
817 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
818 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
819 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 820
33399f07 821 /* FP v5. */
823d2571
TG		 822 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
824 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
825 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
826 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
827 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"},
828 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
829 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
830 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
831 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
832 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
833 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
834 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
835 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
836 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
837 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
838 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
839 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
840 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
841 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
842 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
843 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
844 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
845 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 846
05413229 847 /* Generic coprocessor instructions. */
823d2571
TG		 848 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
850 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
852 0x0c500000, 0x0ff00000,
853 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
855 0x0e000000, 0x0f000010,
856 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
858 0x0e10f010, 0x0f10f010,
859 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
861 0x0e100010, 0x0f100010,
862 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
864 0x0e000010, 0x0f100010,
865 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
867 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
869 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 870
05413229 871 /* V6 coprocessor instructions. */
823d2571
TG		 872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
873 0xfc500000, 0xfff00000,
874 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
876 0xfc400000, 0xfff00000,
877 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 878
05413229 879 /* V5 coprocessor instructions. */
823d2571
TG		 880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
881 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
883 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
885 0xfe000000, 0xff000010,
886 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
888 0xfe000010, 0xff100010,
889 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
891 0xfe100010, 0xff100010,
892 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
893
894 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 895};
896
16980d0b
JB		 897/* Neon opcode table: This does not encode the top byte -- that is
898 checked by the print_insn_neon routine, as it depends on whether we are
899 doing thumb32 or arm32 disassembly. */
900
901/* print_insn_neon recognizes the following format control codes:
902
903 %% %
904
c22aaad1 905 %c print condition code
e2efe87d
MGD		 906 %u print condition code (unconditional in ARM mode,
907 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 908 %A print v{st,ld}[1234] operands
909 %B print v{st,ld}[1234] any one operands
910 %C print v{st,ld}[1234] single->all operands
911 %D print scalar
912 %E print vmov, vmvn, vorr, vbic encoded constant
913 %F print vtbl,vtbx register list
914
915 %<bitfield>r print as an ARM register
916 %<bitfield>d print the bitfield in decimal
917 %<bitfield>e print the 2^N - bitfield in decimal
918 %<bitfield>D print as a NEON D register
919 %<bitfield>Q print as a NEON Q register
920 %<bitfield>R print as a NEON D or Q register
921 %<bitfield>Sn print byte scaled width limited by n
922 %<bitfield>Tn print short scaled width limited by n
923 %<bitfield>Un print long scaled width limited by n
43e65147 924
16980d0b
JB		 925 %<bitfield>'c print specified char iff bitfield is all ones
926 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 927 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 928
929static const struct opcode32 neon_opcodes[] =
930{
fe56b6ce 931 /* Extract. */
823d2571
TG		 932 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
933 0xf2b00840, 0xffb00850,
934 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
935 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
936 0xf2b00000, 0xffb00810,
937 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 938
fe56b6ce 939 /* Move data element to all lanes. */
823d2571
TG		 940 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
941 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
942 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
943 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
944 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
945 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 946
fe56b6ce 947 /* Table lookup. */
823d2571
TG		 948 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
949 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
950 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
951 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
952
8e79c3df 953 /* Half-precision conversions. */
823d2571
TG		 954 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
955 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
956 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
957 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 958
959 /* NEON fused multiply add instructions. */
823d2571
TG		 960 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
961 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
962 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
963 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 964
fe56b6ce 965 /* Two registers, miscellaneous. */
823d2571
TG		 966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
967 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
968 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
969 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
970 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
971 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
972 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
973 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
974 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
975 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
976 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
977 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
978 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
979 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
980 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
981 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
982 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
983 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
984 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
985 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
986 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
987 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
988 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
989 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
990 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
991 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
992 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
993 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
994 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
995 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
996 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
997 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
998 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
999 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1000 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1001 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1002 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1003 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1004 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1005 0xf3b20300, 0xffb30fd0,
1006 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1007 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1008 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1009 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1010 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1011 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1012 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1013 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1014 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1016 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1017 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1018 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1019 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1020 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1021 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1022 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1023 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1024 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1025 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1026 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1027 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1028 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1029 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1030 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1031 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1032 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1033 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1034 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1035 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1036 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1037 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1038 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1039 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1040 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1041 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1042 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1043 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1044 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1045 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1046 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1047 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1048 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1049 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1050 0xf3b30600, 0xffb30e10,
1051 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
16980d0b 1052
fe56b6ce 1053 /* Three registers of the same length. */
823d2571
TG		 1054 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1055 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1056 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1057 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1058 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1059 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1060 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1061 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1062 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1063 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1064 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1065 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1066 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1067 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1069 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1071 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1073 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1075 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1077 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1079 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1081 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1082 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1083 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1085 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1087 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1088 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1089 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1090 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1091 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1093 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1094 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1095 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1096 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1097 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1098 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1099 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1100 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1101 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1102 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1103 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1104 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1105 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1106 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1107 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1108 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1109 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1110 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1111 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1112 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1113 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1114 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1115 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1116 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1117 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1118 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1119 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1120 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1121 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1122 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1123 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1124 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1125 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1126 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1127 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1128 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1129 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1130 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1131 0xf2000b00, 0xff800f10,
1132 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1133 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1134 0xf2000b10, 0xff800f10,
1135 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1136 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1137 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1138 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1139 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1140 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1141 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1142 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1143 0xf3000b00, 0xff800f10,
1144 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1145 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1146 0xf2000000, 0xfe800f10,
1147 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1148 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1149 0xf2000010, 0xfe800f10,
1150 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1151 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1152 0xf2000100, 0xfe800f10,
1153 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1154 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1155 0xf2000200, 0xfe800f10,
1156 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1157 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1158 0xf2000210, 0xfe800f10,
1159 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1160 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1161 0xf2000300, 0xfe800f10,
1162 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1163 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1164 0xf2000310, 0xfe800f10,
1165 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1166 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1167 0xf2000400, 0xfe800f10,
1168 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1169 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1170 0xf2000410, 0xfe800f10,
1171 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1172 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1173 0xf2000500, 0xfe800f10,
1174 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1175 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1176 0xf2000510, 0xfe800f10,
1177 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1178 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1179 0xf2000600, 0xfe800f10,
1180 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1181 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1182 0xf2000610, 0xfe800f10,
1183 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1184 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1185 0xf2000700, 0xfe800f10,
1186 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1187 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1188 0xf2000710, 0xfe800f10,
1189 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1190 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1191 0xf2000910, 0xfe800f10,
1192 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1193 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1194 0xf2000a00, 0xfe800f10,
1195 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1196 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1197 0xf2000a10, 0xfe800f10,
1198 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1199 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1200 0xf3000b10, 0xff800f10,
1201 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1202 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1203 0xf3000c10, 0xff800f10,
1204 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1205
fe56b6ce 1206 /* One register and an immediate value. */
823d2571
TG		 1207 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1208 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1209 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1210 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1211 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1212 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1213 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1214 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1215 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1216 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1217 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1218 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1219 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1220 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1221 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1222 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1223 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1224 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1225 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1226 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1227 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1228 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1229 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1230 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1231 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1232 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1233
fe56b6ce 1234 /* Two registers and a shift amount. */
823d2571
TG		 1235 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1236 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1237 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1238 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1239 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1240 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1241 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1242 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1243 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1244 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1245 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1246 0xf2880950, 0xfeb80fd0,
1247 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1248 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1249 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1250 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1251 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1252 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1253 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1254 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1255 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1256 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1257 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1258 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1259 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1260 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1261 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1262 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1263 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1264 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1265 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1266 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1267 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1268 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1269 0xf2900950, 0xfeb00fd0,
1270 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1271 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1272 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1273 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1274 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1275 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1276 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1277 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1278 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1279 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1280 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1281 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1282 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1283 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1284 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1285 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1286 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1287 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1288 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1291 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1292 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1293 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1294 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1295 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1297 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1298 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1299 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1300 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1302 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1303 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1304 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1305 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1306 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1307 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1308 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1309 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1310 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1311 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1312 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1313 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1314 0xf2a00950, 0xfea00fd0,
1315 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1317 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1318 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1319 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1321 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1322 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1324 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1325 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1326 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1327 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1328 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1329 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1330 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1331 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1333 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1334 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1335 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1336 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1337 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1339 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1340 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1341 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1342 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1343 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1345 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1346 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1347 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1348 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1349 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1351 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1352 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1353 0xf2a00e10, 0xfea00e90,
1354 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1355
fe56b6ce 1356 /* Three registers of different lengths. */
823d2571
TG		 1357 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1358 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1359 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1360 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1361 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1362 0xf2800400, 0xff800f50,
1363 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1365 0xf2800600, 0xff800f50,
1366 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1367 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1368 0xf2800900, 0xff800f50,
1369 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1370 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1371 0xf2800b00, 0xff800f50,
1372 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1373 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1374 0xf2800d00, 0xff800f50,
1375 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377 0xf3800400, 0xff800f50,
1378 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380 0xf3800600, 0xff800f50,
1381 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1382 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1383 0xf2800000, 0xfe800f50,
1384 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386 0xf2800100, 0xfe800f50,
1387 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1388 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1389 0xf2800200, 0xfe800f50,
1390 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1391 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1392 0xf2800300, 0xfe800f50,
1393 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1395 0xf2800500, 0xfe800f50,
1396 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1397 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1398 0xf2800700, 0xfe800f50,
1399 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401 0xf2800800, 0xfe800f50,
1402 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1403 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1404 0xf2800a00, 0xfe800f50,
1405 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0xf2800c00, 0xfe800f50,
1408 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1409
fe56b6ce 1410 /* Two registers and a scalar. */
823d2571
TG		 1411 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1412 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1413 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1414 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1415 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1416 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1429 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1430 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1434 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1443 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1449 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450 0xf2800240, 0xfe800f50,
1451 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1453 0xf2800640, 0xfe800f50,
1454 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456 0xf2800a40, 0xfe800f50,
1457 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1459 0xf2800e40, 0xff800f50,
1460 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1462 0xf2800f40, 0xff800f50,
1463 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1465 0xf3800e40, 0xff800f50,
1466 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1468 0xf3800f40, 0xff800f50,
1469 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1470 },
16980d0b 1471
fe56b6ce 1472 /* Element and structure load/store. */
823d2571
TG		 1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1474 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1476 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1478 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1480 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1482 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1486 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1488 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1490 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1496 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1511
1512 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1513};
1514
8f06b2d8
PB		 1515/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1516 ordered: they must be searched linearly from the top to obtain a correct
1517 match. */
1518
1519/* print_insn_arm recognizes the following format control codes:
1520
1521 %% %
1522
1523 %a print address for ldr/str instruction
1524 %s print address for ldr/str halfword/signextend instruction
c1e26897 1525 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 1526 %b print branch destination
1527 %c print condition code (always bits 28-31)
1528 %m print register mask for ldm/stm instruction
1529 %o print operand2 (immediate or register + shift)
1530 %p print 'p' iff bits 12-15 are 15
1531 %t print 't' iff bit 21 set and bit 24 clear
1532 %B print arm BLX(1) destination
1533 %C print the PSR sub type.
62b3e311
PB		 1534 %U print barrier type.
1535 %P print address for pli instruction.
8f06b2d8
PB		 1536
1537 %<bitfield>r print as an ARM register
9eb6c0f1 1538 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 1539 %<bitfield>R as %r but r15 is UNPREDICTABLE
1540 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1541 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 1542 %<bitfield>d print the bitfield in decimal
43e65147 1543 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 1544 %<bitfield>x print the bitfield in hex
1545 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 1546
16980d0b
JB		 1547 %<bitfield>'c print specified char iff bitfield is all ones
1548 %<bitfield>`c print specified char iff bitfield is all zeroes
1549 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 1550
8f06b2d8
PB		 1551 %e print arm SMI operand (bits 0..7,8..19).
1552 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 1553 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1554 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 1555
8f06b2d8
PB		 1556static const struct opcode32 arm_opcodes[] =
1557{
1558 /* ARM instructions. */
823d2571
TG		 1559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1560 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1562 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1563
1564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1565 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1567 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1569 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1571 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1573 0x00800090, 0x0fa000f0,
1574 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1576 0x00a00090, 0x0fa000f0,
1577 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 1578
53c4b28b 1579 /* V8 instructions. */
823d2571
TG		 1580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1581 0x0320f005, 0x0fffffff, "sevl"},
1582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1583 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
1584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1585 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
1586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1587 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1589 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1591 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
1592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1593 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
1594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1595 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
1596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1597 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
1598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1599 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
1600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1601 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
1602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1603 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
1604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1605 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
1606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1607 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
1608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1609 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
1610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1611 0x01f00c9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
dd5181d5 1612 /* CRC32 instructions. */
823d2571
TG		 1613 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1614 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1615 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1616 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1617 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1618 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1619 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1620 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1621 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1622 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1623 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1624 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 1625
ddfded2f
MW		 1626 /* Privileged Access Never extension instructions. */
1627 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1628 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1629
90ec0d68 1630 /* Virtualization Extension instructions. */
823d2571
TG		 1631 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1632 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 1633
eea54501 1634 /* Integer Divide Extension instructions. */
823d2571
TG		 1635 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1636 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1637 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1638 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 1639
60e5ef9f 1640 /* MP Extension instructions. */
823d2571 1641 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 1642
62b3e311 1643 /* V7 instructions. */
823d2571
TG		 1644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 1651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1652 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 1653
c19d1205 1654 /* ARM V6T2 instructions. */
823d2571
TG		 1655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1656 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1658 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1660 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1662 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1663
1664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1665 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1667 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1668
1669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1670 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
1671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1672 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1674 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1676 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 1677
f4c65163 1678 /* ARM Security extension instructions. */
823d2571
TG		 1679 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1680 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 1681
8f06b2d8 1682 /* ARM V6K instructions. */
823d2571
TG		 1683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1684 0xf57ff01f, 0xffffffff, "clrex"},
1685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1686 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1688 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1690 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1692 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1694 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1696 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 1697
8f06b2d8 1698 /* ARM V6K NOP hints. */
823d2571
TG		 1699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1700 0x0320f001, 0x0fffffff, "yield%c"},
1701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1702 0x0320f002, 0x0fffffff, "wfe%c"},
1703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1704 0x0320f003, 0x0fffffff, "wfi%c"},
1705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1706 0x0320f004, 0x0fffffff, "sev%c"},
1707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1708 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 1709
fe56b6ce 1710 /* ARM V6 instructions. */
823d2571
TG		 1711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1712 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1714 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1716 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1718 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1720 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1722 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1724 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1726 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1728 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1730 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1732 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1734 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1736 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1738 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1740 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1742 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1744 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1746 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1748 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1750 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1752 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1754 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1756 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1758 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1760 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1762 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1764 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1766 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1768 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1770 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1772 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1774 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1776 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1778 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1780 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1782 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1784 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
1785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1786 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
1787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1788 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
1789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1790 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
1791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1792 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
1793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1794 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
1795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1796 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
1797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1798 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
1799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1800 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
1801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1802 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
1803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1804 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
1805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1806 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
1807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1808 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
1809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1810 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
1811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1812 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
1813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1814 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
1815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1816 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
1817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1818 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
1819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1820 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
1821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1822 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
1823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1824 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
1825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1826 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
1827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1828 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
1829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1830 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
1831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1832 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
1833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1834 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
1835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1836 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
1837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1838 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
1839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1840 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
1841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1842 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
1843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1844 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
1845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1846 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
1847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1848 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
1849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1850 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
1851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1852 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
1853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1854 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
1855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1856 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
1857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1858 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
1859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1860 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
1861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1862 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1864 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1866 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1868 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
1869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1870 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1872 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1874 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1876 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
1877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1878 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1880 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1882 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1884 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
1885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1886 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1888 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1890 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1892 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
1893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1894 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1896 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1898 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
1899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1900 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
1901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1902 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1904 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1906 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1908 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
1909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1910 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
1911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1912 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
1913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1914 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
1915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1916 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1918 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1920 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1922 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1924 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
1925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1926 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1928 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1930 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
1931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1932 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
1933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1934 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
1935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1936 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
1937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1938 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
1939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1940 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
1941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1942 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
1943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1944 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
1945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1946 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1948 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
1949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1950 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
1951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1952 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
1953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1954 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 1955
8f06b2d8 1956 /* V5J instruction. */
823d2571
TG		 1957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
1958 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 1959
8f06b2d8 1960 /* V5 Instructions. */
823d2571
TG		 1961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1962 0xe1200070, 0xfff000f0,
1963 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
1964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1965 0xfa000000, 0xfe000000, "blx\t%B"},
1966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1967 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
1968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1969 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
1970
1971 /* V5E "El Segundo" Instructions. */
1972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1973 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
1974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1975 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
1976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1977 0xf450f000, 0xfc70f000, "pld\t%a"},
1978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1979 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1981 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1983 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1985 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
1986
1987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1988 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1990 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
1991
1992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1993 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1995 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1997 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1999 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2000
2001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2002 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2004 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2006 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2008 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2009
2010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2011 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2013 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2014
2015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2016 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2018 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2020 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2022 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 2023
8f06b2d8 2024 /* ARM Instructions. */
823d2571
TG		 2025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2026 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2027
2028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2029 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2031 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2033 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2035 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2037 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2039 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2040
2041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2042 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2044 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2046 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2048 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2049
2050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2051 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2053 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2055 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2057 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2058
2059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2060 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2062 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2064 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2065
2066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2067 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2069 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2071 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2072
2073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2074 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2076 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2078 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2079
2080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2081 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2083 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2085 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2086
2087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2088 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2090 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2092 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2093
2094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2095 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2097 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2099 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2100
2101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2102 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2104 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2106 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2107
2108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2109 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2111 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2113 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2114
2115 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2116 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2118 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2120 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2121
2122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2123 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2125 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2127 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2128
2129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2130 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 2131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2132 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 2133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a
AV		 2134 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2136 0x0130f000, 0x0ff0f010, "bx%c\t%0-3r"},
823d2571
TG		 2137
2138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2139 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2141 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2143 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2144
2145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2146 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2148 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2150 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2151
2152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2153 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2155 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2157 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2158
2159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2160 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2162 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2164 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2166 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2168 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2170 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2172 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2173
2174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2175 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2177 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2179 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2180
2181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2182 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2184 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2186 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2187
2188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2189 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2191 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2192
2193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2194 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2195
2196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2197 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2199 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2200
2201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2202 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2204 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2206 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2208 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2210 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2212 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2214 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2216 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2218 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2220 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2222 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2224 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2226 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2228 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2230 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2232 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2234 0x092d0000, 0x0fff0000, "push%c\t%m"},
2235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2236 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2238 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2239
2240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2241 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2243 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2245 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2247 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2249 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2251 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2253 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2255 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2257 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2259 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2261 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2263 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2265 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2267 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2269 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2271 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2273 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2275 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2277 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2278
2279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2280 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2282 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 2283
2284 /* The rest. */
4ab90a7a
AV		 2285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2286 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 2287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2288 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2289 {ARM_FEATURE_CORE_LOW (0),
2290 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 2291};
2292
2293/* print_insn_thumb16 recognizes the following format control codes:
2294
2295 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2296 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2297 %<bitfield>I print bitfield as a signed decimal
2298 (top bit of range being the sign bit)
2299 %N print Thumb register mask (with LR)
2300 %O print Thumb register mask (with PC)
2301 %M print Thumb register mask
2302 %b print CZB's 6-bit unsigned branch destination
2303 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 2304 %c print the condition code
2305 %C print the condition code, or "s" if not conditional
2306 %x print warning if conditional an not at end of IT block"
2307 %X print "\t; unpredictable <IT:code>" if conditional
2308 %I print IT instruction suffix and operands
4547cb56 2309 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 2310 %<bitfield>r print bitfield as an ARM register
2311 %<bitfield>d print bitfield as a decimal
2312 %<bitfield>H print (bitfield * 2) as a decimal
2313 %<bitfield>W print (bitfield * 4) as a decimal
2314 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2315 %<bitfield>B print Thumb branch destination (signed displacement)
2316 %<bitfield>c print bitfield as a condition code
2317 %<bitnum>'c print specified char iff bit is one
2318 %<bitnum>?ab print a if bit is one else print b. */
2319
2320static const struct opcode16 thumb_opcodes[] =
2321{
2322 /* Thumb instructions. */
2323
53c4b28b 2324 /* ARM V8 instructions. */
823d2571
TG		 2325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 2327 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 2328
8f06b2d8 2329 /* ARM V6K no-argument instructions. */
823d2571
TG		 2330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 2336
2337 /* ARM V6T2 instructions. */
823d2571
TG		 2338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
2340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 2341
2342 /* ARM V6. */
823d2571
TG		 2343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 2354
2355 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 2356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2357 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 2358 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 2359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2360 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 2361 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 2362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2363 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 2364 /* Format 4. */
823d2571
TG		 2365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 2381 /* format 13 */
823d2571
TG		 2382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 2384 /* format 5 */
823d2571
TG		 2385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 2389 /* format 14 */
823d2571
TG		 2390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 2392 /* format 2 */
823d2571
TG		 2393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2394 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2396 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2398 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2400 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 2401 /* format 8 */
823d2571
TG		 2402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2403 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2405 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2407 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2408 /* format 7 */
823d2571
TG		 2409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2410 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2412 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2413 /* format 1 */
823d2571
TG		 2414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2416 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 2419 /* format 3 */
823d2571
TG		 2420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 2424 /* format 6 */
823d2571
TG		 2425 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2427 0x4800, 0xF800,
2428 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 2429 /* format 9 */
823d2571
TG		 2430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2431 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2433 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2435 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2437 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 2438 /* format 10 */
823d2571
TG		 2439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2440 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2442 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 2443 /* format 11 */
823d2571
TG		 2444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2445 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2447 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 2448 /* format 12 */
823d2571
TG		 2449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2450 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2452 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 2453 /* format 15 */
823d2571
TG		 2454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 2456 /* format 17 */
823d2571 2457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 2458 /* format 16 */
823d2571
TG		 2459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 2462 /* format 18 */
823d2571 2463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 2464
2465 /* The E800 .. FFFF range is unconditionally redirected to the
2466 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2467 are processed via that table. Thus, we can never encounter a
2468 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 2469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2470 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 2471};
2472
2473/* Thumb32 opcodes use the same table structure as the ARM opcodes.
2474 We adopt the convention that hw1 is the high 16 bits of .value and
2475 .mask, hw2 the low 16 bits.
2476
2477 print_insn_thumb32 recognizes the following format control codes:
2478
2479 %% %
2480
2481 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2482 %M print a modified 12-bit immediate (same location)
2483 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2484 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 2485 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 2486 %S print a possibly-shifted Rm
2487
32a94698 2488 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 2489 %a print the address of a plain load/store
2490 %w print the width and signedness of a core load/store
2491 %m print register mask for ldm/stm
2492
2493 %E print the lsb and width fields of a bfc/bfi instruction
2494 %F print the lsb and width fields of a sbfx/ubfx instruction
2495 %b print a conditional branch offset
2496 %B print an unconditional branch offset
2497 %s print the shift field of an SSAT instruction
2498 %R print the rotation field of an SXT instruction
62b3e311
PB		 2499 %U print barrier type.
2500 %P print address for pli instruction.
c22aaad1
PB		 2501 %c print the condition code
2502 %x print warning if conditional an not at end of IT block"
2503 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 2504
2505 %<bitfield>d print bitfield in decimal
f0fba320 2506 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 2507 %<bitfield>W print bitfield*4 in decimal
2508 %<bitfield>r print bitfield as an ARM register
dd5181d5
KT		 2509 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
2510 %<bitfield>S as %<>R but r13 is UNPREDICTABLE
8f06b2d8
PB		 2511 %<bitfield>c print bitfield as a condition code
2512
16980d0b
JB		 2513 %<bitfield>'c print specified char iff bitfield is all ones
2514 %<bitfield>`c print specified char iff bitfield is all zeroes
2515 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 2516
2517 With one exception at the bottom (done because BL and BLX(1) need
2518 to come dead last), this table was machine-sorted first in
2519 decreasing order of number of bits set in the mask, then in
2520 increasing numeric order of mask, then in increasing numeric order
2521 of opcode. This order is not the clearest for a human reader, but
2522 is guaranteed never to catch a special-case bit pattern with a more
2523 general mask, which is important, because this instruction encoding
2524 makes heavy use of special-case bit patterns. */
2525static const struct opcode32 thumb32_opcodes[] =
2526{
53c4b28b 2527 /* V8 instructions. */
823d2571
TG		 2528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2529 0xf3af8005, 0xffffffff, "sevl%c.w"},
2530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2531 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2533 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2535 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2537 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2539 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2541 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2543 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2545 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2547 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2549 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2551 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2553 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2555 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2557 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2559 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 2560
dd5181d5 2561 /* CRC32 instructions. */
823d2571
TG		 2562 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2563 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
2564 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2565 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
2566 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2567 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
2568 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2569 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
2570 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2571 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
2572 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2573 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
dd5181d5 2574
62b3e311 2575 /* V7 instructions. */
823d2571
TG		 2576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2583 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2584 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2585 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2586 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 2587
90ec0d68 2588 /* Virtualization Extension instructions. */
823d2571 2589 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 2590 /* We skip ERET as that is SUBS pc, lr, #0. */
2591
60e5ef9f 2592 /* MP Extension instructions. */
823d2571 2593 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 2594
f4c65163 2595 /* Security extension instructions. */
823d2571 2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 2597
8f06b2d8 2598 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 2599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2605 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2607
2608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2609 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2611 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2613 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2615 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2617 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2619 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2621 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2623 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2625 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2627 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2629 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2631 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2633 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2635 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
2636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2637 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
2638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2639 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2641 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2643 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2645 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2647 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2649 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2651 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2653 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2655 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
2656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2657 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2659 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2661 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2663 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2665 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2667 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2669 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2671 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2673 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2675 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2677 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2679 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2681 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2683 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2685 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2687 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2689 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2691 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2693 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2695 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2697 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2699 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2701 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2703 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2705 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2707 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2709 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2711 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2713 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2715 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2717 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2719 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2721 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2723 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2725 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2727 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2729 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2731 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2733 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2735 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2737 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2739 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2741 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2743 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2745 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2747 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2749 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2751 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2753 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2755 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2757 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2759 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2761 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2763 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
2764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2765 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
2766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 2767 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 2768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2769 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
2770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2771 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
2772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2773 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2775 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
2776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2777 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
2778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2779 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2781 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2783 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2785 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2787 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2789 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2791 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2793 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
2794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2795 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
2796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2797 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
2798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2799 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
2800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2801 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
2802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2803 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
2804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2805 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
2806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2807 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
2808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2809 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
2810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2811 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
2812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2813 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
2814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2815 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
2816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2817 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2819 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2821 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2823 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2825 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2827 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2829 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2831 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2833 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
2834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2835 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
2836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2837 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
2838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2839 0xf810f000, 0xff70f000, "pld%c\t%a"},
2840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2841 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2843 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2845 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2847 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2849 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2851 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2853 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2855 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
2856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2857 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
2858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2859 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2861 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2863 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
2864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2865 0xfb100000, 0xfff000c0,
2866 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2868 0xfbc00080, 0xfff000c0,
2869 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2871 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2873 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 2875 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 2876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2877 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2879 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
2880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2881 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
2882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2883 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
2884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2885 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2887 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
2888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2889 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
2890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2891 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
2892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2893 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
2894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2895 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
2896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2897 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
2898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2899 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
2900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2901 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2903 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2905 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2907 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2909 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2911 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
2912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2913 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
2914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2915 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2917 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
2918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2919 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2921 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
2922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2923 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
2924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2925 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2927 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
2928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2929 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
2930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2931 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
2932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2933 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
2934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2935 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
2936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2937 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
2938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2939 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2941 0xe9400000, 0xff500000,
2942 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
2943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2944 0xe9500000, 0xff500000,
2945 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
2946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2947 0xe8600000, 0xff700000,
2948 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
2949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2950 0xe8700000, 0xff700000,
2951 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
2952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2953 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
2954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2955 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 2956
2957 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 2958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2959 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
2960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2961 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
2962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2963 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
2964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2965 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 2966
8f06b2d8 2967 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 2968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2969 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
2970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2971 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 2972
2973 /* Fallback. */
823d2571
TG		 2974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2975 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2976 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 2977};
ff4a8d2b 2978
8f06b2d8
PB		 2979static const char *const arm_conditional[] =
2980{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 2981 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 2982
2983static const char *const arm_fp_const[] =
2984{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
2985
2986static const char *const arm_shift[] =
2987{"lsl", "lsr", "asr", "ror"};
2988
2989typedef struct
2990{
2991 const char *name;
2992 const char *description;
2993 const char *reg_names[16];
2994}
2995arm_regname;
2996
2997static const arm_regname regnames[] =
2998{
2999 { "raw" , "Select raw register names",
3000 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3001 { "gcc", "Select register names used by GCC",
3002 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
3003 { "std", "Select register names used in ARM's ISA documentation",
3004 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
3005 { "apcs", "Select register names used in the APCS",
3006 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
3007 { "atpcs", "Select register names used in the ATPCS",
3008 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
3009 { "special-atpcs", "Select special register names used in the ATPCS",
3010 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
3011};
3012
3013static const char *const iwmmxt_wwnames[] =
3014{"b", "h", "w", "d"};
3015
3016static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 3017{"b", "bus", "bc", "bss",
3018 "h", "hus", "hc", "hss",
3019 "w", "wus", "wc", "wss",
3020 "d", "dus", "dc", "dss"
8f06b2d8
PB		 3021};
3022
3023static const char *const iwmmxt_regnames[] =
3024{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3025 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3026};
3027
3028static const char *const iwmmxt_cregnames[] =
3029{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3030 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3031};
3032
3033/* Default to GCC register name set. */
3034static unsigned int regname_selected = 1;
3035
3036#define NUM_ARM_REGNAMES NUM_ELEM (regnames)
3037#define arm_regnames regnames[regname_selected].reg_names
3038
3039static bfd_boolean force_thumb = FALSE;
3040
c22aaad1
PB		 3041/* Current IT instruction state. This contains the same state as the IT
3042 bits in the CPSR. */
3043static unsigned int ifthen_state;
3044/* IT state for the next instruction. */
3045static unsigned int ifthen_next_state;
3046/* The address of the insn for which the IT state is valid. */
3047static bfd_vma ifthen_address;
3048#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 3049/* Indicates that the current Conditional state is unconditional or outside
3050 an IT block. */
3051#define COND_UNCOND 16
c22aaad1 3052
8f06b2d8
PB		 3053\f
3054/* Functions. */
3055int
3056get_arm_regname_num_options (void)
3057{
3058 return NUM_ARM_REGNAMES;
3059}
3060
3061int
3062set_arm_regname_option (int option)
3063{
3064 int old = regname_selected;
3065 regname_selected = option;
3066 return old;
3067}
3068
3069int
fe56b6ce
NC		 3070get_arm_regnames (int option,
3071 const char **setname,
3072 const char **setdescription,
8f06b2d8
PB		 3073 const char *const **register_names)
3074{
3075 *setname = regnames[option].name;
3076 *setdescription = regnames[option].description;
3077 *register_names = regnames[option].reg_names;
3078 return 16;
3079}
3080
16980d0b
JB		 3081/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3082 Returns pointer to following character of the format string and
3083 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 3084 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 3085
3086static const char *
fe56b6ce
NC		 3087arm_decode_bitfield (const char *ptr,
3088 unsigned long insn,
3089 unsigned long *valuep,
3090 int *widthp)
16980d0b
JB		 3091{
3092 unsigned long value = 0;
3093 int width = 0;
43e65147
L		 3094
3095 do
16980d0b
JB		 3096 {
3097 int start, end;
3098 int bits;
3099
3100 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3101 start = start * 10 + *ptr - '0';
3102 if (*ptr == '-')
3103 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3104 end = end * 10 + *ptr - '0';
3105 else
3106 end = start;
3107 bits = end - start;
3108 if (bits < 0)
3109 abort ();
3110 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3111 width += bits + 1;
3112 }
3113 while (*ptr++ == ',');
3114 *valuep = value;
3115 if (widthp)
3116 *widthp = width;
3117 return ptr - 1;
3118}
3119
8f06b2d8 3120static void
37b37b2d 3121arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 3122 bfd_boolean print_shift)
8f06b2d8
PB		 3123{
3124 func (stream, "%s", arm_regnames[given & 0xf]);
3125
3126 if ((given & 0xff0) != 0)
3127 {
3128 if ((given & 0x10) == 0)
3129 {
3130 int amount = (given & 0xf80) >> 7;
3131 int shift = (given & 0x60) >> 5;
3132
3133 if (amount == 0)
3134 {
3135 if (shift == 3)
3136 {
3137 func (stream, ", rrx");
3138 return;
3139 }
3140
3141 amount = 32;
3142 }
3143
37b37b2d
RE		 3144 if (print_shift)
3145 func (stream, ", %s #%d", arm_shift[shift], amount);
3146 else
3147 func (stream, ", #%d", amount);
8f06b2d8 3148 }
74bdfecf 3149 else if ((given & 0x80) == 0x80)
aefd8a40 3150 func (stream, "\t; <illegal shifter operand>");
37b37b2d 3151 else if (print_shift)
8f06b2d8
PB		 3152 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3153 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 3154 else
3155 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 3156 }
3157}
3158
c1e26897
NC		 3159#define W_BIT 21
3160#define I_BIT 22
3161#define U_BIT 23
3162#define P_BIT 24
3163
3164#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3165#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3166#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3167#define PRE_BIT_SET (given & (1 << P_BIT))
3168
8f06b2d8
PB		 3169/* Print one coprocessor instruction on INFO->STREAM.
3170 Return TRUE if the instuction matched, FALSE if this is not a
3171 recognised coprocessor instruction. */
3172
3173static bfd_boolean
fe56b6ce
NC		 3174print_insn_coprocessor (bfd_vma pc,
3175 struct disassemble_info *info,
3176 long given,
8f06b2d8
PB		 3177 bfd_boolean thumb)
3178{
3179 const struct opcode32 *insn;
3180 void *stream = info->stream;
3181 fprintf_ftype func = info->fprintf_func;
3182 unsigned long mask;
2edcd244 3183 unsigned long value = 0;
c22aaad1 3184 int cond;
823d2571
TG		 3185 struct arm_private_data *private_data = info->private_data;
3186 arm_feature_set allowed_arches = ARM_ARCH_NONE;
3187
3188 ARM_FEATURE_COPY (allowed_arches, private_data->features);
8f06b2d8
PB		 3189
3190 for (insn = coprocessor_opcodes; insn->assembler; insn++)
3191 {
ff4a8d2b
NC		 3192 unsigned long u_reg = 16;
3193 bfd_boolean is_unpredictable = FALSE;
05413229 3194 signed long value_in_comment = 0;
0313a2b8
NC		 3195 const char *c;
3196
823d2571 3197 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 3198 switch (insn->value)
3199 {
3200 case SENTINEL_IWMMXT_START:
3201 if (info->mach != bfd_mach_arm_XScale
3202 && info->mach != bfd_mach_arm_iWMMXt
3203 && info->mach != bfd_mach_arm_iWMMXt2)
3204 do
3205 insn++;
823d2571
TG		 3206 while ((! ARM_FEATURE_ZERO (insn->arch))
3207 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 3208 continue;
3209
3210 case SENTINEL_IWMMXT_END:
3211 continue;
3212
3213 case SENTINEL_GENERIC_START:
823d2571 3214 ARM_FEATURE_COPY (allowed_arches, private_data->features);
05413229
NC		 3215 continue;
3216
3217 default:
3218 abort ();
3219 }
8f06b2d8
PB		 3220
3221 mask = insn->mask;
3222 value = insn->value;
3223 if (thumb)
3224 {
3225 /* The high 4 bits are 0xe for Arm conditional instructions, and
3226 0xe for arm unconditional instructions. The rest of the
3227 encoding is the same. */
3228 mask |= 0xf0000000;
3229 value |= 0xe0000000;
c22aaad1
PB		 3230 if (ifthen_state)
3231 cond = IFTHEN_COND;
3232 else
e2efe87d 3233 cond = COND_UNCOND;
8f06b2d8
PB		 3234 }
3235 else
3236 {
3237 /* Only match unconditional instuctions against unconditional
3238 patterns. */
3239 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 3240 {
3241 mask |= 0xf0000000;
e2efe87d 3242 cond = COND_UNCOND;
c22aaad1
PB		 3243 }
3244 else
3245 {
3246 cond = (given >> 28) & 0xf;
3247 if (cond == 0xe)
e2efe87d 3248 cond = COND_UNCOND;
c22aaad1 3249 }
8f06b2d8 3250 }
823d2571 3251
0313a2b8
NC		 3252 if ((given & mask) != value)
3253 continue;
8f06b2d8 3254
823d2571 3255 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 3256 continue;
3257
3258 for (c = insn->assembler; *c; c++)
3259 {
3260 if (*c == '%')
8f06b2d8 3261 {
0313a2b8 3262 switch (*++c)
8f06b2d8 3263 {
0313a2b8
NC		 3264 case '%':
3265 func (stream, "%%");
3266 break;
3267
3268 case 'A':
05413229 3269 {
79862e45 3270 int rn = (given >> 16) & 0xf;
f8b960bc 3271 bfd_vma offset = given & 0xff;
0313a2b8 3272
05413229 3273 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 3274
79862e45
DJ		 3275 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3276 {
3277 /* Not unindexed. The offset is scaled. */
3278 offset = offset * 4;
3279 if (NEGATIVE_BIT_SET)
3280 offset = - offset;
3281 if (rn != 15)
3282 value_in_comment = offset;
3283 }
3284
c1e26897 3285 if (PRE_BIT_SET)
05413229
NC		 3286 {
3287 if (offset)
fe56b6ce 3288 func (stream, ", #%d]%s",
d908c8af 3289 (int) offset,
c1e26897 3290 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 3291 else if (NEGATIVE_BIT_SET)
3292 func (stream, ", #-0]");
05413229
NC		 3293 else
3294 func (stream, "]");
3295 }
3296 else
3297 {
0313a2b8 3298 func (stream, "]");
8f06b2d8 3299
c1e26897 3300 if (WRITEBACK_BIT_SET)
05413229
NC		 3301 {
3302 if (offset)
d908c8af 3303 func (stream, ", #%d", (int) offset);
26d97720
NS		 3304 else if (NEGATIVE_BIT_SET)
3305 func (stream, ", #-0");
05413229
NC		 3306 }
3307 else
fe56b6ce 3308 {
26d97720
NS		 3309 func (stream, ", {%s%d}",
3310 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 3311 (int) offset);
fe56b6ce
NC		 3312 value_in_comment = offset;
3313 }
05413229 3314 }
79862e45
DJ		 3315 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3316 {
3317 func (stream, "\t; ");
6844b2c2
MGD		 3318 /* For unaligned PCs, apply off-by-alignment
3319 correction. */
43e65147 3320 info->print_address_func (offset + pc
6844b2c2
MGD		 3321 + info->bytes_per_chunk * 2
3322 - (pc & 3),
3323 info);
79862e45 3324 }
05413229 3325 }
0313a2b8 3326 break;
8f06b2d8 3327
0313a2b8
NC		 3328 case 'B':
3329 {
3330 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3331 int offset = (given >> 1) & 0x3f;
3332
3333 if (offset == 1)
3334 func (stream, "{d%d}", regno);
3335 else if (regno + offset > 32)
3336 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3337 else
3338 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3339 }
3340 break;
8f06b2d8 3341
e2efe87d
MGD		 3342 case 'u':
3343 if (cond != COND_UNCOND)
3344 is_unpredictable = TRUE;
3345
3346 /* Fall through. */
0313a2b8
NC		 3347 case 'c':
3348 func (stream, "%s", arm_conditional[cond]);
3349 break;
8f06b2d8 3350
0313a2b8
NC		 3351 case 'I':
3352 /* Print a Cirrus/DSP shift immediate. */
3353 /* Immediates are 7bit signed ints with bits 0..3 in
3354 bits 0..3 of opcode and bits 4..6 in bits 5..7
3355 of opcode. */
3356 {
3357 int imm;
8f06b2d8 3358
0313a2b8 3359 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 3360
0313a2b8
NC		 3361 /* Is ``imm'' a negative number? */
3362 if (imm & 0x40)
24b4cf66 3363 imm -= 0x80;
8f06b2d8 3364
0313a2b8
NC		 3365 func (stream, "%d", imm);
3366 }
3367
3368 break;
8f06b2d8 3369
0313a2b8
NC		 3370 case 'F':
3371 switch (given & 0x00408000)
3372 {
3373 case 0:
3374 func (stream, "4");
3375 break;
3376 case 0x8000:
3377 func (stream, "1");
3378 break;
3379 case 0x00400000:
3380 func (stream, "2");
8f06b2d8 3381 break;
0313a2b8
NC		 3382 default:
3383 func (stream, "3");
3384 }
3385 break;
8f06b2d8 3386
0313a2b8
NC		 3387 case 'P':
3388 switch (given & 0x00080080)
3389 {
3390 case 0:
3391 func (stream, "s");
3392 break;
3393 case 0x80:
3394 func (stream, "d");
3395 break;
3396 case 0x00080000:
3397 func (stream, "e");
3398 break;
3399 default:
3400 func (stream, _("<illegal precision>"));
8f06b2d8 3401 break;
0313a2b8
NC		 3402 }
3403 break;
8f06b2d8 3404
0313a2b8
NC		 3405 case 'Q':
3406 switch (given & 0x00408000)
3407 {
3408 case 0:
3409 func (stream, "s");
8f06b2d8 3410 break;
0313a2b8
NC		 3411 case 0x8000:
3412 func (stream, "d");
8f06b2d8 3413 break;
0313a2b8
NC		 3414 case 0x00400000:
3415 func (stream, "e");
3416 break;
3417 default:
3418 func (stream, "p");
8f06b2d8 3419 break;
0313a2b8
NC		 3420 }
3421 break;
8f06b2d8 3422
0313a2b8
NC		 3423 case 'R':
3424 switch (given & 0x60)
3425 {
3426 case 0:
3427 break;
3428 case 0x20:
3429 func (stream, "p");
3430 break;
3431 case 0x40:
3432 func (stream, "m");
3433 break;
3434 default:
3435 func (stream, "z");
3436 break;
3437 }
3438 break;
16980d0b 3439
0313a2b8
NC		 3440 case '0': case '1': case '2': case '3': case '4':
3441 case '5': case '6': case '7': case '8': case '9':
3442 {
3443 int width;
8f06b2d8 3444
0313a2b8 3445 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 3446
0313a2b8
NC		 3447 switch (*c)
3448 {
ff4a8d2b
NC		 3449 case 'R':
3450 if (value == 15)
3451 is_unpredictable = TRUE;
3452 /* Fall through. */
0313a2b8 3453 case 'r':
ff4a8d2b
NC		 3454 if (c[1] == 'u')
3455 {
3456 /* Eat the 'u' character. */
3457 ++ c;
3458
3459 if (u_reg == value)
3460 is_unpredictable = TRUE;
3461 u_reg = value;
3462 }
0313a2b8
NC		 3463 func (stream, "%s", arm_regnames[value]);
3464 break;
3465 case 'D':
3466 func (stream, "d%ld", value);
3467 break;
3468 case 'Q':
3469 if (value & 1)
3470 func (stream, "<illegal reg q%ld.5>", value >> 1);
3471 else
3472 func (stream, "q%ld", value >> 1);
3473 break;
3474 case 'd':
3475 func (stream, "%ld", value);
05413229 3476 value_in_comment = value;
0313a2b8 3477 break;
6f1c2142
AM		 3478 case 'E':
3479 {
3480 /* Converts immediate 8 bit back to float value. */
3481 unsigned floatVal = (value & 0x80) << 24
3482 | (value & 0x3F) << 19
3483 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3484
3485 /* Quarter float have a maximum value of 31.0.
3486 Get floating point value multiplied by 1e7.
3487 The maximum value stays in limit of a 32-bit int. */
3488 unsigned decVal =
3489 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3490 (16 + (value & 0xF));
3491
3492 if (!(decVal % 1000000))
3493 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3494 floatVal, value & 0x80 ? '-' : ' ',
3495 decVal / 10000000,
3496 decVal % 10000000 / 1000000);
3497 else if (!(decVal % 10000))
3498 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3499 floatVal, value & 0x80 ? '-' : ' ',
3500 decVal / 10000000,
3501 decVal % 10000000 / 10000);
3502 else
3503 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3504 floatVal, value & 0x80 ? '-' : ' ',
3505 decVal / 10000000, decVal % 10000000);
3506 break;
3507 }
0313a2b8
NC		 3508 case 'k':
3509 {
3510 int from = (given & (1 << 7)) ? 32 : 16;
3511 func (stream, "%ld", from - value);
3512 }
3513 break;
8f06b2d8 3514
0313a2b8
NC		 3515 case 'f':
3516 if (value > 7)
3517 func (stream, "#%s", arm_fp_const[value & 7]);
3518 else
3519 func (stream, "f%ld", value);
3520 break;
4146fd53 3521
0313a2b8
NC		 3522 case 'w':
3523 if (width == 2)
3524 func (stream, "%s", iwmmxt_wwnames[value]);
3525 else
3526 func (stream, "%s", iwmmxt_wwssnames[value]);
3527 break;
4146fd53 3528
0313a2b8
NC		 3529 case 'g':
3530 func (stream, "%s", iwmmxt_regnames[value]);
3531 break;
3532 case 'G':
3533 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 3534 break;
8f06b2d8 3535
0313a2b8 3536 case 'x':
d1aaab3c 3537 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 3538 break;
8f06b2d8 3539
33399f07
MGD		 3540 case 'c':
3541 switch (value)
3542 {
3543 case 0:
3544 func (stream, "eq");
3545 break;
3546
3547 case 1:
3548 func (stream, "vs");
3549 break;
3550
3551 case 2:
3552 func (stream, "ge");
3553 break;
3554
3555 case 3:
3556 func (stream, "gt");
3557 break;
3558
3559 default:
3560 func (stream, "??");
3561 break;
3562 }
3563 break;
3564
0313a2b8
NC		 3565 case '`':
3566 c++;
3567 if (value == 0)
3568 func (stream, "%c", *c);
3569 break;
3570 case '\'':
3571 c++;
3572 if (value == ((1ul << width) - 1))
3573 func (stream, "%c", *c);
3574 break;
3575 case '?':
fe56b6ce 3576 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 3577 c += 1 << width;
3578 break;
3579 default:
3580 abort ();
3581 }
3582 break;
8f06b2d8 3583
0313a2b8
NC		 3584 case 'y':
3585 case 'z':
3586 {
3587 int single = *c++ == 'y';
3588 int regno;
3589
3590 switch (*c)
3591 {
3592 case '4': /* Sm pair */
3593 case '0': /* Sm, Dm */
3594 regno = given & 0x0000000f;
3595 if (single)
3596 {
3597 regno <<= 1;
3598 regno += (given >> 5) & 1;
16980d0b 3599 }
0313a2b8
NC		 3600 else
3601 regno += ((given >> 5) & 1) << 4;
3602 break;
8f06b2d8 3603
0313a2b8
NC		 3604 case '1': /* Sd, Dd */
3605 regno = (given >> 12) & 0x0000000f;
3606 if (single)
3607 {
3608 regno <<= 1;
3609 regno += (given >> 22) & 1;
3610 }
3611 else
3612 regno += ((given >> 22) & 1) << 4;
3613 break;
8f06b2d8 3614
0313a2b8
NC		 3615 case '2': /* Sn, Dn */
3616 regno = (given >> 16) & 0x0000000f;
3617 if (single)
8f06b2d8 3618 {
0313a2b8
NC		 3619 regno <<= 1;
3620 regno += (given >> 7) & 1;
8f06b2d8 3621 }
0313a2b8
NC		 3622 else
3623 regno += ((given >> 7) & 1) << 4;
3624 break;
7df76b80 3625
0313a2b8
NC		 3626 case '3': /* List */
3627 func (stream, "{");
3628 regno = (given >> 12) & 0x0000000f;
3629 if (single)
3630 {
3631 regno <<= 1;
3632 regno += (given >> 22) & 1;
3633 }
3634 else
3635 regno += ((given >> 22) & 1) << 4;
3636 break;
a7f8487e 3637
0313a2b8
NC		 3638 default:
3639 abort ();
8f06b2d8 3640 }
a7f8487e 3641
0313a2b8
NC		 3642 func (stream, "%c%d", single ? 's' : 'd', regno);
3643
3644 if (*c == '3')
8f06b2d8 3645 {
0313a2b8 3646 int count = given & 0xff;
a7f8487e 3647
0313a2b8
NC		 3648 if (single == 0)
3649 count >>= 1;
b34976b6 3650
0313a2b8 3651 if (--count)
8f06b2d8 3652 {
0313a2b8
NC		 3653 func (stream, "-%c%d",
3654 single ? 's' : 'd',
3655 regno + count);
8f06b2d8 3656 }
0313a2b8
NC		 3657
3658 func (stream, "}");
8f06b2d8 3659 }
0313a2b8
NC		 3660 else if (*c == '4')
3661 func (stream, ", %c%d", single ? 's' : 'd',
3662 regno + 1);
3663 }
3664 break;
3665
3666 case 'L':
3667 switch (given & 0x00400100)
3668 {
3669 case 0x00000000: func (stream, "b"); break;
3670 case 0x00400000: func (stream, "h"); break;
3671 case 0x00000100: func (stream, "w"); break;
3672 case 0x00400100: func (stream, "d"); break;
3673 default:
8f06b2d8 3674 break;
0313a2b8
NC		 3675 }
3676 break;
b34976b6 3677
0313a2b8
NC		 3678 case 'Z':
3679 {
0313a2b8
NC		 3680 /* given (20, 23) | given (0, 3) */
3681 value = ((given >> 16) & 0xf0) | (given & 0xf);
d908c8af 3682 func (stream, "%d", (int) value);
0313a2b8
NC		 3683 }
3684 break;
2d447fca 3685
0313a2b8
NC		 3686 case 'l':
3687 /* This is like the 'A' operator, except that if
3688 the width field "M" is zero, then the offset is
3689 *not* multiplied by four. */
3690 {
3691 int offset = given & 0xff;
3692 int multiplier = (given & 0x00000100) ? 4 : 1;
3693
3694 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3695
05413229
NC		 3696 if (multiplier > 1)
3697 {
3698 value_in_comment = offset * multiplier;
c1e26897 3699 if (NEGATIVE_BIT_SET)
05413229
NC		 3700 value_in_comment = - value_in_comment;
3701 }
3702
0313a2b8
NC		 3703 if (offset)
3704 {
c1e26897 3705 if (PRE_BIT_SET)
0313a2b8 3706 func (stream, ", #%s%d]%s",
c1e26897 3707 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3708 offset * multiplier,
c1e26897 3709 WRITEBACK_BIT_SET ? "!" : "");
0313a2b8
NC		 3710 else
3711 func (stream, "], #%s%d",
c1e26897 3712 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3713 offset * multiplier);
2d447fca 3714 }
0313a2b8
NC		 3715 else
3716 func (stream, "]");
3717 }
3718 break;
3719
3720 case 'r':
3721 {
3722 int imm4 = (given >> 4) & 0xf;
c1e26897
NC		 3723 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3724 int ubit = ! NEGATIVE_BIT_SET;
0313a2b8
NC		 3725 const char *rm = arm_regnames [given & 0xf];
3726 const char *rn = arm_regnames [(given >> 16) & 0xf];
2d447fca 3727
0313a2b8 3728 switch (puw_bits)
2d447fca 3729 {
0313a2b8
NC		 3730 case 1:
3731 case 3:
3732 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3733 if (imm4)
3734 func (stream, ", lsl #%d", imm4);
3735 break;
3736
3737 case 4:
3738 case 5:
3739 case 6:
3740 case 7:
3741 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3742 if (imm4 > 0)
3743 func (stream, ", lsl #%d", imm4);
3744 func (stream, "]");
3745 if (puw_bits == 5 || puw_bits == 7)
3746 func (stream, "!");
3747 break;
3748
3749 default:
3750 func (stream, "INVALID");
2d447fca 3751 }
0313a2b8
NC		 3752 }
3753 break;
2d447fca 3754
0313a2b8
NC		 3755 case 'i':
3756 {
3757 long imm5;
3758 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
3759 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
8f06b2d8 3760 }
0313a2b8
NC		 3761 break;
3762
3763 default:
3764 abort ();
3765 }
252b5132 3766 }
252b5132 3767 }
0313a2b8
NC		 3768 else
3769 func (stream, "%c", *c);
252b5132 3770 }
05413229
NC		 3771
3772 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 3773 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 3774
ff4a8d2b
NC		 3775 if (is_unpredictable)
3776 func (stream, UNPREDICTABLE_INSTRUCTION);
3777
0313a2b8 3778 return TRUE;
252b5132 3779 }
8f06b2d8 3780 return FALSE;
252b5132
RH		 3781}
3782
05413229
NC		 3783/* Decodes and prints ARM addressing modes. Returns the offset
3784 used in the address, if any, if it is worthwhile printing the
3785 offset as a hexadecimal value in a comment at the end of the
3786 line of disassembly. */
3787
3788static signed long
62b3e311
PB		 3789print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
3790{
3791 void *stream = info->stream;
3792 fprintf_ftype func = info->fprintf_func;
f8b960bc 3793 bfd_vma offset = 0;
62b3e311
PB		 3794
3795 if (((given & 0x000f0000) == 0x000f0000)
3796 && ((given & 0x02000000) == 0))
3797 {
05413229 3798 offset = given & 0xfff;
62b3e311
PB		 3799
3800 func (stream, "[pc");
3801
c1e26897 3802 if (PRE_BIT_SET)
62b3e311 3803 {
26d97720
NS		 3804 /* Pre-indexed. Elide offset of positive zero when
3805 non-writeback. */
3806 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 3807 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 3808
3809 if (NEGATIVE_BIT_SET)
3810 offset = -offset;
62b3e311
PB		 3811
3812 offset += pc + 8;
3813
3814 /* Cope with the possibility of write-back
3815 being used. Probably a very dangerous thing
3816 for the programmer to do, but who are we to
3817 argue ? */
26d97720 3818 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 3819 }
c1e26897 3820 else /* Post indexed. */
62b3e311 3821 {
d908c8af 3822 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 3823
c1e26897 3824 /* Ie ignore the offset. */
62b3e311
PB		 3825 offset = pc + 8;
3826 }
3827
3828 func (stream, "\t; ");
3829 info->print_address_func (offset, info);
05413229 3830 offset = 0;
62b3e311
PB		 3831 }
3832 else
3833 {
3834 func (stream, "[%s",
3835 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 3836
3837 if (PRE_BIT_SET)
62b3e311
PB		 3838 {
3839 if ((given & 0x02000000) == 0)
3840 {
26d97720 3841 /* Elide offset of positive zero when non-writeback. */
05413229 3842 offset = given & 0xfff;
26d97720 3843 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 3844 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 3845 }
3846 else
3847 {
26d97720 3848 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 3849 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 3850 }
3851
3852 func (stream, "]%s",
c1e26897 3853 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 3854 }
3855 else
3856 {
3857 if ((given & 0x02000000) == 0)
3858 {
26d97720 3859 /* Always show offset. */
05413229 3860 offset = given & 0xfff;
26d97720 3861 func (stream, "], #%s%d",
d908c8af 3862 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 3863 }
3864 else
3865 {
3866 func (stream, "], %s",
c1e26897 3867 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 3868 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 3869 }
3870 }
84919466
MR		 3871 if (NEGATIVE_BIT_SET)
3872 offset = -offset;
62b3e311 3873 }
05413229
NC		 3874
3875 return (signed long) offset;
62b3e311
PB		 3876}
3877
16980d0b
JB		 3878/* Print one neon instruction on INFO->STREAM.
3879 Return TRUE if the instuction matched, FALSE if this is not a
3880 recognised neon instruction. */
3881
3882static bfd_boolean
3883print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
3884{
3885 const struct opcode32 *insn;
3886 void *stream = info->stream;
3887 fprintf_ftype func = info->fprintf_func;
3888
3889 if (thumb)
3890 {
3891 if ((given & 0xef000000) == 0xef000000)
3892 {
0313a2b8 3893 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 3894 unsigned long bit28 = given & (1 << 28);
3895
3896 given &= 0x00ffffff;
3897 if (bit28)
3898 given |= 0xf3000000;
3899 else
3900 given |= 0xf2000000;
3901 }
3902 else if ((given & 0xff000000) == 0xf9000000)
3903 given ^= 0xf9000000 ^ 0xf4000000;
3904 else
3905 return FALSE;
3906 }
43e65147 3907
16980d0b
JB		 3908 for (insn = neon_opcodes; insn->assembler; insn++)
3909 {
3910 if ((given & insn->mask) == insn->value)
3911 {
05413229 3912 signed long value_in_comment = 0;
e2efe87d 3913 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 3914 const char *c;
3915
3916 for (c = insn->assembler; *c; c++)
3917 {
3918 if (*c == '%')
3919 {
3920 switch (*++c)
3921 {
3922 case '%':
3923 func (stream, "%%");
3924 break;
3925
e2efe87d
MGD		 3926 case 'u':
3927 if (thumb && ifthen_state)
3928 is_unpredictable = TRUE;
3929
3930 /* Fall through. */
c22aaad1
PB		 3931 case 'c':
3932 if (thumb && ifthen_state)
3933 func (stream, "%s", arm_conditional[IFTHEN_COND]);
3934 break;
3935
16980d0b
JB		 3936 case 'A':
3937 {
43e65147 3938 static const unsigned char enc[16] =
16980d0b
JB		 3939 {
3940 0x4, 0x14, /* st4 0,1 */
3941 0x4, /* st1 2 */
3942 0x4, /* st2 3 */
3943 0x3, /* st3 4 */
3944 0x13, /* st3 5 */
3945 0x3, /* st1 6 */
3946 0x1, /* st1 7 */
3947 0x2, /* st2 8 */
3948 0x12, /* st2 9 */
3949 0x2, /* st1 10 */
3950 0, 0, 0, 0, 0
3951 };
3952 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3953 int rn = ((given >> 16) & 0xf);
3954 int rm = ((given >> 0) & 0xf);
3955 int align = ((given >> 4) & 0x3);
3956 int type = ((given >> 8) & 0xf);
3957 int n = enc[type] & 0xf;
3958 int stride = (enc[type] >> 4) + 1;
3959 int ix;
43e65147 3960
16980d0b
JB		 3961 func (stream, "{");
3962 if (stride > 1)
3963 for (ix = 0; ix != n; ix++)
3964 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
3965 else if (n == 1)
3966 func (stream, "d%d", rd);
3967 else
3968 func (stream, "d%d-d%d", rd, rd + n - 1);
3969 func (stream, "}, [%s", arm_regnames[rn]);
3970 if (align)
8e560766 3971 func (stream, " :%d", 32 << align);
16980d0b
JB		 3972 func (stream, "]");
3973 if (rm == 0xd)
3974 func (stream, "!");
3975 else if (rm != 0xf)
3976 func (stream, ", %s", arm_regnames[rm]);
3977 }
3978 break;
43e65147 3979
16980d0b
JB		 3980 case 'B':
3981 {
3982 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3983 int rn = ((given >> 16) & 0xf);
3984 int rm = ((given >> 0) & 0xf);
3985 int idx_align = ((given >> 4) & 0xf);
3986 int align = 0;
3987 int size = ((given >> 10) & 0x3);
3988 int idx = idx_align >> (size + 1);
3989 int length = ((given >> 8) & 3) + 1;
3990 int stride = 1;
3991 int i;
3992
3993 if (length > 1 && size > 0)
3994 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 3995
16980d0b
JB		 3996 switch (length)
3997 {
3998 case 1:
3999 {
4000 int amask = (1 << size) - 1;
4001 if ((idx_align & (1 << size)) != 0)
4002 return FALSE;
4003 if (size > 0)
4004 {
4005 if ((idx_align & amask) == amask)
4006 align = 8 << size;
4007 else if ((idx_align & amask) != 0)
4008 return FALSE;
4009 }
4010 }
4011 break;
43e65147 4012
16980d0b
JB		 4013 case 2:
4014 if (size == 2 && (idx_align & 2) != 0)
4015 return FALSE;
4016 align = (idx_align & 1) ? 16 << size : 0;
4017 break;
43e65147 4018
16980d0b
JB		 4019 case 3:
4020 if ((size == 2 && (idx_align & 3) != 0)
4021 || (idx_align & 1) != 0)
4022 return FALSE;
4023 break;
43e65147 4024
16980d0b
JB		 4025 case 4:
4026 if (size == 2)
4027 {
4028 if ((idx_align & 3) == 3)
4029 return FALSE;
4030 align = (idx_align & 3) * 64;
4031 }
4032 else
4033 align = (idx_align & 1) ? 32 << size : 0;
4034 break;
43e65147 4035
16980d0b
JB		 4036 default:
4037 abort ();
4038 }
43e65147 4039
16980d0b
JB		 4040 func (stream, "{");
4041 for (i = 0; i < length; i++)
4042 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4043 rd + i * stride, idx);
4044 func (stream, "}, [%s", arm_regnames[rn]);
4045 if (align)
8e560766 4046 func (stream, " :%d", align);
16980d0b
JB		 4047 func (stream, "]");
4048 if (rm == 0xd)
4049 func (stream, "!");
4050 else if (rm != 0xf)
4051 func (stream, ", %s", arm_regnames[rm]);
4052 }
4053 break;
43e65147 4054
16980d0b
JB		 4055 case 'C':
4056 {
4057 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4058 int rn = ((given >> 16) & 0xf);
4059 int rm = ((given >> 0) & 0xf);
4060 int align = ((given >> 4) & 0x1);
4061 int size = ((given >> 6) & 0x3);
4062 int type = ((given >> 8) & 0x3);
4063 int n = type + 1;
4064 int stride = ((given >> 5) & 0x1);
4065 int ix;
43e65147 4066
16980d0b
JB		 4067 if (stride && (n == 1))
4068 n++;
4069 else
4070 stride++;
43e65147 4071
16980d0b
JB		 4072 func (stream, "{");
4073 if (stride > 1)
4074 for (ix = 0; ix != n; ix++)
4075 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4076 else if (n == 1)
4077 func (stream, "d%d[]", rd);
4078 else
4079 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4080 func (stream, "}, [%s", arm_regnames[rn]);
4081 if (align)
4082 {
91d6fa6a 4083 align = (8 * (type + 1)) << size;
16980d0b
JB		 4084 if (type == 3)
4085 align = (size > 1) ? align >> 1 : align;
4086 if (type == 2 || (type == 0 && !size))
8e560766 4087 func (stream, " :<bad align %d>", align);
16980d0b 4088 else
8e560766 4089 func (stream, " :%d", align);
16980d0b
JB		 4090 }
4091 func (stream, "]");
4092 if (rm == 0xd)
4093 func (stream, "!");
4094 else if (rm != 0xf)
4095 func (stream, ", %s", arm_regnames[rm]);
4096 }
4097 break;
43e65147 4098
16980d0b
JB		 4099 case 'D':
4100 {
4101 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4102 int size = (given >> 20) & 3;
4103 int reg = raw_reg & ((4 << size) - 1);
4104 int ix = raw_reg >> size >> 2;
43e65147 4105
16980d0b
JB		 4106 func (stream, "d%d[%d]", reg, ix);
4107 }
4108 break;
43e65147 4109
16980d0b 4110 case 'E':
fe56b6ce 4111 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 4112 {
4113 int bits = 0;
4114 int cmode = (given >> 8) & 0xf;
4115 int op = (given >> 5) & 0x1;
4116 unsigned long value = 0, hival = 0;
4117 unsigned shift;
4118 int size = 0;
0dbde4cf 4119 int isfloat = 0;
43e65147 4120
16980d0b
JB		 4121 bits |= ((given >> 24) & 1) << 7;
4122 bits |= ((given >> 16) & 7) << 4;
4123 bits |= ((given >> 0) & 15) << 0;
43e65147 4124
16980d0b
JB		 4125 if (cmode < 8)
4126 {
4127 shift = (cmode >> 1) & 3;
fe56b6ce 4128 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4129 size = 32;
4130 }
4131 else if (cmode < 12)
4132 {
4133 shift = (cmode >> 1) & 1;
fe56b6ce 4134 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4135 size = 16;
4136 }
4137 else if (cmode < 14)
4138 {
4139 shift = (cmode & 1) + 1;
fe56b6ce 4140 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4141 value |= (1ul << (8 * shift)) - 1;
4142 size = 32;
4143 }
4144 else if (cmode == 14)
4145 {
4146 if (op)
4147 {
fe56b6ce 4148 /* Bit replication into bytes. */
16980d0b
JB		 4149 int ix;
4150 unsigned long mask;
43e65147 4151
16980d0b
JB		 4152 value = 0;
4153 hival = 0;
4154 for (ix = 7; ix >= 0; ix--)
4155 {
4156 mask = ((bits >> ix) & 1) ? 0xff : 0;
4157 if (ix <= 3)
4158 value = (value << 8) | mask;
4159 else
4160 hival = (hival << 8) | mask;
4161 }
4162 size = 64;
4163 }
4164 else
4165 {
fe56b6ce
NC		 4166 /* Byte replication. */
4167 value = (unsigned long) bits;
16980d0b
JB		 4168 size = 8;
4169 }
4170 }
4171 else if (!op)
4172 {
fe56b6ce 4173 /* Floating point encoding. */
16980d0b 4174 int tmp;
43e65147 4175
fe56b6ce
NC		 4176 value = (unsigned long) (bits & 0x7f) << 19;
4177 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 4178 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 4179 value |= (unsigned long) tmp << 24;
16980d0b 4180 size = 32;
0dbde4cf 4181 isfloat = 1;
16980d0b
JB		 4182 }
4183 else
4184 {
4185 func (stream, "<illegal constant %.8x:%x:%x>",
4186 bits, cmode, op);
4187 size = 32;
4188 break;
4189 }
4190 switch (size)
4191 {
4192 case 8:
4193 func (stream, "#%ld\t; 0x%.2lx", value, value);
4194 break;
43e65147 4195
16980d0b
JB		 4196 case 16:
4197 func (stream, "#%ld\t; 0x%.4lx", value, value);
4198 break;
4199
4200 case 32:
0dbde4cf
JB		 4201 if (isfloat)
4202 {
4203 unsigned char valbytes[4];
4204 double fvalue;
43e65147 4205
0dbde4cf
JB		 4206 /* Do this a byte at a time so we don't have to
4207 worry about the host's endianness. */
4208 valbytes[0] = value & 0xff;
4209 valbytes[1] = (value >> 8) & 0xff;
4210 valbytes[2] = (value >> 16) & 0xff;
4211 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 4212
4213 floatformat_to_double
c1e26897
NC		 4214 (& floatformat_ieee_single_little, valbytes,
4215 & fvalue);
43e65147 4216
0dbde4cf
JB		 4217 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4218 value);
4219 }
4220 else
4e9d3b81 4221 func (stream, "#%ld\t; 0x%.8lx",
43e65147 4222 (long) (((value & 0x80000000L) != 0)
9d82ec38 4223 ? value | ~0xffffffffL : value),
c1e26897 4224 value);
16980d0b
JB		 4225 break;
4226
4227 case 64:
4228 func (stream, "#0x%.8lx%.8lx", hival, value);
4229 break;
43e65147 4230
16980d0b
JB		 4231 default:
4232 abort ();
4233 }
4234 }
4235 break;
43e65147 4236
16980d0b
JB		 4237 case 'F':
4238 {
4239 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4240 int num = (given >> 8) & 0x3;
43e65147 4241
16980d0b
JB		 4242 if (!num)
4243 func (stream, "{d%d}", regno);
4244 else if (num + regno >= 32)
4245 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4246 else
4247 func (stream, "{d%d-d%d}", regno, regno + num);
4248 }
4249 break;
7e8e6784 4250
16980d0b
JB		 4251
4252 case '0': case '1': case '2': case '3': case '4':
4253 case '5': case '6': case '7': case '8': case '9':
4254 {
4255 int width;
4256 unsigned long value;
4257
4258 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 4259
16980d0b
JB		 4260 switch (*c)
4261 {
4262 case 'r':
4263 func (stream, "%s", arm_regnames[value]);
4264 break;
4265 case 'd':
4266 func (stream, "%ld", value);
05413229 4267 value_in_comment = value;
16980d0b
JB		 4268 break;
4269 case 'e':
4270 func (stream, "%ld", (1ul << width) - value);
4271 break;
43e65147 4272
16980d0b
JB		 4273 case 'S':
4274 case 'T':
4275 case 'U':
05413229 4276 /* Various width encodings. */
16980d0b
JB		 4277 {
4278 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4279 int limit;
4280 unsigned low, high;
4281
4282 c++;
4283 if (*c >= '0' && *c <= '9')
4284 limit = *c - '0';
4285 else if (*c >= 'a' && *c <= 'f')
4286 limit = *c - 'a' + 10;
4287 else
4288 abort ();
4289 low = limit >> 2;
4290 high = limit & 3;
4291
4292 if (value < low || value > high)
4293 func (stream, "<illegal width %d>", base << value);
4294 else
4295 func (stream, "%d", base << value);
4296 }
4297 break;
4298 case 'R':
4299 if (given & (1 << 6))
4300 goto Q;
4301 /* FALLTHROUGH */
4302 case 'D':
4303 func (stream, "d%ld", value);
4304 break;
4305 case 'Q':
4306 Q:
4307 if (value & 1)
4308 func (stream, "<illegal reg q%ld.5>", value >> 1);
4309 else
4310 func (stream, "q%ld", value >> 1);
4311 break;
43e65147 4312
16980d0b
JB		 4313 case '`':
4314 c++;
4315 if (value == 0)
4316 func (stream, "%c", *c);
4317 break;
4318 case '\'':
4319 c++;
4320 if (value == ((1ul << width) - 1))
4321 func (stream, "%c", *c);
4322 break;
4323 case '?':
fe56b6ce 4324 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 4325 c += 1 << width;
4326 break;
4327 default:
4328 abort ();
4329 }
4330 break;
4331
4332 default:
4333 abort ();
4334 }
4335 }
4336 }
4337 else
4338 func (stream, "%c", *c);
4339 }
05413229
NC		 4340
4341 if (value_in_comment > 32 || value_in_comment < -16)
4342 func (stream, "\t; 0x%lx", value_in_comment);
4343
e2efe87d
MGD		 4344 if (is_unpredictable)
4345 func (stream, UNPREDICTABLE_INSTRUCTION);
4346
16980d0b
JB		 4347 return TRUE;
4348 }
4349 }
4350 return FALSE;
4351}
4352
90ec0d68
MGD		 4353/* Return the name of a v7A special register. */
4354
43e65147 4355static const char *
90ec0d68
MGD		 4356banked_regname (unsigned reg)
4357{
4358 switch (reg)
4359 {
4360 case 15: return "CPSR";
43e65147 4361 case 32: return "R8_usr";
90ec0d68
MGD		 4362 case 33: return "R9_usr";
4363 case 34: return "R10_usr";
4364 case 35: return "R11_usr";
4365 case 36: return "R12_usr";
4366 case 37: return "SP_usr";
4367 case 38: return "LR_usr";
43e65147 4368 case 40: return "R8_fiq";
90ec0d68
MGD		 4369 case 41: return "R9_fiq";
4370 case 42: return "R10_fiq";
4371 case 43: return "R11_fiq";
4372 case 44: return "R12_fiq";
4373 case 45: return "SP_fiq";
4374 case 46: return "LR_fiq";
4375 case 48: return "LR_irq";
4376 case 49: return "SP_irq";
4377 case 50: return "LR_svc";
4378 case 51: return "SP_svc";
4379 case 52: return "LR_abt";
4380 case 53: return "SP_abt";
4381 case 54: return "LR_und";
4382 case 55: return "SP_und";
4383 case 60: return "LR_mon";
4384 case 61: return "SP_mon";
4385 case 62: return "ELR_hyp";
4386 case 63: return "SP_hyp";
4387 case 79: return "SPSR";
4388 case 110: return "SPSR_fiq";
4389 case 112: return "SPSR_irq";
4390 case 114: return "SPSR_svc";
4391 case 116: return "SPSR_abt";
4392 case 118: return "SPSR_und";
4393 case 124: return "SPSR_mon";
4394 case 126: return "SPSR_hyp";
4395 default: return NULL;
4396 }
4397}
4398
e797f7e0
MGD		 4399/* Return the name of the DMB/DSB option. */
4400static const char *
4401data_barrier_option (unsigned option)
4402{
4403 switch (option & 0xf)
4404 {
4405 case 0xf: return "sy";
4406 case 0xe: return "st";
4407 case 0xd: return "ld";
4408 case 0xb: return "ish";
4409 case 0xa: return "ishst";
4410 case 0x9: return "ishld";
4411 case 0x7: return "un";
4412 case 0x6: return "unst";
4413 case 0x5: return "nshld";
4414 case 0x3: return "osh";
4415 case 0x2: return "oshst";
4416 case 0x1: return "oshld";
4417 default: return NULL;
4418 }
4419}
4420
4a5329c6
ZW		 4421/* Print one ARM instruction from PC on INFO->STREAM. */
4422
4423static void
4424print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 4425{
6b5d3a4d 4426 const struct opcode32 *insn;
6a51a8a8 4427 void *stream = info->stream;
6b5d3a4d 4428 fprintf_ftype func = info->fprintf_func;
b0e28b39 4429 struct arm_private_data *private_data = info->private_data;
252b5132 4430
16980d0b
JB		 4431 if (print_insn_coprocessor (pc, info, given, FALSE))
4432 return;
4433
4434 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 4435 return;
4436
252b5132
RH		 4437 for (insn = arm_opcodes; insn->assembler; insn++)
4438 {
0313a2b8
NC		 4439 if ((given & insn->mask) != insn->value)
4440 continue;
823d2571
TG		 4441
4442 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 4443 continue;
4444
4445 /* Special case: an instruction with all bits set in the condition field
4446 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4447 or by the catchall at the end of the table. */
4448 if ((given & 0xF0000000) != 0xF0000000
4449 || (insn->mask & 0xF0000000) == 0xF0000000
4450 || (insn->mask == 0 && insn->value == 0))
252b5132 4451 {
ff4a8d2b
NC		 4452 unsigned long u_reg = 16;
4453 unsigned long U_reg = 16;
ab8e2090 4454 bfd_boolean is_unpredictable = FALSE;
05413229 4455 signed long value_in_comment = 0;
6b5d3a4d 4456 const char *c;
b34976b6 4457
252b5132
RH		 4458 for (c = insn->assembler; *c; c++)
4459 {
4460 if (*c == '%')
4461 {
c1e26897
NC		 4462 bfd_boolean allow_unpredictable = FALSE;
4463
252b5132
RH		 4464 switch (*++c)
4465 {
4466 case '%':
4467 func (stream, "%%");
4468 break;
4469
4470 case 'a':
05413229 4471 value_in_comment = print_arm_address (pc, info, given);
62b3e311 4472 break;
252b5132 4473
62b3e311
PB		 4474 case 'P':
4475 /* Set P address bit and use normal address
4476 printing routine. */
c1e26897 4477 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 4478 break;
4479
c1e26897
NC		 4480 case 'S':
4481 allow_unpredictable = TRUE;
252b5132
RH		 4482 case 's':
4483 if ((given & 0x004f0000) == 0x004f0000)
4484 {
58efb6c0 4485 /* PC relative with immediate offset. */
f8b960bc 4486 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 4487
aefd8a40
NC		 4488 if (PRE_BIT_SET)
4489 {
26d97720
NS		 4490 /* Elide positive zero offset. */
4491 if (offset || NEGATIVE_BIT_SET)
4492 func (stream, "[pc, #%s%d]\t; ",
d908c8af 4493 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 4494 else
26d97720
NS		 4495 func (stream, "[pc]\t; ");
4496 if (NEGATIVE_BIT_SET)
4497 offset = -offset;
aefd8a40
NC		 4498 info->print_address_func (offset + pc + 8, info);
4499 }
4500 else
4501 {
26d97720
NS		 4502 /* Always show the offset. */
4503 func (stream, "[pc], #%s%d",
d908c8af 4504 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 4505 if (! allow_unpredictable)
4506 is_unpredictable = TRUE;
aefd8a40 4507 }
252b5132
RH		 4508 }
4509 else
4510 {
fe56b6ce
NC		 4511 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4512
b34976b6 4513 func (stream, "[%s",
252b5132 4514 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 4515
c1e26897 4516 if (PRE_BIT_SET)
252b5132 4517 {
c1e26897 4518 if (IMMEDIATE_BIT_SET)
252b5132 4519 {
26d97720
NS		 4520 /* Elide offset for non-writeback
4521 positive zero. */
4522 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4523 || offset)
4524 func (stream, ", #%s%d",
4525 NEGATIVE_BIT_SET ? "-" : "", offset);
4526
4527 if (NEGATIVE_BIT_SET)
4528 offset = -offset;
945ee430 4529
fe56b6ce 4530 value_in_comment = offset;
252b5132 4531 }
945ee430 4532 else
ff4a8d2b
NC		 4533 {
4534 /* Register Offset or Register Pre-Indexed. */
4535 func (stream, ", %s%s",
4536 NEGATIVE_BIT_SET ? "-" : "",
4537 arm_regnames[given & 0xf]);
4538
4539 /* Writing back to the register that is the source/
4540 destination of the load/store is unpredictable. */
4541 if (! allow_unpredictable
4542 && WRITEBACK_BIT_SET
4543 && ((given & 0xf) == ((given >> 12) & 0xf)))
4544 is_unpredictable = TRUE;
4545 }
252b5132 4546
b34976b6 4547 func (stream, "]%s",
c1e26897 4548 WRITEBACK_BIT_SET ? "!" : "");
252b5132 4549 }
945ee430 4550 else
252b5132 4551 {
c1e26897 4552 if (IMMEDIATE_BIT_SET)
252b5132 4553 {
945ee430 4554 /* Immediate Post-indexed. */
aefd8a40 4555 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 4556 func (stream, "], #%s%d",
4557 NEGATIVE_BIT_SET ? "-" : "", offset);
4558 if (NEGATIVE_BIT_SET)
4559 offset = -offset;
fe56b6ce 4560 value_in_comment = offset;
252b5132 4561 }
945ee430 4562 else
ff4a8d2b
NC		 4563 {
4564 /* Register Post-indexed. */
4565 func (stream, "], %s%s",
4566 NEGATIVE_BIT_SET ? "-" : "",
4567 arm_regnames[given & 0xf]);
4568
4569 /* Writing back to the register that is the source/
4570 destination of the load/store is unpredictable. */
4571 if (! allow_unpredictable
4572 && (given & 0xf) == ((given >> 12) & 0xf))
4573 is_unpredictable = TRUE;
4574 }
c1e26897 4575
07a28fab
NC		 4576 if (! allow_unpredictable)
4577 {
4578 /* Writeback is automatically implied by post- addressing.
4579 Setting the W bit is unnecessary and ARM specify it as
4580 being unpredictable. */
4581 if (WRITEBACK_BIT_SET
4582 /* Specifying the PC register as the post-indexed
4583 registers is also unpredictable. */
ab8e2090
NC		 4584 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4585 is_unpredictable = TRUE;
07a28fab 4586 }
252b5132
RH		 4587 }
4588 }
4589 break;
b34976b6 4590
252b5132 4591 case 'b':
6b5d3a4d 4592 {
f8b960bc 4593 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 4594 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 4595 }
252b5132
RH		 4596 break;
4597
4598 case 'c':
c22aaad1
PB		 4599 if (((given >> 28) & 0xf) != 0xe)
4600 func (stream, "%s",
4601 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 4602 break;
4603
4604 case 'm':
4605 {
4606 int started = 0;
4607 int reg;
4608
4609 func (stream, "{");
4610 for (reg = 0; reg < 16; reg++)
4611 if ((given & (1 << reg)) != 0)
4612 {
4613 if (started)
4614 func (stream, ", ");
4615 started = 1;
4616 func (stream, "%s", arm_regnames[reg]);
4617 }
4618 func (stream, "}");
ab8e2090
NC		 4619 if (! started)
4620 is_unpredictable = TRUE;
252b5132
RH		 4621 }
4622 break;
4623
37b37b2d 4624 case 'q':
78c66db8 4625 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 4626 break;
4627
252b5132
RH		 4628 case 'o':
4629 if ((given & 0x02000000) != 0)
4630 {
a415b1cd
JB		 4631 unsigned int rotate = (given & 0xf00) >> 7;
4632 unsigned int immed = (given & 0xff);
4633 unsigned int a, i;
4634
4635 a = (((immed << (32 - rotate))
4636 | (immed >> rotate)) & 0xffffffff);
4637 /* If there is another encoding with smaller rotate,
4638 the rotate should be specified directly. */
4639 for (i = 0; i < 32; i += 2)
4640 if ((a << i | a >> (32 - i)) <= 0xff)
4641 break;
4642
4643 if (i != rotate)
4644 func (stream, "#%d, %d", immed, rotate);
4645 else
4646 func (stream, "#%d", a);
4647 value_in_comment = a;
252b5132
RH		 4648 }
4649 else
78c66db8 4650 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 4651 break;
4652
4653 case 'p':
4654 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 4655 {
823d2571
TG		 4656 arm_feature_set arm_ext_v6 =
4657 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4658
aefd8a40
NC		 4659 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4660 mechanism for setting PSR flag bits. They are
4661 obsolete in V6 onwards. */
823d2571
TG		 4662 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4663 arm_ext_v6))
aefd8a40 4664 func (stream, "p");
4ab90a7a
AV		 4665 else
4666 is_unpredictable = TRUE;
aefd8a40 4667 }
252b5132
RH		 4668 break;
4669
4670 case 't':
4671 if ((given & 0x01200000) == 0x00200000)
4672 func (stream, "t");
4673 break;
4674
252b5132 4675 case 'A':
05413229
NC		 4676 {
4677 int offset = given & 0xff;
f02232aa 4678
05413229 4679 value_in_comment = offset * 4;
c1e26897 4680 if (NEGATIVE_BIT_SET)
05413229 4681 value_in_comment = - value_in_comment;
f02232aa 4682
05413229 4683 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 4684
c1e26897 4685 if (PRE_BIT_SET)
05413229
NC		 4686 {
4687 if (offset)
fe56b6ce 4688 func (stream, ", #%d]%s",
d908c8af 4689 (int) value_in_comment,
c1e26897 4690 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 4691 else
4692 func (stream, "]");
4693 }
4694 else
4695 {
4696 func (stream, "]");
f02232aa 4697
c1e26897 4698 if (WRITEBACK_BIT_SET)
05413229
NC		 4699 {
4700 if (offset)
d908c8af 4701 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 4702 }
4703 else
fe56b6ce 4704 {
d908c8af 4705 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 4706 value_in_comment = offset;
4707 }
05413229
NC		 4708 }
4709 }
252b5132
RH		 4710 break;
4711
077b8428
NC		 4712 case 'B':
4713 /* Print ARM V5 BLX(1) address: pc+25 bits. */
4714 {
4715 bfd_vma address;
4716 bfd_vma offset = 0;
b34976b6 4717
c1e26897 4718 if (! NEGATIVE_BIT_SET)
077b8428
NC		 4719 /* Is signed, hi bits should be ones. */
4720 offset = (-1) ^ 0x00ffffff;
4721
4722 /* Offset is (SignExtend(offset field)<<2). */
4723 offset += given & 0x00ffffff;
4724 offset <<= 2;
4725 address = offset + pc + 8;
b34976b6 4726
8f06b2d8
PB		 4727 if (given & 0x01000000)
4728 /* H bit allows addressing to 2-byte boundaries. */
4729 address += 2;
b1ee46c5 4730
8f06b2d8 4731 info->print_address_func (address, info);
b1ee46c5 4732 }
b1ee46c5
AH		 4733 break;
4734
252b5132 4735 case 'C':
90ec0d68
MGD		 4736 if ((given & 0x02000200) == 0x200)
4737 {
4738 const char * name;
4739 unsigned sysm = (given & 0x004f0000) >> 16;
4740
4741 sysm |= (given & 0x300) >> 4;
4742 name = banked_regname (sysm);
4743
4744 if (name != NULL)
4745 func (stream, "%s", name);
4746 else
d908c8af 4747 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 4748 }
4749 else
4750 {
43e65147 4751 func (stream, "%cPSR_",
90ec0d68
MGD		 4752 (given & 0x00400000) ? 'S' : 'C');
4753 if (given & 0x80000)
4754 func (stream, "f");
4755 if (given & 0x40000)
4756 func (stream, "s");
4757 if (given & 0x20000)
4758 func (stream, "x");
4759 if (given & 0x10000)
4760 func (stream, "c");
4761 }
252b5132
RH		 4762 break;
4763
62b3e311 4764 case 'U':
43e65147 4765 if ((given & 0xf0) == 0x60)
62b3e311 4766 {
52e7f43d
RE		 4767 switch (given & 0xf)
4768 {
4769 case 0xf: func (stream, "sy"); break;
4770 default:
4771 func (stream, "#%d", (int) given & 0xf);
4772 break;
4773 }
43e65147
L		 4774 }
4775 else
52e7f43d 4776 {
e797f7e0
MGD		 4777 const char * opt = data_barrier_option (given & 0xf);
4778 if (opt != NULL)
4779 func (stream, "%s", opt);
4780 else
52e7f43d 4781 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 4782 }
4783 break;
4784
b34976b6 4785 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 4786 case '5': case '6': case '7': case '8': case '9':
4787 {
16980d0b
JB		 4788 int width;
4789 unsigned long value;
252b5132 4790
16980d0b 4791 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 4792
252b5132
RH		 4793 switch (*c)
4794 {
ab8e2090
NC		 4795 case 'R':
4796 if (value == 15)
4797 is_unpredictable = TRUE;
4798 /* Fall through. */
16980d0b 4799 case 'r':
9eb6c0f1
MGD		 4800 case 'T':
4801 /* We want register + 1 when decoding T. */
4802 if (*c == 'T')
4803 ++value;
4804
ff4a8d2b
NC		 4805 if (c[1] == 'u')
4806 {
4807 /* Eat the 'u' character. */
4808 ++ c;
4809
4810 if (u_reg == value)
4811 is_unpredictable = TRUE;
4812 u_reg = value;
4813 }
4814 if (c[1] == 'U')
4815 {
4816 /* Eat the 'U' character. */
4817 ++ c;
4818
4819 if (U_reg == value)
4820 is_unpredictable = TRUE;
4821 U_reg = value;
4822 }
16980d0b
JB		 4823 func (stream, "%s", arm_regnames[value]);
4824 break;
4825 case 'd':
4826 func (stream, "%ld", value);
05413229 4827 value_in_comment = value;
16980d0b
JB		 4828 break;
4829 case 'b':
4830 func (stream, "%ld", value * 8);
05413229 4831 value_in_comment = value * 8;
16980d0b
JB		 4832 break;
4833 case 'W':
4834 func (stream, "%ld", value + 1);
05413229 4835 value_in_comment = value + 1;
16980d0b
JB		 4836 break;
4837 case 'x':
4838 func (stream, "0x%08lx", value);
4839
4840 /* Some SWI instructions have special
4841 meanings. */
4842 if ((given & 0x0fffffff) == 0x0FF00000)
4843 func (stream, "\t; IMB");
4844 else if ((given & 0x0fffffff) == 0x0FF00001)
4845 func (stream, "\t; IMBRange");
4846 break;
4847 case 'X':
4848 func (stream, "%01lx", value & 0xf);
05413229 4849 value_in_comment = value;
252b5132
RH		 4850 break;
4851 case '`':
4852 c++;
16980d0b 4853 if (value == 0)
252b5132
RH		 4854 func (stream, "%c", *c);
4855 break;
4856 case '\'':
4857 c++;
16980d0b 4858 if (value == ((1ul << width) - 1))
252b5132
RH		 4859 func (stream, "%c", *c);
4860 break;
4861 case '?':
fe56b6ce 4862 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 4863 c += 1 << width;
252b5132
RH		 4864 break;
4865 default:
4866 abort ();
4867 }
4868 break;
4869
0dd132b6
NC		 4870 case 'e':
4871 {
4872 int imm;
4873
4874 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
4875 func (stream, "%d", imm);
fe56b6ce 4876 value_in_comment = imm;
0dd132b6
NC		 4877 }
4878 break;
4879
0a003adc
ZW		 4880 case 'E':
4881 /* LSB and WIDTH fields of BFI or BFC. The machine-
4882 language instruction encodes LSB and MSB. */
4883 {
4884 long msb = (given & 0x001f0000) >> 16;
4885 long lsb = (given & 0x00000f80) >> 7;
91d6fa6a 4886 long w = msb - lsb + 1;
fe56b6ce 4887
91d6fa6a
NC		 4888 if (w > 0)
4889 func (stream, "#%lu, #%lu", lsb, w);
0a003adc
ZW		 4890 else
4891 func (stream, "(invalid: %lu:%lu)", lsb, msb);
4892 }
4893 break;
4894
90ec0d68
MGD		 4895 case 'R':
4896 /* Get the PSR/banked register name. */
4897 {
4898 const char * name;
4899 unsigned sysm = (given & 0x004f0000) >> 16;
4900
4901 sysm |= (given & 0x300) >> 4;
4902 name = banked_regname (sysm);
4903
4904 if (name != NULL)
4905 func (stream, "%s", name);
4906 else
d908c8af 4907 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 4908 }
4909 break;
4910
0a003adc
ZW		 4911 case 'V':
4912 /* 16-bit unsigned immediate from a MOVT or MOVW
4913 instruction, encoded in bits 0:11 and 15:19. */
4914 {
4915 long hi = (given & 0x000f0000) >> 4;
4916 long lo = (given & 0x00000fff);
4917 long imm16 = hi | lo;
fe56b6ce
NC		 4918
4919 func (stream, "#%lu", imm16);
4920 value_in_comment = imm16;
0a003adc
ZW		 4921 }
4922 break;
4923
252b5132
RH		 4924 default:
4925 abort ();
4926 }
4927 }
4928 }
4929 else
4930 func (stream, "%c", *c);
4931 }
05413229
NC		 4932
4933 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 4934 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 4935
4936 if (is_unpredictable)
4937 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 4938
4a5329c6 4939 return;
252b5132
RH		 4940 }
4941 }
4942 abort ();
4943}
4944
4a5329c6 4945/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 4946
4a5329c6
ZW		 4947static void
4948print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 4949{
6b5d3a4d 4950 const struct opcode16 *insn;
6a51a8a8
AM		 4951 void *stream = info->stream;
4952 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 4953
4954 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 4955 if ((given & insn->mask) == insn->value)
4956 {
05413229 4957 signed long value_in_comment = 0;
6b5d3a4d 4958 const char *c = insn->assembler;
05413229 4959
c19d1205
ZW		 4960 for (; *c; c++)
4961 {
4962 int domaskpc = 0;
4963 int domasklr = 0;
4964
4965 if (*c != '%')
4966 {
4967 func (stream, "%c", *c);
4968 continue;
4969 }
252b5132 4970
c19d1205
ZW		 4971 switch (*++c)
4972 {
4973 case '%':
4974 func (stream, "%%");
4975 break;
b34976b6 4976
c22aaad1
PB		 4977 case 'c':
4978 if (ifthen_state)
4979 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4980 break;
4981
4982 case 'C':
4983 if (ifthen_state)
4984 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4985 else
4986 func (stream, "s");
4987 break;
4988
4989 case 'I':
4990 {
4991 unsigned int tmp;
4992
4993 ifthen_next_state = given & 0xff;
4994 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
4995 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
4996 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
4997 }
4998 break;
4999
5000 case 'x':
5001 if (ifthen_next_state)
5002 func (stream, "\t; unpredictable branch in IT block\n");
5003 break;
5004
5005 case 'X':
5006 if (ifthen_state)
5007 func (stream, "\t; unpredictable <IT:%s>",
5008 arm_conditional[IFTHEN_COND]);
5009 break;
5010
c19d1205
ZW		 5011 case 'S':
5012 {
5013 long reg;
5014
5015 reg = (given >> 3) & 0x7;
5016 if (given & (1 << 6))
5017 reg += 8;
4f3c3dbb 5018
c19d1205
ZW		 5019 func (stream, "%s", arm_regnames[reg]);
5020 }
5021 break;
baf0cc5e 5022
c19d1205 5023 case 'D':
4f3c3dbb 5024 {
c19d1205
ZW		 5025 long reg;
5026
5027 reg = given & 0x7;
5028 if (given & (1 << 7))
5029 reg += 8;
5030
5031 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 5032 }
c19d1205
ZW		 5033 break;
5034
5035 case 'N':
5036 if (given & (1 << 8))
5037 domasklr = 1;
5038 /* Fall through. */
5039 case 'O':
5040 if (*c == 'O' && (given & (1 << 8)))
5041 domaskpc = 1;
5042 /* Fall through. */
5043 case 'M':
5044 {
5045 int started = 0;
5046 int reg;
5047
5048 func (stream, "{");
5049
5050 /* It would be nice if we could spot
5051 ranges, and generate the rS-rE format: */
5052 for (reg = 0; (reg < 8); reg++)
5053 if ((given & (1 << reg)) != 0)
5054 {
5055 if (started)
5056 func (stream, ", ");
5057 started = 1;
5058 func (stream, "%s", arm_regnames[reg]);
5059 }
5060
5061 if (domasklr)
5062 {
5063 if (started)
5064 func (stream, ", ");
5065 started = 1;
d908c8af 5066 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 5067 }
5068
5069 if (domaskpc)
5070 {
5071 if (started)
5072 func (stream, ", ");
d908c8af 5073 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 5074 }
5075
5076 func (stream, "}");
5077 }
5078 break;
5079
4547cb56
NC		 5080 case 'W':
5081 /* Print writeback indicator for a LDMIA. We are doing a
5082 writeback if the base register is not in the register
5083 mask. */
5084 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5085 func (stream, "!");
5086 break;
5087
c19d1205
ZW		 5088 case 'b':
5089 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5090 {
5091 bfd_vma address = (pc + 4
5092 + ((given & 0x00f8) >> 2)
5093 + ((given & 0x0200) >> 3));
5094 info->print_address_func (address, info);
5095 }
5096 break;
5097
5098 case 's':
5099 /* Right shift immediate -- bits 6..10; 1-31 print
5100 as themselves, 0 prints as 32. */
5101 {
5102 long imm = (given & 0x07c0) >> 6;
5103 if (imm == 0)
5104 imm = 32;
0fd3a477 5105 func (stream, "#%ld", imm);
c19d1205
ZW		 5106 }
5107 break;
5108
5109 case '0': case '1': case '2': case '3': case '4':
5110 case '5': case '6': case '7': case '8': case '9':
5111 {
5112 int bitstart = *c++ - '0';
5113 int bitend = 0;
5114
5115 while (*c >= '0' && *c <= '9')
5116 bitstart = (bitstart * 10) + *c++ - '0';
5117
5118 switch (*c)
5119 {
5120 case '-':
5121 {
f8b960bc 5122 bfd_vma reg;
c19d1205
ZW		 5123
5124 c++;
5125 while (*c >= '0' && *c <= '9')
5126 bitend = (bitend * 10) + *c++ - '0';
5127 if (!bitend)
5128 abort ();
5129 reg = given >> bitstart;
5130 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 5131
c19d1205
ZW		 5132 switch (*c)
5133 {
5134 case 'r':
5135 func (stream, "%s", arm_regnames[reg]);
5136 break;
5137
5138 case 'd':
d908c8af 5139 func (stream, "%ld", (long) reg);
05413229 5140 value_in_comment = reg;
c19d1205
ZW		 5141 break;
5142
5143 case 'H':
d908c8af 5144 func (stream, "%ld", (long) (reg << 1));
05413229 5145 value_in_comment = reg << 1;
c19d1205
ZW		 5146 break;
5147
5148 case 'W':
d908c8af 5149 func (stream, "%ld", (long) (reg << 2));
05413229 5150 value_in_comment = reg << 2;
c19d1205
ZW		 5151 break;
5152
5153 case 'a':
5154 /* PC-relative address -- the bottom two
5155 bits of the address are dropped
5156 before the calculation. */
5157 info->print_address_func
5158 (((pc + 4) & ~3) + (reg << 2), info);
05413229 5159 value_in_comment = 0;
c19d1205
ZW		 5160 break;
5161
5162 case 'x':
d908c8af 5163 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 5164 break;
5165
c19d1205
ZW		 5166 case 'B':
5167 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 5168 info->print_address_func (reg * 2 + pc + 4, info);
05413229 5169 value_in_comment = 0;
c19d1205
ZW		 5170 break;
5171
5172 case 'c':
c22aaad1 5173 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 5174 break;
5175
5176 default:
5177 abort ();
5178 }
5179 }
5180 break;
5181
5182 case '\'':
5183 c++;
5184 if ((given & (1 << bitstart)) != 0)
5185 func (stream, "%c", *c);
5186 break;
5187
5188 case '?':
5189 ++c;
5190 if ((given & (1 << bitstart)) != 0)
5191 func (stream, "%c", *c++);
5192 else
5193 func (stream, "%c", *++c);
5194 break;
5195
5196 default:
5197 abort ();
5198 }
5199 }
5200 break;
5201
5202 default:
5203 abort ();
5204 }
5205 }
05413229
NC		 5206
5207 if (value_in_comment > 32 || value_in_comment < -16)
5208 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 5209 return;
c19d1205
ZW		 5210 }
5211
5212 /* No match. */
5213 abort ();
5214}
5215
62b3e311 5216/* Return the name of an V7M special register. */
fe56b6ce 5217
62b3e311
PB		 5218static const char *
5219psr_name (int regno)
5220{
5221 switch (regno)
5222 {
5223 case 0: return "APSR";
5224 case 1: return "IAPSR";
5225 case 2: return "EAPSR";
5226 case 3: return "PSR";
5227 case 5: return "IPSR";
5228 case 6: return "EPSR";
5229 case 7: return "IEPSR";
5230 case 8: return "MSP";
5231 case 9: return "PSP";
5232 case 16: return "PRIMASK";
5233 case 17: return "BASEPRI";
00bbc0bd 5234 case 18: return "BASEPRI_MAX";
62b3e311
PB		 5235 case 19: return "FAULTMASK";
5236 case 20: return "CONTROL";
5237 default: return "<unknown>";
5238 }
5239}
5240
4a5329c6
ZW		 5241/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5242
5243static void
5244print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 5245{
6b5d3a4d 5246 const struct opcode32 *insn;
c19d1205
ZW		 5247 void *stream = info->stream;
5248 fprintf_ftype func = info->fprintf_func;
5249
16980d0b
JB		 5250 if (print_insn_coprocessor (pc, info, given, TRUE))
5251 return;
5252
5253 if (print_insn_neon (info, given, TRUE))
8f06b2d8
PB		 5254 return;
5255
c19d1205
ZW		 5256 for (insn = thumb32_opcodes; insn->assembler; insn++)
5257 if ((given & insn->mask) == insn->value)
5258 {
ff4a8d2b 5259 bfd_boolean is_unpredictable = FALSE;
05413229 5260 signed long value_in_comment = 0;
6b5d3a4d 5261 const char *c = insn->assembler;
05413229 5262
c19d1205
ZW		 5263 for (; *c; c++)
5264 {
5265 if (*c != '%')
5266 {
5267 func (stream, "%c", *c);
5268 continue;
5269 }
5270
5271 switch (*++c)
5272 {
5273 case '%':
5274 func (stream, "%%");
5275 break;
5276
c22aaad1
PB		 5277 case 'c':
5278 if (ifthen_state)
5279 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5280 break;
5281
5282 case 'x':
5283 if (ifthen_next_state)
5284 func (stream, "\t; unpredictable branch in IT block\n");
5285 break;
5286
5287 case 'X':
5288 if (ifthen_state)
5289 func (stream, "\t; unpredictable <IT:%s>",
5290 arm_conditional[IFTHEN_COND]);
5291 break;
5292
c19d1205
ZW		 5293 case 'I':
5294 {
5295 unsigned int imm12 = 0;
fe56b6ce 5296
c19d1205
ZW		 5297 imm12 |= (given & 0x000000ffu);
5298 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 5299 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 5300 func (stream, "#%u", imm12);
5301 value_in_comment = imm12;
c19d1205
ZW		 5302 }
5303 break;
5304
5305 case 'M':
5306 {
5307 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 5308
c19d1205
ZW		 5309 bits |= (given & 0x000000ffu);
5310 bits |= (given & 0x00007000u) >> 4;
5311 bits |= (given & 0x04000000u) >> 15;
5312 imm8 = (bits & 0x0ff);
5313 mod = (bits & 0xf00) >> 8;
5314 switch (mod)
5315 {
5316 case 0: imm = imm8; break;
c1e26897
NC		 5317 case 1: imm = ((imm8 << 16) | imm8); break;
5318 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5319 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 5320 default:
5321 mod = (bits & 0xf80) >> 7;
5322 imm8 = (bits & 0x07f) | 0x80;
5323 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5324 }
fe56b6ce
NC		 5325 func (stream, "#%u", imm);
5326 value_in_comment = imm;
c19d1205
ZW		 5327 }
5328 break;
43e65147 5329
c19d1205
ZW		 5330 case 'J':
5331 {
5332 unsigned int imm = 0;
fe56b6ce 5333
c19d1205
ZW		 5334 imm |= (given & 0x000000ffu);
5335 imm |= (given & 0x00007000u) >> 4;
5336 imm |= (given & 0x04000000u) >> 15;
5337 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 5338 func (stream, "#%u", imm);
5339 value_in_comment = imm;
c19d1205
ZW		 5340 }
5341 break;
5342
5343 case 'K':
5344 {
5345 unsigned int imm = 0;
fe56b6ce 5346
c19d1205
ZW		 5347 imm |= (given & 0x000f0000u) >> 16;
5348 imm |= (given & 0x00000ff0u) >> 0;
5349 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 5350 func (stream, "#%u", imm);
5351 value_in_comment = imm;
c19d1205
ZW		 5352 }
5353 break;
5354
74db7efb
NC		 5355 case 'H':
5356 {
5357 unsigned int imm = 0;
5358
5359 imm |= (given & 0x000f0000u) >> 4;
5360 imm |= (given & 0x00000fffu) >> 0;
5361 func (stream, "#%u", imm);
5362 value_in_comment = imm;
5363 }
5364 break;
5365
90ec0d68
MGD		 5366 case 'V':
5367 {
5368 unsigned int imm = 0;
5369
5370 imm |= (given & 0x00000fffu);
5371 imm |= (given & 0x000f0000u) >> 4;
5372 func (stream, "#%u", imm);
5373 value_in_comment = imm;
5374 }
5375 break;
5376
c19d1205
ZW		 5377 case 'S':
5378 {
5379 unsigned int reg = (given & 0x0000000fu);
5380 unsigned int stp = (given & 0x00000030u) >> 4;
5381 unsigned int imm = 0;
5382 imm |= (given & 0x000000c0u) >> 6;
5383 imm |= (given & 0x00007000u) >> 10;
5384
5385 func (stream, "%s", arm_regnames[reg]);
5386 switch (stp)
5387 {
5388 case 0:
5389 if (imm > 0)
5390 func (stream, ", lsl #%u", imm);
5391 break;
5392
5393 case 1:
5394 if (imm == 0)
5395 imm = 32;
5396 func (stream, ", lsr #%u", imm);
5397 break;
5398
5399 case 2:
5400 if (imm == 0)
5401 imm = 32;
5402 func (stream, ", asr #%u", imm);
5403 break;
5404
5405 case 3:
5406 if (imm == 0)
5407 func (stream, ", rrx");
5408 else
5409 func (stream, ", ror #%u", imm);
5410 }
5411 }
5412 break;
5413
5414 case 'a':
5415 {
5416 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 5417 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 5418 unsigned int op = (given & 0x00000f00) >> 8;
5419 unsigned int i12 = (given & 0x00000fff);
5420 unsigned int i8 = (given & 0x000000ff);
5421 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 5422 bfd_vma offset = 0;
c19d1205
ZW		 5423
5424 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 5425 if (U) /* 12-bit positive immediate offset. */
5426 {
5427 offset = i12;
5428 if (Rn != 15)
5429 value_in_comment = offset;
5430 }
5431 else if (Rn == 15) /* 12-bit negative immediate offset. */
5432 offset = - (int) i12;
5433 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 5434 {
5435 unsigned int Rm = (i8 & 0x0f);
5436 unsigned int sh = (i8 & 0x30) >> 4;
05413229 5437
c19d1205
ZW		 5438 func (stream, ", %s", arm_regnames[Rm]);
5439 if (sh)
5440 func (stream, ", lsl #%u", sh);
5441 func (stream, "]");
5442 break;
5443 }
5444 else switch (op)
5445 {
05413229 5446 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 5447 offset = i8;
5448 break;
5449
05413229 5450 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 5451 offset = -i8;
5452 break;
5453
05413229 5454 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 5455 offset = i8;
5456 writeback = TRUE;
5457 break;
5458
05413229 5459 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 5460 offset = -i8;
5461 writeback = TRUE;
5462 break;
5463
05413229 5464 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 5465 offset = i8;
5466 postind = TRUE;
5467 break;
5468
05413229 5469 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 5470 offset = -i8;
5471 postind = TRUE;
5472 break;
5473
5474 default:
5475 func (stream, ", <undefined>]");
5476 goto skip;
5477 }
5478
5479 if (postind)
d908c8af 5480 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 5481 else
5482 {
5483 if (offset)
d908c8af 5484 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 5485 func (stream, writeback ? "]!" : "]");
5486 }
5487
5488 if (Rn == 15)
5489 {
5490 func (stream, "\t; ");
5491 info->print_address_func (((pc + 4) & ~3) + offset, info);
5492 }
5493 }
5494 skip:
5495 break;
5496
5497 case 'A':
5498 {
c1e26897
NC		 5499 unsigned int U = ! NEGATIVE_BIT_SET;
5500 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 5501 unsigned int Rn = (given & 0x000f0000) >> 16;
5502 unsigned int off = (given & 0x000000ff);
5503
5504 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 5505
5506 if (PRE_BIT_SET)
c19d1205
ZW		 5507 {
5508 if (off || !U)
05413229
NC		 5509 {
5510 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
5511 value_in_comment = off * 4 * U ? 1 : -1;
5512 }
c19d1205
ZW		 5513 func (stream, "]");
5514 if (W)
5515 func (stream, "!");
5516 }
5517 else
5518 {
5519 func (stream, "], ");
5520 if (W)
05413229
NC		 5521 {
5522 func (stream, "#%c%u", U ? '+' : '-', off * 4);
5523 value_in_comment = off * 4 * U ? 1 : -1;
5524 }
c19d1205 5525 else
fe56b6ce
NC		 5526 {
5527 func (stream, "{%u}", off);
5528 value_in_comment = off;
5529 }
c19d1205
ZW		 5530 }
5531 }
5532 break;
5533
5534 case 'w':
5535 {
5536 unsigned int Sbit = (given & 0x01000000) >> 24;
5537 unsigned int type = (given & 0x00600000) >> 21;
05413229 5538
c19d1205
ZW		 5539 switch (type)
5540 {
5541 case 0: func (stream, Sbit ? "sb" : "b"); break;
5542 case 1: func (stream, Sbit ? "sh" : "h"); break;
5543 case 2:
5544 if (Sbit)
5545 func (stream, "??");
5546 break;
5547 case 3:
5548 func (stream, "??");
5549 break;
5550 }
5551 }
5552 break;
5553
5554 case 'm':
5555 {
5556 int started = 0;
5557 int reg;
5558
5559 func (stream, "{");
5560 for (reg = 0; reg < 16; reg++)
5561 if ((given & (1 << reg)) != 0)
5562 {
5563 if (started)
5564 func (stream, ", ");
5565 started = 1;
5566 func (stream, "%s", arm_regnames[reg]);
5567 }
5568 func (stream, "}");
5569 }
5570 break;
5571
5572 case 'E':
5573 {
5574 unsigned int msb = (given & 0x0000001f);
5575 unsigned int lsb = 0;
fe56b6ce 5576
c19d1205
ZW		 5577 lsb |= (given & 0x000000c0u) >> 6;
5578 lsb |= (given & 0x00007000u) >> 10;
5579 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5580 }
5581 break;
5582
5583 case 'F':
5584 {
5585 unsigned int width = (given & 0x0000001f) + 1;
5586 unsigned int lsb = 0;
fe56b6ce 5587
c19d1205
ZW		 5588 lsb |= (given & 0x000000c0u) >> 6;
5589 lsb |= (given & 0x00007000u) >> 10;
5590 func (stream, "#%u, #%u", lsb, width);
5591 }
5592 break;
5593
5594 case 'b':
5595 {
5596 unsigned int S = (given & 0x04000000u) >> 26;
5597 unsigned int J1 = (given & 0x00002000u) >> 13;
5598 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 5599 bfd_vma offset = 0;
c19d1205
ZW		 5600
5601 offset |= !S << 20;
5602 offset |= J2 << 19;
5603 offset |= J1 << 18;
5604 offset |= (given & 0x003f0000) >> 4;
5605 offset |= (given & 0x000007ff) << 1;
5606 offset -= (1 << 20);
5607
5608 info->print_address_func (pc + 4 + offset, info);
5609 }
5610 break;
5611
5612 case 'B':
5613 {
5614 unsigned int S = (given & 0x04000000u) >> 26;
5615 unsigned int I1 = (given & 0x00002000u) >> 13;
5616 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 5617 bfd_vma offset = 0;
c19d1205
ZW		 5618
5619 offset |= !S << 24;
5620 offset |= !(I1 ^ S) << 23;
5621 offset |= !(I2 ^ S) << 22;
5622 offset |= (given & 0x03ff0000u) >> 4;
5623 offset |= (given & 0x000007ffu) << 1;
5624 offset -= (1 << 24);
36b0c57d 5625 offset += pc + 4;
c19d1205 5626
36b0c57d
PB		 5627 /* BLX target addresses are always word aligned. */
5628 if ((given & 0x00001000u) == 0)
5629 offset &= ~2u;
5630
5631 info->print_address_func (offset, info);
c19d1205
ZW		 5632 }
5633 break;
5634
5635 case 's':
5636 {
5637 unsigned int shift = 0;
fe56b6ce 5638
c19d1205
ZW		 5639 shift |= (given & 0x000000c0u) >> 6;
5640 shift |= (given & 0x00007000u) >> 10;
c1e26897 5641 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 5642 func (stream, ", asr #%u", shift);
5643 else if (shift)
5644 func (stream, ", lsl #%u", shift);
5645 /* else print nothing - lsl #0 */
5646 }
5647 break;
5648
5649 case 'R':
5650 {
5651 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 5652
c19d1205
ZW		 5653 if (rot)
5654 func (stream, ", ror #%u", rot * 8);
5655 }
5656 break;
5657
62b3e311 5658 case 'U':
43e65147 5659 if ((given & 0xf0) == 0x60)
62b3e311 5660 {
52e7f43d
RE		 5661 switch (given & 0xf)
5662 {
5663 case 0xf: func (stream, "sy"); break;
5664 default:
5665 func (stream, "#%d", (int) given & 0xf);
5666 break;
5667 }
62b3e311 5668 }
43e65147 5669 else
52e7f43d 5670 {
e797f7e0
MGD		 5671 const char * opt = data_barrier_option (given & 0xf);
5672 if (opt != NULL)
5673 func (stream, "%s", opt);
5674 else
5675 func (stream, "#%d", (int) given & 0xf);
52e7f43d 5676 }
62b3e311
PB		 5677 break;
5678
5679 case 'C':
5680 if ((given & 0xff) == 0)
5681 {
5682 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5683 if (given & 0x800)
5684 func (stream, "f");
5685 if (given & 0x400)
5686 func (stream, "s");
5687 if (given & 0x200)
5688 func (stream, "x");
5689 if (given & 0x100)
5690 func (stream, "c");
5691 }
90ec0d68
MGD		 5692 else if ((given & 0x20) == 0x20)
5693 {
5694 char const* name;
5695 unsigned sysm = (given & 0xf00) >> 8;
5696
5697 sysm |= (given & 0x30);
5698 sysm |= (given & 0x00100000) >> 14;
5699 name = banked_regname (sysm);
43e65147 5700
90ec0d68
MGD		 5701 if (name != NULL)
5702 func (stream, "%s", name);
5703 else
d908c8af 5704 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 5705 }
62b3e311
PB		 5706 else
5707 {
d908c8af 5708 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5709 }
5710 break;
5711
5712 case 'D':
90ec0d68
MGD		 5713 if (((given & 0xff) == 0)
5714 || ((given & 0x20) == 0x20))
5715 {
5716 char const* name;
5717 unsigned sm = (given & 0xf0000) >> 16;
5718
5719 sm |= (given & 0x30);
5720 sm |= (given & 0x00100000) >> 14;
5721 name = banked_regname (sm);
5722
5723 if (name != NULL)
5724 func (stream, "%s", name);
5725 else
d908c8af 5726 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 5727 }
62b3e311 5728 else
d908c8af 5729 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5730 break;
5731
c19d1205
ZW		 5732 case '0': case '1': case '2': case '3': case '4':
5733 case '5': case '6': case '7': case '8': case '9':
5734 {
16980d0b
JB		 5735 int width;
5736 unsigned long val;
c19d1205 5737
16980d0b 5738 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 5739
c19d1205
ZW		 5740 switch (*c)
5741 {
05413229
NC		 5742 case 'd':
5743 func (stream, "%lu", val);
5744 value_in_comment = val;
5745 break;
ff4a8d2b 5746
f0fba320
RL		 5747 case 'D':
5748 func (stream, "%lu", val + 1);
5749 value_in_comment = val + 1;
5750 break;
5751
05413229
NC		 5752 case 'W':
5753 func (stream, "%lu", val * 4);
5754 value_in_comment = val * 4;
5755 break;
ff4a8d2b 5756
dd5181d5
KT		 5757 case 'S':
5758 if (val == 13)
5759 is_unpredictable = TRUE;
5760 /* Fall through. */
ff4a8d2b
NC		 5761 case 'R':
5762 if (val == 15)
5763 is_unpredictable = TRUE;
5764 /* Fall through. */
5765 case 'r':
5766 func (stream, "%s", arm_regnames[val]);
5767 break;
c19d1205
ZW		 5768
5769 case 'c':
c22aaad1 5770 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 5771 break;
5772
5773 case '\'':
c19d1205 5774 c++;
16980d0b
JB		 5775 if (val == ((1ul << width) - 1))
5776 func (stream, "%c", *c);
c19d1205 5777 break;
43e65147 5778
c19d1205 5779 case '`':
c19d1205 5780 c++;
16980d0b
JB		 5781 if (val == 0)
5782 func (stream, "%c", *c);
c19d1205
ZW		 5783 break;
5784
5785 case '?':
fe56b6ce 5786 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 5787 c += 1 << width;
c19d1205 5788 break;
43e65147 5789
0bb027fd
RR		 5790 case 'x':
5791 func (stream, "0x%lx", val & 0xffffffffUL);
5792 break;
c19d1205
ZW		 5793
5794 default:
5795 abort ();
5796 }
5797 }
5798 break;
5799
32a94698
NC		 5800 case 'L':
5801 /* PR binutils/12534
5802 If we have a PC relative offset in an LDRD or STRD
5803 instructions then display the decoded address. */
5804 if (((given >> 16) & 0xf) == 0xf)
5805 {
5806 bfd_vma offset = (given & 0xff) * 4;
5807
5808 if ((given & (1 << 23)) == 0)
5809 offset = - offset;
5810 func (stream, "\t; ");
5811 info->print_address_func ((pc & ~3) + 4 + offset, info);
5812 }
5813 break;
5814
c19d1205
ZW		 5815 default:
5816 abort ();
5817 }
5818 }
05413229
NC		 5819
5820 if (value_in_comment > 32 || value_in_comment < -16)
5821 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 5822
5823 if (is_unpredictable)
5824 func (stream, UNPREDICTABLE_INSTRUCTION);
5825
4a5329c6 5826 return;
c19d1205 5827 }
252b5132 5828
58efb6c0 5829 /* No match. */
252b5132
RH		 5830 abort ();
5831}
5832
e821645d
DJ		 5833/* Print data bytes on INFO->STREAM. */
5834
5835static void
fe56b6ce
NC		 5836print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
5837 struct disassemble_info *info,
e821645d
DJ		 5838 long given)
5839{
5840 switch (info->bytes_per_chunk)
5841 {
5842 case 1:
5843 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
5844 break;
5845 case 2:
5846 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
5847 break;
5848 case 4:
5849 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
5850 break;
5851 default:
5852 abort ();
5853 }
5854}
5855
22a398e1 5856/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 5857 being displayed in symbol relative addresses.
5858
5859 Also disallow private symbol, with __tagsym$$ prefix,
5860 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 5861
5862bfd_boolean
5863arm_symbol_is_valid (asymbol * sym,
5864 struct disassemble_info * info ATTRIBUTE_UNUSED)
5865{
5866 const char * name;
43e65147 5867
22a398e1
NC		 5868 if (sym == NULL)
5869 return FALSE;
5870
5871 name = bfd_asymbol_name (sym);
5872
d8282f0e 5873 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 5874}
5875
58efb6c0 5876/* Parse an individual disassembler option. */
baf0cc5e 5877
a3d9c82d 5878void
4a5329c6 5879parse_arm_disassembler_option (char *option)
dd92f639 5880{
01c7f630 5881 if (option == NULL)
dd92f639 5882 return;
b34976b6 5883
0112cd26 5884 if (CONST_STRNEQ (option, "reg-names-"))
dd92f639 5885 {
58efb6c0 5886 int i;
b34976b6 5887
01c7f630 5888 option += 10;
58efb6c0
NC		 5889
5890 for (i = NUM_ARM_REGNAMES; i--;)
31e0f3cd 5891 if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
58efb6c0
NC		 5892 {
5893 regname_selected = i;
5894 break;
5895 }
b34976b6 5896
58efb6c0 5897 if (i < 0)
31e0f3cd 5898 /* XXX - should break 'option' at following delimiter. */
58efb6c0 5899 fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
dd92f639 5900 }
0112cd26 5901 else if (CONST_STRNEQ (option, "force-thumb"))
01c7f630 5902 force_thumb = 1;
0112cd26 5903 else if (CONST_STRNEQ (option, "no-force-thumb"))
01c7f630 5904 force_thumb = 0;
dd92f639 5905 else
31e0f3cd 5906 /* XXX - should break 'option' at following delimiter. */
58efb6c0 5907 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
b34976b6 5908
dd92f639
NC		 5909 return;
5910}
5911
31e0f3cd
NC		 5912/* Parse the string of disassembler options, spliting it at whitespaces
5913 or commas. (Whitespace separators supported for backwards compatibility). */
baf0cc5e 5914
01c7f630 5915static void
4a5329c6 5916parse_disassembler_options (char *options)
01c7f630 5917{
01c7f630
NC		 5918 if (options == NULL)
5919 return;
5920
31e0f3cd 5921 while (*options)
01c7f630 5922 {
31e0f3cd
NC		 5923 parse_arm_disassembler_option (options);
5924
5925 /* Skip forward to next seperator. */
5926 while ((*options) && (! ISSPACE (*options)) && (*options != ','))
5927 ++ options;
5928 /* Skip forward past seperators. */
5929 while (ISSPACE (*options) || (*options == ','))
43e65147 5930 ++ options;
01c7f630 5931 }
01c7f630
NC		 5932}
5933
c22aaad1
PB		 5934/* Search back through the insn stream to determine if this instruction is
5935 conditionally executed. */
fe56b6ce 5936
c22aaad1 5937static void
fe56b6ce
NC		 5938find_ifthen_state (bfd_vma pc,
5939 struct disassemble_info *info,
c22aaad1
PB		 5940 bfd_boolean little)
5941{
5942 unsigned char b[2];
5943 unsigned int insn;
5944 int status;
5945 /* COUNT is twice the number of instructions seen. It will be odd if we
5946 just crossed an instruction boundary. */
5947 int count;
5948 int it_count;
5949 unsigned int seen_it;
5950 bfd_vma addr;
5951
5952 ifthen_address = pc;
5953 ifthen_state = 0;
5954
5955 addr = pc;
5956 count = 1;
5957 it_count = 0;
5958 seen_it = 0;
5959 /* Scan backwards looking for IT instructions, keeping track of where
5960 instruction boundaries are. We don't know if something is actually an
5961 IT instruction until we find a definite instruction boundary. */
5962 for (;;)
5963 {
fe56b6ce 5964 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 5965 {
5966 /* A symbol must be on an instruction boundary, and will not
5967 be within an IT block. */
5968 if (seen_it && (count & 1))
5969 break;
5970
5971 return;
5972 }
5973 addr -= 2;
fe56b6ce 5974 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 5975 if (status)
5976 return;
5977
5978 if (little)
5979 insn = (b[0]) | (b[1] << 8);
5980 else
5981 insn = (b[1]) | (b[0] << 8);
5982 if (seen_it)
5983 {
5984 if ((insn & 0xf800) < 0xe800)
5985 {
5986 /* Addr + 2 is an instruction boundary. See if this matches
5987 the expected boundary based on the position of the last
5988 IT candidate. */
5989 if (count & 1)
5990 break;
5991 seen_it = 0;
5992 }
5993 }
5994 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
5995 {
5996 /* This could be an IT instruction. */
5997 seen_it = insn;
5998 it_count = count >> 1;
5999 }
6000 if ((insn & 0xf800) >= 0xe800)
6001 count++;
6002 else
6003 count = (count + 2) | 1;
6004 /* IT blocks contain at most 4 instructions. */
6005 if (count >= 8 && !seen_it)
6006 return;
6007 }
6008 /* We found an IT instruction. */
6009 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6010 if ((ifthen_state & 0xf) == 0)
6011 ifthen_state = 0;
6012}
6013
b0e28b39
DJ		 6014/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6015 mapping symbol. */
6016
6017static int
6018is_mapping_symbol (struct disassemble_info *info, int n,
6019 enum map_type *map_type)
6020{
6021 const char *name;
6022
6023 name = bfd_asymbol_name (info->symtab[n]);
6024 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6025 && (name[2] == 0 || name[2] == '.'))
6026 {
6027 *map_type = ((name[1] == 'a') ? MAP_ARM
6028 : (name[1] == 't') ? MAP_THUMB
6029 : MAP_DATA);
6030 return TRUE;
6031 }
6032
6033 return FALSE;
6034}
6035
6036/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6037 Returns nonzero if *MAP_TYPE was set. */
6038
6039static int
6040get_map_sym_type (struct disassemble_info *info,
6041 int n,
6042 enum map_type *map_type)
6043{
6044 /* If the symbol is in a different section, ignore it. */
6045 if (info->section != NULL && info->section != info->symtab[n]->section)
6046 return FALSE;
6047
6048 return is_mapping_symbol (info, n, map_type);
6049}
6050
6051/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 6052 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 6053
6054static int
fe56b6ce
NC		 6055get_sym_code_type (struct disassemble_info *info,
6056 int n,
e821645d 6057 enum map_type *map_type)
2087ad84
PB		 6058{
6059 elf_symbol_type *es;
6060 unsigned int type;
b0e28b39
DJ		 6061
6062 /* If the symbol is in a different section, ignore it. */
6063 if (info->section != NULL && info->section != info->symtab[n]->section)
6064 return FALSE;
2087ad84 6065
e821645d 6066 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 6067 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6068
6069 /* If the symbol has function type then use that. */
34e77a92 6070 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 6071 {
35fc36a8
RS		 6072 if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB)
6073 *map_type = MAP_THUMB;
6074 else
6075 *map_type = MAP_ARM;
2087ad84
PB		 6076 return TRUE;
6077 }
6078
2087ad84
PB		 6079 return FALSE;
6080}
6081
0313a2b8
NC		 6082/* Given a bfd_mach_arm_XXX value, this function fills in the fields
6083 of the supplied arm_feature_set structure with bitmasks indicating
6084 the support base architectures and coprocessor extensions.
6085
6086 FIXME: This could more efficiently implemented as a constant array,
6087 although it would also be less robust. */
6088
6089static void
6090select_arm_features (unsigned long mach,
6091 arm_feature_set * features)
6092{
1af1dd51
MW		 6093#undef ARM_SET_FEATURES
6094#define ARM_SET_FEATURES(FSET) \
6095 { \
6096 const arm_feature_set fset = FSET; \
6097 arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
6098 ARM_MERGE_FEATURE_SETS (*features, tmp, fset); \
6099 }
823d2571 6100
0313a2b8
NC		 6101 switch (mach)
6102 {
1af1dd51
MW		 6103 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
6104 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6105 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
6106 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6107 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
6108 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6109 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
6110 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6111 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6112 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6113 case bfd_mach_arm_ep9312:
6114 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6115 ARM_CEXT_MAVERICK | FPU_MAVERICK));
6116 break;
6117 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6118 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
0313a2b8
NC		 6119 /* If the machine type is unknown allow all
6120 architecture types and all extensions. */
1af1dd51 6121 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 6122 default:
6123 abort ();
6124 }
1af1dd51
MW		 6125
6126#undef ARM_SET_FEATURES
0313a2b8
NC		 6127}
6128
6129
58efb6c0
NC		 6130/* NOTE: There are no checks in these routines that
6131 the relevant number of data bytes exist. */
baf0cc5e 6132
58efb6c0 6133static int
4a5329c6 6134print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 6135{
c19d1205
ZW		 6136 unsigned char b[4];
6137 long given;
6138 int status;
e821645d 6139 int is_thumb = FALSE;
b0e28b39 6140 int is_data = FALSE;
bd2e2557 6141 int little_code;
e821645d 6142 unsigned int size = 4;
4a5329c6 6143 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 6144 bfd_boolean found = FALSE;
b0e28b39 6145 struct arm_private_data *private_data;
58efb6c0 6146
dd92f639
NC		 6147 if (info->disassembler_options)
6148 {
6149 parse_disassembler_options (info->disassembler_options);
b34976b6 6150
58efb6c0 6151 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 6152 info->disassembler_options = NULL;
6153 }
b34976b6 6154
0313a2b8
NC		 6155 /* PR 10288: Control which instructions will be disassembled. */
6156 if (info->private_data == NULL)
6157 {
b0e28b39 6158 static struct arm_private_data private;
0313a2b8
NC		 6159
6160 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6161 /* If the user did not use the -m command line switch then default to
6162 disassembling all types of ARM instruction.
43e65147 6163
0313a2b8
NC		 6164 The info->mach value has to be ignored as this will be based on
6165 the default archictecture for the target and/or hints in the notes
6166 section, but it will never be greater than the current largest arm
6167 machine value (iWMMXt2), which is only equivalent to the V5TE
6168 architecture. ARM architectures have advanced beyond the machine
6169 value encoding, and these newer architectures would be ignored if
6170 the machine value was used.
6171
6172 Ie the -m switch is used to restrict which instructions will be
6173 disassembled. If it is necessary to use the -m switch to tell
6174 objdump that an ARM binary is being disassembled, eg because the
6175 input is a raw binary file, but it is also desired to disassemble
6176 all ARM instructions then use "-marm". This will select the
6177 "unknown" arm architecture which is compatible with any ARM
6178 instruction. */
6179 info->mach = bfd_mach_arm_unknown;
6180
6181 /* Compute the architecture bitmask from the machine number.
6182 Note: This assumes that the machine number will not change
6183 during disassembly.... */
b0e28b39 6184 select_arm_features (info->mach, & private.features);
0313a2b8 6185
b0e28b39 6186 private.has_mapping_symbols = -1;
1fbaefec
PB		 6187 private.last_mapping_sym = -1;
6188 private.last_mapping_addr = 0;
b0e28b39
DJ		 6189
6190 info->private_data = & private;
0313a2b8 6191 }
b0e28b39
DJ		 6192
6193 private_data = info->private_data;
6194
bd2e2557
SS		 6195 /* Decide if our code is going to be little-endian, despite what the
6196 function argument might say. */
6197 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6198
b0e28b39
DJ		 6199 /* For ELF, consult the symbol table to determine what kind of code
6200 or data we have. */
8977d4b2 6201 if (info->symtab_size != 0
e821645d
DJ		 6202 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6203 {
6204 bfd_vma addr;
b0e28b39 6205 int n, start;
e821645d 6206 int last_sym = -1;
b0e28b39 6207 enum map_type type = MAP_ARM;
e821645d 6208
e821645d
DJ		 6209 /* Start scanning at the start of the function, or wherever
6210 we finished last time. */
6750a3a7
NC		 6211 /* PR 14006. When the address is 0 we are either at the start of the
6212 very first function, or else the first function in a new, unlinked
6213 executable section (eg because uf -ffunction-sections). Either way
6214 start scanning from the beginning of the symbol table, not where we
6215 left off last time. */
6216 if (pc == 0)
6217 start = 0;
6218 else
6219 {
6220 start = info->symtab_pos + 1;
6221 if (start < private_data->last_mapping_sym)
6222 start = private_data->last_mapping_sym;
6223 }
b0e28b39 6224 found = FALSE;
e821645d 6225
b0e28b39
DJ		 6226 /* First, look for mapping symbols. */
6227 if (private_data->has_mapping_symbols != 0)
e821645d 6228 {
b0e28b39
DJ		 6229 /* Scan up to the location being disassembled. */
6230 for (n = start; n < info->symtab_size; n++)
6231 {
6232 addr = bfd_asymbol_value (info->symtab[n]);
6233 if (addr > pc)
6234 break;
6235 if (get_map_sym_type (info, n, &type))
6236 {
6237 last_sym = n;
6238 found = TRUE;
6239 }
6240 }
6241
6242 if (!found)
6243 {
6244 /* No mapping symbol found at this address. Look backwards
cc643b88 6245 for a preceding one. */
b0e28b39
DJ		 6246 for (n = start - 1; n >= 0; n--)
6247 {
6248 if (get_map_sym_type (info, n, &type))
6249 {
6250 last_sym = n;
6251 found = TRUE;
6252 break;
6253 }
6254 }
6255 }
6256
6257 if (found)
6258 private_data->has_mapping_symbols = 1;
6259
6260 /* No mapping symbols were found. A leading $d may be
6261 omitted for sections which start with data; but for
6262 compatibility with legacy and stripped binaries, only
6263 assume the leading $d if there is at least one mapping
6264 symbol in the file. */
6265 if (!found && private_data->has_mapping_symbols == -1)
e821645d 6266 {
b0e28b39
DJ		 6267 /* Look for mapping symbols, in any section. */
6268 for (n = 0; n < info->symtab_size; n++)
6269 if (is_mapping_symbol (info, n, &type))
6270 {
6271 private_data->has_mapping_symbols = 1;
6272 break;
6273 }
6274 if (private_data->has_mapping_symbols == -1)
6275 private_data->has_mapping_symbols = 0;
6276 }
6277
6278 if (!found && private_data->has_mapping_symbols == 1)
6279 {
6280 type = MAP_DATA;
e821645d
DJ		 6281 found = TRUE;
6282 }
6283 }
6284
b0e28b39
DJ		 6285 /* Next search for function symbols to separate ARM from Thumb
6286 in binaries without mapping symbols. */
e821645d
DJ		 6287 if (!found)
6288 {
b0e28b39
DJ		 6289 /* Scan up to the location being disassembled. */
6290 for (n = start; n < info->symtab_size; n++)
e821645d 6291 {
b0e28b39
DJ		 6292 addr = bfd_asymbol_value (info->symtab[n]);
6293 if (addr > pc)
6294 break;
6295 if (get_sym_code_type (info, n, &type))
e821645d
DJ		 6296 {
6297 last_sym = n;
6298 found = TRUE;
b0e28b39
DJ		 6299 }
6300 }
6301
6302 if (!found)
6303 {
6304 /* No mapping symbol found at this address. Look backwards
cc643b88 6305 for a preceding one. */
b0e28b39
DJ		 6306 for (n = start - 1; n >= 0; n--)
6307 {
6308 if (get_sym_code_type (info, n, &type))
6309 {
6310 last_sym = n;
6311 found = TRUE;
6312 break;
6313 }
e821645d
DJ		 6314 }
6315 }
6316 }
6317
1fbaefec
PB		 6318 private_data->last_mapping_sym = last_sym;
6319 private_data->last_type = type;
6320 is_thumb = (private_data->last_type == MAP_THUMB);
6321 is_data = (private_data->last_type == MAP_DATA);
b34976b6 6322
e821645d
DJ		 6323 /* Look a little bit ahead to see if we should print out
6324 two or four bytes of data. If there's a symbol,
6325 mapping or otherwise, after two bytes then don't
6326 print more. */
6327 if (is_data)
6328 {
6329 size = 4 - (pc & 3);
6330 for (n = last_sym + 1; n < info->symtab_size; n++)
6331 {
6332 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 6333 if (addr > pc
6334 && (info->section == NULL
6335 || info->section == info->symtab[n]->section))
e821645d
DJ		 6336 {
6337 if (addr - pc < size)
6338 size = addr - pc;
6339 break;
6340 }
6341 }
6342 /* If the next symbol is after three bytes, we need to
6343 print only part of the data, so that we can use either
6344 .byte or .short. */
6345 if (size == 3)
6346 size = (pc & 1) ? 1 : 2;
6347 }
6348 }
6349
6350 if (info->symbols != NULL)
252b5132 6351 {
5876e06d
NC		 6352 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6353 {
2f0ca46a 6354 coff_symbol_type * cs;
b34976b6 6355
5876e06d
NC		 6356 cs = coffsymbol (*info->symbols);
6357 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
6358 || cs->native->u.syment.n_sclass == C_THUMBSTAT
6359 || cs->native->u.syment.n_sclass == C_THUMBLABEL
6360 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6361 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6362 }
e821645d
DJ		 6363 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6364 && !found)
5876e06d 6365 {
2087ad84
PB		 6366 /* If no mapping symbol has been found then fall back to the type
6367 of the function symbol. */
e821645d
DJ		 6368 elf_symbol_type * es;
6369 unsigned int type;
2087ad84 6370
e821645d
DJ		 6371 es = *(elf_symbol_type **)(info->symbols);
6372 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 6373
35fc36a8
RS		 6374 is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym)
6375 == ST_BRANCH_TO_THUMB)
6376 || type == STT_ARM_16BIT);
5876e06d 6377 }
e49d43ff
TG		 6378 else if (bfd_asymbol_flavour (*info->symbols)
6379 == bfd_target_mach_o_flavour)
6380 {
6381 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6382
6383 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6384 }
5876e06d 6385 }
b34976b6 6386
e821645d
DJ		 6387 if (force_thumb)
6388 is_thumb = TRUE;
6389
b8f9ee44
CL		 6390 if (is_data)
6391 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6392 else
6393 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6394
c19d1205 6395 info->bytes_per_line = 4;
252b5132 6396
1316c8b3
NC		 6397 /* PR 10263: Disassemble data if requested to do so by the user. */
6398 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 6399 {
6400 int i;
6401
1316c8b3 6402 /* Size was already set above. */
e821645d
DJ		 6403 info->bytes_per_chunk = size;
6404 printer = print_insn_data;
6405
fe56b6ce 6406 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 6407 given = 0;
6408 if (little)
6409 for (i = size - 1; i >= 0; i--)
6410 given = b[i] | (given << 8);
6411 else
6412 for (i = 0; i < (int) size; i++)
6413 given = b[i] | (given << 8);
6414 }
6415 else if (!is_thumb)
252b5132 6416 {
c19d1205
ZW		 6417 /* In ARM mode endianness is a straightforward issue: the instruction
6418 is four bytes long and is either ordered 0123 or 3210. */
6419 printer = print_insn_arm;
6420 info->bytes_per_chunk = 4;
4a5329c6 6421 size = 4;
c19d1205 6422
0313a2b8 6423 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 6424 if (little_code)
c19d1205
ZW		 6425 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6426 else
6427 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 6428 }
58efb6c0 6429 else
252b5132 6430 {
c19d1205
ZW		 6431 /* In Thumb mode we have the additional wrinkle of two
6432 instruction lengths. Fortunately, the bits that determine
6433 the length of the current instruction are always to be found
6434 in the first two bytes. */
4a5329c6 6435 printer = print_insn_thumb16;
c19d1205 6436 info->bytes_per_chunk = 2;
4a5329c6
ZW		 6437 size = 2;
6438
fe56b6ce 6439 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 6440 if (little_code)
9a2ff3f5
AM		 6441 given = (b[0]) | (b[1] << 8);
6442 else
6443 given = (b[1]) | (b[0] << 8);
6444
c19d1205 6445 if (!status)
252b5132 6446 {
c19d1205
ZW		 6447 /* These bit patterns signal a four-byte Thumb
6448 instruction. */
6449 if ((given & 0xF800) == 0xF800
6450 || (given & 0xF800) == 0xF000
6451 || (given & 0xF800) == 0xE800)
252b5132 6452 {
0313a2b8 6453 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 6454 if (little_code)
c19d1205 6455 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 6456 else
c19d1205
ZW		 6457 given = (b[1]) | (b[0] << 8) | (given << 16);
6458
6459 printer = print_insn_thumb32;
4a5329c6 6460 size = 4;
252b5132 6461 }
252b5132 6462 }
c22aaad1
PB		 6463
6464 if (ifthen_address != pc)
0313a2b8 6465 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 6466
6467 if (ifthen_state)
6468 {
6469 if ((ifthen_state & 0xf) == 0x8)
6470 ifthen_next_state = 0;
6471 else
6472 ifthen_next_state = (ifthen_state & 0xe0)
6473 | ((ifthen_state & 0xf) << 1);
6474 }
252b5132 6475 }
b34976b6 6476
c19d1205
ZW		 6477 if (status)
6478 {
6479 info->memory_error_func (status, pc, info);
6480 return -1;
6481 }
6a56ec7e
NC		 6482 if (info->flags & INSN_HAS_RELOC)
6483 /* If the instruction has a reloc associated with it, then
6484 the offset field in the instruction will actually be the
6485 addend for the reloc. (We are using REL type relocs).
6486 In such cases, we can ignore the pc when computing
6487 addresses, since the addend is not currently pc-relative. */
6488 pc = 0;
b34976b6 6489
4a5329c6 6490 printer (pc, info, given);
c22aaad1
PB		 6491
6492 if (is_thumb)
6493 {
6494 ifthen_state = ifthen_next_state;
6495 ifthen_address += size;
6496 }
4a5329c6 6497 return size;
252b5132
RH		 6498}
6499
6500int
4a5329c6 6501print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 6502{
bd2e2557
SS		 6503 /* Detect BE8-ness and record it in the disassembler info. */
6504 if (info->flavour == bfd_target_elf_flavour
6505 && info->section != NULL
6506 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6507 info->endian_code = BFD_ENDIAN_LITTLE;
6508
b34976b6 6509 return print_insn (pc, info, FALSE);
58efb6c0 6510}
01c7f630 6511
58efb6c0 6512int
4a5329c6 6513print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 6514{
b34976b6 6515 return print_insn (pc, info, TRUE);
58efb6c0 6516}
252b5132 6517
58efb6c0 6518void
4a5329c6 6519print_arm_disassembler_options (FILE *stream)
58efb6c0
NC		 6520{
6521 int i;
252b5132 6522
58efb6c0
NC		 6523 fprintf (stream, _("\n\
6524The following ARM specific disassembler options are supported for use with\n\
6525the -M switch:\n"));
b34976b6 6526
58efb6c0
NC		 6527 for (i = NUM_ARM_REGNAMES; i--;)
6528 fprintf (stream, " reg-names-%s %*c%s\n",
6529 regnames[i].name,
d5b2f4d6 6530 (int)(14 - strlen (regnames[i].name)), ' ',
58efb6c0
NC		 6531 regnames[i].description);
6532
6533 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
cc643b88 6534 fprintf (stream, " no-force-thumb Examine preceding label to determine an insn's type\n\n");
252b5132 6535}
GDB Binutils - Deliverables
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