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Add support for intel TSXLDTRK instructions$
[deliverable/binutils-gdb.git] / opcodes / bfin-dis.c
CommitLineData
4b7f6baa 1/* Disassemble ADI Blackfin Instructions.
b3adc24a 2 Copyright (C) 2005-2020 Free Software Foundation, Inc.
4b7f6baa 3
9b201bb5
NC		 4 This file is part of libopcodes.
5
6 This library is free software; you can redistribute it and/or modify
4b7f6baa 7 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
4b7f6baa 10
9b201bb5
NC		 11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
4b7f6baa
CM		 15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
5eb3690e 21#include "sysdep.h"
4b7f6baa 22#include <stdio.h>
4b7f6baa
CM		 23
24#include "opcode/bfin.h"
25
4b7f6baa
CM		 26#ifndef PRINTF
27#define PRINTF printf
28#endif
29
30#ifndef EXIT
31#define EXIT exit
32#endif
33
34typedef long TIword;
35
2fd2b153
AM		 36#define SIGNBIT(bits) (1ul << ((bits) - 1))
37#define MASKBITS(val, bits) ((val) & ((1ul << (bits)) - 1))
38#define SIGNEXTEND(v, n) ((MASKBITS (v, n) ^ SIGNBIT (n)) - SIGNBIT (n))
4b7f6baa 39
88c1242d 40#include "disassemble.h"
b7d48530 41
b21c9cb4
BS		 42typedef unsigned int bu32;
43
703ec4e8
MF		 44struct private
45{
a4e600b2 46 TIword iw0;
60ac5798 47 bfd_boolean comment, parallel;
703ec4e8 48};
528c6277 49
4b7f6baa
CM		 50typedef enum
51{
52 c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
086134ec
BS		 53 c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
54 c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
55 c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
56 c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
4b7f6baa
CM		 57} const_forms_t;
58
528c6277 59static const struct
4b7f6baa 60{
528c6277
MF		 61 const char *name;
62 const int nbits;
63 const char reloc;
64 const char issigned;
65 const char pcrel;
66 const char scale;
67 const char offset;
68 const char negative;
69 const char positive;
70 const char decimal;
71 const char leading;
72 const char exact;
4b7f6baa
CM		 73} constant_formats[] =
74{
086134ec
BS		 75 { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
76 { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
77 { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
78 { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
79 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
80 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
81 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
82 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
83 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
84 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
85 { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
86 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
87 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
88 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
89 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
90 { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
91 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
92 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
93 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
94 { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
95 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
96 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
97 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
98 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
99 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
100 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
101 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
102 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
103 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
104 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
105 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
106 { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
107 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
108 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
109 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
110 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
111 { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
112 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
113 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
114 { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
115 { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
116 { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
117 { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
4b7f6baa
CM		 118};
119
528c6277
MF		 120static const char *
121fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
4b7f6baa
CM		 122{
123 static char buf[60];
124
125 if (constant_formats[cf].reloc)
126 {
2fd2b153
AM		 127 bfd_vma ea;
128
129 if (constant_formats[cf].pcrel)
130 x = SIGNEXTEND (x, constant_formats[cf].nbits);
cedfc774
AM		 131 ea = x + constant_formats[cf].offset;
132 ea = ea << constant_formats[cf].scale;
4b7f6baa
CM		 133 if (constant_formats[cf].pcrel)
134 ea += pc;
135
602427c4
MF		 136 /* truncate to 32-bits for proper symbol lookup/matching */
137 ea = (bu32)ea;
7a360e83 138
602427c4
MF		 139 if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
140 {
086134ec
BS		 141 outf->print_address_func (ea, outf);
142 return "";
602427c4
MF		 143 }
144 else
145 {
0af1713e 146 sprintf (buf, "%lx", (unsigned long) x);
086134ec 147 return buf;
602427c4 148 }
4b7f6baa
CM		 149 }
150
151 /* Negative constants have an implied sign bit. */
152 if (constant_formats[cf].negative)
153 {
154 int nb = constant_formats[cf].nbits + 1;
b7d48530 155
cedfc774 156 x = x | (1ul << constant_formats[cf].nbits);
4b7f6baa
CM		 157 x = SIGNEXTEND (x, nb);
158 }
2fd2b153
AM		 159 else if (constant_formats[cf].issigned)
160 x = SIGNEXTEND (x, constant_formats[cf].nbits);
4b7f6baa 161
cedfc774
AM		 162 x += constant_formats[cf].offset;
163 x = (unsigned long) x << constant_formats[cf].scale;
4b7f6baa 164
086134ec 165 if (constant_formats[cf].decimal)
5de10af0 166 sprintf (buf, "%*li", constant_formats[cf].leading, x);
4b7f6baa 167 else
086134ec
BS		 168 {
169 if (constant_formats[cf].issigned && x < 0)
b6518b38 170 sprintf (buf, "-0x%lx", (unsigned long)(- x));
086134ec 171 else
0af1713e 172 sprintf (buf, "0x%lx", (unsigned long) x);
086134ec 173 }
4b7f6baa
CM		 174
175 return buf;
176}
177
b21c9cb4
BS		 178static bu32
179fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
180{
181 if (0 && constant_formats[cf].reloc)
182 {
2fd2b153
AM		 183 bu32 ea;
184
185 if (constant_formats[cf].pcrel)
186 x = SIGNEXTEND (x, constant_formats[cf].nbits);
cedfc774
AM		 187 ea = x + constant_formats[cf].offset;
188 ea = ea << constant_formats[cf].scale;
b21c9cb4 189 if (constant_formats[cf].pcrel)
086134ec 190 ea += pc;
b21c9cb4
BS		 191
192 return ea;
193 }
194
195 /* Negative constants have an implied sign bit. */
196 if (constant_formats[cf].negative)
197 {
198 int nb = constant_formats[cf].nbits + 1;
cedfc774 199 x = x | (1ul << constant_formats[cf].nbits);
b21c9cb4
BS		 200 x = SIGNEXTEND (x, nb);
201 }
202 else if (constant_formats[cf].issigned)
203 x = SIGNEXTEND (x, constant_formats[cf].nbits);
204
205 x += constant_formats[cf].offset;
206 x <<= constant_formats[cf].scale;
207
208 return x;
209}
210
4b7f6baa
CM		 211enum machine_registers
212{
213 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
214 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
215 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
216 REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
217 REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
218 REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
219 REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
220 REG_L2, REG_L3,
221 REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
222 REG_AQ, REG_V, REG_VS,
223 REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
43a6aa65 224 REG_LC1, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
4b7f6baa
CM		 225 REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
226 REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
227 REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
228 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
229 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
230 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
231 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
232 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
22215ae0 233 REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
4b7f6baa
CM		 234 REG_LASTREG,
235};
236
237enum reg_class
238{
239 rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
240 rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
241 rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
242 rc_sysregs3, rc_allregs,
243 LIM_REG_CLASSES
244};
245
69b8ea4a 246static const char * const reg_names[] =
4b7f6baa
CM		 247{
248 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
249 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
250 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
251 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
086134ec 252 "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
4b7f6baa
CM		 253 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
254 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
255 "L2", "L3",
256 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
257 "AQ", "V", "VS",
258 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
43a6aa65 259 "LC1", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
4b7f6baa
CM		 260 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
261 "RETE", "EMUDAT",
262 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
263 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
264 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
265 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
266 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
267 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
268 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
22215ae0 269 "AC0_COPY", "V_COPY", "RND_MOD",
4b7f6baa
CM		 270 "LASTREG",
271 0
272};
273
274#define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
275
276/* RL(0..7). */
69b8ea4a 277static const enum machine_registers decode_dregs_lo[] =
4b7f6baa
CM		 278{
279 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
280};
281
b7d48530 282#define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
4b7f6baa
CM		 283
284/* RH(0..7). */
69b8ea4a 285static const enum machine_registers decode_dregs_hi[] =
4b7f6baa
CM		 286{
287 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
288};
289
b7d48530 290#define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
4b7f6baa
CM		 291
292/* R(0..7). */
69b8ea4a 293static const enum machine_registers decode_dregs[] =
4b7f6baa
CM		 294{
295 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
296};
297
b7d48530 298#define dregs(x) REGNAME (decode_dregs[(x) & 7])
4b7f6baa
CM		 299
300/* R BYTE(0..7). */
69b8ea4a 301static const enum machine_registers decode_dregs_byte[] =
4b7f6baa
CM		 302{
303 REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
304};
305
b7d48530 306#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
4b7f6baa
CM		 307
308/* P(0..5) SP FP. */
69b8ea4a 309static const enum machine_registers decode_pregs[] =
4b7f6baa
CM		 310{
311 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
312};
313
b7d48530
NC		 314#define pregs(x) REGNAME (decode_pregs[(x) & 7])
315#define spfp(x) REGNAME (decode_spfp[(x) & 1])
602427c4 316#define dregs_hilo(x, i) REGNAME (decode_dregs_hilo[((i) << 3) | (x)])
b7d48530
NC		 317#define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
318#define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
319#define accum(x) REGNAME (decode_accum[(x) & 1])
4b7f6baa
CM		 320
321/* I(0..3). */
69b8ea4a 322static const enum machine_registers decode_iregs[] =
4b7f6baa
CM		 323{
324 REG_I0, REG_I1, REG_I2, REG_I3,
325};
326
b7d48530 327#define iregs(x) REGNAME (decode_iregs[(x) & 3])
4b7f6baa
CM		 328
329/* M(0..3). */
69b8ea4a 330static const enum machine_registers decode_mregs[] =
4b7f6baa
CM		 331{
332 REG_M0, REG_M1, REG_M2, REG_M3,
333};
334
b7d48530
NC		 335#define mregs(x) REGNAME (decode_mregs[(x) & 3])
336#define bregs(x) REGNAME (decode_bregs[(x) & 3])
337#define lregs(x) REGNAME (decode_lregs[(x) & 3])
4b7f6baa
CM		 338
339/* dregs pregs. */
69b8ea4a 340static const enum machine_registers decode_dpregs[] =
4b7f6baa
CM		 341{
342 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
343 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
344};
345
b7d48530 346#define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
4b7f6baa
CM		 347
348/* [dregs pregs]. */
69b8ea4a 349static const enum machine_registers decode_gregs[] =
4b7f6baa
CM		 350{
351 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
352 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
353};
354
08c7881b 355#define gregs(x, i) REGNAME (decode_gregs[(((i) << 3) | (x)) & 15])
4b7f6baa
CM		 356
357/* [dregs pregs (iregs mregs) (bregs lregs)]. */
69b8ea4a 358static const enum machine_registers decode_regs[] =
4b7f6baa
CM		 359{
360 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
361 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
362 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
363 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
364};
365
08c7881b 366#define regs(x, i) REGNAME (decode_regs[(((i) << 3) | (x)) & 31])
4b7f6baa
CM		 367
368/* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
69b8ea4a 369static const enum machine_registers decode_regs_lo[] =
4b7f6baa
CM		 370{
371 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
372 REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
373 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
374 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
375};
376
08c7881b 377#define regs_lo(x, i) REGNAME (decode_regs_lo[(((i) << 3) | (x)) & 31])
602427c4 378
4b7f6baa 379/* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
69b8ea4a 380static const enum machine_registers decode_regs_hi[] =
4b7f6baa
CM		 381{
382 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
383 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
1985c81c 384 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
4b7f6baa
CM		 385 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
386};
387
08c7881b 388#define regs_hi(x, i) REGNAME (decode_regs_hi[(((i) << 3) | (x)) & 31])
4b7f6baa 389
69b8ea4a 390static const enum machine_registers decode_statbits[] =
4b7f6baa 391{
22215ae0
MF		 392 REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
393 REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
394 REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG,
395 REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
396 REG_AV0, REG_AV0S, REG_AV1, REG_AV1S,
397 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
398 REG_V, REG_VS, REG_LASTREG, REG_LASTREG,
399 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
4b7f6baa
CM		 400};
401
ad15c38e 402#define statbits(x) REGNAME (decode_statbits[(x) & 31])
4b7f6baa
CM		 403
404/* LC0 LC1. */
69b8ea4a 405static const enum machine_registers decode_counters[] =
4b7f6baa
CM		 406{
407 REG_LC0, REG_LC1,
408};
409
b7d48530
NC		 410#define counters(x) REGNAME (decode_counters[(x) & 1])
411#define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
4b7f6baa
CM		 412
413/* [dregs pregs (iregs mregs) (bregs lregs)
414 dregs2_sysregs1 open sysregs2 sysregs3]. */
69b8ea4a 415static const enum machine_registers decode_allregs[] =
4b7f6baa
CM		 416{
417 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
418 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
419 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
420 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
43a6aa65 421 REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_LASTREG, REG_LASTREG, REG_ASTAT, REG_RETS,
4b7f6baa
CM		 422 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
423 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
c958a8a8
JZ		 424 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
425 REG_LASTREG,
4b7f6baa
CM		 426};
427
50e2162a
MF		 428#define IS_DREG(g,r) ((g) == 0 && (r) < 8)
429#define IS_PREG(g,r) ((g) == 1 && (r) < 8)
c958a8a8 430#define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
50e2162a
MF		 431#define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
432#define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
c958a8a8
JZ		 433#define IS_SYSREG(g,r) \
434 (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
50e2162a
MF		 435#define IS_RESERVEDREG(g,r) \
436 (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
437
438#define allreg(r,g) (!IS_RESERVEDREG (g, r))
439#define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
c958a8a8 440
602427c4 441#define allregs(x, i) REGNAME (decode_allregs[((i) << 3) | (x)])
b7d48530 442#define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
086134ec 443#define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
b7d48530
NC		 444#define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
445#define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
446#define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
447#define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
448#define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
449#define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
450#define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
451#define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
452#define imm16(x) fmtconst (c_imm16, x, 0, outf)
086134ec 453#define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
b7d48530
NC		 454#define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
455#define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
456#define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
457#define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
458#define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
459#define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
460#define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
461#define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
462#define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
463#define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
086134ec 464#define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
b7d48530
NC		 465#define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
466#define imm3(x) fmtconst (c_imm3, x, 0, outf)
467#define imm4(x) fmtconst (c_imm4, x, 0, outf)
468#define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
469#define imm5(x) fmtconst (c_imm5, x, 0, outf)
086134ec 470#define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
b7d48530
NC		 471#define imm6(x) fmtconst (c_imm6, x, 0, outf)
472#define imm7(x) fmtconst (c_imm7, x, 0, outf)
086134ec 473#define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
b7d48530
NC		 474#define imm8(x) fmtconst (c_imm8, x, 0, outf)
475#define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
476#define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
b21c9cb4 477#define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
086134ec 478#define imm32(x) fmtconst (c_imm32, x, 0, outf)
b21c9cb4 479#define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
086134ec
BS		 480#define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
481#define imm7_val(x) fmtconst_val (c_imm7, x, 0)
b21c9cb4
BS		 482#define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
483#define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
4b7f6baa
CM		 484
485/* (arch.pm)arch_disassembler_functions. */
4b7f6baa 486#ifndef OUTS
500cccad 487#define OUTS(p, txt) (p)->fprintf_func ((p)->stream, "%s", txt)
4b7f6baa 488#endif
b3f3b4b0 489#define OUT(p, txt, ...) (p)->fprintf_func ((p)->stream, txt, ## __VA_ARGS__)
4b7f6baa 490
4b7f6baa
CM		 491static void
492amod0 (int s0, int x0, disassemble_info *outf)
493{
b7d48530 494 if (s0 == 1 && x0 == 0)
086134ec 495 OUTS (outf, " (S)");
4b7f6baa 496 else if (s0 == 0 && x0 == 1)
086134ec 497 OUTS (outf, " (CO)");
4b7f6baa 498 else if (s0 == 1 && x0 == 1)
086134ec 499 OUTS (outf, " (SCO)");
4b7f6baa
CM		 500}
501
502static void
503amod1 (int s0, int x0, disassemble_info *outf)
504{
505 if (s0 == 0 && x0 == 0)
086134ec 506 OUTS (outf, " (NS)");
4b7f6baa 507 else if (s0 == 1 && x0 == 0)
086134ec 508 OUTS (outf, " (S)");
4b7f6baa
CM		 509}
510
511static void
512amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
513{
b7d48530 514 if (s0 == 1 && x0 == 0 && aop0 == 0)
086134ec 515 OUTS (outf, " (S)");
4b7f6baa 516 else if (s0 == 0 && x0 == 1 && aop0 == 0)
086134ec 517 OUTS (outf, " (CO)");
4b7f6baa 518 else if (s0 == 1 && x0 == 1 && aop0 == 0)
086134ec 519 OUTS (outf, " (SCO)");
4b7f6baa 520 else if (s0 == 0 && x0 == 0 && aop0 == 2)
086134ec 521 OUTS (outf, " (ASR)");
4b7f6baa 522 else if (s0 == 1 && x0 == 0 && aop0 == 2)
086134ec 523 OUTS (outf, " (S, ASR)");
4b7f6baa 524 else if (s0 == 0 && x0 == 1 && aop0 == 2)
086134ec 525 OUTS (outf, " (CO, ASR)");
4b7f6baa 526 else if (s0 == 1 && x0 == 1 && aop0 == 2)
086134ec 527 OUTS (outf, " (SCO, ASR)");
4b7f6baa 528 else if (s0 == 0 && x0 == 0 && aop0 == 3)
086134ec 529 OUTS (outf, " (ASL)");
4b7f6baa 530 else if (s0 == 1 && x0 == 0 && aop0 == 3)
086134ec 531 OUTS (outf, " (S, ASL)");
4b7f6baa 532 else if (s0 == 0 && x0 == 1 && aop0 == 3)
086134ec 533 OUTS (outf, " (CO, ASL)");
4b7f6baa 534 else if (s0 == 1 && x0 == 1 && aop0 == 3)
086134ec 535 OUTS (outf, " (SCO, ASL)");
4b7f6baa
CM		 536}
537
538static void
539searchmod (int r0, disassemble_info *outf)
540{
b7d48530
NC		 541 if (r0 == 0)
542 OUTS (outf, "GT");
543 else if (r0 == 1)
544 OUTS (outf, "GE");
545 else if (r0 == 2)
546 OUTS (outf, "LT");
547 else if (r0 == 3)
548 OUTS (outf, "LE");
4b7f6baa
CM		 549}
550
551static void
552aligndir (int r0, disassemble_info *outf)
553{
b7d48530 554 if (r0 == 1)
086134ec 555 OUTS (outf, " (R)");
4b7f6baa
CM		 556}
557
558static int
602427c4 559decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf)
4b7f6baa 560{
528c6277 561 const char *s0, *s1;
4b7f6baa
CM		 562
563 if (h0)
564 s0 = dregs_hi (src0);
565 else
566 s0 = dregs_lo (src0);
567
568 if (h1)
569 s1 = dregs_hi (src1);
570 else
571 s1 = dregs_lo (src1);
572
573 OUTS (outf, s0);
574 OUTS (outf, " * ");
575 OUTS (outf, s1);
576 return 0;
577}
578
579static int
602427c4 580decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf)
4b7f6baa 581{
528c6277
MF		 582 const char *a;
583 const char *sop = "<unknown op>";
4b7f6baa
CM		 584
585 if (which)
086134ec 586 a = "A1";
4b7f6baa 587 else
086134ec 588 a = "A0";
4b7f6baa
CM		 589
590 if (op == 3)
591 {
592 OUTS (outf, a);
593 return 0;
594 }
595
596 switch (op)
597 {
086134ec
BS		 598 case 0: sop = " = "; break;
599 case 1: sop = " += "; break;
600 case 2: sop = " -= "; break;
b7d48530 601 default: break;
4b7f6baa
CM		 602 }
603
604 OUTS (outf, a);
4b7f6baa 605 OUTS (outf, sop);
4b7f6baa
CM		 606 decode_multfunc (h0, h1, src0, src1, outf);
607
608 return 0;
609}
610
611static void
612decode_optmode (int mod, int MM, disassemble_info *outf)
613{
614 if (mod == 0 && MM == 0)
615 return;
616
617 OUTS (outf, " (");
618
619 if (MM && !mod)
620 {
621 OUTS (outf, "M)");
622 return;
623 }
624
625 if (MM)
626 OUTS (outf, "M, ");
b7d48530 627
4b7f6baa
CM		 628 if (mod == M_S2RND)
629 OUTS (outf, "S2RND");
630 else if (mod == M_T)
631 OUTS (outf, "T");
632 else if (mod == M_W32)
633 OUTS (outf, "W32");
634 else if (mod == M_FU)
635 OUTS (outf, "FU");
636 else if (mod == M_TFU)
637 OUTS (outf, "TFU");
638 else if (mod == M_IS)
639 OUTS (outf, "IS");
640 else if (mod == M_ISS2)
641 OUTS (outf, "ISS2");
642 else if (mod == M_IH)
643 OUTS (outf, "IH");
644 else if (mod == M_IU)
645 OUTS (outf, "IU");
646 else
647 abort ();
648
649 OUTS (outf, ")");
650}
b7d48530 651
e5bc4265 652static struct saved_state
b21c9cb4
BS		 653{
654 bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
e5bc4265 655 bu32 ax[2], aw[2];
b21c9cb4 656 bu32 lt[2], lc[2], lb[2];
e5bc4265 657 bu32 rets;
602427c4 658} saved_state;
b21c9cb4
BS		 659
660#define DREG(x) (saved_state.dpregs[x])
602427c4 661#define GREG(x, i) DPREG ((x) | ((i) << 3))
b21c9cb4
BS		 662#define DPREG(x) (saved_state.dpregs[x])
663#define DREG(x) (saved_state.dpregs[x])
602427c4 664#define PREG(x) (saved_state.dpregs[(x) + 8])
b21c9cb4
BS		 665#define SPREG PREG (6)
666#define FPREG PREG (7)
667#define IREG(x) (saved_state.iregs[x])
668#define MREG(x) (saved_state.mregs[x])
669#define BREG(x) (saved_state.bregs[x])
670#define LREG(x) (saved_state.lregs[x])
e5bc4265
MF		 671#define AXREG(x) (saved_state.ax[x])
672#define AWREG(x) (saved_state.aw[x])
673#define LCREG(x) (saved_state.lc[x])
674#define LTREG(x) (saved_state.lt[x])
675#define LBREG(x) (saved_state.lb[x])
b21c9cb4 676#define RETSREG (saved_state.rets)
b21c9cb4
BS		 677
678static bu32 *
679get_allreg (int grp, int reg)
680{
681 int fullreg = (grp << 3) | reg;
682 /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
683 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
684 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
685 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
686 REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
687 , , , , , , , ,
688 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
689 REG_CYCLES2,
690 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
691 REG_LASTREG */
692 switch (fullreg >> 2)
693 {
e5bc4265
MF		 694 case 0: case 1: return &DREG (reg);
695 case 2: case 3: return &PREG (reg);
696 case 4: return &IREG (reg & 3);
697 case 5: return &MREG (reg & 3);
698 case 6: return &BREG (reg & 3);
699 case 7: return &LREG (reg & 3);
b21c9cb4
BS		 700 default:
701 switch (fullreg)
086134ec 702 {
e5bc4265
MF		 703 case 32: return &AXREG (0);
704 case 33: return &AWREG (0);
705 case 34: return &AXREG (1);
706 case 35: return &AWREG (1);
707 case 39: return &RETSREG;
708 case 48: return &LCREG (0);
709 case 49: return &LTREG (0);
710 case 50: return &LBREG (0);
711 case 51: return &LCREG (1);
712 case 52: return &LTREG (1);
713 case 53: return &LBREG (1);
086134ec 714 }
b21c9cb4 715 }
e5bc4265 716 abort ();
b21c9cb4
BS		 717}
718
4b7f6baa
CM		 719static int
720decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
721{
703ec4e8 722 struct private *priv = outf->private_data;
b7d48530
NC		 723 /* ProgCtrl
724 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
725 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
726 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 727 int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
728 int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
729
730 if (prgfunc == 0 && poprnd == 0)
b7d48530 731 OUTS (outf, "NOP");
703ec4e8 732 else if (priv->parallel)
219b747a 733 return 0;
4b7f6baa 734 else if (prgfunc == 1 && poprnd == 0)
b7d48530 735 OUTS (outf, "RTS");
4b7f6baa 736 else if (prgfunc == 1 && poprnd == 1)
b7d48530 737 OUTS (outf, "RTI");
4b7f6baa 738 else if (prgfunc == 1 && poprnd == 2)
b7d48530 739 OUTS (outf, "RTX");
4b7f6baa 740 else if (prgfunc == 1 && poprnd == 3)
b7d48530 741 OUTS (outf, "RTN");
4b7f6baa 742 else if (prgfunc == 1 && poprnd == 4)
b7d48530 743 OUTS (outf, "RTE");
4b7f6baa 744 else if (prgfunc == 2 && poprnd == 0)
b7d48530 745 OUTS (outf, "IDLE");
4b7f6baa 746 else if (prgfunc == 2 && poprnd == 3)
b7d48530 747 OUTS (outf, "CSYNC");
4b7f6baa 748 else if (prgfunc == 2 && poprnd == 4)
b7d48530 749 OUTS (outf, "SSYNC");
4b7f6baa 750 else if (prgfunc == 2 && poprnd == 5)
b7d48530 751 OUTS (outf, "EMUEXCPT");
50e2162a 752 else if (prgfunc == 3 && IS_DREG (0, poprnd))
4b7f6baa 753 {
086134ec 754 OUTS (outf, "CLI ");
4b7f6baa 755 OUTS (outf, dregs (poprnd));
4b7f6baa 756 }
50e2162a 757 else if (prgfunc == 4 && IS_DREG (0, poprnd))
4b7f6baa 758 {
086134ec 759 OUTS (outf, "STI ");
4b7f6baa 760 OUTS (outf, dregs (poprnd));
4b7f6baa 761 }
50e2162a 762 else if (prgfunc == 5 && IS_PREG (1, poprnd))
4b7f6baa 763 {
086134ec 764 OUTS (outf, "JUMP (");
4b7f6baa
CM		 765 OUTS (outf, pregs (poprnd));
766 OUTS (outf, ")");
4b7f6baa 767 }
50e2162a 768 else if (prgfunc == 6 && IS_PREG (1, poprnd))
4b7f6baa 769 {
086134ec 770 OUTS (outf, "CALL (");
4b7f6baa
CM		 771 OUTS (outf, pregs (poprnd));
772 OUTS (outf, ")");
4b7f6baa 773 }
50e2162a 774 else if (prgfunc == 7 && IS_PREG (1, poprnd))
4b7f6baa 775 {
086134ec 776 OUTS (outf, "CALL (PC + ");
4b7f6baa
CM		 777 OUTS (outf, pregs (poprnd));
778 OUTS (outf, ")");
4b7f6baa 779 }
50e2162a 780 else if (prgfunc == 8 && IS_PREG (1, poprnd))
4b7f6baa 781 {
086134ec 782 OUTS (outf, "JUMP (PC + ");
4b7f6baa
CM		 783 OUTS (outf, pregs (poprnd));
784 OUTS (outf, ")");
4b7f6baa
CM		 785 }
786 else if (prgfunc == 9)
787 {
086134ec 788 OUTS (outf, "RAISE ");
4b7f6baa 789 OUTS (outf, uimm4 (poprnd));
4b7f6baa
CM		 790 }
791 else if (prgfunc == 10)
792 {
086134ec 793 OUTS (outf, "EXCPT ");
4b7f6baa 794 OUTS (outf, uimm4 (poprnd));
4b7f6baa 795 }
219b747a 796 else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5)
4b7f6baa 797 {
086134ec 798 OUTS (outf, "TESTSET (");
4b7f6baa
CM		 799 OUTS (outf, pregs (poprnd));
800 OUTS (outf, ")");
4b7f6baa
CM		 801 }
802 else
b7d48530
NC		 803 return 0;
804 return 2;
4b7f6baa
CM		 805}
806
807static int
808decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
809{
703ec4e8 810 struct private *priv = outf->private_data;
b7d48530
NC		 811 /* CaCTRL
812 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
813 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
814 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 815 int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
816 int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
817 int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
818
703ec4e8 819 if (priv->parallel)
219b747a
MF		 820 return 0;
821
4b7f6baa
CM		 822 if (a == 0 && op == 0)
823 {
4b7f6baa
CM		 824 OUTS (outf, "PREFETCH[");
825 OUTS (outf, pregs (reg));
826 OUTS (outf, "]");
4b7f6baa
CM		 827 }
828 else if (a == 0 && op == 1)
829 {
4b7f6baa
CM		 830 OUTS (outf, "FLUSHINV[");
831 OUTS (outf, pregs (reg));
832 OUTS (outf, "]");
4b7f6baa
CM		 833 }
834 else if (a == 0 && op == 2)
835 {
4b7f6baa
CM		 836 OUTS (outf, "FLUSH[");
837 OUTS (outf, pregs (reg));
838 OUTS (outf, "]");
4b7f6baa
CM		 839 }
840 else if (a == 0 && op == 3)
841 {
4b7f6baa
CM		 842 OUTS (outf, "IFLUSH[");
843 OUTS (outf, pregs (reg));
844 OUTS (outf, "]");
4b7f6baa
CM		 845 }
846 else if (a == 1 && op == 0)
847 {
4b7f6baa
CM		 848 OUTS (outf, "PREFETCH[");
849 OUTS (outf, pregs (reg));
850 OUTS (outf, "++]");
4b7f6baa
CM		 851 }
852 else if (a == 1 && op == 1)
853 {
4b7f6baa
CM		 854 OUTS (outf, "FLUSHINV[");
855 OUTS (outf, pregs (reg));
856 OUTS (outf, "++]");
4b7f6baa
CM		 857 }
858 else if (a == 1 && op == 2)
859 {
4b7f6baa
CM		 860 OUTS (outf, "FLUSH[");
861 OUTS (outf, pregs (reg));
862 OUTS (outf, "++]");
4b7f6baa
CM		 863 }
864 else if (a == 1 && op == 3)
865 {
4b7f6baa
CM		 866 OUTS (outf, "IFLUSH[");
867 OUTS (outf, pregs (reg));
868 OUTS (outf, "++]");
4b7f6baa
CM		 869 }
870 else
b7d48530
NC		 871 return 0;
872 return 2;
4b7f6baa
CM		 873}
874
875static int
876decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
877{
703ec4e8 878 struct private *priv = outf->private_data;
b7d48530
NC		 879 /* PushPopReg
880 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
881 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
882 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 883 int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
884 int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
885 int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
886
703ec4e8 887 if (priv->parallel)
219b747a
MF		 888 return 0;
889
50e2162a 890 if (W == 0 && mostreg (reg, grp))
4b7f6baa 891 {
4b7f6baa
CM		 892 OUTS (outf, allregs (reg, grp));
893 OUTS (outf, " = [SP++]");
4b7f6baa 894 }
219b747a 895 else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6))
4b7f6baa 896 {
4b7f6baa
CM		 897 OUTS (outf, "[--SP] = ");
898 OUTS (outf, allregs (reg, grp));
4b7f6baa
CM		 899 }
900 else
b7d48530
NC		 901 return 0;
902 return 2;
4b7f6baa
CM		 903}
904
905static int
906decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
907{
703ec4e8 908 struct private *priv = outf->private_data;
b7d48530
NC		 909 /* PushPopMultiple
910 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
911 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
912 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 913 int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
914 int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
915 int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
916 int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
917 int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
4b7f6baa 918
703ec4e8 919 if (priv->parallel)
219b747a
MF		 920 return 0;
921
775f1cf0
MF		 922 if (pr > 5)
923 return 0;
924
4b7f6baa
CM		 925 if (W == 1 && d == 1 && p == 1)
926 {
4b7f6baa 927 OUTS (outf, "[--SP] = (R7:");
086134ec 928 OUTS (outf, imm5d (dr));
4b7f6baa 929 OUTS (outf, ", P5:");
086134ec 930 OUTS (outf, imm5d (pr));
4b7f6baa 931 OUTS (outf, ")");
4b7f6baa 932 }
219b747a 933 else if (W == 1 && d == 1 && p == 0 && pr == 0)
4b7f6baa 934 {
4b7f6baa 935 OUTS (outf, "[--SP] = (R7:");
086134ec 936 OUTS (outf, imm5d (dr));
4b7f6baa 937 OUTS (outf, ")");
4b7f6baa 938 }
219b747a 939 else if (W == 1 && d == 0 && p == 1 && dr == 0)
4b7f6baa 940 {
4b7f6baa 941 OUTS (outf, "[--SP] = (P5:");
086134ec 942 OUTS (outf, imm5d (pr));
4b7f6baa 943 OUTS (outf, ")");
4b7f6baa
CM		 944 }
945 else if (W == 0 && d == 1 && p == 1)
946 {
4b7f6baa 947 OUTS (outf, "(R7:");
086134ec 948 OUTS (outf, imm5d (dr));
4b7f6baa 949 OUTS (outf, ", P5:");
086134ec 950 OUTS (outf, imm5d (pr));
4b7f6baa 951 OUTS (outf, ") = [SP++]");
4b7f6baa 952 }
219b747a 953 else if (W == 0 && d == 1 && p == 0 && pr == 0)
4b7f6baa 954 {
4b7f6baa 955 OUTS (outf, "(R7:");
086134ec 956 OUTS (outf, imm5d (dr));
4b7f6baa 957 OUTS (outf, ") = [SP++]");
4b7f6baa 958 }
219b747a 959 else if (W == 0 && d == 0 && p == 1 && dr == 0)
4b7f6baa 960 {
4b7f6baa 961 OUTS (outf, "(P5:");
086134ec 962 OUTS (outf, imm5d (pr));
4b7f6baa 963 OUTS (outf, ") = [SP++]");
4b7f6baa
CM		 964 }
965 else
b7d48530
NC		 966 return 0;
967 return 2;
4b7f6baa
CM		 968}
969
970static int
971decode_ccMV_0 (TIword iw0, disassemble_info *outf)
972{
703ec4e8 973 struct private *priv = outf->private_data;
b7d48530
NC		 974 /* ccMV
975 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
976 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
977 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 978 int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
979 int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
980 int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
981 int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
982 int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
983
703ec4e8 984 if (priv->parallel)
219b747a
MF		 985 return 0;
986
4b7f6baa
CM		 987 if (T == 1)
988 {
4b7f6baa
CM		 989 OUTS (outf, "IF CC ");
990 OUTS (outf, gregs (dst, d));
991 OUTS (outf, " = ");
992 OUTS (outf, gregs (src, s));
4b7f6baa
CM		 993 }
994 else if (T == 0)
995 {
086134ec 996 OUTS (outf, "IF !CC ");
4b7f6baa
CM		 997 OUTS (outf, gregs (dst, d));
998 OUTS (outf, " = ");
999 OUTS (outf, gregs (src, s));
4b7f6baa
CM		 1000 }
1001 else
b7d48530
NC		 1002 return 0;
1003 return 2;
4b7f6baa
CM		 1004}
1005
1006static int
1007decode_CCflag_0 (TIword iw0, disassemble_info *outf)
1008{
703ec4e8 1009 struct private *priv = outf->private_data;
b7d48530
NC		 1010 /* CCflag
1011 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1012 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1013 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1014 int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1015 int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1016 int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1017 int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1018 int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1019
703ec4e8 1020 if (priv->parallel)
219b747a
MF		 1021 return 0;
1022
4b7f6baa
CM		 1023 if (opc == 0 && I == 0 && G == 0)
1024 {
086134ec 1025 OUTS (outf, "CC = ");
4b7f6baa 1026 OUTS (outf, dregs (x));
086134ec 1027 OUTS (outf, " == ");
4b7f6baa 1028 OUTS (outf, dregs (y));
4b7f6baa
CM		 1029 }
1030 else if (opc == 1 && I == 0 && G == 0)
1031 {
086134ec 1032 OUTS (outf, "CC = ");
4b7f6baa 1033 OUTS (outf, dregs (x));
086134ec 1034 OUTS (outf, " < ");
4b7f6baa 1035 OUTS (outf, dregs (y));
4b7f6baa
CM		 1036 }
1037 else if (opc == 2 && I == 0 && G == 0)
1038 {
086134ec 1039 OUTS (outf, "CC = ");
4b7f6baa 1040 OUTS (outf, dregs (x));
086134ec 1041 OUTS (outf, " <= ");
4b7f6baa 1042 OUTS (outf, dregs (y));
4b7f6baa
CM		 1043 }
1044 else if (opc == 3 && I == 0 && G == 0)
1045 {
086134ec 1046 OUTS (outf, "CC = ");
4b7f6baa 1047 OUTS (outf, dregs (x));
086134ec 1048 OUTS (outf, " < ");
4b7f6baa 1049 OUTS (outf, dregs (y));
086134ec 1050 OUTS (outf, " (IU)");
4b7f6baa
CM		 1051 }
1052 else if (opc == 4 && I == 0 && G == 0)
1053 {
086134ec 1054 OUTS (outf, "CC = ");
4b7f6baa 1055 OUTS (outf, dregs (x));
086134ec 1056 OUTS (outf, " <= ");
4b7f6baa 1057 OUTS (outf, dregs (y));
086134ec 1058 OUTS (outf, " (IU)");
4b7f6baa
CM		 1059 }
1060 else if (opc == 0 && I == 1 && G == 0)
1061 {
086134ec 1062 OUTS (outf, "CC = ");
4b7f6baa 1063 OUTS (outf, dregs (x));
086134ec 1064 OUTS (outf, " == ");
4b7f6baa 1065 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1066 }
1067 else if (opc == 1 && I == 1 && G == 0)
1068 {
086134ec 1069 OUTS (outf, "CC = ");
4b7f6baa 1070 OUTS (outf, dregs (x));
086134ec 1071 OUTS (outf, " < ");
4b7f6baa 1072 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1073 }
1074 else if (opc == 2 && I == 1 && G == 0)
1075 {
086134ec 1076 OUTS (outf, "CC = ");
4b7f6baa 1077 OUTS (outf, dregs (x));
086134ec 1078 OUTS (outf, " <= ");
4b7f6baa 1079 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1080 }
1081 else if (opc == 3 && I == 1 && G == 0)
1082 {
086134ec 1083 OUTS (outf, "CC = ");
4b7f6baa 1084 OUTS (outf, dregs (x));
086134ec 1085 OUTS (outf, " < ");
4b7f6baa 1086 OUTS (outf, uimm3 (y));
086134ec 1087 OUTS (outf, " (IU)");
4b7f6baa
CM		 1088 }
1089 else if (opc == 4 && I == 1 && G == 0)
1090 {
086134ec 1091 OUTS (outf, "CC = ");
4b7f6baa 1092 OUTS (outf, dregs (x));
086134ec 1093 OUTS (outf, " <= ");
4b7f6baa 1094 OUTS (outf, uimm3 (y));
086134ec 1095 OUTS (outf, " (IU)");
4b7f6baa
CM		 1096 }
1097 else if (opc == 0 && I == 0 && G == 1)
1098 {
086134ec 1099 OUTS (outf, "CC = ");
4b7f6baa 1100 OUTS (outf, pregs (x));
086134ec 1101 OUTS (outf, " == ");
4b7f6baa 1102 OUTS (outf, pregs (y));
4b7f6baa
CM		 1103 }
1104 else if (opc == 1 && I == 0 && G == 1)
1105 {
086134ec 1106 OUTS (outf, "CC = ");
4b7f6baa 1107 OUTS (outf, pregs (x));
086134ec 1108 OUTS (outf, " < ");
4b7f6baa 1109 OUTS (outf, pregs (y));
4b7f6baa
CM		 1110 }
1111 else if (opc == 2 && I == 0 && G == 1)
1112 {
086134ec 1113 OUTS (outf, "CC = ");
4b7f6baa 1114 OUTS (outf, pregs (x));
086134ec 1115 OUTS (outf, " <= ");
4b7f6baa 1116 OUTS (outf, pregs (y));
4b7f6baa
CM		 1117 }
1118 else if (opc == 3 && I == 0 && G == 1)
1119 {
086134ec 1120 OUTS (outf, "CC = ");
4b7f6baa 1121 OUTS (outf, pregs (x));
086134ec 1122 OUTS (outf, " < ");
4b7f6baa 1123 OUTS (outf, pregs (y));
086134ec 1124 OUTS (outf, " (IU)");
4b7f6baa
CM		 1125 }
1126 else if (opc == 4 && I == 0 && G == 1)
1127 {
086134ec 1128 OUTS (outf, "CC = ");
4b7f6baa 1129 OUTS (outf, pregs (x));
086134ec 1130 OUTS (outf, " <= ");
4b7f6baa 1131 OUTS (outf, pregs (y));
086134ec 1132 OUTS (outf, " (IU)");
4b7f6baa
CM		 1133 }
1134 else if (opc == 0 && I == 1 && G == 1)
1135 {
086134ec 1136 OUTS (outf, "CC = ");
4b7f6baa 1137 OUTS (outf, pregs (x));
086134ec 1138 OUTS (outf, " == ");
4b7f6baa 1139 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1140 }
1141 else if (opc == 1 && I == 1 && G == 1)
1142 {
086134ec 1143 OUTS (outf, "CC = ");
4b7f6baa 1144 OUTS (outf, pregs (x));
086134ec 1145 OUTS (outf, " < ");
4b7f6baa 1146 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1147 }
1148 else if (opc == 2 && I == 1 && G == 1)
1149 {
086134ec 1150 OUTS (outf, "CC = ");
4b7f6baa 1151 OUTS (outf, pregs (x));
086134ec 1152 OUTS (outf, " <= ");
4b7f6baa 1153 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1154 }
1155 else if (opc == 3 && I == 1 && G == 1)
1156 {
086134ec 1157 OUTS (outf, "CC = ");
4b7f6baa 1158 OUTS (outf, pregs (x));
086134ec 1159 OUTS (outf, " < ");
4b7f6baa 1160 OUTS (outf, uimm3 (y));
086134ec 1161 OUTS (outf, " (IU)");
4b7f6baa
CM		 1162 }
1163 else if (opc == 4 && I == 1 && G == 1)
1164 {
086134ec 1165 OUTS (outf, "CC = ");
4b7f6baa 1166 OUTS (outf, pregs (x));
086134ec 1167 OUTS (outf, " <= ");
4b7f6baa 1168 OUTS (outf, uimm3 (y));
086134ec 1169 OUTS (outf, " (IU)");
4b7f6baa 1170 }
219b747a 1171 else if (opc == 5 && I == 0 && G == 0 && x == 0 && y == 0)
086134ec 1172 OUTS (outf, "CC = A0 == A1");
b7d48530 1173
219b747a 1174 else if (opc == 6 && I == 0 && G == 0 && x == 0 && y == 0)
086134ec 1175 OUTS (outf, "CC = A0 < A1");
b7d48530 1176
219b747a 1177 else if (opc == 7 && I == 0 && G == 0 && x == 0 && y == 0)
086134ec 1178 OUTS (outf, "CC = A0 <= A1");
b7d48530 1179
4b7f6baa 1180 else
b7d48530
NC		 1181 return 0;
1182 return 2;
4b7f6baa
CM		 1183}
1184
1185static int
1186decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1187{
703ec4e8 1188 struct private *priv = outf->private_data;
b7d48530
NC		 1189 /* CC2dreg
1190 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1191 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1192 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1193 int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1194 int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1195
703ec4e8 1196 if (priv->parallel)
219b747a
MF		 1197 return 0;
1198
4b7f6baa
CM		 1199 if (op == 0)
1200 {
4b7f6baa 1201 OUTS (outf, dregs (reg));
086134ec 1202 OUTS (outf, " = CC");
4b7f6baa
CM		 1203 }
1204 else if (op == 1)
1205 {
086134ec 1206 OUTS (outf, "CC = ");
4b7f6baa 1207 OUTS (outf, dregs (reg));
4b7f6baa 1208 }
50e2162a 1209 else if (op == 3 && reg == 0)
086134ec 1210 OUTS (outf, "CC = !CC");
4b7f6baa 1211 else
b7d48530
NC		 1212 return 0;
1213
1214 return 2;
4b7f6baa
CM		 1215}
1216
1217static int
1218decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1219{
703ec4e8 1220 struct private *priv = outf->private_data;
b7d48530
NC		 1221 /* CC2stat
1222 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1223 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1224 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1225 int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1226 int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1227 int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1228
b2459327 1229 const char *bitname = statbits (cbit);
b3f3b4b0 1230 const char * const op_names[] = { "", "|", "&", "^" } ;
219b747a 1231
703ec4e8 1232 if (priv->parallel)
219b747a
MF		 1233 return 0;
1234
b2459327
MF		 1235 if (decode_statbits[cbit] == REG_LASTREG)
1236 {
1237 /* All ASTAT bits except CC may be operated on in hardware, but may
1238 not have a dedicated insn, so still decode "valid" insns. */
1239 static char bitnames[64];
1240 if (cbit != 5)
1241 sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit);
1242 else
219b747a
MF		 1243 return 0;
1244
b2459327
MF		 1245 bitname = bitnames;
1246 }
1247
b3f3b4b0
MF		 1248 if (D == 0)
1249 OUT (outf, "CC %s= %s", op_names[op], bitname);
4b7f6baa 1250 else
b3f3b4b0 1251 OUT (outf, "%s %s= CC", bitname, op_names[op]);
b7d48530
NC		 1252
1253 return 2;
4b7f6baa
CM		 1254}
1255
1256static int
1257decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1258{
703ec4e8 1259 struct private *priv = outf->private_data;
b7d48530
NC		 1260 /* BRCC
1261 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1262 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1263 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1264 int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1265 int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1266 int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1267
703ec4e8 1268 if (priv->parallel)
219b747a
MF		 1269 return 0;
1270
4b7f6baa
CM		 1271 if (T == 1 && B == 1)
1272 {
086134ec 1273 OUTS (outf, "IF CC JUMP 0x");
4b7f6baa 1274 OUTS (outf, pcrel10 (offset));
086134ec 1275 OUTS (outf, " (BP)");
4b7f6baa
CM		 1276 }
1277 else if (T == 0 && B == 1)
1278 {
086134ec 1279 OUTS (outf, "IF !CC JUMP 0x");
4b7f6baa 1280 OUTS (outf, pcrel10 (offset));
086134ec 1281 OUTS (outf, " (BP)");
4b7f6baa
CM		 1282 }
1283 else if (T == 1)
1284 {
086134ec 1285 OUTS (outf, "IF CC JUMP 0x");
4b7f6baa 1286 OUTS (outf, pcrel10 (offset));
4b7f6baa
CM		 1287 }
1288 else if (T == 0)
1289 {
086134ec 1290 OUTS (outf, "IF !CC JUMP 0x");
4b7f6baa 1291 OUTS (outf, pcrel10 (offset));
4b7f6baa
CM		 1292 }
1293 else
b7d48530
NC		 1294 return 0;
1295
1296 return 2;
4b7f6baa
CM		 1297}
1298
1299static int
1300decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1301{
703ec4e8 1302 struct private *priv = outf->private_data;
b7d48530
NC		 1303 /* UJUMP
1304 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1305 | 0 | 0 | 1 | 0 |.offset........................................|
1306 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1307 int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1308
703ec4e8 1309 if (priv->parallel)
219b747a
MF		 1310 return 0;
1311
086134ec 1312 OUTS (outf, "JUMP.S 0x");
4b7f6baa 1313 OUTS (outf, pcrel12 (offset));
b7d48530 1314 return 2;
4b7f6baa
CM		 1315}
1316
1317static int
1318decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1319{
b7d48530
NC		 1320 /* REGMV
1321 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1322 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1323 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1324 int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1325 int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1326 int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1327 int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1328
602427c4 1329 /* Reserved slots cannot be a src/dst. */
35fc57f3
MF		 1330 if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst))
1331 goto invalid_move;
1332
1333 /* Standard register moves */
1334 if ((gs < 2) || /* Dregs/Pregs as source */
1335 (gd < 2) || /* Dregs/Pregs as dest */
1336 (gs == 4 && src < 4) || /* Accumulators as source */
1337 (gd == 4 && dst < 4 && (gs < 4)) || /* Accumulators as dest */
1338 (gs == 7 && src == 7 && !(gd == 4 && dst < 4)) || /* EMUDAT as src */
1339 (gd == 7 && dst == 7)) /* EMUDAT as dest */
1340 goto valid_move;
1341
1342 /* dareg = dareg (IMBL) */
1343 if (gs < 4 && gd < 4)
1344 goto valid_move;
1345
1346 /* USP can be src to sysregs, but not dagregs. */
1347 if ((gs == 7 && src == 0) && (gd >= 4))
1348 goto valid_move;
1349
1350 /* USP can move between genregs (only check Accumulators). */
1351 if (((gs == 7 && src == 0) && (gd == 4 && dst < 4)) ||
1352 ((gd == 7 && dst == 0) && (gs == 4 && src < 4)))
1353 goto valid_move;
1354
1355 /* Still here ? Invalid reg pair. */
1356 invalid_move:
1357 return 0;
c958a8a8 1358
35fc57f3 1359 valid_move:
4b7f6baa 1360 OUTS (outf, allregs (dst, gd));
086134ec 1361 OUTS (outf, " = ");
4b7f6baa 1362 OUTS (outf, allregs (src, gs));
b7d48530 1363 return 2;
4b7f6baa
CM		 1364}
1365
1366static int
1367decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1368{
b7d48530
NC		 1369 /* ALU2op
1370 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1371 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1372 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1373 int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1374 int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1375 int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1376
1377 if (opc == 0)
1378 {
4b7f6baa 1379 OUTS (outf, dregs (dst));
086134ec 1380 OUTS (outf, " >>>= ");
4b7f6baa 1381 OUTS (outf, dregs (src));
4b7f6baa
CM		 1382 }
1383 else if (opc == 1)
1384 {
4b7f6baa 1385 OUTS (outf, dregs (dst));
086134ec 1386 OUTS (outf, " >>= ");
4b7f6baa 1387 OUTS (outf, dregs (src));
4b7f6baa
CM		 1388 }
1389 else if (opc == 2)
1390 {
4b7f6baa 1391 OUTS (outf, dregs (dst));
086134ec 1392 OUTS (outf, " <<= ");
4b7f6baa 1393 OUTS (outf, dregs (src));
4b7f6baa
CM		 1394 }
1395 else if (opc == 3)
1396 {
4b7f6baa 1397 OUTS (outf, dregs (dst));
086134ec 1398 OUTS (outf, " *= ");
4b7f6baa 1399 OUTS (outf, dregs (src));
4b7f6baa
CM		 1400 }
1401 else if (opc == 4)
1402 {
4b7f6baa 1403 OUTS (outf, dregs (dst));
086134ec 1404 OUTS (outf, " = (");
4b7f6baa 1405 OUTS (outf, dregs (dst));
086134ec 1406 OUTS (outf, " + ");
4b7f6baa 1407 OUTS (outf, dregs (src));
086134ec 1408 OUTS (outf, ") << 0x1");
4b7f6baa
CM		 1409 }
1410 else if (opc == 5)
1411 {
4b7f6baa 1412 OUTS (outf, dregs (dst));
086134ec 1413 OUTS (outf, " = (");
4b7f6baa 1414 OUTS (outf, dregs (dst));
086134ec 1415 OUTS (outf, " + ");
4b7f6baa 1416 OUTS (outf, dregs (src));
086134ec 1417 OUTS (outf, ") << 0x2");
4b7f6baa
CM		 1418 }
1419 else if (opc == 8)
1420 {
086134ec 1421 OUTS (outf, "DIVQ (");
4b7f6baa 1422 OUTS (outf, dregs (dst));
086134ec 1423 OUTS (outf, ", ");
4b7f6baa
CM		 1424 OUTS (outf, dregs (src));
1425 OUTS (outf, ")");
4b7f6baa
CM		 1426 }
1427 else if (opc == 9)
1428 {
086134ec 1429 OUTS (outf, "DIVS (");
4b7f6baa 1430 OUTS (outf, dregs (dst));
086134ec 1431 OUTS (outf, ", ");
4b7f6baa
CM		 1432 OUTS (outf, dregs (src));
1433 OUTS (outf, ")");
4b7f6baa
CM		 1434 }
1435 else if (opc == 10)
1436 {
4b7f6baa 1437 OUTS (outf, dregs (dst));
086134ec 1438 OUTS (outf, " = ");
4b7f6baa 1439 OUTS (outf, dregs_lo (src));
086134ec 1440 OUTS (outf, " (X)");
4b7f6baa
CM		 1441 }
1442 else if (opc == 11)
1443 {
4b7f6baa 1444 OUTS (outf, dregs (dst));
086134ec 1445 OUTS (outf, " = ");
4b7f6baa 1446 OUTS (outf, dregs_lo (src));
086134ec 1447 OUTS (outf, " (Z)");
4b7f6baa
CM		 1448 }
1449 else if (opc == 12)
1450 {
4b7f6baa 1451 OUTS (outf, dregs (dst));
086134ec 1452 OUTS (outf, " = ");
4b7f6baa 1453 OUTS (outf, dregs_byte (src));
086134ec 1454 OUTS (outf, " (X)");
4b7f6baa
CM		 1455 }
1456 else if (opc == 13)
1457 {
4b7f6baa 1458 OUTS (outf, dregs (dst));
086134ec 1459 OUTS (outf, " = ");
4b7f6baa 1460 OUTS (outf, dregs_byte (src));
086134ec 1461 OUTS (outf, " (Z)");
4b7f6baa
CM		 1462 }
1463 else if (opc == 14)
1464 {
4b7f6baa 1465 OUTS (outf, dregs (dst));
086134ec 1466 OUTS (outf, " = -");
4b7f6baa 1467 OUTS (outf, dregs (src));
4b7f6baa
CM		 1468 }
1469 else if (opc == 15)
1470 {
4b7f6baa 1471 OUTS (outf, dregs (dst));
086134ec 1472 OUTS (outf, " =~ ");
4b7f6baa 1473 OUTS (outf, dregs (src));
4b7f6baa
CM		 1474 }
1475 else
b7d48530
NC		 1476 return 0;
1477
1478 return 2;
4b7f6baa
CM		 1479}
1480
1481static int
1482decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1483{
b7d48530
NC		 1484 /* PTR2op
1485 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1486 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1487 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1488 int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1489 int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1490 int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1491
1492 if (opc == 0)
1493 {
4b7f6baa 1494 OUTS (outf, pregs (dst));
086134ec 1495 OUTS (outf, " -= ");
4b7f6baa 1496 OUTS (outf, pregs (src));
4b7f6baa
CM		 1497 }
1498 else if (opc == 1)
1499 {
4b7f6baa 1500 OUTS (outf, pregs (dst));
086134ec 1501 OUTS (outf, " = ");
4b7f6baa 1502 OUTS (outf, pregs (src));
086134ec 1503 OUTS (outf, " << 0x2");
4b7f6baa
CM		 1504 }
1505 else if (opc == 3)
1506 {
4b7f6baa 1507 OUTS (outf, pregs (dst));
086134ec 1508 OUTS (outf, " = ");
4b7f6baa 1509 OUTS (outf, pregs (src));
086134ec 1510 OUTS (outf, " >> 0x2");
4b7f6baa
CM		 1511 }
1512 else if (opc == 4)
1513 {
4b7f6baa 1514 OUTS (outf, pregs (dst));
086134ec 1515 OUTS (outf, " = ");
4b7f6baa 1516 OUTS (outf, pregs (src));
086134ec 1517 OUTS (outf, " >> 0x1");
4b7f6baa
CM		 1518 }
1519 else if (opc == 5)
1520 {
4b7f6baa 1521 OUTS (outf, pregs (dst));
086134ec 1522 OUTS (outf, " += ");
4b7f6baa 1523 OUTS (outf, pregs (src));
086134ec 1524 OUTS (outf, " (BREV)");
4b7f6baa
CM		 1525 }
1526 else if (opc == 6)
1527 {
4b7f6baa 1528 OUTS (outf, pregs (dst));
086134ec 1529 OUTS (outf, " = (");
4b7f6baa 1530 OUTS (outf, pregs (dst));
086134ec 1531 OUTS (outf, " + ");
4b7f6baa 1532 OUTS (outf, pregs (src));
086134ec 1533 OUTS (outf, ") << 0x1");
4b7f6baa
CM		 1534 }
1535 else if (opc == 7)
1536 {
4b7f6baa 1537 OUTS (outf, pregs (dst));
086134ec 1538 OUTS (outf, " = (");
4b7f6baa 1539 OUTS (outf, pregs (dst));
086134ec 1540 OUTS (outf, " + ");
4b7f6baa 1541 OUTS (outf, pregs (src));
086134ec 1542 OUTS (outf, ") << 0x2");
4b7f6baa
CM		 1543 }
1544 else
b7d48530
NC		 1545 return 0;
1546
1547 return 2;
4b7f6baa
CM		 1548}
1549
1550static int
1551decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1552{
703ec4e8 1553 struct private *priv = outf->private_data;
b7d48530
NC		 1554 /* LOGI2op
1555 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1556 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1557 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1558 int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1559 int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1560 int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1561
703ec4e8 1562 if (priv->parallel)
219b747a
MF		 1563 return 0;
1564
4b7f6baa
CM		 1565 if (opc == 0)
1566 {
086134ec 1567 OUTS (outf, "CC = !BITTST (");
4b7f6baa 1568 OUTS (outf, dregs (dst));
086134ec 1569 OUTS (outf, ", ");
4b7f6baa 1570 OUTS (outf, uimm5 (src));
086134ec
BS		 1571 OUTS (outf, ");\t\t/* bit");
1572 OUTS (outf, imm7d (src));
1573 OUTS (outf, " */");
60ac5798 1574 priv->comment = TRUE;
4b7f6baa
CM		 1575 }
1576 else if (opc == 1)
1577 {
4b7f6baa
CM		 1578 OUTS (outf, "CC = BITTST (");
1579 OUTS (outf, dregs (dst));
086134ec 1580 OUTS (outf, ", ");
4b7f6baa 1581 OUTS (outf, uimm5 (src));
086134ec
BS		 1582 OUTS (outf, ");\t\t/* bit");
1583 OUTS (outf, imm7d (src));
1584 OUTS (outf, " */");
60ac5798 1585 priv->comment = TRUE;
4b7f6baa
CM		 1586 }
1587 else if (opc == 2)
1588 {
4b7f6baa
CM		 1589 OUTS (outf, "BITSET (");
1590 OUTS (outf, dregs (dst));
086134ec 1591 OUTS (outf, ", ");
4b7f6baa 1592 OUTS (outf, uimm5 (src));
086134ec
BS		 1593 OUTS (outf, ");\t\t/* bit");
1594 OUTS (outf, imm7d (src));
1595 OUTS (outf, " */");
60ac5798 1596 priv->comment = TRUE;
4b7f6baa
CM		 1597 }
1598 else if (opc == 3)
1599 {
4b7f6baa
CM		 1600 OUTS (outf, "BITTGL (");
1601 OUTS (outf, dregs (dst));
086134ec 1602 OUTS (outf, ", ");
4b7f6baa 1603 OUTS (outf, uimm5 (src));
086134ec
BS		 1604 OUTS (outf, ");\t\t/* bit");
1605 OUTS (outf, imm7d (src));
1606 OUTS (outf, " */");
60ac5798 1607 priv->comment = TRUE;
4b7f6baa
CM		 1608 }
1609 else if (opc == 4)
1610 {
4b7f6baa
CM		 1611 OUTS (outf, "BITCLR (");
1612 OUTS (outf, dregs (dst));
086134ec 1613 OUTS (outf, ", ");
4b7f6baa 1614 OUTS (outf, uimm5 (src));
086134ec
BS		 1615 OUTS (outf, ");\t\t/* bit");
1616 OUTS (outf, imm7d (src));
1617 OUTS (outf, " */");
60ac5798 1618 priv->comment = TRUE;
4b7f6baa
CM		 1619 }
1620 else if (opc == 5)
1621 {
4b7f6baa 1622 OUTS (outf, dregs (dst));
086134ec 1623 OUTS (outf, " >>>= ");
4b7f6baa 1624 OUTS (outf, uimm5 (src));
4b7f6baa
CM		 1625 }
1626 else if (opc == 6)
1627 {
4b7f6baa 1628 OUTS (outf, dregs (dst));
086134ec 1629 OUTS (outf, " >>= ");
4b7f6baa 1630 OUTS (outf, uimm5 (src));
4b7f6baa
CM		 1631 }
1632 else if (opc == 7)
1633 {
4b7f6baa 1634 OUTS (outf, dregs (dst));
086134ec 1635 OUTS (outf, " <<= ");
4b7f6baa 1636 OUTS (outf, uimm5 (src));
4b7f6baa
CM		 1637 }
1638 else
b7d48530
NC		 1639 return 0;
1640
1641 return 2;
4b7f6baa
CM		 1642}
1643
1644static int
1645decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1646{
b7d48530
NC		 1647 /* COMP3op
1648 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1649 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1650 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1651 int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1652 int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1653 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1654 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1655
1656 if (opc == 5 && src1 == src0)
1657 {
4b7f6baa 1658 OUTS (outf, pregs (dst));
086134ec 1659 OUTS (outf, " = ");
4b7f6baa 1660 OUTS (outf, pregs (src0));
086134ec 1661 OUTS (outf, " << 0x1");
4b7f6baa
CM		 1662 }
1663 else if (opc == 1)
1664 {
4b7f6baa 1665 OUTS (outf, dregs (dst));
086134ec 1666 OUTS (outf, " = ");
4b7f6baa 1667 OUTS (outf, dregs (src0));
086134ec 1668 OUTS (outf, " - ");
4b7f6baa 1669 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1670 }
1671 else if (opc == 2)
1672 {
4b7f6baa 1673 OUTS (outf, dregs (dst));
086134ec 1674 OUTS (outf, " = ");
4b7f6baa 1675 OUTS (outf, dregs (src0));
086134ec 1676 OUTS (outf, " & ");
4b7f6baa 1677 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1678 }
1679 else if (opc == 3)
1680 {
4b7f6baa 1681 OUTS (outf, dregs (dst));
086134ec 1682 OUTS (outf, " = ");
4b7f6baa 1683 OUTS (outf, dregs (src0));
086134ec 1684 OUTS (outf, " | ");
4b7f6baa 1685 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1686 }
1687 else if (opc == 4)
1688 {
4b7f6baa 1689 OUTS (outf, dregs (dst));
086134ec 1690 OUTS (outf, " = ");
4b7f6baa 1691 OUTS (outf, dregs (src0));
086134ec 1692 OUTS (outf, " ^ ");
4b7f6baa 1693 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1694 }
1695 else if (opc == 5)
1696 {
4b7f6baa 1697 OUTS (outf, pregs (dst));
086134ec 1698 OUTS (outf, " = ");
4b7f6baa 1699 OUTS (outf, pregs (src0));
086134ec 1700 OUTS (outf, " + ");
4b7f6baa 1701 OUTS (outf, pregs (src1));
4b7f6baa
CM		 1702 }
1703 else if (opc == 6)
1704 {
4b7f6baa 1705 OUTS (outf, pregs (dst));
086134ec 1706 OUTS (outf, " = ");
4b7f6baa 1707 OUTS (outf, pregs (src0));
086134ec 1708 OUTS (outf, " + (");
4b7f6baa 1709 OUTS (outf, pregs (src1));
086134ec 1710 OUTS (outf, " << 0x1)");
4b7f6baa
CM		 1711 }
1712 else if (opc == 7)
1713 {
4b7f6baa 1714 OUTS (outf, pregs (dst));
086134ec 1715 OUTS (outf, " = ");
4b7f6baa 1716 OUTS (outf, pregs (src0));
086134ec 1717 OUTS (outf, " + (");
4b7f6baa 1718 OUTS (outf, pregs (src1));
086134ec 1719 OUTS (outf, " << 0x2)");
4b7f6baa
CM		 1720 }
1721 else if (opc == 0)
1722 {
4b7f6baa 1723 OUTS (outf, dregs (dst));
086134ec 1724 OUTS (outf, " = ");
4b7f6baa 1725 OUTS (outf, dregs (src0));
086134ec 1726 OUTS (outf, " + ");
4b7f6baa 1727 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1728 }
1729 else
b7d48530
NC		 1730 return 0;
1731
1732 return 2;
4b7f6baa
CM		 1733}
1734
1735static int
1736decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1737{
703ec4e8 1738 struct private *priv = outf->private_data;
b7d48530
NC		 1739 /* COMPI2opD
1740 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1741 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1742 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1743 int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1744 int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1745 int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1746
086134ec
BS		 1747 bu32 *pval = get_allreg (0, dst);
1748
703ec4e8 1749 if (priv->parallel)
219b747a
MF		 1750 return 0;
1751
086134ec
BS		 1752 /* Since we don't have 32-bit immediate loads, we allow the disassembler
1753 to combine them, so it prints out the right values.
1754 Here we keep track of the registers. */
1755 if (op == 0)
1756 {
1757 *pval = imm7_val (src);
1758 if (src & 0x40)
1759 *pval |= 0xFFFFFF80;
1760 else
1761 *pval &= 0x7F;
1762 }
1763
4b7f6baa
CM		 1764 if (op == 0)
1765 {
4b7f6baa 1766 OUTS (outf, dregs (dst));
086134ec 1767 OUTS (outf, " = ");
4b7f6baa 1768 OUTS (outf, imm7 (src));
086134ec
BS		 1769 OUTS (outf, " (X);\t\t/*\t\t");
1770 OUTS (outf, dregs (dst));
1771 OUTS (outf, "=");
1772 OUTS (outf, uimm32 (*pval));
1773 OUTS (outf, "(");
1774 OUTS (outf, imm32 (*pval));
1775 OUTS (outf, ") */");
60ac5798 1776 priv->comment = TRUE;
4b7f6baa
CM		 1777 }
1778 else if (op == 1)
1779 {
4b7f6baa 1780 OUTS (outf, dregs (dst));
086134ec 1781 OUTS (outf, " += ");
4b7f6baa 1782 OUTS (outf, imm7 (src));
086134ec
BS		 1783 OUTS (outf, ";\t\t/* (");
1784 OUTS (outf, imm7d (src));
1785 OUTS (outf, ") */");
60ac5798 1786 priv->comment = TRUE;
4b7f6baa
CM		 1787 }
1788 else
b7d48530
NC		 1789 return 0;
1790
1791 return 2;
4b7f6baa
CM		 1792}
1793
1794static int
1795decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1796{
703ec4e8 1797 struct private *priv = outf->private_data;
b7d48530
NC		 1798 /* COMPI2opP
1799 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1800 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1801 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1802 int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1803 int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1804 int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1805
086134ec
BS		 1806 bu32 *pval = get_allreg (1, dst);
1807
703ec4e8 1808 if (priv->parallel)
219b747a
MF		 1809 return 0;
1810
086134ec
BS		 1811 if (op == 0)
1812 {
1813 *pval = imm7_val (src);
1814 if (src & 0x40)
1815 *pval |= 0xFFFFFF80;
1816 else
1817 *pval &= 0x7F;
1818 }
1819
4b7f6baa
CM		 1820 if (op == 0)
1821 {
4b7f6baa 1822 OUTS (outf, pregs (dst));
086134ec 1823 OUTS (outf, " = ");
4b7f6baa 1824 OUTS (outf, imm7 (src));
086134ec
BS		 1825 OUTS (outf, " (X);\t\t/*\t\t");
1826 OUTS (outf, pregs (dst));
1827 OUTS (outf, "=");
1828 OUTS (outf, uimm32 (*pval));
1829 OUTS (outf, "(");
1830 OUTS (outf, imm32 (*pval));
1831 OUTS (outf, ") */");
60ac5798 1832 priv->comment = TRUE;
4b7f6baa
CM		 1833 }
1834 else if (op == 1)
1835 {
4b7f6baa 1836 OUTS (outf, pregs (dst));
086134ec 1837 OUTS (outf, " += ");
4b7f6baa 1838 OUTS (outf, imm7 (src));
086134ec
BS		 1839 OUTS (outf, ";\t\t/* (");
1840 OUTS (outf, imm7d (src));
1841 OUTS (outf, ") */");
60ac5798 1842 priv->comment = TRUE;
4b7f6baa
CM		 1843 }
1844 else
b7d48530
NC		 1845 return 0;
1846
1847 return 2;
4b7f6baa
CM		 1848}
1849
1850static int
1851decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1852{
b7d48530
NC		 1853 /* LDSTpmod
1854 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1855 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1856 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1857 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1858 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1859 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1860 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1861 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1862
1863 if (aop == 1 && W == 0 && idx == ptr)
1864 {
4b7f6baa 1865 OUTS (outf, dregs_lo (reg));
086134ec 1866 OUTS (outf, " = W[");
4b7f6baa
CM		 1867 OUTS (outf, pregs (ptr));
1868 OUTS (outf, "]");
4b7f6baa
CM		 1869 }
1870 else if (aop == 2 && W == 0 && idx == ptr)
1871 {
4b7f6baa 1872 OUTS (outf, dregs_hi (reg));
086134ec 1873 OUTS (outf, " = W[");
4b7f6baa
CM		 1874 OUTS (outf, pregs (ptr));
1875 OUTS (outf, "]");
4b7f6baa
CM		 1876 }
1877 else if (aop == 1 && W == 1 && idx == ptr)
1878 {
4b7f6baa
CM		 1879 OUTS (outf, "W[");
1880 OUTS (outf, pregs (ptr));
086134ec 1881 OUTS (outf, "] = ");
4b7f6baa 1882 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 1883 }
1884 else if (aop == 2 && W == 1 && idx == ptr)
1885 {
4b7f6baa
CM		 1886 OUTS (outf, "W[");
1887 OUTS (outf, pregs (ptr));
086134ec 1888 OUTS (outf, "] = ");
4b7f6baa 1889 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 1890 }
1891 else if (aop == 0 && W == 0)
1892 {
4b7f6baa 1893 OUTS (outf, dregs (reg));
086134ec 1894 OUTS (outf, " = [");
4b7f6baa 1895 OUTS (outf, pregs (ptr));
086134ec 1896 OUTS (outf, " ++ ");
4b7f6baa
CM		 1897 OUTS (outf, pregs (idx));
1898 OUTS (outf, "]");
4b7f6baa
CM		 1899 }
1900 else if (aop == 1 && W == 0)
1901 {
4b7f6baa 1902 OUTS (outf, dregs_lo (reg));
086134ec 1903 OUTS (outf, " = W[");
4b7f6baa 1904 OUTS (outf, pregs (ptr));
086134ec 1905 OUTS (outf, " ++ ");
4b7f6baa
CM		 1906 OUTS (outf, pregs (idx));
1907 OUTS (outf, "]");
4b7f6baa
CM		 1908 }
1909 else if (aop == 2 && W == 0)
1910 {
4b7f6baa 1911 OUTS (outf, dregs_hi (reg));
086134ec 1912 OUTS (outf, " = W[");
4b7f6baa 1913 OUTS (outf, pregs (ptr));
086134ec 1914 OUTS (outf, " ++ ");
4b7f6baa
CM		 1915 OUTS (outf, pregs (idx));
1916 OUTS (outf, "]");
4b7f6baa
CM		 1917 }
1918 else if (aop == 3 && W == 0)
1919 {
4b7f6baa 1920 OUTS (outf, dregs (reg));
086134ec 1921 OUTS (outf, " = W[");
4b7f6baa 1922 OUTS (outf, pregs (ptr));
086134ec 1923 OUTS (outf, " ++ ");
4b7f6baa
CM		 1924 OUTS (outf, pregs (idx));
1925 OUTS (outf, "] (Z)");
4b7f6baa
CM		 1926 }
1927 else if (aop == 3 && W == 1)
1928 {
4b7f6baa 1929 OUTS (outf, dregs (reg));
086134ec 1930 OUTS (outf, " = W[");
4b7f6baa 1931 OUTS (outf, pregs (ptr));
086134ec 1932 OUTS (outf, " ++ ");
4b7f6baa 1933 OUTS (outf, pregs (idx));
086134ec 1934 OUTS (outf, "] (X)");
4b7f6baa
CM		 1935 }
1936 else if (aop == 0 && W == 1)
1937 {
4b7f6baa
CM		 1938 OUTS (outf, "[");
1939 OUTS (outf, pregs (ptr));
086134ec 1940 OUTS (outf, " ++ ");
4b7f6baa 1941 OUTS (outf, pregs (idx));
086134ec 1942 OUTS (outf, "] = ");
4b7f6baa 1943 OUTS (outf, dregs (reg));
4b7f6baa
CM		 1944 }
1945 else if (aop == 1 && W == 1)
1946 {
4b7f6baa
CM		 1947 OUTS (outf, "W[");
1948 OUTS (outf, pregs (ptr));
086134ec 1949 OUTS (outf, " ++ ");
4b7f6baa 1950 OUTS (outf, pregs (idx));
086134ec 1951 OUTS (outf, "] = ");
4b7f6baa 1952 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 1953 }
1954 else if (aop == 2 && W == 1)
1955 {
4b7f6baa
CM		 1956 OUTS (outf, "W[");
1957 OUTS (outf, pregs (ptr));
086134ec 1958 OUTS (outf, " ++ ");
4b7f6baa 1959 OUTS (outf, pregs (idx));
086134ec 1960 OUTS (outf, "] = ");
4b7f6baa 1961 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 1962 }
1963 else
b7d48530
NC		 1964 return 0;
1965
1966 return 2;
4b7f6baa
CM		 1967}
1968
1969static int
1970decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
1971{
b7d48530
NC		 1972 /* dagMODim
1973 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1974 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
1975 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1976 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
1977 int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
1978 int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
1979 int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
1980
1981 if (op == 0 && br == 1)
1982 {
4b7f6baa 1983 OUTS (outf, iregs (i));
086134ec 1984 OUTS (outf, " += ");
4b7f6baa 1985 OUTS (outf, mregs (m));
086134ec 1986 OUTS (outf, " (BREV)");
4b7f6baa
CM		 1987 }
1988 else if (op == 0)
1989 {
4b7f6baa 1990 OUTS (outf, iregs (i));
086134ec 1991 OUTS (outf, " += ");
4b7f6baa 1992 OUTS (outf, mregs (m));
4b7f6baa 1993 }
219b747a 1994 else if (op == 1 && br == 0)
4b7f6baa 1995 {
4b7f6baa 1996 OUTS (outf, iregs (i));
086134ec 1997 OUTS (outf, " -= ");
4b7f6baa 1998 OUTS (outf, mregs (m));
4b7f6baa
CM		 1999 }
2000 else
b7d48530
NC		 2001 return 0;
2002
2003 return 2;
4b7f6baa
CM		 2004}
2005
2006static int
2007decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
2008{
703ec4e8 2009 struct private *priv = outf->private_data;
b7d48530
NC		 2010 /* dagMODik
2011 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2012 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2013 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2014 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2015 int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
2016
2017 if (op == 0)
2018 {
4b7f6baa 2019 OUTS (outf, iregs (i));
086134ec 2020 OUTS (outf, " += 0x2");
4b7f6baa
CM		 2021 }
2022 else if (op == 1)
2023 {
4b7f6baa 2024 OUTS (outf, iregs (i));
086134ec 2025 OUTS (outf, " -= 0x2");
4b7f6baa
CM		 2026 }
2027 else if (op == 2)
2028 {
4b7f6baa 2029 OUTS (outf, iregs (i));
086134ec 2030 OUTS (outf, " += 0x4");
4b7f6baa
CM		 2031 }
2032 else if (op == 3)
2033 {
4b7f6baa 2034 OUTS (outf, iregs (i));
086134ec 2035 OUTS (outf, " -= 0x4");
4b7f6baa
CM		 2036 }
2037 else
b7d48530
NC		 2038 return 0;
2039
703ec4e8 2040 if (!priv->parallel)
602427c4
MF		 2041 {
2042 OUTS (outf, ";\t\t/* ( ");
2043 if (op == 0 || op == 1)
2044 OUTS (outf, "2");
2045 else if (op == 2 || op == 3)
086134ec 2046 OUTS (outf, "4");
602427c4 2047 OUTS (outf, ") */");
60ac5798 2048 priv->comment = TRUE;
602427c4 2049 }
086134ec 2050
b7d48530 2051 return 2;
4b7f6baa
CM		 2052}
2053
2054static int
2055decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2056{
b7d48530
NC		 2057 /* dspLDST
2058 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2059 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2060 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2061 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2062 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2063 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2064 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2065 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2066
2067 if (aop == 0 && W == 0 && m == 0)
2068 {
4b7f6baa 2069 OUTS (outf, dregs (reg));
086134ec 2070 OUTS (outf, " = [");
4b7f6baa
CM		 2071 OUTS (outf, iregs (i));
2072 OUTS (outf, "++]");
4b7f6baa
CM		 2073 }
2074 else if (aop == 0 && W == 0 && m == 1)
2075 {
4b7f6baa 2076 OUTS (outf, dregs_lo (reg));
086134ec 2077 OUTS (outf, " = W[");
4b7f6baa
CM		 2078 OUTS (outf, iregs (i));
2079 OUTS (outf, "++]");
4b7f6baa
CM		 2080 }
2081 else if (aop == 0 && W == 0 && m == 2)
2082 {
4b7f6baa 2083 OUTS (outf, dregs_hi (reg));
086134ec 2084 OUTS (outf, " = W[");
4b7f6baa
CM		 2085 OUTS (outf, iregs (i));
2086 OUTS (outf, "++]");
4b7f6baa
CM		 2087 }
2088 else if (aop == 1 && W == 0 && m == 0)
2089 {
4b7f6baa 2090 OUTS (outf, dregs (reg));
086134ec 2091 OUTS (outf, " = [");
4b7f6baa
CM		 2092 OUTS (outf, iregs (i));
2093 OUTS (outf, "--]");
4b7f6baa
CM		 2094 }
2095 else if (aop == 1 && W == 0 && m == 1)
2096 {
4b7f6baa 2097 OUTS (outf, dregs_lo (reg));
086134ec 2098 OUTS (outf, " = W[");
4b7f6baa
CM		 2099 OUTS (outf, iregs (i));
2100 OUTS (outf, "--]");
4b7f6baa
CM		 2101 }
2102 else if (aop == 1 && W == 0 && m == 2)
2103 {
4b7f6baa 2104 OUTS (outf, dregs_hi (reg));
086134ec 2105 OUTS (outf, " = W[");
4b7f6baa
CM		 2106 OUTS (outf, iregs (i));
2107 OUTS (outf, "--]");
4b7f6baa
CM		 2108 }
2109 else if (aop == 2 && W == 0 && m == 0)
2110 {
4b7f6baa 2111 OUTS (outf, dregs (reg));
086134ec 2112 OUTS (outf, " = [");
4b7f6baa
CM		 2113 OUTS (outf, iregs (i));
2114 OUTS (outf, "]");
4b7f6baa
CM		 2115 }
2116 else if (aop == 2 && W == 0 && m == 1)
2117 {
4b7f6baa 2118 OUTS (outf, dregs_lo (reg));
086134ec 2119 OUTS (outf, " = W[");
4b7f6baa
CM		 2120 OUTS (outf, iregs (i));
2121 OUTS (outf, "]");
4b7f6baa
CM		 2122 }
2123 else if (aop == 2 && W == 0 && m == 2)
2124 {
4b7f6baa 2125 OUTS (outf, dregs_hi (reg));
086134ec 2126 OUTS (outf, " = W[");
4b7f6baa
CM		 2127 OUTS (outf, iregs (i));
2128 OUTS (outf, "]");
4b7f6baa
CM		 2129 }
2130 else if (aop == 0 && W == 1 && m == 0)
2131 {
4b7f6baa
CM		 2132 OUTS (outf, "[");
2133 OUTS (outf, iregs (i));
086134ec 2134 OUTS (outf, "++] = ");
4b7f6baa 2135 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2136 }
2137 else if (aop == 0 && W == 1 && m == 1)
2138 {
4b7f6baa
CM		 2139 OUTS (outf, "W[");
2140 OUTS (outf, iregs (i));
086134ec 2141 OUTS (outf, "++] = ");
4b7f6baa 2142 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 2143 }
2144 else if (aop == 0 && W == 1 && m == 2)
2145 {
4b7f6baa
CM		 2146 OUTS (outf, "W[");
2147 OUTS (outf, iregs (i));
086134ec 2148 OUTS (outf, "++] = ");
4b7f6baa 2149 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 2150 }
2151 else if (aop == 1 && W == 1 && m == 0)
2152 {
4b7f6baa
CM		 2153 OUTS (outf, "[");
2154 OUTS (outf, iregs (i));
086134ec 2155 OUTS (outf, "--] = ");
4b7f6baa 2156 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2157 }
2158 else if (aop == 1 && W == 1 && m == 1)
2159 {
4b7f6baa
CM		 2160 OUTS (outf, "W[");
2161 OUTS (outf, iregs (i));
086134ec 2162 OUTS (outf, "--] = ");
4b7f6baa 2163 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 2164 }
2165 else if (aop == 1 && W == 1 && m == 2)
2166 {
4b7f6baa
CM		 2167 OUTS (outf, "W[");
2168 OUTS (outf, iregs (i));
086134ec 2169 OUTS (outf, "--] = ");
4b7f6baa 2170 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 2171 }
2172 else if (aop == 2 && W == 1 && m == 0)
2173 {
4b7f6baa
CM		 2174 OUTS (outf, "[");
2175 OUTS (outf, iregs (i));
086134ec 2176 OUTS (outf, "] = ");
4b7f6baa 2177 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2178 }
2179 else if (aop == 2 && W == 1 && m == 1)
2180 {
4b7f6baa
CM		 2181 OUTS (outf, "W[");
2182 OUTS (outf, iregs (i));
086134ec 2183 OUTS (outf, "] = ");
4b7f6baa 2184 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 2185 }
2186 else if (aop == 2 && W == 1 && m == 2)
2187 {
4b7f6baa
CM		 2188 OUTS (outf, "W[");
2189 OUTS (outf, iregs (i));
086134ec 2190 OUTS (outf, "] = ");
4b7f6baa 2191 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 2192 }
2193 else if (aop == 3 && W == 0)
2194 {
4b7f6baa 2195 OUTS (outf, dregs (reg));
086134ec 2196 OUTS (outf, " = [");
4b7f6baa 2197 OUTS (outf, iregs (i));
086134ec 2198 OUTS (outf, " ++ ");
4b7f6baa
CM		 2199 OUTS (outf, mregs (m));
2200 OUTS (outf, "]");
4b7f6baa
CM		 2201 }
2202 else if (aop == 3 && W == 1)
2203 {
4b7f6baa
CM		 2204 OUTS (outf, "[");
2205 OUTS (outf, iregs (i));
086134ec 2206 OUTS (outf, " ++ ");
4b7f6baa 2207 OUTS (outf, mregs (m));
086134ec 2208 OUTS (outf, "] = ");
4b7f6baa 2209 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2210 }
2211 else
b7d48530
NC		 2212 return 0;
2213
2214 return 2;
4b7f6baa
CM		 2215}
2216
2217static int
2218decode_LDST_0 (TIword iw0, disassemble_info *outf)
2219{
b7d48530
NC		 2220 /* LDST
2221 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2222 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2223 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2224 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2225 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2226 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2227 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2228 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2229 int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2230
2231 if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2232 {
4b7f6baa 2233 OUTS (outf, dregs (reg));
086134ec 2234 OUTS (outf, " = [");
4b7f6baa
CM		 2235 OUTS (outf, pregs (ptr));
2236 OUTS (outf, "++]");
4b7f6baa 2237 }
219b747a 2238 else if (aop == 0 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
4b7f6baa 2239 {
4b7f6baa 2240 OUTS (outf, pregs (reg));
086134ec 2241 OUTS (outf, " = [");
4b7f6baa
CM		 2242 OUTS (outf, pregs (ptr));
2243 OUTS (outf, "++]");
4b7f6baa
CM		 2244 }
2245 else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2246 {
4b7f6baa 2247 OUTS (outf, dregs (reg));
086134ec 2248 OUTS (outf, " = W[");
4b7f6baa
CM		 2249 OUTS (outf, pregs (ptr));
2250 OUTS (outf, "++] (Z)");
4b7f6baa
CM		 2251 }
2252 else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2253 {
4b7f6baa 2254 OUTS (outf, dregs (reg));
086134ec 2255 OUTS (outf, " = W[");
4b7f6baa 2256 OUTS (outf, pregs (ptr));
086134ec 2257 OUTS (outf, "++] (X)");
4b7f6baa
CM		 2258 }
2259 else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2260 {
4b7f6baa 2261 OUTS (outf, dregs (reg));
086134ec 2262 OUTS (outf, " = B[");
4b7f6baa
CM		 2263 OUTS (outf, pregs (ptr));
2264 OUTS (outf, "++] (Z)");
4b7f6baa
CM		 2265 }
2266 else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2267 {
4b7f6baa 2268 OUTS (outf, dregs (reg));
086134ec 2269 OUTS (outf, " = B[");
4b7f6baa 2270 OUTS (outf, pregs (ptr));
086134ec 2271 OUTS (outf, "++] (X)");
4b7f6baa
CM		 2272 }
2273 else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2274 {
4b7f6baa 2275 OUTS (outf, dregs (reg));
086134ec 2276 OUTS (outf, " = [");
4b7f6baa
CM		 2277 OUTS (outf, pregs (ptr));
2278 OUTS (outf, "--]");
4b7f6baa 2279 }
219b747a 2280 else if (aop == 1 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
4b7f6baa 2281 {
4b7f6baa 2282 OUTS (outf, pregs (reg));
086134ec 2283 OUTS (outf, " = [");
4b7f6baa
CM		 2284 OUTS (outf, pregs (ptr));
2285 OUTS (outf, "--]");
4b7f6baa
CM		 2286 }
2287 else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2288 {
4b7f6baa 2289 OUTS (outf, dregs (reg));
086134ec 2290 OUTS (outf, " = W[");
4b7f6baa
CM		 2291 OUTS (outf, pregs (ptr));
2292 OUTS (outf, "--] (Z)");
4b7f6baa
CM		 2293 }
2294 else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2295 {
4b7f6baa 2296 OUTS (outf, dregs (reg));
086134ec 2297 OUTS (outf, " = W[");
4b7f6baa 2298 OUTS (outf, pregs (ptr));
086134ec 2299 OUTS (outf, "--] (X)");
4b7f6baa
CM		 2300 }
2301 else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2302 {
4b7f6baa 2303 OUTS (outf, dregs (reg));
086134ec 2304 OUTS (outf, " = B[");
4b7f6baa
CM		 2305 OUTS (outf, pregs (ptr));
2306 OUTS (outf, "--] (Z)");
4b7f6baa
CM		 2307 }
2308 else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2309 {
4b7f6baa 2310 OUTS (outf, dregs (reg));
086134ec 2311 OUTS (outf, " = B[");
4b7f6baa 2312 OUTS (outf, pregs (ptr));
086134ec 2313 OUTS (outf, "--] (X)");
4b7f6baa
CM		 2314 }
2315 else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2316 {
4b7f6baa 2317 OUTS (outf, dregs (reg));
086134ec 2318 OUTS (outf, " = [");
4b7f6baa
CM		 2319 OUTS (outf, pregs (ptr));
2320 OUTS (outf, "]");
4b7f6baa
CM		 2321 }
2322 else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2323 {
4b7f6baa 2324 OUTS (outf, pregs (reg));
086134ec 2325 OUTS (outf, " = [");
4b7f6baa
CM		 2326 OUTS (outf, pregs (ptr));
2327 OUTS (outf, "]");
4b7f6baa
CM		 2328 }
2329 else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2330 {
4b7f6baa 2331 OUTS (outf, dregs (reg));
086134ec 2332 OUTS (outf, " = W[");
4b7f6baa
CM		 2333 OUTS (outf, pregs (ptr));
2334 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2335 }
2336 else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2337 {
4b7f6baa 2338 OUTS (outf, dregs (reg));
086134ec 2339 OUTS (outf, " = W[");
4b7f6baa 2340 OUTS (outf, pregs (ptr));
086134ec 2341 OUTS (outf, "] (X)");
4b7f6baa
CM		 2342 }
2343 else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2344 {
4b7f6baa 2345 OUTS (outf, dregs (reg));
086134ec 2346 OUTS (outf, " = B[");
4b7f6baa
CM		 2347 OUTS (outf, pregs (ptr));
2348 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2349 }
2350 else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2351 {
4b7f6baa 2352 OUTS (outf, dregs (reg));
086134ec 2353 OUTS (outf, " = B[");
4b7f6baa 2354 OUTS (outf, pregs (ptr));
086134ec 2355 OUTS (outf, "] (X)");
4b7f6baa
CM		 2356 }
2357 else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2358 {
4b7f6baa
CM		 2359 OUTS (outf, "[");
2360 OUTS (outf, pregs (ptr));
086134ec 2361 OUTS (outf, "++] = ");
4b7f6baa 2362 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2363 }
2364 else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2365 {
4b7f6baa
CM		 2366 OUTS (outf, "[");
2367 OUTS (outf, pregs (ptr));
086134ec 2368 OUTS (outf, "++] = ");
4b7f6baa 2369 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2370 }
2371 else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2372 {
4b7f6baa
CM		 2373 OUTS (outf, "W[");
2374 OUTS (outf, pregs (ptr));
086134ec 2375 OUTS (outf, "++] = ");
4b7f6baa 2376 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2377 }
2378 else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2379 {
4b7f6baa
CM		 2380 OUTS (outf, "B[");
2381 OUTS (outf, pregs (ptr));
086134ec 2382 OUTS (outf, "++] = ");
4b7f6baa 2383 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2384 }
2385 else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2386 {
4b7f6baa
CM		 2387 OUTS (outf, "[");
2388 OUTS (outf, pregs (ptr));
086134ec 2389 OUTS (outf, "--] = ");
4b7f6baa 2390 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2391 }
2392 else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2393 {
4b7f6baa
CM		 2394 OUTS (outf, "[");
2395 OUTS (outf, pregs (ptr));
086134ec 2396 OUTS (outf, "--] = ");
4b7f6baa 2397 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2398 }
2399 else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2400 {
4b7f6baa
CM		 2401 OUTS (outf, "W[");
2402 OUTS (outf, pregs (ptr));
086134ec 2403 OUTS (outf, "--] = ");
4b7f6baa 2404 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2405 }
2406 else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2407 {
4b7f6baa
CM		 2408 OUTS (outf, "B[");
2409 OUTS (outf, pregs (ptr));
086134ec 2410 OUTS (outf, "--] = ");
4b7f6baa 2411 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2412 }
2413 else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2414 {
4b7f6baa
CM		 2415 OUTS (outf, "[");
2416 OUTS (outf, pregs (ptr));
086134ec 2417 OUTS (outf, "] = ");
4b7f6baa 2418 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2419 }
2420 else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2421 {
4b7f6baa
CM		 2422 OUTS (outf, "[");
2423 OUTS (outf, pregs (ptr));
086134ec 2424 OUTS (outf, "] = ");
4b7f6baa 2425 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2426 }
2427 else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2428 {
4b7f6baa
CM		 2429 OUTS (outf, "W[");
2430 OUTS (outf, pregs (ptr));
086134ec 2431 OUTS (outf, "] = ");
4b7f6baa 2432 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2433 }
2434 else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2435 {
4b7f6baa
CM		 2436 OUTS (outf, "B[");
2437 OUTS (outf, pregs (ptr));
086134ec 2438 OUTS (outf, "] = ");
4b7f6baa 2439 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2440 }
2441 else
b7d48530
NC		 2442 return 0;
2443
2444 return 2;
4b7f6baa
CM		 2445}
2446
2447static int
2448decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2449{
b7d48530
NC		 2450 /* LDSTiiFP
2451 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2452 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2453 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2454 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2455 int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2456 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2457
2458 if (W == 0)
2459 {
4b7f6baa 2460 OUTS (outf, dpregs (reg));
086134ec 2461 OUTS (outf, " = [FP ");
4b7f6baa
CM		 2462 OUTS (outf, negimm5s4 (offset));
2463 OUTS (outf, "]");
4b7f6baa
CM		 2464 }
2465 else if (W == 1)
2466 {
086134ec 2467 OUTS (outf, "[FP ");
4b7f6baa 2468 OUTS (outf, negimm5s4 (offset));
086134ec 2469 OUTS (outf, "] = ");
4b7f6baa 2470 OUTS (outf, dpregs (reg));
4b7f6baa
CM		 2471 }
2472 else
b7d48530
NC		 2473 return 0;
2474
2475 return 2;
4b7f6baa
CM		 2476}
2477
2478static int
2479decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2480{
b7d48530
NC		 2481 /* LDSTii
2482 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2483 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2484 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2485 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2486 int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2487 int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2488 int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2489 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2490
2491 if (W == 0 && op == 0)
2492 {
4b7f6baa 2493 OUTS (outf, dregs (reg));
086134ec 2494 OUTS (outf, " = [");
4b7f6baa 2495 OUTS (outf, pregs (ptr));
086134ec 2496 OUTS (outf, " + ");
4b7f6baa
CM		 2497 OUTS (outf, uimm4s4 (offset));
2498 OUTS (outf, "]");
4b7f6baa
CM		 2499 }
2500 else if (W == 0 && op == 1)
2501 {
4b7f6baa 2502 OUTS (outf, dregs (reg));
086134ec 2503 OUTS (outf, " = W[");
4b7f6baa 2504 OUTS (outf, pregs (ptr));
086134ec 2505 OUTS (outf, " + ");
4b7f6baa
CM		 2506 OUTS (outf, uimm4s2 (offset));
2507 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2508 }
2509 else if (W == 0 && op == 2)
2510 {
4b7f6baa 2511 OUTS (outf, dregs (reg));
086134ec 2512 OUTS (outf, " = W[");
4b7f6baa 2513 OUTS (outf, pregs (ptr));
086134ec 2514 OUTS (outf, " + ");
4b7f6baa 2515 OUTS (outf, uimm4s2 (offset));
086134ec 2516 OUTS (outf, "] (X)");
4b7f6baa
CM		 2517 }
2518 else if (W == 0 && op == 3)
2519 {
4b7f6baa 2520 OUTS (outf, pregs (reg));
086134ec 2521 OUTS (outf, " = [");
4b7f6baa 2522 OUTS (outf, pregs (ptr));
086134ec 2523 OUTS (outf, " + ");
4b7f6baa
CM		 2524 OUTS (outf, uimm4s4 (offset));
2525 OUTS (outf, "]");
4b7f6baa
CM		 2526 }
2527 else if (W == 1 && op == 0)
2528 {
4b7f6baa
CM		 2529 OUTS (outf, "[");
2530 OUTS (outf, pregs (ptr));
086134ec 2531 OUTS (outf, " + ");
4b7f6baa 2532 OUTS (outf, uimm4s4 (offset));
086134ec 2533 OUTS (outf, "] = ");
4b7f6baa 2534 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2535 }
2536 else if (W == 1 && op == 1)
2537 {
086134ec 2538 OUTS (outf, "W[");
4b7f6baa 2539 OUTS (outf, pregs (ptr));
086134ec 2540 OUTS (outf, " + ");
4b7f6baa 2541 OUTS (outf, uimm4s2 (offset));
086134ec 2542 OUTS (outf, "] = ");
4b7f6baa 2543 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2544 }
2545 else if (W == 1 && op == 3)
2546 {
4b7f6baa
CM		 2547 OUTS (outf, "[");
2548 OUTS (outf, pregs (ptr));
086134ec 2549 OUTS (outf, " + ");
4b7f6baa 2550 OUTS (outf, uimm4s4 (offset));
086134ec 2551 OUTS (outf, "] = ");
4b7f6baa 2552 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2553 }
2554 else
b7d48530
NC		 2555 return 0;
2556
2557 return 2;
4b7f6baa
CM		 2558}
2559
2560static int
2561decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2562{
703ec4e8 2563 struct private *priv = outf->private_data;
b7d48530
NC		 2564 /* LoopSetup
2565 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2566 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2567 |.reg...........| - | - |.eoffset...............................|
2568 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2569 int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2570 int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2571 int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2572 int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2573 int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2574
703ec4e8 2575 if (priv->parallel)
219b747a
MF		 2576 return 0;
2577
298c1ec2
MF		 2578 if (reg > 7)
2579 return 0;
2580
4b7f6baa
CM		 2581 if (rop == 0)
2582 {
4b7f6baa 2583 OUTS (outf, "LSETUP");
086134ec 2584 OUTS (outf, "(0x");
4b7f6baa 2585 OUTS (outf, pcrel4 (soffset));
086134ec 2586 OUTS (outf, ", 0x");
4b7f6baa 2587 OUTS (outf, lppcrel10 (eoffset));
086134ec 2588 OUTS (outf, ") ");
4b7f6baa 2589 OUTS (outf, counters (c));
4b7f6baa
CM		 2590 }
2591 else if (rop == 1)
2592 {
4b7f6baa 2593 OUTS (outf, "LSETUP");
086134ec 2594 OUTS (outf, "(0x");
4b7f6baa 2595 OUTS (outf, pcrel4 (soffset));
086134ec 2596 OUTS (outf, ", 0x");
4b7f6baa 2597 OUTS (outf, lppcrel10 (eoffset));
086134ec 2598 OUTS (outf, ") ");
4b7f6baa 2599 OUTS (outf, counters (c));
086134ec 2600 OUTS (outf, " = ");
4b7f6baa 2601 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2602 }
2603 else if (rop == 3)
2604 {
4b7f6baa 2605 OUTS (outf, "LSETUP");
086134ec 2606 OUTS (outf, "(0x");
4b7f6baa 2607 OUTS (outf, pcrel4 (soffset));
086134ec 2608 OUTS (outf, ", 0x");
4b7f6baa 2609 OUTS (outf, lppcrel10 (eoffset));
086134ec 2610 OUTS (outf, ") ");
4b7f6baa 2611 OUTS (outf, counters (c));
086134ec 2612 OUTS (outf, " = ");
4b7f6baa 2613 OUTS (outf, pregs (reg));
086134ec 2614 OUTS (outf, " >> 0x1");
4b7f6baa
CM		 2615 }
2616 else
b7d48530
NC		 2617 return 0;
2618
2619 return 4;
4b7f6baa
CM		 2620}
2621
2622static int
2623decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2624{
703ec4e8 2625 struct private *priv = outf->private_data;
b7d48530
NC		 2626 /* LDIMMhalf
2627 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2628 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2629 |.hword.........................................................|
2630 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2631 int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2632 int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2633 int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2634 int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2635 int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2636 int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2637
b21c9cb4
BS		 2638 bu32 *pval = get_allreg (grp, reg);
2639
703ec4e8 2640 if (priv->parallel)
219b747a
MF		 2641 return 0;
2642
b21c9cb4
BS		 2643 /* Since we don't have 32-bit immediate loads, we allow the disassembler
2644 to combine them, so it prints out the right values.
2645 Here we keep track of the registers. */
2646 if (H == 0 && S == 1 && Z == 0)
2647 {
2648 /* regs = imm16 (x) */
2649 *pval = imm16_val (hword);
086134ec
BS		 2650 if (hword & 0x8000)
2651 *pval |= 0xFFFF0000;
2652 else
2653 *pval &= 0xFFFF;
b21c9cb4
BS		 2654 }
2655 else if (H == 0 && S == 0 && Z == 1)
2656 {
2657 /* regs = luimm16 (Z) */
2658 *pval = luimm16_val (hword);
086134ec 2659 *pval &= 0xFFFF;
b21c9cb4
BS		 2660 }
2661 else if (H == 0 && S == 0 && Z == 0)
2662 {
2663 /* regs_lo = luimm16 */
2664 *pval &= 0xFFFF0000;
2665 *pval |= luimm16_val (hword);
2666 }
2667 else if (H == 1 && S == 0 && Z == 0)
2668 {
2669 /* regs_hi = huimm16 */
2670 *pval &= 0xFFFF;
2671 *pval |= luimm16_val (hword) << 16;
2672 }
2673
2674 /* Here we do the disassembly */
4b7f6baa
CM		 2675 if (grp == 0 && H == 0 && S == 0 && Z == 0)
2676 {
4b7f6baa 2677 OUTS (outf, dregs_lo (reg));
086134ec
BS		 2678 OUTS (outf, " = ");
2679 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2680 }
2681 else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2682 {
4b7f6baa 2683 OUTS (outf, dregs_hi (reg));
086134ec
BS		 2684 OUTS (outf, " = ");
2685 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2686 }
2687 else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2688 {
4b7f6baa 2689 OUTS (outf, dregs (reg));
086134ec 2690 OUTS (outf, " = ");
4b7f6baa
CM		 2691 OUTS (outf, imm16 (hword));
2692 OUTS (outf, " (X)");
4b7f6baa
CM		 2693 }
2694 else if (H == 0 && S == 1 && Z == 0)
602427c4 2695 {
4b7f6baa 2696 OUTS (outf, regs (reg, grp));
086134ec 2697 OUTS (outf, " = ");
4b7f6baa
CM		 2698 OUTS (outf, imm16 (hword));
2699 OUTS (outf, " (X)");
4b7f6baa
CM		 2700 }
2701 else if (H == 0 && S == 0 && Z == 1)
2702 {
4b7f6baa 2703 OUTS (outf, regs (reg, grp));
086134ec
BS		 2704 OUTS (outf, " = ");
2705 OUTS (outf, uimm16 (hword));
2706 OUTS (outf, " (Z)");
4b7f6baa
CM		 2707 }
2708 else if (H == 0 && S == 0 && Z == 0)
2709 {
4b7f6baa 2710 OUTS (outf, regs_lo (reg, grp));
086134ec 2711 OUTS (outf, " = ");
b21c9cb4 2712 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2713 }
2714 else if (H == 1 && S == 0 && Z == 0)
2715 {
4b7f6baa 2716 OUTS (outf, regs_hi (reg, grp));
086134ec 2717 OUTS (outf, " = ");
b21c9cb4 2718 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2719 }
2720 else
b7d48530
NC		 2721 return 0;
2722
b21c9cb4 2723 /* And we print out the 32-bit value if it is a pointer. */
086134ec 2724 if (S == 0 && Z == 0)
b21c9cb4 2725 {
086134ec
BS		 2726 OUTS (outf, ";\t\t/* (");
2727 OUTS (outf, imm16d (hword));
2728 OUTS (outf, ")\t");
2729
b21c9cb4 2730 /* If it is an MMR, don't print the symbol. */
086134ec
BS		 2731 if (*pval < 0xFFC00000 && grp == 1)
2732 {
2733 OUTS (outf, regs (reg, grp));
2734 OUTS (outf, "=0x");
2735 OUTS (outf, huimm32e (*pval));
2736 }
b21c9cb4 2737 else
086134ec
BS		 2738 {
2739 OUTS (outf, regs (reg, grp));
2740 OUTS (outf, "=0x");
2741 OUTS (outf, huimm32e (*pval));
2742 OUTS (outf, "(");
2743 OUTS (outf, imm32 (*pval));
2744 OUTS (outf, ")");
2745 }
b21c9cb4
BS		 2746
2747 OUTS (outf, " */");
60ac5798 2748 priv->comment = TRUE;
086134ec
BS		 2749 }
2750 if (S == 1 || Z == 1)
2751 {
602427c4
MF		 2752 OUTS (outf, ";\t\t/*\t\t");
2753 OUTS (outf, regs (reg, grp));
2754 OUTS (outf, "=0x");
2755 OUTS (outf, huimm32e (*pval));
2756 OUTS (outf, "(");
2757 OUTS (outf, imm32 (*pval));
2758 OUTS (outf, ") */");
60ac5798 2759 priv->comment = TRUE;
b21c9cb4 2760 }
b7d48530 2761 return 4;
4b7f6baa
CM		 2762}
2763
2764static int
2765decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2766{
703ec4e8 2767 struct private *priv = outf->private_data;
b7d48530
NC		 2768 /* CALLa
2769 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2770 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2771 |.lsw...........................................................|
2772 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2773 int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2774 int lsw = ((iw1 >> 0) & 0xffff);
2775 int msw = ((iw0 >> 0) & 0xff);
2776
703ec4e8 2777 if (priv->parallel)
219b747a
MF		 2778 return 0;
2779
4b7f6baa 2780 if (S == 1)
086134ec 2781 OUTS (outf, "CALL 0x");
4b7f6baa 2782 else if (S == 0)
086134ec 2783 OUTS (outf, "JUMP.L 0x");
4b7f6baa 2784 else
b7d48530
NC		 2785 return 0;
2786
2787 OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2788 return 4;
4b7f6baa
CM		 2789}
2790
2791static int
2792decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2793{
b7d48530
NC		 2794 /* LDSTidxI
2795 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2796 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2797 |.offset........................................................|
2798 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2799 int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2800 int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2801 int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2802 int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2803 int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2804 int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2805
2806 if (W == 0 && sz == 0 && Z == 0)
2807 {
4b7f6baa 2808 OUTS (outf, dregs (reg));
086134ec 2809 OUTS (outf, " = [");
4b7f6baa 2810 OUTS (outf, pregs (ptr));
086134ec 2811 OUTS (outf, " + ");
4b7f6baa
CM		 2812 OUTS (outf, imm16s4 (offset));
2813 OUTS (outf, "]");
4b7f6baa
CM		 2814 }
2815 else if (W == 0 && sz == 0 && Z == 1)
2816 {
4b7f6baa 2817 OUTS (outf, pregs (reg));
086134ec 2818 OUTS (outf, " = [");
4b7f6baa 2819 OUTS (outf, pregs (ptr));
086134ec 2820 OUTS (outf, " + ");
4b7f6baa
CM		 2821 OUTS (outf, imm16s4 (offset));
2822 OUTS (outf, "]");
4b7f6baa
CM		 2823 }
2824 else if (W == 0 && sz == 1 && Z == 0)
2825 {
4b7f6baa 2826 OUTS (outf, dregs (reg));
086134ec 2827 OUTS (outf, " = W[");
4b7f6baa 2828 OUTS (outf, pregs (ptr));
086134ec 2829 OUTS (outf, " + ");
4b7f6baa
CM		 2830 OUTS (outf, imm16s2 (offset));
2831 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2832 }
2833 else if (W == 0 && sz == 1 && Z == 1)
2834 {
4b7f6baa 2835 OUTS (outf, dregs (reg));
086134ec 2836 OUTS (outf, " = W[");
4b7f6baa 2837 OUTS (outf, pregs (ptr));
086134ec 2838 OUTS (outf, " + ");
4b7f6baa 2839 OUTS (outf, imm16s2 (offset));
086134ec 2840 OUTS (outf, "] (X)");
4b7f6baa
CM		 2841 }
2842 else if (W == 0 && sz == 2 && Z == 0)
2843 {
4b7f6baa 2844 OUTS (outf, dregs (reg));
086134ec 2845 OUTS (outf, " = B[");
4b7f6baa 2846 OUTS (outf, pregs (ptr));
086134ec 2847 OUTS (outf, " + ");
4b7f6baa
CM		 2848 OUTS (outf, imm16 (offset));
2849 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2850 }
2851 else if (W == 0 && sz == 2 && Z == 1)
2852 {
4b7f6baa 2853 OUTS (outf, dregs (reg));
086134ec 2854 OUTS (outf, " = B[");
4b7f6baa 2855 OUTS (outf, pregs (ptr));
086134ec 2856 OUTS (outf, " + ");
4b7f6baa 2857 OUTS (outf, imm16 (offset));
086134ec 2858 OUTS (outf, "] (X)");
4b7f6baa
CM		 2859 }
2860 else if (W == 1 && sz == 0 && Z == 0)
2861 {
4b7f6baa
CM		 2862 OUTS (outf, "[");
2863 OUTS (outf, pregs (ptr));
086134ec 2864 OUTS (outf, " + ");
4b7f6baa 2865 OUTS (outf, imm16s4 (offset));
086134ec 2866 OUTS (outf, "] = ");
4b7f6baa 2867 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2868 }
2869 else if (W == 1 && sz == 0 && Z == 1)
2870 {
4b7f6baa
CM		 2871 OUTS (outf, "[");
2872 OUTS (outf, pregs (ptr));
086134ec 2873 OUTS (outf, " + ");
4b7f6baa 2874 OUTS (outf, imm16s4 (offset));
086134ec 2875 OUTS (outf, "] = ");
4b7f6baa 2876 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2877 }
2878 else if (W == 1 && sz == 1 && Z == 0)
2879 {
4b7f6baa
CM		 2880 OUTS (outf, "W[");
2881 OUTS (outf, pregs (ptr));
086134ec 2882 OUTS (outf, " + ");
4b7f6baa 2883 OUTS (outf, imm16s2 (offset));
086134ec 2884 OUTS (outf, "] = ");
4b7f6baa 2885 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2886 }
2887 else if (W == 1 && sz == 2 && Z == 0)
2888 {
4b7f6baa
CM		 2889 OUTS (outf, "B[");
2890 OUTS (outf, pregs (ptr));
086134ec 2891 OUTS (outf, " + ");
4b7f6baa 2892 OUTS (outf, imm16 (offset));
086134ec 2893 OUTS (outf, "] = ");
4b7f6baa 2894 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2895 }
2896 else
b7d48530
NC		 2897 return 0;
2898
2899 return 4;
4b7f6baa
CM		 2900}
2901
2902static int
2903decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2904{
703ec4e8 2905 struct private *priv = outf->private_data;
b7d48530
NC		 2906 /* linkage
2907 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2908 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2909 |.framesize.....................................................|
2910 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2911 int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2912 int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2913
703ec4e8 2914 if (priv->parallel)
219b747a
MF		 2915 return 0;
2916
4b7f6baa
CM		 2917 if (R == 0)
2918 {
4b7f6baa
CM		 2919 OUTS (outf, "LINK ");
2920 OUTS (outf, uimm16s4 (framesize));
086134ec
BS		 2921 OUTS (outf, ";\t\t/* (");
2922 OUTS (outf, uimm16s4d (framesize));
2923 OUTS (outf, ") */");
60ac5798 2924 priv->comment = TRUE;
4b7f6baa
CM		 2925 }
2926 else if (R == 1)
b7d48530 2927 OUTS (outf, "UNLINK");
4b7f6baa 2928 else
b7d48530
NC		 2929 return 0;
2930
2931 return 4;
4b7f6baa
CM		 2932}
2933
2934static int
2935decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2936{
b7d48530
NC		 2937 /* dsp32mac
2938 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2939 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2940 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2941 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2942 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2943 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2944 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2945 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
4b7f6baa 2946 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
b7d48530 2947 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
4b7f6baa
CM		 2948 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2949 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
b7d48530
NC		 2950 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2951 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2952 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2953 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2954 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2955 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
4b7f6baa
CM		 2956
2957 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
2958 return 0;
2959
2960 if (op1 == 3 && MM)
2961 return 0;
2962
2963 if ((w1 || w0) && mmod == M_W32)
2964 return 0;
2965
ee171c8f 2966 if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
4b7f6baa
CM		 2967 return 0;
2968
2969 if (w1 == 1 || op1 != 3)
2970 {
2971 if (w1)
2972 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
2973
2974 if (op1 == 3)
2975 OUTS (outf, " = A1");
2976 else
2977 {
2978 if (w1)
2979 OUTS (outf, " = (");
2980 decode_macfunc (1, op1, h01, h11, src0, src1, outf);
2981 if (w1)
2982 OUTS (outf, ")");
2983 }
2984
2985 if (w0 == 1 || op0 != 3)
2986 {
2987 if (MM)
2988 OUTS (outf, " (M)");
4b7f6baa
CM		 2989 OUTS (outf, ", ");
2990 }
2991 }
2992
2993 if (w0 == 1 || op0 != 3)
2994 {
67171547
MF		 2995 /* Clear MM option since it only matters for MAC1, and if we made
2996 it this far, we've already shown it or we want to ignore it. */
2997 MM = 0;
2998
4b7f6baa
CM		 2999 if (w0)
3000 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3001
3002 if (op0 == 3)
3003 OUTS (outf, " = A0");
3004 else
3005 {
3006 if (w0)
3007 OUTS (outf, " = (");
3008 decode_macfunc (0, op0, h00, h10, src0, src1, outf);
3009 if (w0)
3010 OUTS (outf, ")");
3011 }
3012 }
3013
3014 decode_optmode (mmod, MM, outf);
3015
3016 return 4;
3017}
3018
3019static int
3020decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3021{
b7d48530
NC		 3022 /* dsp32mult
3023 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3024 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
3025 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
3026 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3027 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
3028 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
3029 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
4b7f6baa 3030 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
b7d48530 3031 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
4b7f6baa
CM		 3032 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
3033 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
b7d48530
NC		 3034 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
3035 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3036 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3037 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3038 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
4b7f6baa
CM		 3039
3040 if (w1 == 0 && w0 == 0)
3041 return 0;
b7d48530 3042
4b7f6baa
CM		 3043 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
3044 return 0;
b7d48530 3045
4b7f6baa
CM		 3046 if (w1)
3047 {
4db66394 3048 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
4b7f6baa
CM		 3049 OUTS (outf, " = ");
3050 decode_multfunc (h01, h11, src0, src1, outf);
3051
3052 if (w0)
3053 {
3054 if (MM)
3055 OUTS (outf, " (M)");
3056 MM = 0;
3057 OUTS (outf, ", ");
3058 }
3059 }
3060
3061 if (w0)
3062 {
4db66394 3063 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
4b7f6baa
CM		 3064 OUTS (outf, " = ");
3065 decode_multfunc (h00, h10, src0, src1, outf);
3066 }
3067
3068 decode_optmode (mmod, MM, outf);
3069 return 4;
3070}
3071
3072static int
3073decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3074{
b7d48530
NC		 3075 /* dsp32alu
3076 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3077 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3078 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3079 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 3080 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3081 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3082 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3083 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3084 int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3085 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3086 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3087 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3088 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3089
3090 if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3091 {
086134ec 3092 OUTS (outf, "A0.L = ");
4b7f6baa 3093 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3094 }
3095 else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3096 {
086134ec 3097 OUTS (outf, "A1.H = ");
4b7f6baa 3098 OUTS (outf, dregs_hi (src0));
4b7f6baa
CM		 3099 }
3100 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3101 {
086134ec 3102 OUTS (outf, "A1.L = ");
4b7f6baa 3103 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3104 }
3105 else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3106 {
086134ec 3107 OUTS (outf, "A0.H = ");
4b7f6baa 3108 OUTS (outf, dregs_hi (src0));
4b7f6baa
CM		 3109 }
3110 else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3111 {
4b7f6baa 3112 OUTS (outf, dregs_hi (dst0));
086134ec 3113 OUTS (outf, " = ");
4b7f6baa 3114 OUTS (outf, dregs (src0));
086134ec 3115 OUTS (outf, " - ");
4b7f6baa 3116 OUTS (outf, dregs (src1));
086134ec 3117 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3118 }
3119 else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3120 {
4b7f6baa 3121 OUTS (outf, dregs_hi (dst0));
086134ec 3122 OUTS (outf, " = ");
4b7f6baa 3123 OUTS (outf, dregs (src0));
086134ec 3124 OUTS (outf, " + ");
4b7f6baa 3125 OUTS (outf, dregs (src1));
086134ec 3126 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3127 }
3128 else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3129 {
4b7f6baa 3130 OUTS (outf, dregs_lo (dst0));
086134ec 3131 OUTS (outf, " = ");
4b7f6baa 3132 OUTS (outf, dregs (src0));
086134ec 3133 OUTS (outf, " - ");
4b7f6baa 3134 OUTS (outf, dregs (src1));
086134ec 3135 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3136 }
3137 else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3138 {
4b7f6baa 3139 OUTS (outf, dregs_lo (dst0));
086134ec 3140 OUTS (outf, " = ");
4b7f6baa 3141 OUTS (outf, dregs (src0));
086134ec 3142 OUTS (outf, " + ");
4b7f6baa 3143 OUTS (outf, dregs (src1));
086134ec 3144 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3145 }
3146 else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3147 {
4b7f6baa 3148 OUTS (outf, dregs_lo (dst0));
086134ec 3149 OUTS (outf, " = ");
4b7f6baa 3150 OUTS (outf, dregs (src0));
086134ec 3151 OUTS (outf, " - ");
4b7f6baa 3152 OUTS (outf, dregs (src1));
086134ec 3153 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3154 }
3155 else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3156 {
4b7f6baa 3157 OUTS (outf, dregs_hi (dst0));
086134ec 3158 OUTS (outf, " = ");
4b7f6baa 3159 OUTS (outf, dregs (src0));
086134ec 3160 OUTS (outf, " + ");
4b7f6baa 3161 OUTS (outf, dregs (src1));
086134ec 3162 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3163 }
3164 else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3165 {
4b7f6baa 3166 OUTS (outf, dregs_lo (dst0));
086134ec 3167 OUTS (outf, " = ");
4b7f6baa 3168 OUTS (outf, dregs (src0));
086134ec 3169 OUTS (outf, " + ");
4b7f6baa 3170 OUTS (outf, dregs (src1));
086134ec 3171 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3172 }
3173 else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3174 {
4b7f6baa 3175 OUTS (outf, dregs_hi (dst0));
086134ec 3176 OUTS (outf, " = ");
4b7f6baa 3177 OUTS (outf, dregs (src0));
086134ec 3178 OUTS (outf, " - ");
4b7f6baa 3179 OUTS (outf, dregs (src1));
086134ec 3180 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3181 }
3182 else if (HL == 1 && aop == 0 && aopcde == 2)
3183 {
4b7f6baa 3184 OUTS (outf, dregs_hi (dst0));
086134ec 3185 OUTS (outf, " = ");
4b7f6baa 3186 OUTS (outf, dregs_lo (src0));
086134ec 3187 OUTS (outf, " + ");
4b7f6baa 3188 OUTS (outf, dregs_lo (src1));
4b7f6baa 3189 amod1 (s, x, outf);
4b7f6baa
CM		 3190 }
3191 else if (HL == 1 && aop == 1 && aopcde == 2)
3192 {
4b7f6baa 3193 OUTS (outf, dregs_hi (dst0));
086134ec 3194 OUTS (outf, " = ");
4b7f6baa 3195 OUTS (outf, dregs_lo (src0));
086134ec 3196 OUTS (outf, " + ");
4b7f6baa 3197 OUTS (outf, dregs_hi (src1));
4b7f6baa 3198 amod1 (s, x, outf);
4b7f6baa
CM		 3199 }
3200 else if (HL == 1 && aop == 2 && aopcde == 2)
3201 {
4b7f6baa 3202 OUTS (outf, dregs_hi (dst0));
086134ec 3203 OUTS (outf, " = ");
4b7f6baa 3204 OUTS (outf, dregs_hi (src0));
086134ec 3205 OUTS (outf, " + ");
4b7f6baa 3206 OUTS (outf, dregs_lo (src1));
4b7f6baa 3207 amod1 (s, x, outf);
4b7f6baa
CM		 3208 }
3209 else if (HL == 1 && aop == 3 && aopcde == 2)
3210 {
4b7f6baa 3211 OUTS (outf, dregs_hi (dst0));
086134ec 3212 OUTS (outf, " = ");
4b7f6baa 3213 OUTS (outf, dregs_hi (src0));
086134ec 3214 OUTS (outf, " + ");
4b7f6baa 3215 OUTS (outf, dregs_hi (src1));
4b7f6baa 3216 amod1 (s, x, outf);
4b7f6baa
CM		 3217 }
3218 else if (HL == 0 && aop == 0 && aopcde == 3)
3219 {
4b7f6baa 3220 OUTS (outf, dregs_lo (dst0));
086134ec 3221 OUTS (outf, " = ");
4b7f6baa 3222 OUTS (outf, dregs_lo (src0));
086134ec 3223 OUTS (outf, " - ");
4b7f6baa 3224 OUTS (outf, dregs_lo (src1));
4b7f6baa 3225 amod1 (s, x, outf);
4b7f6baa
CM		 3226 }
3227 else if (HL == 0 && aop == 1 && aopcde == 3)
3228 {
4b7f6baa 3229 OUTS (outf, dregs_lo (dst0));
086134ec 3230 OUTS (outf, " = ");
4b7f6baa 3231 OUTS (outf, dregs_lo (src0));
086134ec 3232 OUTS (outf, " - ");
4b7f6baa 3233 OUTS (outf, dregs_hi (src1));
4b7f6baa 3234 amod1 (s, x, outf);
4b7f6baa
CM		 3235 }
3236 else if (HL == 0 && aop == 3 && aopcde == 2)
3237 {
4b7f6baa 3238 OUTS (outf, dregs_lo (dst0));
086134ec 3239 OUTS (outf, " = ");
4b7f6baa 3240 OUTS (outf, dregs_hi (src0));
086134ec 3241 OUTS (outf, " + ");
4b7f6baa 3242 OUTS (outf, dregs_hi (src1));
4b7f6baa 3243 amod1 (s, x, outf);
4b7f6baa
CM		 3244 }
3245 else if (HL == 1 && aop == 0 && aopcde == 3)
3246 {
4b7f6baa 3247 OUTS (outf, dregs_hi (dst0));
086134ec 3248 OUTS (outf, " = ");
4b7f6baa 3249 OUTS (outf, dregs_lo (src0));
086134ec 3250 OUTS (outf, " - ");
4b7f6baa 3251 OUTS (outf, dregs_lo (src1));
4b7f6baa 3252 amod1 (s, x, outf);
4b7f6baa
CM		 3253 }
3254 else if (HL == 1 && aop == 1 && aopcde == 3)
3255 {
4b7f6baa 3256 OUTS (outf, dregs_hi (dst0));
086134ec 3257 OUTS (outf, " = ");
4b7f6baa 3258 OUTS (outf, dregs_lo (src0));
086134ec 3259 OUTS (outf, " - ");
4b7f6baa 3260 OUTS (outf, dregs_hi (src1));
4b7f6baa 3261 amod1 (s, x, outf);
4b7f6baa
CM		 3262 }
3263 else if (HL == 1 && aop == 2 && aopcde == 3)
3264 {
4b7f6baa 3265 OUTS (outf, dregs_hi (dst0));
086134ec 3266 OUTS (outf, " = ");
4b7f6baa 3267 OUTS (outf, dregs_hi (src0));
086134ec 3268 OUTS (outf, " - ");
4b7f6baa 3269 OUTS (outf, dregs_lo (src1));
4b7f6baa 3270 amod1 (s, x, outf);
4b7f6baa
CM		 3271 }
3272 else if (HL == 1 && aop == 3 && aopcde == 3)
3273 {
4b7f6baa 3274 OUTS (outf, dregs_hi (dst0));
086134ec 3275 OUTS (outf, " = ");
4b7f6baa 3276 OUTS (outf, dregs_hi (src0));
086134ec 3277 OUTS (outf, " - ");
4b7f6baa 3278 OUTS (outf, dregs_hi (src1));
4b7f6baa 3279 amod1 (s, x, outf);
4b7f6baa
CM		 3280 }
3281 else if (HL == 0 && aop == 2 && aopcde == 2)
3282 {
4b7f6baa 3283 OUTS (outf, dregs_lo (dst0));
086134ec 3284 OUTS (outf, " = ");
4b7f6baa 3285 OUTS (outf, dregs_hi (src0));
086134ec 3286 OUTS (outf, " + ");
4b7f6baa 3287 OUTS (outf, dregs_lo (src1));
4b7f6baa 3288 amod1 (s, x, outf);
4b7f6baa
CM		 3289 }
3290 else if (HL == 0 && aop == 1 && aopcde == 2)
3291 {
4b7f6baa 3292 OUTS (outf, dregs_lo (dst0));
086134ec 3293 OUTS (outf, " = ");
4b7f6baa 3294 OUTS (outf, dregs_lo (src0));
086134ec 3295 OUTS (outf, " + ");
4b7f6baa 3296 OUTS (outf, dregs_hi (src1));
4b7f6baa 3297 amod1 (s, x, outf);
4b7f6baa
CM		 3298 }
3299 else if (HL == 0 && aop == 2 && aopcde == 3)
3300 {
4b7f6baa 3301 OUTS (outf, dregs_lo (dst0));
086134ec 3302 OUTS (outf, " = ");
4b7f6baa 3303 OUTS (outf, dregs_hi (src0));
086134ec 3304 OUTS (outf, " - ");
4b7f6baa 3305 OUTS (outf, dregs_lo (src1));
4b7f6baa 3306 amod1 (s, x, outf);
4b7f6baa
CM		 3307 }
3308 else if (HL == 0 && aop == 3 && aopcde == 3)
3309 {
4b7f6baa 3310 OUTS (outf, dregs_lo (dst0));
086134ec 3311 OUTS (outf, " = ");
4b7f6baa 3312 OUTS (outf, dregs_hi (src0));
086134ec 3313 OUTS (outf, " - ");
4b7f6baa 3314 OUTS (outf, dregs_hi (src1));
4b7f6baa 3315 amod1 (s, x, outf);
4b7f6baa
CM		 3316 }
3317 else if (HL == 0 && aop == 0 && aopcde == 2)
3318 {
4b7f6baa 3319 OUTS (outf, dregs_lo (dst0));
086134ec 3320 OUTS (outf, " = ");
4b7f6baa 3321 OUTS (outf, dregs_lo (src0));
086134ec 3322 OUTS (outf, " + ");
4b7f6baa 3323 OUTS (outf, dregs_lo (src1));
4b7f6baa 3324 amod1 (s, x, outf);
4b7f6baa
CM		 3325 }
3326 else if (aop == 0 && aopcde == 9 && s == 1)
3327 {
086134ec 3328 OUTS (outf, "A0 = ");
4b7f6baa 3329 OUTS (outf, dregs (src0));
4b7f6baa
CM		 3330 }
3331 else if (aop == 3 && aopcde == 11 && s == 0)
086134ec 3332 OUTS (outf, "A0 -= A1");
b7d48530 3333
4b7f6baa 3334 else if (aop == 3 && aopcde == 11 && s == 1)
086134ec 3335 OUTS (outf, "A0 -= A1 (W32)");
b7d48530 3336
4b7f6baa
CM		 3337 else if (aop == 1 && aopcde == 22 && HL == 1)
3338 {
4b7f6baa 3339 OUTS (outf, dregs (dst0));
086134ec 3340 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3341 OUTS (outf, dregs (src0 + 1));
3342 OUTS (outf, ":");
086134ec
BS		 3343 OUTS (outf, imm5d (src0));
3344 OUTS (outf, ", ");
4b7f6baa
CM		 3345 OUTS (outf, dregs (src1 + 1));
3346 OUTS (outf, ":");
086134ec
BS		 3347 OUTS (outf, imm5d (src1));
3348 OUTS (outf, ") (TH");
4b7f6baa
CM		 3349 if (s == 1)
3350 OUTS (outf, ", R)");
3351 else
3352 OUTS (outf, ")");
4b7f6baa
CM		 3353 }
3354 else if (aop == 1 && aopcde == 22 && HL == 0)
3355 {
4b7f6baa 3356 OUTS (outf, dregs (dst0));
086134ec 3357 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3358 OUTS (outf, dregs (src0 + 1));
3359 OUTS (outf, ":");
086134ec
BS		 3360 OUTS (outf, imm5d (src0));
3361 OUTS (outf, ", ");
4b7f6baa
CM		 3362 OUTS (outf, dregs (src1 + 1));
3363 OUTS (outf, ":");
086134ec
BS		 3364 OUTS (outf, imm5d (src1));
3365 OUTS (outf, ") (TL");
4b7f6baa
CM		 3366 if (s == 1)
3367 OUTS (outf, ", R)");
3368 else
3369 OUTS (outf, ")");
4b7f6baa
CM		 3370 }
3371 else if (aop == 0 && aopcde == 22 && HL == 1)
3372 {
4b7f6baa 3373 OUTS (outf, dregs (dst0));
086134ec 3374 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3375 OUTS (outf, dregs (src0 + 1));
3376 OUTS (outf, ":");
086134ec
BS		 3377 OUTS (outf, imm5d (src0));
3378 OUTS (outf, ", ");
4b7f6baa
CM		 3379 OUTS (outf, dregs (src1 + 1));
3380 OUTS (outf, ":");
086134ec
BS		 3381 OUTS (outf, imm5d (src1));
3382 OUTS (outf, ") (RNDH");
4b7f6baa
CM		 3383 if (s == 1)
3384 OUTS (outf, ", R)");
3385 else
3386 OUTS (outf, ")");
4b7f6baa
CM		 3387 }
3388 else if (aop == 0 && aopcde == 22 && HL == 0)
3389 {
4b7f6baa 3390 OUTS (outf, dregs (dst0));
086134ec 3391 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3392 OUTS (outf, dregs (src0 + 1));
3393 OUTS (outf, ":");
086134ec
BS		 3394 OUTS (outf, imm5d (src0));
3395 OUTS (outf, ", ");
4b7f6baa
CM		 3396 OUTS (outf, dregs (src1 + 1));
3397 OUTS (outf, ":");
086134ec
BS		 3398 OUTS (outf, imm5d (src1));
3399 OUTS (outf, ") (RNDL");
4b7f6baa
CM		 3400 if (s == 1)
3401 OUTS (outf, ", R)");
3402 else
3403 OUTS (outf, ")");
4b7f6baa
CM		 3404 }
3405 else if (aop == 0 && s == 0 && aopcde == 8)
086134ec 3406 OUTS (outf, "A0 = 0");
b7d48530 3407
4b7f6baa 3408 else if (aop == 0 && s == 1 && aopcde == 8)
086134ec 3409 OUTS (outf, "A0 = A0 (S)");
b7d48530 3410
4b7f6baa 3411 else if (aop == 1 && s == 0 && aopcde == 8)
086134ec 3412 OUTS (outf, "A1 = 0");
b7d48530 3413
4b7f6baa 3414 else if (aop == 1 && s == 1 && aopcde == 8)
086134ec 3415 OUTS (outf, "A1 = A1 (S)");
b7d48530 3416
4b7f6baa 3417 else if (aop == 2 && s == 0 && aopcde == 8)
086134ec 3418 OUTS (outf, "A1 = A0 = 0");
b7d48530 3419
4b7f6baa 3420 else if (aop == 2 && s == 1 && aopcde == 8)
086134ec 3421 OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
b7d48530 3422
4b7f6baa 3423 else if (aop == 3 && s == 0 && aopcde == 8)
086134ec 3424 OUTS (outf, "A0 = A1");
b7d48530 3425
4b7f6baa 3426 else if (aop == 3 && s == 1 && aopcde == 8)
086134ec 3427 OUTS (outf, "A1 = A0");
b7d48530 3428
4b7f6baa
CM		 3429 else if (aop == 1 && aopcde == 9 && s == 0)
3430 {
086134ec 3431 OUTS (outf, "A0.X = ");
4b7f6baa 3432 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3433 }
3434 else if (aop == 1 && HL == 0 && aopcde == 11)
3435 {
4b7f6baa 3436 OUTS (outf, dregs_lo (dst0));
086134ec 3437 OUTS (outf, " = (A0 += A1)");
4b7f6baa
CM		 3438 }
3439 else if (aop == 3 && HL == 0 && aopcde == 16)
13c02f06 3440 OUTS (outf, "A1 = ABS A1, A0 = ABS A0");
b7d48530 3441
4b7f6baa
CM		 3442 else if (aop == 0 && aopcde == 23 && HL == 1)
3443 {
4b7f6baa 3444 OUTS (outf, dregs (dst0));
086134ec 3445 OUTS (outf, " = BYTEOP3P (");
4b7f6baa
CM		 3446 OUTS (outf, dregs (src0 + 1));
3447 OUTS (outf, ":");
086134ec
BS		 3448 OUTS (outf, imm5d (src0));
3449 OUTS (outf, ", ");
4b7f6baa
CM		 3450 OUTS (outf, dregs (src1 + 1));
3451 OUTS (outf, ":");
086134ec
BS		 3452 OUTS (outf, imm5d (src1));
3453 OUTS (outf, ") (HI");
4b7f6baa
CM		 3454 if (s == 1)
3455 OUTS (outf, ", R)");
3456 else
3457 OUTS (outf, ")");
4b7f6baa
CM		 3458 }
3459 else if (aop == 3 && aopcde == 9 && s == 0)
3460 {
086134ec 3461 OUTS (outf, "A1.X = ");
4b7f6baa 3462 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3463 }
3464 else if (aop == 1 && HL == 1 && aopcde == 16)
086134ec 3465 OUTS (outf, "A1 = ABS A1");
b7d48530 3466
4b7f6baa 3467 else if (aop == 0 && HL == 1 && aopcde == 16)
086134ec 3468 OUTS (outf, "A1 = ABS A0");
b7d48530 3469
4b7f6baa
CM		 3470 else if (aop == 2 && aopcde == 9 && s == 1)
3471 {
086134ec 3472 OUTS (outf, "A1 = ");
4b7f6baa 3473 OUTS (outf, dregs (src0));
4b7f6baa
CM		 3474 }
3475 else if (HL == 0 && aop == 3 && aopcde == 12)
3476 {
4b7f6baa 3477 OUTS (outf, dregs_lo (dst0));
086134ec 3478 OUTS (outf, " = ");
4b7f6baa 3479 OUTS (outf, dregs (src0));
086134ec 3480 OUTS (outf, " (RND)");
4b7f6baa
CM		 3481 }
3482 else if (aop == 1 && HL == 0 && aopcde == 16)
086134ec 3483 OUTS (outf, "A0 = ABS A1");
b7d48530 3484
4b7f6baa 3485 else if (aop == 0 && HL == 0 && aopcde == 16)
086134ec 3486 OUTS (outf, "A0 = ABS A0");
b7d48530 3487
4b7f6baa
CM		 3488 else if (aop == 3 && HL == 0 && aopcde == 15)
3489 {
4b7f6baa 3490 OUTS (outf, dregs (dst0));
086134ec 3491 OUTS (outf, " = -");
4b7f6baa 3492 OUTS (outf, dregs (src0));
086134ec 3493 OUTS (outf, " (V)");
4b7f6baa
CM		 3494 }
3495 else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3496 {
4b7f6baa 3497 OUTS (outf, dregs (dst0));
086134ec 3498 OUTS (outf, " = -");
4b7f6baa 3499 OUTS (outf, dregs (src0));
086134ec 3500 OUTS (outf, " (S)");
4b7f6baa
CM		 3501 }
3502 else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3503 {
4b7f6baa 3504 OUTS (outf, dregs (dst0));
086134ec 3505 OUTS (outf, " = -");
4b7f6baa 3506 OUTS (outf, dregs (src0));
086134ec 3507 OUTS (outf, " (NS)");
4b7f6baa
CM		 3508 }
3509 else if (aop == 1 && HL == 1 && aopcde == 11)
3510 {
4b7f6baa 3511 OUTS (outf, dregs_hi (dst0));
086134ec 3512 OUTS (outf, " = (A0 += A1)");
4b7f6baa
CM		 3513 }
3514 else if (aop == 2 && aopcde == 11 && s == 0)
086134ec 3515 OUTS (outf, "A0 += A1");
b7d48530 3516
4b7f6baa 3517 else if (aop == 2 && aopcde == 11 && s == 1)
086134ec 3518 OUTS (outf, "A0 += A1 (W32)");
b7d48530 3519
4b7f6baa 3520 else if (aop == 3 && HL == 0 && aopcde == 14)
086134ec 3521 OUTS (outf, "A1 = -A1, A0 = -A0");
b7d48530 3522
4b7f6baa
CM		 3523 else if (HL == 1 && aop == 3 && aopcde == 12)
3524 {
4b7f6baa 3525 OUTS (outf, dregs_hi (dst0));
086134ec 3526 OUTS (outf, " = ");
4b7f6baa 3527 OUTS (outf, dregs (src0));
086134ec 3528 OUTS (outf, " (RND)");
4b7f6baa
CM		 3529 }
3530 else if (aop == 0 && aopcde == 23 && HL == 0)
3531 {
4b7f6baa 3532 OUTS (outf, dregs (dst0));
086134ec 3533 OUTS (outf, " = BYTEOP3P (");
4b7f6baa
CM		 3534 OUTS (outf, dregs (src0 + 1));
3535 OUTS (outf, ":");
086134ec
BS		 3536 OUTS (outf, imm5d (src0));
3537 OUTS (outf, ", ");
4b7f6baa
CM		 3538 OUTS (outf, dregs (src1 + 1));
3539 OUTS (outf, ":");
086134ec
BS		 3540 OUTS (outf, imm5d (src1));
3541 OUTS (outf, ") (LO");
4b7f6baa
CM		 3542 if (s == 1)
3543 OUTS (outf, ", R)");
3544 else
3545 OUTS (outf, ")");
4b7f6baa
CM		 3546 }
3547 else if (aop == 0 && HL == 0 && aopcde == 14)
086134ec 3548 OUTS (outf, "A0 = -A0");
b7d48530 3549
4b7f6baa 3550 else if (aop == 1 && HL == 0 && aopcde == 14)
086134ec 3551 OUTS (outf, "A0 = -A1");
b7d48530 3552
4b7f6baa 3553 else if (aop == 0 && HL == 1 && aopcde == 14)
086134ec 3554 OUTS (outf, "A1 = -A0");
b7d48530 3555
4b7f6baa 3556 else if (aop == 1 && HL == 1 && aopcde == 14)
086134ec 3557 OUTS (outf, "A1 = -A1");
b7d48530 3558
4b7f6baa
CM		 3559 else if (aop == 0 && aopcde == 12)
3560 {
4b7f6baa 3561 OUTS (outf, dregs_hi (dst0));
086134ec 3562 OUTS (outf, " = ");
4b7f6baa 3563 OUTS (outf, dregs_lo (dst0));
086134ec 3564 OUTS (outf, " = SIGN (");
4b7f6baa 3565 OUTS (outf, dregs_hi (src0));
086134ec 3566 OUTS (outf, ") * ");
4b7f6baa 3567 OUTS (outf, dregs_hi (src1));
086134ec 3568 OUTS (outf, " + SIGN (");
4b7f6baa 3569 OUTS (outf, dregs_lo (src0));
086134ec 3570 OUTS (outf, ") * ");
4b7f6baa 3571 OUTS (outf, dregs_lo (src1));
4b7f6baa
CM		 3572 }
3573 else if (aop == 2 && aopcde == 0)
3574 {
4b7f6baa 3575 OUTS (outf, dregs (dst0));
086134ec 3576 OUTS (outf, " = ");
4b7f6baa 3577 OUTS (outf, dregs (src0));
086134ec 3578 OUTS (outf, " -|+ ");
4b7f6baa 3579 OUTS (outf, dregs (src1));
4b7f6baa 3580 amod0 (s, x, outf);
4b7f6baa
CM		 3581 }
3582 else if (aop == 1 && aopcde == 12)
3583 {
4b7f6baa 3584 OUTS (outf, dregs (dst1));
086134ec 3585 OUTS (outf, " = A1.L + A1.H, ");
4b7f6baa 3586 OUTS (outf, dregs (dst0));
086134ec 3587 OUTS (outf, " = A0.L + A0.H");
4b7f6baa
CM		 3588 }
3589 else if (aop == 2 && aopcde == 4)
3590 {
4b7f6baa 3591 OUTS (outf, dregs (dst1));
086134ec 3592 OUTS (outf, " = ");
4b7f6baa 3593 OUTS (outf, dregs (src0));
086134ec 3594 OUTS (outf, " + ");
4b7f6baa 3595 OUTS (outf, dregs (src1));
086134ec 3596 OUTS (outf, ", ");
4b7f6baa 3597 OUTS (outf, dregs (dst0));
086134ec 3598 OUTS (outf, " = ");
4b7f6baa 3599 OUTS (outf, dregs (src0));
086134ec 3600 OUTS (outf, " - ");
4b7f6baa 3601 OUTS (outf, dregs (src1));
4b7f6baa 3602 amod1 (s, x, outf);
4b7f6baa
CM		 3603 }
3604 else if (HL == 0 && aopcde == 1)
3605 {
4b7f6baa 3606 OUTS (outf, dregs (dst1));
086134ec 3607 OUTS (outf, " = ");
4b7f6baa 3608 OUTS (outf, dregs (src0));
086134ec 3609 OUTS (outf, " +|+ ");
4b7f6baa 3610 OUTS (outf, dregs (src1));
086134ec 3611 OUTS (outf, ", ");
4b7f6baa 3612 OUTS (outf, dregs (dst0));
086134ec 3613 OUTS (outf, " = ");
4b7f6baa 3614 OUTS (outf, dregs (src0));
086134ec 3615 OUTS (outf, " -|- ");
4b7f6baa
CM		 3616 OUTS (outf, dregs (src1));
3617 amod0amod2 (s, x, aop, outf);
4b7f6baa
CM		 3618 }
3619 else if (aop == 0 && aopcde == 11)
3620 {
4b7f6baa 3621 OUTS (outf, dregs (dst0));
086134ec 3622 OUTS (outf, " = (A0 += A1)");
4b7f6baa
CM		 3623 }
3624 else if (aop == 0 && aopcde == 10)
3625 {
4b7f6baa 3626 OUTS (outf, dregs_lo (dst0));
086134ec 3627 OUTS (outf, " = A0.X");
4b7f6baa
CM		 3628 }
3629 else if (aop == 1 && aopcde == 10)
3630 {
4b7f6baa 3631 OUTS (outf, dregs_lo (dst0));
086134ec 3632 OUTS (outf, " = A1.X");
4b7f6baa
CM		 3633 }
3634 else if (aop == 1 && aopcde == 0)
3635 {
4b7f6baa 3636 OUTS (outf, dregs (dst0));
086134ec 3637 OUTS (outf, " = ");
4b7f6baa 3638 OUTS (outf, dregs (src0));
086134ec 3639 OUTS (outf, " +|- ");
4b7f6baa 3640 OUTS (outf, dregs (src1));
4b7f6baa 3641 amod0 (s, x, outf);
4b7f6baa
CM		 3642 }
3643 else if (aop == 3 && aopcde == 0)
3644 {
4b7f6baa 3645 OUTS (outf, dregs (dst0));
086134ec 3646 OUTS (outf, " = ");
4b7f6baa 3647 OUTS (outf, dregs (src0));
086134ec 3648 OUTS (outf, " -|- ");
4b7f6baa 3649 OUTS (outf, dregs (src1));
4b7f6baa 3650 amod0 (s, x, outf);
4b7f6baa
CM		 3651 }
3652 else if (aop == 1 && aopcde == 4)
3653 {
4b7f6baa 3654 OUTS (outf, dregs (dst0));
086134ec 3655 OUTS (outf, " = ");
4b7f6baa 3656 OUTS (outf, dregs (src0));
086134ec 3657 OUTS (outf, " - ");
4b7f6baa 3658 OUTS (outf, dregs (src1));
4b7f6baa 3659 amod1 (s, x, outf);
4b7f6baa
CM		 3660 }
3661 else if (aop == 0 && aopcde == 17)
3662 {
4b7f6baa 3663 OUTS (outf, dregs (dst1));
086134ec 3664 OUTS (outf, " = A1 + A0, ");
4b7f6baa 3665 OUTS (outf, dregs (dst0));
086134ec 3666 OUTS (outf, " = A1 - A0");
4b7f6baa 3667 amod1 (s, x, outf);
4b7f6baa
CM		 3668 }
3669 else if (aop == 1 && aopcde == 17)
3670 {
4b7f6baa 3671 OUTS (outf, dregs (dst1));
086134ec 3672 OUTS (outf, " = A0 + A1, ");
4b7f6baa 3673 OUTS (outf, dregs (dst0));
086134ec 3674 OUTS (outf, " = A0 - A1");
4b7f6baa 3675 amod1 (s, x, outf);
4b7f6baa
CM		 3676 }
3677 else if (aop == 0 && aopcde == 18)
3678 {
086134ec 3679 OUTS (outf, "SAA (");
4b7f6baa
CM		 3680 OUTS (outf, dregs (src0 + 1));
3681 OUTS (outf, ":");
086134ec
BS		 3682 OUTS (outf, imm5d (src0));
3683 OUTS (outf, ", ");
4b7f6baa
CM		 3684 OUTS (outf, dregs (src1 + 1));
3685 OUTS (outf, ":");
086134ec
BS		 3686 OUTS (outf, imm5d (src1));
3687 OUTS (outf, ")");
4b7f6baa 3688 aligndir (s, outf);
4b7f6baa
CM		 3689 }
3690 else if (aop == 3 && aopcde == 18)
b7d48530
NC		 3691 OUTS (outf, "DISALGNEXCPT");
3692
4b7f6baa
CM		 3693 else if (aop == 0 && aopcde == 20)
3694 {
4b7f6baa 3695 OUTS (outf, dregs (dst0));
086134ec 3696 OUTS (outf, " = BYTEOP1P (");
4b7f6baa
CM		 3697 OUTS (outf, dregs (src0 + 1));
3698 OUTS (outf, ":");
086134ec
BS		 3699 OUTS (outf, imm5d (src0));
3700 OUTS (outf, ", ");
4b7f6baa
CM		 3701 OUTS (outf, dregs (src1 + 1));
3702 OUTS (outf, ":");
086134ec 3703 OUTS (outf, imm5d (src1));
4b7f6baa
CM		 3704 OUTS (outf, ")");
3705 aligndir (s, outf);
4b7f6baa
CM		 3706 }
3707 else if (aop == 1 && aopcde == 20)
3708 {
4b7f6baa 3709 OUTS (outf, dregs (dst0));
086134ec 3710 OUTS (outf, " = BYTEOP1P (");
4b7f6baa
CM		 3711 OUTS (outf, dregs (src0 + 1));
3712 OUTS (outf, ":");
086134ec
BS		 3713 OUTS (outf, imm5d (src0));
3714 OUTS (outf, ", ");
4b7f6baa
CM		 3715 OUTS (outf, dregs (src1 + 1));
3716 OUTS (outf, ":");
086134ec
BS		 3717 OUTS (outf, imm5d (src1));
3718 OUTS (outf, ") (T");
4b7f6baa
CM		 3719 if (s == 1)
3720 OUTS (outf, ", R)");
3721 else
3722 OUTS (outf, ")");
4b7f6baa
CM		 3723 }
3724 else if (aop == 0 && aopcde == 21)
3725 {
4b7f6baa
CM		 3726 OUTS (outf, "(");
3727 OUTS (outf, dregs (dst1));
086134ec 3728 OUTS (outf, ", ");
4b7f6baa 3729 OUTS (outf, dregs (dst0));
086134ec 3730 OUTS (outf, ") = BYTEOP16P (");
4b7f6baa
CM		 3731 OUTS (outf, dregs (src0 + 1));
3732 OUTS (outf, ":");
086134ec
BS		 3733 OUTS (outf, imm5d (src0));
3734 OUTS (outf, ", ");
4b7f6baa
CM		 3735 OUTS (outf, dregs (src1 + 1));
3736 OUTS (outf, ":");
086134ec
BS		 3737 OUTS (outf, imm5d (src1));
3738 OUTS (outf, ")");
4b7f6baa 3739 aligndir (s, outf);
4b7f6baa
CM		 3740 }
3741 else if (aop == 1 && aopcde == 21)
3742 {
4b7f6baa
CM		 3743 OUTS (outf, "(");
3744 OUTS (outf, dregs (dst1));
086134ec 3745 OUTS (outf, ", ");
4b7f6baa 3746 OUTS (outf, dregs (dst0));
086134ec 3747 OUTS (outf, ") = BYTEOP16M (");
4b7f6baa
CM		 3748 OUTS (outf, dregs (src0 + 1));
3749 OUTS (outf, ":");
086134ec
BS		 3750 OUTS (outf, imm5d (src0));
3751 OUTS (outf, ", ");
4b7f6baa
CM		 3752 OUTS (outf, dregs (src1 + 1));
3753 OUTS (outf, ":");
086134ec
BS		 3754 OUTS (outf, imm5d (src1));
3755 OUTS (outf, ")");
4b7f6baa 3756 aligndir (s, outf);
4b7f6baa
CM		 3757 }
3758 else if (aop == 2 && aopcde == 7)
3759 {
4b7f6baa 3760 OUTS (outf, dregs (dst0));
086134ec 3761 OUTS (outf, " = ABS ");
4b7f6baa 3762 OUTS (outf, dregs (src0));
4b7f6baa
CM		 3763 }
3764 else if (aop == 1 && aopcde == 7)
3765 {
4b7f6baa 3766 OUTS (outf, dregs (dst0));
086134ec 3767 OUTS (outf, " = MIN (");
4b7f6baa 3768 OUTS (outf, dregs (src0));
086134ec 3769 OUTS (outf, ", ");
4b7f6baa
CM		 3770 OUTS (outf, dregs (src1));
3771 OUTS (outf, ")");
4b7f6baa
CM		 3772 }
3773 else if (aop == 0 && aopcde == 7)
3774 {
4b7f6baa 3775 OUTS (outf, dregs (dst0));
086134ec 3776 OUTS (outf, " = MAX (");
4b7f6baa 3777 OUTS (outf, dregs (src0));
086134ec 3778 OUTS (outf, ", ");
4b7f6baa
CM		 3779 OUTS (outf, dregs (src1));
3780 OUTS (outf, ")");
4b7f6baa
CM		 3781 }
3782 else if (aop == 2 && aopcde == 6)
3783 {
4b7f6baa 3784 OUTS (outf, dregs (dst0));
086134ec 3785 OUTS (outf, " = ABS ");
4b7f6baa 3786 OUTS (outf, dregs (src0));
086134ec 3787 OUTS (outf, " (V)");
4b7f6baa
CM		 3788 }
3789 else if (aop == 1 && aopcde == 6)
3790 {
4b7f6baa 3791 OUTS (outf, dregs (dst0));
086134ec 3792 OUTS (outf, " = MIN (");
4b7f6baa 3793 OUTS (outf, dregs (src0));
086134ec 3794 OUTS (outf, ", ");
4b7f6baa 3795 OUTS (outf, dregs (src1));
086134ec 3796 OUTS (outf, ") (V)");
4b7f6baa
CM		 3797 }
3798 else if (aop == 0 && aopcde == 6)
3799 {
4b7f6baa 3800 OUTS (outf, dregs (dst0));
086134ec 3801 OUTS (outf, " = MAX (");
4b7f6baa 3802 OUTS (outf, dregs (src0));
086134ec 3803 OUTS (outf, ", ");
4b7f6baa 3804 OUTS (outf, dregs (src1));
086134ec 3805 OUTS (outf, ") (V)");
4b7f6baa
CM		 3806 }
3807 else if (HL == 1 && aopcde == 1)
3808 {
4b7f6baa 3809 OUTS (outf, dregs (dst1));
086134ec 3810 OUTS (outf, " = ");
4b7f6baa 3811 OUTS (outf, dregs (src0));
086134ec 3812 OUTS (outf, " +|- ");
4b7f6baa 3813 OUTS (outf, dregs (src1));
086134ec 3814 OUTS (outf, ", ");
4b7f6baa 3815 OUTS (outf, dregs (dst0));
086134ec 3816 OUTS (outf, " = ");
4b7f6baa 3817 OUTS (outf, dregs (src0));
086134ec 3818 OUTS (outf, " -|+ ");
4b7f6baa
CM		 3819 OUTS (outf, dregs (src1));
3820 amod0amod2 (s, x, aop, outf);
4b7f6baa
CM		 3821 }
3822 else if (aop == 0 && aopcde == 4)
3823 {
4b7f6baa 3824 OUTS (outf, dregs (dst0));
086134ec 3825 OUTS (outf, " = ");
4b7f6baa 3826 OUTS (outf, dregs (src0));
086134ec 3827 OUTS (outf, " + ");
4b7f6baa 3828 OUTS (outf, dregs (src1));
4b7f6baa 3829 amod1 (s, x, outf);
4b7f6baa
CM		 3830 }
3831 else if (aop == 0 && aopcde == 0)
3832 {
4b7f6baa 3833 OUTS (outf, dregs (dst0));
086134ec 3834 OUTS (outf, " = ");
4b7f6baa 3835 OUTS (outf, dregs (src0));
086134ec 3836 OUTS (outf, " +|+ ");
4b7f6baa 3837 OUTS (outf, dregs (src1));
4b7f6baa 3838 amod0 (s, x, outf);
4b7f6baa
CM		 3839 }
3840 else if (aop == 0 && aopcde == 24)
3841 {
4b7f6baa 3842 OUTS (outf, dregs (dst0));
086134ec 3843 OUTS (outf, " = BYTEPACK (");
4b7f6baa 3844 OUTS (outf, dregs (src0));
086134ec 3845 OUTS (outf, ", ");
4b7f6baa
CM		 3846 OUTS (outf, dregs (src1));
3847 OUTS (outf, ")");
4b7f6baa
CM		 3848 }
3849 else if (aop == 1 && aopcde == 24)
3850 {
4b7f6baa
CM		 3851 OUTS (outf, "(");
3852 OUTS (outf, dregs (dst1));
086134ec 3853 OUTS (outf, ", ");
4b7f6baa
CM		 3854 OUTS (outf, dregs (dst0));
3855 OUTS (outf, ") = BYTEUNPACK ");
3856 OUTS (outf, dregs (src0 + 1));
3857 OUTS (outf, ":");
086134ec 3858 OUTS (outf, imm5d (src0));
4b7f6baa 3859 aligndir (s, outf);
4b7f6baa
CM		 3860 }
3861 else if (aopcde == 13)
3862 {
4b7f6baa
CM		 3863 OUTS (outf, "(");
3864 OUTS (outf, dregs (dst1));
086134ec 3865 OUTS (outf, ", ");
4b7f6baa
CM		 3866 OUTS (outf, dregs (dst0));
3867 OUTS (outf, ") = SEARCH ");
3868 OUTS (outf, dregs (src0));
086134ec 3869 OUTS (outf, " (");
4b7f6baa
CM		 3870 searchmod (aop, outf);
3871 OUTS (outf, ")");
4b7f6baa
CM		 3872 }
3873 else
b7d48530
NC		 3874 return 0;
3875
3876 return 4;
4b7f6baa
CM		 3877}
3878
3879static int
3880decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3881{
b7d48530
NC		 3882 /* dsp32shift
3883 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3884 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3885 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3886 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 3887 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
3888 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
3889 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
3890 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
3891 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
3892 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
3893 const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
3894
4b7f6baa
CM		 3895 if (HLs == 0 && sop == 0 && sopcde == 0)
3896 {
4b7f6baa 3897 OUTS (outf, dregs_lo (dst0));
086134ec 3898 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3899 OUTS (outf, dregs_lo (src1));
3900 OUTS (outf, " BY ");
3901 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3902 }
3903 else if (HLs == 1 && sop == 0 && sopcde == 0)
3904 {
4b7f6baa 3905 OUTS (outf, dregs_lo (dst0));
086134ec 3906 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3907 OUTS (outf, dregs_hi (src1));
3908 OUTS (outf, " BY ");
3909 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3910 }
3911 else if (HLs == 2 && sop == 0 && sopcde == 0)
3912 {
4b7f6baa 3913 OUTS (outf, dregs_hi (dst0));
086134ec 3914 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3915 OUTS (outf, dregs_lo (src1));
3916 OUTS (outf, " BY ");
3917 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3918 }
3919 else if (HLs == 3 && sop == 0 && sopcde == 0)
3920 {
4b7f6baa 3921 OUTS (outf, dregs_hi (dst0));
086134ec 3922 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3923 OUTS (outf, dregs_hi (src1));
3924 OUTS (outf, " BY ");
3925 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3926 }
3927 else if (HLs == 0 && sop == 1 && sopcde == 0)
3928 {
4b7f6baa 3929 OUTS (outf, dregs_lo (dst0));
086134ec 3930 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3931 OUTS (outf, dregs_lo (src1));
3932 OUTS (outf, " BY ");
3933 OUTS (outf, dregs_lo (src0));
086134ec 3934 OUTS (outf, " (S)");
4b7f6baa
CM		 3935 }
3936 else if (HLs == 1 && sop == 1 && sopcde == 0)
3937 {
4b7f6baa 3938 OUTS (outf, dregs_lo (dst0));
086134ec 3939 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3940 OUTS (outf, dregs_hi (src1));
3941 OUTS (outf, " BY ");
3942 OUTS (outf, dregs_lo (src0));
086134ec 3943 OUTS (outf, " (S)");
4b7f6baa
CM		 3944 }
3945 else if (HLs == 2 && sop == 1 && sopcde == 0)
3946 {
4b7f6baa 3947 OUTS (outf, dregs_hi (dst0));
086134ec 3948 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3949 OUTS (outf, dregs_lo (src1));
3950 OUTS (outf, " BY ");
3951 OUTS (outf, dregs_lo (src0));
086134ec 3952 OUTS (outf, " (S)");
4b7f6baa
CM		 3953 }
3954 else if (HLs == 3 && sop == 1 && sopcde == 0)
3955 {
4b7f6baa 3956 OUTS (outf, dregs_hi (dst0));
086134ec 3957 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3958 OUTS (outf, dregs_hi (src1));
3959 OUTS (outf, " BY ");
3960 OUTS (outf, dregs_lo (src0));
086134ec 3961 OUTS (outf, " (S)");
4b7f6baa
CM		 3962 }
3963 else if (sop == 2 && sopcde == 0)
3964 {
4b7f6baa 3965 OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
086134ec 3966 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 3967 OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
3968 OUTS (outf, " BY ");
3969 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3970 }
3971 else if (sop == 0 && sopcde == 3)
3972 {
4b7f6baa 3973 OUTS (outf, acc01);
086134ec 3974 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3975 OUTS (outf, acc01);
3976 OUTS (outf, " BY ");
3977 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3978 }
3979 else if (sop == 1 && sopcde == 3)
3980 {
4b7f6baa 3981 OUTS (outf, acc01);
086134ec 3982 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 3983 OUTS (outf, acc01);
3984 OUTS (outf, " BY ");
3985 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3986 }
3987 else if (sop == 2 && sopcde == 3)
3988 {
4b7f6baa 3989 OUTS (outf, acc01);
086134ec 3990 OUTS (outf, " = ROT ");
4b7f6baa
CM		 3991 OUTS (outf, acc01);
3992 OUTS (outf, " BY ");
3993 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3994 }
3995 else if (sop == 3 && sopcde == 3)
3996 {
4b7f6baa 3997 OUTS (outf, dregs (dst0));
086134ec 3998 OUTS (outf, " = ROT ");
4b7f6baa
CM		 3999 OUTS (outf, dregs (src1));
4000 OUTS (outf, " BY ");
4001 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4002 }
4003 else if (sop == 1 && sopcde == 1)
4004 {
4b7f6baa 4005 OUTS (outf, dregs (dst0));
086134ec 4006 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4007 OUTS (outf, dregs (src1));
4008 OUTS (outf, " BY ");
4009 OUTS (outf, dregs_lo (src0));
086134ec 4010 OUTS (outf, " (V, S)");
4b7f6baa
CM		 4011 }
4012 else if (sop == 0 && sopcde == 1)
4013 {
4b7f6baa 4014 OUTS (outf, dregs (dst0));
086134ec 4015 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4016 OUTS (outf, dregs (src1));
4017 OUTS (outf, " BY ");
4018 OUTS (outf, dregs_lo (src0));
086134ec 4019 OUTS (outf, " (V)");
4b7f6baa
CM		 4020 }
4021 else if (sop == 0 && sopcde == 2)
4022 {
4b7f6baa 4023 OUTS (outf, dregs (dst0));
086134ec 4024 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4025 OUTS (outf, dregs (src1));
4026 OUTS (outf, " BY ");
4027 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4028 }
4029 else if (sop == 1 && sopcde == 2)
4030 {
4b7f6baa 4031 OUTS (outf, dregs (dst0));
086134ec 4032 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4033 OUTS (outf, dregs (src1));
4034 OUTS (outf, " BY ");
4035 OUTS (outf, dregs_lo (src0));
086134ec 4036 OUTS (outf, " (S)");
4b7f6baa
CM		 4037 }
4038 else if (sop == 2 && sopcde == 2)
4039 {
4b7f6baa 4040 OUTS (outf, dregs (dst0));
59a82d23 4041 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 4042 OUTS (outf, dregs (src1));
4043 OUTS (outf, " BY ");
4044 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4045 }
4046 else if (sop == 3 && sopcde == 2)
4047 {
4b7f6baa 4048 OUTS (outf, dregs (dst0));
086134ec 4049 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4050 OUTS (outf, dregs (src1));
4051 OUTS (outf, " BY ");
4052 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4053 }
4054 else if (sop == 2 && sopcde == 1)
4055 {
4b7f6baa 4056 OUTS (outf, dregs (dst0));
59a82d23 4057 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 4058 OUTS (outf, dregs (src1));
4059 OUTS (outf, " BY ");
4060 OUTS (outf, dregs_lo (src0));
086134ec 4061 OUTS (outf, " (V)");
4b7f6baa
CM		 4062 }
4063 else if (sop == 0 && sopcde == 4)
4064 {
4b7f6baa 4065 OUTS (outf, dregs (dst0));
086134ec 4066 OUTS (outf, " = PACK (");
4b7f6baa 4067 OUTS (outf, dregs_lo (src1));
086134ec 4068 OUTS (outf, ", ");
4b7f6baa
CM		 4069 OUTS (outf, dregs_lo (src0));
4070 OUTS (outf, ")");
4b7f6baa
CM		 4071 }
4072 else if (sop == 1 && sopcde == 4)
4073 {
4b7f6baa 4074 OUTS (outf, dregs (dst0));
086134ec 4075 OUTS (outf, " = PACK (");
4b7f6baa 4076 OUTS (outf, dregs_lo (src1));
086134ec 4077 OUTS (outf, ", ");
4b7f6baa
CM		 4078 OUTS (outf, dregs_hi (src0));
4079 OUTS (outf, ")");
4b7f6baa
CM		 4080 }
4081 else if (sop == 2 && sopcde == 4)
4082 {
4b7f6baa 4083 OUTS (outf, dregs (dst0));
086134ec 4084 OUTS (outf, " = PACK (");
4b7f6baa 4085 OUTS (outf, dregs_hi (src1));
086134ec 4086 OUTS (outf, ", ");
4b7f6baa
CM		 4087 OUTS (outf, dregs_lo (src0));
4088 OUTS (outf, ")");
4b7f6baa
CM		 4089 }
4090 else if (sop == 3 && sopcde == 4)
4091 {
4b7f6baa 4092 OUTS (outf, dregs (dst0));
086134ec 4093 OUTS (outf, " = PACK (");
4b7f6baa 4094 OUTS (outf, dregs_hi (src1));
086134ec 4095 OUTS (outf, ", ");
4b7f6baa
CM		 4096 OUTS (outf, dregs_hi (src0));
4097 OUTS (outf, ")");
4b7f6baa
CM		 4098 }
4099 else if (sop == 0 && sopcde == 5)
4100 {
4b7f6baa 4101 OUTS (outf, dregs_lo (dst0));
086134ec 4102 OUTS (outf, " = SIGNBITS ");
4b7f6baa 4103 OUTS (outf, dregs (src1));
4b7f6baa
CM		 4104 }
4105 else if (sop == 1 && sopcde == 5)
4106 {
4b7f6baa 4107 OUTS (outf, dregs_lo (dst0));
086134ec 4108 OUTS (outf, " = SIGNBITS ");
4b7f6baa 4109 OUTS (outf, dregs_lo (src1));
4b7f6baa
CM		 4110 }
4111 else if (sop == 2 && sopcde == 5)
4112 {
4b7f6baa 4113 OUTS (outf, dregs_lo (dst0));
086134ec 4114 OUTS (outf, " = SIGNBITS ");
4b7f6baa 4115 OUTS (outf, dregs_hi (src1));
4b7f6baa
CM		 4116 }
4117 else if (sop == 0 && sopcde == 6)
4118 {
4b7f6baa 4119 OUTS (outf, dregs_lo (dst0));
086134ec 4120 OUTS (outf, " = SIGNBITS A0");
4b7f6baa
CM		 4121 }
4122 else if (sop == 1 && sopcde == 6)
4123 {
4b7f6baa 4124 OUTS (outf, dregs_lo (dst0));
086134ec 4125 OUTS (outf, " = SIGNBITS A1");
4b7f6baa
CM		 4126 }
4127 else if (sop == 3 && sopcde == 6)
4128 {
4b7f6baa 4129 OUTS (outf, dregs_lo (dst0));
086134ec 4130 OUTS (outf, " = ONES ");
4b7f6baa 4131 OUTS (outf, dregs (src1));
4b7f6baa
CM		 4132 }
4133 else if (sop == 0 && sopcde == 7)
4134 {
4b7f6baa 4135 OUTS (outf, dregs_lo (dst0));
086134ec 4136 OUTS (outf, " = EXPADJ (");
4b7f6baa 4137 OUTS (outf, dregs (src1));
086134ec 4138 OUTS (outf, ", ");
4b7f6baa
CM		 4139 OUTS (outf, dregs_lo (src0));
4140 OUTS (outf, ")");
4b7f6baa
CM		 4141 }
4142 else if (sop == 1 && sopcde == 7)
4143 {
4b7f6baa 4144 OUTS (outf, dregs_lo (dst0));
086134ec 4145 OUTS (outf, " = EXPADJ (");
4b7f6baa 4146 OUTS (outf, dregs (src1));
086134ec 4147 OUTS (outf, ", ");
4b7f6baa
CM		 4148 OUTS (outf, dregs_lo (src0));
4149 OUTS (outf, ") (V)");
4b7f6baa
CM		 4150 }
4151 else if (sop == 2 && sopcde == 7)
4152 {
4b7f6baa 4153 OUTS (outf, dregs_lo (dst0));
086134ec 4154 OUTS (outf, " = EXPADJ (");
4b7f6baa 4155 OUTS (outf, dregs_lo (src1));
086134ec 4156 OUTS (outf, ", ");
4b7f6baa
CM		 4157 OUTS (outf, dregs_lo (src0));
4158 OUTS (outf, ")");
4b7f6baa
CM		 4159 }
4160 else if (sop == 3 && sopcde == 7)
4161 {
4b7f6baa 4162 OUTS (outf, dregs_lo (dst0));
086134ec 4163 OUTS (outf, " = EXPADJ (");
4b7f6baa 4164 OUTS (outf, dregs_hi (src1));
086134ec 4165 OUTS (outf, ", ");
4b7f6baa
CM		 4166 OUTS (outf, dregs_lo (src0));
4167 OUTS (outf, ")");
4b7f6baa
CM		 4168 }
4169 else if (sop == 0 && sopcde == 8)
4170 {
4b7f6baa
CM		 4171 OUTS (outf, "BITMUX (");
4172 OUTS (outf, dregs (src0));
086134ec 4173 OUTS (outf, ", ");
4b7f6baa 4174 OUTS (outf, dregs (src1));
086134ec 4175 OUTS (outf, ", A0) (ASR)");
4b7f6baa
CM		 4176 }
4177 else if (sop == 1 && sopcde == 8)
4178 {
4b7f6baa
CM		 4179 OUTS (outf, "BITMUX (");
4180 OUTS (outf, dregs (src0));
086134ec 4181 OUTS (outf, ", ");
4b7f6baa 4182 OUTS (outf, dregs (src1));
086134ec 4183 OUTS (outf, ", A0) (ASL)");
4b7f6baa
CM		 4184 }
4185 else if (sop == 0 && sopcde == 9)
4186 {
4b7f6baa 4187 OUTS (outf, dregs_lo (dst0));
086134ec 4188 OUTS (outf, " = VIT_MAX (");
4b7f6baa
CM		 4189 OUTS (outf, dregs (src1));
4190 OUTS (outf, ") (ASL)");
4b7f6baa
CM		 4191 }
4192 else if (sop == 1 && sopcde == 9)
4193 {
4b7f6baa 4194 OUTS (outf, dregs_lo (dst0));
086134ec 4195 OUTS (outf, " = VIT_MAX (");
4b7f6baa
CM		 4196 OUTS (outf, dregs (src1));
4197 OUTS (outf, ") (ASR)");
4b7f6baa
CM		 4198 }
4199 else if (sop == 2 && sopcde == 9)
4200 {
4b7f6baa 4201 OUTS (outf, dregs (dst0));
086134ec 4202 OUTS (outf, " = VIT_MAX (");
4b7f6baa 4203 OUTS (outf, dregs (src1));
086134ec 4204 OUTS (outf, ", ");
4b7f6baa 4205 OUTS (outf, dregs (src0));
086134ec 4206 OUTS (outf, ") (ASL)");
4b7f6baa
CM		 4207 }
4208 else if (sop == 3 && sopcde == 9)
4209 {
4b7f6baa 4210 OUTS (outf, dregs (dst0));
086134ec 4211 OUTS (outf, " = VIT_MAX (");
4b7f6baa 4212 OUTS (outf, dregs (src1));
086134ec 4213 OUTS (outf, ", ");
4b7f6baa 4214 OUTS (outf, dregs (src0));
086134ec 4215 OUTS (outf, ") (ASR)");
4b7f6baa
CM		 4216 }
4217 else if (sop == 0 && sopcde == 10)
4218 {
4b7f6baa 4219 OUTS (outf, dregs (dst0));
086134ec 4220 OUTS (outf, " = EXTRACT (");
4b7f6baa 4221 OUTS (outf, dregs (src1));
086134ec 4222 OUTS (outf, ", ");
4b7f6baa
CM		 4223 OUTS (outf, dregs_lo (src0));
4224 OUTS (outf, ") (Z)");
4b7f6baa
CM		 4225 }
4226 else if (sop == 1 && sopcde == 10)
4227 {
4b7f6baa 4228 OUTS (outf, dregs (dst0));
086134ec 4229 OUTS (outf, " = EXTRACT (");
4b7f6baa 4230 OUTS (outf, dregs (src1));
086134ec 4231 OUTS (outf, ", ");
4b7f6baa 4232 OUTS (outf, dregs_lo (src0));
086134ec 4233 OUTS (outf, ") (X)");
4b7f6baa
CM		 4234 }
4235 else if (sop == 2 && sopcde == 10)
4236 {
4b7f6baa 4237 OUTS (outf, dregs (dst0));
086134ec 4238 OUTS (outf, " = DEPOSIT (");
4b7f6baa 4239 OUTS (outf, dregs (src1));
086134ec 4240 OUTS (outf, ", ");
4b7f6baa
CM		 4241 OUTS (outf, dregs (src0));
4242 OUTS (outf, ")");
4b7f6baa
CM		 4243 }
4244 else if (sop == 3 && sopcde == 10)
4245 {
4b7f6baa 4246 OUTS (outf, dregs (dst0));
086134ec 4247 OUTS (outf, " = DEPOSIT (");
4b7f6baa 4248 OUTS (outf, dregs (src1));
086134ec 4249 OUTS (outf, ", ");
4b7f6baa 4250 OUTS (outf, dregs (src0));
086134ec 4251 OUTS (outf, ") (X)");
4b7f6baa
CM		 4252 }
4253 else if (sop == 0 && sopcde == 11)
4254 {
4b7f6baa 4255 OUTS (outf, dregs_lo (dst0));
086134ec 4256 OUTS (outf, " = CC = BXORSHIFT (A0, ");
4b7f6baa
CM		 4257 OUTS (outf, dregs (src0));
4258 OUTS (outf, ")");
4b7f6baa
CM		 4259 }
4260 else if (sop == 1 && sopcde == 11)
4261 {
4b7f6baa 4262 OUTS (outf, dregs_lo (dst0));
086134ec 4263 OUTS (outf, " = CC = BXOR (A0, ");
4b7f6baa
CM		 4264 OUTS (outf, dregs (src0));
4265 OUTS (outf, ")");
4b7f6baa
CM		 4266 }
4267 else if (sop == 0 && sopcde == 12)
086134ec 4268 OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
b7d48530 4269
4b7f6baa
CM		 4270 else if (sop == 1 && sopcde == 12)
4271 {
4b7f6baa 4272 OUTS (outf, dregs_lo (dst0));
086134ec 4273 OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4b7f6baa
CM		 4274 }
4275 else if (sop == 0 && sopcde == 13)
4276 {
4b7f6baa 4277 OUTS (outf, dregs (dst0));
086134ec 4278 OUTS (outf, " = ALIGN8 (");
4b7f6baa 4279 OUTS (outf, dregs (src1));
086134ec 4280 OUTS (outf, ", ");
4b7f6baa
CM		 4281 OUTS (outf, dregs (src0));
4282 OUTS (outf, ")");
4b7f6baa
CM		 4283 }
4284 else if (sop == 1 && sopcde == 13)
4285 {
4b7f6baa 4286 OUTS (outf, dregs (dst0));
086134ec 4287 OUTS (outf, " = ALIGN16 (");
4b7f6baa 4288 OUTS (outf, dregs (src1));
086134ec 4289 OUTS (outf, ", ");
4b7f6baa
CM		 4290 OUTS (outf, dregs (src0));
4291 OUTS (outf, ")");
4b7f6baa
CM		 4292 }
4293 else if (sop == 2 && sopcde == 13)
4294 {
4b7f6baa 4295 OUTS (outf, dregs (dst0));
086134ec 4296 OUTS (outf, " = ALIGN24 (");
4b7f6baa 4297 OUTS (outf, dregs (src1));
086134ec 4298 OUTS (outf, ", ");
4b7f6baa
CM		 4299 OUTS (outf, dregs (src0));
4300 OUTS (outf, ")");
4b7f6baa
CM		 4301 }
4302 else
b7d48530
NC		 4303 return 0;
4304
4305 return 4;
4b7f6baa
CM		 4306}
4307
4308static int
4309decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4310{
b7d48530
NC		 4311 /* dsp32shiftimm
4312 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4313 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4314 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4315 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4316 int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4317 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4318 int bit8 = ((iw1 >> 8) & 0x1);
4319 int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4b7f6baa 4320 int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
b7d48530
NC		 4321 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4322 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4323 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4b7f6baa 4324
331f1cbe 4325 if (sop == 0 && sopcde == 0)
4b7f6baa 4326 {
331f1cbe
BS		 4327 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4328 OUTS (outf, " = ");
4329 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4330 OUTS (outf, " >>> ");
4b7f6baa 4331 OUTS (outf, uimm4 (newimmag));
4b7f6baa 4332 }
331f1cbe 4333 else if (sop == 1 && sopcde == 0 && bit8 == 0)
4b7f6baa 4334 {
331f1cbe
BS		 4335 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4336 OUTS (outf, " = ");
4337 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4338 OUTS (outf, " << ");
4b7f6baa 4339 OUTS (outf, uimm4 (immag));
331f1cbe 4340 OUTS (outf, " (S)");
4b7f6baa 4341 }
331f1cbe 4342 else if (sop == 1 && sopcde == 0 && bit8 == 1)
4b7f6baa 4343 {
331f1cbe
BS		 4344 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4345 OUTS (outf, " = ");
4346 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4347 OUTS (outf, " >>> ");
4b7f6baa 4348 OUTS (outf, uimm4 (newimmag));
331f1cbe 4349 OUTS (outf, " (S)");
4b7f6baa 4350 }
331f1cbe 4351 else if (sop == 2 && sopcde == 0 && bit8 == 0)
4b7f6baa 4352 {
331f1cbe
BS		 4353 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4354 OUTS (outf, " = ");
4355 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4356 OUTS (outf, " << ");
4b7f6baa 4357 OUTS (outf, uimm4 (immag));
4b7f6baa 4358 }
331f1cbe 4359 else if (sop == 2 && sopcde == 0 && bit8 == 1)
4b7f6baa 4360 {
331f1cbe
BS		 4361 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4362 OUTS (outf, " = ");
4363 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4364 OUTS (outf, " >> ");
4b7f6baa 4365 OUTS (outf, uimm4 (newimmag));
4b7f6baa 4366 }
4b7f6baa
CM		 4367 else if (sop == 2 && sopcde == 3 && HLs == 1)
4368 {
086134ec 4369 OUTS (outf, "A1 = ROT A1 BY ");
4b7f6baa 4370 OUTS (outf, imm6 (immag));
4b7f6baa
CM		 4371 }
4372 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4373 {
086134ec 4374 OUTS (outf, "A0 = A0 << ");
4b7f6baa 4375 OUTS (outf, uimm5 (immag));
4b7f6baa
CM		 4376 }
4377 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4378 {
086134ec 4379 OUTS (outf, "A0 = A0 >>> ");
4b7f6baa 4380 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4381 }
4382 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4383 {
086134ec 4384 OUTS (outf, "A1 = A1 << ");
4b7f6baa 4385 OUTS (outf, uimm5 (immag));
4b7f6baa
CM		 4386 }
4387 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4388 {
086134ec 4389 OUTS (outf, "A1 = A1 >>> ");
4b7f6baa 4390 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4391 }
4392 else if (sop == 1 && sopcde == 3 && HLs == 0)
4393 {
086134ec 4394 OUTS (outf, "A0 = A0 >> ");
4b7f6baa 4395 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4396 }
4397 else if (sop == 1 && sopcde == 3 && HLs == 1)
4398 {
086134ec 4399 OUTS (outf, "A1 = A1 >> ");
4b7f6baa 4400 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4401 }
4402 else if (sop == 2 && sopcde == 3 && HLs == 0)
4403 {
086134ec 4404 OUTS (outf, "A0 = ROT A0 BY ");
4b7f6baa 4405 OUTS (outf, imm6 (immag));
4b7f6baa
CM		 4406 }
4407 else if (sop == 1 && sopcde == 1 && bit8 == 0)
4408 {
4b7f6baa 4409 OUTS (outf, dregs (dst0));
086134ec 4410 OUTS (outf, " = ");
4b7f6baa 4411 OUTS (outf, dregs (src1));
086134ec 4412 OUTS (outf, " << ");
4b7f6baa
CM		 4413 OUTS (outf, uimm5 (immag));
4414 OUTS (outf, " (V, S)");
4b7f6baa
CM		 4415 }
4416 else if (sop == 1 && sopcde == 1 && bit8 == 1)
4417 {
4b7f6baa 4418 OUTS (outf, dregs (dst0));
086134ec 4419 OUTS (outf, " = ");
4b7f6baa 4420 OUTS (outf, dregs (src1));
086134ec 4421 OUTS (outf, " >>> ");
4b7f6baa 4422 OUTS (outf, imm5 (-immag));
0b7691fd 4423 OUTS (outf, " (V, S)");
4b7f6baa
CM		 4424 }
4425 else if (sop == 2 && sopcde == 1 && bit8 == 1)
4426 {
4b7f6baa 4427 OUTS (outf, dregs (dst0));
086134ec 4428 OUTS (outf, " = ");
4b7f6baa
CM		 4429 OUTS (outf, dregs (src1));
4430 OUTS (outf, " >> ");
4431 OUTS (outf, uimm5 (newimmag));
4432 OUTS (outf, " (V)");
4b7f6baa
CM		 4433 }
4434 else if (sop == 2 && sopcde == 1 && bit8 == 0)
4435 {
4b7f6baa 4436 OUTS (outf, dregs (dst0));
086134ec 4437 OUTS (outf, " = ");
4b7f6baa 4438 OUTS (outf, dregs (src1));
086134ec 4439 OUTS (outf, " << ");
4b7f6baa
CM		 4440 OUTS (outf, imm5 (immag));
4441 OUTS (outf, " (V)");
4b7f6baa
CM		 4442 }
4443 else if (sop == 0 && sopcde == 1)
4444 {
4b7f6baa 4445 OUTS (outf, dregs (dst0));
086134ec 4446 OUTS (outf, " = ");
4b7f6baa 4447 OUTS (outf, dregs (src1));
086134ec 4448 OUTS (outf, " >>> ");
4b7f6baa
CM		 4449 OUTS (outf, uimm5 (newimmag));
4450 OUTS (outf, " (V)");
4b7f6baa
CM		 4451 }
4452 else if (sop == 1 && sopcde == 2)
4453 {
4b7f6baa 4454 OUTS (outf, dregs (dst0));
086134ec 4455 OUTS (outf, " = ");
4b7f6baa 4456 OUTS (outf, dregs (src1));
086134ec 4457 OUTS (outf, " << ");
4b7f6baa 4458 OUTS (outf, uimm5 (immag));
086134ec 4459 OUTS (outf, " (S)");
4b7f6baa
CM		 4460 }
4461 else if (sop == 2 && sopcde == 2 && bit8 == 1)
4462 {
4b7f6baa 4463 OUTS (outf, dregs (dst0));
086134ec 4464 OUTS (outf, " = ");
4b7f6baa 4465 OUTS (outf, dregs (src1));
086134ec 4466 OUTS (outf, " >> ");
4b7f6baa 4467 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4468 }
4469 else if (sop == 2 && sopcde == 2 && bit8 == 0)
4470 {
4b7f6baa 4471 OUTS (outf, dregs (dst0));
086134ec 4472 OUTS (outf, " = ");
4b7f6baa 4473 OUTS (outf, dregs (src1));
086134ec 4474 OUTS (outf, " << ");
4b7f6baa 4475 OUTS (outf, uimm5 (immag));
4b7f6baa
CM		 4476 }
4477 else if (sop == 3 && sopcde == 2)
4478 {
4b7f6baa 4479 OUTS (outf, dregs (dst0));
086134ec 4480 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4481 OUTS (outf, dregs (src1));
4482 OUTS (outf, " BY ");
4483 OUTS (outf, imm6 (immag));
4b7f6baa
CM		 4484 }
4485 else if (sop == 0 && sopcde == 2)
4486 {
4b7f6baa 4487 OUTS (outf, dregs (dst0));
086134ec 4488 OUTS (outf, " = ");
4b7f6baa 4489 OUTS (outf, dregs (src1));
086134ec 4490 OUTS (outf, " >>> ");
4b7f6baa 4491 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4492 }
4493 else
b7d48530
NC		 4494 return 0;
4495
4496 return 4;
4b7f6baa
CM		 4497}
4498
4499static int
4500decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4501{
703ec4e8 4502 struct private *priv = outf->private_data;
b7d48530
NC		 4503 /* pseudoDEBUG
4504 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4505 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4506 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 4507 int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4508 int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4509 int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4510
703ec4e8 4511 if (priv->parallel)
219b747a
MF		 4512 return 0;
4513
4b7f6baa 4514 if (reg == 0 && fn == 3)
b7d48530
NC		 4515 OUTS (outf, "DBG A0");
4516
4b7f6baa 4517 else if (reg == 1 && fn == 3)
b7d48530
NC		 4518 OUTS (outf, "DBG A1");
4519
4b7f6baa 4520 else if (reg == 3 && fn == 3)
b7d48530
NC		 4521 OUTS (outf, "ABORT");
4522
4b7f6baa 4523 else if (reg == 4 && fn == 3)
b7d48530
NC		 4524 OUTS (outf, "HLT");
4525
4b7f6baa 4526 else if (reg == 5 && fn == 3)
b7d48530
NC		 4527 OUTS (outf, "DBGHALT");
4528
4b7f6baa
CM		 4529 else if (reg == 6 && fn == 3)
4530 {
086134ec 4531 OUTS (outf, "DBGCMPLX (");
4b7f6baa
CM		 4532 OUTS (outf, dregs (grp));
4533 OUTS (outf, ")");
4b7f6baa
CM		 4534 }
4535 else if (reg == 7 && fn == 3)
b7d48530
NC		 4536 OUTS (outf, "DBG");
4537
4b7f6baa
CM		 4538 else if (grp == 0 && fn == 2)
4539 {
73a63ccf 4540 OUTS (outf, "OUTC ");
4b7f6baa 4541 OUTS (outf, dregs (reg));
4b7f6baa
CM		 4542 }
4543 else if (fn == 0)
4544 {
a01eda85 4545 OUTS (outf, "DBG ");
4b7f6baa 4546 OUTS (outf, allregs (reg, grp));
4b7f6baa
CM		 4547 }
4548 else if (fn == 1)
4549 {
9805c0a5 4550 OUTS (outf, "PRNT ");
4b7f6baa 4551 OUTS (outf, allregs (reg, grp));
4b7f6baa
CM		 4552 }
4553 else
b7d48530
NC		 4554 return 0;
4555
4556 return 2;
4b7f6baa
CM		 4557}
4558
73a63ccf
MF		 4559static int
4560decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
4561{
703ec4e8 4562 struct private *priv = outf->private_data;
73a63ccf
MF		 4563 /* psedoOChar
4564 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4565 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4566 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4567 int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
4568
703ec4e8 4569 if (priv->parallel)
219b747a
MF		 4570 return 0;
4571
73a63ccf
MF		 4572 OUTS (outf, "OUTC ");
4573 OUTS (outf, uimm8 (ch));
4574
4575 return 2;
4576}
4577
4b7f6baa
CM		 4578static int
4579decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4580{
703ec4e8 4581 struct private *priv = outf->private_data;
b7d48530
NC		 4582 /* pseudodbg_assert
4583 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
66a6900a 4584 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
b7d48530
NC		 4585 |.expected......................................................|
4586 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa 4587 int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
b7d48530 4588 int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
66a6900a 4589 int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
b7d48530 4590 int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4b7f6baa 4591
703ec4e8 4592 if (priv->parallel)
219b747a
MF		 4593 return 0;
4594
4b7f6baa
CM		 4595 if (dbgop == 0)
4596 {
086134ec 4597 OUTS (outf, "DBGA (");
66a6900a 4598 OUTS (outf, regs_lo (regtest, grp));
086134ec 4599 OUTS (outf, ", ");
4b7f6baa
CM		 4600 OUTS (outf, uimm16 (expected));
4601 OUTS (outf, ")");
4b7f6baa
CM		 4602 }
4603 else if (dbgop == 1)
4604 {
086134ec 4605 OUTS (outf, "DBGA (");
66a6900a 4606 OUTS (outf, regs_hi (regtest, grp));
086134ec 4607 OUTS (outf, ", ");
4b7f6baa
CM		 4608 OUTS (outf, uimm16 (expected));
4609 OUTS (outf, ")");
4b7f6baa
CM		 4610 }
4611 else if (dbgop == 2)
4612 {
086134ec 4613 OUTS (outf, "DBGAL (");
66a6900a 4614 OUTS (outf, allregs (regtest, grp));
086134ec 4615 OUTS (outf, ", ");
4b7f6baa
CM		 4616 OUTS (outf, uimm16 (expected));
4617 OUTS (outf, ")");
4b7f6baa
CM		 4618 }
4619 else if (dbgop == 3)
4620 {
086134ec 4621 OUTS (outf, "DBGAH (");
66a6900a 4622 OUTS (outf, allregs (regtest, grp));
086134ec 4623 OUTS (outf, ", ");
4b7f6baa
CM		 4624 OUTS (outf, uimm16 (expected));
4625 OUTS (outf, ")");
4b7f6baa
CM		 4626 }
4627 else
b7d48530
NC		 4628 return 0;
4629 return 4;
4b7f6baa
CM		 4630}
4631
ba329817
MF		 4632static int
4633ifetch (bfd_vma pc, disassemble_info *outf, TIword *iw)
4634{
4635 bfd_byte buf[2];
4636 int status;
4637
ed2c4879 4638 status = (*outf->read_memory_func) (pc, buf, 2, outf);
ba329817
MF		 4639 if (status != 0)
4640 {
4641 (*outf->memory_error_func) (status, pc, outf);
4642 return -1;
4643 }
4644
4645 *iw = bfd_getl16 (buf);
4646 return 0;
4647}
4648
ad15c38e 4649static int
4b7f6baa
CM		 4650_print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4651{
703ec4e8 4652 struct private *priv = outf->private_data;
4b7f6baa
CM		 4653 TIword iw0;
4654 TIword iw1;
b7d48530
NC		 4655 int rv = 0;
4656
ed2c4879
MF		 4657 /* The PC must be 16-bit aligned. */
4658 if (pc & 1)
4659 {
4660 OUTS (outf, "ILLEGAL (UNALIGNED)");
4661 /* For people dumping data, just re-align the return value. */
4662 return 1;
4663 }
4664
ba329817
MF		 4665 if (ifetch (pc, outf, &iw0))
4666 return -1;
a4e600b2 4667 priv->iw0 = iw0;
4b7f6baa 4668
bdc4de1b 4669 if (((iw0 & 0xc000) == 0xc000) && ((iw0 & 0xff00) != 0xf800))
ba329817
MF		 4670 {
4671 /* 32-bit insn. */
4672 if (ifetch (pc + 2, outf, &iw1))
4673 return -1;
4674 }
4675 else
4676 /* 16-bit insn. */
4677 iw1 = 0;
4b7f6baa
CM		 4678
4679 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4680 {
703ec4e8 4681 if (priv->parallel)
219b747a 4682 {
602427c4
MF		 4683 OUTS (outf, "ILLEGAL");
4684 return 0;
219b747a 4685 }
086134ec 4686 OUTS (outf, "MNOP");
4b7f6baa
CM		 4687 return 4;
4688 }
4689 else if ((iw0 & 0xff00) == 0x0000)
b7d48530 4690 rv = decode_ProgCtrl_0 (iw0, outf);
4b7f6baa 4691 else if ((iw0 & 0xffc0) == 0x0240)
b7d48530 4692 rv = decode_CaCTRL_0 (iw0, outf);
4b7f6baa 4693 else if ((iw0 & 0xff80) == 0x0100)
b7d48530 4694 rv = decode_PushPopReg_0 (iw0, outf);
4b7f6baa 4695 else if ((iw0 & 0xfe00) == 0x0400)
b7d48530 4696 rv = decode_PushPopMultiple_0 (iw0, outf);
4b7f6baa 4697 else if ((iw0 & 0xfe00) == 0x0600)
b7d48530 4698 rv = decode_ccMV_0 (iw0, outf);
4b7f6baa 4699 else if ((iw0 & 0xf800) == 0x0800)
b7d48530 4700 rv = decode_CCflag_0 (iw0, outf);
4b7f6baa 4701 else if ((iw0 & 0xffe0) == 0x0200)
b7d48530 4702 rv = decode_CC2dreg_0 (iw0, outf);
4b7f6baa 4703 else if ((iw0 & 0xff00) == 0x0300)
b7d48530 4704 rv = decode_CC2stat_0 (iw0, outf);
4b7f6baa 4705 else if ((iw0 & 0xf000) == 0x1000)
b7d48530 4706 rv = decode_BRCC_0 (iw0, pc, outf);
4b7f6baa 4707 else if ((iw0 & 0xf000) == 0x2000)
b7d48530 4708 rv = decode_UJUMP_0 (iw0, pc, outf);
4b7f6baa 4709 else if ((iw0 & 0xf000) == 0x3000)
b7d48530 4710 rv = decode_REGMV_0 (iw0, outf);
4b7f6baa 4711 else if ((iw0 & 0xfc00) == 0x4000)
b7d48530 4712 rv = decode_ALU2op_0 (iw0, outf);
4b7f6baa 4713 else if ((iw0 & 0xfe00) == 0x4400)
b7d48530 4714 rv = decode_PTR2op_0 (iw0, outf);
4b7f6baa 4715 else if ((iw0 & 0xf800) == 0x4800)
b7d48530 4716 rv = decode_LOGI2op_0 (iw0, outf);
4b7f6baa 4717 else if ((iw0 & 0xf000) == 0x5000)
b7d48530 4718 rv = decode_COMP3op_0 (iw0, outf);
4b7f6baa 4719 else if ((iw0 & 0xf800) == 0x6000)
b7d48530 4720 rv = decode_COMPI2opD_0 (iw0, outf);
4b7f6baa 4721 else if ((iw0 & 0xf800) == 0x6800)
b7d48530 4722 rv = decode_COMPI2opP_0 (iw0, outf);
4b7f6baa 4723 else if ((iw0 & 0xf000) == 0x8000)
b7d48530 4724 rv = decode_LDSTpmod_0 (iw0, outf);
4b7f6baa 4725 else if ((iw0 & 0xff60) == 0x9e60)
b7d48530 4726 rv = decode_dagMODim_0 (iw0, outf);
4b7f6baa 4727 else if ((iw0 & 0xfff0) == 0x9f60)
b7d48530 4728 rv = decode_dagMODik_0 (iw0, outf);
4b7f6baa 4729 else if ((iw0 & 0xfc00) == 0x9c00)
b7d48530 4730 rv = decode_dspLDST_0 (iw0, outf);
4b7f6baa 4731 else if ((iw0 & 0xf000) == 0x9000)
b7d48530 4732 rv = decode_LDST_0 (iw0, outf);
4b7f6baa 4733 else if ((iw0 & 0xfc00) == 0xb800)
b7d48530 4734 rv = decode_LDSTiiFP_0 (iw0, outf);
4b7f6baa 4735 else if ((iw0 & 0xe000) == 0xA000)
b7d48530 4736 rv = decode_LDSTii_0 (iw0, outf);
4b7f6baa 4737 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
b7d48530 4738 rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4b7f6baa 4739 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
b7d48530 4740 rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4b7f6baa 4741 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
b7d48530 4742 rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4b7f6baa 4743 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
b7d48530 4744 rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4b7f6baa 4745 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
b7d48530 4746 rv = decode_linkage_0 (iw0, iw1, outf);
4b7f6baa 4747 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
b7d48530 4748 rv = decode_dsp32mac_0 (iw0, iw1, outf);
4b7f6baa 4749 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
b7d48530 4750 rv = decode_dsp32mult_0 (iw0, iw1, outf);
4b7f6baa 4751 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
b7d48530 4752 rv = decode_dsp32alu_0 (iw0, iw1, outf);
4b7f6baa 4753 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
b7d48530 4754 rv = decode_dsp32shift_0 (iw0, iw1, outf);
4b7f6baa 4755 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
b7d48530 4756 rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4b7f6baa 4757 else if ((iw0 & 0xff00) == 0xf800)
b7d48530 4758 rv = decode_pseudoDEBUG_0 (iw0, outf);
4b7f6baa 4759 else if ((iw0 & 0xFF00) == 0xF900)
73a63ccf 4760 rv = decode_pseudoOChar_0 (iw0, outf);
66a6900a 4761 else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
b7d48530 4762 rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4b7f6baa 4763
219b747a
MF		 4764 if (rv == 0)
4765 OUTS (outf, "ILLEGAL");
4766
b7d48530 4767 return rv;
4b7f6baa
CM		 4768}
4769
4b7f6baa
CM		 4770int
4771print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4772{
703ec4e8 4773 struct private priv;
ba329817 4774 int count;
471e4e36 4775
60ac5798
MF		 4776 priv.parallel = FALSE;
4777 priv.comment = FALSE;
703ec4e8
MF		 4778 outf->private_data = &priv;
4779
ba329817
MF		 4780 count = _print_insn_bfin (pc, outf);
4781 if (count == -1)
4782 return -1;
471e4e36 4783
4b7f6baa 4784 /* Proper display of multiple issue instructions. */
471e4e36 4785
a4e600b2
MF		 4786 if (count == 4 && (priv.iw0 & 0xc000) == 0xc000 && (priv.iw0 & BIT_MULTI_INS)
4787 && ((priv.iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
4b7f6baa 4788 {
60ac5798 4789 bfd_boolean legal = TRUE;
219b747a
MF		 4790 int len;
4791
60ac5798 4792 priv.parallel = TRUE;
f5caf9f4 4793 OUTS (outf, " || ");
219b747a 4794 len = _print_insn_bfin (pc + 4, outf);
ba329817
MF		 4795 if (len == -1)
4796 return -1;
f5caf9f4 4797 OUTS (outf, " || ");
219b747a 4798 if (len != 2)
60ac5798 4799 legal = FALSE;
219b747a 4800 len = _print_insn_bfin (pc + 6, outf);
ba329817
MF		 4801 if (len == -1)
4802 return -1;
219b747a 4803 if (len != 2)
60ac5798 4804 legal = FALSE;
219b747a
MF		 4805
4806 if (legal)
4807 count = 8;
4808 else
4809 {
f5caf9f4 4810 OUTS (outf, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
60ac5798 4811 priv.comment = TRUE;
219b747a
MF		 4812 count = 0;
4813 }
4b7f6baa 4814 }
219b747a 4815
703ec4e8 4816 if (!priv.comment)
f5caf9f4 4817 OUTS (outf, ";");
086134ec 4818
219b747a
MF		 4819 if (count == 0)
4820 return 2;
4821
4b7f6baa
CM		 4822 return count;
4823}
GDB Binutils - Deliverables
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