Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Select disassembly routine for specified architecture. |
219d1afa | 2 | Copyright (C) 1994-2018 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 NC |
4 | This file is part of the GNU opcodes library. |
5 | ||
6 | This library is free software; you can redistribute it and/or modify | |
7499d566 | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 | 8 | the Free Software Foundation; either version 3 of the License, or |
7499d566 | 9 | (at your option) any later version. |
252b5132 | 10 | |
7499d566 NC |
11 | This program is distributed in the hope that it will be useful, |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
252b5132 | 15 | |
7499d566 NC |
16 | You should have received a copy of the GNU General Public License |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
252b5132 | 20 | |
0d8dfecf | 21 | #include "sysdep.h" |
88c1242d | 22 | #include "disassemble.h" |
65b48a81 | 23 | #include "safe-ctype.h" |
003ca0fd | 24 | #include <assert.h> |
252b5132 RH |
25 | |
26 | #ifdef ARCH_all | |
a06ea964 | 27 | #define ARCH_aarch64 |
252b5132 RH |
28 | #define ARCH_alpha |
29 | #define ARCH_arc | |
30 | #define ARCH_arm | |
adde6300 | 31 | #define ARCH_avr |
4b7f6baa | 32 | #define ARCH_bfin |
3d3d428f | 33 | #define ARCH_cr16 |
6c95a37f | 34 | #define ARCH_cris |
1fe1f39c | 35 | #define ARCH_crx |
252b5132 RH |
36 | #define ARCH_d10v |
37 | #define ARCH_d30v | |
d172d4ba | 38 | #define ARCH_dlx |
56b13185 | 39 | #define ARCH_epiphany |
e729279b NC |
40 | #define ARCH_fr30 |
41 | #define ARCH_frv | |
3f8107ab | 42 | #define ARCH_ft32 |
252b5132 | 43 | #define ARCH_h8300 |
252b5132 RH |
44 | #define ARCH_hppa |
45 | #define ARCH_i386 | |
800eeca4 | 46 | #define ARCH_ia64 |
e729279b NC |
47 | #define ARCH_ip2k |
48 | #define ARCH_iq2000 | |
84e94c90 | 49 | #define ARCH_lm32 |
e729279b | 50 | #define ARCH_m32c |
252b5132 | 51 | #define ARCH_m32r |
60bcf0fa NC |
52 | #define ARCH_m68hc11 |
53 | #define ARCH_m68hc12 | |
e729279b | 54 | #define ARCH_m68k |
252b5132 | 55 | #define ARCH_mcore |
bd2f2e55 | 56 | #define ARCH_mep |
a3c62988 | 57 | #define ARCH_metag |
7ba29e2a | 58 | #define ARCH_microblaze |
252b5132 | 59 | #define ARCH_mips |
3c3bdf30 | 60 | #define ARCH_mmix |
252b5132 RH |
61 | #define ARCH_mn10200 |
62 | #define ARCH_mn10300 | |
59b1530d | 63 | #define ARCH_moxie |
d031aafb | 64 | #define ARCH_mt |
2469cfa2 | 65 | #define ARCH_msp430 |
35c08157 | 66 | #define ARCH_nds32 |
fe944acf | 67 | #define ARCH_nfp |
36591ba1 | 68 | #define ARCH_nios2 |
252b5132 | 69 | #define ARCH_ns32k |
73589c9d | 70 | #define ARCH_or1k |
e135f41b | 71 | #define ARCH_pdp11 |
1e608f98 | 72 | #define ARCH_pj |
252b5132 | 73 | #define ARCH_powerpc |
11146849 | 74 | #define ARCH_pru |
0bccfb29 | 75 | #define ARCH_riscv |
252b5132 | 76 | #define ARCH_rs6000 |
99c513f6 | 77 | #define ARCH_rl78 |
c7927a3c | 78 | #define ARCH_rx |
a85d7ed0 | 79 | #define ARCH_s390 |
1c0d3aa6 | 80 | #define ARCH_score |
252b5132 RH |
81 | #define ARCH_sh |
82 | #define ARCH_sparc | |
e9f53129 | 83 | #define ARCH_spu |
252b5132 | 84 | #define ARCH_tic30 |
026df7c5 | 85 | #define ARCH_tic4x |
5c84d377 | 86 | #define ARCH_tic54x |
40b36596 | 87 | #define ARCH_tic6x |
252b5132 | 88 | #define ARCH_tic80 |
aa137e4d NC |
89 | #define ARCH_tilegx |
90 | #define ARCH_tilepro | |
252b5132 RH |
91 | #define ARCH_v850 |
92 | #define ARCH_vax | |
1945cfa5 | 93 | #define ARCH_visium |
62ecb94c | 94 | #define ARCH_wasm32 |
93fbbb04 | 95 | #define ARCH_xstormy16 |
d70c5fc7 | 96 | #define ARCH_xc16x |
f6c1a2d5 | 97 | #define ARCH_xgate |
e0001a05 | 98 | #define ARCH_xtensa |
3c9b82ba | 99 | #define ARCH_z80 |
252b5132 RH |
100 | #define ARCH_z8k |
101 | #endif | |
102 | ||
49f58d10 JB |
103 | #ifdef ARCH_m32c |
104 | #include "m32c-desc.h" | |
105 | #endif | |
252b5132 RH |
106 | |
107 | disassembler_ftype | |
b28b8b5e L |
108 | disassembler (enum bfd_architecture a, |
109 | bfd_boolean big ATTRIBUTE_UNUSED, | |
110 | unsigned long mach ATTRIBUTE_UNUSED, | |
e347efc3 | 111 | bfd *abfd ATTRIBUTE_UNUSED) |
252b5132 | 112 | { |
252b5132 RH |
113 | disassembler_ftype disassemble; |
114 | ||
115 | switch (a) | |
116 | { | |
117 | /* If you add a case to this table, also add it to the | |
118 | ARCH_all definition right above this function. */ | |
a06ea964 NC |
119 | #ifdef ARCH_aarch64 |
120 | case bfd_arch_aarch64: | |
121 | disassemble = print_insn_aarch64; | |
122 | break; | |
123 | #endif | |
252b5132 RH |
124 | #ifdef ARCH_alpha |
125 | case bfd_arch_alpha: | |
126 | disassemble = print_insn_alpha; | |
127 | break; | |
128 | #endif | |
129 | #ifdef ARCH_arc | |
130 | case bfd_arch_arc: | |
6ca4eb77 AM |
131 | disassemble = arc_get_disassembler (abfd); |
132 | break; | |
252b5132 RH |
133 | #endif |
134 | #ifdef ARCH_arm | |
135 | case bfd_arch_arm: | |
003ca0fd | 136 | if (big) |
252b5132 RH |
137 | disassemble = print_insn_big_arm; |
138 | else | |
139 | disassemble = print_insn_little_arm; | |
140 | break; | |
141 | #endif | |
adde6300 AM |
142 | #ifdef ARCH_avr |
143 | case bfd_arch_avr: | |
144 | disassemble = print_insn_avr; | |
145 | break; | |
146 | #endif | |
4b7f6baa CM |
147 | #ifdef ARCH_bfin |
148 | case bfd_arch_bfin: | |
149 | disassemble = print_insn_bfin; | |
150 | break; | |
151 | #endif | |
3d3d428f NC |
152 | #ifdef ARCH_cr16 |
153 | case bfd_arch_cr16: | |
154 | disassemble = print_insn_cr16; | |
155 | break; | |
156 | #endif | |
6c95a37f HPN |
157 | #ifdef ARCH_cris |
158 | case bfd_arch_cris: | |
78966507 | 159 | disassemble = cris_get_disassembler (abfd); |
6c95a37f | 160 | break; |
1fe1f39c NC |
161 | #endif |
162 | #ifdef ARCH_crx | |
163 | case bfd_arch_crx: | |
164 | disassemble = print_insn_crx; | |
165 | break; | |
6c95a37f | 166 | #endif |
252b5132 RH |
167 | #ifdef ARCH_d10v |
168 | case bfd_arch_d10v: | |
169 | disassemble = print_insn_d10v; | |
170 | break; | |
171 | #endif | |
172 | #ifdef ARCH_d30v | |
173 | case bfd_arch_d30v: | |
174 | disassemble = print_insn_d30v; | |
175 | break; | |
176 | #endif | |
d172d4ba NC |
177 | #ifdef ARCH_dlx |
178 | case bfd_arch_dlx: | |
179 | /* As far as I know we only handle big-endian DLX objects. */ | |
180 | disassemble = print_insn_dlx; | |
181 | break; | |
182 | #endif | |
252b5132 RH |
183 | #ifdef ARCH_h8300 |
184 | case bfd_arch_h8300: | |
003ca0fd | 185 | if (mach == bfd_mach_h8300h || mach == bfd_mach_h8300hn) |
252b5132 | 186 | disassemble = print_insn_h8300h; |
003ca0fd YQ |
187 | else if (mach == bfd_mach_h8300s |
188 | || mach == bfd_mach_h8300sn | |
189 | || mach == bfd_mach_h8300sx | |
190 | || mach == bfd_mach_h8300sxn) | |
252b5132 | 191 | disassemble = print_insn_h8300s; |
b7ed8fad | 192 | else |
252b5132 RH |
193 | disassemble = print_insn_h8300; |
194 | break; | |
195 | #endif | |
252b5132 RH |
196 | #ifdef ARCH_hppa |
197 | case bfd_arch_hppa: | |
198 | disassemble = print_insn_hppa; | |
199 | break; | |
200 | #endif | |
201 | #ifdef ARCH_i386 | |
202 | case bfd_arch_i386: | |
7b6d09fb | 203 | case bfd_arch_iamcu: |
8a9036a4 | 204 | case bfd_arch_l1om: |
7a9068fe | 205 | case bfd_arch_k1om: |
e396998b | 206 | disassemble = print_insn_i386; |
252b5132 RH |
207 | break; |
208 | #endif | |
800eeca4 JW |
209 | #ifdef ARCH_ia64 |
210 | case bfd_arch_ia64: | |
211 | disassemble = print_insn_ia64; | |
212 | break; | |
213 | #endif | |
a40cbfa3 NC |
214 | #ifdef ARCH_ip2k |
215 | case bfd_arch_ip2k: | |
216 | disassemble = print_insn_ip2k; | |
217 | break; | |
218 | #endif | |
cfb8c092 NC |
219 | #ifdef ARCH_epiphany |
220 | case bfd_arch_epiphany: | |
221 | disassemble = print_insn_epiphany; | |
222 | break; | |
223 | #endif | |
252b5132 RH |
224 | #ifdef ARCH_fr30 |
225 | case bfd_arch_fr30: | |
226 | disassemble = print_insn_fr30; | |
227 | break; | |
228 | #endif | |
84e94c90 NC |
229 | #ifdef ARCH_lm32 |
230 | case bfd_arch_lm32: | |
231 | disassemble = print_insn_lm32; | |
232 | break; | |
233 | #endif | |
252b5132 RH |
234 | #ifdef ARCH_m32r |
235 | case bfd_arch_m32r: | |
236 | disassemble = print_insn_m32r; | |
237 | break; | |
238 | #endif | |
6927f982 NC |
239 | #if defined(ARCH_m68hc11) || defined(ARCH_m68hc12) \ |
240 | || defined(ARCH_9s12x) || defined(ARCH_m9s12xg) | |
60bcf0fa NC |
241 | case bfd_arch_m68hc11: |
242 | disassemble = print_insn_m68hc11; | |
243 | break; | |
244 | case bfd_arch_m68hc12: | |
245 | disassemble = print_insn_m68hc12; | |
246 | break; | |
6927f982 NC |
247 | case bfd_arch_m9s12x: |
248 | disassemble = print_insn_m9s12x; | |
249 | break; | |
250 | case bfd_arch_m9s12xg: | |
251 | disassemble = print_insn_m9s12xg; | |
252 | break; | |
60bcf0fa | 253 | #endif |
7b4ae824 JD |
254 | #if defined(ARCH_s12z) |
255 | case bfd_arch_s12z: | |
256 | disassemble = print_insn_s12z; | |
257 | break; | |
258 | #endif | |
252b5132 RH |
259 | #ifdef ARCH_m68k |
260 | case bfd_arch_m68k: | |
261 | disassemble = print_insn_m68k; | |
262 | break; | |
263 | #endif | |
d031aafb NS |
264 | #ifdef ARCH_mt |
265 | case bfd_arch_mt: | |
266 | disassemble = print_insn_mt; | |
ac188222 DB |
267 | break; |
268 | #endif | |
7ba29e2a NC |
269 | #ifdef ARCH_microblaze |
270 | case bfd_arch_microblaze: | |
271 | disassemble = print_insn_microblaze; | |
272 | break; | |
273 | #endif | |
2469cfa2 NC |
274 | #ifdef ARCH_msp430 |
275 | case bfd_arch_msp430: | |
276 | disassemble = print_insn_msp430; | |
277 | break; | |
278 | #endif | |
35c08157 KLC |
279 | #ifdef ARCH_nds32 |
280 | case bfd_arch_nds32: | |
281 | disassemble = print_insn_nds32; | |
282 | break; | |
283 | #endif | |
fe944acf FT |
284 | #ifdef ARCH_nfp |
285 | case bfd_arch_nfp: | |
286 | disassemble = print_insn_nfp; | |
287 | break; | |
288 | #endif | |
252b5132 RH |
289 | #ifdef ARCH_ns32k |
290 | case bfd_arch_ns32k: | |
291 | disassemble = print_insn_ns32k; | |
292 | break; | |
293 | #endif | |
294 | #ifdef ARCH_mcore | |
295 | case bfd_arch_mcore: | |
296 | disassemble = print_insn_mcore; | |
297 | break; | |
298 | #endif | |
bd2f2e55 DB |
299 | #ifdef ARCH_mep |
300 | case bfd_arch_mep: | |
301 | disassemble = print_insn_mep; | |
302 | break; | |
303 | #endif | |
a3c62988 NC |
304 | #ifdef ARCH_metag |
305 | case bfd_arch_metag: | |
306 | disassemble = print_insn_metag; | |
307 | break; | |
308 | #endif | |
252b5132 RH |
309 | #ifdef ARCH_mips |
310 | case bfd_arch_mips: | |
003ca0fd | 311 | if (big) |
252b5132 RH |
312 | disassemble = print_insn_big_mips; |
313 | else | |
314 | disassemble = print_insn_little_mips; | |
315 | break; | |
316 | #endif | |
3c3bdf30 NC |
317 | #ifdef ARCH_mmix |
318 | case bfd_arch_mmix: | |
319 | disassemble = print_insn_mmix; | |
320 | break; | |
321 | #endif | |
252b5132 RH |
322 | #ifdef ARCH_mn10200 |
323 | case bfd_arch_mn10200: | |
324 | disassemble = print_insn_mn10200; | |
325 | break; | |
326 | #endif | |
327 | #ifdef ARCH_mn10300 | |
328 | case bfd_arch_mn10300: | |
329 | disassemble = print_insn_mn10300; | |
330 | break; | |
331 | #endif | |
36591ba1 SL |
332 | #ifdef ARCH_nios2 |
333 | case bfd_arch_nios2: | |
003ca0fd | 334 | if (big) |
36591ba1 SL |
335 | disassemble = print_insn_big_nios2; |
336 | else | |
337 | disassemble = print_insn_little_nios2; | |
338 | break; | |
339 | #endif | |
73589c9d CS |
340 | #ifdef ARCH_or1k |
341 | case bfd_arch_or1k: | |
342 | disassemble = print_insn_or1k; | |
3b16e843 NC |
343 | break; |
344 | #endif | |
e135f41b NC |
345 | #ifdef ARCH_pdp11 |
346 | case bfd_arch_pdp11: | |
347 | disassemble = print_insn_pdp11; | |
348 | break; | |
349 | #endif | |
1e608f98 ILT |
350 | #ifdef ARCH_pj |
351 | case bfd_arch_pj: | |
352 | disassemble = print_insn_pj; | |
353 | break; | |
354 | #endif | |
252b5132 RH |
355 | #ifdef ARCH_powerpc |
356 | case bfd_arch_powerpc: | |
52fe4420 AM |
357 | #endif |
358 | #ifdef ARCH_rs6000 | |
359 | case bfd_arch_rs6000: | |
360 | #endif | |
361 | #if defined ARCH_powerpc || defined ARCH_rs6000 | |
003ca0fd | 362 | if (big) |
252b5132 RH |
363 | disassemble = print_insn_big_powerpc; |
364 | else | |
365 | disassemble = print_insn_little_powerpc; | |
366 | break; | |
367 | #endif | |
11146849 DD |
368 | #ifdef ARCH_pru |
369 | case bfd_arch_pru: | |
370 | disassemble = print_insn_pru; | |
371 | break; | |
372 | #endif | |
e23eba97 NC |
373 | #ifdef ARCH_riscv |
374 | case bfd_arch_riscv: | |
375 | disassemble = print_insn_riscv; | |
ae4c0df4 | 376 | break; |
e23eba97 | 377 | #endif |
99c513f6 DD |
378 | #ifdef ARCH_rl78 |
379 | case bfd_arch_rl78: | |
0952813b | 380 | disassemble = rl78_get_disassembler (abfd); |
99c513f6 DD |
381 | break; |
382 | #endif | |
c7927a3c NC |
383 | #ifdef ARCH_rx |
384 | case bfd_arch_rx: | |
385 | disassemble = print_insn_rx; | |
386 | break; | |
387 | #endif | |
a85d7ed0 NC |
388 | #ifdef ARCH_s390 |
389 | case bfd_arch_s390: | |
390 | disassemble = print_insn_s390; | |
391 | break; | |
392 | #endif | |
1c0d3aa6 NC |
393 | #ifdef ARCH_score |
394 | case bfd_arch_score: | |
003ca0fd | 395 | if (big) |
6ca4eb77 | 396 | disassemble = print_insn_big_score; |
1c0d3aa6 | 397 | else |
6ca4eb77 | 398 | disassemble = print_insn_little_score; |
1c0d3aa6 NC |
399 | break; |
400 | #endif | |
252b5132 RH |
401 | #ifdef ARCH_sh |
402 | case bfd_arch_sh: | |
1c509ca8 | 403 | disassemble = print_insn_sh; |
252b5132 RH |
404 | break; |
405 | #endif | |
406 | #ifdef ARCH_sparc | |
407 | case bfd_arch_sparc: | |
408 | disassemble = print_insn_sparc; | |
409 | break; | |
410 | #endif | |
e9f53129 AM |
411 | #ifdef ARCH_spu |
412 | case bfd_arch_spu: | |
413 | disassemble = print_insn_spu; | |
414 | break; | |
415 | #endif | |
252b5132 RH |
416 | #ifdef ARCH_tic30 |
417 | case bfd_arch_tic30: | |
418 | disassemble = print_insn_tic30; | |
419 | break; | |
420 | #endif | |
026df7c5 NC |
421 | #ifdef ARCH_tic4x |
422 | case bfd_arch_tic4x: | |
423 | disassemble = print_insn_tic4x; | |
424 | break; | |
425 | #endif | |
5c84d377 TW |
426 | #ifdef ARCH_tic54x |
427 | case bfd_arch_tic54x: | |
428 | disassemble = print_insn_tic54x; | |
429 | break; | |
430 | #endif | |
40b36596 JM |
431 | #ifdef ARCH_tic6x |
432 | case bfd_arch_tic6x: | |
433 | disassemble = print_insn_tic6x; | |
434 | break; | |
435 | #endif | |
252b5132 RH |
436 | #ifdef ARCH_tic80 |
437 | case bfd_arch_tic80: | |
438 | disassemble = print_insn_tic80; | |
439 | break; | |
440 | #endif | |
3f8107ab AM |
441 | #ifdef ARCH_ft32 |
442 | case bfd_arch_ft32: | |
443 | disassemble = print_insn_ft32; | |
444 | break; | |
445 | #endif | |
252b5132 RH |
446 | #ifdef ARCH_v850 |
447 | case bfd_arch_v850: | |
de863c74 | 448 | case bfd_arch_v850_rh850: |
252b5132 RH |
449 | disassemble = print_insn_v850; |
450 | break; | |
451 | #endif | |
62ecb94c PC |
452 | #ifdef ARCH_wasm32 |
453 | case bfd_arch_wasm32: | |
454 | disassemble = print_insn_wasm32; | |
455 | break; | |
456 | #endif | |
f6c1a2d5 NC |
457 | #ifdef ARCH_xgate |
458 | case bfd_arch_xgate: | |
459 | disassemble = print_insn_xgate; | |
460 | break; | |
461 | #endif | |
93fbbb04 GK |
462 | #ifdef ARCH_xstormy16 |
463 | case bfd_arch_xstormy16: | |
464 | disassemble = print_insn_xstormy16; | |
465 | break; | |
466 | #endif | |
d70c5fc7 NC |
467 | #ifdef ARCH_xc16x |
468 | case bfd_arch_xc16x: | |
469 | disassemble = print_insn_xc16x; | |
470 | break; | |
471 | #endif | |
e0001a05 NC |
472 | #ifdef ARCH_xtensa |
473 | case bfd_arch_xtensa: | |
474 | disassemble = print_insn_xtensa; | |
475 | break; | |
476 | #endif | |
3c9b82ba NC |
477 | #ifdef ARCH_z80 |
478 | case bfd_arch_z80: | |
479 | disassemble = print_insn_z80; | |
480 | break; | |
481 | #endif | |
252b5132 RH |
482 | #ifdef ARCH_z8k |
483 | case bfd_arch_z8k: | |
003ca0fd | 484 | if (mach == bfd_mach_z8001) |
252b5132 | 485 | disassemble = print_insn_z8001; |
b7ed8fad | 486 | else |
252b5132 RH |
487 | disassemble = print_insn_z8002; |
488 | break; | |
489 | #endif | |
490 | #ifdef ARCH_vax | |
491 | case bfd_arch_vax: | |
492 | disassemble = print_insn_vax; | |
493 | break; | |
fd3c93d5 | 494 | #endif |
1945cfa5 EB |
495 | #ifdef ARCH_visium |
496 | case bfd_arch_visium: | |
497 | disassemble = print_insn_visium; | |
498 | break; | |
499 | #endif | |
fd3c93d5 DB |
500 | #ifdef ARCH_frv |
501 | case bfd_arch_frv: | |
502 | disassemble = print_insn_frv; | |
503 | break; | |
47b1a55a | 504 | #endif |
59b1530d AG |
505 | #ifdef ARCH_moxie |
506 | case bfd_arch_moxie: | |
507 | disassemble = print_insn_moxie; | |
508 | break; | |
509 | #endif | |
47b1a55a SC |
510 | #ifdef ARCH_iq2000 |
511 | case bfd_arch_iq2000: | |
512 | disassemble = print_insn_iq2000; | |
513 | break; | |
49f58d10 JB |
514 | #endif |
515 | #ifdef ARCH_m32c | |
516 | case bfd_arch_m32c: | |
517 | disassemble = print_insn_m32c; | |
518 | break; | |
aa137e4d NC |
519 | #endif |
520 | #ifdef ARCH_tilegx | |
521 | case bfd_arch_tilegx: | |
522 | disassemble = print_insn_tilegx; | |
523 | break; | |
524 | #endif | |
525 | #ifdef ARCH_tilepro | |
526 | case bfd_arch_tilepro: | |
527 | disassemble = print_insn_tilepro; | |
528 | break; | |
252b5132 RH |
529 | #endif |
530 | default: | |
531 | return 0; | |
532 | } | |
533 | return disassemble; | |
534 | } | |
94470b23 NC |
535 | |
536 | void | |
e6c7cdec | 537 | disassembler_usage (FILE *stream ATTRIBUTE_UNUSED) |
94470b23 | 538 | { |
a06ea964 NC |
539 | #ifdef ARCH_aarch64 |
540 | print_aarch64_disassembler_options (stream); | |
541 | #endif | |
37fd5ef3 CZ |
542 | #ifdef ARCH_arc |
543 | print_arc_disassembler_options (stream); | |
544 | #endif | |
58efb6c0 NC |
545 | #ifdef ARCH_arm |
546 | print_arm_disassembler_options (stream); | |
547 | #endif | |
640c0ccd CD |
548 | #ifdef ARCH_mips |
549 | print_mips_disassembler_options (stream); | |
550 | #endif | |
fe944acf FT |
551 | #ifdef ARCH_nfp |
552 | print_nfp_disassembler_options (stream); | |
553 | #endif | |
07dd56a9 NC |
554 | #ifdef ARCH_powerpc |
555 | print_ppc_disassembler_options (stream); | |
556 | #endif | |
e23eba97 NC |
557 | #ifdef ARCH_riscv |
558 | print_riscv_disassembler_options (stream); | |
559 | #endif | |
f59a29b9 L |
560 | #ifdef ARCH_i386 |
561 | print_i386_disassembler_options (stream); | |
562 | #endif | |
112b7c50 AK |
563 | #ifdef ARCH_s390 |
564 | print_s390_disassembler_options (stream); | |
565 | #endif | |
62ecb94c PC |
566 | #ifdef ARCH_wasm32 |
567 | print_wasm32_disassembler_options (stream); | |
568 | #endif | |
b7ed8fad | 569 | |
94470b23 NC |
570 | return; |
571 | } | |
22a398e1 NC |
572 | |
573 | void | |
574 | disassemble_init_for_target (struct disassemble_info * info) | |
575 | { | |
576 | if (info == NULL) | |
577 | return; | |
578 | ||
579 | switch (info->arch) | |
580 | { | |
a06ea964 NC |
581 | #ifdef ARCH_aarch64 |
582 | case bfd_arch_aarch64: | |
583 | info->symbol_is_valid = aarch64_symbol_is_valid; | |
584 | info->disassembler_needs_relocs = TRUE; | |
585 | break; | |
586 | #endif | |
22a398e1 NC |
587 | #ifdef ARCH_arm |
588 | case bfd_arch_arm: | |
589 | info->symbol_is_valid = arm_symbol_is_valid; | |
d99b6465 | 590 | info->disassembler_needs_relocs = TRUE; |
22a398e1 | 591 | break; |
0bcb06d2 AS |
592 | #endif |
593 | #ifdef ARCH_ia64 | |
594 | case bfd_arch_ia64: | |
595 | info->skip_zeroes = 16; | |
596 | break; | |
597 | #endif | |
598 | #ifdef ARCH_tic4x | |
599 | case bfd_arch_tic4x: | |
600 | info->skip_zeroes = 32; | |
fb53f5a8 | 601 | break; |
49f58d10 | 602 | #endif |
bd2f2e55 DB |
603 | #ifdef ARCH_mep |
604 | case bfd_arch_mep: | |
605 | info->skip_zeroes = 256; | |
606 | info->skip_zeroes_at_end = 0; | |
607 | break; | |
608 | #endif | |
a3c62988 NC |
609 | #ifdef ARCH_metag |
610 | case bfd_arch_metag: | |
611 | info->disassembler_needs_relocs = TRUE; | |
612 | break; | |
613 | #endif | |
49f58d10 JB |
614 | #ifdef ARCH_m32c |
615 | case bfd_arch_m32c: | |
6ca4eb77 AM |
616 | /* This processor in fact is little endian. The value set here |
617 | reflects the way opcodes are written in the cgen description. */ | |
49f58d10 | 618 | info->endian = BFD_ENDIAN_BIG; |
fb53f5a8 DB |
619 | if (! info->insn_sets) |
620 | { | |
621 | info->insn_sets = cgen_bitset_create (ISA_MAX); | |
622 | if (info->mach == bfd_mach_m16c) | |
623 | cgen_bitset_set (info->insn_sets, ISA_M16C); | |
624 | else | |
625 | cgen_bitset_set (info->insn_sets, ISA_M32C); | |
626 | } | |
49f58d10 | 627 | break; |
b240011a | 628 | #endif |
024d185c DD |
629 | #ifdef ARCH_pru |
630 | case bfd_arch_pru: | |
631 | info->disassembler_needs_relocs = TRUE; | |
632 | break; | |
633 | #endif | |
fbc22555 DD |
634 | #ifdef ARCH_powerpc |
635 | case bfd_arch_powerpc: | |
636 | #endif | |
b240011a AM |
637 | #ifdef ARCH_rs6000 |
638 | case bfd_arch_rs6000: | |
639 | #endif | |
640 | #if defined (ARCH_powerpc) || defined (ARCH_rs6000) | |
641 | disassemble_init_powerpc (info); | |
642 | break; | |
65b48a81 | 643 | #endif |
62ecb94c PC |
644 | #ifdef ARCH_wasm32 |
645 | case bfd_arch_wasm32: | |
646 | disassemble_init_wasm32 (info); | |
647 | break; | |
648 | #endif | |
65b48a81 PB |
649 | #ifdef ARCH_s390 |
650 | case bfd_arch_s390: | |
651 | disassemble_init_s390 (info); | |
652 | break; | |
22a398e1 NC |
653 | #endif |
654 | default: | |
655 | break; | |
656 | } | |
657 | } | |
65b48a81 PB |
658 | |
659 | /* Remove whitespace and consecutive commas from OPTIONS. */ | |
660 | ||
661 | char * | |
662 | remove_whitespace_and_extra_commas (char *options) | |
663 | { | |
664 | char *str; | |
665 | size_t i, len; | |
666 | ||
667 | if (options == NULL) | |
668 | return NULL; | |
669 | ||
670 | /* Strip off all trailing whitespace and commas. */ | |
671 | for (len = strlen (options); len > 0; len--) | |
672 | { | |
673 | if (!ISSPACE (options[len - 1]) && options[len - 1] != ',') | |
674 | break; | |
675 | options[len - 1] = '\0'; | |
676 | } | |
677 | ||
678 | /* Convert all remaining whitespace to commas. */ | |
679 | for (i = 0; options[i] != '\0'; i++) | |
680 | if (ISSPACE (options[i])) | |
681 | options[i] = ','; | |
682 | ||
683 | /* Remove consecutive commas. */ | |
684 | for (str = options; *str != '\0'; str++) | |
685 | if (*str == ',' && (*(str + 1) == ',' || str == options)) | |
686 | { | |
687 | char *next = str + 1; | |
688 | while (*next == ',') | |
689 | next++; | |
690 | len = strlen (next); | |
691 | if (str != options) | |
692 | str++; | |
693 | memmove (str, next, len); | |
694 | next[len - (size_t)(next - str)] = '\0'; | |
695 | } | |
696 | return (strlen (options) != 0) ? options : NULL; | |
697 | } | |
698 | ||
699 | /* Like STRCMP, but treat ',' the same as '\0' so that we match | |
700 | strings like "foobar" against "foobar,xxyyzz,...". */ | |
701 | ||
702 | int | |
703 | disassembler_options_cmp (const char *s1, const char *s2) | |
704 | { | |
705 | unsigned char c1, c2; | |
706 | ||
707 | do | |
708 | { | |
709 | c1 = (unsigned char) *s1++; | |
710 | if (c1 == ',') | |
711 | c1 = '\0'; | |
712 | c2 = (unsigned char) *s2++; | |
713 | if (c2 == ',') | |
714 | c2 = '\0'; | |
715 | if (c1 == '\0') | |
716 | return c1 - c2; | |
717 | } | |
718 | while (c1 == c2); | |
719 | ||
720 | return c1 - c2; | |
721 | } |