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* hppa.h (pa_opcodes): Change condition args to use '?' prefix.
[deliverable/binutils-gdb.git] / opcodes / hppa-dis.c
CommitLineData
252b5132
RH		 1/* Disassembler for the PA-RISC. Somewhat derived from sparc-pinsn.c.
2 Copyright 1989, 1990, 1992, 1993 Free Software Foundation, Inc.
3
4 Contributed by the Center for Software Science at the
5 University of Utah (pa-gdb-bugs@cs.utah.edu).
6
7This program is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 2 of the License, or
10(at your option) any later version.
11
12This program is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with this program; if not, write to the Free Software
19Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21#include <ansidecl.h>
22#include "sysdep.h"
23#include "dis-asm.h"
24#include "libhppa.h"
25#include "opcode/hppa.h"
26
27/* Integer register names, indexed by the numbers which appear in the
28 opcodes. */
29static const char *const reg_names[] =
30 {"flags", "r1", "rp", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
31 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
32 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "dp", "ret0", "ret1",
33 "sp", "r31"};
34
35/* Floating point register names, indexed by the numbers which appear in the
36 opcodes. */
37static const char *const fp_reg_names[] =
38 {"fpsr", "fpe2", "fpe4", "fpe6",
39 "fr4", "fr5", "fr6", "fr7", "fr8",
40 "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
41 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
42 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31"};
43
44typedef unsigned int CORE_ADDR;
45
46/* Get at various relevent fields of an instruction word. */
47
48#define MASK_5 0x1f
49#define MASK_11 0x7ff
50#define MASK_14 0x3fff
51#define MASK_21 0x1fffff
52
53/* This macro gets bit fields using HP's numbering (MSB = 0) */
54
55#define GET_FIELD(X, FROM, TO) \
56 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
57
58/* Some of these have been converted to 2-d arrays because they
59 consume less storage this way. If the maintenance becomes a
60 problem, convert them back to const 1-d pointer arrays. */
61static const char control_reg[][6] = {
62 "rctr", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
63 "pidr1", "pidr2", "ccr", "sar", "pidr3", "pidr4",
64 "iva", "eiem", "itmr", "pcsq", "pcoq", "iir", "isr",
65 "ior", "ipsw", "eirr", "tr0", "tr1", "tr2", "tr3",
66 "tr4", "tr5", "tr6", "tr7"
67};
68
69static const char compare_cond_names[][5] = {
70 "", ",=", ",<", ",<=", ",<<", ",<<=", ",sv",
71 ",od", ",tr", ",<>", ",>=", ",>", ",>>=",
72 ",>>", ",nsv", ",ev"
73};
74static const char add_cond_names[][5] = {
75 "", ",=", ",<", ",<=", ",nuv", ",znv", ",sv",
76 ",od", ",tr", ",<>", ",>=", ",>", ",uv",
77 ",vnz", ",nsv", ",ev"
78};
79static const char *const logical_cond_names[] = {
80 "", ",=", ",<", ",<=", 0, 0, 0, ",od",
81 ",tr", ",<>", ",>=", ",>", 0, 0, 0, ",ev"};
82static const char *const unit_cond_names[] = {
83 "", 0, ",sbz", ",shz", ",sdc", 0, ",sbc", ",shc",
84 ",tr", 0, ",nbz", ",nhz", ",ndc", 0, ",nbc", ",nhc"
85};
86static const char shift_cond_names[][4] = {
87 "", ",=", ",<", ",od", ",tr", ",<>", ",>=", ",ev"
88};
89static const char index_compl_names[][4] = {"", ",m", ",s", ",sm"};
90static const char short_ldst_compl_names[][4] = {"", ",ma", "", ",mb"};
91static const char *const short_bytes_compl_names[] = {
92 "", ",b,m", ",e", ",e,m"
93};
94static const char *const float_format_names[] = {",sgl", ",dbl", "", ",quad"};
95static const char float_comp_names[][8] =
96{
97 ",false?", ",false", ",?", ",!<=>", ",=", ",=t", ",?=", ",!<>",
98 ",!?>=", ",<", ",?<", ",!>=", ",!?>", ",<=", ",?<=", ",!>",
99 ",!?<=", ",>", ",?>", ",!<=", ",!?<", ",>=", ",?>=", ",!<",
100 ",!?=", ",<>", ",!=", ",!=t", ",!?", ",<=>", ",true?", ",true"
101};
102
103/* For a bunch of different instructions form an index into a
104 completer name table. */
105#define GET_COMPL(insn) (GET_FIELD (insn, 26, 26) | \
106 GET_FIELD (insn, 18, 18) << 1)
107
108#define GET_COND(insn) (GET_FIELD ((insn), 16, 18) + \
109 (GET_FIELD ((insn), 19, 19) ? 8 : 0))
110
111/* Utility function to print registers. Put these first, so gcc's function
112 inlining can do its stuff. */
113
114#define fputs_filtered(STR,F) (*info->fprintf_func) (info->stream, "%s", STR)
115
116static void
117fput_reg (reg, info)
118 unsigned reg;
119 disassemble_info *info;
120{
121 (*info->fprintf_func) (info->stream, reg ? reg_names[reg] : "r0");
122}
123
124static void
125fput_fp_reg (reg, info)
126 unsigned reg;
127 disassemble_info *info;
128{
129 (*info->fprintf_func) (info->stream, reg ? fp_reg_names[reg] : "fr0");
130}
131
132static void
133fput_fp_reg_r (reg, info)
134 unsigned reg;
135 disassemble_info *info;
136{
137 /* Special case floating point exception registers. */
138 if (reg < 4)
139 (*info->fprintf_func) (info->stream, "fpe%d", reg * 2 + 1);
140 else
141 (*info->fprintf_func) (info->stream, "%sR", reg ? fp_reg_names[reg]
142 : "fr0");
143}
144
145static void
146fput_creg (reg, info)
147 unsigned reg;
148 disassemble_info *info;
149{
150 (*info->fprintf_func) (info->stream, control_reg[reg]);
151}
152
153/* print constants with sign */
154
155static void
156fput_const (num, info)
157 unsigned num;
158 disassemble_info *info;
159{
160 if ((int)num < 0)
161 (*info->fprintf_func) (info->stream, "-%x", -(int)num);
162 else
163 (*info->fprintf_func) (info->stream, "%x", num);
164}
165
166/* Routines to extract various sized constants out of hppa
167 instructions. */
168
169/* extract a 3-bit space register number from a be, ble, mtsp or mfsp */
170static int
171extract_3 (word)
172 unsigned word;
173{
174 return GET_FIELD (word, 18, 18) << 2 | GET_FIELD (word, 16, 17);
175}
176
177static int
178extract_5_load (word)
179 unsigned word;
180{
181 return low_sign_extend (word >> 16 & MASK_5, 5);
182}
183
184/* extract the immediate field from a st{bhw}s instruction */
185static int
186extract_5_store (word)
187 unsigned word;
188{
189 return low_sign_extend (word & MASK_5, 5);
190}
191
192/* extract the immediate field from a break instruction */
193static unsigned
194extract_5r_store (word)
195 unsigned word;
196{
197 return (word & MASK_5);
198}
199
200/* extract the immediate field from a {sr}sm instruction */
201static unsigned
202extract_5R_store (word)
203 unsigned word;
204{
205 return (word >> 16 & MASK_5);
206}
207
208/* extract the immediate field from a bb instruction */
209static unsigned
210extract_5Q_store (word)
211 unsigned word;
212{
213 return (word >> 21 & MASK_5);
214}
215
216/* extract an 11 bit immediate field */
217static int
218extract_11 (word)
219 unsigned word;
220{
221 return low_sign_extend (word & MASK_11, 11);
222}
223
224/* extract a 14 bit immediate field */
225static int
226extract_14 (word)
227 unsigned word;
228{
229 return low_sign_extend (word & MASK_14, 14);
230}
231
232/* extract a 21 bit constant */
233
234static int
235extract_21 (word)
236 unsigned word;
237{
238 int val;
239
240 word &= MASK_21;
241 word <<= 11;
242 val = GET_FIELD (word, 20, 20);
243 val <<= 11;
244 val |= GET_FIELD (word, 9, 19);
245 val <<= 2;
246 val |= GET_FIELD (word, 5, 6);
247 val <<= 5;
248 val |= GET_FIELD (word, 0, 4);
249 val <<= 2;
250 val |= GET_FIELD (word, 7, 8);
251 return sign_extend (val, 21) << 11;
252}
253
254/* extract a 12 bit constant from branch instructions */
255
256static int
257extract_12 (word)
258 unsigned word;
259{
260 return sign_extend (GET_FIELD (word, 19, 28) |
261 GET_FIELD (word, 29, 29) << 10 |
262 (word & 0x1) << 11, 12) << 2;
263}
264
265/* extract a 17 bit constant from branch instructions, returning the
266 19 bit signed value. */
267
268static int
269extract_17 (word)
270 unsigned word;
271{
272 return sign_extend (GET_FIELD (word, 19, 28) |
273 GET_FIELD (word, 29, 29) << 10 |
274 GET_FIELD (word, 11, 15) << 11 |
275 (word & 0x1) << 16, 17) << 2;
276}
277
278/* Print one instruction. */
279int
280print_insn_hppa (memaddr, info)
281 bfd_vma memaddr;
282 disassemble_info *info;
283{
284 bfd_byte buffer[4];
285 unsigned int insn, i;
286
287 {
288 int status =
289 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
290 if (status != 0)
291 {
292 (*info->memory_error_func) (status, memaddr, info);
293 return -1;
294 }
295 }
296
297 insn = bfd_getb32 (buffer);
298
299 for (i = 0; i < NUMOPCODES; ++i)
300 {
301 const struct pa_opcode *opcode = &pa_opcodes[i];
302 if ((insn & opcode->mask) == opcode->match)
303 {
304 register const char *s;
305
306 (*info->fprintf_func) (info->stream, "%s", opcode->name);
307
308 if (!strchr ("cfCY<?!@-+&U>~nHNZFIMadu|", opcode->args[0]))
309 (*info->fprintf_func) (info->stream, " ");
310 for (s = opcode->args; *s != '\0'; ++s)
311 {
312 switch (*s)
313 {
314 case 'x':
315 fput_reg (GET_FIELD (insn, 11, 15), info);
316 break;
317 case 'X':
318 if (GET_FIELD (insn, 25, 25))
319 fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
320 else
321 fput_fp_reg (GET_FIELD (insn, 11, 15), info);
322 break;
323 case 'b':
324 fput_reg (GET_FIELD (insn, 6, 10), info);
325 break;
326 case '^':
327 fput_creg (GET_FIELD (insn, 6, 10), info);
328 break;
329 case 'E':
3ea80b33 330 fput_fp_reg (GET_FIELD (insn, 6, 10), info);
25ef477f 331 break;
252b5132
RH		 332 case 't':
333 fput_reg (GET_FIELD (insn, 27, 31), info);
334 break;
335 case 'v':
336 if (GET_FIELD (insn, 25, 25))
337 fput_fp_reg_r (GET_FIELD (insn, 27, 31), info);
338 else
339 fput_fp_reg (GET_FIELD (insn, 27, 31), info);
340 break;
341 case 'y':
342 fput_fp_reg (GET_FIELD (insn, 27, 31), info);
343 break;
344 case '4':
345 {
346 int reg = GET_FIELD (insn, 6, 10);
347
348 reg |= (GET_FIELD (insn, 26, 26) << 4);
349 fput_fp_reg (reg, info);
350 break;
351 }
352 case '6':
353 {
354 int reg = GET_FIELD (insn, 11, 15);
355
356 reg |= (GET_FIELD (insn, 26, 26) << 4);
357 fput_fp_reg (reg, info);
358 break;
359 }
360 case '7':
361 {
362 int reg = GET_FIELD (insn, 27, 31);
363
364 reg |= (GET_FIELD (insn, 26, 26) << 4);
365 fput_fp_reg (reg, info);
366 break;
367 }
368 case '8':
369 {
370 int reg = GET_FIELD (insn, 16, 20);
371
372 reg |= (GET_FIELD (insn, 26, 26) << 4);
373 fput_fp_reg (reg, info);
374 break;
375 }
376 case '9':
377 {
378 int reg = GET_FIELD (insn, 21, 25);
379
380 reg |= (GET_FIELD (insn, 26, 26) << 4);
381 fput_fp_reg (reg, info);
382 break;
383 }
384 case '5':
385 fput_const (extract_5_load (insn), info);
386 break;
387 case 's':
388 (*info->fprintf_func) (info->stream,
389 "sr%d", GET_FIELD (insn, 16, 17));
390 break;
391 case 'S':
392 (*info->fprintf_func) (info->stream, "sr%d", extract_3 (insn));
393 break;
394 case 'c':
395 (*info->fprintf_func) (info->stream, "%s ",
396 index_compl_names[GET_COMPL (insn)]);
397 break;
398 case 'C':
399 (*info->fprintf_func) (info->stream, "%s ",
400 short_ldst_compl_names[GET_COMPL (insn)]);
401 break;
402 case 'Y':
403 (*info->fprintf_func) (info->stream, "%s ",
404 short_bytes_compl_names[GET_COMPL (insn)]);
405 break;
406 /* these four conditions are for the set of instructions
407 which distinguish true/false conditions by opcode rather
408 than by the 'f' bit (sigh): comb, comib, addb, addib */
409 case '<':
410 fputs_filtered (compare_cond_names[GET_FIELD (insn, 16, 18)],
411 info);
412 break;
413 case '?':
414 fputs_filtered (compare_cond_names[GET_FIELD (insn, 16, 18)
415 + GET_FIELD (insn, 4, 4) * 8], info);
416 break;
417 case '@':
418 fputs_filtered (add_cond_names[GET_FIELD (insn, 16, 18)
419 + GET_FIELD (insn, 4, 4) * 8], info);
420 break;
421 case 'a':
422 (*info->fprintf_func) (info->stream, "%s ",
423 compare_cond_names[GET_COND (insn)]);
424 break;
425 case 'd':
426 (*info->fprintf_func) (info->stream, "%s ",
427 add_cond_names[GET_COND (insn)]);
428 break;
429 case '!':
430 (*info->fprintf_func) (info->stream, "%s",
431 add_cond_names[GET_FIELD (insn, 16, 18)]);
432 break;
433
434 case '&':
435 (*info->fprintf_func) (info->stream, "%s ",
436 logical_cond_names[GET_COND (insn)]);
437 break;
438 case 'U':
439 (*info->fprintf_func) (info->stream, "%s ",
440 unit_cond_names[GET_COND (insn)]);
441 break;
442 case '|':
443 case '>':
444 case '~':
445 (*info->fprintf_func)
446 (info->stream, "%s",
447 shift_cond_names[GET_FIELD (insn, 16, 18)]);
448
449 /* If the next character in args is 'n', it will handle
450 putting out the space. */
451 if (s[1] != 'n')
452 (*info->fprintf_func) (info->stream, " ");
453 break;
454 case 'V':
455 fput_const (extract_5_store (insn), info);
456 break;
457 case 'r':
458 fput_const (extract_5r_store (insn), info);
459 break;
460 case 'R':
461 fput_const (extract_5R_store (insn), info);
462 break;
463 case 'Q':
464 fput_const (extract_5Q_store (insn), info);
465 break;
466 case 'i':
467 fput_const (extract_11 (insn), info);
468 break;
469 case 'j':
470 fput_const (extract_14 (insn), info);
471 break;
472 case 'k':
473 fput_const (extract_21 (insn), info);
474 break;
475 case 'n':
476 if (insn & 0x2)
477 (*info->fprintf_func) (info->stream, ",n ");
478 else
479 (*info->fprintf_func) (info->stream, " ");
480 break;
481 case 'N':
482 if ((insn & 0x20) && s[1])
483 (*info->fprintf_func) (info->stream, ",n ");
484 else if (insn & 0x20)
485 (*info->fprintf_func) (info->stream, ",n");
486 else if (s[1])
487 (*info->fprintf_func) (info->stream, " ");
488 break;
489 case 'w':
490 (*info->print_address_func) (memaddr + 8 + extract_12 (insn),
491 info);
492 break;
493 case 'W':
494 /* 17 bit PC-relative branch. */
495 (*info->print_address_func) ((memaddr + 8
496 + extract_17 (insn)),
497 info);
498 break;
499 case 'z':
500 /* 17 bit displacement. This is an offset from a register
501 so it gets disasssembled as just a number, not any sort
502 of address. */
503 fput_const (extract_17 (insn), info);
504 break;
505 case 'p':
506 (*info->fprintf_func) (info->stream, "%d",
507 31 - GET_FIELD (insn, 22, 26));
508 break;
509 case 'P':
510 (*info->fprintf_func) (info->stream, "%d",
511 GET_FIELD (insn, 22, 26));
512 break;
513 case 'T':
514 (*info->fprintf_func) (info->stream, "%d",
515 32 - GET_FIELD (insn, 27, 31));
516 break;
517 case 'A':
518 fput_const (GET_FIELD (insn, 6, 18), info);
519 break;
520 case 'Z':
521 if (GET_FIELD (insn, 26, 26))
522 (*info->fprintf_func) (info->stream, ",m ");
523 else
524 (*info->fprintf_func) (info->stream, " ");
525 break;
526 case 'D':
527 fput_const (GET_FIELD (insn, 6, 31), info);
528 break;
529 case 'f':
530 (*info->fprintf_func) (info->stream, ",%d", GET_FIELD (insn, 23, 25));
531 break;
532 case 'O':
533 fput_const ((GET_FIELD (insn, 6,20) << 5 |
534 GET_FIELD (insn, 27, 31)), info);
535 break;
536 case 'o':
537 fput_const (GET_FIELD (insn, 6, 20), info);
538 break;
539 case '3':
540 {
541 int reg = GET_FIELD (insn, 21, 22);
542 reg |= GET_FIELD (insn, 16, 18) << 2;
543 if (GET_FIELD (insn, 23, 23) != 0)
544 fput_fp_reg_r (reg, info);
545 else
546 fput_fp_reg (reg, info);
547 break;
548 }
549
550 case '2':
551 fput_const ((GET_FIELD (insn, 6, 22) << 5 |
552 GET_FIELD (insn, 27, 31)), info);
553 break;
554 case '1':
555 fput_const ((GET_FIELD (insn, 11, 20) << 5 |
556 GET_FIELD (insn, 27, 31)), info);
557 break;
558 case '0':
559 fput_const ((GET_FIELD (insn, 16, 20) << 5 |
560 GET_FIELD (insn, 27, 31)), info);
561 break;
562 case 'u':
563 (*info->fprintf_func) (info->stream, ",%d", GET_FIELD (insn, 23, 25));
564 break;
565 case 'F':
566 /* if no destination completer and not before a completer
567 for fcmp, need a space here */
568 if (GET_FIELD (insn, 21, 22) == 1 || s[1] == 'M')
569 fputs_filtered (float_format_names[GET_FIELD (insn, 19, 20)],
570 info);
571 else
572 (*info->fprintf_func) (info->stream, "%s ",
573 float_format_names[GET_FIELD
574 (insn, 19, 20)]);
575 break;
576 case 'G':
577 (*info->fprintf_func) (info->stream, "%s ",
578 float_format_names[GET_FIELD (insn,
579 17, 18)]);
580 break;
581 case 'H':
582 if (GET_FIELD (insn, 26, 26) == 1)
583 (*info->fprintf_func) (info->stream, "%s ",
584 float_format_names[0]);
585 else
586 (*info->fprintf_func) (info->stream, "%s ",
587 float_format_names[1]);
588 break;
589 case 'I':
590 /* if no destination completer and not before a completer
591 for fcmp, need a space here */
592 if (GET_FIELD (insn, 21, 22) == 1 || s[1] == 'M')
593 fputs_filtered (float_format_names[GET_FIELD (insn, 20, 20)],
594 info);
595 else
596 (*info->fprintf_func) (info->stream, "%s ",
597 float_format_names[GET_FIELD
598 (insn, 20, 20)]);
599 break;
600 case 'J':
601 if (GET_FIELD (insn, 24, 24))
602 fput_fp_reg_r (GET_FIELD (insn, 6, 10), info);
603 else
604 fput_fp_reg (GET_FIELD (insn, 6, 10), info);
605
606 break;
607 case 'K':
608 if (GET_FIELD (insn, 19, 19))
609 fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
610 else
611 fput_fp_reg (GET_FIELD (insn, 11, 15), info);
612 break;
613 case 'M':
614 (*info->fprintf_func) (info->stream, "%s ",
615 float_comp_names[GET_FIELD
616 (insn, 27, 31)]);
617 break;
618 default:
619 (*info->fprintf_func) (info->stream, "%c", *s);
620 break;
621 }
622 }
623 return sizeof(insn);
624 }
625 }
626 (*info->fprintf_func) (info->stream, "#%8x", insn);
627 return sizeof(insn);
628}
GDB Binutils - Deliverables
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