Commit | Line | Data |
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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
b3adc24a | 2 | Copyright (C) 1988-2020 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
88c1242d | 36 | #include "disassemble.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
252b5132 RH |
40 | |
41 | #include <setjmp.h> | |
42 | ||
26ca5450 AJ |
43 | static int print_insn (bfd_vma, disassemble_info *); |
44 | static void dofloat (int); | |
45 | static void OP_ST (int, int); | |
46 | static void OP_STi (int, int); | |
47 | static int putop (const char *, int); | |
48 | static void oappend (const char *); | |
49 | static void append_seg (void); | |
50 | static void OP_indirE (int, int); | |
51 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 52 | static void OP_E_register (int, int); |
c1e679ec | 53 | static void OP_E_memory (int, int); |
5d669648 | 54 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
55 | static void OP_E (int, int); |
56 | static void OP_G (int, int); | |
57 | static bfd_vma get64 (void); | |
58 | static bfd_signed_vma get32 (void); | |
59 | static bfd_signed_vma get32s (void); | |
60 | static int get16 (void); | |
61 | static void set_op (bfd_vma, int); | |
b844680a | 62 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
63 | static void OP_REG (int, int); |
64 | static void OP_IMREG (int, int); | |
65 | static void OP_I (int, int); | |
66 | static void OP_I64 (int, int); | |
67 | static void OP_sI (int, int); | |
68 | static void OP_J (int, int); | |
69 | static void OP_SEG (int, int); | |
70 | static void OP_DIR (int, int); | |
71 | static void OP_OFF (int, int); | |
72 | static void OP_OFF64 (int, int); | |
73 | static void ptr_reg (int, int); | |
74 | static void OP_ESreg (int, int); | |
75 | static void OP_DSreg (int, int); | |
76 | static void OP_C (int, int); | |
77 | static void OP_D (int, int); | |
78 | static void OP_T (int, int); | |
6f74c397 | 79 | static void OP_R (int, int); |
26ca5450 AJ |
80 | static void OP_MMX (int, int); |
81 | static void OP_XMM (int, int); | |
82 | static void OP_EM (int, int); | |
83 | static void OP_EX (int, int); | |
4d9567e0 MM |
84 | static void OP_EMC (int,int); |
85 | static void OP_MXC (int,int); | |
26ca5450 AJ |
86 | static void OP_MS (int, int); |
87 | static void OP_XS (int, int); | |
cc0ec051 | 88 | static void OP_M (int, int); |
c0f3af97 L |
89 | static void OP_VEX (int, int); |
90 | static void OP_EX_Vex (int, int); | |
922d8de8 | 91 | static void OP_EX_VexW (int, int); |
a683cc34 | 92 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 93 | static void OP_XMM_Vex (int, int); |
922d8de8 | 94 | static void OP_XMM_VexW (int, int); |
43234a1e | 95 | static void OP_Rounding (int, int); |
c0f3af97 L |
96 | static void OP_REG_VexI4 (int, int); |
97 | static void PCLMUL_Fixup (int, int); | |
c0f3af97 | 98 | static void VCMP_Fixup (int, int); |
43234a1e | 99 | static void VPCMP_Fixup (int, int); |
be92cb14 | 100 | static void VPCOM_Fixup (int, int); |
cc0ec051 | 101 | static void OP_0f07 (int, int); |
b844680a L |
102 | static void OP_Monitor (int, int); |
103 | static void OP_Mwait (int, int); | |
46e883c5 L |
104 | static void NOP_Fixup1 (int, int); |
105 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 106 | static void OP_3DNowSuffix (int, int); |
ad19981d | 107 | static void CMP_Fixup (int, int); |
26ca5450 | 108 | static void BadOp (void); |
35c52694 | 109 | static void REP_Fixup (int, int); |
d835a58b | 110 | static void SEP_Fixup (int, int); |
7e8b059b | 111 | static void BND_Fixup (int, int); |
04ef582a | 112 | static void NOTRACK_Fixup (int, int); |
42164a71 L |
113 | static void HLE_Fixup1 (int, int); |
114 | static void HLE_Fixup2 (int, int); | |
115 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 116 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 117 | static void XMM_Fixup (int, int); |
381d071f | 118 | static void CRC32_Fixup (int, int); |
eacc9c89 | 119 | static void FXSAVE_Fixup (int, int); |
15c7c1d8 | 120 | static void PCMPESTR_Fixup (int, int); |
f88c9eb0 SP |
121 | static void OP_LWPCB_E (int, int); |
122 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
123 | static void OP_Vex_2src_1 (int, int); |
124 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 125 | |
f1f8f695 | 126 | static void MOVBE_Fixup (int, int); |
bc31405e | 127 | static void MOVSXD_Fixup (int, int); |
252b5132 | 128 | |
43234a1e L |
129 | static void OP_Mask (int, int); |
130 | ||
6608db57 | 131 | struct dis_private { |
252b5132 RH |
132 | /* Points to first byte not fetched. */ |
133 | bfd_byte *max_fetched; | |
0b1cf022 | 134 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 135 | bfd_vma insn_start; |
e396998b | 136 | int orig_sizeflag; |
8df14d78 | 137 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
138 | }; |
139 | ||
cb712a9e L |
140 | enum address_mode |
141 | { | |
142 | mode_16bit, | |
143 | mode_32bit, | |
144 | mode_64bit | |
145 | }; | |
146 | ||
147 | enum address_mode address_mode; | |
52b15da3 | 148 | |
5076851f ILT |
149 | /* Flags for the prefixes for the current instruction. See below. */ |
150 | static int prefixes; | |
151 | ||
52b15da3 JH |
152 | /* REX prefix the current instruction. See below. */ |
153 | static int rex; | |
154 | /* Bits of REX we've already used. */ | |
155 | static int rex_used; | |
52b15da3 JH |
156 | /* Mark parts used in the REX prefix. When we are testing for |
157 | empty prefix (for 8bit register REX extension), just mask it | |
158 | out. Otherwise test for REX bit is excuse for existence of REX | |
159 | only in case value is nonzero. */ | |
160 | #define USED_REX(value) \ | |
161 | { \ | |
162 | if (value) \ | |
161a04f6 L |
163 | { \ |
164 | if ((rex & value)) \ | |
165 | rex_used |= (value) | REX_OPCODE; \ | |
166 | } \ | |
52b15da3 | 167 | else \ |
161a04f6 | 168 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
169 | } |
170 | ||
7d421014 ILT |
171 | /* Flags for prefixes which we somehow handled when printing the |
172 | current instruction. */ | |
173 | static int used_prefixes; | |
174 | ||
5076851f ILT |
175 | /* Flags stored in PREFIXES. */ |
176 | #define PREFIX_REPZ 1 | |
177 | #define PREFIX_REPNZ 2 | |
178 | #define PREFIX_LOCK 4 | |
179 | #define PREFIX_CS 8 | |
180 | #define PREFIX_SS 0x10 | |
181 | #define PREFIX_DS 0x20 | |
182 | #define PREFIX_ES 0x40 | |
183 | #define PREFIX_FS 0x80 | |
184 | #define PREFIX_GS 0x100 | |
185 | #define PREFIX_DATA 0x200 | |
186 | #define PREFIX_ADDR 0x400 | |
187 | #define PREFIX_FWAIT 0x800 | |
188 | ||
252b5132 RH |
189 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
190 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
191 | on error. */ | |
192 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 193 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
194 | ? 1 : fetch_data ((info), (addr))) |
195 | ||
196 | static int | |
26ca5450 | 197 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
198 | { |
199 | int status; | |
6608db57 | 200 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
201 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
202 | ||
0b1cf022 | 203 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
204 | status = (*info->read_memory_func) (start, |
205 | priv->max_fetched, | |
206 | addr - priv->max_fetched, | |
207 | info); | |
208 | else | |
209 | status = -1; | |
252b5132 RH |
210 | if (status != 0) |
211 | { | |
7d421014 | 212 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
213 | print_insn_i386 will do something sensible. Otherwise, print |
214 | an error. We do that here because this is where we know | |
215 | STATUS. */ | |
7d421014 | 216 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 217 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 218 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
219 | } |
220 | else | |
221 | priv->max_fetched = addr; | |
222 | return 1; | |
223 | } | |
224 | ||
bf890a93 | 225 | /* Possible values for prefix requirement. */ |
507bd325 L |
226 | #define PREFIX_IGNORED_SHIFT 16 |
227 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
228 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
229 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
230 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
231 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
232 | ||
233 | /* Opcode prefixes. */ | |
234 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
235 | | PREFIX_REPNZ \ | |
236 | | PREFIX_DATA) | |
237 | ||
238 | /* Prefixes ignored. */ | |
239 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
240 | | PREFIX_IGNORED_REPNZ \ | |
241 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 242 | |
ce518a5f | 243 | #define XX { NULL, 0 } |
507bd325 | 244 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
245 | |
246 | #define Eb { OP_E, b_mode } | |
7e8b059b | 247 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 248 | #define EbS { OP_E, b_swap_mode } |
9f79e886 | 249 | #define EbndS { OP_E, bnd_swap_mode } |
ce518a5f | 250 | #define Ev { OP_E, v_mode } |
de89d0a3 | 251 | #define Eva { OP_E, va_mode } |
7e8b059b | 252 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 253 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
254 | #define Ed { OP_E, d_mode } |
255 | #define Edq { OP_E, dq_mode } | |
256 | #define Edqw { OP_E, dqw_mode } | |
42903f7f | 257 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
258 | #define Edb { OP_E, db_mode } |
259 | #define Edw { OP_E, dw_mode } | |
42903f7f | 260 | #define Edqd { OP_E, dqd_mode } |
09335d05 | 261 | #define Eq { OP_E, q_mode } |
07f5af7d | 262 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
263 | #define indirEp { OP_indirE, f_mode } |
264 | #define stackEv { OP_E, stack_v_mode } | |
265 | #define Em { OP_E, m_mode } | |
266 | #define Ew { OP_E, w_mode } | |
267 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 268 | #define Ma { OP_M, a_mode } |
b844680a | 269 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 270 | #define Md { OP_M, d_mode } |
f1f8f695 | 271 | #define Mo { OP_M, o_mode } |
ce518a5f L |
272 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
273 | #define Mq { OP_M, q_mode } | |
d276ec69 | 274 | #define Mv_bnd { OP_M, v_bndmk_mode } |
4ee52178 | 275 | #define Mx { OP_M, x_mode } |
c0f3af97 | 276 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 277 | #define Gb { OP_G, b_mode } |
7e8b059b | 278 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
279 | #define Gv { OP_G, v_mode } |
280 | #define Gd { OP_G, d_mode } | |
281 | #define Gdq { OP_G, dq_mode } | |
282 | #define Gm { OP_G, m_mode } | |
c0a30a9f | 283 | #define Gva { OP_G, va_mode } |
ce518a5f | 284 | #define Gw { OP_G, w_mode } |
6f74c397 | 285 | #define Rd { OP_R, d_mode } |
43234a1e | 286 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 287 | #define Rm { OP_R, m_mode } |
ce518a5f L |
288 | #define Ib { OP_I, b_mode } |
289 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 290 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 291 | #define Iv { OP_I, v_mode } |
7bb15c6f | 292 | #define sIv { OP_sI, v_mode } |
ce518a5f | 293 | #define Iv64 { OP_I64, v_mode } |
c1dc7af5 | 294 | #define Id { OP_I, d_mode } |
ce518a5f L |
295 | #define Iw { OP_I, w_mode } |
296 | #define I1 { OP_I, const_1_mode } | |
297 | #define Jb { OP_J, b_mode } | |
298 | #define Jv { OP_J, v_mode } | |
376cd056 | 299 | #define Jdqw { OP_J, dqw_mode } |
ce518a5f L |
300 | #define Cm { OP_C, m_mode } |
301 | #define Dm { OP_D, m_mode } | |
302 | #define Td { OP_T, d_mode } | |
b844680a | 303 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
304 | |
305 | #define RMeAX { OP_REG, eAX_reg } | |
306 | #define RMeBX { OP_REG, eBX_reg } | |
307 | #define RMeCX { OP_REG, eCX_reg } | |
308 | #define RMeDX { OP_REG, eDX_reg } | |
309 | #define RMeSP { OP_REG, eSP_reg } | |
310 | #define RMeBP { OP_REG, eBP_reg } | |
311 | #define RMeSI { OP_REG, eSI_reg } | |
312 | #define RMeDI { OP_REG, eDI_reg } | |
313 | #define RMrAX { OP_REG, rAX_reg } | |
314 | #define RMrBX { OP_REG, rBX_reg } | |
315 | #define RMrCX { OP_REG, rCX_reg } | |
316 | #define RMrDX { OP_REG, rDX_reg } | |
317 | #define RMrSP { OP_REG, rSP_reg } | |
318 | #define RMrBP { OP_REG, rBP_reg } | |
319 | #define RMrSI { OP_REG, rSI_reg } | |
320 | #define RMrDI { OP_REG, rDI_reg } | |
321 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
322 | #define RMCL { OP_REG, cl_reg } |
323 | #define RMDL { OP_REG, dl_reg } | |
324 | #define RMBL { OP_REG, bl_reg } | |
325 | #define RMAH { OP_REG, ah_reg } | |
326 | #define RMCH { OP_REG, ch_reg } | |
327 | #define RMDH { OP_REG, dh_reg } | |
328 | #define RMBH { OP_REG, bh_reg } | |
329 | #define RMAX { OP_REG, ax_reg } | |
330 | #define RMDX { OP_REG, dx_reg } | |
331 | ||
332 | #define eAX { OP_IMREG, eAX_reg } | |
333 | #define eBX { OP_IMREG, eBX_reg } | |
334 | #define eCX { OP_IMREG, eCX_reg } | |
335 | #define eDX { OP_IMREG, eDX_reg } | |
336 | #define eSP { OP_IMREG, eSP_reg } | |
337 | #define eBP { OP_IMREG, eBP_reg } | |
338 | #define eSI { OP_IMREG, eSI_reg } | |
339 | #define eDI { OP_IMREG, eDI_reg } | |
340 | #define AL { OP_IMREG, al_reg } | |
341 | #define CL { OP_IMREG, cl_reg } | |
342 | #define DL { OP_IMREG, dl_reg } | |
343 | #define BL { OP_IMREG, bl_reg } | |
344 | #define AH { OP_IMREG, ah_reg } | |
345 | #define CH { OP_IMREG, ch_reg } | |
346 | #define DH { OP_IMREG, dh_reg } | |
347 | #define BH { OP_IMREG, bh_reg } | |
348 | #define AX { OP_IMREG, ax_reg } | |
349 | #define DX { OP_IMREG, dx_reg } | |
350 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
351 | #define indirDX { OP_IMREG, indir_dx_reg } | |
352 | ||
353 | #define Sw { OP_SEG, w_mode } | |
354 | #define Sv { OP_SEG, v_mode } | |
355 | #define Ap { OP_DIR, 0 } | |
356 | #define Ob { OP_OFF64, b_mode } | |
357 | #define Ov { OP_OFF64, v_mode } | |
358 | #define Xb { OP_DSreg, eSI_reg } | |
359 | #define Xv { OP_DSreg, eSI_reg } | |
360 | #define Xz { OP_DSreg, eSI_reg } | |
361 | #define Yb { OP_ESreg, eDI_reg } | |
362 | #define Yv { OP_ESreg, eDI_reg } | |
363 | #define DSBX { OP_DSreg, eBX_reg } | |
364 | ||
365 | #define es { OP_REG, es_reg } | |
366 | #define ss { OP_REG, ss_reg } | |
367 | #define cs { OP_REG, cs_reg } | |
368 | #define ds { OP_REG, ds_reg } | |
369 | #define fs { OP_REG, fs_reg } | |
370 | #define gs { OP_REG, gs_reg } | |
371 | ||
372 | #define MX { OP_MMX, 0 } | |
373 | #define XM { OP_XMM, 0 } | |
539f890d | 374 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 375 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 376 | #define XMM { OP_XMM, xmm_mode } |
43234a1e | 377 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 378 | #define EM { OP_EM, v_mode } |
b6169b20 | 379 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 380 | #define EMd { OP_EM, d_mode } |
14051056 | 381 | #define EMx { OP_EM, x_mode } |
53467f57 | 382 | #define EXbScalar { OP_EX, b_scalar_mode } |
8976381e | 383 | #define EXw { OP_EX, w_mode } |
53467f57 | 384 | #define EXwScalar { OP_EX, w_scalar_mode } |
09a2c6cf | 385 | #define EXd { OP_EX, d_mode } |
539f890d | 386 | #define EXdScalar { OP_EX, d_scalar_mode } |
fa99fab2 | 387 | #define EXdS { OP_EX, d_swap_mode } |
09a2c6cf | 388 | #define EXq { OP_EX, q_mode } |
539f890d L |
389 | #define EXqScalar { OP_EX, q_scalar_mode } |
390 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } | |
b6169b20 | 391 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 392 | #define EXx { OP_EX, x_mode } |
b6169b20 | 393 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 394 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 395 | #define EXymm { OP_EX, ymm_mode } |
c0f3af97 | 396 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 397 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
398 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
399 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
400 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
401 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
402 | #define EXxmmdw { OP_EX, xmmdw_mode } | |
403 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 404 | #define EXymmq { OP_EX, ymmq_mode } |
1c480963 | 405 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
406 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
407 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
408 | #define MS { OP_MS, v_mode } |
409 | #define XS { OP_XS, v_mode } | |
09335d05 | 410 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 411 | #define MXC { OP_MXC, 0 } |
ce518a5f | 412 | #define OPSUF { OP_3DNowSuffix, 0 } |
d835a58b | 413 | #define SEP { SEP_Fixup, 0 } |
ad19981d | 414 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 415 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 416 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
417 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
418 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 419 | |
c0f3af97 | 420 | #define Vex { OP_VEX, vex_mode } |
539f890d | 421 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 422 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
423 | #define Vex128 { OP_VEX, vex128_mode } |
424 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 425 | #define VexGdq { OP_VEX, dq_mode } |
539f890d | 426 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
539f890d | 427 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
922d8de8 DR |
428 | #define EXVexW { OP_EX_VexW, x_mode } |
429 | #define EXdVexW { OP_EX_VexW, d_mode } | |
430 | #define EXqVexW { OP_EX_VexW, q_mode } | |
a683cc34 | 431 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
539f890d | 432 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 433 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
434 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
435 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
c0f3af97 | 436 | #define VCMP { VCMP_Fixup, 0 } |
43234a1e | 437 | #define VPCMP { VPCMP_Fixup, 0 } |
be92cb14 | 438 | #define VPCOM { VPCOM_Fixup, 0 } |
43234a1e L |
439 | |
440 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
70df6fc9 | 441 | #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode } |
43234a1e L |
442 | #define EXxEVexS { OP_Rounding, evex_sae_mode } |
443 | ||
444 | #define XMask { OP_Mask, mask_mode } | |
445 | #define MaskG { OP_G, mask_mode } | |
446 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 447 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e L |
448 | #define MaskR { OP_R, mask_mode } |
449 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 450 | |
6c30d220 | 451 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 452 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 453 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 454 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 455 | |
35c52694 | 456 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
457 | #define Xbr { REP_Fixup, eSI_reg } |
458 | #define Xvr { REP_Fixup, eSI_reg } | |
459 | #define Ybr { REP_Fixup, eDI_reg } | |
460 | #define Yvr { REP_Fixup, eDI_reg } | |
461 | #define Yzr { REP_Fixup, eDI_reg } | |
462 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
463 | #define ALr { REP_Fixup, al_reg } | |
464 | #define eAXr { REP_Fixup, eAX_reg } | |
465 | ||
42164a71 L |
466 | /* Used handle HLE prefix for lockable instructions. */ |
467 | #define Ebh1 { HLE_Fixup1, b_mode } | |
468 | #define Evh1 { HLE_Fixup1, v_mode } | |
469 | #define Ebh2 { HLE_Fixup2, b_mode } | |
470 | #define Evh2 { HLE_Fixup2, v_mode } | |
471 | #define Ebh3 { HLE_Fixup3, b_mode } | |
472 | #define Evh3 { HLE_Fixup3, v_mode } | |
473 | ||
7e8b059b | 474 | #define BND { BND_Fixup, 0 } |
04ef582a | 475 | #define NOTRACK { NOTRACK_Fixup, 0 } |
7e8b059b | 476 | |
ce518a5f L |
477 | #define cond_jump_flag { NULL, cond_jump_mode } |
478 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 479 | |
252b5132 | 480 | /* bits in sizeflag */ |
252b5132 | 481 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
482 | #define AFLAG 2 |
483 | #define DFLAG 1 | |
484 | ||
51e7da1b L |
485 | enum |
486 | { | |
487 | /* byte operand */ | |
488 | b_mode = 1, | |
489 | /* byte operand with operand swapped */ | |
3873ba12 | 490 | b_swap_mode, |
e3949f17 L |
491 | /* byte operand, sign extend like 'T' suffix */ |
492 | b_T_mode, | |
51e7da1b | 493 | /* operand size depends on prefixes */ |
3873ba12 | 494 | v_mode, |
51e7da1b | 495 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 496 | v_swap_mode, |
de89d0a3 IT |
497 | /* operand size depends on address prefix */ |
498 | va_mode, | |
51e7da1b | 499 | /* word operand */ |
3873ba12 | 500 | w_mode, |
51e7da1b | 501 | /* double word operand */ |
3873ba12 | 502 | d_mode, |
51e7da1b | 503 | /* double word operand with operand swapped */ |
3873ba12 | 504 | d_swap_mode, |
51e7da1b | 505 | /* quad word operand */ |
3873ba12 | 506 | q_mode, |
51e7da1b | 507 | /* quad word operand with operand swapped */ |
3873ba12 | 508 | q_swap_mode, |
51e7da1b | 509 | /* ten-byte operand */ |
3873ba12 | 510 | t_mode, |
43234a1e L |
511 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
512 | broadcast enabled. */ | |
3873ba12 | 513 | x_mode, |
43234a1e L |
514 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
515 | evex_x_gscat_mode, | |
516 | /* Similar to x_mode, but with disabled broadcast. */ | |
517 | evex_x_nobcst_mode, | |
518 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
519 | in EVEX. */ | |
3873ba12 | 520 | x_swap_mode, |
51e7da1b | 521 | /* 16-byte XMM operand */ |
3873ba12 | 522 | xmm_mode, |
43234a1e L |
523 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
524 | memory operand (depending on vector length). Broadcast isn't | |
525 | allowed. */ | |
3873ba12 | 526 | xmmq_mode, |
43234a1e L |
527 | /* Same as xmmq_mode, but broadcast is allowed. */ |
528 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
529 | /* XMM register or byte memory operand */ |
530 | xmm_mb_mode, | |
531 | /* XMM register or word memory operand */ | |
532 | xmm_mw_mode, | |
533 | /* XMM register or double word memory operand */ | |
534 | xmm_md_mode, | |
535 | /* XMM register or quad word memory operand */ | |
536 | xmm_mq_mode, | |
43234a1e | 537 | /* 16-byte XMM, word, double word or quad word operand. */ |
6c30d220 | 538 | xmmdw_mode, |
43234a1e | 539 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 540 | xmmqd_mode, |
43234a1e L |
541 | /* 32-byte YMM operand */ |
542 | ymm_mode, | |
543 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 544 | ymmq_mode, |
6c30d220 L |
545 | /* 32-byte YMM or 16-byte word operand */ |
546 | ymmxmm_mode, | |
51e7da1b | 547 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 548 | m_mode, |
51e7da1b | 549 | /* pair of v_mode operands */ |
3873ba12 L |
550 | a_mode, |
551 | cond_jump_mode, | |
552 | loop_jcxz_mode, | |
bc31405e | 553 | movsxd_mode, |
7e8b059b | 554 | v_bnd_mode, |
d276ec69 JB |
555 | /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */ |
556 | v_bndmk_mode, | |
51e7da1b | 557 | /* operand size depends on REX prefixes. */ |
3873ba12 | 558 | dq_mode, |
376cd056 JB |
559 | /* registers like dq_mode, memory like w_mode, displacements like |
560 | v_mode without considering Intel64 ISA. */ | |
3873ba12 | 561 | dqw_mode, |
9f79e886 | 562 | /* bounds operand */ |
7e8b059b | 563 | bnd_mode, |
9f79e886 JB |
564 | /* bounds operand with operand swapped */ |
565 | bnd_swap_mode, | |
51e7da1b | 566 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
567 | f_mode, |
568 | const_1_mode, | |
07f5af7d L |
569 | /* v_mode for indirect branch opcodes. */ |
570 | indir_v_mode, | |
51e7da1b | 571 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 572 | stack_v_mode, |
51e7da1b | 573 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 574 | z_mode, |
51e7da1b | 575 | /* 16-byte operand */ |
3873ba12 | 576 | o_mode, |
51e7da1b | 577 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 578 | dqb_mode, |
1ba585e8 IT |
579 | /* registers like d_mode, memory like b_mode. */ |
580 | db_mode, | |
581 | /* registers like d_mode, memory like w_mode. */ | |
582 | dw_mode, | |
51e7da1b | 583 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 584 | dqd_mode, |
51e7da1b | 585 | /* normal vex mode */ |
3873ba12 | 586 | vex_mode, |
51e7da1b | 587 | /* 128bit vex mode */ |
3873ba12 | 588 | vex128_mode, |
51e7da1b | 589 | /* 256bit vex mode */ |
3873ba12 | 590 | vex256_mode, |
d55ee72f | 591 | |
825bd36c | 592 | /* Operand size depends on the VEX.W bit, with VSIB dword indices. */ |
6c30d220 | 593 | vex_vsib_d_w_dq_mode, |
5fc35d96 IT |
594 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
595 | vex_vsib_d_w_d_mode, | |
825bd36c | 596 | /* Operand size depends on the VEX.W bit, with VSIB qword indices. */ |
6c30d220 | 597 | vex_vsib_q_w_dq_mode, |
5fc35d96 IT |
598 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
599 | vex_vsib_q_w_d_mode, | |
6c30d220 | 600 | |
539f890d L |
601 | /* scalar, ignore vector length. */ |
602 | scalar_mode, | |
53467f57 IT |
603 | /* like b_mode, ignore vector length. */ |
604 | b_scalar_mode, | |
605 | /* like w_mode, ignore vector length. */ | |
606 | w_scalar_mode, | |
539f890d L |
607 | /* like d_mode, ignore vector length. */ |
608 | d_scalar_mode, | |
609 | /* like d_swap_mode, ignore vector length. */ | |
610 | d_scalar_swap_mode, | |
611 | /* like q_mode, ignore vector length. */ | |
612 | q_scalar_mode, | |
613 | /* like q_swap_mode, ignore vector length. */ | |
614 | q_scalar_swap_mode, | |
615 | /* like vex_mode, ignore vector length. */ | |
616 | vex_scalar_mode, | |
825bd36c | 617 | /* Operand size depends on the VEX.W bit, ignore vector length. */ |
1c480963 | 618 | vex_scalar_w_dq_mode, |
539f890d | 619 | |
43234a1e L |
620 | /* Static rounding. */ |
621 | evex_rounding_mode, | |
70df6fc9 L |
622 | /* Static rounding, 64-bit mode only. */ |
623 | evex_rounding_64_mode, | |
43234a1e L |
624 | /* Supress all exceptions. */ |
625 | evex_sae_mode, | |
626 | ||
627 | /* Mask register operand. */ | |
628 | mask_mode, | |
1ba585e8 IT |
629 | /* Mask register operand. */ |
630 | mask_bd_mode, | |
43234a1e | 631 | |
3873ba12 L |
632 | es_reg, |
633 | cs_reg, | |
634 | ss_reg, | |
635 | ds_reg, | |
636 | fs_reg, | |
637 | gs_reg, | |
d55ee72f | 638 | |
3873ba12 L |
639 | eAX_reg, |
640 | eCX_reg, | |
641 | eDX_reg, | |
642 | eBX_reg, | |
643 | eSP_reg, | |
644 | eBP_reg, | |
645 | eSI_reg, | |
646 | eDI_reg, | |
d55ee72f | 647 | |
3873ba12 L |
648 | al_reg, |
649 | cl_reg, | |
650 | dl_reg, | |
651 | bl_reg, | |
652 | ah_reg, | |
653 | ch_reg, | |
654 | dh_reg, | |
655 | bh_reg, | |
d55ee72f | 656 | |
3873ba12 L |
657 | ax_reg, |
658 | cx_reg, | |
659 | dx_reg, | |
660 | bx_reg, | |
661 | sp_reg, | |
662 | bp_reg, | |
663 | si_reg, | |
664 | di_reg, | |
d55ee72f | 665 | |
3873ba12 L |
666 | rAX_reg, |
667 | rCX_reg, | |
668 | rDX_reg, | |
669 | rBX_reg, | |
670 | rSP_reg, | |
671 | rBP_reg, | |
672 | rSI_reg, | |
673 | rDI_reg, | |
d55ee72f | 674 | |
3873ba12 L |
675 | z_mode_ax_reg, |
676 | indir_dx_reg | |
51e7da1b | 677 | }; |
252b5132 | 678 | |
51e7da1b L |
679 | enum |
680 | { | |
681 | FLOATCODE = 1, | |
3873ba12 L |
682 | USE_REG_TABLE, |
683 | USE_MOD_TABLE, | |
684 | USE_RM_TABLE, | |
685 | USE_PREFIX_TABLE, | |
686 | USE_X86_64_TABLE, | |
687 | USE_3BYTE_TABLE, | |
f88c9eb0 | 688 | USE_XOP_8F_TABLE, |
3873ba12 L |
689 | USE_VEX_C4_TABLE, |
690 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 691 | USE_VEX_LEN_TABLE, |
43234a1e | 692 | USE_VEX_W_TABLE, |
04e2a182 L |
693 | USE_EVEX_TABLE, |
694 | USE_EVEX_LEN_TABLE | |
51e7da1b | 695 | }; |
6439fc28 | 696 | |
bf890a93 | 697 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 698 | |
bf890a93 IT |
699 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
700 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
701 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
702 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
703 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
704 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
705 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
706 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 707 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 708 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
709 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
710 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
711 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 712 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 713 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
04e2a182 | 714 | #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I)) |
1ceb70f8 | 715 | |
51e7da1b L |
716 | enum |
717 | { | |
718 | REG_80 = 0, | |
3873ba12 | 719 | REG_81, |
7148c369 | 720 | REG_83, |
3873ba12 L |
721 | REG_8F, |
722 | REG_C0, | |
723 | REG_C1, | |
724 | REG_C6, | |
725 | REG_C7, | |
726 | REG_D0, | |
727 | REG_D1, | |
728 | REG_D2, | |
729 | REG_D3, | |
730 | REG_F6, | |
731 | REG_F7, | |
732 | REG_FE, | |
733 | REG_FF, | |
734 | REG_0F00, | |
735 | REG_0F01, | |
736 | REG_0F0D, | |
737 | REG_0F18, | |
f8687e93 JB |
738 | REG_0F1C_P_0_MOD_0, |
739 | REG_0F1E_P_1_MOD_3, | |
3873ba12 L |
740 | REG_0F71, |
741 | REG_0F72, | |
742 | REG_0F73, | |
743 | REG_0FA6, | |
744 | REG_0FA7, | |
745 | REG_0FAE, | |
746 | REG_0FBA, | |
747 | REG_0FC7, | |
592a252b L |
748 | REG_VEX_0F71, |
749 | REG_VEX_0F72, | |
750 | REG_VEX_0F73, | |
751 | REG_VEX_0FAE, | |
f12dc422 | 752 | REG_VEX_0F38F3, |
f88c9eb0 | 753 | REG_XOP_LWPCB, |
2a2a0f38 QN |
754 | REG_XOP_LWP, |
755 | REG_XOP_TBM_01, | |
43234a1e L |
756 | REG_XOP_TBM_02, |
757 | ||
1ba585e8 | 758 | REG_EVEX_0F71, |
43234a1e L |
759 | REG_EVEX_0F72, |
760 | REG_EVEX_0F73, | |
761 | REG_EVEX_0F38C6, | |
762 | REG_EVEX_0F38C7 | |
51e7da1b | 763 | }; |
1ceb70f8 | 764 | |
51e7da1b L |
765 | enum |
766 | { | |
767 | MOD_8D = 0, | |
42164a71 L |
768 | MOD_C6_REG_7, |
769 | MOD_C7_REG_7, | |
4a357820 MZ |
770 | MOD_FF_REG_3, |
771 | MOD_FF_REG_5, | |
3873ba12 L |
772 | MOD_0F01_REG_0, |
773 | MOD_0F01_REG_1, | |
774 | MOD_0F01_REG_2, | |
775 | MOD_0F01_REG_3, | |
8eab4136 | 776 | MOD_0F01_REG_5, |
3873ba12 L |
777 | MOD_0F01_REG_7, |
778 | MOD_0F12_PREFIX_0, | |
18897deb | 779 | MOD_0F12_PREFIX_2, |
3873ba12 L |
780 | MOD_0F13, |
781 | MOD_0F16_PREFIX_0, | |
18897deb | 782 | MOD_0F16_PREFIX_2, |
3873ba12 L |
783 | MOD_0F17, |
784 | MOD_0F18_REG_0, | |
785 | MOD_0F18_REG_1, | |
786 | MOD_0F18_REG_2, | |
787 | MOD_0F18_REG_3, | |
d7189fa5 RM |
788 | MOD_0F18_REG_4, |
789 | MOD_0F18_REG_5, | |
790 | MOD_0F18_REG_6, | |
791 | MOD_0F18_REG_7, | |
7e8b059b L |
792 | MOD_0F1A_PREFIX_0, |
793 | MOD_0F1B_PREFIX_0, | |
794 | MOD_0F1B_PREFIX_1, | |
c48935d7 | 795 | MOD_0F1C_PREFIX_0, |
603555e5 | 796 | MOD_0F1E_PREFIX_1, |
3873ba12 L |
797 | MOD_0F24, |
798 | MOD_0F26, | |
799 | MOD_0F2B_PREFIX_0, | |
800 | MOD_0F2B_PREFIX_1, | |
801 | MOD_0F2B_PREFIX_2, | |
802 | MOD_0F2B_PREFIX_3, | |
a5aaedb9 | 803 | MOD_0F50, |
3873ba12 L |
804 | MOD_0F71_REG_2, |
805 | MOD_0F71_REG_4, | |
806 | MOD_0F71_REG_6, | |
807 | MOD_0F72_REG_2, | |
808 | MOD_0F72_REG_4, | |
809 | MOD_0F72_REG_6, | |
810 | MOD_0F73_REG_2, | |
811 | MOD_0F73_REG_3, | |
812 | MOD_0F73_REG_6, | |
813 | MOD_0F73_REG_7, | |
814 | MOD_0FAE_REG_0, | |
815 | MOD_0FAE_REG_1, | |
816 | MOD_0FAE_REG_2, | |
817 | MOD_0FAE_REG_3, | |
818 | MOD_0FAE_REG_4, | |
819 | MOD_0FAE_REG_5, | |
820 | MOD_0FAE_REG_6, | |
821 | MOD_0FAE_REG_7, | |
822 | MOD_0FB2, | |
823 | MOD_0FB4, | |
824 | MOD_0FB5, | |
a8484f96 | 825 | MOD_0FC3, |
963f3586 IT |
826 | MOD_0FC7_REG_3, |
827 | MOD_0FC7_REG_4, | |
828 | MOD_0FC7_REG_5, | |
3873ba12 L |
829 | MOD_0FC7_REG_6, |
830 | MOD_0FC7_REG_7, | |
831 | MOD_0FD7, | |
832 | MOD_0FE7_PREFIX_2, | |
833 | MOD_0FF0_PREFIX_3, | |
834 | MOD_0F382A_PREFIX_2, | |
603555e5 L |
835 | MOD_0F38F5_PREFIX_2, |
836 | MOD_0F38F6_PREFIX_0, | |
5d79adc4 | 837 | MOD_0F38F8_PREFIX_1, |
c0a30a9f | 838 | MOD_0F38F8_PREFIX_2, |
5d79adc4 | 839 | MOD_0F38F8_PREFIX_3, |
c0a30a9f | 840 | MOD_0F38F9_PREFIX_0, |
3873ba12 L |
841 | MOD_62_32BIT, |
842 | MOD_C4_32BIT, | |
843 | MOD_C5_32BIT, | |
592a252b | 844 | MOD_VEX_0F12_PREFIX_0, |
18897deb | 845 | MOD_VEX_0F12_PREFIX_2, |
592a252b L |
846 | MOD_VEX_0F13, |
847 | MOD_VEX_0F16_PREFIX_0, | |
18897deb | 848 | MOD_VEX_0F16_PREFIX_2, |
592a252b L |
849 | MOD_VEX_0F17, |
850 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
851 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
852 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
853 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
854 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
855 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
856 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
857 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
858 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
859 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
860 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
861 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
862 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
863 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
864 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
865 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
866 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
867 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
868 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
869 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
870 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
871 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
872 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
873 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
874 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
875 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
876 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
877 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
878 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
879 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
880 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
881 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
882 | MOD_VEX_0F50, |
883 | MOD_VEX_0F71_REG_2, | |
884 | MOD_VEX_0F71_REG_4, | |
885 | MOD_VEX_0F71_REG_6, | |
886 | MOD_VEX_0F72_REG_2, | |
887 | MOD_VEX_0F72_REG_4, | |
888 | MOD_VEX_0F72_REG_6, | |
889 | MOD_VEX_0F73_REG_2, | |
890 | MOD_VEX_0F73_REG_3, | |
891 | MOD_VEX_0F73_REG_6, | |
892 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
893 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
894 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
895 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
896 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
897 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
898 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
58a211d2 | 899 | MOD_VEX_0F92_P_3_LEN_0, |
ab4e4ed5 AF |
900 | MOD_VEX_W_0_0F93_P_0_LEN_0, |
901 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
58a211d2 | 902 | MOD_VEX_0F93_P_3_LEN_0, |
ab4e4ed5 AF |
903 | MOD_VEX_W_0_0F98_P_0_LEN_0, |
904 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
905 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
906 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
907 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
908 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
909 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
910 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
911 | MOD_VEX_0FAE_REG_2, |
912 | MOD_VEX_0FAE_REG_3, | |
913 | MOD_VEX_0FD7_PREFIX_2, | |
914 | MOD_VEX_0FE7_PREFIX_2, | |
915 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
916 | MOD_VEX_0F381A_PREFIX_2, |
917 | MOD_VEX_0F382A_PREFIX_2, | |
918 | MOD_VEX_0F382C_PREFIX_2, | |
919 | MOD_VEX_0F382D_PREFIX_2, | |
920 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
921 | MOD_VEX_0F382F_PREFIX_2, |
922 | MOD_VEX_0F385A_PREFIX_2, | |
923 | MOD_VEX_0F388C_PREFIX_2, | |
924 | MOD_VEX_0F388E_PREFIX_2, | |
ab4e4ed5 AF |
925 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
926 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
927 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, | |
928 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
929 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, | |
930 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
931 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, | |
932 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, | |
43234a1e | 933 | |
43234a1e | 934 | MOD_EVEX_0F12_PREFIX_0, |
97e6786a JB |
935 | MOD_EVEX_0F12_PREFIX_2, |
936 | MOD_EVEX_0F13, | |
43234a1e | 937 | MOD_EVEX_0F16_PREFIX_0, |
97e6786a JB |
938 | MOD_EVEX_0F16_PREFIX_2, |
939 | MOD_EVEX_0F17, | |
940 | MOD_EVEX_0F2B, | |
43234a1e L |
941 | MOD_EVEX_0F38C6_REG_1, |
942 | MOD_EVEX_0F38C6_REG_2, | |
943 | MOD_EVEX_0F38C6_REG_5, | |
944 | MOD_EVEX_0F38C6_REG_6, | |
945 | MOD_EVEX_0F38C7_REG_1, | |
946 | MOD_EVEX_0F38C7_REG_2, | |
947 | MOD_EVEX_0F38C7_REG_5, | |
948 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 949 | }; |
1ceb70f8 | 950 | |
51e7da1b L |
951 | enum |
952 | { | |
42164a71 L |
953 | RM_C6_REG_7 = 0, |
954 | RM_C7_REG_7, | |
955 | RM_0F01_REG_0, | |
3873ba12 L |
956 | RM_0F01_REG_1, |
957 | RM_0F01_REG_2, | |
958 | RM_0F01_REG_3, | |
f8687e93 JB |
959 | RM_0F01_REG_5_MOD_3, |
960 | RM_0F01_REG_7_MOD_3, | |
961 | RM_0F1E_P_1_MOD_3_REG_7, | |
962 | RM_0FAE_REG_6_MOD_3_P_0, | |
963 | RM_0FAE_REG_7_MOD_3, | |
51e7da1b | 964 | }; |
1ceb70f8 | 965 | |
51e7da1b L |
966 | enum |
967 | { | |
968 | PREFIX_90 = 0, | |
a847e322 | 969 | PREFIX_0F01_REG_3_RM_1, |
f8687e93 JB |
970 | PREFIX_0F01_REG_5_MOD_0, |
971 | PREFIX_0F01_REG_5_MOD_3_RM_0, | |
bb651e8b | 972 | PREFIX_0F01_REG_5_MOD_3_RM_1, |
f8687e93 | 973 | PREFIX_0F01_REG_5_MOD_3_RM_2, |
267b8516 JB |
974 | PREFIX_0F01_REG_7_MOD_3_RM_2, |
975 | PREFIX_0F01_REG_7_MOD_3_RM_3, | |
3233d7d0 | 976 | PREFIX_0F09, |
3873ba12 L |
977 | PREFIX_0F10, |
978 | PREFIX_0F11, | |
979 | PREFIX_0F12, | |
980 | PREFIX_0F16, | |
7e8b059b L |
981 | PREFIX_0F1A, |
982 | PREFIX_0F1B, | |
c48935d7 | 983 | PREFIX_0F1C, |
603555e5 | 984 | PREFIX_0F1E, |
3873ba12 L |
985 | PREFIX_0F2A, |
986 | PREFIX_0F2B, | |
987 | PREFIX_0F2C, | |
988 | PREFIX_0F2D, | |
989 | PREFIX_0F2E, | |
990 | PREFIX_0F2F, | |
991 | PREFIX_0F51, | |
992 | PREFIX_0F52, | |
993 | PREFIX_0F53, | |
994 | PREFIX_0F58, | |
995 | PREFIX_0F59, | |
996 | PREFIX_0F5A, | |
997 | PREFIX_0F5B, | |
998 | PREFIX_0F5C, | |
999 | PREFIX_0F5D, | |
1000 | PREFIX_0F5E, | |
1001 | PREFIX_0F5F, | |
1002 | PREFIX_0F60, | |
1003 | PREFIX_0F61, | |
1004 | PREFIX_0F62, | |
1005 | PREFIX_0F6C, | |
1006 | PREFIX_0F6D, | |
1007 | PREFIX_0F6F, | |
1008 | PREFIX_0F70, | |
1009 | PREFIX_0F73_REG_3, | |
1010 | PREFIX_0F73_REG_7, | |
1011 | PREFIX_0F78, | |
1012 | PREFIX_0F79, | |
1013 | PREFIX_0F7C, | |
1014 | PREFIX_0F7D, | |
1015 | PREFIX_0F7E, | |
1016 | PREFIX_0F7F, | |
f8687e93 JB |
1017 | PREFIX_0FAE_REG_0_MOD_3, |
1018 | PREFIX_0FAE_REG_1_MOD_3, | |
1019 | PREFIX_0FAE_REG_2_MOD_3, | |
1020 | PREFIX_0FAE_REG_3_MOD_3, | |
1021 | PREFIX_0FAE_REG_4_MOD_0, | |
1022 | PREFIX_0FAE_REG_4_MOD_3, | |
1023 | PREFIX_0FAE_REG_5_MOD_0, | |
1024 | PREFIX_0FAE_REG_5_MOD_3, | |
1025 | PREFIX_0FAE_REG_6_MOD_0, | |
1026 | PREFIX_0FAE_REG_6_MOD_3, | |
1027 | PREFIX_0FAE_REG_7_MOD_0, | |
3873ba12 | 1028 | PREFIX_0FB8, |
f12dc422 | 1029 | PREFIX_0FBC, |
3873ba12 L |
1030 | PREFIX_0FBD, |
1031 | PREFIX_0FC2, | |
f8687e93 JB |
1032 | PREFIX_0FC3_MOD_0, |
1033 | PREFIX_0FC7_REG_6_MOD_0, | |
1034 | PREFIX_0FC7_REG_6_MOD_3, | |
1035 | PREFIX_0FC7_REG_7_MOD_3, | |
3873ba12 L |
1036 | PREFIX_0FD0, |
1037 | PREFIX_0FD6, | |
1038 | PREFIX_0FE6, | |
1039 | PREFIX_0FE7, | |
1040 | PREFIX_0FF0, | |
1041 | PREFIX_0FF7, | |
1042 | PREFIX_0F3810, | |
1043 | PREFIX_0F3814, | |
1044 | PREFIX_0F3815, | |
1045 | PREFIX_0F3817, | |
1046 | PREFIX_0F3820, | |
1047 | PREFIX_0F3821, | |
1048 | PREFIX_0F3822, | |
1049 | PREFIX_0F3823, | |
1050 | PREFIX_0F3824, | |
1051 | PREFIX_0F3825, | |
1052 | PREFIX_0F3828, | |
1053 | PREFIX_0F3829, | |
1054 | PREFIX_0F382A, | |
1055 | PREFIX_0F382B, | |
1056 | PREFIX_0F3830, | |
1057 | PREFIX_0F3831, | |
1058 | PREFIX_0F3832, | |
1059 | PREFIX_0F3833, | |
1060 | PREFIX_0F3834, | |
1061 | PREFIX_0F3835, | |
1062 | PREFIX_0F3837, | |
1063 | PREFIX_0F3838, | |
1064 | PREFIX_0F3839, | |
1065 | PREFIX_0F383A, | |
1066 | PREFIX_0F383B, | |
1067 | PREFIX_0F383C, | |
1068 | PREFIX_0F383D, | |
1069 | PREFIX_0F383E, | |
1070 | PREFIX_0F383F, | |
1071 | PREFIX_0F3840, | |
1072 | PREFIX_0F3841, | |
1073 | PREFIX_0F3880, | |
1074 | PREFIX_0F3881, | |
6c30d220 | 1075 | PREFIX_0F3882, |
a0046408 L |
1076 | PREFIX_0F38C8, |
1077 | PREFIX_0F38C9, | |
1078 | PREFIX_0F38CA, | |
1079 | PREFIX_0F38CB, | |
1080 | PREFIX_0F38CC, | |
1081 | PREFIX_0F38CD, | |
48521003 | 1082 | PREFIX_0F38CF, |
3873ba12 L |
1083 | PREFIX_0F38DB, |
1084 | PREFIX_0F38DC, | |
1085 | PREFIX_0F38DD, | |
1086 | PREFIX_0F38DE, | |
1087 | PREFIX_0F38DF, | |
1088 | PREFIX_0F38F0, | |
1089 | PREFIX_0F38F1, | |
603555e5 | 1090 | PREFIX_0F38F5, |
e2e1fcde | 1091 | PREFIX_0F38F6, |
c0a30a9f L |
1092 | PREFIX_0F38F8, |
1093 | PREFIX_0F38F9, | |
3873ba12 L |
1094 | PREFIX_0F3A08, |
1095 | PREFIX_0F3A09, | |
1096 | PREFIX_0F3A0A, | |
1097 | PREFIX_0F3A0B, | |
1098 | PREFIX_0F3A0C, | |
1099 | PREFIX_0F3A0D, | |
1100 | PREFIX_0F3A0E, | |
1101 | PREFIX_0F3A14, | |
1102 | PREFIX_0F3A15, | |
1103 | PREFIX_0F3A16, | |
1104 | PREFIX_0F3A17, | |
1105 | PREFIX_0F3A20, | |
1106 | PREFIX_0F3A21, | |
1107 | PREFIX_0F3A22, | |
1108 | PREFIX_0F3A40, | |
1109 | PREFIX_0F3A41, | |
1110 | PREFIX_0F3A42, | |
1111 | PREFIX_0F3A44, | |
1112 | PREFIX_0F3A60, | |
1113 | PREFIX_0F3A61, | |
1114 | PREFIX_0F3A62, | |
1115 | PREFIX_0F3A63, | |
a0046408 | 1116 | PREFIX_0F3ACC, |
48521003 IT |
1117 | PREFIX_0F3ACE, |
1118 | PREFIX_0F3ACF, | |
3873ba12 | 1119 | PREFIX_0F3ADF, |
592a252b L |
1120 | PREFIX_VEX_0F10, |
1121 | PREFIX_VEX_0F11, | |
1122 | PREFIX_VEX_0F12, | |
1123 | PREFIX_VEX_0F16, | |
1124 | PREFIX_VEX_0F2A, | |
1125 | PREFIX_VEX_0F2C, | |
1126 | PREFIX_VEX_0F2D, | |
1127 | PREFIX_VEX_0F2E, | |
1128 | PREFIX_VEX_0F2F, | |
43234a1e L |
1129 | PREFIX_VEX_0F41, |
1130 | PREFIX_VEX_0F42, | |
1131 | PREFIX_VEX_0F44, | |
1132 | PREFIX_VEX_0F45, | |
1133 | PREFIX_VEX_0F46, | |
1134 | PREFIX_VEX_0F47, | |
1ba585e8 | 1135 | PREFIX_VEX_0F4A, |
43234a1e | 1136 | PREFIX_VEX_0F4B, |
592a252b L |
1137 | PREFIX_VEX_0F51, |
1138 | PREFIX_VEX_0F52, | |
1139 | PREFIX_VEX_0F53, | |
1140 | PREFIX_VEX_0F58, | |
1141 | PREFIX_VEX_0F59, | |
1142 | PREFIX_VEX_0F5A, | |
1143 | PREFIX_VEX_0F5B, | |
1144 | PREFIX_VEX_0F5C, | |
1145 | PREFIX_VEX_0F5D, | |
1146 | PREFIX_VEX_0F5E, | |
1147 | PREFIX_VEX_0F5F, | |
1148 | PREFIX_VEX_0F60, | |
1149 | PREFIX_VEX_0F61, | |
1150 | PREFIX_VEX_0F62, | |
1151 | PREFIX_VEX_0F63, | |
1152 | PREFIX_VEX_0F64, | |
1153 | PREFIX_VEX_0F65, | |
1154 | PREFIX_VEX_0F66, | |
1155 | PREFIX_VEX_0F67, | |
1156 | PREFIX_VEX_0F68, | |
1157 | PREFIX_VEX_0F69, | |
1158 | PREFIX_VEX_0F6A, | |
1159 | PREFIX_VEX_0F6B, | |
1160 | PREFIX_VEX_0F6C, | |
1161 | PREFIX_VEX_0F6D, | |
1162 | PREFIX_VEX_0F6E, | |
1163 | PREFIX_VEX_0F6F, | |
1164 | PREFIX_VEX_0F70, | |
1165 | PREFIX_VEX_0F71_REG_2, | |
1166 | PREFIX_VEX_0F71_REG_4, | |
1167 | PREFIX_VEX_0F71_REG_6, | |
1168 | PREFIX_VEX_0F72_REG_2, | |
1169 | PREFIX_VEX_0F72_REG_4, | |
1170 | PREFIX_VEX_0F72_REG_6, | |
1171 | PREFIX_VEX_0F73_REG_2, | |
1172 | PREFIX_VEX_0F73_REG_3, | |
1173 | PREFIX_VEX_0F73_REG_6, | |
1174 | PREFIX_VEX_0F73_REG_7, | |
1175 | PREFIX_VEX_0F74, | |
1176 | PREFIX_VEX_0F75, | |
1177 | PREFIX_VEX_0F76, | |
1178 | PREFIX_VEX_0F77, | |
1179 | PREFIX_VEX_0F7C, | |
1180 | PREFIX_VEX_0F7D, | |
1181 | PREFIX_VEX_0F7E, | |
1182 | PREFIX_VEX_0F7F, | |
43234a1e L |
1183 | PREFIX_VEX_0F90, |
1184 | PREFIX_VEX_0F91, | |
1185 | PREFIX_VEX_0F92, | |
1186 | PREFIX_VEX_0F93, | |
1187 | PREFIX_VEX_0F98, | |
1ba585e8 | 1188 | PREFIX_VEX_0F99, |
592a252b L |
1189 | PREFIX_VEX_0FC2, |
1190 | PREFIX_VEX_0FC4, | |
1191 | PREFIX_VEX_0FC5, | |
1192 | PREFIX_VEX_0FD0, | |
1193 | PREFIX_VEX_0FD1, | |
1194 | PREFIX_VEX_0FD2, | |
1195 | PREFIX_VEX_0FD3, | |
1196 | PREFIX_VEX_0FD4, | |
1197 | PREFIX_VEX_0FD5, | |
1198 | PREFIX_VEX_0FD6, | |
1199 | PREFIX_VEX_0FD7, | |
1200 | PREFIX_VEX_0FD8, | |
1201 | PREFIX_VEX_0FD9, | |
1202 | PREFIX_VEX_0FDA, | |
1203 | PREFIX_VEX_0FDB, | |
1204 | PREFIX_VEX_0FDC, | |
1205 | PREFIX_VEX_0FDD, | |
1206 | PREFIX_VEX_0FDE, | |
1207 | PREFIX_VEX_0FDF, | |
1208 | PREFIX_VEX_0FE0, | |
1209 | PREFIX_VEX_0FE1, | |
1210 | PREFIX_VEX_0FE2, | |
1211 | PREFIX_VEX_0FE3, | |
1212 | PREFIX_VEX_0FE4, | |
1213 | PREFIX_VEX_0FE5, | |
1214 | PREFIX_VEX_0FE6, | |
1215 | PREFIX_VEX_0FE7, | |
1216 | PREFIX_VEX_0FE8, | |
1217 | PREFIX_VEX_0FE9, | |
1218 | PREFIX_VEX_0FEA, | |
1219 | PREFIX_VEX_0FEB, | |
1220 | PREFIX_VEX_0FEC, | |
1221 | PREFIX_VEX_0FED, | |
1222 | PREFIX_VEX_0FEE, | |
1223 | PREFIX_VEX_0FEF, | |
1224 | PREFIX_VEX_0FF0, | |
1225 | PREFIX_VEX_0FF1, | |
1226 | PREFIX_VEX_0FF2, | |
1227 | PREFIX_VEX_0FF3, | |
1228 | PREFIX_VEX_0FF4, | |
1229 | PREFIX_VEX_0FF5, | |
1230 | PREFIX_VEX_0FF6, | |
1231 | PREFIX_VEX_0FF7, | |
1232 | PREFIX_VEX_0FF8, | |
1233 | PREFIX_VEX_0FF9, | |
1234 | PREFIX_VEX_0FFA, | |
1235 | PREFIX_VEX_0FFB, | |
1236 | PREFIX_VEX_0FFC, | |
1237 | PREFIX_VEX_0FFD, | |
1238 | PREFIX_VEX_0FFE, | |
1239 | PREFIX_VEX_0F3800, | |
1240 | PREFIX_VEX_0F3801, | |
1241 | PREFIX_VEX_0F3802, | |
1242 | PREFIX_VEX_0F3803, | |
1243 | PREFIX_VEX_0F3804, | |
1244 | PREFIX_VEX_0F3805, | |
1245 | PREFIX_VEX_0F3806, | |
1246 | PREFIX_VEX_0F3807, | |
1247 | PREFIX_VEX_0F3808, | |
1248 | PREFIX_VEX_0F3809, | |
1249 | PREFIX_VEX_0F380A, | |
1250 | PREFIX_VEX_0F380B, | |
1251 | PREFIX_VEX_0F380C, | |
1252 | PREFIX_VEX_0F380D, | |
1253 | PREFIX_VEX_0F380E, | |
1254 | PREFIX_VEX_0F380F, | |
1255 | PREFIX_VEX_0F3813, | |
6c30d220 | 1256 | PREFIX_VEX_0F3816, |
592a252b L |
1257 | PREFIX_VEX_0F3817, |
1258 | PREFIX_VEX_0F3818, | |
1259 | PREFIX_VEX_0F3819, | |
1260 | PREFIX_VEX_0F381A, | |
1261 | PREFIX_VEX_0F381C, | |
1262 | PREFIX_VEX_0F381D, | |
1263 | PREFIX_VEX_0F381E, | |
1264 | PREFIX_VEX_0F3820, | |
1265 | PREFIX_VEX_0F3821, | |
1266 | PREFIX_VEX_0F3822, | |
1267 | PREFIX_VEX_0F3823, | |
1268 | PREFIX_VEX_0F3824, | |
1269 | PREFIX_VEX_0F3825, | |
1270 | PREFIX_VEX_0F3828, | |
1271 | PREFIX_VEX_0F3829, | |
1272 | PREFIX_VEX_0F382A, | |
1273 | PREFIX_VEX_0F382B, | |
1274 | PREFIX_VEX_0F382C, | |
1275 | PREFIX_VEX_0F382D, | |
1276 | PREFIX_VEX_0F382E, | |
1277 | PREFIX_VEX_0F382F, | |
1278 | PREFIX_VEX_0F3830, | |
1279 | PREFIX_VEX_0F3831, | |
1280 | PREFIX_VEX_0F3832, | |
1281 | PREFIX_VEX_0F3833, | |
1282 | PREFIX_VEX_0F3834, | |
1283 | PREFIX_VEX_0F3835, | |
6c30d220 | 1284 | PREFIX_VEX_0F3836, |
592a252b L |
1285 | PREFIX_VEX_0F3837, |
1286 | PREFIX_VEX_0F3838, | |
1287 | PREFIX_VEX_0F3839, | |
1288 | PREFIX_VEX_0F383A, | |
1289 | PREFIX_VEX_0F383B, | |
1290 | PREFIX_VEX_0F383C, | |
1291 | PREFIX_VEX_0F383D, | |
1292 | PREFIX_VEX_0F383E, | |
1293 | PREFIX_VEX_0F383F, | |
1294 | PREFIX_VEX_0F3840, | |
1295 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1296 | PREFIX_VEX_0F3845, |
1297 | PREFIX_VEX_0F3846, | |
1298 | PREFIX_VEX_0F3847, | |
1299 | PREFIX_VEX_0F3858, | |
1300 | PREFIX_VEX_0F3859, | |
1301 | PREFIX_VEX_0F385A, | |
1302 | PREFIX_VEX_0F3878, | |
1303 | PREFIX_VEX_0F3879, | |
1304 | PREFIX_VEX_0F388C, | |
1305 | PREFIX_VEX_0F388E, | |
1306 | PREFIX_VEX_0F3890, | |
1307 | PREFIX_VEX_0F3891, | |
1308 | PREFIX_VEX_0F3892, | |
1309 | PREFIX_VEX_0F3893, | |
592a252b L |
1310 | PREFIX_VEX_0F3896, |
1311 | PREFIX_VEX_0F3897, | |
1312 | PREFIX_VEX_0F3898, | |
1313 | PREFIX_VEX_0F3899, | |
1314 | PREFIX_VEX_0F389A, | |
1315 | PREFIX_VEX_0F389B, | |
1316 | PREFIX_VEX_0F389C, | |
1317 | PREFIX_VEX_0F389D, | |
1318 | PREFIX_VEX_0F389E, | |
1319 | PREFIX_VEX_0F389F, | |
1320 | PREFIX_VEX_0F38A6, | |
1321 | PREFIX_VEX_0F38A7, | |
1322 | PREFIX_VEX_0F38A8, | |
1323 | PREFIX_VEX_0F38A9, | |
1324 | PREFIX_VEX_0F38AA, | |
1325 | PREFIX_VEX_0F38AB, | |
1326 | PREFIX_VEX_0F38AC, | |
1327 | PREFIX_VEX_0F38AD, | |
1328 | PREFIX_VEX_0F38AE, | |
1329 | PREFIX_VEX_0F38AF, | |
1330 | PREFIX_VEX_0F38B6, | |
1331 | PREFIX_VEX_0F38B7, | |
1332 | PREFIX_VEX_0F38B8, | |
1333 | PREFIX_VEX_0F38B9, | |
1334 | PREFIX_VEX_0F38BA, | |
1335 | PREFIX_VEX_0F38BB, | |
1336 | PREFIX_VEX_0F38BC, | |
1337 | PREFIX_VEX_0F38BD, | |
1338 | PREFIX_VEX_0F38BE, | |
1339 | PREFIX_VEX_0F38BF, | |
48521003 | 1340 | PREFIX_VEX_0F38CF, |
592a252b L |
1341 | PREFIX_VEX_0F38DB, |
1342 | PREFIX_VEX_0F38DC, | |
1343 | PREFIX_VEX_0F38DD, | |
1344 | PREFIX_VEX_0F38DE, | |
1345 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1346 | PREFIX_VEX_0F38F2, |
1347 | PREFIX_VEX_0F38F3_REG_1, | |
1348 | PREFIX_VEX_0F38F3_REG_2, | |
1349 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1350 | PREFIX_VEX_0F38F5, |
1351 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1352 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1353 | PREFIX_VEX_0F3A00, |
1354 | PREFIX_VEX_0F3A01, | |
1355 | PREFIX_VEX_0F3A02, | |
592a252b L |
1356 | PREFIX_VEX_0F3A04, |
1357 | PREFIX_VEX_0F3A05, | |
1358 | PREFIX_VEX_0F3A06, | |
1359 | PREFIX_VEX_0F3A08, | |
1360 | PREFIX_VEX_0F3A09, | |
1361 | PREFIX_VEX_0F3A0A, | |
1362 | PREFIX_VEX_0F3A0B, | |
1363 | PREFIX_VEX_0F3A0C, | |
1364 | PREFIX_VEX_0F3A0D, | |
1365 | PREFIX_VEX_0F3A0E, | |
1366 | PREFIX_VEX_0F3A0F, | |
1367 | PREFIX_VEX_0F3A14, | |
1368 | PREFIX_VEX_0F3A15, | |
1369 | PREFIX_VEX_0F3A16, | |
1370 | PREFIX_VEX_0F3A17, | |
1371 | PREFIX_VEX_0F3A18, | |
1372 | PREFIX_VEX_0F3A19, | |
1373 | PREFIX_VEX_0F3A1D, | |
1374 | PREFIX_VEX_0F3A20, | |
1375 | PREFIX_VEX_0F3A21, | |
1376 | PREFIX_VEX_0F3A22, | |
43234a1e | 1377 | PREFIX_VEX_0F3A30, |
1ba585e8 | 1378 | PREFIX_VEX_0F3A31, |
43234a1e | 1379 | PREFIX_VEX_0F3A32, |
1ba585e8 | 1380 | PREFIX_VEX_0F3A33, |
6c30d220 L |
1381 | PREFIX_VEX_0F3A38, |
1382 | PREFIX_VEX_0F3A39, | |
592a252b L |
1383 | PREFIX_VEX_0F3A40, |
1384 | PREFIX_VEX_0F3A41, | |
1385 | PREFIX_VEX_0F3A42, | |
1386 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1387 | PREFIX_VEX_0F3A46, |
592a252b L |
1388 | PREFIX_VEX_0F3A48, |
1389 | PREFIX_VEX_0F3A49, | |
1390 | PREFIX_VEX_0F3A4A, | |
1391 | PREFIX_VEX_0F3A4B, | |
1392 | PREFIX_VEX_0F3A4C, | |
1393 | PREFIX_VEX_0F3A5C, | |
1394 | PREFIX_VEX_0F3A5D, | |
1395 | PREFIX_VEX_0F3A5E, | |
1396 | PREFIX_VEX_0F3A5F, | |
1397 | PREFIX_VEX_0F3A60, | |
1398 | PREFIX_VEX_0F3A61, | |
1399 | PREFIX_VEX_0F3A62, | |
1400 | PREFIX_VEX_0F3A63, | |
1401 | PREFIX_VEX_0F3A68, | |
1402 | PREFIX_VEX_0F3A69, | |
1403 | PREFIX_VEX_0F3A6A, | |
1404 | PREFIX_VEX_0F3A6B, | |
1405 | PREFIX_VEX_0F3A6C, | |
1406 | PREFIX_VEX_0F3A6D, | |
1407 | PREFIX_VEX_0F3A6E, | |
1408 | PREFIX_VEX_0F3A6F, | |
1409 | PREFIX_VEX_0F3A78, | |
1410 | PREFIX_VEX_0F3A79, | |
1411 | PREFIX_VEX_0F3A7A, | |
1412 | PREFIX_VEX_0F3A7B, | |
1413 | PREFIX_VEX_0F3A7C, | |
1414 | PREFIX_VEX_0F3A7D, | |
1415 | PREFIX_VEX_0F3A7E, | |
1416 | PREFIX_VEX_0F3A7F, | |
48521003 IT |
1417 | PREFIX_VEX_0F3ACE, |
1418 | PREFIX_VEX_0F3ACF, | |
6c30d220 | 1419 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1420 | PREFIX_VEX_0F3AF0, |
1421 | ||
1422 | PREFIX_EVEX_0F10, | |
1423 | PREFIX_EVEX_0F11, | |
1424 | PREFIX_EVEX_0F12, | |
43234a1e | 1425 | PREFIX_EVEX_0F16, |
43234a1e | 1426 | PREFIX_EVEX_0F2A, |
43234a1e L |
1427 | PREFIX_EVEX_0F2C, |
1428 | PREFIX_EVEX_0F2D, | |
1429 | PREFIX_EVEX_0F2E, | |
1430 | PREFIX_EVEX_0F2F, | |
1431 | PREFIX_EVEX_0F51, | |
1432 | PREFIX_EVEX_0F58, | |
1433 | PREFIX_EVEX_0F59, | |
1434 | PREFIX_EVEX_0F5A, | |
1435 | PREFIX_EVEX_0F5B, | |
1436 | PREFIX_EVEX_0F5C, | |
1437 | PREFIX_EVEX_0F5D, | |
1438 | PREFIX_EVEX_0F5E, | |
1439 | PREFIX_EVEX_0F5F, | |
1ba585e8 IT |
1440 | PREFIX_EVEX_0F60, |
1441 | PREFIX_EVEX_0F61, | |
43234a1e | 1442 | PREFIX_EVEX_0F62, |
1ba585e8 IT |
1443 | PREFIX_EVEX_0F63, |
1444 | PREFIX_EVEX_0F64, | |
1445 | PREFIX_EVEX_0F65, | |
43234a1e | 1446 | PREFIX_EVEX_0F66, |
1ba585e8 IT |
1447 | PREFIX_EVEX_0F67, |
1448 | PREFIX_EVEX_0F68, | |
1449 | PREFIX_EVEX_0F69, | |
43234a1e | 1450 | PREFIX_EVEX_0F6A, |
1ba585e8 | 1451 | PREFIX_EVEX_0F6B, |
43234a1e L |
1452 | PREFIX_EVEX_0F6C, |
1453 | PREFIX_EVEX_0F6D, | |
1454 | PREFIX_EVEX_0F6E, | |
1455 | PREFIX_EVEX_0F6F, | |
1456 | PREFIX_EVEX_0F70, | |
1ba585e8 IT |
1457 | PREFIX_EVEX_0F71_REG_2, |
1458 | PREFIX_EVEX_0F71_REG_4, | |
1459 | PREFIX_EVEX_0F71_REG_6, | |
43234a1e L |
1460 | PREFIX_EVEX_0F72_REG_0, |
1461 | PREFIX_EVEX_0F72_REG_1, | |
1462 | PREFIX_EVEX_0F72_REG_2, | |
1463 | PREFIX_EVEX_0F72_REG_4, | |
1464 | PREFIX_EVEX_0F72_REG_6, | |
1465 | PREFIX_EVEX_0F73_REG_2, | |
1ba585e8 | 1466 | PREFIX_EVEX_0F73_REG_3, |
43234a1e | 1467 | PREFIX_EVEX_0F73_REG_6, |
1ba585e8 IT |
1468 | PREFIX_EVEX_0F73_REG_7, |
1469 | PREFIX_EVEX_0F74, | |
1470 | PREFIX_EVEX_0F75, | |
43234a1e L |
1471 | PREFIX_EVEX_0F76, |
1472 | PREFIX_EVEX_0F78, | |
1473 | PREFIX_EVEX_0F79, | |
1474 | PREFIX_EVEX_0F7A, | |
1475 | PREFIX_EVEX_0F7B, | |
1476 | PREFIX_EVEX_0F7E, | |
1477 | PREFIX_EVEX_0F7F, | |
1478 | PREFIX_EVEX_0FC2, | |
1ba585e8 IT |
1479 | PREFIX_EVEX_0FC4, |
1480 | PREFIX_EVEX_0FC5, | |
1ba585e8 | 1481 | PREFIX_EVEX_0FD1, |
43234a1e L |
1482 | PREFIX_EVEX_0FD2, |
1483 | PREFIX_EVEX_0FD3, | |
1484 | PREFIX_EVEX_0FD4, | |
1ba585e8 | 1485 | PREFIX_EVEX_0FD5, |
43234a1e | 1486 | PREFIX_EVEX_0FD6, |
1ba585e8 IT |
1487 | PREFIX_EVEX_0FD8, |
1488 | PREFIX_EVEX_0FD9, | |
1489 | PREFIX_EVEX_0FDA, | |
43234a1e | 1490 | PREFIX_EVEX_0FDB, |
1ba585e8 IT |
1491 | PREFIX_EVEX_0FDC, |
1492 | PREFIX_EVEX_0FDD, | |
1493 | PREFIX_EVEX_0FDE, | |
43234a1e | 1494 | PREFIX_EVEX_0FDF, |
1ba585e8 IT |
1495 | PREFIX_EVEX_0FE0, |
1496 | PREFIX_EVEX_0FE1, | |
43234a1e | 1497 | PREFIX_EVEX_0FE2, |
1ba585e8 IT |
1498 | PREFIX_EVEX_0FE3, |
1499 | PREFIX_EVEX_0FE4, | |
1500 | PREFIX_EVEX_0FE5, | |
43234a1e L |
1501 | PREFIX_EVEX_0FE6, |
1502 | PREFIX_EVEX_0FE7, | |
1ba585e8 IT |
1503 | PREFIX_EVEX_0FE8, |
1504 | PREFIX_EVEX_0FE9, | |
1505 | PREFIX_EVEX_0FEA, | |
43234a1e | 1506 | PREFIX_EVEX_0FEB, |
1ba585e8 IT |
1507 | PREFIX_EVEX_0FEC, |
1508 | PREFIX_EVEX_0FED, | |
1509 | PREFIX_EVEX_0FEE, | |
43234a1e | 1510 | PREFIX_EVEX_0FEF, |
1ba585e8 | 1511 | PREFIX_EVEX_0FF1, |
43234a1e L |
1512 | PREFIX_EVEX_0FF2, |
1513 | PREFIX_EVEX_0FF3, | |
1514 | PREFIX_EVEX_0FF4, | |
1ba585e8 IT |
1515 | PREFIX_EVEX_0FF5, |
1516 | PREFIX_EVEX_0FF6, | |
1517 | PREFIX_EVEX_0FF8, | |
1518 | PREFIX_EVEX_0FF9, | |
43234a1e L |
1519 | PREFIX_EVEX_0FFA, |
1520 | PREFIX_EVEX_0FFB, | |
1ba585e8 IT |
1521 | PREFIX_EVEX_0FFC, |
1522 | PREFIX_EVEX_0FFD, | |
43234a1e | 1523 | PREFIX_EVEX_0FFE, |
1ba585e8 IT |
1524 | PREFIX_EVEX_0F3800, |
1525 | PREFIX_EVEX_0F3804, | |
1526 | PREFIX_EVEX_0F380B, | |
43234a1e L |
1527 | PREFIX_EVEX_0F380C, |
1528 | PREFIX_EVEX_0F380D, | |
1ba585e8 | 1529 | PREFIX_EVEX_0F3810, |
43234a1e L |
1530 | PREFIX_EVEX_0F3811, |
1531 | PREFIX_EVEX_0F3812, | |
1532 | PREFIX_EVEX_0F3813, | |
1533 | PREFIX_EVEX_0F3814, | |
1534 | PREFIX_EVEX_0F3815, | |
1535 | PREFIX_EVEX_0F3816, | |
1536 | PREFIX_EVEX_0F3818, | |
1537 | PREFIX_EVEX_0F3819, | |
1538 | PREFIX_EVEX_0F381A, | |
1539 | PREFIX_EVEX_0F381B, | |
1ba585e8 IT |
1540 | PREFIX_EVEX_0F381C, |
1541 | PREFIX_EVEX_0F381D, | |
43234a1e L |
1542 | PREFIX_EVEX_0F381E, |
1543 | PREFIX_EVEX_0F381F, | |
1ba585e8 | 1544 | PREFIX_EVEX_0F3820, |
43234a1e L |
1545 | PREFIX_EVEX_0F3821, |
1546 | PREFIX_EVEX_0F3822, | |
1547 | PREFIX_EVEX_0F3823, | |
1548 | PREFIX_EVEX_0F3824, | |
1549 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1550 | PREFIX_EVEX_0F3826, |
43234a1e L |
1551 | PREFIX_EVEX_0F3827, |
1552 | PREFIX_EVEX_0F3828, | |
1553 | PREFIX_EVEX_0F3829, | |
1554 | PREFIX_EVEX_0F382A, | |
1ba585e8 | 1555 | PREFIX_EVEX_0F382B, |
43234a1e L |
1556 | PREFIX_EVEX_0F382C, |
1557 | PREFIX_EVEX_0F382D, | |
1ba585e8 | 1558 | PREFIX_EVEX_0F3830, |
43234a1e L |
1559 | PREFIX_EVEX_0F3831, |
1560 | PREFIX_EVEX_0F3832, | |
1561 | PREFIX_EVEX_0F3833, | |
1562 | PREFIX_EVEX_0F3834, | |
1563 | PREFIX_EVEX_0F3835, | |
1564 | PREFIX_EVEX_0F3836, | |
1565 | PREFIX_EVEX_0F3837, | |
1ba585e8 | 1566 | PREFIX_EVEX_0F3838, |
43234a1e L |
1567 | PREFIX_EVEX_0F3839, |
1568 | PREFIX_EVEX_0F383A, | |
1569 | PREFIX_EVEX_0F383B, | |
1ba585e8 | 1570 | PREFIX_EVEX_0F383C, |
43234a1e | 1571 | PREFIX_EVEX_0F383D, |
1ba585e8 | 1572 | PREFIX_EVEX_0F383E, |
43234a1e L |
1573 | PREFIX_EVEX_0F383F, |
1574 | PREFIX_EVEX_0F3840, | |
1575 | PREFIX_EVEX_0F3842, | |
1576 | PREFIX_EVEX_0F3843, | |
1577 | PREFIX_EVEX_0F3844, | |
1578 | PREFIX_EVEX_0F3845, | |
1579 | PREFIX_EVEX_0F3846, | |
1580 | PREFIX_EVEX_0F3847, | |
1581 | PREFIX_EVEX_0F384C, | |
1582 | PREFIX_EVEX_0F384D, | |
1583 | PREFIX_EVEX_0F384E, | |
1584 | PREFIX_EVEX_0F384F, | |
8cfcb765 IT |
1585 | PREFIX_EVEX_0F3850, |
1586 | PREFIX_EVEX_0F3851, | |
47acf0bd IT |
1587 | PREFIX_EVEX_0F3852, |
1588 | PREFIX_EVEX_0F3853, | |
ee6872be | 1589 | PREFIX_EVEX_0F3854, |
620214f7 | 1590 | PREFIX_EVEX_0F3855, |
43234a1e L |
1591 | PREFIX_EVEX_0F3858, |
1592 | PREFIX_EVEX_0F3859, | |
1593 | PREFIX_EVEX_0F385A, | |
1594 | PREFIX_EVEX_0F385B, | |
53467f57 IT |
1595 | PREFIX_EVEX_0F3862, |
1596 | PREFIX_EVEX_0F3863, | |
43234a1e L |
1597 | PREFIX_EVEX_0F3864, |
1598 | PREFIX_EVEX_0F3865, | |
1ba585e8 | 1599 | PREFIX_EVEX_0F3866, |
9186c494 | 1600 | PREFIX_EVEX_0F3868, |
53467f57 IT |
1601 | PREFIX_EVEX_0F3870, |
1602 | PREFIX_EVEX_0F3871, | |
1603 | PREFIX_EVEX_0F3872, | |
1604 | PREFIX_EVEX_0F3873, | |
1ba585e8 | 1605 | PREFIX_EVEX_0F3875, |
43234a1e L |
1606 | PREFIX_EVEX_0F3876, |
1607 | PREFIX_EVEX_0F3877, | |
1ba585e8 IT |
1608 | PREFIX_EVEX_0F3878, |
1609 | PREFIX_EVEX_0F3879, | |
1610 | PREFIX_EVEX_0F387A, | |
1611 | PREFIX_EVEX_0F387B, | |
43234a1e | 1612 | PREFIX_EVEX_0F387C, |
1ba585e8 | 1613 | PREFIX_EVEX_0F387D, |
43234a1e L |
1614 | PREFIX_EVEX_0F387E, |
1615 | PREFIX_EVEX_0F387F, | |
14f195c9 | 1616 | PREFIX_EVEX_0F3883, |
43234a1e L |
1617 | PREFIX_EVEX_0F3888, |
1618 | PREFIX_EVEX_0F3889, | |
1619 | PREFIX_EVEX_0F388A, | |
1620 | PREFIX_EVEX_0F388B, | |
1ba585e8 | 1621 | PREFIX_EVEX_0F388D, |
ee6872be | 1622 | PREFIX_EVEX_0F388F, |
43234a1e L |
1623 | PREFIX_EVEX_0F3890, |
1624 | PREFIX_EVEX_0F3891, | |
1625 | PREFIX_EVEX_0F3892, | |
1626 | PREFIX_EVEX_0F3893, | |
1627 | PREFIX_EVEX_0F3896, | |
1628 | PREFIX_EVEX_0F3897, | |
1629 | PREFIX_EVEX_0F3898, | |
1630 | PREFIX_EVEX_0F3899, | |
1631 | PREFIX_EVEX_0F389A, | |
1632 | PREFIX_EVEX_0F389B, | |
1633 | PREFIX_EVEX_0F389C, | |
1634 | PREFIX_EVEX_0F389D, | |
1635 | PREFIX_EVEX_0F389E, | |
1636 | PREFIX_EVEX_0F389F, | |
1637 | PREFIX_EVEX_0F38A0, | |
1638 | PREFIX_EVEX_0F38A1, | |
1639 | PREFIX_EVEX_0F38A2, | |
1640 | PREFIX_EVEX_0F38A3, | |
1641 | PREFIX_EVEX_0F38A6, | |
1642 | PREFIX_EVEX_0F38A7, | |
1643 | PREFIX_EVEX_0F38A8, | |
1644 | PREFIX_EVEX_0F38A9, | |
1645 | PREFIX_EVEX_0F38AA, | |
1646 | PREFIX_EVEX_0F38AB, | |
1647 | PREFIX_EVEX_0F38AC, | |
1648 | PREFIX_EVEX_0F38AD, | |
1649 | PREFIX_EVEX_0F38AE, | |
1650 | PREFIX_EVEX_0F38AF, | |
2cc1b5aa IT |
1651 | PREFIX_EVEX_0F38B4, |
1652 | PREFIX_EVEX_0F38B5, | |
43234a1e L |
1653 | PREFIX_EVEX_0F38B6, |
1654 | PREFIX_EVEX_0F38B7, | |
1655 | PREFIX_EVEX_0F38B8, | |
1656 | PREFIX_EVEX_0F38B9, | |
1657 | PREFIX_EVEX_0F38BA, | |
1658 | PREFIX_EVEX_0F38BB, | |
1659 | PREFIX_EVEX_0F38BC, | |
1660 | PREFIX_EVEX_0F38BD, | |
1661 | PREFIX_EVEX_0F38BE, | |
1662 | PREFIX_EVEX_0F38BF, | |
1663 | PREFIX_EVEX_0F38C4, | |
1664 | PREFIX_EVEX_0F38C6_REG_1, | |
1665 | PREFIX_EVEX_0F38C6_REG_2, | |
1666 | PREFIX_EVEX_0F38C6_REG_5, | |
1667 | PREFIX_EVEX_0F38C6_REG_6, | |
1668 | PREFIX_EVEX_0F38C7_REG_1, | |
1669 | PREFIX_EVEX_0F38C7_REG_2, | |
1670 | PREFIX_EVEX_0F38C7_REG_5, | |
1671 | PREFIX_EVEX_0F38C7_REG_6, | |
1672 | PREFIX_EVEX_0F38C8, | |
1673 | PREFIX_EVEX_0F38CA, | |
1674 | PREFIX_EVEX_0F38CB, | |
1675 | PREFIX_EVEX_0F38CC, | |
1676 | PREFIX_EVEX_0F38CD, | |
48521003 | 1677 | PREFIX_EVEX_0F38CF, |
8dcf1fad IT |
1678 | PREFIX_EVEX_0F38DC, |
1679 | PREFIX_EVEX_0F38DD, | |
1680 | PREFIX_EVEX_0F38DE, | |
1681 | PREFIX_EVEX_0F38DF, | |
43234a1e L |
1682 | |
1683 | PREFIX_EVEX_0F3A00, | |
1684 | PREFIX_EVEX_0F3A01, | |
1685 | PREFIX_EVEX_0F3A03, | |
1686 | PREFIX_EVEX_0F3A04, | |
1687 | PREFIX_EVEX_0F3A05, | |
1688 | PREFIX_EVEX_0F3A08, | |
1689 | PREFIX_EVEX_0F3A09, | |
1690 | PREFIX_EVEX_0F3A0A, | |
1691 | PREFIX_EVEX_0F3A0B, | |
1ba585e8 IT |
1692 | PREFIX_EVEX_0F3A0F, |
1693 | PREFIX_EVEX_0F3A14, | |
1694 | PREFIX_EVEX_0F3A15, | |
90a915bf | 1695 | PREFIX_EVEX_0F3A16, |
43234a1e L |
1696 | PREFIX_EVEX_0F3A17, |
1697 | PREFIX_EVEX_0F3A18, | |
1698 | PREFIX_EVEX_0F3A19, | |
1699 | PREFIX_EVEX_0F3A1A, | |
1700 | PREFIX_EVEX_0F3A1B, | |
1701 | PREFIX_EVEX_0F3A1D, | |
1702 | PREFIX_EVEX_0F3A1E, | |
1703 | PREFIX_EVEX_0F3A1F, | |
1ba585e8 | 1704 | PREFIX_EVEX_0F3A20, |
43234a1e | 1705 | PREFIX_EVEX_0F3A21, |
90a915bf | 1706 | PREFIX_EVEX_0F3A22, |
43234a1e L |
1707 | PREFIX_EVEX_0F3A23, |
1708 | PREFIX_EVEX_0F3A25, | |
1709 | PREFIX_EVEX_0F3A26, | |
1710 | PREFIX_EVEX_0F3A27, | |
1711 | PREFIX_EVEX_0F3A38, | |
1712 | PREFIX_EVEX_0F3A39, | |
1713 | PREFIX_EVEX_0F3A3A, | |
1714 | PREFIX_EVEX_0F3A3B, | |
1ba585e8 IT |
1715 | PREFIX_EVEX_0F3A3E, |
1716 | PREFIX_EVEX_0F3A3F, | |
1717 | PREFIX_EVEX_0F3A42, | |
43234a1e | 1718 | PREFIX_EVEX_0F3A43, |
ff1982d5 | 1719 | PREFIX_EVEX_0F3A44, |
90a915bf IT |
1720 | PREFIX_EVEX_0F3A50, |
1721 | PREFIX_EVEX_0F3A51, | |
43234a1e | 1722 | PREFIX_EVEX_0F3A54, |
90a915bf IT |
1723 | PREFIX_EVEX_0F3A55, |
1724 | PREFIX_EVEX_0F3A56, | |
1725 | PREFIX_EVEX_0F3A57, | |
1726 | PREFIX_EVEX_0F3A66, | |
53467f57 IT |
1727 | PREFIX_EVEX_0F3A67, |
1728 | PREFIX_EVEX_0F3A70, | |
1729 | PREFIX_EVEX_0F3A71, | |
1730 | PREFIX_EVEX_0F3A72, | |
48521003 IT |
1731 | PREFIX_EVEX_0F3A73, |
1732 | PREFIX_EVEX_0F3ACE, | |
1733 | PREFIX_EVEX_0F3ACF | |
51e7da1b | 1734 | }; |
4e7d34a6 | 1735 | |
51e7da1b L |
1736 | enum |
1737 | { | |
1738 | X86_64_06 = 0, | |
3873ba12 | 1739 | X86_64_07, |
1673df32 | 1740 | X86_64_0E, |
3873ba12 L |
1741 | X86_64_16, |
1742 | X86_64_17, | |
1743 | X86_64_1E, | |
1744 | X86_64_1F, | |
1745 | X86_64_27, | |
1746 | X86_64_2F, | |
1747 | X86_64_37, | |
1748 | X86_64_3F, | |
1749 | X86_64_60, | |
1750 | X86_64_61, | |
1751 | X86_64_62, | |
1752 | X86_64_63, | |
1753 | X86_64_6D, | |
1754 | X86_64_6F, | |
d039fef3 | 1755 | X86_64_82, |
3873ba12 | 1756 | X86_64_9A, |
aeab2b26 JB |
1757 | X86_64_C2, |
1758 | X86_64_C3, | |
3873ba12 L |
1759 | X86_64_C4, |
1760 | X86_64_C5, | |
1761 | X86_64_CE, | |
1762 | X86_64_D4, | |
1763 | X86_64_D5, | |
a72d2af2 L |
1764 | X86_64_E8, |
1765 | X86_64_E9, | |
3873ba12 L |
1766 | X86_64_EA, |
1767 | X86_64_0F01_REG_0, | |
1768 | X86_64_0F01_REG_1, | |
1769 | X86_64_0F01_REG_2, | |
1770 | X86_64_0F01_REG_3 | |
51e7da1b | 1771 | }; |
4e7d34a6 | 1772 | |
51e7da1b L |
1773 | enum |
1774 | { | |
1775 | THREE_BYTE_0F38 = 0, | |
1f334aeb | 1776 | THREE_BYTE_0F3A |
51e7da1b | 1777 | }; |
4e7d34a6 | 1778 | |
f88c9eb0 SP |
1779 | enum |
1780 | { | |
5dd85c99 SP |
1781 | XOP_08 = 0, |
1782 | XOP_09, | |
f88c9eb0 SP |
1783 | XOP_0A |
1784 | }; | |
1785 | ||
51e7da1b L |
1786 | enum |
1787 | { | |
1788 | VEX_0F = 0, | |
3873ba12 L |
1789 | VEX_0F38, |
1790 | VEX_0F3A | |
51e7da1b | 1791 | }; |
c0f3af97 | 1792 | |
43234a1e L |
1793 | enum |
1794 | { | |
1795 | EVEX_0F = 0, | |
1796 | EVEX_0F38, | |
1797 | EVEX_0F3A | |
1798 | }; | |
1799 | ||
51e7da1b L |
1800 | enum |
1801 | { | |
ec6f095a | 1802 | VEX_LEN_0F12_P_0_M_0 = 0, |
592a252b | 1803 | VEX_LEN_0F12_P_0_M_1, |
18897deb | 1804 | #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0 |
592a252b L |
1805 | VEX_LEN_0F13_M_0, |
1806 | VEX_LEN_0F16_P_0_M_0, | |
1807 | VEX_LEN_0F16_P_0_M_1, | |
18897deb | 1808 | #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0 |
592a252b | 1809 | VEX_LEN_0F17_M_0, |
43234a1e | 1810 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1811 | VEX_LEN_0F41_P_2, |
43234a1e | 1812 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1813 | VEX_LEN_0F42_P_2, |
43234a1e | 1814 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1815 | VEX_LEN_0F44_P_2, |
43234a1e | 1816 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1817 | VEX_LEN_0F45_P_2, |
43234a1e | 1818 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1819 | VEX_LEN_0F46_P_2, |
43234a1e | 1820 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1821 | VEX_LEN_0F47_P_2, |
1822 | VEX_LEN_0F4A_P_0, | |
1823 | VEX_LEN_0F4A_P_2, | |
1824 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1825 | VEX_LEN_0F4B_P_2, |
592a252b | 1826 | VEX_LEN_0F6E_P_2, |
ec6f095a | 1827 | VEX_LEN_0F77_P_0, |
592a252b L |
1828 | VEX_LEN_0F7E_P_1, |
1829 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1830 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1831 | VEX_LEN_0F90_P_2, |
43234a1e | 1832 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1833 | VEX_LEN_0F91_P_2, |
43234a1e | 1834 | VEX_LEN_0F92_P_0, |
90a915bf | 1835 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1836 | VEX_LEN_0F92_P_3, |
43234a1e | 1837 | VEX_LEN_0F93_P_0, |
90a915bf | 1838 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1839 | VEX_LEN_0F93_P_3, |
43234a1e | 1840 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1841 | VEX_LEN_0F98_P_2, |
1842 | VEX_LEN_0F99_P_0, | |
1843 | VEX_LEN_0F99_P_2, | |
592a252b L |
1844 | VEX_LEN_0FAE_R_2_M_0, |
1845 | VEX_LEN_0FAE_R_3_M_0, | |
592a252b L |
1846 | VEX_LEN_0FC4_P_2, |
1847 | VEX_LEN_0FC5_P_2, | |
592a252b | 1848 | VEX_LEN_0FD6_P_2, |
592a252b | 1849 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1850 | VEX_LEN_0F3816_P_2, |
1851 | VEX_LEN_0F3819_P_2, | |
592a252b | 1852 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1853 | VEX_LEN_0F3836_P_2, |
592a252b | 1854 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1855 | VEX_LEN_0F385A_P_2_M_0, |
592a252b | 1856 | VEX_LEN_0F38DB_P_2, |
f12dc422 L |
1857 | VEX_LEN_0F38F2_P_0, |
1858 | VEX_LEN_0F38F3_R_1_P_0, | |
1859 | VEX_LEN_0F38F3_R_2_P_0, | |
1860 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1861 | VEX_LEN_0F38F5_P_0, |
1862 | VEX_LEN_0F38F5_P_1, | |
1863 | VEX_LEN_0F38F5_P_3, | |
1864 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1865 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1866 | VEX_LEN_0F38F7_P_1, |
1867 | VEX_LEN_0F38F7_P_2, | |
1868 | VEX_LEN_0F38F7_P_3, | |
1869 | VEX_LEN_0F3A00_P_2, | |
1870 | VEX_LEN_0F3A01_P_2, | |
592a252b | 1871 | VEX_LEN_0F3A06_P_2, |
592a252b L |
1872 | VEX_LEN_0F3A14_P_2, |
1873 | VEX_LEN_0F3A15_P_2, | |
1874 | VEX_LEN_0F3A16_P_2, | |
1875 | VEX_LEN_0F3A17_P_2, | |
1876 | VEX_LEN_0F3A18_P_2, | |
1877 | VEX_LEN_0F3A19_P_2, | |
1878 | VEX_LEN_0F3A20_P_2, | |
1879 | VEX_LEN_0F3A21_P_2, | |
1880 | VEX_LEN_0F3A22_P_2, | |
43234a1e | 1881 | VEX_LEN_0F3A30_P_2, |
1ba585e8 | 1882 | VEX_LEN_0F3A31_P_2, |
43234a1e | 1883 | VEX_LEN_0F3A32_P_2, |
1ba585e8 | 1884 | VEX_LEN_0F3A33_P_2, |
6c30d220 L |
1885 | VEX_LEN_0F3A38_P_2, |
1886 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1887 | VEX_LEN_0F3A41_P_2, |
6c30d220 | 1888 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1889 | VEX_LEN_0F3A60_P_2, |
1890 | VEX_LEN_0F3A61_P_2, | |
1891 | VEX_LEN_0F3A62_P_2, | |
1892 | VEX_LEN_0F3A63_P_2, | |
1893 | VEX_LEN_0F3A6A_P_2, | |
1894 | VEX_LEN_0F3A6B_P_2, | |
1895 | VEX_LEN_0F3A6E_P_2, | |
1896 | VEX_LEN_0F3A6F_P_2, | |
1897 | VEX_LEN_0F3A7A_P_2, | |
1898 | VEX_LEN_0F3A7B_P_2, | |
1899 | VEX_LEN_0F3A7E_P_2, | |
1900 | VEX_LEN_0F3A7F_P_2, | |
1901 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1902 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1903 | VEX_LEN_0FXOP_08_CC, |
1904 | VEX_LEN_0FXOP_08_CD, | |
1905 | VEX_LEN_0FXOP_08_CE, | |
1906 | VEX_LEN_0FXOP_08_CF, | |
1907 | VEX_LEN_0FXOP_08_EC, | |
1908 | VEX_LEN_0FXOP_08_ED, | |
1909 | VEX_LEN_0FXOP_08_EE, | |
1910 | VEX_LEN_0FXOP_08_EF, | |
592a252b L |
1911 | VEX_LEN_0FXOP_09_80, |
1912 | VEX_LEN_0FXOP_09_81 | |
51e7da1b | 1913 | }; |
c0f3af97 | 1914 | |
04e2a182 L |
1915 | enum |
1916 | { | |
1917 | EVEX_LEN_0F6E_P_2 = 0, | |
1918 | EVEX_LEN_0F7E_P_1, | |
1919 | EVEX_LEN_0F7E_P_2, | |
12efd68d | 1920 | EVEX_LEN_0FD6_P_2, |
f0a6222e L |
1921 | EVEX_LEN_0F3819_P_2_W_0, |
1922 | EVEX_LEN_0F3819_P_2_W_1, | |
1923 | EVEX_LEN_0F381A_P_2_W_0, | |
1924 | EVEX_LEN_0F381A_P_2_W_1, | |
1925 | EVEX_LEN_0F381B_P_2_W_0, | |
1926 | EVEX_LEN_0F381B_P_2_W_1, | |
1927 | EVEX_LEN_0F385A_P_2_W_0, | |
1928 | EVEX_LEN_0F385A_P_2_W_1, | |
1929 | EVEX_LEN_0F385B_P_2_W_0, | |
1930 | EVEX_LEN_0F385B_P_2_W_1, | |
e395f487 L |
1931 | EVEX_LEN_0F38C6_REG_1_PREFIX_2, |
1932 | EVEX_LEN_0F38C6_REG_2_PREFIX_2, | |
1933 | EVEX_LEN_0F38C6_REG_5_PREFIX_2, | |
1934 | EVEX_LEN_0F38C6_REG_6_PREFIX_2, | |
1935 | EVEX_LEN_0F38C7_R_1_P_2_W_0, | |
1936 | EVEX_LEN_0F38C7_R_1_P_2_W_1, | |
1937 | EVEX_LEN_0F38C7_R_2_P_2_W_0, | |
1938 | EVEX_LEN_0F38C7_R_2_P_2_W_1, | |
1939 | EVEX_LEN_0F38C7_R_5_P_2_W_0, | |
1940 | EVEX_LEN_0F38C7_R_5_P_2_W_1, | |
1941 | EVEX_LEN_0F38C7_R_6_P_2_W_0, | |
1942 | EVEX_LEN_0F38C7_R_6_P_2_W_1, | |
12efd68d L |
1943 | EVEX_LEN_0F3A18_P_2_W_0, |
1944 | EVEX_LEN_0F3A18_P_2_W_1, | |
1945 | EVEX_LEN_0F3A19_P_2_W_0, | |
1946 | EVEX_LEN_0F3A19_P_2_W_1, | |
1947 | EVEX_LEN_0F3A1A_P_2_W_0, | |
1948 | EVEX_LEN_0F3A1A_P_2_W_1, | |
1949 | EVEX_LEN_0F3A1B_P_2_W_0, | |
6e1c90b7 L |
1950 | EVEX_LEN_0F3A1B_P_2_W_1, |
1951 | EVEX_LEN_0F3A23_P_2_W_0, | |
1952 | EVEX_LEN_0F3A23_P_2_W_1, | |
1953 | EVEX_LEN_0F3A38_P_2_W_0, | |
1954 | EVEX_LEN_0F3A38_P_2_W_1, | |
1955 | EVEX_LEN_0F3A39_P_2_W_0, | |
1956 | EVEX_LEN_0F3A39_P_2_W_1, | |
1957 | EVEX_LEN_0F3A3A_P_2_W_0, | |
1958 | EVEX_LEN_0F3A3A_P_2_W_1, | |
1959 | EVEX_LEN_0F3A3B_P_2_W_0, | |
1960 | EVEX_LEN_0F3A3B_P_2_W_1, | |
1961 | EVEX_LEN_0F3A43_P_2_W_0, | |
1962 | EVEX_LEN_0F3A43_P_2_W_1 | |
04e2a182 L |
1963 | }; |
1964 | ||
9e30b8e0 L |
1965 | enum |
1966 | { | |
ec6f095a | 1967 | VEX_W_0F41_P_0_LEN_1 = 0, |
1ba585e8 | 1968 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1969 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1970 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1971 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1972 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1973 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1974 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1975 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1976 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1977 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1978 | VEX_W_0F47_P_2_LEN_1, |
1979 | VEX_W_0F4A_P_0_LEN_1, | |
1980 | VEX_W_0F4A_P_2_LEN_1, | |
1981 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1982 | VEX_W_0F4B_P_2_LEN_1, |
43234a1e | 1983 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 1984 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 1985 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 1986 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 1987 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 1988 | VEX_W_0F92_P_2_LEN_0, |
43234a1e | 1989 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 1990 | VEX_W_0F93_P_2_LEN_0, |
43234a1e | 1991 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
1992 | VEX_W_0F98_P_2_LEN_0, |
1993 | VEX_W_0F99_P_0_LEN_0, | |
1994 | VEX_W_0F99_P_2_LEN_0, | |
592a252b L |
1995 | VEX_W_0F380C_P_2, |
1996 | VEX_W_0F380D_P_2, | |
1997 | VEX_W_0F380E_P_2, | |
1998 | VEX_W_0F380F_P_2, | |
6c30d220 | 1999 | VEX_W_0F3816_P_2, |
6c30d220 L |
2000 | VEX_W_0F3818_P_2, |
2001 | VEX_W_0F3819_P_2, | |
592a252b | 2002 | VEX_W_0F381A_P_2_M_0, |
592a252b L |
2003 | VEX_W_0F382C_P_2_M_0, |
2004 | VEX_W_0F382D_P_2_M_0, | |
2005 | VEX_W_0F382E_P_2_M_0, | |
2006 | VEX_W_0F382F_P_2_M_0, | |
6c30d220 | 2007 | VEX_W_0F3836_P_2, |
6c30d220 L |
2008 | VEX_W_0F3846_P_2, |
2009 | VEX_W_0F3858_P_2, | |
2010 | VEX_W_0F3859_P_2, | |
2011 | VEX_W_0F385A_P_2_M_0, | |
2012 | VEX_W_0F3878_P_2, | |
2013 | VEX_W_0F3879_P_2, | |
48521003 | 2014 | VEX_W_0F38CF_P_2, |
6c30d220 L |
2015 | VEX_W_0F3A00_P_2, |
2016 | VEX_W_0F3A01_P_2, | |
2017 | VEX_W_0F3A02_P_2, | |
592a252b L |
2018 | VEX_W_0F3A04_P_2, |
2019 | VEX_W_0F3A05_P_2, | |
2020 | VEX_W_0F3A06_P_2, | |
592a252b L |
2021 | VEX_W_0F3A18_P_2, |
2022 | VEX_W_0F3A19_P_2, | |
43234a1e | 2023 | VEX_W_0F3A30_P_2_LEN_0, |
1ba585e8 | 2024 | VEX_W_0F3A31_P_2_LEN_0, |
43234a1e | 2025 | VEX_W_0F3A32_P_2_LEN_0, |
1ba585e8 | 2026 | VEX_W_0F3A33_P_2_LEN_0, |
6c30d220 L |
2027 | VEX_W_0F3A38_P_2, |
2028 | VEX_W_0F3A39_P_2, | |
6c30d220 | 2029 | VEX_W_0F3A46_P_2, |
592a252b L |
2030 | VEX_W_0F3A48_P_2, |
2031 | VEX_W_0F3A49_P_2, | |
2032 | VEX_W_0F3A4A_P_2, | |
2033 | VEX_W_0F3A4B_P_2, | |
2034 | VEX_W_0F3A4C_P_2, | |
48521003 IT |
2035 | VEX_W_0F3ACE_P_2, |
2036 | VEX_W_0F3ACF_P_2, | |
43234a1e | 2037 | |
36cc073e | 2038 | EVEX_W_0F10_P_1, |
36cc073e | 2039 | EVEX_W_0F10_P_3, |
36cc073e | 2040 | EVEX_W_0F11_P_1, |
36cc073e | 2041 | EVEX_W_0F11_P_3, |
43234a1e L |
2042 | EVEX_W_0F12_P_0_M_1, |
2043 | EVEX_W_0F12_P_1, | |
43234a1e | 2044 | EVEX_W_0F12_P_3, |
43234a1e L |
2045 | EVEX_W_0F16_P_0_M_1, |
2046 | EVEX_W_0F16_P_1, | |
43234a1e | 2047 | EVEX_W_0F2A_P_3, |
43234a1e | 2048 | EVEX_W_0F51_P_1, |
43234a1e | 2049 | EVEX_W_0F51_P_3, |
43234a1e | 2050 | EVEX_W_0F58_P_1, |
43234a1e | 2051 | EVEX_W_0F58_P_3, |
43234a1e | 2052 | EVEX_W_0F59_P_1, |
43234a1e L |
2053 | EVEX_W_0F59_P_3, |
2054 | EVEX_W_0F5A_P_0, | |
2055 | EVEX_W_0F5A_P_1, | |
2056 | EVEX_W_0F5A_P_2, | |
2057 | EVEX_W_0F5A_P_3, | |
2058 | EVEX_W_0F5B_P_0, | |
2059 | EVEX_W_0F5B_P_1, | |
2060 | EVEX_W_0F5B_P_2, | |
43234a1e | 2061 | EVEX_W_0F5C_P_1, |
43234a1e | 2062 | EVEX_W_0F5C_P_3, |
43234a1e | 2063 | EVEX_W_0F5D_P_1, |
43234a1e | 2064 | EVEX_W_0F5D_P_3, |
43234a1e | 2065 | EVEX_W_0F5E_P_1, |
43234a1e | 2066 | EVEX_W_0F5E_P_3, |
43234a1e | 2067 | EVEX_W_0F5F_P_1, |
43234a1e L |
2068 | EVEX_W_0F5F_P_3, |
2069 | EVEX_W_0F62_P_2, | |
2070 | EVEX_W_0F66_P_2, | |
2071 | EVEX_W_0F6A_P_2, | |
1ba585e8 | 2072 | EVEX_W_0F6B_P_2, |
43234a1e L |
2073 | EVEX_W_0F6C_P_2, |
2074 | EVEX_W_0F6D_P_2, | |
43234a1e L |
2075 | EVEX_W_0F6F_P_1, |
2076 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 2077 | EVEX_W_0F6F_P_3, |
43234a1e L |
2078 | EVEX_W_0F70_P_2, |
2079 | EVEX_W_0F72_R_2_P_2, | |
2080 | EVEX_W_0F72_R_6_P_2, | |
2081 | EVEX_W_0F73_R_2_P_2, | |
2082 | EVEX_W_0F73_R_6_P_2, | |
2083 | EVEX_W_0F76_P_2, | |
2084 | EVEX_W_0F78_P_0, | |
90a915bf | 2085 | EVEX_W_0F78_P_2, |
43234a1e | 2086 | EVEX_W_0F79_P_0, |
90a915bf | 2087 | EVEX_W_0F79_P_2, |
43234a1e | 2088 | EVEX_W_0F7A_P_1, |
90a915bf | 2089 | EVEX_W_0F7A_P_2, |
43234a1e | 2090 | EVEX_W_0F7A_P_3, |
90a915bf | 2091 | EVEX_W_0F7B_P_2, |
43234a1e L |
2092 | EVEX_W_0F7B_P_3, |
2093 | EVEX_W_0F7E_P_1, | |
43234a1e L |
2094 | EVEX_W_0F7F_P_1, |
2095 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 2096 | EVEX_W_0F7F_P_3, |
43234a1e | 2097 | EVEX_W_0FC2_P_1, |
43234a1e | 2098 | EVEX_W_0FC2_P_3, |
43234a1e L |
2099 | EVEX_W_0FD2_P_2, |
2100 | EVEX_W_0FD3_P_2, | |
2101 | EVEX_W_0FD4_P_2, | |
2102 | EVEX_W_0FD6_P_2, | |
2103 | EVEX_W_0FE6_P_1, | |
2104 | EVEX_W_0FE6_P_2, | |
2105 | EVEX_W_0FE6_P_3, | |
2106 | EVEX_W_0FE7_P_2, | |
2107 | EVEX_W_0FF2_P_2, | |
2108 | EVEX_W_0FF3_P_2, | |
2109 | EVEX_W_0FF4_P_2, | |
2110 | EVEX_W_0FFA_P_2, | |
2111 | EVEX_W_0FFB_P_2, | |
2112 | EVEX_W_0FFE_P_2, | |
2113 | EVEX_W_0F380C_P_2, | |
2114 | EVEX_W_0F380D_P_2, | |
1ba585e8 IT |
2115 | EVEX_W_0F3810_P_1, |
2116 | EVEX_W_0F3810_P_2, | |
43234a1e | 2117 | EVEX_W_0F3811_P_1, |
1ba585e8 | 2118 | EVEX_W_0F3811_P_2, |
43234a1e | 2119 | EVEX_W_0F3812_P_1, |
1ba585e8 | 2120 | EVEX_W_0F3812_P_2, |
43234a1e L |
2121 | EVEX_W_0F3813_P_1, |
2122 | EVEX_W_0F3813_P_2, | |
2123 | EVEX_W_0F3814_P_1, | |
2124 | EVEX_W_0F3815_P_1, | |
2125 | EVEX_W_0F3818_P_2, | |
2126 | EVEX_W_0F3819_P_2, | |
2127 | EVEX_W_0F381A_P_2, | |
2128 | EVEX_W_0F381B_P_2, | |
2129 | EVEX_W_0F381E_P_2, | |
2130 | EVEX_W_0F381F_P_2, | |
1ba585e8 | 2131 | EVEX_W_0F3820_P_1, |
43234a1e L |
2132 | EVEX_W_0F3821_P_1, |
2133 | EVEX_W_0F3822_P_1, | |
2134 | EVEX_W_0F3823_P_1, | |
2135 | EVEX_W_0F3824_P_1, | |
2136 | EVEX_W_0F3825_P_1, | |
2137 | EVEX_W_0F3825_P_2, | |
1ba585e8 IT |
2138 | EVEX_W_0F3826_P_1, |
2139 | EVEX_W_0F3826_P_2, | |
2140 | EVEX_W_0F3828_P_1, | |
43234a1e | 2141 | EVEX_W_0F3828_P_2, |
1ba585e8 | 2142 | EVEX_W_0F3829_P_1, |
43234a1e L |
2143 | EVEX_W_0F3829_P_2, |
2144 | EVEX_W_0F382A_P_1, | |
2145 | EVEX_W_0F382A_P_2, | |
1ba585e8 IT |
2146 | EVEX_W_0F382B_P_2, |
2147 | EVEX_W_0F3830_P_1, | |
43234a1e L |
2148 | EVEX_W_0F3831_P_1, |
2149 | EVEX_W_0F3832_P_1, | |
2150 | EVEX_W_0F3833_P_1, | |
2151 | EVEX_W_0F3834_P_1, | |
2152 | EVEX_W_0F3835_P_1, | |
2153 | EVEX_W_0F3835_P_2, | |
2154 | EVEX_W_0F3837_P_2, | |
90a915bf IT |
2155 | EVEX_W_0F3838_P_1, |
2156 | EVEX_W_0F3839_P_1, | |
43234a1e L |
2157 | EVEX_W_0F383A_P_1, |
2158 | EVEX_W_0F3840_P_2, | |
d6aab7a1 | 2159 | EVEX_W_0F3852_P_1, |
ee6872be | 2160 | EVEX_W_0F3854_P_2, |
620214f7 | 2161 | EVEX_W_0F3855_P_2, |
43234a1e L |
2162 | EVEX_W_0F3858_P_2, |
2163 | EVEX_W_0F3859_P_2, | |
2164 | EVEX_W_0F385A_P_2, | |
2165 | EVEX_W_0F385B_P_2, | |
53467f57 IT |
2166 | EVEX_W_0F3862_P_2, |
2167 | EVEX_W_0F3863_P_2, | |
1ba585e8 | 2168 | EVEX_W_0F3866_P_2, |
9186c494 | 2169 | EVEX_W_0F3868_P_3, |
53467f57 IT |
2170 | EVEX_W_0F3870_P_2, |
2171 | EVEX_W_0F3871_P_2, | |
d6aab7a1 | 2172 | EVEX_W_0F3872_P_1, |
53467f57 | 2173 | EVEX_W_0F3872_P_2, |
d6aab7a1 | 2174 | EVEX_W_0F3872_P_3, |
53467f57 | 2175 | EVEX_W_0F3873_P_2, |
1ba585e8 IT |
2176 | EVEX_W_0F3875_P_2, |
2177 | EVEX_W_0F3878_P_2, | |
2178 | EVEX_W_0F3879_P_2, | |
2179 | EVEX_W_0F387A_P_2, | |
2180 | EVEX_W_0F387B_P_2, | |
2181 | EVEX_W_0F387D_P_2, | |
14f195c9 | 2182 | EVEX_W_0F3883_P_2, |
1ba585e8 | 2183 | EVEX_W_0F388D_P_2, |
43234a1e L |
2184 | EVEX_W_0F3891_P_2, |
2185 | EVEX_W_0F3893_P_2, | |
2186 | EVEX_W_0F38A1_P_2, | |
2187 | EVEX_W_0F38A3_P_2, | |
2188 | EVEX_W_0F38C7_R_1_P_2, | |
2189 | EVEX_W_0F38C7_R_2_P_2, | |
2190 | EVEX_W_0F38C7_R_5_P_2, | |
2191 | EVEX_W_0F38C7_R_6_P_2, | |
2192 | ||
2193 | EVEX_W_0F3A00_P_2, | |
2194 | EVEX_W_0F3A01_P_2, | |
2195 | EVEX_W_0F3A04_P_2, | |
2196 | EVEX_W_0F3A05_P_2, | |
2197 | EVEX_W_0F3A08_P_2, | |
2198 | EVEX_W_0F3A09_P_2, | |
2199 | EVEX_W_0F3A0A_P_2, | |
2200 | EVEX_W_0F3A0B_P_2, | |
2201 | EVEX_W_0F3A18_P_2, | |
2202 | EVEX_W_0F3A19_P_2, | |
2203 | EVEX_W_0F3A1A_P_2, | |
2204 | EVEX_W_0F3A1B_P_2, | |
2205 | EVEX_W_0F3A1D_P_2, | |
2206 | EVEX_W_0F3A21_P_2, | |
2207 | EVEX_W_0F3A23_P_2, | |
2208 | EVEX_W_0F3A38_P_2, | |
2209 | EVEX_W_0F3A39_P_2, | |
2210 | EVEX_W_0F3A3A_P_2, | |
2211 | EVEX_W_0F3A3B_P_2, | |
1ba585e8 IT |
2212 | EVEX_W_0F3A3E_P_2, |
2213 | EVEX_W_0F3A3F_P_2, | |
2214 | EVEX_W_0F3A42_P_2, | |
90a915bf IT |
2215 | EVEX_W_0F3A43_P_2, |
2216 | EVEX_W_0F3A50_P_2, | |
2217 | EVEX_W_0F3A51_P_2, | |
2218 | EVEX_W_0F3A56_P_2, | |
2219 | EVEX_W_0F3A57_P_2, | |
2220 | EVEX_W_0F3A66_P_2, | |
53467f57 IT |
2221 | EVEX_W_0F3A67_P_2, |
2222 | EVEX_W_0F3A70_P_2, | |
2223 | EVEX_W_0F3A71_P_2, | |
2224 | EVEX_W_0F3A72_P_2, | |
48521003 IT |
2225 | EVEX_W_0F3A73_P_2, |
2226 | EVEX_W_0F3ACE_P_2, | |
2227 | EVEX_W_0F3ACF_P_2 | |
9e30b8e0 L |
2228 | }; |
2229 | ||
26ca5450 | 2230 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2231 | |
2232 | struct dis386 { | |
2da11e11 | 2233 | const char *name; |
ce518a5f L |
2234 | struct |
2235 | { | |
2236 | op_rtn rtn; | |
2237 | int bytemode; | |
2238 | } op[MAX_OPERANDS]; | |
bf890a93 | 2239 | unsigned int prefix_requirement; |
252b5132 RH |
2240 | }; |
2241 | ||
2242 | /* Upper case letters in the instruction names here are macros. | |
2243 | 'A' => print 'b' if no register operands or suffix_always is true | |
2244 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2245 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2246 | size prefix |
ed7841b3 | 2247 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2248 | suffix_always is true |
252b5132 | 2249 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2250 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2251 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2252 | 'H' => print ",pt" or ",pn" branch hint |
d1c36125 | 2253 | 'I' unused. |
8f570d62 | 2254 | 'J' unused. |
42903f7f | 2255 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2256 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2257 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2258 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2259 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2260 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2261 | or suffix_always is true. print 'q' if rex prefix is present. |
2262 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2263 | is true | |
a35ca55a | 2264 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2265 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
a72d2af2 L |
2266 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
2267 | prefix and behave as 'P' otherwise | |
2268 | 'U' => print 'q' in 64bit mode if instruction has no operand size | |
2269 | prefix and behave as 'Q' otherwise | |
2270 | 'V' => print 'q' in 64bit mode if instruction has no operand size | |
2271 | prefix and behave as 'S' otherwise | |
a35ca55a | 2272 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2273 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
9646c87b | 2274 | 'Y' unused. |
6dd5059a | 2275 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2276 | '!' => change condition from true to false or from false to true. |
98b528ac | 2277 | '%' => add 1 upper case letter to the macro. |
5990e377 JB |
2278 | '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size |
2279 | prefix or suffix_always is true (lcall/ljmp). | |
5db04b09 L |
2280 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
2281 | on operand size prefix. | |
07f5af7d L |
2282 | '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction |
2283 | has no operand size prefix for AMD64 ISA, behave as 'P' | |
2284 | otherwise | |
98b528ac L |
2285 | |
2286 | 2 upper case letter macros: | |
04d824a4 JB |
2287 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
2288 | operands and no broadcast. | |
2289 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
2290 | register operands and no broadcast. | |
4b06377f | 2291 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
589958d6 JB |
2292 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory |
2293 | operand or no operand at all in 64bit mode, or if suffix_always | |
2294 | is true. | |
4b06377f L |
2295 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2296 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2297 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2298 | "LW" => print 'd', 'q' depending on the VEX.W bit |
4b4c407a L |
2299 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2300 | an operand size prefix, or suffix_always is true. print | |
2301 | 'q' if rex prefix is present. | |
52b15da3 | 2302 | |
6439fc28 AM |
2303 | Many of the above letters print nothing in Intel mode. See "putop" |
2304 | for the details. | |
52b15da3 | 2305 | |
6439fc28 | 2306 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2307 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2308 | |
6439fc28 | 2309 | static const struct dis386 dis386[] = { |
252b5132 | 2310 | /* 00 */ |
bf890a93 IT |
2311 | { "addB", { Ebh1, Gb }, 0 }, |
2312 | { "addS", { Evh1, Gv }, 0 }, | |
2313 | { "addB", { Gb, EbS }, 0 }, | |
2314 | { "addS", { Gv, EvS }, 0 }, | |
2315 | { "addB", { AL, Ib }, 0 }, | |
2316 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2317 | { X86_64_TABLE (X86_64_06) }, |
2318 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2319 | /* 08 */ |
bf890a93 IT |
2320 | { "orB", { Ebh1, Gb }, 0 }, |
2321 | { "orS", { Evh1, Gv }, 0 }, | |
2322 | { "orB", { Gb, EbS }, 0 }, | |
2323 | { "orS", { Gv, EvS }, 0 }, | |
2324 | { "orB", { AL, Ib }, 0 }, | |
2325 | { "orS", { eAX, Iv }, 0 }, | |
1673df32 | 2326 | { X86_64_TABLE (X86_64_0E) }, |
592d1631 | 2327 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2328 | /* 10 */ |
bf890a93 IT |
2329 | { "adcB", { Ebh1, Gb }, 0 }, |
2330 | { "adcS", { Evh1, Gv }, 0 }, | |
2331 | { "adcB", { Gb, EbS }, 0 }, | |
2332 | { "adcS", { Gv, EvS }, 0 }, | |
2333 | { "adcB", { AL, Ib }, 0 }, | |
2334 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2335 | { X86_64_TABLE (X86_64_16) }, |
2336 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2337 | /* 18 */ |
bf890a93 IT |
2338 | { "sbbB", { Ebh1, Gb }, 0 }, |
2339 | { "sbbS", { Evh1, Gv }, 0 }, | |
2340 | { "sbbB", { Gb, EbS }, 0 }, | |
2341 | { "sbbS", { Gv, EvS }, 0 }, | |
2342 | { "sbbB", { AL, Ib }, 0 }, | |
2343 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2344 | { X86_64_TABLE (X86_64_1E) }, |
2345 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2346 | /* 20 */ |
bf890a93 IT |
2347 | { "andB", { Ebh1, Gb }, 0 }, |
2348 | { "andS", { Evh1, Gv }, 0 }, | |
2349 | { "andB", { Gb, EbS }, 0 }, | |
2350 | { "andS", { Gv, EvS }, 0 }, | |
2351 | { "andB", { AL, Ib }, 0 }, | |
2352 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 2353 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2354 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2355 | /* 28 */ |
bf890a93 IT |
2356 | { "subB", { Ebh1, Gb }, 0 }, |
2357 | { "subS", { Evh1, Gv }, 0 }, | |
2358 | { "subB", { Gb, EbS }, 0 }, | |
2359 | { "subS", { Gv, EvS }, 0 }, | |
2360 | { "subB", { AL, Ib }, 0 }, | |
2361 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 2362 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2363 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2364 | /* 30 */ |
bf890a93 IT |
2365 | { "xorB", { Ebh1, Gb }, 0 }, |
2366 | { "xorS", { Evh1, Gv }, 0 }, | |
2367 | { "xorB", { Gb, EbS }, 0 }, | |
2368 | { "xorS", { Gv, EvS }, 0 }, | |
2369 | { "xorB", { AL, Ib }, 0 }, | |
2370 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 2371 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2372 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2373 | /* 38 */ |
bf890a93 IT |
2374 | { "cmpB", { Eb, Gb }, 0 }, |
2375 | { "cmpS", { Ev, Gv }, 0 }, | |
2376 | { "cmpB", { Gb, EbS }, 0 }, | |
2377 | { "cmpS", { Gv, EvS }, 0 }, | |
2378 | { "cmpB", { AL, Ib }, 0 }, | |
2379 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 2380 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2381 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2382 | /* 40 */ |
bf890a93 IT |
2383 | { "inc{S|}", { RMeAX }, 0 }, |
2384 | { "inc{S|}", { RMeCX }, 0 }, | |
2385 | { "inc{S|}", { RMeDX }, 0 }, | |
2386 | { "inc{S|}", { RMeBX }, 0 }, | |
2387 | { "inc{S|}", { RMeSP }, 0 }, | |
2388 | { "inc{S|}", { RMeBP }, 0 }, | |
2389 | { "inc{S|}", { RMeSI }, 0 }, | |
2390 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 2391 | /* 48 */ |
bf890a93 IT |
2392 | { "dec{S|}", { RMeAX }, 0 }, |
2393 | { "dec{S|}", { RMeCX }, 0 }, | |
2394 | { "dec{S|}", { RMeDX }, 0 }, | |
2395 | { "dec{S|}", { RMeBX }, 0 }, | |
2396 | { "dec{S|}", { RMeSP }, 0 }, | |
2397 | { "dec{S|}", { RMeBP }, 0 }, | |
2398 | { "dec{S|}", { RMeSI }, 0 }, | |
2399 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 2400 | /* 50 */ |
bf890a93 IT |
2401 | { "pushV", { RMrAX }, 0 }, |
2402 | { "pushV", { RMrCX }, 0 }, | |
2403 | { "pushV", { RMrDX }, 0 }, | |
2404 | { "pushV", { RMrBX }, 0 }, | |
2405 | { "pushV", { RMrSP }, 0 }, | |
2406 | { "pushV", { RMrBP }, 0 }, | |
2407 | { "pushV", { RMrSI }, 0 }, | |
2408 | { "pushV", { RMrDI }, 0 }, | |
252b5132 | 2409 | /* 58 */ |
bf890a93 IT |
2410 | { "popV", { RMrAX }, 0 }, |
2411 | { "popV", { RMrCX }, 0 }, | |
2412 | { "popV", { RMrDX }, 0 }, | |
2413 | { "popV", { RMrBX }, 0 }, | |
2414 | { "popV", { RMrSP }, 0 }, | |
2415 | { "popV", { RMrBP }, 0 }, | |
2416 | { "popV", { RMrSI }, 0 }, | |
2417 | { "popV", { RMrDI }, 0 }, | |
252b5132 | 2418 | /* 60 */ |
4e7d34a6 L |
2419 | { X86_64_TABLE (X86_64_60) }, |
2420 | { X86_64_TABLE (X86_64_61) }, | |
2421 | { X86_64_TABLE (X86_64_62) }, | |
2422 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2423 | { Bad_Opcode }, /* seg fs */ |
2424 | { Bad_Opcode }, /* seg gs */ | |
2425 | { Bad_Opcode }, /* op size prefix */ | |
2426 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2427 | /* 68 */ |
bf890a93 IT |
2428 | { "pushT", { sIv }, 0 }, |
2429 | { "imulS", { Gv, Ev, Iv }, 0 }, | |
2430 | { "pushT", { sIbT }, 0 }, | |
2431 | { "imulS", { Gv, Ev, sIb }, 0 }, | |
2432 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 2433 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 2434 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 2435 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2436 | /* 70 */ |
bf890a93 IT |
2437 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2438 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
2439 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
2440 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2441 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2442 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
2443 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2444 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2445 | /* 78 */ |
bf890a93 IT |
2446 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2447 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
2448 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2449 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2450 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
2451 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2452 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
2453 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2454 | /* 80 */ |
1ceb70f8 L |
2455 | { REG_TABLE (REG_80) }, |
2456 | { REG_TABLE (REG_81) }, | |
d039fef3 | 2457 | { X86_64_TABLE (X86_64_82) }, |
7148c369 | 2458 | { REG_TABLE (REG_83) }, |
bf890a93 IT |
2459 | { "testB", { Eb, Gb }, 0 }, |
2460 | { "testS", { Ev, Gv }, 0 }, | |
2461 | { "xchgB", { Ebh2, Gb }, 0 }, | |
2462 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 2463 | /* 88 */ |
bf890a93 IT |
2464 | { "movB", { Ebh3, Gb }, 0 }, |
2465 | { "movS", { Evh3, Gv }, 0 }, | |
2466 | { "movB", { Gb, EbS }, 0 }, | |
2467 | { "movS", { Gv, EvS }, 0 }, | |
2468 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 2469 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 2470 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 2471 | { REG_TABLE (REG_8F) }, |
252b5132 | 2472 | /* 90 */ |
1ceb70f8 | 2473 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
2474 | { "xchgS", { RMeCX, eAX }, 0 }, |
2475 | { "xchgS", { RMeDX, eAX }, 0 }, | |
2476 | { "xchgS", { RMeBX, eAX }, 0 }, | |
2477 | { "xchgS", { RMeSP, eAX }, 0 }, | |
2478 | { "xchgS", { RMeBP, eAX }, 0 }, | |
2479 | { "xchgS", { RMeSI, eAX }, 0 }, | |
2480 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 2481 | /* 98 */ |
bf890a93 IT |
2482 | { "cW{t|}R", { XX }, 0 }, |
2483 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2484 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2485 | { Bad_Opcode }, /* fwait */ |
bf890a93 IT |
2486 | { "pushfT", { XX }, 0 }, |
2487 | { "popfT", { XX }, 0 }, | |
2488 | { "sahf", { XX }, 0 }, | |
2489 | { "lahf", { XX }, 0 }, | |
252b5132 | 2490 | /* a0 */ |
bf890a93 IT |
2491 | { "mov%LB", { AL, Ob }, 0 }, |
2492 | { "mov%LS", { eAX, Ov }, 0 }, | |
2493 | { "mov%LB", { Ob, AL }, 0 }, | |
2494 | { "mov%LS", { Ov, eAX }, 0 }, | |
2495 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2496 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2497 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2498 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2499 | /* a8 */ |
bf890a93 IT |
2500 | { "testB", { AL, Ib }, 0 }, |
2501 | { "testS", { eAX, Iv }, 0 }, | |
2502 | { "stosB", { Ybr, AL }, 0 }, | |
2503 | { "stosS", { Yvr, eAX }, 0 }, | |
2504 | { "lodsB", { ALr, Xb }, 0 }, | |
2505 | { "lodsS", { eAXr, Xv }, 0 }, | |
2506 | { "scasB", { AL, Yb }, 0 }, | |
2507 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2508 | /* b0 */ |
bf890a93 IT |
2509 | { "movB", { RMAL, Ib }, 0 }, |
2510 | { "movB", { RMCL, Ib }, 0 }, | |
2511 | { "movB", { RMDL, Ib }, 0 }, | |
2512 | { "movB", { RMBL, Ib }, 0 }, | |
2513 | { "movB", { RMAH, Ib }, 0 }, | |
2514 | { "movB", { RMCH, Ib }, 0 }, | |
2515 | { "movB", { RMDH, Ib }, 0 }, | |
2516 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2517 | /* b8 */ |
bf890a93 IT |
2518 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2519 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2520 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2521 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2522 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2523 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2524 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2525 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2526 | /* c0 */ |
1ceb70f8 L |
2527 | { REG_TABLE (REG_C0) }, |
2528 | { REG_TABLE (REG_C1) }, | |
aeab2b26 JB |
2529 | { X86_64_TABLE (X86_64_C2) }, |
2530 | { X86_64_TABLE (X86_64_C3) }, | |
4e7d34a6 L |
2531 | { X86_64_TABLE (X86_64_C4) }, |
2532 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2533 | { REG_TABLE (REG_C6) }, |
2534 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2535 | /* c8 */ |
bf890a93 IT |
2536 | { "enterT", { Iw, Ib }, 0 }, |
2537 | { "leaveT", { XX }, 0 }, | |
8f570d62 JB |
2538 | { "{l|}ret{|f}P", { Iw }, 0 }, |
2539 | { "{l|}ret{|f}P", { XX }, 0 }, | |
bf890a93 IT |
2540 | { "int3", { XX }, 0 }, |
2541 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2542 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2543 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2544 | /* d0 */ |
1ceb70f8 L |
2545 | { REG_TABLE (REG_D0) }, |
2546 | { REG_TABLE (REG_D1) }, | |
2547 | { REG_TABLE (REG_D2) }, | |
2548 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2549 | { X86_64_TABLE (X86_64_D4) }, |
2550 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2551 | { Bad_Opcode }, |
bf890a93 | 2552 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2553 | /* d8 */ |
2554 | { FLOAT }, | |
2555 | { FLOAT }, | |
2556 | { FLOAT }, | |
2557 | { FLOAT }, | |
2558 | { FLOAT }, | |
2559 | { FLOAT }, | |
2560 | { FLOAT }, | |
2561 | { FLOAT }, | |
2562 | /* e0 */ | |
bf890a93 IT |
2563 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2564 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2565 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2566 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2567 | { "inB", { AL, Ib }, 0 }, | |
2568 | { "inG", { zAX, Ib }, 0 }, | |
2569 | { "outB", { Ib, AL }, 0 }, | |
2570 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2571 | /* e8 */ |
a72d2af2 L |
2572 | { X86_64_TABLE (X86_64_E8) }, |
2573 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2574 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2575 | { "jmp", { Jb, BND }, 0 }, |
2576 | { "inB", { AL, indirDX }, 0 }, | |
2577 | { "inG", { zAX, indirDX }, 0 }, | |
2578 | { "outB", { indirDX, AL }, 0 }, | |
2579 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2580 | /* f0 */ |
592d1631 | 2581 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2582 | { "icebp", { XX }, 0 }, |
592d1631 L |
2583 | { Bad_Opcode }, /* repne */ |
2584 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2585 | { "hlt", { XX }, 0 }, |
2586 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2587 | { REG_TABLE (REG_F6) }, |
2588 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2589 | /* f8 */ |
bf890a93 IT |
2590 | { "clc", { XX }, 0 }, |
2591 | { "stc", { XX }, 0 }, | |
2592 | { "cli", { XX }, 0 }, | |
2593 | { "sti", { XX }, 0 }, | |
2594 | { "cld", { XX }, 0 }, | |
2595 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2596 | { REG_TABLE (REG_FE) }, |
2597 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2598 | }; |
2599 | ||
6439fc28 | 2600 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2601 | /* 00 */ |
1ceb70f8 L |
2602 | { REG_TABLE (REG_0F00 ) }, |
2603 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2604 | { "larS", { Gv, Ew }, 0 }, |
2605 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2606 | { Bad_Opcode }, |
bf890a93 IT |
2607 | { "syscall", { XX }, 0 }, |
2608 | { "clts", { XX }, 0 }, | |
589958d6 | 2609 | { "sysret%LQ", { XX }, 0 }, |
252b5132 | 2610 | /* 08 */ |
bf890a93 | 2611 | { "invd", { XX }, 0 }, |
3233d7d0 | 2612 | { PREFIX_TABLE (PREFIX_0F09) }, |
592d1631 | 2613 | { Bad_Opcode }, |
bf890a93 | 2614 | { "ud2", { XX }, 0 }, |
592d1631 | 2615 | { Bad_Opcode }, |
b5b1fc4f | 2616 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2617 | { "femms", { XX }, 0 }, |
2618 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2619 | /* 10 */ |
1ceb70f8 L |
2620 | { PREFIX_TABLE (PREFIX_0F10) }, |
2621 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2622 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2623 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2624 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2625 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2626 | { PREFIX_TABLE (PREFIX_0F16) }, |
2627 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2628 | /* 18 */ |
1ceb70f8 | 2629 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2630 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2631 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2632 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
c48935d7 | 2633 | { PREFIX_TABLE (PREFIX_0F1C) }, |
bf890a93 | 2634 | { "nopQ", { Ev }, 0 }, |
603555e5 | 2635 | { PREFIX_TABLE (PREFIX_0F1E) }, |
bf890a93 | 2636 | { "nopQ", { Ev }, 0 }, |
252b5132 | 2637 | /* 20 */ |
bf890a93 IT |
2638 | { "movZ", { Rm, Cm }, 0 }, |
2639 | { "movZ", { Rm, Dm }, 0 }, | |
2640 | { "movZ", { Cm, Rm }, 0 }, | |
2641 | { "movZ", { Dm, Rm }, 0 }, | |
1ceb70f8 | 2642 | { MOD_TABLE (MOD_0F24) }, |
592d1631 | 2643 | { Bad_Opcode }, |
1ceb70f8 | 2644 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2645 | { Bad_Opcode }, |
252b5132 | 2646 | /* 28 */ |
507bd325 L |
2647 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2648 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2649 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2650 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2651 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2652 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2653 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2654 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2655 | /* 30 */ |
bf890a93 IT |
2656 | { "wrmsr", { XX }, 0 }, |
2657 | { "rdtsc", { XX }, 0 }, | |
2658 | { "rdmsr", { XX }, 0 }, | |
2659 | { "rdpmc", { XX }, 0 }, | |
d835a58b JB |
2660 | { "sysenter", { SEP }, 0 }, |
2661 | { "sysexit", { SEP }, 0 }, | |
592d1631 | 2662 | { Bad_Opcode }, |
bf890a93 | 2663 | { "getsec", { XX }, 0 }, |
252b5132 | 2664 | /* 38 */ |
507bd325 | 2665 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2666 | { Bad_Opcode }, |
507bd325 | 2667 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2668 | { Bad_Opcode }, |
2669 | { Bad_Opcode }, | |
2670 | { Bad_Opcode }, | |
2671 | { Bad_Opcode }, | |
2672 | { Bad_Opcode }, | |
252b5132 | 2673 | /* 40 */ |
bf890a93 IT |
2674 | { "cmovoS", { Gv, Ev }, 0 }, |
2675 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2676 | { "cmovbS", { Gv, Ev }, 0 }, | |
2677 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2678 | { "cmoveS", { Gv, Ev }, 0 }, | |
2679 | { "cmovneS", { Gv, Ev }, 0 }, | |
2680 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2681 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2682 | /* 48 */ |
bf890a93 IT |
2683 | { "cmovsS", { Gv, Ev }, 0 }, |
2684 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2685 | { "cmovpS", { Gv, Ev }, 0 }, | |
2686 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2687 | { "cmovlS", { Gv, Ev }, 0 }, | |
2688 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2689 | { "cmovleS", { Gv, Ev }, 0 }, | |
2690 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2691 | /* 50 */ |
a5aaedb9 | 2692 | { MOD_TABLE (MOD_0F50) }, |
1ceb70f8 L |
2693 | { PREFIX_TABLE (PREFIX_0F51) }, |
2694 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2695 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2696 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2697 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2698 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2699 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2700 | /* 58 */ |
1ceb70f8 L |
2701 | { PREFIX_TABLE (PREFIX_0F58) }, |
2702 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2703 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2704 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2705 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2706 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2707 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2708 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2709 | /* 60 */ |
1ceb70f8 L |
2710 | { PREFIX_TABLE (PREFIX_0F60) }, |
2711 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2712 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2713 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2714 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2715 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2716 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2717 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2718 | /* 68 */ |
507bd325 L |
2719 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2720 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2721 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2722 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2723 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2724 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
507bd325 | 2725 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2726 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2727 | /* 70 */ |
1ceb70f8 L |
2728 | { PREFIX_TABLE (PREFIX_0F70) }, |
2729 | { REG_TABLE (REG_0F71) }, | |
2730 | { REG_TABLE (REG_0F72) }, | |
2731 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
2732 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2733 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
2734 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
2735 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 2736 | /* 78 */ |
1ceb70f8 L |
2737 | { PREFIX_TABLE (PREFIX_0F78) }, |
2738 | { PREFIX_TABLE (PREFIX_0F79) }, | |
1f334aeb | 2739 | { Bad_Opcode }, |
592d1631 | 2740 | { Bad_Opcode }, |
1ceb70f8 L |
2741 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2742 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2743 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2744 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2745 | /* 80 */ |
bf890a93 IT |
2746 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2747 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
2748 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
2749 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2750 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2751 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
2752 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2753 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2754 | /* 88 */ |
bf890a93 IT |
2755 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2756 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
2757 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2758 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2759 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
2760 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2761 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
2762 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2763 | /* 90 */ |
bf890a93 IT |
2764 | { "seto", { Eb }, 0 }, |
2765 | { "setno", { Eb }, 0 }, | |
2766 | { "setb", { Eb }, 0 }, | |
2767 | { "setae", { Eb }, 0 }, | |
2768 | { "sete", { Eb }, 0 }, | |
2769 | { "setne", { Eb }, 0 }, | |
2770 | { "setbe", { Eb }, 0 }, | |
2771 | { "seta", { Eb }, 0 }, | |
252b5132 | 2772 | /* 98 */ |
bf890a93 IT |
2773 | { "sets", { Eb }, 0 }, |
2774 | { "setns", { Eb }, 0 }, | |
2775 | { "setp", { Eb }, 0 }, | |
2776 | { "setnp", { Eb }, 0 }, | |
2777 | { "setl", { Eb }, 0 }, | |
2778 | { "setge", { Eb }, 0 }, | |
2779 | { "setle", { Eb }, 0 }, | |
2780 | { "setg", { Eb }, 0 }, | |
252b5132 | 2781 | /* a0 */ |
bf890a93 IT |
2782 | { "pushT", { fs }, 0 }, |
2783 | { "popT", { fs }, 0 }, | |
2784 | { "cpuid", { XX }, 0 }, | |
2785 | { "btS", { Ev, Gv }, 0 }, | |
2786 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
2787 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
2788 | { REG_TABLE (REG_0FA6) }, |
2789 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2790 | /* a8 */ |
bf890a93 IT |
2791 | { "pushT", { gs }, 0 }, |
2792 | { "popT", { gs }, 0 }, | |
2793 | { "rsm", { XX }, 0 }, | |
2794 | { "btsS", { Evh1, Gv }, 0 }, | |
2795 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
2796 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 2797 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 2798 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 2799 | /* b0 */ |
bf890a93 IT |
2800 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
2801 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2802 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 2803 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
2804 | { MOD_TABLE (MOD_0FB4) }, |
2805 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
2806 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
2807 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 2808 | /* b8 */ |
1ceb70f8 | 2809 | { PREFIX_TABLE (PREFIX_0FB8) }, |
66f1eba0 | 2810 | { "ud1S", { Gv, Ev }, 0 }, |
1ceb70f8 | 2811 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 2812 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 2813 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 2814 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
2815 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
2816 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 2817 | /* c0 */ |
bf890a93 IT |
2818 | { "xaddB", { Ebh1, Gb }, 0 }, |
2819 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2820 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 2821 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
2822 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
2823 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
2824 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 2825 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2826 | /* c8 */ |
bf890a93 IT |
2827 | { "bswap", { RMeAX }, 0 }, |
2828 | { "bswap", { RMeCX }, 0 }, | |
2829 | { "bswap", { RMeDX }, 0 }, | |
2830 | { "bswap", { RMeBX }, 0 }, | |
2831 | { "bswap", { RMeSP }, 0 }, | |
2832 | { "bswap", { RMeBP }, 0 }, | |
2833 | { "bswap", { RMeSI }, 0 }, | |
2834 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 2835 | /* d0 */ |
1ceb70f8 | 2836 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
2837 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
2838 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
2839 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
2840 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
2841 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2842 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 2843 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 2844 | /* d8 */ |
507bd325 L |
2845 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
2846 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
2847 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
2848 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
2849 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
2850 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
2851 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
2852 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2853 | /* e0 */ |
507bd325 L |
2854 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
2855 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
2856 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
2857 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
2858 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
2859 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2860 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2861 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 2862 | /* e8 */ |
507bd325 L |
2863 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
2864 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
2865 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
2866 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
2867 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
2868 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
2869 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
2870 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2871 | /* f0 */ |
1ceb70f8 | 2872 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
2873 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
2874 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
2875 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
2876 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
2877 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
2878 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2879 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 2880 | /* f8 */ |
507bd325 L |
2881 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
2882 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
2883 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
2884 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
2885 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
2886 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
2887 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
66f1eba0 | 2888 | { "ud0S", { Gv, Ev }, 0 }, |
252b5132 RH |
2889 | }; |
2890 | ||
2891 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
2892 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2893 | /* ------------------------------- */ | |
2894 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
2895 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
2896 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
2897 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
2898 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
2899 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
2900 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
2901 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
2902 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
2903 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
2904 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
2905 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
2906 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
2907 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
2908 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
2909 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
2910 | /* ------------------------------- */ | |
2911 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
2912 | }; |
2913 | ||
2914 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
2915 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2916 | /* ------------------------------- */ | |
252b5132 | 2917 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 2918 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 2919 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 2920 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 2921 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
2922 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
2923 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 2924 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
2925 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
2926 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 2927 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
66f1eba0 | 2928 | /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ |
252b5132 | 2929 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 2930 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 2931 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
66f1eba0 | 2932 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ |
c608c12e AM |
2933 | /* ------------------------------- */ |
2934 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
2935 | }; | |
2936 | ||
252b5132 RH |
2937 | static char obuf[100]; |
2938 | static char *obufp; | |
ea397f5b | 2939 | static char *mnemonicendp; |
252b5132 RH |
2940 | static char scratchbuf[100]; |
2941 | static unsigned char *start_codep; | |
2942 | static unsigned char *insn_codep; | |
2943 | static unsigned char *codep; | |
285ca992 | 2944 | static unsigned char *end_codep; |
f16cd0d5 L |
2945 | static int last_lock_prefix; |
2946 | static int last_repz_prefix; | |
2947 | static int last_repnz_prefix; | |
2948 | static int last_data_prefix; | |
2949 | static int last_addr_prefix; | |
2950 | static int last_rex_prefix; | |
2951 | static int last_seg_prefix; | |
d9949a36 | 2952 | static int fwait_prefix; |
285ca992 L |
2953 | /* The active segment register prefix. */ |
2954 | static int active_seg_prefix; | |
f16cd0d5 L |
2955 | #define MAX_CODE_LENGTH 15 |
2956 | /* We can up to 14 prefixes since the maximum instruction length is | |
2957 | 15bytes. */ | |
2958 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 2959 | static disassemble_info *the_info; |
7967e09e L |
2960 | static struct |
2961 | { | |
2962 | int mod; | |
7967e09e | 2963 | int reg; |
484c222e | 2964 | int rm; |
7967e09e L |
2965 | } |
2966 | modrm; | |
4bba6815 | 2967 | static unsigned char need_modrm; |
dfc8cf43 L |
2968 | static struct |
2969 | { | |
2970 | int scale; | |
2971 | int index; | |
2972 | int base; | |
2973 | } | |
2974 | sib; | |
c0f3af97 L |
2975 | static struct |
2976 | { | |
2977 | int register_specifier; | |
2978 | int length; | |
2979 | int prefix; | |
2980 | int w; | |
43234a1e L |
2981 | int evex; |
2982 | int r; | |
2983 | int v; | |
2984 | int mask_register_specifier; | |
2985 | int zeroing; | |
2986 | int ll; | |
2987 | int b; | |
c0f3af97 L |
2988 | } |
2989 | vex; | |
2990 | static unsigned char need_vex; | |
2991 | static unsigned char need_vex_reg; | |
dae39acc | 2992 | static unsigned char vex_w_done; |
252b5132 | 2993 | |
ea397f5b L |
2994 | struct op |
2995 | { | |
2996 | const char *name; | |
2997 | unsigned int len; | |
2998 | }; | |
2999 | ||
4bba6815 AM |
3000 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
3001 | values are stale. Hitting this abort likely indicates that you | |
3002 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
3003 | #define MODRM_CHECK if (!need_modrm) abort () | |
3004 | ||
d708bcba AM |
3005 | static const char **names64; |
3006 | static const char **names32; | |
3007 | static const char **names16; | |
3008 | static const char **names8; | |
3009 | static const char **names8rex; | |
3010 | static const char **names_seg; | |
db51cc60 L |
3011 | static const char *index64; |
3012 | static const char *index32; | |
d708bcba | 3013 | static const char **index16; |
7e8b059b | 3014 | static const char **names_bnd; |
d708bcba AM |
3015 | |
3016 | static const char *intel_names64[] = { | |
3017 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
3018 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
3019 | }; | |
3020 | static const char *intel_names32[] = { | |
3021 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
3022 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
3023 | }; | |
3024 | static const char *intel_names16[] = { | |
3025 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
3026 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
3027 | }; | |
3028 | static const char *intel_names8[] = { | |
3029 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
3030 | }; | |
3031 | static const char *intel_names8rex[] = { | |
3032 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
3033 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
3034 | }; | |
3035 | static const char *intel_names_seg[] = { | |
3036 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
3037 | }; | |
db51cc60 L |
3038 | static const char *intel_index64 = "riz"; |
3039 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
3040 | static const char *intel_index16[] = { |
3041 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
3042 | }; | |
3043 | ||
3044 | static const char *att_names64[] = { | |
3045 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
3046 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
3047 | }; | |
d708bcba AM |
3048 | static const char *att_names32[] = { |
3049 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 3050 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 3051 | }; |
d708bcba AM |
3052 | static const char *att_names16[] = { |
3053 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 3054 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 3055 | }; |
d708bcba AM |
3056 | static const char *att_names8[] = { |
3057 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 3058 | }; |
d708bcba AM |
3059 | static const char *att_names8rex[] = { |
3060 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
3061 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
3062 | }; | |
d708bcba AM |
3063 | static const char *att_names_seg[] = { |
3064 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 3065 | }; |
db51cc60 L |
3066 | static const char *att_index64 = "%riz"; |
3067 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
3068 | static const char *att_index16[] = { |
3069 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
3070 | }; |
3071 | ||
b9733481 L |
3072 | static const char **names_mm; |
3073 | static const char *intel_names_mm[] = { | |
3074 | "mm0", "mm1", "mm2", "mm3", | |
3075 | "mm4", "mm5", "mm6", "mm7" | |
3076 | }; | |
3077 | static const char *att_names_mm[] = { | |
3078 | "%mm0", "%mm1", "%mm2", "%mm3", | |
3079 | "%mm4", "%mm5", "%mm6", "%mm7" | |
3080 | }; | |
3081 | ||
7e8b059b L |
3082 | static const char *intel_names_bnd[] = { |
3083 | "bnd0", "bnd1", "bnd2", "bnd3" | |
3084 | }; | |
3085 | ||
3086 | static const char *att_names_bnd[] = { | |
3087 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
3088 | }; | |
3089 | ||
b9733481 L |
3090 | static const char **names_xmm; |
3091 | static const char *intel_names_xmm[] = { | |
3092 | "xmm0", "xmm1", "xmm2", "xmm3", | |
3093 | "xmm4", "xmm5", "xmm6", "xmm7", | |
3094 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
3095 | "xmm12", "xmm13", "xmm14", "xmm15", |
3096 | "xmm16", "xmm17", "xmm18", "xmm19", | |
3097 | "xmm20", "xmm21", "xmm22", "xmm23", | |
3098 | "xmm24", "xmm25", "xmm26", "xmm27", | |
3099 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
3100 | }; |
3101 | static const char *att_names_xmm[] = { | |
3102 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3103 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3104 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3105 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3106 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3107 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3108 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3109 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3110 | }; |
3111 | ||
3112 | static const char **names_ymm; | |
3113 | static const char *intel_names_ymm[] = { | |
3114 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3115 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3116 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3117 | "ymm12", "ymm13", "ymm14", "ymm15", |
3118 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3119 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3120 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3121 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3122 | }; |
3123 | static const char *att_names_ymm[] = { | |
3124 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3125 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3126 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3127 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3128 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3129 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3130 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3131 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3132 | }; | |
3133 | ||
3134 | static const char **names_zmm; | |
3135 | static const char *intel_names_zmm[] = { | |
3136 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3137 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3138 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3139 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3140 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3141 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3142 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3143 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3144 | }; | |
3145 | static const char *att_names_zmm[] = { | |
3146 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3147 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3148 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3149 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3150 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3151 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3152 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3153 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3154 | }; | |
3155 | ||
3156 | static const char **names_mask; | |
3157 | static const char *intel_names_mask[] = { | |
3158 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3159 | }; | |
3160 | static const char *att_names_mask[] = { | |
3161 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3162 | }; | |
3163 | ||
3164 | static const char *names_rounding[] = | |
3165 | { | |
3166 | "{rn-sae}", | |
3167 | "{rd-sae}", | |
3168 | "{ru-sae}", | |
3169 | "{rz-sae}" | |
b9733481 L |
3170 | }; |
3171 | ||
1ceb70f8 L |
3172 | static const struct dis386 reg_table[][8] = { |
3173 | /* REG_80 */ | |
252b5132 | 3174 | { |
bf890a93 IT |
3175 | { "addA", { Ebh1, Ib }, 0 }, |
3176 | { "orA", { Ebh1, Ib }, 0 }, | |
3177 | { "adcA", { Ebh1, Ib }, 0 }, | |
3178 | { "sbbA", { Ebh1, Ib }, 0 }, | |
3179 | { "andA", { Ebh1, Ib }, 0 }, | |
3180 | { "subA", { Ebh1, Ib }, 0 }, | |
3181 | { "xorA", { Ebh1, Ib }, 0 }, | |
3182 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 3183 | }, |
1ceb70f8 | 3184 | /* REG_81 */ |
252b5132 | 3185 | { |
bf890a93 IT |
3186 | { "addQ", { Evh1, Iv }, 0 }, |
3187 | { "orQ", { Evh1, Iv }, 0 }, | |
3188 | { "adcQ", { Evh1, Iv }, 0 }, | |
3189 | { "sbbQ", { Evh1, Iv }, 0 }, | |
3190 | { "andQ", { Evh1, Iv }, 0 }, | |
3191 | { "subQ", { Evh1, Iv }, 0 }, | |
3192 | { "xorQ", { Evh1, Iv }, 0 }, | |
3193 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 3194 | }, |
7148c369 | 3195 | /* REG_83 */ |
252b5132 | 3196 | { |
bf890a93 IT |
3197 | { "addQ", { Evh1, sIb }, 0 }, |
3198 | { "orQ", { Evh1, sIb }, 0 }, | |
3199 | { "adcQ", { Evh1, sIb }, 0 }, | |
3200 | { "sbbQ", { Evh1, sIb }, 0 }, | |
3201 | { "andQ", { Evh1, sIb }, 0 }, | |
3202 | { "subQ", { Evh1, sIb }, 0 }, | |
3203 | { "xorQ", { Evh1, sIb }, 0 }, | |
3204 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 3205 | }, |
1ceb70f8 | 3206 | /* REG_8F */ |
4e7d34a6 | 3207 | { |
bf890a93 | 3208 | { "popU", { stackEv }, 0 }, |
c48244a5 | 3209 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3210 | { Bad_Opcode }, |
3211 | { Bad_Opcode }, | |
3212 | { Bad_Opcode }, | |
f88c9eb0 | 3213 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3214 | }, |
1ceb70f8 | 3215 | /* REG_C0 */ |
252b5132 | 3216 | { |
bf890a93 IT |
3217 | { "rolA", { Eb, Ib }, 0 }, |
3218 | { "rorA", { Eb, Ib }, 0 }, | |
3219 | { "rclA", { Eb, Ib }, 0 }, | |
3220 | { "rcrA", { Eb, Ib }, 0 }, | |
3221 | { "shlA", { Eb, Ib }, 0 }, | |
3222 | { "shrA", { Eb, Ib }, 0 }, | |
e4bdd679 | 3223 | { "shlA", { Eb, Ib }, 0 }, |
bf890a93 | 3224 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 3225 | }, |
1ceb70f8 | 3226 | /* REG_C1 */ |
252b5132 | 3227 | { |
bf890a93 IT |
3228 | { "rolQ", { Ev, Ib }, 0 }, |
3229 | { "rorQ", { Ev, Ib }, 0 }, | |
3230 | { "rclQ", { Ev, Ib }, 0 }, | |
3231 | { "rcrQ", { Ev, Ib }, 0 }, | |
3232 | { "shlQ", { Ev, Ib }, 0 }, | |
3233 | { "shrQ", { Ev, Ib }, 0 }, | |
e4bdd679 | 3234 | { "shlQ", { Ev, Ib }, 0 }, |
bf890a93 | 3235 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 3236 | }, |
1ceb70f8 | 3237 | /* REG_C6 */ |
4e7d34a6 | 3238 | { |
bf890a93 | 3239 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
3240 | { Bad_Opcode }, |
3241 | { Bad_Opcode }, | |
3242 | { Bad_Opcode }, | |
3243 | { Bad_Opcode }, | |
3244 | { Bad_Opcode }, | |
3245 | { Bad_Opcode }, | |
3246 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3247 | }, |
1ceb70f8 | 3248 | /* REG_C7 */ |
4e7d34a6 | 3249 | { |
bf890a93 | 3250 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
3251 | { Bad_Opcode }, |
3252 | { Bad_Opcode }, | |
3253 | { Bad_Opcode }, | |
3254 | { Bad_Opcode }, | |
3255 | { Bad_Opcode }, | |
3256 | { Bad_Opcode }, | |
3257 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3258 | }, |
1ceb70f8 | 3259 | /* REG_D0 */ |
252b5132 | 3260 | { |
bf890a93 IT |
3261 | { "rolA", { Eb, I1 }, 0 }, |
3262 | { "rorA", { Eb, I1 }, 0 }, | |
3263 | { "rclA", { Eb, I1 }, 0 }, | |
3264 | { "rcrA", { Eb, I1 }, 0 }, | |
3265 | { "shlA", { Eb, I1 }, 0 }, | |
3266 | { "shrA", { Eb, I1 }, 0 }, | |
e4bdd679 | 3267 | { "shlA", { Eb, I1 }, 0 }, |
bf890a93 | 3268 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 3269 | }, |
1ceb70f8 | 3270 | /* REG_D1 */ |
252b5132 | 3271 | { |
bf890a93 IT |
3272 | { "rolQ", { Ev, I1 }, 0 }, |
3273 | { "rorQ", { Ev, I1 }, 0 }, | |
3274 | { "rclQ", { Ev, I1 }, 0 }, | |
3275 | { "rcrQ", { Ev, I1 }, 0 }, | |
3276 | { "shlQ", { Ev, I1 }, 0 }, | |
3277 | { "shrQ", { Ev, I1 }, 0 }, | |
e4bdd679 | 3278 | { "shlQ", { Ev, I1 }, 0 }, |
bf890a93 | 3279 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 3280 | }, |
1ceb70f8 | 3281 | /* REG_D2 */ |
252b5132 | 3282 | { |
bf890a93 IT |
3283 | { "rolA", { Eb, CL }, 0 }, |
3284 | { "rorA", { Eb, CL }, 0 }, | |
3285 | { "rclA", { Eb, CL }, 0 }, | |
3286 | { "rcrA", { Eb, CL }, 0 }, | |
3287 | { "shlA", { Eb, CL }, 0 }, | |
3288 | { "shrA", { Eb, CL }, 0 }, | |
e4bdd679 | 3289 | { "shlA", { Eb, CL }, 0 }, |
bf890a93 | 3290 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 3291 | }, |
1ceb70f8 | 3292 | /* REG_D3 */ |
252b5132 | 3293 | { |
bf890a93 IT |
3294 | { "rolQ", { Ev, CL }, 0 }, |
3295 | { "rorQ", { Ev, CL }, 0 }, | |
3296 | { "rclQ", { Ev, CL }, 0 }, | |
3297 | { "rcrQ", { Ev, CL }, 0 }, | |
3298 | { "shlQ", { Ev, CL }, 0 }, | |
3299 | { "shrQ", { Ev, CL }, 0 }, | |
e4bdd679 | 3300 | { "shlQ", { Ev, CL }, 0 }, |
bf890a93 | 3301 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 3302 | }, |
1ceb70f8 | 3303 | /* REG_F6 */ |
252b5132 | 3304 | { |
bf890a93 | 3305 | { "testA", { Eb, Ib }, 0 }, |
7db2c588 | 3306 | { "testA", { Eb, Ib }, 0 }, |
bf890a93 IT |
3307 | { "notA", { Ebh1 }, 0 }, |
3308 | { "negA", { Ebh1 }, 0 }, | |
3309 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
3310 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
3311 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
3312 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 3313 | }, |
1ceb70f8 | 3314 | /* REG_F7 */ |
252b5132 | 3315 | { |
bf890a93 | 3316 | { "testQ", { Ev, Iv }, 0 }, |
7db2c588 | 3317 | { "testQ", { Ev, Iv }, 0 }, |
bf890a93 IT |
3318 | { "notQ", { Evh1 }, 0 }, |
3319 | { "negQ", { Evh1 }, 0 }, | |
3320 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
3321 | { "imulQ", { Ev }, 0 }, | |
3322 | { "divQ", { Ev }, 0 }, | |
3323 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 3324 | }, |
1ceb70f8 | 3325 | /* REG_FE */ |
252b5132 | 3326 | { |
bf890a93 IT |
3327 | { "incA", { Ebh1 }, 0 }, |
3328 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 3329 | }, |
1ceb70f8 | 3330 | /* REG_FF */ |
252b5132 | 3331 | { |
bf890a93 IT |
3332 | { "incQ", { Evh1 }, 0 }, |
3333 | { "decQ", { Evh1 }, 0 }, | |
9fef80d6 | 3334 | { "call{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3335 | { MOD_TABLE (MOD_FF_REG_3) }, |
9fef80d6 | 3336 | { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3337 | { MOD_TABLE (MOD_FF_REG_5) }, |
bf890a93 | 3338 | { "pushU", { stackEv }, 0 }, |
592d1631 | 3339 | { Bad_Opcode }, |
252b5132 | 3340 | }, |
1ceb70f8 | 3341 | /* REG_0F00 */ |
252b5132 | 3342 | { |
bf890a93 IT |
3343 | { "sldtD", { Sv }, 0 }, |
3344 | { "strD", { Sv }, 0 }, | |
3345 | { "lldt", { Ew }, 0 }, | |
3346 | { "ltr", { Ew }, 0 }, | |
3347 | { "verr", { Ew }, 0 }, | |
3348 | { "verw", { Ew }, 0 }, | |
592d1631 L |
3349 | { Bad_Opcode }, |
3350 | { Bad_Opcode }, | |
252b5132 | 3351 | }, |
1ceb70f8 | 3352 | /* REG_0F01 */ |
252b5132 | 3353 | { |
1ceb70f8 L |
3354 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3355 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3356 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3357 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 3358 | { "smswD", { Sv }, 0 }, |
8eab4136 | 3359 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 3360 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 3361 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3362 | }, |
b5b1fc4f | 3363 | /* REG_0F0D */ |
252b5132 | 3364 | { |
bf890a93 IT |
3365 | { "prefetch", { Mb }, 0 }, |
3366 | { "prefetchw", { Mb }, 0 }, | |
3367 | { "prefetchwt1", { Mb }, 0 }, | |
3368 | { "prefetch", { Mb }, 0 }, | |
3369 | { "prefetch", { Mb }, 0 }, | |
3370 | { "prefetch", { Mb }, 0 }, | |
3371 | { "prefetch", { Mb }, 0 }, | |
3372 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 3373 | }, |
1ceb70f8 | 3374 | /* REG_0F18 */ |
252b5132 | 3375 | { |
1ceb70f8 L |
3376 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3377 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3378 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3379 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3380 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3381 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3382 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3383 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3384 | }, |
f8687e93 | 3385 | /* REG_0F1C_P_0_MOD_0 */ |
c48935d7 IT |
3386 | { |
3387 | { "cldemote", { Mb }, 0 }, | |
3388 | { "nopQ", { Ev }, 0 }, | |
3389 | { "nopQ", { Ev }, 0 }, | |
3390 | { "nopQ", { Ev }, 0 }, | |
3391 | { "nopQ", { Ev }, 0 }, | |
3392 | { "nopQ", { Ev }, 0 }, | |
3393 | { "nopQ", { Ev }, 0 }, | |
3394 | { "nopQ", { Ev }, 0 }, | |
3395 | }, | |
f8687e93 | 3396 | /* REG_0F1E_P_1_MOD_3 */ |
603555e5 L |
3397 | { |
3398 | { "nopQ", { Ev }, 0 }, | |
3399 | { "rdsspK", { Rdq }, PREFIX_OPCODE }, | |
3400 | { "nopQ", { Ev }, 0 }, | |
3401 | { "nopQ", { Ev }, 0 }, | |
3402 | { "nopQ", { Ev }, 0 }, | |
3403 | { "nopQ", { Ev }, 0 }, | |
3404 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 3405 | { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) }, |
603555e5 | 3406 | }, |
1ceb70f8 | 3407 | /* REG_0F71 */ |
a6bd098c | 3408 | { |
592d1631 L |
3409 | { Bad_Opcode }, |
3410 | { Bad_Opcode }, | |
1ceb70f8 | 3411 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3412 | { Bad_Opcode }, |
1ceb70f8 | 3413 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3414 | { Bad_Opcode }, |
1ceb70f8 | 3415 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3416 | }, |
1ceb70f8 | 3417 | /* REG_0F72 */ |
a6bd098c | 3418 | { |
592d1631 L |
3419 | { Bad_Opcode }, |
3420 | { Bad_Opcode }, | |
1ceb70f8 | 3421 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3422 | { Bad_Opcode }, |
1ceb70f8 | 3423 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3424 | { Bad_Opcode }, |
1ceb70f8 | 3425 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3426 | }, |
1ceb70f8 | 3427 | /* REG_0F73 */ |
252b5132 | 3428 | { |
592d1631 L |
3429 | { Bad_Opcode }, |
3430 | { Bad_Opcode }, | |
1ceb70f8 L |
3431 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3432 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3433 | { Bad_Opcode }, |
3434 | { Bad_Opcode }, | |
1ceb70f8 L |
3435 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3436 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3437 | }, |
1ceb70f8 | 3438 | /* REG_0FA6 */ |
252b5132 | 3439 | { |
bf890a93 IT |
3440 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3441 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
3442 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3443 | }, |
1ceb70f8 | 3444 | /* REG_0FA7 */ |
4e7d34a6 | 3445 | { |
bf890a93 IT |
3446 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3447 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
3448 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
3449 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
3450 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
3451 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3452 | }, |
1ceb70f8 | 3453 | /* REG_0FAE */ |
4e7d34a6 | 3454 | { |
1ceb70f8 L |
3455 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3456 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3457 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3458 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3459 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3460 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3461 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3462 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3463 | }, |
1ceb70f8 | 3464 | /* REG_0FBA */ |
252b5132 | 3465 | { |
592d1631 L |
3466 | { Bad_Opcode }, |
3467 | { Bad_Opcode }, | |
3468 | { Bad_Opcode }, | |
3469 | { Bad_Opcode }, | |
bf890a93 IT |
3470 | { "btQ", { Ev, Ib }, 0 }, |
3471 | { "btsQ", { Evh1, Ib }, 0 }, | |
3472 | { "btrQ", { Evh1, Ib }, 0 }, | |
3473 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3474 | }, |
1ceb70f8 | 3475 | /* REG_0FC7 */ |
c608c12e | 3476 | { |
592d1631 | 3477 | { Bad_Opcode }, |
bf890a93 | 3478 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3479 | { Bad_Opcode }, |
963f3586 IT |
3480 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3481 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3482 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3483 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3484 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3485 | }, |
592a252b | 3486 | /* REG_VEX_0F71 */ |
c0f3af97 | 3487 | { |
592d1631 L |
3488 | { Bad_Opcode }, |
3489 | { Bad_Opcode }, | |
592a252b | 3490 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3491 | { Bad_Opcode }, |
592a252b | 3492 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3493 | { Bad_Opcode }, |
592a252b | 3494 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3495 | }, |
592a252b | 3496 | /* REG_VEX_0F72 */ |
c0f3af97 | 3497 | { |
592d1631 L |
3498 | { Bad_Opcode }, |
3499 | { Bad_Opcode }, | |
592a252b | 3500 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3501 | { Bad_Opcode }, |
592a252b | 3502 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3503 | { Bad_Opcode }, |
592a252b | 3504 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3505 | }, |
592a252b | 3506 | /* REG_VEX_0F73 */ |
c0f3af97 | 3507 | { |
592d1631 L |
3508 | { Bad_Opcode }, |
3509 | { Bad_Opcode }, | |
592a252b L |
3510 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3511 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3512 | { Bad_Opcode }, |
3513 | { Bad_Opcode }, | |
592a252b L |
3514 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3515 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3516 | }, |
592a252b | 3517 | /* REG_VEX_0FAE */ |
c0f3af97 | 3518 | { |
592d1631 L |
3519 | { Bad_Opcode }, |
3520 | { Bad_Opcode }, | |
592a252b L |
3521 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3522 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3523 | }, |
f12dc422 L |
3524 | /* REG_VEX_0F38F3 */ |
3525 | { | |
3526 | { Bad_Opcode }, | |
3527 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3528 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3529 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3530 | }, | |
f88c9eb0 SP |
3531 | /* REG_XOP_LWPCB */ |
3532 | { | |
bf890a93 IT |
3533 | { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3534 | { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, | |
f88c9eb0 SP |
3535 | }, |
3536 | /* REG_XOP_LWP */ | |
3537 | { | |
c1dc7af5 JB |
3538 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, |
3539 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, | |
f88c9eb0 | 3540 | }, |
2a2a0f38 QN |
3541 | /* REG_XOP_TBM_01 */ |
3542 | { | |
3543 | { Bad_Opcode }, | |
c1dc7af5 JB |
3544 | { "blcfill", { { OP_LWP_E, 0 }, Edq }, 0 }, |
3545 | { "blsfill", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3546 | { "blcs", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3547 | { "tzmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3548 | { "blcic", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3549 | { "blsic", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3550 | { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
2a2a0f38 QN |
3551 | }, |
3552 | /* REG_XOP_TBM_02 */ | |
3553 | { | |
3554 | { Bad_Opcode }, | |
c1dc7af5 | 3555 | { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, |
2a2a0f38 QN |
3556 | { Bad_Opcode }, |
3557 | { Bad_Opcode }, | |
3558 | { Bad_Opcode }, | |
3559 | { Bad_Opcode }, | |
c1dc7af5 | 3560 | { "blci", { { OP_LWP_E, 0 }, Edq }, 0 }, |
2a2a0f38 | 3561 | }, |
ad692897 L |
3562 | |
3563 | #include "i386-dis-evex-reg.h" | |
4e7d34a6 L |
3564 | }; |
3565 | ||
1ceb70f8 L |
3566 | static const struct dis386 prefix_table[][4] = { |
3567 | /* PREFIX_90 */ | |
252b5132 | 3568 | { |
bf890a93 IT |
3569 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3570 | { "pause", { XX }, 0 }, | |
3571 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3572 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3573 | }, |
4e7d34a6 | 3574 | |
f9630fa6 | 3575 | /* PREFIX_0F01_REG_3_RM_1 */ |
a847e322 JB |
3576 | { |
3577 | { "vmmcall", { Skip_MODRM }, 0 }, | |
3578 | { "vmgexit", { Skip_MODRM }, 0 }, | |
d27c357a JB |
3579 | { Bad_Opcode }, |
3580 | { "vmgexit", { Skip_MODRM }, 0 }, | |
a847e322 JB |
3581 | }, |
3582 | ||
f8687e93 | 3583 | /* PREFIX_0F01_REG_5_MOD_0 */ |
603555e5 L |
3584 | { |
3585 | { Bad_Opcode }, | |
3586 | { "rstorssp", { Mq }, PREFIX_OPCODE }, | |
3587 | }, | |
3588 | ||
f8687e93 | 3589 | /* PREFIX_0F01_REG_5_MOD_3_RM_0 */ |
603555e5 | 3590 | { |
4b27d27c | 3591 | { "serialize", { Skip_MODRM }, PREFIX_OPCODE }, |
2234eee6 | 3592 | { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b | 3593 | { Bad_Opcode }, |
efe30057 | 3594 | { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b CL |
3595 | }, |
3596 | ||
3597 | /* PREFIX_0F01_REG_5_MOD_3_RM_1 */ | |
3598 | { | |
3599 | { Bad_Opcode }, | |
3600 | { Bad_Opcode }, | |
3601 | { Bad_Opcode }, | |
3602 | { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE }, | |
603555e5 L |
3603 | }, |
3604 | ||
f8687e93 | 3605 | /* PREFIX_0F01_REG_5_MOD_3_RM_2 */ |
603555e5 L |
3606 | { |
3607 | { Bad_Opcode }, | |
c2f76402 | 3608 | { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3609 | }, |
3610 | ||
267b8516 JB |
3611 | /* PREFIX_0F01_REG_7_MOD_3_RM_2 */ |
3612 | { | |
3613 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, | |
142861df | 3614 | { "mcommit", { Skip_MODRM }, 0 }, |
267b8516 JB |
3615 | }, |
3616 | ||
3617 | /* PREFIX_0F01_REG_7_MOD_3_RM_3 */ | |
3618 | { | |
7abb8d81 | 3619 | { "mwaitx", { { OP_Mwait, eBX_reg } }, 0 }, |
267b8516 JB |
3620 | }, |
3621 | ||
3233d7d0 IT |
3622 | /* PREFIX_0F09 */ |
3623 | { | |
3624 | { "wbinvd", { XX }, 0 }, | |
3625 | { "wbnoinvd", { XX }, 0 }, | |
3626 | }, | |
3627 | ||
1ceb70f8 | 3628 | /* PREFIX_0F10 */ |
cc0ec051 | 3629 | { |
507bd325 L |
3630 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3631 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3632 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3633 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3634 | }, |
4e7d34a6 | 3635 | |
1ceb70f8 | 3636 | /* PREFIX_0F11 */ |
30d1c836 | 3637 | { |
507bd325 L |
3638 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3639 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3640 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3641 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3642 | }, |
252b5132 | 3643 | |
1ceb70f8 | 3644 | /* PREFIX_0F12 */ |
c608c12e | 3645 | { |
1ceb70f8 | 3646 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 | 3647 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3648 | { MOD_TABLE (MOD_0F12_PREFIX_2) }, |
507bd325 | 3649 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, |
c608c12e | 3650 | }, |
4e7d34a6 | 3651 | |
1ceb70f8 | 3652 | /* PREFIX_0F16 */ |
c608c12e | 3653 | { |
1ceb70f8 | 3654 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 | 3655 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3656 | { MOD_TABLE (MOD_0F16_PREFIX_2) }, |
c608c12e | 3657 | }, |
4e7d34a6 | 3658 | |
7e8b059b L |
3659 | /* PREFIX_0F1A */ |
3660 | { | |
3661 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3662 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3663 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3664 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3665 | }, |
3666 | ||
3667 | /* PREFIX_0F1B */ | |
3668 | { | |
3669 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3670 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
9f79e886 | 3671 | { "bndmov", { EbndS, Gbnd }, 0 }, |
bf890a93 | 3672 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
7e8b059b L |
3673 | }, |
3674 | ||
c48935d7 IT |
3675 | /* PREFIX_0F1C */ |
3676 | { | |
3677 | { MOD_TABLE (MOD_0F1C_PREFIX_0) }, | |
3678 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3679 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3680 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3681 | }, | |
3682 | ||
603555e5 L |
3683 | /* PREFIX_0F1E */ |
3684 | { | |
3685 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3686 | { MOD_TABLE (MOD_0F1E_PREFIX_1) }, | |
3687 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3688 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3689 | }, | |
3690 | ||
1ceb70f8 | 3691 | /* PREFIX_0F2A */ |
c608c12e | 3692 | { |
507bd325 | 3693 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
e1a1babd | 3694 | { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE }, |
507bd325 | 3695 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, |
e1a1babd | 3696 | { "cvtsi2sd%LQ", { XM, Edq }, 0 }, |
c608c12e | 3697 | }, |
4e7d34a6 | 3698 | |
1ceb70f8 | 3699 | /* PREFIX_0F2B */ |
c608c12e | 3700 | { |
75c135a8 L |
3701 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3702 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3703 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3704 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3705 | }, |
4e7d34a6 | 3706 | |
1ceb70f8 | 3707 | /* PREFIX_0F2C */ |
c608c12e | 3708 | { |
507bd325 | 3709 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3710 | { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3711 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3712 | { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3713 | }, |
4e7d34a6 | 3714 | |
1ceb70f8 | 3715 | /* PREFIX_0F2D */ |
c608c12e | 3716 | { |
507bd325 | 3717 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3718 | { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3719 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3720 | { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3721 | }, |
4e7d34a6 | 3722 | |
1ceb70f8 | 3723 | /* PREFIX_0F2E */ |
c608c12e | 3724 | { |
bf890a93 | 3725 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3726 | { Bad_Opcode }, |
bf890a93 | 3727 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3728 | }, |
4e7d34a6 | 3729 | |
1ceb70f8 | 3730 | /* PREFIX_0F2F */ |
c608c12e | 3731 | { |
bf890a93 | 3732 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3733 | { Bad_Opcode }, |
bf890a93 | 3734 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3735 | }, |
4e7d34a6 | 3736 | |
1ceb70f8 | 3737 | /* PREFIX_0F51 */ |
c608c12e | 3738 | { |
507bd325 L |
3739 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3740 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3741 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3742 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3743 | }, |
4e7d34a6 | 3744 | |
1ceb70f8 | 3745 | /* PREFIX_0F52 */ |
c608c12e | 3746 | { |
507bd325 L |
3747 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3748 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3749 | }, |
4e7d34a6 | 3750 | |
1ceb70f8 | 3751 | /* PREFIX_0F53 */ |
c608c12e | 3752 | { |
507bd325 L |
3753 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3754 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3755 | }, |
4e7d34a6 | 3756 | |
1ceb70f8 | 3757 | /* PREFIX_0F58 */ |
c608c12e | 3758 | { |
507bd325 L |
3759 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3760 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
3761 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
3762 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3763 | }, |
4e7d34a6 | 3764 | |
1ceb70f8 | 3765 | /* PREFIX_0F59 */ |
c608c12e | 3766 | { |
507bd325 L |
3767 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3768 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
3769 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
3770 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3771 | }, |
4e7d34a6 | 3772 | |
1ceb70f8 | 3773 | /* PREFIX_0F5A */ |
041bd2e0 | 3774 | { |
507bd325 L |
3775 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3776 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
3777 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
3778 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3779 | }, |
4e7d34a6 | 3780 | |
1ceb70f8 | 3781 | /* PREFIX_0F5B */ |
041bd2e0 | 3782 | { |
507bd325 L |
3783 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3784 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3785 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 3786 | }, |
4e7d34a6 | 3787 | |
1ceb70f8 | 3788 | /* PREFIX_0F5C */ |
041bd2e0 | 3789 | { |
507bd325 L |
3790 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3791 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
3792 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
3793 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3794 | }, |
4e7d34a6 | 3795 | |
1ceb70f8 | 3796 | /* PREFIX_0F5D */ |
041bd2e0 | 3797 | { |
507bd325 L |
3798 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3799 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
3800 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
3801 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3802 | }, |
4e7d34a6 | 3803 | |
1ceb70f8 | 3804 | /* PREFIX_0F5E */ |
041bd2e0 | 3805 | { |
507bd325 L |
3806 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3807 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
3808 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
3809 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3810 | }, |
4e7d34a6 | 3811 | |
1ceb70f8 | 3812 | /* PREFIX_0F5F */ |
041bd2e0 | 3813 | { |
507bd325 L |
3814 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3815 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
3816 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
3817 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3818 | }, |
4e7d34a6 | 3819 | |
1ceb70f8 | 3820 | /* PREFIX_0F60 */ |
041bd2e0 | 3821 | { |
507bd325 | 3822 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3823 | { Bad_Opcode }, |
507bd325 | 3824 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3825 | }, |
4e7d34a6 | 3826 | |
1ceb70f8 | 3827 | /* PREFIX_0F61 */ |
041bd2e0 | 3828 | { |
507bd325 | 3829 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3830 | { Bad_Opcode }, |
507bd325 | 3831 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3832 | }, |
4e7d34a6 | 3833 | |
1ceb70f8 | 3834 | /* PREFIX_0F62 */ |
041bd2e0 | 3835 | { |
507bd325 | 3836 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3837 | { Bad_Opcode }, |
507bd325 | 3838 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3839 | }, |
4e7d34a6 | 3840 | |
1ceb70f8 | 3841 | /* PREFIX_0F6C */ |
041bd2e0 | 3842 | { |
592d1631 L |
3843 | { Bad_Opcode }, |
3844 | { Bad_Opcode }, | |
507bd325 | 3845 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
0f17484f | 3846 | }, |
4e7d34a6 | 3847 | |
1ceb70f8 | 3848 | /* PREFIX_0F6D */ |
0f17484f | 3849 | { |
592d1631 L |
3850 | { Bad_Opcode }, |
3851 | { Bad_Opcode }, | |
507bd325 | 3852 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
041bd2e0 | 3853 | }, |
4e7d34a6 | 3854 | |
1ceb70f8 | 3855 | /* PREFIX_0F6F */ |
ca164297 | 3856 | { |
507bd325 L |
3857 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3858 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
3859 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3860 | }, |
4e7d34a6 | 3861 | |
1ceb70f8 | 3862 | /* PREFIX_0F70 */ |
4e7d34a6 | 3863 | { |
507bd325 L |
3864 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3865 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
3866 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
3867 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
3868 | }, |
3869 | ||
92fddf8e L |
3870 | /* PREFIX_0F73_REG_3 */ |
3871 | { | |
592d1631 L |
3872 | { Bad_Opcode }, |
3873 | { Bad_Opcode }, | |
bf890a93 | 3874 | { "psrldq", { XS, Ib }, 0 }, |
92fddf8e L |
3875 | }, |
3876 | ||
3877 | /* PREFIX_0F73_REG_7 */ | |
3878 | { | |
592d1631 L |
3879 | { Bad_Opcode }, |
3880 | { Bad_Opcode }, | |
bf890a93 | 3881 | { "pslldq", { XS, Ib }, 0 }, |
92fddf8e L |
3882 | }, |
3883 | ||
1ceb70f8 | 3884 | /* PREFIX_0F78 */ |
4e7d34a6 | 3885 | { |
bf890a93 | 3886 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 3887 | { Bad_Opcode }, |
bf890a93 IT |
3888 | {"extrq", { XS, Ib, Ib }, 0 }, |
3889 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
3890 | }, |
3891 | ||
1ceb70f8 | 3892 | /* PREFIX_0F79 */ |
4e7d34a6 | 3893 | { |
bf890a93 | 3894 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 3895 | { Bad_Opcode }, |
bf890a93 IT |
3896 | {"extrq", { XM, XS }, 0 }, |
3897 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
3898 | }, |
3899 | ||
1ceb70f8 | 3900 | /* PREFIX_0F7C */ |
ca164297 | 3901 | { |
592d1631 L |
3902 | { Bad_Opcode }, |
3903 | { Bad_Opcode }, | |
507bd325 L |
3904 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
3905 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3906 | }, |
4e7d34a6 | 3907 | |
1ceb70f8 | 3908 | /* PREFIX_0F7D */ |
ca164297 | 3909 | { |
592d1631 L |
3910 | { Bad_Opcode }, |
3911 | { Bad_Opcode }, | |
507bd325 L |
3912 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
3913 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3914 | }, |
4e7d34a6 | 3915 | |
1ceb70f8 | 3916 | /* PREFIX_0F7E */ |
ca164297 | 3917 | { |
507bd325 L |
3918 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
3919 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
3920 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 3921 | }, |
4e7d34a6 | 3922 | |
1ceb70f8 | 3923 | /* PREFIX_0F7F */ |
ca164297 | 3924 | { |
507bd325 L |
3925 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
3926 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
3927 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 3928 | }, |
4e7d34a6 | 3929 | |
f8687e93 | 3930 | /* PREFIX_0FAE_REG_0_MOD_3 */ |
c7b8aa3a L |
3931 | { |
3932 | { Bad_Opcode }, | |
bf890a93 | 3933 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3934 | }, |
3935 | ||
f8687e93 | 3936 | /* PREFIX_0FAE_REG_1_MOD_3 */ |
c7b8aa3a L |
3937 | { |
3938 | { Bad_Opcode }, | |
bf890a93 | 3939 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3940 | }, |
3941 | ||
f8687e93 | 3942 | /* PREFIX_0FAE_REG_2_MOD_3 */ |
c7b8aa3a L |
3943 | { |
3944 | { Bad_Opcode }, | |
bf890a93 | 3945 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3946 | }, |
3947 | ||
f8687e93 | 3948 | /* PREFIX_0FAE_REG_3_MOD_3 */ |
c7b8aa3a L |
3949 | { |
3950 | { Bad_Opcode }, | |
bf890a93 | 3951 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3952 | }, |
3953 | ||
f8687e93 | 3954 | /* PREFIX_0FAE_REG_4_MOD_0 */ |
6b40c462 L |
3955 | { |
3956 | { "xsave", { FXSAVE }, 0 }, | |
3957 | { "ptwrite%LQ", { Edq }, 0 }, | |
3958 | }, | |
3959 | ||
f8687e93 | 3960 | /* PREFIX_0FAE_REG_4_MOD_3 */ |
6b40c462 L |
3961 | { |
3962 | { Bad_Opcode }, | |
3963 | { "ptwrite%LQ", { Edq }, 0 }, | |
3964 | }, | |
3965 | ||
f8687e93 | 3966 | /* PREFIX_0FAE_REG_5_MOD_0 */ |
603555e5 L |
3967 | { |
3968 | { "xrstor", { FXSAVE }, PREFIX_OPCODE }, | |
2234eee6 L |
3969 | }, |
3970 | ||
f8687e93 | 3971 | /* PREFIX_0FAE_REG_5_MOD_3 */ |
2234eee6 L |
3972 | { |
3973 | { "lfence", { Skip_MODRM }, 0 }, | |
3974 | { "incsspK", { Rdq }, PREFIX_OPCODE }, | |
603555e5 L |
3975 | }, |
3976 | ||
f8687e93 | 3977 | /* PREFIX_0FAE_REG_6_MOD_0 */ |
c5e7287a | 3978 | { |
603555e5 L |
3979 | { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, |
3980 | { "clrssbsy", { Mq }, PREFIX_OPCODE }, | |
3981 | { "clwb", { Mb }, PREFIX_OPCODE }, | |
c5e7287a IT |
3982 | }, |
3983 | ||
f8687e93 | 3984 | /* PREFIX_0FAE_REG_6_MOD_3 */ |
de89d0a3 | 3985 | { |
f8687e93 | 3986 | { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) }, |
de89d0a3 | 3987 | { "umonitor", { Eva }, PREFIX_OPCODE }, |
ae1d3843 L |
3988 | { "tpause", { Edq }, PREFIX_OPCODE }, |
3989 | { "umwait", { Edq }, PREFIX_OPCODE }, | |
de89d0a3 IT |
3990 | }, |
3991 | ||
f8687e93 | 3992 | /* PREFIX_0FAE_REG_7_MOD_0 */ |
963f3586 | 3993 | { |
bf890a93 | 3994 | { "clflush", { Mb }, 0 }, |
963f3586 | 3995 | { Bad_Opcode }, |
bf890a93 | 3996 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
3997 | }, |
3998 | ||
1ceb70f8 | 3999 | /* PREFIX_0FB8 */ |
ca164297 | 4000 | { |
592d1631 | 4001 | { Bad_Opcode }, |
bf890a93 | 4002 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 4003 | }, |
4e7d34a6 | 4004 | |
f12dc422 L |
4005 | /* PREFIX_0FBC */ |
4006 | { | |
bf890a93 IT |
4007 | { "bsfS", { Gv, Ev }, 0 }, |
4008 | { "tzcntS", { Gv, Ev }, 0 }, | |
4009 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
4010 | }, |
4011 | ||
1ceb70f8 | 4012 | /* PREFIX_0FBD */ |
050dfa73 | 4013 | { |
bf890a93 IT |
4014 | { "bsrS", { Gv, Ev }, 0 }, |
4015 | { "lzcntS", { Gv, Ev }, 0 }, | |
4016 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
4017 | }, |
4018 | ||
1ceb70f8 | 4019 | /* PREFIX_0FC2 */ |
050dfa73 | 4020 | { |
507bd325 L |
4021 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
4022 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
4023 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
4024 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 4025 | }, |
246c51aa | 4026 | |
f8687e93 | 4027 | /* PREFIX_0FC3_MOD_0 */ |
4ee52178 | 4028 | { |
e1a1babd | 4029 | { "movntiS", { Edq, Gdq }, PREFIX_OPCODE }, |
4ee52178 L |
4030 | }, |
4031 | ||
f8687e93 | 4032 | /* PREFIX_0FC7_REG_6_MOD_0 */ |
92fddf8e | 4033 | { |
bf890a93 IT |
4034 | { "vmptrld",{ Mq }, 0 }, |
4035 | { "vmxon", { Mq }, 0 }, | |
4036 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
4037 | }, |
4038 | ||
f8687e93 | 4039 | /* PREFIX_0FC7_REG_6_MOD_3 */ |
f24bcbaa L |
4040 | { |
4041 | { "rdrand", { Ev }, 0 }, | |
4042 | { Bad_Opcode }, | |
4043 | { "rdrand", { Ev }, 0 } | |
4044 | }, | |
4045 | ||
f8687e93 | 4046 | /* PREFIX_0FC7_REG_7_MOD_3 */ |
f24bcbaa L |
4047 | { |
4048 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 4049 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
4050 | { "rdseed", { Ev }, 0 }, |
4051 | }, | |
4052 | ||
1ceb70f8 | 4053 | /* PREFIX_0FD0 */ |
050dfa73 | 4054 | { |
592d1631 L |
4055 | { Bad_Opcode }, |
4056 | { Bad_Opcode }, | |
bf890a93 IT |
4057 | { "addsubpd", { XM, EXx }, 0 }, |
4058 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 4059 | }, |
050dfa73 | 4060 | |
1ceb70f8 | 4061 | /* PREFIX_0FD6 */ |
050dfa73 | 4062 | { |
592d1631 | 4063 | { Bad_Opcode }, |
bf890a93 IT |
4064 | { "movq2dq",{ XM, MS }, 0 }, |
4065 | { "movq", { EXqS, XM }, 0 }, | |
4066 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
4067 | }, |
4068 | ||
1ceb70f8 | 4069 | /* PREFIX_0FE6 */ |
7918206c | 4070 | { |
592d1631 | 4071 | { Bad_Opcode }, |
507bd325 L |
4072 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
4073 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
4074 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 4075 | }, |
8b38ad71 | 4076 | |
1ceb70f8 | 4077 | /* PREFIX_0FE7 */ |
8b38ad71 | 4078 | { |
507bd325 | 4079 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 4080 | { Bad_Opcode }, |
75c135a8 | 4081 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
4082 | }, |
4083 | ||
1ceb70f8 | 4084 | /* PREFIX_0FF0 */ |
4e7d34a6 | 4085 | { |
592d1631 L |
4086 | { Bad_Opcode }, |
4087 | { Bad_Opcode }, | |
4088 | { Bad_Opcode }, | |
1ceb70f8 | 4089 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
4090 | }, |
4091 | ||
1ceb70f8 | 4092 | /* PREFIX_0FF7 */ |
4e7d34a6 | 4093 | { |
507bd325 | 4094 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 4095 | { Bad_Opcode }, |
507bd325 | 4096 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 4097 | }, |
42903f7f | 4098 | |
1ceb70f8 | 4099 | /* PREFIX_0F3810 */ |
42903f7f | 4100 | { |
592d1631 L |
4101 | { Bad_Opcode }, |
4102 | { Bad_Opcode }, | |
507bd325 | 4103 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4104 | }, |
4105 | ||
1ceb70f8 | 4106 | /* PREFIX_0F3814 */ |
42903f7f | 4107 | { |
592d1631 L |
4108 | { Bad_Opcode }, |
4109 | { Bad_Opcode }, | |
507bd325 | 4110 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4111 | }, |
4112 | ||
1ceb70f8 | 4113 | /* PREFIX_0F3815 */ |
42903f7f | 4114 | { |
592d1631 L |
4115 | { Bad_Opcode }, |
4116 | { Bad_Opcode }, | |
507bd325 | 4117 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4118 | }, |
4119 | ||
1ceb70f8 | 4120 | /* PREFIX_0F3817 */ |
42903f7f | 4121 | { |
592d1631 L |
4122 | { Bad_Opcode }, |
4123 | { Bad_Opcode }, | |
507bd325 | 4124 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4125 | }, |
4126 | ||
1ceb70f8 | 4127 | /* PREFIX_0F3820 */ |
42903f7f | 4128 | { |
592d1631 L |
4129 | { Bad_Opcode }, |
4130 | { Bad_Opcode }, | |
507bd325 | 4131 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4132 | }, |
4133 | ||
1ceb70f8 | 4134 | /* PREFIX_0F3821 */ |
42903f7f | 4135 | { |
592d1631 L |
4136 | { Bad_Opcode }, |
4137 | { Bad_Opcode }, | |
507bd325 | 4138 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4139 | }, |
4140 | ||
1ceb70f8 | 4141 | /* PREFIX_0F3822 */ |
42903f7f | 4142 | { |
592d1631 L |
4143 | { Bad_Opcode }, |
4144 | { Bad_Opcode }, | |
507bd325 | 4145 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4146 | }, |
4147 | ||
1ceb70f8 | 4148 | /* PREFIX_0F3823 */ |
42903f7f | 4149 | { |
592d1631 L |
4150 | { Bad_Opcode }, |
4151 | { Bad_Opcode }, | |
507bd325 | 4152 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4153 | }, |
4154 | ||
1ceb70f8 | 4155 | /* PREFIX_0F3824 */ |
42903f7f | 4156 | { |
592d1631 L |
4157 | { Bad_Opcode }, |
4158 | { Bad_Opcode }, | |
507bd325 | 4159 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4160 | }, |
4161 | ||
1ceb70f8 | 4162 | /* PREFIX_0F3825 */ |
42903f7f | 4163 | { |
592d1631 L |
4164 | { Bad_Opcode }, |
4165 | { Bad_Opcode }, | |
507bd325 | 4166 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4167 | }, |
4168 | ||
1ceb70f8 | 4169 | /* PREFIX_0F3828 */ |
42903f7f | 4170 | { |
592d1631 L |
4171 | { Bad_Opcode }, |
4172 | { Bad_Opcode }, | |
507bd325 | 4173 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4174 | }, |
4175 | ||
1ceb70f8 | 4176 | /* PREFIX_0F3829 */ |
42903f7f | 4177 | { |
592d1631 L |
4178 | { Bad_Opcode }, |
4179 | { Bad_Opcode }, | |
507bd325 | 4180 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4181 | }, |
4182 | ||
1ceb70f8 | 4183 | /* PREFIX_0F382A */ |
42903f7f | 4184 | { |
592d1631 L |
4185 | { Bad_Opcode }, |
4186 | { Bad_Opcode }, | |
75c135a8 | 4187 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
4188 | }, |
4189 | ||
1ceb70f8 | 4190 | /* PREFIX_0F382B */ |
42903f7f | 4191 | { |
592d1631 L |
4192 | { Bad_Opcode }, |
4193 | { Bad_Opcode }, | |
507bd325 | 4194 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4195 | }, |
4196 | ||
1ceb70f8 | 4197 | /* PREFIX_0F3830 */ |
42903f7f | 4198 | { |
592d1631 L |
4199 | { Bad_Opcode }, |
4200 | { Bad_Opcode }, | |
507bd325 | 4201 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4202 | }, |
4203 | ||
1ceb70f8 | 4204 | /* PREFIX_0F3831 */ |
42903f7f | 4205 | { |
592d1631 L |
4206 | { Bad_Opcode }, |
4207 | { Bad_Opcode }, | |
507bd325 | 4208 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4209 | }, |
4210 | ||
1ceb70f8 | 4211 | /* PREFIX_0F3832 */ |
42903f7f | 4212 | { |
592d1631 L |
4213 | { Bad_Opcode }, |
4214 | { Bad_Opcode }, | |
507bd325 | 4215 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4216 | }, |
4217 | ||
1ceb70f8 | 4218 | /* PREFIX_0F3833 */ |
42903f7f | 4219 | { |
592d1631 L |
4220 | { Bad_Opcode }, |
4221 | { Bad_Opcode }, | |
507bd325 | 4222 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4223 | }, |
4224 | ||
1ceb70f8 | 4225 | /* PREFIX_0F3834 */ |
42903f7f | 4226 | { |
592d1631 L |
4227 | { Bad_Opcode }, |
4228 | { Bad_Opcode }, | |
507bd325 | 4229 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4230 | }, |
4231 | ||
1ceb70f8 | 4232 | /* PREFIX_0F3835 */ |
42903f7f | 4233 | { |
592d1631 L |
4234 | { Bad_Opcode }, |
4235 | { Bad_Opcode }, | |
507bd325 | 4236 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4237 | }, |
4238 | ||
1ceb70f8 | 4239 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4240 | { |
592d1631 L |
4241 | { Bad_Opcode }, |
4242 | { Bad_Opcode }, | |
507bd325 | 4243 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
4e7d34a6 L |
4244 | }, |
4245 | ||
1ceb70f8 | 4246 | /* PREFIX_0F3838 */ |
42903f7f | 4247 | { |
592d1631 L |
4248 | { Bad_Opcode }, |
4249 | { Bad_Opcode }, | |
507bd325 | 4250 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4251 | }, |
4252 | ||
1ceb70f8 | 4253 | /* PREFIX_0F3839 */ |
42903f7f | 4254 | { |
592d1631 L |
4255 | { Bad_Opcode }, |
4256 | { Bad_Opcode }, | |
507bd325 | 4257 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4258 | }, |
4259 | ||
1ceb70f8 | 4260 | /* PREFIX_0F383A */ |
42903f7f | 4261 | { |
592d1631 L |
4262 | { Bad_Opcode }, |
4263 | { Bad_Opcode }, | |
507bd325 | 4264 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4265 | }, |
4266 | ||
1ceb70f8 | 4267 | /* PREFIX_0F383B */ |
42903f7f | 4268 | { |
592d1631 L |
4269 | { Bad_Opcode }, |
4270 | { Bad_Opcode }, | |
507bd325 | 4271 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4272 | }, |
4273 | ||
1ceb70f8 | 4274 | /* PREFIX_0F383C */ |
42903f7f | 4275 | { |
592d1631 L |
4276 | { Bad_Opcode }, |
4277 | { Bad_Opcode }, | |
507bd325 | 4278 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4279 | }, |
4280 | ||
1ceb70f8 | 4281 | /* PREFIX_0F383D */ |
42903f7f | 4282 | { |
592d1631 L |
4283 | { Bad_Opcode }, |
4284 | { Bad_Opcode }, | |
507bd325 | 4285 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4286 | }, |
4287 | ||
1ceb70f8 | 4288 | /* PREFIX_0F383E */ |
42903f7f | 4289 | { |
592d1631 L |
4290 | { Bad_Opcode }, |
4291 | { Bad_Opcode }, | |
507bd325 | 4292 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4293 | }, |
4294 | ||
1ceb70f8 | 4295 | /* PREFIX_0F383F */ |
42903f7f | 4296 | { |
592d1631 L |
4297 | { Bad_Opcode }, |
4298 | { Bad_Opcode }, | |
507bd325 | 4299 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4300 | }, |
4301 | ||
1ceb70f8 | 4302 | /* PREFIX_0F3840 */ |
42903f7f | 4303 | { |
592d1631 L |
4304 | { Bad_Opcode }, |
4305 | { Bad_Opcode }, | |
507bd325 | 4306 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4307 | }, |
4308 | ||
1ceb70f8 | 4309 | /* PREFIX_0F3841 */ |
42903f7f | 4310 | { |
592d1631 L |
4311 | { Bad_Opcode }, |
4312 | { Bad_Opcode }, | |
507bd325 | 4313 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4314 | }, |
4315 | ||
f1f8f695 L |
4316 | /* PREFIX_0F3880 */ |
4317 | { | |
592d1631 L |
4318 | { Bad_Opcode }, |
4319 | { Bad_Opcode }, | |
507bd325 | 4320 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4321 | }, |
4322 | ||
4323 | /* PREFIX_0F3881 */ | |
4324 | { | |
592d1631 L |
4325 | { Bad_Opcode }, |
4326 | { Bad_Opcode }, | |
507bd325 | 4327 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4328 | }, |
4329 | ||
6c30d220 L |
4330 | /* PREFIX_0F3882 */ |
4331 | { | |
4332 | { Bad_Opcode }, | |
4333 | { Bad_Opcode }, | |
507bd325 | 4334 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
6c30d220 L |
4335 | }, |
4336 | ||
a0046408 L |
4337 | /* PREFIX_0F38C8 */ |
4338 | { | |
507bd325 | 4339 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4340 | }, |
4341 | ||
4342 | /* PREFIX_0F38C9 */ | |
4343 | { | |
507bd325 | 4344 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4345 | }, |
4346 | ||
4347 | /* PREFIX_0F38CA */ | |
4348 | { | |
507bd325 | 4349 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4350 | }, |
4351 | ||
4352 | /* PREFIX_0F38CB */ | |
4353 | { | |
507bd325 | 4354 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
a0046408 L |
4355 | }, |
4356 | ||
4357 | /* PREFIX_0F38CC */ | |
4358 | { | |
507bd325 | 4359 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4360 | }, |
4361 | ||
4362 | /* PREFIX_0F38CD */ | |
4363 | { | |
507bd325 | 4364 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4365 | }, |
4366 | ||
48521003 IT |
4367 | /* PREFIX_0F38CF */ |
4368 | { | |
4369 | { Bad_Opcode }, | |
4370 | { Bad_Opcode }, | |
4371 | { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE }, | |
4372 | }, | |
4373 | ||
c0f3af97 L |
4374 | /* PREFIX_0F38DB */ |
4375 | { | |
592d1631 L |
4376 | { Bad_Opcode }, |
4377 | { Bad_Opcode }, | |
507bd325 | 4378 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4379 | }, |
4380 | ||
4381 | /* PREFIX_0F38DC */ | |
4382 | { | |
592d1631 L |
4383 | { Bad_Opcode }, |
4384 | { Bad_Opcode }, | |
507bd325 | 4385 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4386 | }, |
4387 | ||
4388 | /* PREFIX_0F38DD */ | |
4389 | { | |
592d1631 L |
4390 | { Bad_Opcode }, |
4391 | { Bad_Opcode }, | |
507bd325 | 4392 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4393 | }, |
4394 | ||
4395 | /* PREFIX_0F38DE */ | |
4396 | { | |
592d1631 L |
4397 | { Bad_Opcode }, |
4398 | { Bad_Opcode }, | |
507bd325 | 4399 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4400 | }, |
4401 | ||
4402 | /* PREFIX_0F38DF */ | |
4403 | { | |
592d1631 L |
4404 | { Bad_Opcode }, |
4405 | { Bad_Opcode }, | |
507bd325 | 4406 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4407 | }, |
4408 | ||
1ceb70f8 | 4409 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4410 | { |
507bd325 | 4411 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
592d1631 | 4412 | { Bad_Opcode }, |
507bd325 L |
4413 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4414 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4415 | }, |
4416 | ||
1ceb70f8 | 4417 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4418 | { |
507bd325 | 4419 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
592d1631 | 4420 | { Bad_Opcode }, |
507bd325 L |
4421 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4422 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4423 | }, |
4424 | ||
603555e5 | 4425 | /* PREFIX_0F38F5 */ |
e2e1fcde L |
4426 | { |
4427 | { Bad_Opcode }, | |
603555e5 L |
4428 | { Bad_Opcode }, |
4429 | { MOD_TABLE (MOD_0F38F5_PREFIX_2) }, | |
4430 | }, | |
4431 | ||
4432 | /* PREFIX_0F38F6 */ | |
4433 | { | |
4434 | { MOD_TABLE (MOD_0F38F6_PREFIX_0) }, | |
507bd325 L |
4435 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4436 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
4437 | { Bad_Opcode }, |
4438 | }, | |
4439 | ||
c0a30a9f L |
4440 | /* PREFIX_0F38F8 */ |
4441 | { | |
4442 | { Bad_Opcode }, | |
5d79adc4 | 4443 | { MOD_TABLE (MOD_0F38F8_PREFIX_1) }, |
c0a30a9f | 4444 | { MOD_TABLE (MOD_0F38F8_PREFIX_2) }, |
5d79adc4 | 4445 | { MOD_TABLE (MOD_0F38F8_PREFIX_3) }, |
c0a30a9f L |
4446 | }, |
4447 | ||
4448 | /* PREFIX_0F38F9 */ | |
4449 | { | |
4450 | { MOD_TABLE (MOD_0F38F9_PREFIX_0) }, | |
4451 | }, | |
4452 | ||
1ceb70f8 | 4453 | /* PREFIX_0F3A08 */ |
42903f7f | 4454 | { |
592d1631 L |
4455 | { Bad_Opcode }, |
4456 | { Bad_Opcode }, | |
507bd325 | 4457 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4458 | }, |
4459 | ||
1ceb70f8 | 4460 | /* PREFIX_0F3A09 */ |
42903f7f | 4461 | { |
592d1631 L |
4462 | { Bad_Opcode }, |
4463 | { Bad_Opcode }, | |
507bd325 | 4464 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4465 | }, |
4466 | ||
1ceb70f8 | 4467 | /* PREFIX_0F3A0A */ |
42903f7f | 4468 | { |
592d1631 L |
4469 | { Bad_Opcode }, |
4470 | { Bad_Opcode }, | |
507bd325 | 4471 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4472 | }, |
4473 | ||
1ceb70f8 | 4474 | /* PREFIX_0F3A0B */ |
42903f7f | 4475 | { |
592d1631 L |
4476 | { Bad_Opcode }, |
4477 | { Bad_Opcode }, | |
507bd325 | 4478 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4479 | }, |
4480 | ||
1ceb70f8 | 4481 | /* PREFIX_0F3A0C */ |
42903f7f | 4482 | { |
592d1631 L |
4483 | { Bad_Opcode }, |
4484 | { Bad_Opcode }, | |
507bd325 | 4485 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4486 | }, |
4487 | ||
1ceb70f8 | 4488 | /* PREFIX_0F3A0D */ |
42903f7f | 4489 | { |
592d1631 L |
4490 | { Bad_Opcode }, |
4491 | { Bad_Opcode }, | |
507bd325 | 4492 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4493 | }, |
4494 | ||
1ceb70f8 | 4495 | /* PREFIX_0F3A0E */ |
42903f7f | 4496 | { |
592d1631 L |
4497 | { Bad_Opcode }, |
4498 | { Bad_Opcode }, | |
507bd325 | 4499 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4500 | }, |
4501 | ||
1ceb70f8 | 4502 | /* PREFIX_0F3A14 */ |
42903f7f | 4503 | { |
592d1631 L |
4504 | { Bad_Opcode }, |
4505 | { Bad_Opcode }, | |
507bd325 | 4506 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4507 | }, |
4508 | ||
1ceb70f8 | 4509 | /* PREFIX_0F3A15 */ |
42903f7f | 4510 | { |
592d1631 L |
4511 | { Bad_Opcode }, |
4512 | { Bad_Opcode }, | |
507bd325 | 4513 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4514 | }, |
4515 | ||
1ceb70f8 | 4516 | /* PREFIX_0F3A16 */ |
42903f7f | 4517 | { |
592d1631 L |
4518 | { Bad_Opcode }, |
4519 | { Bad_Opcode }, | |
507bd325 | 4520 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4521 | }, |
4522 | ||
1ceb70f8 | 4523 | /* PREFIX_0F3A17 */ |
42903f7f | 4524 | { |
592d1631 L |
4525 | { Bad_Opcode }, |
4526 | { Bad_Opcode }, | |
507bd325 | 4527 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4528 | }, |
4529 | ||
1ceb70f8 | 4530 | /* PREFIX_0F3A20 */ |
42903f7f | 4531 | { |
592d1631 L |
4532 | { Bad_Opcode }, |
4533 | { Bad_Opcode }, | |
507bd325 | 4534 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4535 | }, |
4536 | ||
1ceb70f8 | 4537 | /* PREFIX_0F3A21 */ |
42903f7f | 4538 | { |
592d1631 L |
4539 | { Bad_Opcode }, |
4540 | { Bad_Opcode }, | |
507bd325 | 4541 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4542 | }, |
4543 | ||
1ceb70f8 | 4544 | /* PREFIX_0F3A22 */ |
42903f7f | 4545 | { |
592d1631 L |
4546 | { Bad_Opcode }, |
4547 | { Bad_Opcode }, | |
507bd325 | 4548 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4549 | }, |
4550 | ||
1ceb70f8 | 4551 | /* PREFIX_0F3A40 */ |
42903f7f | 4552 | { |
592d1631 L |
4553 | { Bad_Opcode }, |
4554 | { Bad_Opcode }, | |
507bd325 | 4555 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4556 | }, |
4557 | ||
1ceb70f8 | 4558 | /* PREFIX_0F3A41 */ |
42903f7f | 4559 | { |
592d1631 L |
4560 | { Bad_Opcode }, |
4561 | { Bad_Opcode }, | |
507bd325 | 4562 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4563 | }, |
4564 | ||
1ceb70f8 | 4565 | /* PREFIX_0F3A42 */ |
42903f7f | 4566 | { |
592d1631 L |
4567 | { Bad_Opcode }, |
4568 | { Bad_Opcode }, | |
507bd325 | 4569 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f | 4570 | }, |
381d071f | 4571 | |
c0f3af97 L |
4572 | /* PREFIX_0F3A44 */ |
4573 | { | |
592d1631 L |
4574 | { Bad_Opcode }, |
4575 | { Bad_Opcode }, | |
507bd325 | 4576 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
c0f3af97 L |
4577 | }, |
4578 | ||
1ceb70f8 | 4579 | /* PREFIX_0F3A60 */ |
381d071f | 4580 | { |
592d1631 L |
4581 | { Bad_Opcode }, |
4582 | { Bad_Opcode }, | |
15c7c1d8 | 4583 | { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4584 | }, |
4585 | ||
1ceb70f8 | 4586 | /* PREFIX_0F3A61 */ |
381d071f | 4587 | { |
592d1631 L |
4588 | { Bad_Opcode }, |
4589 | { Bad_Opcode }, | |
15c7c1d8 | 4590 | { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4591 | }, |
4592 | ||
1ceb70f8 | 4593 | /* PREFIX_0F3A62 */ |
381d071f | 4594 | { |
592d1631 L |
4595 | { Bad_Opcode }, |
4596 | { Bad_Opcode }, | |
507bd325 | 4597 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4598 | }, |
4599 | ||
1ceb70f8 | 4600 | /* PREFIX_0F3A63 */ |
381d071f | 4601 | { |
592d1631 L |
4602 | { Bad_Opcode }, |
4603 | { Bad_Opcode }, | |
507bd325 | 4604 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f | 4605 | }, |
09a2c6cf | 4606 | |
a0046408 L |
4607 | /* PREFIX_0F3ACC */ |
4608 | { | |
507bd325 | 4609 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
a0046408 L |
4610 | }, |
4611 | ||
48521003 IT |
4612 | /* PREFIX_0F3ACE */ |
4613 | { | |
4614 | { Bad_Opcode }, | |
4615 | { Bad_Opcode }, | |
4616 | { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4617 | }, | |
4618 | ||
4619 | /* PREFIX_0F3ACF */ | |
4620 | { | |
4621 | { Bad_Opcode }, | |
4622 | { Bad_Opcode }, | |
4623 | { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4624 | }, | |
4625 | ||
c0f3af97 | 4626 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4627 | { |
592d1631 L |
4628 | { Bad_Opcode }, |
4629 | { Bad_Opcode }, | |
507bd325 | 4630 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
09a2c6cf L |
4631 | }, |
4632 | ||
592a252b | 4633 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4634 | { |
ec6f095a L |
4635 | { "vmovups", { XM, EXx }, 0 }, |
4636 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, | |
4637 | { "vmovupd", { XM, EXx }, 0 }, | |
4638 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, | |
09a2c6cf L |
4639 | }, |
4640 | ||
592a252b | 4641 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4642 | { |
ec6f095a L |
4643 | { "vmovups", { EXxS, XM }, 0 }, |
4644 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, | |
4645 | { "vmovupd", { EXxS, XM }, 0 }, | |
4646 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, | |
09a2c6cf L |
4647 | }, |
4648 | ||
592a252b | 4649 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4650 | { |
592a252b | 4651 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
ec6f095a | 4652 | { "vmovsldup", { XM, EXx }, 0 }, |
18897deb | 4653 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) }, |
ec6f095a | 4654 | { "vmovddup", { XM, EXymmq }, 0 }, |
09a2c6cf L |
4655 | }, |
4656 | ||
592a252b | 4657 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4658 | { |
592a252b | 4659 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
ec6f095a | 4660 | { "vmovshdup", { XM, EXx }, 0 }, |
18897deb | 4661 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) }, |
5f754f58 | 4662 | }, |
7c52e0e8 | 4663 | |
592a252b | 4664 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4665 | { |
592d1631 | 4666 | { Bad_Opcode }, |
2b7bcc87 | 4667 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Edq }, 0 }, |
592d1631 | 4668 | { Bad_Opcode }, |
2b7bcc87 | 4669 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Edq }, 0 }, |
5f754f58 | 4670 | }, |
7c52e0e8 | 4671 | |
592a252b | 4672 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4673 | { |
592d1631 | 4674 | { Bad_Opcode }, |
2b7bcc87 | 4675 | { "vcvttss2si", { Gdq, EXdScalar }, 0 }, |
592d1631 | 4676 | { Bad_Opcode }, |
2b7bcc87 | 4677 | { "vcvttsd2si", { Gdq, EXqScalar }, 0 }, |
5f754f58 | 4678 | }, |
7c52e0e8 | 4679 | |
592a252b | 4680 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4681 | { |
592d1631 | 4682 | { Bad_Opcode }, |
2b7bcc87 | 4683 | { "vcvtss2si", { Gdq, EXdScalar }, 0 }, |
592d1631 | 4684 | { Bad_Opcode }, |
2b7bcc87 | 4685 | { "vcvtsd2si", { Gdq, EXqScalar }, 0 }, |
7c52e0e8 L |
4686 | }, |
4687 | ||
592a252b | 4688 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4689 | { |
ec6f095a | 4690 | { "vucomiss", { XMScalar, EXdScalar }, 0 }, |
592d1631 | 4691 | { Bad_Opcode }, |
ec6f095a | 4692 | { "vucomisd", { XMScalar, EXqScalar }, 0 }, |
7c52e0e8 L |
4693 | }, |
4694 | ||
592a252b | 4695 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4696 | { |
ec6f095a | 4697 | { "vcomiss", { XMScalar, EXdScalar }, 0 }, |
592d1631 | 4698 | { Bad_Opcode }, |
ec6f095a | 4699 | { "vcomisd", { XMScalar, EXqScalar }, 0 }, |
7c52e0e8 L |
4700 | }, |
4701 | ||
43234a1e L |
4702 | /* PREFIX_VEX_0F41 */ |
4703 | { | |
4704 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
4705 | { Bad_Opcode }, |
4706 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
4707 | }, |
4708 | ||
4709 | /* PREFIX_VEX_0F42 */ | |
4710 | { | |
4711 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
4712 | { Bad_Opcode }, |
4713 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
4714 | }, |
4715 | ||
4716 | /* PREFIX_VEX_0F44 */ | |
4717 | { | |
4718 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
1ba585e8 IT |
4719 | { Bad_Opcode }, |
4720 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, | |
43234a1e L |
4721 | }, |
4722 | ||
4723 | /* PREFIX_VEX_0F45 */ | |
4724 | { | |
4725 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
1ba585e8 IT |
4726 | { Bad_Opcode }, |
4727 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, | |
43234a1e L |
4728 | }, |
4729 | ||
4730 | /* PREFIX_VEX_0F46 */ | |
4731 | { | |
4732 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
1ba585e8 IT |
4733 | { Bad_Opcode }, |
4734 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, | |
43234a1e L |
4735 | }, |
4736 | ||
4737 | /* PREFIX_VEX_0F47 */ | |
4738 | { | |
4739 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
1ba585e8 IT |
4740 | { Bad_Opcode }, |
4741 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, | |
43234a1e L |
4742 | }, |
4743 | ||
1ba585e8 | 4744 | /* PREFIX_VEX_0F4A */ |
43234a1e | 4745 | { |
1ba585e8 | 4746 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 4747 | { Bad_Opcode }, |
1ba585e8 IT |
4748 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
4749 | }, | |
4750 | ||
4751 | /* PREFIX_VEX_0F4B */ | |
4752 | { | |
4753 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, | |
43234a1e L |
4754 | { Bad_Opcode }, |
4755 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
4756 | }, | |
4757 | ||
592a252b | 4758 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 4759 | { |
ec6f095a L |
4760 | { "vsqrtps", { XM, EXx }, 0 }, |
4761 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4762 | { "vsqrtpd", { XM, EXx }, 0 }, | |
4763 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4764 | }, |
4765 | ||
592a252b | 4766 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 4767 | { |
ec6f095a L |
4768 | { "vrsqrtps", { XM, EXx }, 0 }, |
4769 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
7c52e0e8 L |
4770 | }, |
4771 | ||
592a252b | 4772 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 4773 | { |
ec6f095a L |
4774 | { "vrcpps", { XM, EXx }, 0 }, |
4775 | { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
7c52e0e8 L |
4776 | }, |
4777 | ||
592a252b | 4778 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 4779 | { |
ec6f095a L |
4780 | { "vaddps", { XM, Vex, EXx }, 0 }, |
4781 | { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4782 | { "vaddpd", { XM, Vex, EXx }, 0 }, | |
4783 | { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4784 | }, |
4785 | ||
592a252b | 4786 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 4787 | { |
ec6f095a L |
4788 | { "vmulps", { XM, Vex, EXx }, 0 }, |
4789 | { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4790 | { "vmulpd", { XM, Vex, EXx }, 0 }, | |
4791 | { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4792 | }, |
4793 | ||
592a252b | 4794 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 4795 | { |
ec6f095a L |
4796 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
4797 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4798 | { "vcvtpd2ps%XY",{ XMM, EXx }, 0 }, | |
4799 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4800 | }, |
4801 | ||
592a252b | 4802 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 4803 | { |
ec6f095a L |
4804 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
4805 | { "vcvttps2dq", { XM, EXx }, 0 }, | |
4806 | { "vcvtps2dq", { XM, EXx }, 0 }, | |
7c52e0e8 L |
4807 | }, |
4808 | ||
592a252b | 4809 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 4810 | { |
ec6f095a L |
4811 | { "vsubps", { XM, Vex, EXx }, 0 }, |
4812 | { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4813 | { "vsubpd", { XM, Vex, EXx }, 0 }, | |
4814 | { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4815 | }, |
4816 | ||
592a252b | 4817 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 4818 | { |
ec6f095a L |
4819 | { "vminps", { XM, Vex, EXx }, 0 }, |
4820 | { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4821 | { "vminpd", { XM, Vex, EXx }, 0 }, | |
4822 | { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4823 | }, |
4824 | ||
592a252b | 4825 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 4826 | { |
ec6f095a L |
4827 | { "vdivps", { XM, Vex, EXx }, 0 }, |
4828 | { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4829 | { "vdivpd", { XM, Vex, EXx }, 0 }, | |
4830 | { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4831 | }, |
4832 | ||
592a252b | 4833 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 4834 | { |
ec6f095a L |
4835 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
4836 | { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4837 | { "vmaxpd", { XM, Vex, EXx }, 0 }, | |
4838 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4839 | }, |
4840 | ||
592a252b | 4841 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 4842 | { |
592d1631 L |
4843 | { Bad_Opcode }, |
4844 | { Bad_Opcode }, | |
ec6f095a | 4845 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4846 | }, |
4847 | ||
592a252b | 4848 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 4849 | { |
592d1631 L |
4850 | { Bad_Opcode }, |
4851 | { Bad_Opcode }, | |
ec6f095a | 4852 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4853 | }, |
4854 | ||
592a252b | 4855 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 4856 | { |
592d1631 L |
4857 | { Bad_Opcode }, |
4858 | { Bad_Opcode }, | |
ec6f095a | 4859 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4860 | }, |
4861 | ||
592a252b | 4862 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 4863 | { |
592d1631 L |
4864 | { Bad_Opcode }, |
4865 | { Bad_Opcode }, | |
ec6f095a | 4866 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4867 | }, |
4868 | ||
592a252b | 4869 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 4870 | { |
592d1631 L |
4871 | { Bad_Opcode }, |
4872 | { Bad_Opcode }, | |
ec6f095a | 4873 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4874 | }, |
4875 | ||
592a252b | 4876 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 4877 | { |
592d1631 L |
4878 | { Bad_Opcode }, |
4879 | { Bad_Opcode }, | |
ec6f095a | 4880 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4881 | }, |
4882 | ||
592a252b | 4883 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 4884 | { |
592d1631 L |
4885 | { Bad_Opcode }, |
4886 | { Bad_Opcode }, | |
ec6f095a | 4887 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 | 4888 | }, |
6439fc28 | 4889 | |
592a252b | 4890 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 4891 | { |
592d1631 L |
4892 | { Bad_Opcode }, |
4893 | { Bad_Opcode }, | |
ec6f095a | 4894 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4895 | }, |
4896 | ||
592a252b | 4897 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 4898 | { |
592d1631 L |
4899 | { Bad_Opcode }, |
4900 | { Bad_Opcode }, | |
ec6f095a | 4901 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4902 | }, |
4903 | ||
592a252b | 4904 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 4905 | { |
592d1631 L |
4906 | { Bad_Opcode }, |
4907 | { Bad_Opcode }, | |
ec6f095a | 4908 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4909 | }, |
4910 | ||
592a252b | 4911 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 4912 | { |
592d1631 L |
4913 | { Bad_Opcode }, |
4914 | { Bad_Opcode }, | |
ec6f095a | 4915 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4916 | }, |
4917 | ||
592a252b | 4918 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 4919 | { |
592d1631 L |
4920 | { Bad_Opcode }, |
4921 | { Bad_Opcode }, | |
ec6f095a | 4922 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4923 | }, |
4924 | ||
592a252b | 4925 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 4926 | { |
592d1631 L |
4927 | { Bad_Opcode }, |
4928 | { Bad_Opcode }, | |
ec6f095a | 4929 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4930 | }, |
4931 | ||
592a252b | 4932 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 4933 | { |
592d1631 L |
4934 | { Bad_Opcode }, |
4935 | { Bad_Opcode }, | |
ec6f095a | 4936 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4937 | }, |
4938 | ||
592a252b | 4939 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 4940 | { |
592d1631 L |
4941 | { Bad_Opcode }, |
4942 | { Bad_Opcode }, | |
592a252b | 4943 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
4944 | }, |
4945 | ||
592a252b | 4946 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 4947 | { |
592d1631 | 4948 | { Bad_Opcode }, |
ec6f095a L |
4949 | { "vmovdqu", { XM, EXx }, 0 }, |
4950 | { "vmovdqa", { XM, EXx }, 0 }, | |
c0f3af97 L |
4951 | }, |
4952 | ||
592a252b | 4953 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 4954 | { |
592d1631 | 4955 | { Bad_Opcode }, |
ec6f095a L |
4956 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
4957 | { "vpshufd", { XM, EXx, Ib }, 0 }, | |
4958 | { "vpshuflw", { XM, EXx, Ib }, 0 }, | |
c0f3af97 L |
4959 | }, |
4960 | ||
592a252b | 4961 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 4962 | { |
592d1631 L |
4963 | { Bad_Opcode }, |
4964 | { Bad_Opcode }, | |
ec6f095a | 4965 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4966 | }, |
4967 | ||
592a252b | 4968 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 4969 | { |
592d1631 L |
4970 | { Bad_Opcode }, |
4971 | { Bad_Opcode }, | |
ec6f095a | 4972 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4973 | }, |
4974 | ||
592a252b | 4975 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 4976 | { |
592d1631 L |
4977 | { Bad_Opcode }, |
4978 | { Bad_Opcode }, | |
ec6f095a | 4979 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4980 | }, |
4981 | ||
592a252b | 4982 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 4983 | { |
592d1631 L |
4984 | { Bad_Opcode }, |
4985 | { Bad_Opcode }, | |
ec6f095a | 4986 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4987 | }, |
4988 | ||
592a252b | 4989 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 4990 | { |
592d1631 L |
4991 | { Bad_Opcode }, |
4992 | { Bad_Opcode }, | |
ec6f095a | 4993 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4994 | }, |
4995 | ||
592a252b | 4996 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 4997 | { |
592d1631 L |
4998 | { Bad_Opcode }, |
4999 | { Bad_Opcode }, | |
ec6f095a | 5000 | { "vpslld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5001 | }, |
5002 | ||
592a252b | 5003 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 5004 | { |
592d1631 L |
5005 | { Bad_Opcode }, |
5006 | { Bad_Opcode }, | |
ec6f095a | 5007 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5008 | }, |
5009 | ||
592a252b | 5010 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 5011 | { |
592d1631 L |
5012 | { Bad_Opcode }, |
5013 | { Bad_Opcode }, | |
ec6f095a | 5014 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5015 | }, |
5016 | ||
592a252b | 5017 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 5018 | { |
592d1631 L |
5019 | { Bad_Opcode }, |
5020 | { Bad_Opcode }, | |
ec6f095a | 5021 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5022 | }, |
5023 | ||
592a252b | 5024 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 5025 | { |
592d1631 L |
5026 | { Bad_Opcode }, |
5027 | { Bad_Opcode }, | |
ec6f095a | 5028 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5029 | }, |
5030 | ||
592a252b | 5031 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 5032 | { |
592d1631 L |
5033 | { Bad_Opcode }, |
5034 | { Bad_Opcode }, | |
ec6f095a | 5035 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5036 | }, |
5037 | ||
592a252b | 5038 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 5039 | { |
592d1631 L |
5040 | { Bad_Opcode }, |
5041 | { Bad_Opcode }, | |
ec6f095a | 5042 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5043 | }, |
5044 | ||
592a252b | 5045 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 5046 | { |
592d1631 L |
5047 | { Bad_Opcode }, |
5048 | { Bad_Opcode }, | |
ec6f095a | 5049 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5050 | }, |
5051 | ||
592a252b | 5052 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 5053 | { |
ec6f095a | 5054 | { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) }, |
c0f3af97 L |
5055 | }, |
5056 | ||
592a252b | 5057 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 5058 | { |
592d1631 L |
5059 | { Bad_Opcode }, |
5060 | { Bad_Opcode }, | |
ec6f095a L |
5061 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
5062 | { "vhaddps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5063 | }, |
5064 | ||
592a252b | 5065 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 5066 | { |
592d1631 L |
5067 | { Bad_Opcode }, |
5068 | { Bad_Opcode }, | |
ec6f095a L |
5069 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
5070 | { "vhsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5071 | }, |
5072 | ||
592a252b | 5073 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 5074 | { |
592d1631 | 5075 | { Bad_Opcode }, |
592a252b L |
5076 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
5077 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
5078 | }, |
5079 | ||
592a252b | 5080 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 5081 | { |
592d1631 | 5082 | { Bad_Opcode }, |
ec6f095a L |
5083 | { "vmovdqu", { EXxS, XM }, 0 }, |
5084 | { "vmovdqa", { EXxS, XM }, 0 }, | |
c0f3af97 L |
5085 | }, |
5086 | ||
43234a1e L |
5087 | /* PREFIX_VEX_0F90 */ |
5088 | { | |
5089 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
1ba585e8 IT |
5090 | { Bad_Opcode }, |
5091 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, | |
43234a1e L |
5092 | }, |
5093 | ||
5094 | /* PREFIX_VEX_0F91 */ | |
5095 | { | |
5096 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
1ba585e8 IT |
5097 | { Bad_Opcode }, |
5098 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, | |
43234a1e L |
5099 | }, |
5100 | ||
5101 | /* PREFIX_VEX_0F92 */ | |
5102 | { | |
5103 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
1ba585e8 | 5104 | { Bad_Opcode }, |
90a915bf | 5105 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
1ba585e8 | 5106 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
43234a1e L |
5107 | }, |
5108 | ||
5109 | /* PREFIX_VEX_0F93 */ | |
5110 | { | |
5111 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
1ba585e8 | 5112 | { Bad_Opcode }, |
90a915bf | 5113 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
1ba585e8 | 5114 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
43234a1e L |
5115 | }, |
5116 | ||
5117 | /* PREFIX_VEX_0F98 */ | |
5118 | { | |
5119 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
1ba585e8 IT |
5120 | { Bad_Opcode }, |
5121 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, | |
5122 | }, | |
5123 | ||
5124 | /* PREFIX_VEX_0F99 */ | |
5125 | { | |
5126 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, | |
5127 | { Bad_Opcode }, | |
5128 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, | |
43234a1e L |
5129 | }, |
5130 | ||
592a252b | 5131 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 5132 | { |
ec6f095a L |
5133 | { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, |
5134 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, | |
5135 | { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, | |
5136 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, | |
c0f3af97 L |
5137 | }, |
5138 | ||
592a252b | 5139 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 5140 | { |
592d1631 L |
5141 | { Bad_Opcode }, |
5142 | { Bad_Opcode }, | |
592a252b | 5143 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
5144 | }, |
5145 | ||
592a252b | 5146 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 5147 | { |
592d1631 L |
5148 | { Bad_Opcode }, |
5149 | { Bad_Opcode }, | |
592a252b | 5150 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
5151 | }, |
5152 | ||
592a252b | 5153 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 5154 | { |
592d1631 L |
5155 | { Bad_Opcode }, |
5156 | { Bad_Opcode }, | |
ec6f095a L |
5157 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
5158 | { "vaddsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5159 | }, |
5160 | ||
592a252b | 5161 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 5162 | { |
592d1631 L |
5163 | { Bad_Opcode }, |
5164 | { Bad_Opcode }, | |
ec6f095a | 5165 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5166 | }, |
5167 | ||
592a252b | 5168 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 5169 | { |
592d1631 L |
5170 | { Bad_Opcode }, |
5171 | { Bad_Opcode }, | |
ec6f095a | 5172 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5173 | }, |
5174 | ||
592a252b | 5175 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 5176 | { |
592d1631 L |
5177 | { Bad_Opcode }, |
5178 | { Bad_Opcode }, | |
ec6f095a | 5179 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5180 | }, |
5181 | ||
592a252b | 5182 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 5183 | { |
592d1631 L |
5184 | { Bad_Opcode }, |
5185 | { Bad_Opcode }, | |
ec6f095a | 5186 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5187 | }, |
5188 | ||
592a252b | 5189 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 5190 | { |
592d1631 L |
5191 | { Bad_Opcode }, |
5192 | { Bad_Opcode }, | |
ec6f095a | 5193 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5194 | }, |
5195 | ||
592a252b | 5196 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 5197 | { |
592d1631 L |
5198 | { Bad_Opcode }, |
5199 | { Bad_Opcode }, | |
592a252b | 5200 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
5201 | }, |
5202 | ||
592a252b | 5203 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 5204 | { |
592d1631 L |
5205 | { Bad_Opcode }, |
5206 | { Bad_Opcode }, | |
592a252b | 5207 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
5208 | }, |
5209 | ||
592a252b | 5210 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 5211 | { |
592d1631 L |
5212 | { Bad_Opcode }, |
5213 | { Bad_Opcode }, | |
ec6f095a | 5214 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5215 | }, |
5216 | ||
592a252b | 5217 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 5218 | { |
592d1631 L |
5219 | { Bad_Opcode }, |
5220 | { Bad_Opcode }, | |
ec6f095a | 5221 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5222 | }, |
5223 | ||
592a252b | 5224 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 5225 | { |
592d1631 L |
5226 | { Bad_Opcode }, |
5227 | { Bad_Opcode }, | |
ec6f095a | 5228 | { "vpminub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5229 | }, |
5230 | ||
592a252b | 5231 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 5232 | { |
592d1631 L |
5233 | { Bad_Opcode }, |
5234 | { Bad_Opcode }, | |
ec6f095a | 5235 | { "vpand", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5236 | }, |
5237 | ||
592a252b | 5238 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 5239 | { |
592d1631 L |
5240 | { Bad_Opcode }, |
5241 | { Bad_Opcode }, | |
ec6f095a | 5242 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5243 | }, |
5244 | ||
592a252b | 5245 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 5246 | { |
592d1631 L |
5247 | { Bad_Opcode }, |
5248 | { Bad_Opcode }, | |
ec6f095a | 5249 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5250 | }, |
5251 | ||
592a252b | 5252 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 5253 | { |
592d1631 L |
5254 | { Bad_Opcode }, |
5255 | { Bad_Opcode }, | |
ec6f095a | 5256 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5257 | }, |
5258 | ||
592a252b | 5259 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 5260 | { |
592d1631 L |
5261 | { Bad_Opcode }, |
5262 | { Bad_Opcode }, | |
ec6f095a | 5263 | { "vpandn", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5264 | }, |
5265 | ||
592a252b | 5266 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 5267 | { |
592d1631 L |
5268 | { Bad_Opcode }, |
5269 | { Bad_Opcode }, | |
ec6f095a | 5270 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5271 | }, |
5272 | ||
592a252b | 5273 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 5274 | { |
592d1631 L |
5275 | { Bad_Opcode }, |
5276 | { Bad_Opcode }, | |
ec6f095a | 5277 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5278 | }, |
5279 | ||
592a252b | 5280 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 5281 | { |
592d1631 L |
5282 | { Bad_Opcode }, |
5283 | { Bad_Opcode }, | |
ec6f095a | 5284 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5285 | }, |
5286 | ||
592a252b | 5287 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 5288 | { |
592d1631 L |
5289 | { Bad_Opcode }, |
5290 | { Bad_Opcode }, | |
ec6f095a | 5291 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5292 | }, |
5293 | ||
592a252b | 5294 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 5295 | { |
592d1631 L |
5296 | { Bad_Opcode }, |
5297 | { Bad_Opcode }, | |
ec6f095a | 5298 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5299 | }, |
5300 | ||
592a252b | 5301 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 5302 | { |
592d1631 L |
5303 | { Bad_Opcode }, |
5304 | { Bad_Opcode }, | |
ec6f095a | 5305 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5306 | }, |
5307 | ||
592a252b | 5308 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 5309 | { |
592d1631 | 5310 | { Bad_Opcode }, |
ec6f095a L |
5311 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
5312 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, | |
5313 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, | |
c0f3af97 L |
5314 | }, |
5315 | ||
592a252b | 5316 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5317 | { |
592d1631 L |
5318 | { Bad_Opcode }, |
5319 | { Bad_Opcode }, | |
592a252b | 5320 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5321 | }, |
5322 | ||
592a252b | 5323 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5324 | { |
592d1631 L |
5325 | { Bad_Opcode }, |
5326 | { Bad_Opcode }, | |
ec6f095a | 5327 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5328 | }, |
5329 | ||
592a252b | 5330 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5331 | { |
592d1631 L |
5332 | { Bad_Opcode }, |
5333 | { Bad_Opcode }, | |
ec6f095a | 5334 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5335 | }, |
5336 | ||
592a252b | 5337 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5338 | { |
592d1631 L |
5339 | { Bad_Opcode }, |
5340 | { Bad_Opcode }, | |
ec6f095a | 5341 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5342 | }, |
5343 | ||
592a252b | 5344 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5345 | { |
592d1631 L |
5346 | { Bad_Opcode }, |
5347 | { Bad_Opcode }, | |
ec6f095a | 5348 | { "vpor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5349 | }, |
5350 | ||
592a252b | 5351 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5352 | { |
592d1631 L |
5353 | { Bad_Opcode }, |
5354 | { Bad_Opcode }, | |
ec6f095a | 5355 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5356 | }, |
5357 | ||
592a252b | 5358 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5359 | { |
592d1631 L |
5360 | { Bad_Opcode }, |
5361 | { Bad_Opcode }, | |
ec6f095a | 5362 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5363 | }, |
5364 | ||
592a252b | 5365 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5366 | { |
592d1631 L |
5367 | { Bad_Opcode }, |
5368 | { Bad_Opcode }, | |
ec6f095a | 5369 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5370 | }, |
5371 | ||
592a252b | 5372 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5373 | { |
592d1631 L |
5374 | { Bad_Opcode }, |
5375 | { Bad_Opcode }, | |
ec6f095a | 5376 | { "vpxor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5377 | }, |
5378 | ||
592a252b | 5379 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5380 | { |
592d1631 L |
5381 | { Bad_Opcode }, |
5382 | { Bad_Opcode }, | |
5383 | { Bad_Opcode }, | |
592a252b | 5384 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5385 | }, |
5386 | ||
592a252b | 5387 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5388 | { |
592d1631 L |
5389 | { Bad_Opcode }, |
5390 | { Bad_Opcode }, | |
ec6f095a | 5391 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5392 | }, |
5393 | ||
592a252b | 5394 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5395 | { |
592d1631 L |
5396 | { Bad_Opcode }, |
5397 | { Bad_Opcode }, | |
ec6f095a | 5398 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5399 | }, |
5400 | ||
592a252b | 5401 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5402 | { |
592d1631 L |
5403 | { Bad_Opcode }, |
5404 | { Bad_Opcode }, | |
ec6f095a | 5405 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5406 | }, |
5407 | ||
592a252b | 5408 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5409 | { |
592d1631 L |
5410 | { Bad_Opcode }, |
5411 | { Bad_Opcode }, | |
ec6f095a | 5412 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5413 | }, |
5414 | ||
592a252b | 5415 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5416 | { |
592d1631 L |
5417 | { Bad_Opcode }, |
5418 | { Bad_Opcode }, | |
ec6f095a | 5419 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5420 | }, |
5421 | ||
592a252b | 5422 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5423 | { |
592d1631 L |
5424 | { Bad_Opcode }, |
5425 | { Bad_Opcode }, | |
ec6f095a | 5426 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5427 | }, |
5428 | ||
592a252b | 5429 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5430 | { |
592d1631 L |
5431 | { Bad_Opcode }, |
5432 | { Bad_Opcode }, | |
592a252b | 5433 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5434 | }, |
5435 | ||
592a252b | 5436 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5437 | { |
592d1631 L |
5438 | { Bad_Opcode }, |
5439 | { Bad_Opcode }, | |
ec6f095a | 5440 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5441 | }, |
5442 | ||
592a252b | 5443 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5444 | { |
592d1631 L |
5445 | { Bad_Opcode }, |
5446 | { Bad_Opcode }, | |
ec6f095a | 5447 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5448 | }, |
5449 | ||
592a252b | 5450 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5451 | { |
592d1631 L |
5452 | { Bad_Opcode }, |
5453 | { Bad_Opcode }, | |
ec6f095a | 5454 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5455 | }, |
5456 | ||
592a252b | 5457 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5458 | { |
592d1631 L |
5459 | { Bad_Opcode }, |
5460 | { Bad_Opcode }, | |
ec6f095a | 5461 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5462 | }, |
5463 | ||
592a252b | 5464 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5465 | { |
592d1631 L |
5466 | { Bad_Opcode }, |
5467 | { Bad_Opcode }, | |
ec6f095a | 5468 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5469 | }, |
5470 | ||
592a252b | 5471 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5472 | { |
592d1631 L |
5473 | { Bad_Opcode }, |
5474 | { Bad_Opcode }, | |
ec6f095a | 5475 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5476 | }, |
5477 | ||
592a252b | 5478 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5479 | { |
592d1631 L |
5480 | { Bad_Opcode }, |
5481 | { Bad_Opcode }, | |
ec6f095a | 5482 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5483 | }, |
5484 | ||
592a252b | 5485 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5486 | { |
592d1631 L |
5487 | { Bad_Opcode }, |
5488 | { Bad_Opcode }, | |
ec6f095a | 5489 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5490 | }, |
5491 | ||
592a252b | 5492 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5493 | { |
592d1631 L |
5494 | { Bad_Opcode }, |
5495 | { Bad_Opcode }, | |
ec6f095a | 5496 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5497 | }, |
5498 | ||
592a252b | 5499 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5500 | { |
592d1631 L |
5501 | { Bad_Opcode }, |
5502 | { Bad_Opcode }, | |
ec6f095a | 5503 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5504 | }, |
5505 | ||
592a252b | 5506 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5507 | { |
592d1631 L |
5508 | { Bad_Opcode }, |
5509 | { Bad_Opcode }, | |
ec6f095a | 5510 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5511 | }, |
5512 | ||
592a252b | 5513 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5514 | { |
592d1631 L |
5515 | { Bad_Opcode }, |
5516 | { Bad_Opcode }, | |
ec6f095a | 5517 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5518 | }, |
5519 | ||
592a252b | 5520 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5521 | { |
592d1631 L |
5522 | { Bad_Opcode }, |
5523 | { Bad_Opcode }, | |
ec6f095a | 5524 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5525 | }, |
5526 | ||
592a252b | 5527 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5528 | { |
592d1631 L |
5529 | { Bad_Opcode }, |
5530 | { Bad_Opcode }, | |
ec6f095a | 5531 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5532 | }, |
5533 | ||
592a252b | 5534 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5535 | { |
592d1631 L |
5536 | { Bad_Opcode }, |
5537 | { Bad_Opcode }, | |
ec6f095a | 5538 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5539 | }, |
5540 | ||
592a252b | 5541 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5542 | { |
592d1631 L |
5543 | { Bad_Opcode }, |
5544 | { Bad_Opcode }, | |
ec6f095a | 5545 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5546 | }, |
5547 | ||
592a252b | 5548 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5549 | { |
592d1631 L |
5550 | { Bad_Opcode }, |
5551 | { Bad_Opcode }, | |
ec6f095a | 5552 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5553 | }, |
5554 | ||
592a252b | 5555 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5556 | { |
592d1631 L |
5557 | { Bad_Opcode }, |
5558 | { Bad_Opcode }, | |
ec6f095a | 5559 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5560 | }, |
5561 | ||
592a252b | 5562 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5563 | { |
592d1631 L |
5564 | { Bad_Opcode }, |
5565 | { Bad_Opcode }, | |
ec6f095a | 5566 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5567 | }, |
5568 | ||
592a252b | 5569 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5570 | { |
592d1631 L |
5571 | { Bad_Opcode }, |
5572 | { Bad_Opcode }, | |
592a252b | 5573 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5574 | }, |
5575 | ||
592a252b | 5576 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5577 | { |
592d1631 L |
5578 | { Bad_Opcode }, |
5579 | { Bad_Opcode }, | |
592a252b | 5580 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5581 | }, |
5582 | ||
592a252b | 5583 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5584 | { |
592d1631 L |
5585 | { Bad_Opcode }, |
5586 | { Bad_Opcode }, | |
592a252b | 5587 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5588 | }, |
5589 | ||
592a252b | 5590 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5591 | { |
592d1631 L |
5592 | { Bad_Opcode }, |
5593 | { Bad_Opcode }, | |
592a252b | 5594 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5595 | }, |
5596 | ||
592a252b | 5597 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5598 | { |
5599 | { Bad_Opcode }, | |
5600 | { Bad_Opcode }, | |
bf890a93 | 5601 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, |
c7b8aa3a L |
5602 | }, |
5603 | ||
6c30d220 L |
5604 | /* PREFIX_VEX_0F3816 */ |
5605 | { | |
5606 | { Bad_Opcode }, | |
5607 | { Bad_Opcode }, | |
5608 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5609 | }, | |
5610 | ||
592a252b | 5611 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5612 | { |
592d1631 L |
5613 | { Bad_Opcode }, |
5614 | { Bad_Opcode }, | |
ec6f095a | 5615 | { "vptest", { XM, EXx }, 0 }, |
c0f3af97 L |
5616 | }, |
5617 | ||
592a252b | 5618 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5619 | { |
592d1631 L |
5620 | { Bad_Opcode }, |
5621 | { Bad_Opcode }, | |
6c30d220 | 5622 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5623 | }, |
5624 | ||
592a252b | 5625 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5626 | { |
592d1631 L |
5627 | { Bad_Opcode }, |
5628 | { Bad_Opcode }, | |
6c30d220 | 5629 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5630 | }, |
5631 | ||
592a252b | 5632 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5633 | { |
592d1631 L |
5634 | { Bad_Opcode }, |
5635 | { Bad_Opcode }, | |
592a252b | 5636 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5637 | }, |
5638 | ||
592a252b | 5639 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5640 | { |
592d1631 L |
5641 | { Bad_Opcode }, |
5642 | { Bad_Opcode }, | |
ec6f095a | 5643 | { "vpabsb", { XM, EXx }, 0 }, |
c0f3af97 L |
5644 | }, |
5645 | ||
592a252b | 5646 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5647 | { |
592d1631 L |
5648 | { Bad_Opcode }, |
5649 | { Bad_Opcode }, | |
ec6f095a | 5650 | { "vpabsw", { XM, EXx }, 0 }, |
c0f3af97 L |
5651 | }, |
5652 | ||
592a252b | 5653 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5654 | { |
592d1631 L |
5655 | { Bad_Opcode }, |
5656 | { Bad_Opcode }, | |
ec6f095a | 5657 | { "vpabsd", { XM, EXx }, 0 }, |
c0f3af97 L |
5658 | }, |
5659 | ||
592a252b | 5660 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5661 | { |
592d1631 L |
5662 | { Bad_Opcode }, |
5663 | { Bad_Opcode }, | |
ec6f095a | 5664 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5665 | }, |
5666 | ||
592a252b | 5667 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5668 | { |
592d1631 L |
5669 | { Bad_Opcode }, |
5670 | { Bad_Opcode }, | |
ec6f095a | 5671 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5672 | }, |
5673 | ||
592a252b | 5674 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5675 | { |
592d1631 L |
5676 | { Bad_Opcode }, |
5677 | { Bad_Opcode }, | |
ec6f095a | 5678 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5679 | }, |
5680 | ||
592a252b | 5681 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5682 | { |
592d1631 L |
5683 | { Bad_Opcode }, |
5684 | { Bad_Opcode }, | |
ec6f095a | 5685 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5686 | }, |
5687 | ||
592a252b | 5688 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5689 | { |
592d1631 L |
5690 | { Bad_Opcode }, |
5691 | { Bad_Opcode }, | |
ec6f095a | 5692 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5693 | }, |
5694 | ||
592a252b | 5695 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5696 | { |
592d1631 L |
5697 | { Bad_Opcode }, |
5698 | { Bad_Opcode }, | |
ec6f095a | 5699 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5700 | }, |
5701 | ||
592a252b | 5702 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5703 | { |
592d1631 L |
5704 | { Bad_Opcode }, |
5705 | { Bad_Opcode }, | |
ec6f095a | 5706 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5707 | }, |
5708 | ||
592a252b | 5709 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5710 | { |
592d1631 L |
5711 | { Bad_Opcode }, |
5712 | { Bad_Opcode }, | |
ec6f095a | 5713 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5714 | }, |
5715 | ||
592a252b | 5716 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5717 | { |
592d1631 L |
5718 | { Bad_Opcode }, |
5719 | { Bad_Opcode }, | |
592a252b | 5720 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5721 | }, |
5722 | ||
592a252b | 5723 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5724 | { |
592d1631 L |
5725 | { Bad_Opcode }, |
5726 | { Bad_Opcode }, | |
ec6f095a | 5727 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5728 | }, |
5729 | ||
592a252b | 5730 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5731 | { |
592d1631 L |
5732 | { Bad_Opcode }, |
5733 | { Bad_Opcode }, | |
592a252b | 5734 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5735 | }, |
5736 | ||
592a252b | 5737 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5738 | { |
592d1631 L |
5739 | { Bad_Opcode }, |
5740 | { Bad_Opcode }, | |
592a252b | 5741 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5742 | }, |
5743 | ||
592a252b | 5744 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5745 | { |
592d1631 L |
5746 | { Bad_Opcode }, |
5747 | { Bad_Opcode }, | |
592a252b | 5748 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5749 | }, |
5750 | ||
592a252b | 5751 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5752 | { |
592d1631 L |
5753 | { Bad_Opcode }, |
5754 | { Bad_Opcode }, | |
592a252b | 5755 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
5756 | }, |
5757 | ||
592a252b | 5758 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 5759 | { |
592d1631 L |
5760 | { Bad_Opcode }, |
5761 | { Bad_Opcode }, | |
ec6f095a | 5762 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5763 | }, |
5764 | ||
592a252b | 5765 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 5766 | { |
592d1631 L |
5767 | { Bad_Opcode }, |
5768 | { Bad_Opcode }, | |
ec6f095a | 5769 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5770 | }, |
5771 | ||
592a252b | 5772 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 5773 | { |
592d1631 L |
5774 | { Bad_Opcode }, |
5775 | { Bad_Opcode }, | |
ec6f095a | 5776 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5777 | }, |
5778 | ||
592a252b | 5779 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 5780 | { |
592d1631 L |
5781 | { Bad_Opcode }, |
5782 | { Bad_Opcode }, | |
ec6f095a | 5783 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5784 | }, |
5785 | ||
592a252b | 5786 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 5787 | { |
592d1631 L |
5788 | { Bad_Opcode }, |
5789 | { Bad_Opcode }, | |
ec6f095a | 5790 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5791 | }, |
5792 | ||
592a252b | 5793 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 5794 | { |
592d1631 L |
5795 | { Bad_Opcode }, |
5796 | { Bad_Opcode }, | |
ec6f095a | 5797 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
6c30d220 L |
5798 | }, |
5799 | ||
5800 | /* PREFIX_VEX_0F3836 */ | |
5801 | { | |
5802 | { Bad_Opcode }, | |
5803 | { Bad_Opcode }, | |
5804 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
5805 | }, |
5806 | ||
592a252b | 5807 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 5808 | { |
592d1631 L |
5809 | { Bad_Opcode }, |
5810 | { Bad_Opcode }, | |
ec6f095a | 5811 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5812 | }, |
5813 | ||
592a252b | 5814 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 5815 | { |
592d1631 L |
5816 | { Bad_Opcode }, |
5817 | { Bad_Opcode }, | |
ec6f095a | 5818 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5819 | }, |
5820 | ||
592a252b | 5821 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 5822 | { |
592d1631 L |
5823 | { Bad_Opcode }, |
5824 | { Bad_Opcode }, | |
ec6f095a | 5825 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5826 | }, |
5827 | ||
592a252b | 5828 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 5829 | { |
592d1631 L |
5830 | { Bad_Opcode }, |
5831 | { Bad_Opcode }, | |
ec6f095a | 5832 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5833 | }, |
5834 | ||
592a252b | 5835 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 5836 | { |
592d1631 L |
5837 | { Bad_Opcode }, |
5838 | { Bad_Opcode }, | |
ec6f095a | 5839 | { "vpminud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5840 | }, |
5841 | ||
592a252b | 5842 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 5843 | { |
592d1631 L |
5844 | { Bad_Opcode }, |
5845 | { Bad_Opcode }, | |
ec6f095a | 5846 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5847 | }, |
5848 | ||
592a252b | 5849 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 5850 | { |
592d1631 L |
5851 | { Bad_Opcode }, |
5852 | { Bad_Opcode }, | |
ec6f095a | 5853 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5854 | }, |
5855 | ||
592a252b | 5856 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 5857 | { |
592d1631 L |
5858 | { Bad_Opcode }, |
5859 | { Bad_Opcode }, | |
ec6f095a | 5860 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5861 | }, |
5862 | ||
592a252b | 5863 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 5864 | { |
592d1631 L |
5865 | { Bad_Opcode }, |
5866 | { Bad_Opcode }, | |
ec6f095a | 5867 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5868 | }, |
5869 | ||
592a252b | 5870 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 5871 | { |
592d1631 L |
5872 | { Bad_Opcode }, |
5873 | { Bad_Opcode }, | |
ec6f095a | 5874 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5875 | }, |
5876 | ||
592a252b | 5877 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 5878 | { |
592d1631 L |
5879 | { Bad_Opcode }, |
5880 | { Bad_Opcode }, | |
592a252b | 5881 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
5882 | }, |
5883 | ||
6c30d220 L |
5884 | /* PREFIX_VEX_0F3845 */ |
5885 | { | |
5886 | { Bad_Opcode }, | |
5887 | { Bad_Opcode }, | |
bf890a93 | 5888 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5889 | }, |
5890 | ||
5891 | /* PREFIX_VEX_0F3846 */ | |
5892 | { | |
5893 | { Bad_Opcode }, | |
5894 | { Bad_Opcode }, | |
5895 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
5896 | }, | |
5897 | ||
5898 | /* PREFIX_VEX_0F3847 */ | |
5899 | { | |
5900 | { Bad_Opcode }, | |
5901 | { Bad_Opcode }, | |
bf890a93 | 5902 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5903 | }, |
5904 | ||
5905 | /* PREFIX_VEX_0F3858 */ | |
5906 | { | |
5907 | { Bad_Opcode }, | |
5908 | { Bad_Opcode }, | |
5909 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
5910 | }, | |
5911 | ||
5912 | /* PREFIX_VEX_0F3859 */ | |
5913 | { | |
5914 | { Bad_Opcode }, | |
5915 | { Bad_Opcode }, | |
5916 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
5917 | }, | |
5918 | ||
5919 | /* PREFIX_VEX_0F385A */ | |
5920 | { | |
5921 | { Bad_Opcode }, | |
5922 | { Bad_Opcode }, | |
5923 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
5924 | }, | |
5925 | ||
5926 | /* PREFIX_VEX_0F3878 */ | |
5927 | { | |
5928 | { Bad_Opcode }, | |
5929 | { Bad_Opcode }, | |
5930 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
5931 | }, | |
5932 | ||
5933 | /* PREFIX_VEX_0F3879 */ | |
5934 | { | |
5935 | { Bad_Opcode }, | |
5936 | { Bad_Opcode }, | |
5937 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
5938 | }, | |
5939 | ||
5940 | /* PREFIX_VEX_0F388C */ | |
5941 | { | |
5942 | { Bad_Opcode }, | |
5943 | { Bad_Opcode }, | |
f7002f42 | 5944 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
5945 | }, |
5946 | ||
5947 | /* PREFIX_VEX_0F388E */ | |
5948 | { | |
5949 | { Bad_Opcode }, | |
5950 | { Bad_Opcode }, | |
f7002f42 | 5951 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
5952 | }, |
5953 | ||
5954 | /* PREFIX_VEX_0F3890 */ | |
5955 | { | |
5956 | { Bad_Opcode }, | |
5957 | { Bad_Opcode }, | |
bf890a93 | 5958 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
5959 | }, |
5960 | ||
5961 | /* PREFIX_VEX_0F3891 */ | |
5962 | { | |
5963 | { Bad_Opcode }, | |
5964 | { Bad_Opcode }, | |
bf890a93 | 5965 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
5966 | }, |
5967 | ||
5968 | /* PREFIX_VEX_0F3892 */ | |
5969 | { | |
5970 | { Bad_Opcode }, | |
5971 | { Bad_Opcode }, | |
bf890a93 | 5972 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
5973 | }, |
5974 | ||
5975 | /* PREFIX_VEX_0F3893 */ | |
5976 | { | |
5977 | { Bad_Opcode }, | |
5978 | { Bad_Opcode }, | |
bf890a93 | 5979 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
5980 | }, |
5981 | ||
592a252b | 5982 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 5983 | { |
592d1631 L |
5984 | { Bad_Opcode }, |
5985 | { Bad_Opcode }, | |
bf890a93 | 5986 | { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
5987 | }, |
5988 | ||
592a252b | 5989 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 5990 | { |
592d1631 L |
5991 | { Bad_Opcode }, |
5992 | { Bad_Opcode }, | |
bf890a93 | 5993 | { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
5994 | }, |
5995 | ||
592a252b | 5996 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 5997 | { |
592d1631 L |
5998 | { Bad_Opcode }, |
5999 | { Bad_Opcode }, | |
bf890a93 | 6000 | { "vfmadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6001 | }, |
6002 | ||
592a252b | 6003 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 6004 | { |
592d1631 L |
6005 | { Bad_Opcode }, |
6006 | { Bad_Opcode }, | |
bf890a93 | 6007 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
a5ff0eb2 L |
6008 | }, |
6009 | ||
592a252b | 6010 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 6011 | { |
592d1631 L |
6012 | { Bad_Opcode }, |
6013 | { Bad_Opcode }, | |
bf890a93 | 6014 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6015 | }, |
6016 | ||
592a252b | 6017 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 6018 | { |
592d1631 L |
6019 | { Bad_Opcode }, |
6020 | { Bad_Opcode }, | |
bf890a93 | 6021 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6022 | }, |
6023 | ||
592a252b | 6024 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 6025 | { |
592d1631 L |
6026 | { Bad_Opcode }, |
6027 | { Bad_Opcode }, | |
bf890a93 | 6028 | { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6029 | }, |
6030 | ||
592a252b | 6031 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 6032 | { |
592d1631 L |
6033 | { Bad_Opcode }, |
6034 | { Bad_Opcode }, | |
bf890a93 | 6035 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6036 | }, |
6037 | ||
592a252b | 6038 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 6039 | { |
592d1631 L |
6040 | { Bad_Opcode }, |
6041 | { Bad_Opcode }, | |
bf890a93 | 6042 | { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6043 | }, |
6044 | ||
592a252b | 6045 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 6046 | { |
592d1631 L |
6047 | { Bad_Opcode }, |
6048 | { Bad_Opcode }, | |
bf890a93 | 6049 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6050 | }, |
6051 | ||
592a252b | 6052 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 6053 | { |
592d1631 L |
6054 | { Bad_Opcode }, |
6055 | { Bad_Opcode }, | |
bf890a93 | 6056 | { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 }, |
592d1631 | 6057 | { Bad_Opcode }, |
c0f3af97 L |
6058 | }, |
6059 | ||
592a252b | 6060 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 6061 | { |
592d1631 L |
6062 | { Bad_Opcode }, |
6063 | { Bad_Opcode }, | |
bf890a93 | 6064 | { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6065 | }, |
6066 | ||
592a252b | 6067 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 6068 | { |
592d1631 L |
6069 | { Bad_Opcode }, |
6070 | { Bad_Opcode }, | |
bf890a93 | 6071 | { "vfmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6072 | }, |
6073 | ||
592a252b | 6074 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 6075 | { |
592d1631 L |
6076 | { Bad_Opcode }, |
6077 | { Bad_Opcode }, | |
bf890a93 | 6078 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6079 | }, |
6080 | ||
592a252b | 6081 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 6082 | { |
592d1631 L |
6083 | { Bad_Opcode }, |
6084 | { Bad_Opcode }, | |
bf890a93 | 6085 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6086 | }, |
6087 | ||
592a252b | 6088 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 6089 | { |
592d1631 L |
6090 | { Bad_Opcode }, |
6091 | { Bad_Opcode }, | |
bf890a93 | 6092 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6093 | }, |
6094 | ||
592a252b | 6095 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 6096 | { |
592d1631 L |
6097 | { Bad_Opcode }, |
6098 | { Bad_Opcode }, | |
bf890a93 | 6099 | { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6100 | }, |
6101 | ||
592a252b | 6102 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 6103 | { |
592d1631 L |
6104 | { Bad_Opcode }, |
6105 | { Bad_Opcode }, | |
bf890a93 | 6106 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6107 | }, |
6108 | ||
592a252b | 6109 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 6110 | { |
592d1631 L |
6111 | { Bad_Opcode }, |
6112 | { Bad_Opcode }, | |
bf890a93 | 6113 | { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6114 | }, |
6115 | ||
592a252b | 6116 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 6117 | { |
592d1631 L |
6118 | { Bad_Opcode }, |
6119 | { Bad_Opcode }, | |
bf890a93 | 6120 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6121 | }, |
6122 | ||
592a252b | 6123 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 6124 | { |
592d1631 L |
6125 | { Bad_Opcode }, |
6126 | { Bad_Opcode }, | |
bf890a93 | 6127 | { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6128 | }, |
6129 | ||
592a252b | 6130 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 6131 | { |
592d1631 L |
6132 | { Bad_Opcode }, |
6133 | { Bad_Opcode }, | |
bf890a93 | 6134 | { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6135 | }, |
6136 | ||
592a252b | 6137 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 6138 | { |
592d1631 L |
6139 | { Bad_Opcode }, |
6140 | { Bad_Opcode }, | |
bf890a93 | 6141 | { "vfmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6142 | }, |
6143 | ||
592a252b | 6144 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 6145 | { |
592d1631 L |
6146 | { Bad_Opcode }, |
6147 | { Bad_Opcode }, | |
bf890a93 | 6148 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6149 | }, |
6150 | ||
592a252b | 6151 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 6152 | { |
592d1631 L |
6153 | { Bad_Opcode }, |
6154 | { Bad_Opcode }, | |
bf890a93 | 6155 | { "vfmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6156 | }, |
6157 | ||
592a252b | 6158 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 6159 | { |
592d1631 L |
6160 | { Bad_Opcode }, |
6161 | { Bad_Opcode }, | |
bf890a93 | 6162 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6163 | }, |
6164 | ||
592a252b | 6165 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 6166 | { |
592d1631 L |
6167 | { Bad_Opcode }, |
6168 | { Bad_Opcode }, | |
bf890a93 | 6169 | { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6170 | }, |
6171 | ||
592a252b | 6172 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 6173 | { |
592d1631 L |
6174 | { Bad_Opcode }, |
6175 | { Bad_Opcode }, | |
bf890a93 | 6176 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6177 | }, |
6178 | ||
592a252b | 6179 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 6180 | { |
592d1631 L |
6181 | { Bad_Opcode }, |
6182 | { Bad_Opcode }, | |
bf890a93 | 6183 | { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6184 | }, |
6185 | ||
592a252b | 6186 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 6187 | { |
592d1631 L |
6188 | { Bad_Opcode }, |
6189 | { Bad_Opcode }, | |
bf890a93 | 6190 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6191 | }, |
6192 | ||
48521003 IT |
6193 | /* PREFIX_VEX_0F38CF */ |
6194 | { | |
6195 | { Bad_Opcode }, | |
6196 | { Bad_Opcode }, | |
6197 | { VEX_W_TABLE (VEX_W_0F38CF_P_2) }, | |
6198 | }, | |
6199 | ||
592a252b | 6200 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 6201 | { |
592d1631 L |
6202 | { Bad_Opcode }, |
6203 | { Bad_Opcode }, | |
592a252b | 6204 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
6205 | }, |
6206 | ||
592a252b | 6207 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 6208 | { |
592d1631 L |
6209 | { Bad_Opcode }, |
6210 | { Bad_Opcode }, | |
8dcf1fad | 6211 | { "vaesenc", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6212 | }, |
6213 | ||
592a252b | 6214 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 6215 | { |
592d1631 L |
6216 | { Bad_Opcode }, |
6217 | { Bad_Opcode }, | |
8dcf1fad | 6218 | { "vaesenclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6219 | }, |
6220 | ||
592a252b | 6221 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 6222 | { |
592d1631 L |
6223 | { Bad_Opcode }, |
6224 | { Bad_Opcode }, | |
8dcf1fad | 6225 | { "vaesdec", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6226 | }, |
6227 | ||
592a252b | 6228 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 6229 | { |
592d1631 L |
6230 | { Bad_Opcode }, |
6231 | { Bad_Opcode }, | |
8dcf1fad | 6232 | { "vaesdeclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6233 | }, |
6234 | ||
f12dc422 L |
6235 | /* PREFIX_VEX_0F38F2 */ |
6236 | { | |
6237 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
6238 | }, | |
6239 | ||
6240 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
6241 | { | |
6242 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
6243 | }, | |
6244 | ||
6245 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
6246 | { | |
6247 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
6248 | }, | |
6249 | ||
6250 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
6251 | { | |
6252 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
6253 | }, | |
6254 | ||
6c30d220 L |
6255 | /* PREFIX_VEX_0F38F5 */ |
6256 | { | |
6257 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
6258 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
6259 | { Bad_Opcode }, | |
6260 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
6261 | }, | |
6262 | ||
6263 | /* PREFIX_VEX_0F38F6 */ | |
6264 | { | |
6265 | { Bad_Opcode }, | |
6266 | { Bad_Opcode }, | |
6267 | { Bad_Opcode }, | |
6268 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
6269 | }, | |
6270 | ||
f12dc422 L |
6271 | /* PREFIX_VEX_0F38F7 */ |
6272 | { | |
6273 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
6274 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6275 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
6276 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
6277 | }, | |
6278 | ||
6279 | /* PREFIX_VEX_0F3A00 */ | |
6280 | { | |
6281 | { Bad_Opcode }, | |
6282 | { Bad_Opcode }, | |
6283 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
6284 | }, | |
6285 | ||
6286 | /* PREFIX_VEX_0F3A01 */ | |
6287 | { | |
6288 | { Bad_Opcode }, | |
6289 | { Bad_Opcode }, | |
6290 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
6291 | }, | |
6292 | ||
6293 | /* PREFIX_VEX_0F3A02 */ | |
6294 | { | |
6295 | { Bad_Opcode }, | |
6296 | { Bad_Opcode }, | |
6297 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
6298 | }, |
6299 | ||
592a252b | 6300 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 6301 | { |
592d1631 L |
6302 | { Bad_Opcode }, |
6303 | { Bad_Opcode }, | |
592a252b | 6304 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
6305 | }, |
6306 | ||
592a252b | 6307 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 6308 | { |
592d1631 L |
6309 | { Bad_Opcode }, |
6310 | { Bad_Opcode }, | |
592a252b | 6311 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
6312 | }, |
6313 | ||
592a252b | 6314 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 6315 | { |
592d1631 L |
6316 | { Bad_Opcode }, |
6317 | { Bad_Opcode }, | |
592a252b | 6318 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
6319 | }, |
6320 | ||
592a252b | 6321 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6322 | { |
592d1631 L |
6323 | { Bad_Opcode }, |
6324 | { Bad_Opcode }, | |
ec6f095a | 6325 | { "vroundps", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6326 | }, |
6327 | ||
592a252b | 6328 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6329 | { |
592d1631 L |
6330 | { Bad_Opcode }, |
6331 | { Bad_Opcode }, | |
ec6f095a | 6332 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6333 | }, |
6334 | ||
592a252b | 6335 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6336 | { |
592d1631 L |
6337 | { Bad_Opcode }, |
6338 | { Bad_Opcode }, | |
ec6f095a | 6339 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, |
0bfee649 L |
6340 | }, |
6341 | ||
592a252b | 6342 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6343 | { |
592d1631 L |
6344 | { Bad_Opcode }, |
6345 | { Bad_Opcode }, | |
ec6f095a | 6346 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, |
0bfee649 L |
6347 | }, |
6348 | ||
592a252b | 6349 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6350 | { |
592d1631 L |
6351 | { Bad_Opcode }, |
6352 | { Bad_Opcode }, | |
ec6f095a | 6353 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6354 | }, |
6355 | ||
592a252b | 6356 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6357 | { |
592d1631 L |
6358 | { Bad_Opcode }, |
6359 | { Bad_Opcode }, | |
ec6f095a | 6360 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6361 | }, |
6362 | ||
592a252b | 6363 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6364 | { |
592d1631 L |
6365 | { Bad_Opcode }, |
6366 | { Bad_Opcode }, | |
ec6f095a | 6367 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6368 | }, |
6369 | ||
592a252b | 6370 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6371 | { |
592d1631 L |
6372 | { Bad_Opcode }, |
6373 | { Bad_Opcode }, | |
ec6f095a | 6374 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6375 | }, |
6376 | ||
592a252b | 6377 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6378 | { |
592d1631 L |
6379 | { Bad_Opcode }, |
6380 | { Bad_Opcode }, | |
592a252b | 6381 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6382 | }, |
6383 | ||
592a252b | 6384 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6385 | { |
592d1631 L |
6386 | { Bad_Opcode }, |
6387 | { Bad_Opcode }, | |
592a252b | 6388 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6389 | }, |
6390 | ||
592a252b | 6391 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6392 | { |
592d1631 L |
6393 | { Bad_Opcode }, |
6394 | { Bad_Opcode }, | |
592a252b | 6395 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6396 | }, |
6397 | ||
592a252b | 6398 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6399 | { |
592d1631 L |
6400 | { Bad_Opcode }, |
6401 | { Bad_Opcode }, | |
592a252b | 6402 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6403 | }, |
6404 | ||
592a252b | 6405 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6406 | { |
592d1631 L |
6407 | { Bad_Opcode }, |
6408 | { Bad_Opcode }, | |
592a252b | 6409 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6410 | }, |
6411 | ||
592a252b | 6412 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6413 | { |
592d1631 L |
6414 | { Bad_Opcode }, |
6415 | { Bad_Opcode }, | |
592a252b | 6416 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6417 | }, |
6418 | ||
592a252b | 6419 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6420 | { |
6421 | { Bad_Opcode }, | |
6422 | { Bad_Opcode }, | |
bf890a93 | 6423 | { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 }, |
c7b8aa3a L |
6424 | }, |
6425 | ||
592a252b | 6426 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6427 | { |
592d1631 L |
6428 | { Bad_Opcode }, |
6429 | { Bad_Opcode }, | |
592a252b | 6430 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6431 | }, |
6432 | ||
592a252b | 6433 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6434 | { |
592d1631 L |
6435 | { Bad_Opcode }, |
6436 | { Bad_Opcode }, | |
592a252b | 6437 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6438 | }, |
6439 | ||
592a252b | 6440 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6441 | { |
592d1631 L |
6442 | { Bad_Opcode }, |
6443 | { Bad_Opcode }, | |
592a252b | 6444 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6445 | }, |
6446 | ||
43234a1e L |
6447 | /* PREFIX_VEX_0F3A30 */ |
6448 | { | |
6449 | { Bad_Opcode }, | |
6450 | { Bad_Opcode }, | |
6451 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6452 | }, | |
6453 | ||
1ba585e8 IT |
6454 | /* PREFIX_VEX_0F3A31 */ |
6455 | { | |
6456 | { Bad_Opcode }, | |
6457 | { Bad_Opcode }, | |
6458 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, | |
6459 | }, | |
6460 | ||
43234a1e L |
6461 | /* PREFIX_VEX_0F3A32 */ |
6462 | { | |
6463 | { Bad_Opcode }, | |
6464 | { Bad_Opcode }, | |
6465 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6466 | }, | |
6467 | ||
1ba585e8 IT |
6468 | /* PREFIX_VEX_0F3A33 */ |
6469 | { | |
6470 | { Bad_Opcode }, | |
6471 | { Bad_Opcode }, | |
6472 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, | |
6473 | }, | |
6474 | ||
6c30d220 L |
6475 | /* PREFIX_VEX_0F3A38 */ |
6476 | { | |
6477 | { Bad_Opcode }, | |
6478 | { Bad_Opcode }, | |
6479 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6480 | }, | |
6481 | ||
6482 | /* PREFIX_VEX_0F3A39 */ | |
6483 | { | |
6484 | { Bad_Opcode }, | |
6485 | { Bad_Opcode }, | |
6486 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6487 | }, | |
6488 | ||
592a252b | 6489 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6490 | { |
592d1631 L |
6491 | { Bad_Opcode }, |
6492 | { Bad_Opcode }, | |
ec6f095a | 6493 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6494 | }, |
6495 | ||
592a252b | 6496 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6497 | { |
592d1631 L |
6498 | { Bad_Opcode }, |
6499 | { Bad_Opcode }, | |
592a252b | 6500 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6501 | }, |
6502 | ||
592a252b | 6503 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6504 | { |
592d1631 L |
6505 | { Bad_Opcode }, |
6506 | { Bad_Opcode }, | |
ec6f095a | 6507 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6508 | }, |
6509 | ||
592a252b | 6510 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6511 | { |
592d1631 L |
6512 | { Bad_Opcode }, |
6513 | { Bad_Opcode }, | |
ff1982d5 | 6514 | { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 }, |
ce2f5b3c L |
6515 | }, |
6516 | ||
6c30d220 L |
6517 | /* PREFIX_VEX_0F3A46 */ |
6518 | { | |
6519 | { Bad_Opcode }, | |
6520 | { Bad_Opcode }, | |
6521 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6522 | }, | |
6523 | ||
592a252b | 6524 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6525 | { |
6526 | { Bad_Opcode }, | |
6527 | { Bad_Opcode }, | |
592a252b | 6528 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
6529 | }, |
6530 | ||
592a252b | 6531 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6532 | { |
6533 | { Bad_Opcode }, | |
6534 | { Bad_Opcode }, | |
592a252b | 6535 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
6536 | }, |
6537 | ||
592a252b | 6538 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6539 | { |
592d1631 L |
6540 | { Bad_Opcode }, |
6541 | { Bad_Opcode }, | |
592a252b | 6542 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6543 | }, |
6544 | ||
592a252b | 6545 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6546 | { |
592d1631 L |
6547 | { Bad_Opcode }, |
6548 | { Bad_Opcode }, | |
592a252b | 6549 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6550 | }, |
6551 | ||
592a252b | 6552 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6553 | { |
592d1631 L |
6554 | { Bad_Opcode }, |
6555 | { Bad_Opcode }, | |
6c30d220 | 6556 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6557 | }, |
6558 | ||
592a252b | 6559 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6560 | { |
592d1631 L |
6561 | { Bad_Opcode }, |
6562 | { Bad_Opcode }, | |
3a2430e0 | 6563 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6564 | }, |
6565 | ||
592a252b | 6566 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6567 | { |
592d1631 L |
6568 | { Bad_Opcode }, |
6569 | { Bad_Opcode }, | |
3a2430e0 | 6570 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6571 | }, |
6572 | ||
592a252b | 6573 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6574 | { |
592d1631 L |
6575 | { Bad_Opcode }, |
6576 | { Bad_Opcode }, | |
3a2430e0 | 6577 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6578 | }, |
6579 | ||
592a252b | 6580 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6581 | { |
592d1631 L |
6582 | { Bad_Opcode }, |
6583 | { Bad_Opcode }, | |
3a2430e0 | 6584 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6585 | }, |
6586 | ||
592a252b | 6587 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6588 | { |
592d1631 L |
6589 | { Bad_Opcode }, |
6590 | { Bad_Opcode }, | |
592a252b | 6591 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6592 | { Bad_Opcode }, |
c0f3af97 L |
6593 | }, |
6594 | ||
592a252b | 6595 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6596 | { |
592d1631 L |
6597 | { Bad_Opcode }, |
6598 | { Bad_Opcode }, | |
592a252b | 6599 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6600 | }, |
6601 | ||
592a252b | 6602 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6603 | { |
592d1631 L |
6604 | { Bad_Opcode }, |
6605 | { Bad_Opcode }, | |
592a252b | 6606 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6607 | }, |
6608 | ||
592a252b | 6609 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6610 | { |
592d1631 L |
6611 | { Bad_Opcode }, |
6612 | { Bad_Opcode }, | |
592a252b | 6613 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6614 | }, |
a5ff0eb2 | 6615 | |
592a252b | 6616 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6617 | { |
592d1631 L |
6618 | { Bad_Opcode }, |
6619 | { Bad_Opcode }, | |
3a2430e0 | 6620 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6621 | }, |
6622 | ||
592a252b | 6623 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6624 | { |
592d1631 L |
6625 | { Bad_Opcode }, |
6626 | { Bad_Opcode }, | |
3a2430e0 | 6627 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6628 | }, |
6629 | ||
592a252b | 6630 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6631 | { |
592d1631 L |
6632 | { Bad_Opcode }, |
6633 | { Bad_Opcode }, | |
592a252b | 6634 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
6635 | }, |
6636 | ||
592a252b | 6637 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6638 | { |
592d1631 L |
6639 | { Bad_Opcode }, |
6640 | { Bad_Opcode }, | |
592a252b | 6641 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
6642 | }, |
6643 | ||
592a252b | 6644 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6645 | { |
592d1631 L |
6646 | { Bad_Opcode }, |
6647 | { Bad_Opcode }, | |
3a2430e0 | 6648 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6649 | }, |
6650 | ||
592a252b | 6651 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6652 | { |
592d1631 L |
6653 | { Bad_Opcode }, |
6654 | { Bad_Opcode }, | |
3a2430e0 | 6655 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6656 | }, |
6657 | ||
592a252b | 6658 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6659 | { |
592d1631 L |
6660 | { Bad_Opcode }, |
6661 | { Bad_Opcode }, | |
592a252b | 6662 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
6663 | }, |
6664 | ||
592a252b | 6665 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6666 | { |
592d1631 L |
6667 | { Bad_Opcode }, |
6668 | { Bad_Opcode }, | |
592a252b | 6669 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
6670 | }, |
6671 | ||
592a252b | 6672 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6673 | { |
592d1631 L |
6674 | { Bad_Opcode }, |
6675 | { Bad_Opcode }, | |
3a2430e0 | 6676 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6677 | }, |
6678 | ||
592a252b | 6679 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6680 | { |
592d1631 L |
6681 | { Bad_Opcode }, |
6682 | { Bad_Opcode }, | |
3a2430e0 | 6683 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6684 | }, |
6685 | ||
592a252b | 6686 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6687 | { |
592d1631 L |
6688 | { Bad_Opcode }, |
6689 | { Bad_Opcode }, | |
592a252b | 6690 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
6691 | }, |
6692 | ||
592a252b | 6693 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6694 | { |
592d1631 L |
6695 | { Bad_Opcode }, |
6696 | { Bad_Opcode }, | |
592a252b | 6697 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
6698 | }, |
6699 | ||
592a252b | 6700 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6701 | { |
592d1631 L |
6702 | { Bad_Opcode }, |
6703 | { Bad_Opcode }, | |
3a2430e0 | 6704 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 6705 | { Bad_Opcode }, |
922d8de8 DR |
6706 | }, |
6707 | ||
592a252b | 6708 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6709 | { |
592d1631 L |
6710 | { Bad_Opcode }, |
6711 | { Bad_Opcode }, | |
3a2430e0 | 6712 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6713 | }, |
6714 | ||
592a252b | 6715 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6716 | { |
592d1631 L |
6717 | { Bad_Opcode }, |
6718 | { Bad_Opcode }, | |
592a252b | 6719 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
6720 | }, |
6721 | ||
592a252b | 6722 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6723 | { |
592d1631 L |
6724 | { Bad_Opcode }, |
6725 | { Bad_Opcode }, | |
592a252b | 6726 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
6727 | }, |
6728 | ||
48521003 IT |
6729 | /* PREFIX_VEX_0F3ACE */ |
6730 | { | |
6731 | { Bad_Opcode }, | |
6732 | { Bad_Opcode }, | |
6733 | { VEX_W_TABLE (VEX_W_0F3ACE_P_2) }, | |
6734 | }, | |
6735 | ||
6736 | /* PREFIX_VEX_0F3ACF */ | |
6737 | { | |
6738 | { Bad_Opcode }, | |
6739 | { Bad_Opcode }, | |
6740 | { VEX_W_TABLE (VEX_W_0F3ACF_P_2) }, | |
6741 | }, | |
6742 | ||
592a252b | 6743 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6744 | { |
592d1631 L |
6745 | { Bad_Opcode }, |
6746 | { Bad_Opcode }, | |
592a252b | 6747 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6748 | }, |
6c30d220 L |
6749 | |
6750 | /* PREFIX_VEX_0F3AF0 */ | |
6751 | { | |
6752 | { Bad_Opcode }, | |
6753 | { Bad_Opcode }, | |
6754 | { Bad_Opcode }, | |
6755 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
6756 | }, | |
43234a1e | 6757 | |
ad692897 | 6758 | #include "i386-dis-evex-prefix.h" |
c0f3af97 L |
6759 | }; |
6760 | ||
6761 | static const struct dis386 x86_64_table[][2] = { | |
6762 | /* X86_64_06 */ | |
6763 | { | |
bf890a93 | 6764 | { "pushP", { es }, 0 }, |
c0f3af97 L |
6765 | }, |
6766 | ||
6767 | /* X86_64_07 */ | |
6768 | { | |
bf890a93 | 6769 | { "popP", { es }, 0 }, |
c0f3af97 L |
6770 | }, |
6771 | ||
1673df32 | 6772 | /* X86_64_0E */ |
c0f3af97 | 6773 | { |
bf890a93 | 6774 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
6775 | }, |
6776 | ||
6777 | /* X86_64_16 */ | |
6778 | { | |
bf890a93 | 6779 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
6780 | }, |
6781 | ||
6782 | /* X86_64_17 */ | |
6783 | { | |
bf890a93 | 6784 | { "popP", { ss }, 0 }, |
c0f3af97 L |
6785 | }, |
6786 | ||
6787 | /* X86_64_1E */ | |
6788 | { | |
bf890a93 | 6789 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
6790 | }, |
6791 | ||
6792 | /* X86_64_1F */ | |
6793 | { | |
bf890a93 | 6794 | { "popP", { ds }, 0 }, |
c0f3af97 L |
6795 | }, |
6796 | ||
6797 | /* X86_64_27 */ | |
6798 | { | |
bf890a93 | 6799 | { "daa", { XX }, 0 }, |
c0f3af97 L |
6800 | }, |
6801 | ||
6802 | /* X86_64_2F */ | |
6803 | { | |
bf890a93 | 6804 | { "das", { XX }, 0 }, |
c0f3af97 L |
6805 | }, |
6806 | ||
6807 | /* X86_64_37 */ | |
6808 | { | |
bf890a93 | 6809 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
6810 | }, |
6811 | ||
6812 | /* X86_64_3F */ | |
6813 | { | |
bf890a93 | 6814 | { "aas", { XX }, 0 }, |
c0f3af97 L |
6815 | }, |
6816 | ||
6817 | /* X86_64_60 */ | |
6818 | { | |
bf890a93 | 6819 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
6820 | }, |
6821 | ||
6822 | /* X86_64_61 */ | |
6823 | { | |
bf890a93 | 6824 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
6825 | }, |
6826 | ||
6827 | /* X86_64_62 */ | |
6828 | { | |
6829 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 6830 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
6831 | }, |
6832 | ||
6833 | /* X86_64_63 */ | |
6834 | { | |
bf890a93 | 6835 | { "arpl", { Ew, Gw }, 0 }, |
bc31405e | 6836 | { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 }, |
c0f3af97 L |
6837 | }, |
6838 | ||
6839 | /* X86_64_6D */ | |
6840 | { | |
bf890a93 IT |
6841 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
6842 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
6843 | }, |
6844 | ||
6845 | /* X86_64_6F */ | |
6846 | { | |
bf890a93 IT |
6847 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
6848 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
6849 | }, |
6850 | ||
d039fef3 | 6851 | /* X86_64_82 */ |
8b89fe14 | 6852 | { |
de194d85 | 6853 | /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ |
d039fef3 | 6854 | { REG_TABLE (REG_80) }, |
8b89fe14 L |
6855 | }, |
6856 | ||
c0f3af97 L |
6857 | /* X86_64_9A */ |
6858 | { | |
8f570d62 | 6859 | { "{l|}call{T|}", { Ap }, 0 }, |
c0f3af97 L |
6860 | }, |
6861 | ||
aeab2b26 JB |
6862 | /* X86_64_C2 */ |
6863 | { | |
6864 | { "retP", { Iw, BND }, 0 }, | |
6865 | { "ret@", { Iw, BND }, 0 }, | |
6866 | }, | |
6867 | ||
6868 | /* X86_64_C3 */ | |
6869 | { | |
6870 | { "retP", { BND }, 0 }, | |
6871 | { "ret@", { BND }, 0 }, | |
6872 | }, | |
6873 | ||
c0f3af97 L |
6874 | /* X86_64_C4 */ |
6875 | { | |
6876 | { MOD_TABLE (MOD_C4_32BIT) }, | |
6877 | { VEX_C4_TABLE (VEX_0F) }, | |
6878 | }, | |
6879 | ||
6880 | /* X86_64_C5 */ | |
6881 | { | |
6882 | { MOD_TABLE (MOD_C5_32BIT) }, | |
6883 | { VEX_C5_TABLE (VEX_0F) }, | |
6884 | }, | |
6885 | ||
6886 | /* X86_64_CE */ | |
6887 | { | |
bf890a93 | 6888 | { "into", { XX }, 0 }, |
c0f3af97 L |
6889 | }, |
6890 | ||
6891 | /* X86_64_D4 */ | |
6892 | { | |
bf890a93 | 6893 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
6894 | }, |
6895 | ||
6896 | /* X86_64_D5 */ | |
6897 | { | |
bf890a93 | 6898 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
6899 | }, |
6900 | ||
a72d2af2 L |
6901 | /* X86_64_E8 */ |
6902 | { | |
6903 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 6904 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
6905 | }, |
6906 | ||
6907 | /* X86_64_E9 */ | |
6908 | { | |
6909 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 6910 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
6911 | }, |
6912 | ||
c0f3af97 L |
6913 | /* X86_64_EA */ |
6914 | { | |
8f570d62 | 6915 | { "{l|}jmp{T|}", { Ap }, 0 }, |
c0f3af97 L |
6916 | }, |
6917 | ||
6918 | /* X86_64_0F01_REG_0 */ | |
6919 | { | |
d1c36125 | 6920 | { "sgdt{Q|Q}", { M }, 0 }, |
bf890a93 | 6921 | { "sgdt", { M }, 0 }, |
c0f3af97 L |
6922 | }, |
6923 | ||
6924 | /* X86_64_0F01_REG_1 */ | |
6925 | { | |
d1c36125 | 6926 | { "sidt{Q|Q}", { M }, 0 }, |
bf890a93 | 6927 | { "sidt", { M }, 0 }, |
c0f3af97 L |
6928 | }, |
6929 | ||
6930 | /* X86_64_0F01_REG_2 */ | |
6931 | { | |
bf890a93 IT |
6932 | { "lgdt{Q|Q}", { M }, 0 }, |
6933 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
6934 | }, |
6935 | ||
6936 | /* X86_64_0F01_REG_3 */ | |
6937 | { | |
bf890a93 IT |
6938 | { "lidt{Q|Q}", { M }, 0 }, |
6939 | { "lidt", { M }, 0 }, | |
c0f3af97 L |
6940 | }, |
6941 | }; | |
6942 | ||
6943 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
6944 | |
6945 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
6946 | { |
6947 | /* 00 */ | |
507bd325 L |
6948 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
6949 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
6950 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
6951 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
6952 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
6953 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
6954 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
6955 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 6956 | /* 08 */ |
507bd325 L |
6957 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
6958 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
6959 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
6960 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
6961 | { Bad_Opcode }, |
6962 | { Bad_Opcode }, | |
6963 | { Bad_Opcode }, | |
6964 | { Bad_Opcode }, | |
f88c9eb0 SP |
6965 | /* 10 */ |
6966 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
6967 | { Bad_Opcode }, |
6968 | { Bad_Opcode }, | |
6969 | { Bad_Opcode }, | |
f88c9eb0 SP |
6970 | { PREFIX_TABLE (PREFIX_0F3814) }, |
6971 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 6972 | { Bad_Opcode }, |
f88c9eb0 SP |
6973 | { PREFIX_TABLE (PREFIX_0F3817) }, |
6974 | /* 18 */ | |
592d1631 L |
6975 | { Bad_Opcode }, |
6976 | { Bad_Opcode }, | |
6977 | { Bad_Opcode }, | |
6978 | { Bad_Opcode }, | |
507bd325 L |
6979 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
6980 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
6981 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 6982 | { Bad_Opcode }, |
f88c9eb0 SP |
6983 | /* 20 */ |
6984 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
6985 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
6986 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
6987 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
6988 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
6989 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
6990 | { Bad_Opcode }, |
6991 | { Bad_Opcode }, | |
f88c9eb0 SP |
6992 | /* 28 */ |
6993 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
6994 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
6995 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
6996 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
6997 | { Bad_Opcode }, |
6998 | { Bad_Opcode }, | |
6999 | { Bad_Opcode }, | |
7000 | { Bad_Opcode }, | |
f88c9eb0 SP |
7001 | /* 30 */ |
7002 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
7003 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
7004 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
7005 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
7006 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
7007 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 7008 | { Bad_Opcode }, |
f88c9eb0 SP |
7009 | { PREFIX_TABLE (PREFIX_0F3837) }, |
7010 | /* 38 */ | |
7011 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
7012 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
7013 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
7014 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
7015 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
7016 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
7017 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
7018 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
7019 | /* 40 */ | |
7020 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
7021 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
7022 | { Bad_Opcode }, |
7023 | { Bad_Opcode }, | |
7024 | { Bad_Opcode }, | |
7025 | { Bad_Opcode }, | |
7026 | { Bad_Opcode }, | |
7027 | { Bad_Opcode }, | |
f88c9eb0 | 7028 | /* 48 */ |
592d1631 L |
7029 | { Bad_Opcode }, |
7030 | { Bad_Opcode }, | |
7031 | { Bad_Opcode }, | |
7032 | { Bad_Opcode }, | |
7033 | { Bad_Opcode }, | |
7034 | { Bad_Opcode }, | |
7035 | { Bad_Opcode }, | |
7036 | { Bad_Opcode }, | |
f88c9eb0 | 7037 | /* 50 */ |
592d1631 L |
7038 | { Bad_Opcode }, |
7039 | { Bad_Opcode }, | |
7040 | { Bad_Opcode }, | |
7041 | { Bad_Opcode }, | |
7042 | { Bad_Opcode }, | |
7043 | { Bad_Opcode }, | |
7044 | { Bad_Opcode }, | |
7045 | { Bad_Opcode }, | |
f88c9eb0 | 7046 | /* 58 */ |
592d1631 L |
7047 | { Bad_Opcode }, |
7048 | { Bad_Opcode }, | |
7049 | { Bad_Opcode }, | |
7050 | { Bad_Opcode }, | |
7051 | { Bad_Opcode }, | |
7052 | { Bad_Opcode }, | |
7053 | { Bad_Opcode }, | |
7054 | { Bad_Opcode }, | |
f88c9eb0 | 7055 | /* 60 */ |
592d1631 L |
7056 | { Bad_Opcode }, |
7057 | { Bad_Opcode }, | |
7058 | { Bad_Opcode }, | |
7059 | { Bad_Opcode }, | |
7060 | { Bad_Opcode }, | |
7061 | { Bad_Opcode }, | |
7062 | { Bad_Opcode }, | |
7063 | { Bad_Opcode }, | |
f88c9eb0 | 7064 | /* 68 */ |
592d1631 L |
7065 | { Bad_Opcode }, |
7066 | { Bad_Opcode }, | |
7067 | { Bad_Opcode }, | |
7068 | { Bad_Opcode }, | |
7069 | { Bad_Opcode }, | |
7070 | { Bad_Opcode }, | |
7071 | { Bad_Opcode }, | |
7072 | { Bad_Opcode }, | |
f88c9eb0 | 7073 | /* 70 */ |
592d1631 L |
7074 | { Bad_Opcode }, |
7075 | { Bad_Opcode }, | |
7076 | { Bad_Opcode }, | |
7077 | { Bad_Opcode }, | |
7078 | { Bad_Opcode }, | |
7079 | { Bad_Opcode }, | |
7080 | { Bad_Opcode }, | |
7081 | { Bad_Opcode }, | |
f88c9eb0 | 7082 | /* 78 */ |
592d1631 L |
7083 | { Bad_Opcode }, |
7084 | { Bad_Opcode }, | |
7085 | { Bad_Opcode }, | |
7086 | { Bad_Opcode }, | |
7087 | { Bad_Opcode }, | |
7088 | { Bad_Opcode }, | |
7089 | { Bad_Opcode }, | |
7090 | { Bad_Opcode }, | |
f88c9eb0 SP |
7091 | /* 80 */ |
7092 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
7093 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 7094 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
7095 | { Bad_Opcode }, |
7096 | { Bad_Opcode }, | |
7097 | { Bad_Opcode }, | |
7098 | { Bad_Opcode }, | |
7099 | { Bad_Opcode }, | |
f88c9eb0 | 7100 | /* 88 */ |
592d1631 L |
7101 | { Bad_Opcode }, |
7102 | { Bad_Opcode }, | |
7103 | { Bad_Opcode }, | |
7104 | { Bad_Opcode }, | |
7105 | { Bad_Opcode }, | |
7106 | { Bad_Opcode }, | |
7107 | { Bad_Opcode }, | |
7108 | { Bad_Opcode }, | |
f88c9eb0 | 7109 | /* 90 */ |
592d1631 L |
7110 | { Bad_Opcode }, |
7111 | { Bad_Opcode }, | |
7112 | { Bad_Opcode }, | |
7113 | { Bad_Opcode }, | |
7114 | { Bad_Opcode }, | |
7115 | { Bad_Opcode }, | |
7116 | { Bad_Opcode }, | |
7117 | { Bad_Opcode }, | |
f88c9eb0 | 7118 | /* 98 */ |
592d1631 L |
7119 | { Bad_Opcode }, |
7120 | { Bad_Opcode }, | |
7121 | { Bad_Opcode }, | |
7122 | { Bad_Opcode }, | |
7123 | { Bad_Opcode }, | |
7124 | { Bad_Opcode }, | |
7125 | { Bad_Opcode }, | |
7126 | { Bad_Opcode }, | |
f88c9eb0 | 7127 | /* a0 */ |
592d1631 L |
7128 | { Bad_Opcode }, |
7129 | { Bad_Opcode }, | |
7130 | { Bad_Opcode }, | |
7131 | { Bad_Opcode }, | |
7132 | { Bad_Opcode }, | |
7133 | { Bad_Opcode }, | |
7134 | { Bad_Opcode }, | |
7135 | { Bad_Opcode }, | |
f88c9eb0 | 7136 | /* a8 */ |
592d1631 L |
7137 | { Bad_Opcode }, |
7138 | { Bad_Opcode }, | |
7139 | { Bad_Opcode }, | |
7140 | { Bad_Opcode }, | |
7141 | { Bad_Opcode }, | |
7142 | { Bad_Opcode }, | |
7143 | { Bad_Opcode }, | |
7144 | { Bad_Opcode }, | |
f88c9eb0 | 7145 | /* b0 */ |
592d1631 L |
7146 | { Bad_Opcode }, |
7147 | { Bad_Opcode }, | |
7148 | { Bad_Opcode }, | |
7149 | { Bad_Opcode }, | |
7150 | { Bad_Opcode }, | |
7151 | { Bad_Opcode }, | |
7152 | { Bad_Opcode }, | |
7153 | { Bad_Opcode }, | |
f88c9eb0 | 7154 | /* b8 */ |
592d1631 L |
7155 | { Bad_Opcode }, |
7156 | { Bad_Opcode }, | |
7157 | { Bad_Opcode }, | |
7158 | { Bad_Opcode }, | |
7159 | { Bad_Opcode }, | |
7160 | { Bad_Opcode }, | |
7161 | { Bad_Opcode }, | |
7162 | { Bad_Opcode }, | |
f88c9eb0 | 7163 | /* c0 */ |
592d1631 L |
7164 | { Bad_Opcode }, |
7165 | { Bad_Opcode }, | |
7166 | { Bad_Opcode }, | |
7167 | { Bad_Opcode }, | |
7168 | { Bad_Opcode }, | |
7169 | { Bad_Opcode }, | |
7170 | { Bad_Opcode }, | |
7171 | { Bad_Opcode }, | |
f88c9eb0 | 7172 | /* c8 */ |
a0046408 L |
7173 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7174 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
7175 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
7176 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
7177 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
7178 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 | 7179 | { Bad_Opcode }, |
48521003 | 7180 | { PREFIX_TABLE (PREFIX_0F38CF) }, |
f88c9eb0 | 7181 | /* d0 */ |
592d1631 L |
7182 | { Bad_Opcode }, |
7183 | { Bad_Opcode }, | |
7184 | { Bad_Opcode }, | |
7185 | { Bad_Opcode }, | |
7186 | { Bad_Opcode }, | |
7187 | { Bad_Opcode }, | |
7188 | { Bad_Opcode }, | |
7189 | { Bad_Opcode }, | |
f88c9eb0 | 7190 | /* d8 */ |
592d1631 L |
7191 | { Bad_Opcode }, |
7192 | { Bad_Opcode }, | |
7193 | { Bad_Opcode }, | |
f88c9eb0 SP |
7194 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7195 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
7196 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
7197 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
7198 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
7199 | /* e0 */ | |
592d1631 L |
7200 | { Bad_Opcode }, |
7201 | { Bad_Opcode }, | |
7202 | { Bad_Opcode }, | |
7203 | { Bad_Opcode }, | |
7204 | { Bad_Opcode }, | |
7205 | { Bad_Opcode }, | |
7206 | { Bad_Opcode }, | |
7207 | { Bad_Opcode }, | |
f88c9eb0 | 7208 | /* e8 */ |
592d1631 L |
7209 | { Bad_Opcode }, |
7210 | { Bad_Opcode }, | |
7211 | { Bad_Opcode }, | |
7212 | { Bad_Opcode }, | |
7213 | { Bad_Opcode }, | |
7214 | { Bad_Opcode }, | |
7215 | { Bad_Opcode }, | |
7216 | { Bad_Opcode }, | |
f88c9eb0 SP |
7217 | /* f0 */ |
7218 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
7219 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
7220 | { Bad_Opcode }, |
7221 | { Bad_Opcode }, | |
7222 | { Bad_Opcode }, | |
603555e5 | 7223 | { PREFIX_TABLE (PREFIX_0F38F5) }, |
e2e1fcde | 7224 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 7225 | { Bad_Opcode }, |
f88c9eb0 | 7226 | /* f8 */ |
c0a30a9f L |
7227 | { PREFIX_TABLE (PREFIX_0F38F8) }, |
7228 | { PREFIX_TABLE (PREFIX_0F38F9) }, | |
592d1631 L |
7229 | { Bad_Opcode }, |
7230 | { Bad_Opcode }, | |
7231 | { Bad_Opcode }, | |
7232 | { Bad_Opcode }, | |
7233 | { Bad_Opcode }, | |
7234 | { Bad_Opcode }, | |
f88c9eb0 SP |
7235 | }, |
7236 | /* THREE_BYTE_0F3A */ | |
7237 | { | |
7238 | /* 00 */ | |
592d1631 L |
7239 | { Bad_Opcode }, |
7240 | { Bad_Opcode }, | |
7241 | { Bad_Opcode }, | |
7242 | { Bad_Opcode }, | |
7243 | { Bad_Opcode }, | |
7244 | { Bad_Opcode }, | |
7245 | { Bad_Opcode }, | |
7246 | { Bad_Opcode }, | |
f88c9eb0 SP |
7247 | /* 08 */ |
7248 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
7249 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
7250 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
7251 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
7252 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
7253 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
7254 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
507bd325 | 7255 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 7256 | /* 10 */ |
592d1631 L |
7257 | { Bad_Opcode }, |
7258 | { Bad_Opcode }, | |
7259 | { Bad_Opcode }, | |
7260 | { Bad_Opcode }, | |
f88c9eb0 SP |
7261 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7262 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
7263 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
7264 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
7265 | /* 18 */ | |
592d1631 L |
7266 | { Bad_Opcode }, |
7267 | { Bad_Opcode }, | |
7268 | { Bad_Opcode }, | |
7269 | { Bad_Opcode }, | |
7270 | { Bad_Opcode }, | |
7271 | { Bad_Opcode }, | |
7272 | { Bad_Opcode }, | |
7273 | { Bad_Opcode }, | |
f88c9eb0 SP |
7274 | /* 20 */ |
7275 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
7276 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
7277 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
7278 | { Bad_Opcode }, |
7279 | { Bad_Opcode }, | |
7280 | { Bad_Opcode }, | |
7281 | { Bad_Opcode }, | |
7282 | { Bad_Opcode }, | |
f88c9eb0 | 7283 | /* 28 */ |
592d1631 L |
7284 | { Bad_Opcode }, |
7285 | { Bad_Opcode }, | |
7286 | { Bad_Opcode }, | |
7287 | { Bad_Opcode }, | |
7288 | { Bad_Opcode }, | |
7289 | { Bad_Opcode }, | |
7290 | { Bad_Opcode }, | |
7291 | { Bad_Opcode }, | |
f88c9eb0 | 7292 | /* 30 */ |
592d1631 L |
7293 | { Bad_Opcode }, |
7294 | { Bad_Opcode }, | |
7295 | { Bad_Opcode }, | |
7296 | { Bad_Opcode }, | |
7297 | { Bad_Opcode }, | |
7298 | { Bad_Opcode }, | |
7299 | { Bad_Opcode }, | |
7300 | { Bad_Opcode }, | |
f88c9eb0 | 7301 | /* 38 */ |
592d1631 L |
7302 | { Bad_Opcode }, |
7303 | { Bad_Opcode }, | |
7304 | { Bad_Opcode }, | |
7305 | { Bad_Opcode }, | |
7306 | { Bad_Opcode }, | |
7307 | { Bad_Opcode }, | |
7308 | { Bad_Opcode }, | |
7309 | { Bad_Opcode }, | |
f88c9eb0 SP |
7310 | /* 40 */ |
7311 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
7312 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
7313 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 7314 | { Bad_Opcode }, |
f88c9eb0 | 7315 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
7316 | { Bad_Opcode }, |
7317 | { Bad_Opcode }, | |
7318 | { Bad_Opcode }, | |
f88c9eb0 | 7319 | /* 48 */ |
592d1631 L |
7320 | { Bad_Opcode }, |
7321 | { Bad_Opcode }, | |
7322 | { Bad_Opcode }, | |
7323 | { Bad_Opcode }, | |
7324 | { Bad_Opcode }, | |
7325 | { Bad_Opcode }, | |
7326 | { Bad_Opcode }, | |
7327 | { Bad_Opcode }, | |
f88c9eb0 | 7328 | /* 50 */ |
592d1631 L |
7329 | { Bad_Opcode }, |
7330 | { Bad_Opcode }, | |
7331 | { Bad_Opcode }, | |
7332 | { Bad_Opcode }, | |
7333 | { Bad_Opcode }, | |
7334 | { Bad_Opcode }, | |
7335 | { Bad_Opcode }, | |
7336 | { Bad_Opcode }, | |
f88c9eb0 | 7337 | /* 58 */ |
592d1631 L |
7338 | { Bad_Opcode }, |
7339 | { Bad_Opcode }, | |
7340 | { Bad_Opcode }, | |
7341 | { Bad_Opcode }, | |
7342 | { Bad_Opcode }, | |
7343 | { Bad_Opcode }, | |
7344 | { Bad_Opcode }, | |
7345 | { Bad_Opcode }, | |
f88c9eb0 SP |
7346 | /* 60 */ |
7347 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
7348 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
7349 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
7350 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
7351 | { Bad_Opcode }, |
7352 | { Bad_Opcode }, | |
7353 | { Bad_Opcode }, | |
7354 | { Bad_Opcode }, | |
f88c9eb0 | 7355 | /* 68 */ |
592d1631 L |
7356 | { Bad_Opcode }, |
7357 | { Bad_Opcode }, | |
7358 | { Bad_Opcode }, | |
7359 | { Bad_Opcode }, | |
7360 | { Bad_Opcode }, | |
7361 | { Bad_Opcode }, | |
7362 | { Bad_Opcode }, | |
7363 | { Bad_Opcode }, | |
f88c9eb0 | 7364 | /* 70 */ |
592d1631 L |
7365 | { Bad_Opcode }, |
7366 | { Bad_Opcode }, | |
7367 | { Bad_Opcode }, | |
7368 | { Bad_Opcode }, | |
7369 | { Bad_Opcode }, | |
7370 | { Bad_Opcode }, | |
7371 | { Bad_Opcode }, | |
7372 | { Bad_Opcode }, | |
f88c9eb0 | 7373 | /* 78 */ |
592d1631 L |
7374 | { Bad_Opcode }, |
7375 | { Bad_Opcode }, | |
7376 | { Bad_Opcode }, | |
7377 | { Bad_Opcode }, | |
7378 | { Bad_Opcode }, | |
7379 | { Bad_Opcode }, | |
7380 | { Bad_Opcode }, | |
7381 | { Bad_Opcode }, | |
f88c9eb0 | 7382 | /* 80 */ |
592d1631 L |
7383 | { Bad_Opcode }, |
7384 | { Bad_Opcode }, | |
7385 | { Bad_Opcode }, | |
7386 | { Bad_Opcode }, | |
7387 | { Bad_Opcode }, | |
7388 | { Bad_Opcode }, | |
7389 | { Bad_Opcode }, | |
7390 | { Bad_Opcode }, | |
f88c9eb0 | 7391 | /* 88 */ |
592d1631 L |
7392 | { Bad_Opcode }, |
7393 | { Bad_Opcode }, | |
7394 | { Bad_Opcode }, | |
7395 | { Bad_Opcode }, | |
7396 | { Bad_Opcode }, | |
7397 | { Bad_Opcode }, | |
7398 | { Bad_Opcode }, | |
7399 | { Bad_Opcode }, | |
f88c9eb0 | 7400 | /* 90 */ |
592d1631 L |
7401 | { Bad_Opcode }, |
7402 | { Bad_Opcode }, | |
7403 | { Bad_Opcode }, | |
7404 | { Bad_Opcode }, | |
7405 | { Bad_Opcode }, | |
7406 | { Bad_Opcode }, | |
7407 | { Bad_Opcode }, | |
7408 | { Bad_Opcode }, | |
f88c9eb0 | 7409 | /* 98 */ |
592d1631 L |
7410 | { Bad_Opcode }, |
7411 | { Bad_Opcode }, | |
7412 | { Bad_Opcode }, | |
7413 | { Bad_Opcode }, | |
7414 | { Bad_Opcode }, | |
7415 | { Bad_Opcode }, | |
7416 | { Bad_Opcode }, | |
7417 | { Bad_Opcode }, | |
f88c9eb0 | 7418 | /* a0 */ |
592d1631 L |
7419 | { Bad_Opcode }, |
7420 | { Bad_Opcode }, | |
7421 | { Bad_Opcode }, | |
7422 | { Bad_Opcode }, | |
7423 | { Bad_Opcode }, | |
7424 | { Bad_Opcode }, | |
7425 | { Bad_Opcode }, | |
7426 | { Bad_Opcode }, | |
f88c9eb0 | 7427 | /* a8 */ |
592d1631 L |
7428 | { Bad_Opcode }, |
7429 | { Bad_Opcode }, | |
7430 | { Bad_Opcode }, | |
7431 | { Bad_Opcode }, | |
7432 | { Bad_Opcode }, | |
7433 | { Bad_Opcode }, | |
7434 | { Bad_Opcode }, | |
7435 | { Bad_Opcode }, | |
f88c9eb0 | 7436 | /* b0 */ |
592d1631 L |
7437 | { Bad_Opcode }, |
7438 | { Bad_Opcode }, | |
7439 | { Bad_Opcode }, | |
7440 | { Bad_Opcode }, | |
7441 | { Bad_Opcode }, | |
7442 | { Bad_Opcode }, | |
7443 | { Bad_Opcode }, | |
7444 | { Bad_Opcode }, | |
f88c9eb0 | 7445 | /* b8 */ |
592d1631 L |
7446 | { Bad_Opcode }, |
7447 | { Bad_Opcode }, | |
7448 | { Bad_Opcode }, | |
7449 | { Bad_Opcode }, | |
7450 | { Bad_Opcode }, | |
7451 | { Bad_Opcode }, | |
7452 | { Bad_Opcode }, | |
7453 | { Bad_Opcode }, | |
f88c9eb0 | 7454 | /* c0 */ |
592d1631 L |
7455 | { Bad_Opcode }, |
7456 | { Bad_Opcode }, | |
7457 | { Bad_Opcode }, | |
7458 | { Bad_Opcode }, | |
7459 | { Bad_Opcode }, | |
7460 | { Bad_Opcode }, | |
7461 | { Bad_Opcode }, | |
7462 | { Bad_Opcode }, | |
f88c9eb0 | 7463 | /* c8 */ |
592d1631 L |
7464 | { Bad_Opcode }, |
7465 | { Bad_Opcode }, | |
7466 | { Bad_Opcode }, | |
7467 | { Bad_Opcode }, | |
a0046408 | 7468 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 | 7469 | { Bad_Opcode }, |
48521003 IT |
7470 | { PREFIX_TABLE (PREFIX_0F3ACE) }, |
7471 | { PREFIX_TABLE (PREFIX_0F3ACF) }, | |
f88c9eb0 | 7472 | /* d0 */ |
592d1631 L |
7473 | { Bad_Opcode }, |
7474 | { Bad_Opcode }, | |
7475 | { Bad_Opcode }, | |
7476 | { Bad_Opcode }, | |
7477 | { Bad_Opcode }, | |
7478 | { Bad_Opcode }, | |
7479 | { Bad_Opcode }, | |
7480 | { Bad_Opcode }, | |
f88c9eb0 | 7481 | /* d8 */ |
592d1631 L |
7482 | { Bad_Opcode }, |
7483 | { Bad_Opcode }, | |
7484 | { Bad_Opcode }, | |
7485 | { Bad_Opcode }, | |
7486 | { Bad_Opcode }, | |
7487 | { Bad_Opcode }, | |
7488 | { Bad_Opcode }, | |
f88c9eb0 SP |
7489 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7490 | /* e0 */ | |
592d1631 L |
7491 | { Bad_Opcode }, |
7492 | { Bad_Opcode }, | |
7493 | { Bad_Opcode }, | |
7494 | { Bad_Opcode }, | |
7495 | { Bad_Opcode }, | |
592d1631 L |
7496 | { Bad_Opcode }, |
7497 | { Bad_Opcode }, | |
7498 | { Bad_Opcode }, | |
85f10a01 | 7499 | /* e8 */ |
592d1631 L |
7500 | { Bad_Opcode }, |
7501 | { Bad_Opcode }, | |
7502 | { Bad_Opcode }, | |
7503 | { Bad_Opcode }, | |
7504 | { Bad_Opcode }, | |
7505 | { Bad_Opcode }, | |
7506 | { Bad_Opcode }, | |
7507 | { Bad_Opcode }, | |
85f10a01 | 7508 | /* f0 */ |
592d1631 L |
7509 | { Bad_Opcode }, |
7510 | { Bad_Opcode }, | |
7511 | { Bad_Opcode }, | |
7512 | { Bad_Opcode }, | |
7513 | { Bad_Opcode }, | |
7514 | { Bad_Opcode }, | |
7515 | { Bad_Opcode }, | |
7516 | { Bad_Opcode }, | |
85f10a01 | 7517 | /* f8 */ |
592d1631 L |
7518 | { Bad_Opcode }, |
7519 | { Bad_Opcode }, | |
7520 | { Bad_Opcode }, | |
7521 | { Bad_Opcode }, | |
7522 | { Bad_Opcode }, | |
7523 | { Bad_Opcode }, | |
7524 | { Bad_Opcode }, | |
7525 | { Bad_Opcode }, | |
85f10a01 | 7526 | }, |
f88c9eb0 SP |
7527 | }; |
7528 | ||
7529 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7530 | /* XOP_08 */ |
85f10a01 MM |
7531 | { |
7532 | /* 00 */ | |
592d1631 L |
7533 | { Bad_Opcode }, |
7534 | { Bad_Opcode }, | |
7535 | { Bad_Opcode }, | |
7536 | { Bad_Opcode }, | |
7537 | { Bad_Opcode }, | |
7538 | { Bad_Opcode }, | |
7539 | { Bad_Opcode }, | |
7540 | { Bad_Opcode }, | |
85f10a01 | 7541 | /* 08 */ |
592d1631 L |
7542 | { Bad_Opcode }, |
7543 | { Bad_Opcode }, | |
7544 | { Bad_Opcode }, | |
7545 | { Bad_Opcode }, | |
7546 | { Bad_Opcode }, | |
7547 | { Bad_Opcode }, | |
7548 | { Bad_Opcode }, | |
7549 | { Bad_Opcode }, | |
85f10a01 | 7550 | /* 10 */ |
3929df09 | 7551 | { Bad_Opcode }, |
592d1631 L |
7552 | { Bad_Opcode }, |
7553 | { Bad_Opcode }, | |
7554 | { Bad_Opcode }, | |
7555 | { Bad_Opcode }, | |
7556 | { Bad_Opcode }, | |
7557 | { Bad_Opcode }, | |
7558 | { Bad_Opcode }, | |
85f10a01 | 7559 | /* 18 */ |
592d1631 L |
7560 | { Bad_Opcode }, |
7561 | { Bad_Opcode }, | |
7562 | { Bad_Opcode }, | |
7563 | { Bad_Opcode }, | |
7564 | { Bad_Opcode }, | |
7565 | { Bad_Opcode }, | |
7566 | { Bad_Opcode }, | |
7567 | { Bad_Opcode }, | |
85f10a01 | 7568 | /* 20 */ |
592d1631 L |
7569 | { Bad_Opcode }, |
7570 | { Bad_Opcode }, | |
7571 | { Bad_Opcode }, | |
7572 | { Bad_Opcode }, | |
7573 | { Bad_Opcode }, | |
7574 | { Bad_Opcode }, | |
7575 | { Bad_Opcode }, | |
7576 | { Bad_Opcode }, | |
85f10a01 | 7577 | /* 28 */ |
592d1631 L |
7578 | { Bad_Opcode }, |
7579 | { Bad_Opcode }, | |
7580 | { Bad_Opcode }, | |
7581 | { Bad_Opcode }, | |
7582 | { Bad_Opcode }, | |
7583 | { Bad_Opcode }, | |
7584 | { Bad_Opcode }, | |
7585 | { Bad_Opcode }, | |
c0f3af97 | 7586 | /* 30 */ |
592d1631 L |
7587 | { Bad_Opcode }, |
7588 | { Bad_Opcode }, | |
7589 | { Bad_Opcode }, | |
7590 | { Bad_Opcode }, | |
7591 | { Bad_Opcode }, | |
7592 | { Bad_Opcode }, | |
7593 | { Bad_Opcode }, | |
7594 | { Bad_Opcode }, | |
c0f3af97 | 7595 | /* 38 */ |
592d1631 L |
7596 | { Bad_Opcode }, |
7597 | { Bad_Opcode }, | |
7598 | { Bad_Opcode }, | |
7599 | { Bad_Opcode }, | |
7600 | { Bad_Opcode }, | |
7601 | { Bad_Opcode }, | |
7602 | { Bad_Opcode }, | |
7603 | { Bad_Opcode }, | |
c0f3af97 | 7604 | /* 40 */ |
592d1631 L |
7605 | { Bad_Opcode }, |
7606 | { Bad_Opcode }, | |
7607 | { Bad_Opcode }, | |
7608 | { Bad_Opcode }, | |
7609 | { Bad_Opcode }, | |
7610 | { Bad_Opcode }, | |
7611 | { Bad_Opcode }, | |
7612 | { Bad_Opcode }, | |
85f10a01 | 7613 | /* 48 */ |
592d1631 L |
7614 | { Bad_Opcode }, |
7615 | { Bad_Opcode }, | |
7616 | { Bad_Opcode }, | |
7617 | { Bad_Opcode }, | |
7618 | { Bad_Opcode }, | |
7619 | { Bad_Opcode }, | |
7620 | { Bad_Opcode }, | |
7621 | { Bad_Opcode }, | |
c0f3af97 | 7622 | /* 50 */ |
592d1631 L |
7623 | { Bad_Opcode }, |
7624 | { Bad_Opcode }, | |
7625 | { Bad_Opcode }, | |
7626 | { Bad_Opcode }, | |
7627 | { Bad_Opcode }, | |
7628 | { Bad_Opcode }, | |
7629 | { Bad_Opcode }, | |
7630 | { Bad_Opcode }, | |
85f10a01 | 7631 | /* 58 */ |
592d1631 L |
7632 | { Bad_Opcode }, |
7633 | { Bad_Opcode }, | |
7634 | { Bad_Opcode }, | |
7635 | { Bad_Opcode }, | |
7636 | { Bad_Opcode }, | |
7637 | { Bad_Opcode }, | |
7638 | { Bad_Opcode }, | |
7639 | { Bad_Opcode }, | |
c1e679ec | 7640 | /* 60 */ |
592d1631 L |
7641 | { Bad_Opcode }, |
7642 | { Bad_Opcode }, | |
7643 | { Bad_Opcode }, | |
7644 | { Bad_Opcode }, | |
7645 | { Bad_Opcode }, | |
7646 | { Bad_Opcode }, | |
7647 | { Bad_Opcode }, | |
7648 | { Bad_Opcode }, | |
c0f3af97 | 7649 | /* 68 */ |
592d1631 L |
7650 | { Bad_Opcode }, |
7651 | { Bad_Opcode }, | |
7652 | { Bad_Opcode }, | |
7653 | { Bad_Opcode }, | |
7654 | { Bad_Opcode }, | |
7655 | { Bad_Opcode }, | |
7656 | { Bad_Opcode }, | |
7657 | { Bad_Opcode }, | |
85f10a01 | 7658 | /* 70 */ |
592d1631 L |
7659 | { Bad_Opcode }, |
7660 | { Bad_Opcode }, | |
7661 | { Bad_Opcode }, | |
7662 | { Bad_Opcode }, | |
7663 | { Bad_Opcode }, | |
7664 | { Bad_Opcode }, | |
7665 | { Bad_Opcode }, | |
7666 | { Bad_Opcode }, | |
85f10a01 | 7667 | /* 78 */ |
592d1631 L |
7668 | { Bad_Opcode }, |
7669 | { Bad_Opcode }, | |
7670 | { Bad_Opcode }, | |
7671 | { Bad_Opcode }, | |
7672 | { Bad_Opcode }, | |
7673 | { Bad_Opcode }, | |
7674 | { Bad_Opcode }, | |
7675 | { Bad_Opcode }, | |
85f10a01 | 7676 | /* 80 */ |
592d1631 L |
7677 | { Bad_Opcode }, |
7678 | { Bad_Opcode }, | |
7679 | { Bad_Opcode }, | |
7680 | { Bad_Opcode }, | |
7681 | { Bad_Opcode }, | |
3a2430e0 JB |
7682 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7683 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7684 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7685 | /* 88 */ |
592d1631 L |
7686 | { Bad_Opcode }, |
7687 | { Bad_Opcode }, | |
7688 | { Bad_Opcode }, | |
7689 | { Bad_Opcode }, | |
7690 | { Bad_Opcode }, | |
7691 | { Bad_Opcode }, | |
3a2430e0 JB |
7692 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7693 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7694 | /* 90 */ |
592d1631 L |
7695 | { Bad_Opcode }, |
7696 | { Bad_Opcode }, | |
7697 | { Bad_Opcode }, | |
7698 | { Bad_Opcode }, | |
7699 | { Bad_Opcode }, | |
3a2430e0 JB |
7700 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7701 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7702 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7703 | /* 98 */ |
592d1631 L |
7704 | { Bad_Opcode }, |
7705 | { Bad_Opcode }, | |
7706 | { Bad_Opcode }, | |
7707 | { Bad_Opcode }, | |
7708 | { Bad_Opcode }, | |
7709 | { Bad_Opcode }, | |
3a2430e0 JB |
7710 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7711 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7712 | /* a0 */ |
592d1631 L |
7713 | { Bad_Opcode }, |
7714 | { Bad_Opcode }, | |
3a2430e0 JB |
7715 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7716 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
592d1631 L |
7717 | { Bad_Opcode }, |
7718 | { Bad_Opcode }, | |
3a2430e0 | 7719 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7720 | { Bad_Opcode }, |
5dd85c99 | 7721 | /* a8 */ |
592d1631 L |
7722 | { Bad_Opcode }, |
7723 | { Bad_Opcode }, | |
7724 | { Bad_Opcode }, | |
7725 | { Bad_Opcode }, | |
7726 | { Bad_Opcode }, | |
7727 | { Bad_Opcode }, | |
7728 | { Bad_Opcode }, | |
7729 | { Bad_Opcode }, | |
5dd85c99 | 7730 | /* b0 */ |
592d1631 L |
7731 | { Bad_Opcode }, |
7732 | { Bad_Opcode }, | |
7733 | { Bad_Opcode }, | |
7734 | { Bad_Opcode }, | |
7735 | { Bad_Opcode }, | |
7736 | { Bad_Opcode }, | |
3a2430e0 | 7737 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7738 | { Bad_Opcode }, |
5dd85c99 | 7739 | /* b8 */ |
592d1631 L |
7740 | { Bad_Opcode }, |
7741 | { Bad_Opcode }, | |
7742 | { Bad_Opcode }, | |
7743 | { Bad_Opcode }, | |
7744 | { Bad_Opcode }, | |
7745 | { Bad_Opcode }, | |
7746 | { Bad_Opcode }, | |
7747 | { Bad_Opcode }, | |
5dd85c99 | 7748 | /* c0 */ |
bf890a93 IT |
7749 | { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, |
7750 | { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, | |
7751 | { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, | |
7752 | { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, | |
592d1631 L |
7753 | { Bad_Opcode }, |
7754 | { Bad_Opcode }, | |
7755 | { Bad_Opcode }, | |
7756 | { Bad_Opcode }, | |
5dd85c99 | 7757 | /* c8 */ |
592d1631 L |
7758 | { Bad_Opcode }, |
7759 | { Bad_Opcode }, | |
7760 | { Bad_Opcode }, | |
7761 | { Bad_Opcode }, | |
ff688e1f L |
7762 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
7763 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
7764 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
7765 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 7766 | /* d0 */ |
592d1631 L |
7767 | { Bad_Opcode }, |
7768 | { Bad_Opcode }, | |
7769 | { Bad_Opcode }, | |
7770 | { Bad_Opcode }, | |
7771 | { Bad_Opcode }, | |
7772 | { Bad_Opcode }, | |
7773 | { Bad_Opcode }, | |
7774 | { Bad_Opcode }, | |
5dd85c99 | 7775 | /* d8 */ |
592d1631 L |
7776 | { Bad_Opcode }, |
7777 | { Bad_Opcode }, | |
7778 | { Bad_Opcode }, | |
7779 | { Bad_Opcode }, | |
7780 | { Bad_Opcode }, | |
7781 | { Bad_Opcode }, | |
7782 | { Bad_Opcode }, | |
7783 | { Bad_Opcode }, | |
5dd85c99 | 7784 | /* e0 */ |
592d1631 L |
7785 | { Bad_Opcode }, |
7786 | { Bad_Opcode }, | |
7787 | { Bad_Opcode }, | |
7788 | { Bad_Opcode }, | |
7789 | { Bad_Opcode }, | |
7790 | { Bad_Opcode }, | |
7791 | { Bad_Opcode }, | |
7792 | { Bad_Opcode }, | |
5dd85c99 | 7793 | /* e8 */ |
592d1631 L |
7794 | { Bad_Opcode }, |
7795 | { Bad_Opcode }, | |
7796 | { Bad_Opcode }, | |
7797 | { Bad_Opcode }, | |
ff688e1f L |
7798 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
7799 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
7800 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
7801 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 7802 | /* f0 */ |
592d1631 L |
7803 | { Bad_Opcode }, |
7804 | { Bad_Opcode }, | |
7805 | { Bad_Opcode }, | |
7806 | { Bad_Opcode }, | |
7807 | { Bad_Opcode }, | |
7808 | { Bad_Opcode }, | |
7809 | { Bad_Opcode }, | |
7810 | { Bad_Opcode }, | |
5dd85c99 | 7811 | /* f8 */ |
592d1631 L |
7812 | { Bad_Opcode }, |
7813 | { Bad_Opcode }, | |
7814 | { Bad_Opcode }, | |
7815 | { Bad_Opcode }, | |
7816 | { Bad_Opcode }, | |
7817 | { Bad_Opcode }, | |
7818 | { Bad_Opcode }, | |
7819 | { Bad_Opcode }, | |
5dd85c99 SP |
7820 | }, |
7821 | /* XOP_09 */ | |
7822 | { | |
7823 | /* 00 */ | |
592d1631 | 7824 | { Bad_Opcode }, |
2a2a0f38 QN |
7825 | { REG_TABLE (REG_XOP_TBM_01) }, |
7826 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
7827 | { Bad_Opcode }, |
7828 | { Bad_Opcode }, | |
7829 | { Bad_Opcode }, | |
7830 | { Bad_Opcode }, | |
7831 | { Bad_Opcode }, | |
5dd85c99 | 7832 | /* 08 */ |
592d1631 L |
7833 | { Bad_Opcode }, |
7834 | { Bad_Opcode }, | |
7835 | { Bad_Opcode }, | |
7836 | { Bad_Opcode }, | |
7837 | { Bad_Opcode }, | |
7838 | { Bad_Opcode }, | |
7839 | { Bad_Opcode }, | |
7840 | { Bad_Opcode }, | |
5dd85c99 | 7841 | /* 10 */ |
592d1631 L |
7842 | { Bad_Opcode }, |
7843 | { Bad_Opcode }, | |
5dd85c99 | 7844 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
7845 | { Bad_Opcode }, |
7846 | { Bad_Opcode }, | |
7847 | { Bad_Opcode }, | |
7848 | { Bad_Opcode }, | |
7849 | { Bad_Opcode }, | |
5dd85c99 | 7850 | /* 18 */ |
592d1631 L |
7851 | { Bad_Opcode }, |
7852 | { Bad_Opcode }, | |
7853 | { Bad_Opcode }, | |
7854 | { Bad_Opcode }, | |
7855 | { Bad_Opcode }, | |
7856 | { Bad_Opcode }, | |
7857 | { Bad_Opcode }, | |
7858 | { Bad_Opcode }, | |
5dd85c99 | 7859 | /* 20 */ |
592d1631 L |
7860 | { Bad_Opcode }, |
7861 | { Bad_Opcode }, | |
7862 | { Bad_Opcode }, | |
7863 | { Bad_Opcode }, | |
7864 | { Bad_Opcode }, | |
7865 | { Bad_Opcode }, | |
7866 | { Bad_Opcode }, | |
7867 | { Bad_Opcode }, | |
5dd85c99 | 7868 | /* 28 */ |
592d1631 L |
7869 | { Bad_Opcode }, |
7870 | { Bad_Opcode }, | |
7871 | { Bad_Opcode }, | |
7872 | { Bad_Opcode }, | |
7873 | { Bad_Opcode }, | |
7874 | { Bad_Opcode }, | |
7875 | { Bad_Opcode }, | |
7876 | { Bad_Opcode }, | |
5dd85c99 | 7877 | /* 30 */ |
592d1631 L |
7878 | { Bad_Opcode }, |
7879 | { Bad_Opcode }, | |
7880 | { Bad_Opcode }, | |
7881 | { Bad_Opcode }, | |
7882 | { Bad_Opcode }, | |
7883 | { Bad_Opcode }, | |
7884 | { Bad_Opcode }, | |
7885 | { Bad_Opcode }, | |
5dd85c99 | 7886 | /* 38 */ |
592d1631 L |
7887 | { Bad_Opcode }, |
7888 | { Bad_Opcode }, | |
7889 | { Bad_Opcode }, | |
7890 | { Bad_Opcode }, | |
7891 | { Bad_Opcode }, | |
7892 | { Bad_Opcode }, | |
7893 | { Bad_Opcode }, | |
7894 | { Bad_Opcode }, | |
5dd85c99 | 7895 | /* 40 */ |
592d1631 L |
7896 | { Bad_Opcode }, |
7897 | { Bad_Opcode }, | |
7898 | { Bad_Opcode }, | |
7899 | { Bad_Opcode }, | |
7900 | { Bad_Opcode }, | |
7901 | { Bad_Opcode }, | |
7902 | { Bad_Opcode }, | |
7903 | { Bad_Opcode }, | |
5dd85c99 | 7904 | /* 48 */ |
592d1631 L |
7905 | { Bad_Opcode }, |
7906 | { Bad_Opcode }, | |
7907 | { Bad_Opcode }, | |
7908 | { Bad_Opcode }, | |
7909 | { Bad_Opcode }, | |
7910 | { Bad_Opcode }, | |
7911 | { Bad_Opcode }, | |
7912 | { Bad_Opcode }, | |
5dd85c99 | 7913 | /* 50 */ |
592d1631 L |
7914 | { Bad_Opcode }, |
7915 | { Bad_Opcode }, | |
7916 | { Bad_Opcode }, | |
7917 | { Bad_Opcode }, | |
7918 | { Bad_Opcode }, | |
7919 | { Bad_Opcode }, | |
7920 | { Bad_Opcode }, | |
7921 | { Bad_Opcode }, | |
5dd85c99 | 7922 | /* 58 */ |
592d1631 L |
7923 | { Bad_Opcode }, |
7924 | { Bad_Opcode }, | |
7925 | { Bad_Opcode }, | |
7926 | { Bad_Opcode }, | |
7927 | { Bad_Opcode }, | |
7928 | { Bad_Opcode }, | |
7929 | { Bad_Opcode }, | |
7930 | { Bad_Opcode }, | |
5dd85c99 | 7931 | /* 60 */ |
592d1631 L |
7932 | { Bad_Opcode }, |
7933 | { Bad_Opcode }, | |
7934 | { Bad_Opcode }, | |
7935 | { Bad_Opcode }, | |
7936 | { Bad_Opcode }, | |
7937 | { Bad_Opcode }, | |
7938 | { Bad_Opcode }, | |
7939 | { Bad_Opcode }, | |
5dd85c99 | 7940 | /* 68 */ |
592d1631 L |
7941 | { Bad_Opcode }, |
7942 | { Bad_Opcode }, | |
7943 | { Bad_Opcode }, | |
7944 | { Bad_Opcode }, | |
7945 | { Bad_Opcode }, | |
7946 | { Bad_Opcode }, | |
7947 | { Bad_Opcode }, | |
7948 | { Bad_Opcode }, | |
5dd85c99 | 7949 | /* 70 */ |
592d1631 L |
7950 | { Bad_Opcode }, |
7951 | { Bad_Opcode }, | |
7952 | { Bad_Opcode }, | |
7953 | { Bad_Opcode }, | |
7954 | { Bad_Opcode }, | |
7955 | { Bad_Opcode }, | |
7956 | { Bad_Opcode }, | |
7957 | { Bad_Opcode }, | |
5dd85c99 | 7958 | /* 78 */ |
592d1631 L |
7959 | { Bad_Opcode }, |
7960 | { Bad_Opcode }, | |
7961 | { Bad_Opcode }, | |
7962 | { Bad_Opcode }, | |
7963 | { Bad_Opcode }, | |
7964 | { Bad_Opcode }, | |
7965 | { Bad_Opcode }, | |
7966 | { Bad_Opcode }, | |
5dd85c99 | 7967 | /* 80 */ |
592a252b L |
7968 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
7969 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, | |
bf890a93 IT |
7970 | { "vfrczss", { XM, EXd }, 0 }, |
7971 | { "vfrczsd", { XM, EXq }, 0 }, | |
592d1631 L |
7972 | { Bad_Opcode }, |
7973 | { Bad_Opcode }, | |
7974 | { Bad_Opcode }, | |
7975 | { Bad_Opcode }, | |
5dd85c99 | 7976 | /* 88 */ |
592d1631 L |
7977 | { Bad_Opcode }, |
7978 | { Bad_Opcode }, | |
7979 | { Bad_Opcode }, | |
7980 | { Bad_Opcode }, | |
7981 | { Bad_Opcode }, | |
7982 | { Bad_Opcode }, | |
7983 | { Bad_Opcode }, | |
7984 | { Bad_Opcode }, | |
5dd85c99 | 7985 | /* 90 */ |
bf890a93 IT |
7986 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7987 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7988 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7989 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7990 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7991 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7992 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7993 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
5dd85c99 | 7994 | /* 98 */ |
bf890a93 IT |
7995 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7996 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7997 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7998 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
592d1631 L |
7999 | { Bad_Opcode }, |
8000 | { Bad_Opcode }, | |
8001 | { Bad_Opcode }, | |
8002 | { Bad_Opcode }, | |
5dd85c99 | 8003 | /* a0 */ |
592d1631 L |
8004 | { Bad_Opcode }, |
8005 | { Bad_Opcode }, | |
8006 | { Bad_Opcode }, | |
8007 | { Bad_Opcode }, | |
8008 | { Bad_Opcode }, | |
8009 | { Bad_Opcode }, | |
8010 | { Bad_Opcode }, | |
8011 | { Bad_Opcode }, | |
5dd85c99 | 8012 | /* a8 */ |
592d1631 L |
8013 | { Bad_Opcode }, |
8014 | { Bad_Opcode }, | |
8015 | { Bad_Opcode }, | |
8016 | { Bad_Opcode }, | |
8017 | { Bad_Opcode }, | |
8018 | { Bad_Opcode }, | |
8019 | { Bad_Opcode }, | |
8020 | { Bad_Opcode }, | |
5dd85c99 | 8021 | /* b0 */ |
592d1631 L |
8022 | { Bad_Opcode }, |
8023 | { Bad_Opcode }, | |
8024 | { Bad_Opcode }, | |
8025 | { Bad_Opcode }, | |
8026 | { Bad_Opcode }, | |
8027 | { Bad_Opcode }, | |
8028 | { Bad_Opcode }, | |
8029 | { Bad_Opcode }, | |
5dd85c99 | 8030 | /* b8 */ |
592d1631 L |
8031 | { Bad_Opcode }, |
8032 | { Bad_Opcode }, | |
8033 | { Bad_Opcode }, | |
8034 | { Bad_Opcode }, | |
8035 | { Bad_Opcode }, | |
8036 | { Bad_Opcode }, | |
8037 | { Bad_Opcode }, | |
8038 | { Bad_Opcode }, | |
5dd85c99 | 8039 | /* c0 */ |
592d1631 | 8040 | { Bad_Opcode }, |
bf890a93 IT |
8041 | { "vphaddbw", { XM, EXxmm }, 0 }, |
8042 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
8043 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8044 | { Bad_Opcode }, |
8045 | { Bad_Opcode }, | |
bf890a93 IT |
8046 | { "vphaddwd", { XM, EXxmm }, 0 }, |
8047 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8048 | /* c8 */ |
592d1631 L |
8049 | { Bad_Opcode }, |
8050 | { Bad_Opcode }, | |
8051 | { Bad_Opcode }, | |
bf890a93 | 8052 | { "vphadddq", { XM, EXxmm }, 0 }, |
592d1631 L |
8053 | { Bad_Opcode }, |
8054 | { Bad_Opcode }, | |
8055 | { Bad_Opcode }, | |
8056 | { Bad_Opcode }, | |
5dd85c99 | 8057 | /* d0 */ |
592d1631 | 8058 | { Bad_Opcode }, |
bf890a93 IT |
8059 | { "vphaddubw", { XM, EXxmm }, 0 }, |
8060 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
8061 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8062 | { Bad_Opcode }, |
8063 | { Bad_Opcode }, | |
bf890a93 IT |
8064 | { "vphadduwd", { XM, EXxmm }, 0 }, |
8065 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8066 | /* d8 */ |
592d1631 L |
8067 | { Bad_Opcode }, |
8068 | { Bad_Opcode }, | |
8069 | { Bad_Opcode }, | |
bf890a93 | 8070 | { "vphaddudq", { XM, EXxmm }, 0 }, |
592d1631 L |
8071 | { Bad_Opcode }, |
8072 | { Bad_Opcode }, | |
8073 | { Bad_Opcode }, | |
8074 | { Bad_Opcode }, | |
5dd85c99 | 8075 | /* e0 */ |
592d1631 | 8076 | { Bad_Opcode }, |
bf890a93 IT |
8077 | { "vphsubbw", { XM, EXxmm }, 0 }, |
8078 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
8079 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8080 | { Bad_Opcode }, |
8081 | { Bad_Opcode }, | |
8082 | { Bad_Opcode }, | |
8083 | { Bad_Opcode }, | |
4e7d34a6 | 8084 | /* e8 */ |
592d1631 L |
8085 | { Bad_Opcode }, |
8086 | { Bad_Opcode }, | |
8087 | { Bad_Opcode }, | |
8088 | { Bad_Opcode }, | |
8089 | { Bad_Opcode }, | |
8090 | { Bad_Opcode }, | |
8091 | { Bad_Opcode }, | |
8092 | { Bad_Opcode }, | |
4e7d34a6 | 8093 | /* f0 */ |
592d1631 L |
8094 | { Bad_Opcode }, |
8095 | { Bad_Opcode }, | |
8096 | { Bad_Opcode }, | |
8097 | { Bad_Opcode }, | |
8098 | { Bad_Opcode }, | |
8099 | { Bad_Opcode }, | |
8100 | { Bad_Opcode }, | |
8101 | { Bad_Opcode }, | |
4e7d34a6 | 8102 | /* f8 */ |
592d1631 L |
8103 | { Bad_Opcode }, |
8104 | { Bad_Opcode }, | |
8105 | { Bad_Opcode }, | |
8106 | { Bad_Opcode }, | |
8107 | { Bad_Opcode }, | |
8108 | { Bad_Opcode }, | |
8109 | { Bad_Opcode }, | |
8110 | { Bad_Opcode }, | |
4e7d34a6 | 8111 | }, |
f88c9eb0 | 8112 | /* XOP_0A */ |
4e7d34a6 L |
8113 | { |
8114 | /* 00 */ | |
592d1631 L |
8115 | { Bad_Opcode }, |
8116 | { Bad_Opcode }, | |
8117 | { Bad_Opcode }, | |
8118 | { Bad_Opcode }, | |
8119 | { Bad_Opcode }, | |
8120 | { Bad_Opcode }, | |
8121 | { Bad_Opcode }, | |
8122 | { Bad_Opcode }, | |
4e7d34a6 | 8123 | /* 08 */ |
592d1631 L |
8124 | { Bad_Opcode }, |
8125 | { Bad_Opcode }, | |
8126 | { Bad_Opcode }, | |
8127 | { Bad_Opcode }, | |
8128 | { Bad_Opcode }, | |
8129 | { Bad_Opcode }, | |
8130 | { Bad_Opcode }, | |
8131 | { Bad_Opcode }, | |
4e7d34a6 | 8132 | /* 10 */ |
c1dc7af5 | 8133 | { "bextrS", { Gdq, Edq, Id }, 0 }, |
592d1631 | 8134 | { Bad_Opcode }, |
f88c9eb0 | 8135 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
8136 | { Bad_Opcode }, |
8137 | { Bad_Opcode }, | |
8138 | { Bad_Opcode }, | |
8139 | { Bad_Opcode }, | |
8140 | { Bad_Opcode }, | |
4e7d34a6 | 8141 | /* 18 */ |
592d1631 L |
8142 | { Bad_Opcode }, |
8143 | { Bad_Opcode }, | |
8144 | { Bad_Opcode }, | |
8145 | { Bad_Opcode }, | |
8146 | { Bad_Opcode }, | |
8147 | { Bad_Opcode }, | |
8148 | { Bad_Opcode }, | |
8149 | { Bad_Opcode }, | |
4e7d34a6 | 8150 | /* 20 */ |
592d1631 L |
8151 | { Bad_Opcode }, |
8152 | { Bad_Opcode }, | |
8153 | { Bad_Opcode }, | |
8154 | { Bad_Opcode }, | |
8155 | { Bad_Opcode }, | |
8156 | { Bad_Opcode }, | |
8157 | { Bad_Opcode }, | |
8158 | { Bad_Opcode }, | |
4e7d34a6 | 8159 | /* 28 */ |
592d1631 L |
8160 | { Bad_Opcode }, |
8161 | { Bad_Opcode }, | |
8162 | { Bad_Opcode }, | |
8163 | { Bad_Opcode }, | |
8164 | { Bad_Opcode }, | |
8165 | { Bad_Opcode }, | |
8166 | { Bad_Opcode }, | |
8167 | { Bad_Opcode }, | |
4e7d34a6 | 8168 | /* 30 */ |
592d1631 L |
8169 | { Bad_Opcode }, |
8170 | { Bad_Opcode }, | |
8171 | { Bad_Opcode }, | |
8172 | { Bad_Opcode }, | |
8173 | { Bad_Opcode }, | |
8174 | { Bad_Opcode }, | |
8175 | { Bad_Opcode }, | |
8176 | { Bad_Opcode }, | |
c0f3af97 | 8177 | /* 38 */ |
592d1631 L |
8178 | { Bad_Opcode }, |
8179 | { Bad_Opcode }, | |
8180 | { Bad_Opcode }, | |
8181 | { Bad_Opcode }, | |
8182 | { Bad_Opcode }, | |
8183 | { Bad_Opcode }, | |
8184 | { Bad_Opcode }, | |
8185 | { Bad_Opcode }, | |
c0f3af97 | 8186 | /* 40 */ |
592d1631 L |
8187 | { Bad_Opcode }, |
8188 | { Bad_Opcode }, | |
8189 | { Bad_Opcode }, | |
8190 | { Bad_Opcode }, | |
8191 | { Bad_Opcode }, | |
8192 | { Bad_Opcode }, | |
8193 | { Bad_Opcode }, | |
8194 | { Bad_Opcode }, | |
c1e679ec | 8195 | /* 48 */ |
592d1631 L |
8196 | { Bad_Opcode }, |
8197 | { Bad_Opcode }, | |
8198 | { Bad_Opcode }, | |
8199 | { Bad_Opcode }, | |
8200 | { Bad_Opcode }, | |
8201 | { Bad_Opcode }, | |
8202 | { Bad_Opcode }, | |
8203 | { Bad_Opcode }, | |
c1e679ec | 8204 | /* 50 */ |
592d1631 L |
8205 | { Bad_Opcode }, |
8206 | { Bad_Opcode }, | |
8207 | { Bad_Opcode }, | |
8208 | { Bad_Opcode }, | |
8209 | { Bad_Opcode }, | |
8210 | { Bad_Opcode }, | |
8211 | { Bad_Opcode }, | |
8212 | { Bad_Opcode }, | |
4e7d34a6 | 8213 | /* 58 */ |
592d1631 L |
8214 | { Bad_Opcode }, |
8215 | { Bad_Opcode }, | |
8216 | { Bad_Opcode }, | |
8217 | { Bad_Opcode }, | |
8218 | { Bad_Opcode }, | |
8219 | { Bad_Opcode }, | |
8220 | { Bad_Opcode }, | |
8221 | { Bad_Opcode }, | |
4e7d34a6 | 8222 | /* 60 */ |
592d1631 L |
8223 | { Bad_Opcode }, |
8224 | { Bad_Opcode }, | |
8225 | { Bad_Opcode }, | |
8226 | { Bad_Opcode }, | |
8227 | { Bad_Opcode }, | |
8228 | { Bad_Opcode }, | |
8229 | { Bad_Opcode }, | |
8230 | { Bad_Opcode }, | |
4e7d34a6 | 8231 | /* 68 */ |
592d1631 L |
8232 | { Bad_Opcode }, |
8233 | { Bad_Opcode }, | |
8234 | { Bad_Opcode }, | |
8235 | { Bad_Opcode }, | |
8236 | { Bad_Opcode }, | |
8237 | { Bad_Opcode }, | |
8238 | { Bad_Opcode }, | |
8239 | { Bad_Opcode }, | |
4e7d34a6 | 8240 | /* 70 */ |
592d1631 L |
8241 | { Bad_Opcode }, |
8242 | { Bad_Opcode }, | |
8243 | { Bad_Opcode }, | |
8244 | { Bad_Opcode }, | |
8245 | { Bad_Opcode }, | |
8246 | { Bad_Opcode }, | |
8247 | { Bad_Opcode }, | |
8248 | { Bad_Opcode }, | |
4e7d34a6 | 8249 | /* 78 */ |
592d1631 L |
8250 | { Bad_Opcode }, |
8251 | { Bad_Opcode }, | |
8252 | { Bad_Opcode }, | |
8253 | { Bad_Opcode }, | |
8254 | { Bad_Opcode }, | |
8255 | { Bad_Opcode }, | |
8256 | { Bad_Opcode }, | |
8257 | { Bad_Opcode }, | |
4e7d34a6 | 8258 | /* 80 */ |
592d1631 L |
8259 | { Bad_Opcode }, |
8260 | { Bad_Opcode }, | |
8261 | { Bad_Opcode }, | |
8262 | { Bad_Opcode }, | |
8263 | { Bad_Opcode }, | |
8264 | { Bad_Opcode }, | |
8265 | { Bad_Opcode }, | |
8266 | { Bad_Opcode }, | |
4e7d34a6 | 8267 | /* 88 */ |
592d1631 L |
8268 | { Bad_Opcode }, |
8269 | { Bad_Opcode }, | |
8270 | { Bad_Opcode }, | |
8271 | { Bad_Opcode }, | |
8272 | { Bad_Opcode }, | |
8273 | { Bad_Opcode }, | |
8274 | { Bad_Opcode }, | |
8275 | { Bad_Opcode }, | |
4e7d34a6 | 8276 | /* 90 */ |
592d1631 L |
8277 | { Bad_Opcode }, |
8278 | { Bad_Opcode }, | |
8279 | { Bad_Opcode }, | |
8280 | { Bad_Opcode }, | |
8281 | { Bad_Opcode }, | |
8282 | { Bad_Opcode }, | |
8283 | { Bad_Opcode }, | |
8284 | { Bad_Opcode }, | |
4e7d34a6 | 8285 | /* 98 */ |
592d1631 L |
8286 | { Bad_Opcode }, |
8287 | { Bad_Opcode }, | |
8288 | { Bad_Opcode }, | |
8289 | { Bad_Opcode }, | |
8290 | { Bad_Opcode }, | |
8291 | { Bad_Opcode }, | |
8292 | { Bad_Opcode }, | |
8293 | { Bad_Opcode }, | |
4e7d34a6 | 8294 | /* a0 */ |
592d1631 L |
8295 | { Bad_Opcode }, |
8296 | { Bad_Opcode }, | |
8297 | { Bad_Opcode }, | |
8298 | { Bad_Opcode }, | |
8299 | { Bad_Opcode }, | |
8300 | { Bad_Opcode }, | |
8301 | { Bad_Opcode }, | |
8302 | { Bad_Opcode }, | |
4e7d34a6 | 8303 | /* a8 */ |
592d1631 L |
8304 | { Bad_Opcode }, |
8305 | { Bad_Opcode }, | |
8306 | { Bad_Opcode }, | |
8307 | { Bad_Opcode }, | |
8308 | { Bad_Opcode }, | |
8309 | { Bad_Opcode }, | |
8310 | { Bad_Opcode }, | |
8311 | { Bad_Opcode }, | |
d5d7db8e | 8312 | /* b0 */ |
592d1631 L |
8313 | { Bad_Opcode }, |
8314 | { Bad_Opcode }, | |
8315 | { Bad_Opcode }, | |
8316 | { Bad_Opcode }, | |
8317 | { Bad_Opcode }, | |
8318 | { Bad_Opcode }, | |
8319 | { Bad_Opcode }, | |
8320 | { Bad_Opcode }, | |
85f10a01 | 8321 | /* b8 */ |
592d1631 L |
8322 | { Bad_Opcode }, |
8323 | { Bad_Opcode }, | |
8324 | { Bad_Opcode }, | |
8325 | { Bad_Opcode }, | |
8326 | { Bad_Opcode }, | |
8327 | { Bad_Opcode }, | |
8328 | { Bad_Opcode }, | |
8329 | { Bad_Opcode }, | |
85f10a01 | 8330 | /* c0 */ |
592d1631 L |
8331 | { Bad_Opcode }, |
8332 | { Bad_Opcode }, | |
8333 | { Bad_Opcode }, | |
8334 | { Bad_Opcode }, | |
8335 | { Bad_Opcode }, | |
8336 | { Bad_Opcode }, | |
8337 | { Bad_Opcode }, | |
8338 | { Bad_Opcode }, | |
85f10a01 | 8339 | /* c8 */ |
592d1631 L |
8340 | { Bad_Opcode }, |
8341 | { Bad_Opcode }, | |
8342 | { Bad_Opcode }, | |
8343 | { Bad_Opcode }, | |
8344 | { Bad_Opcode }, | |
8345 | { Bad_Opcode }, | |
8346 | { Bad_Opcode }, | |
8347 | { Bad_Opcode }, | |
85f10a01 | 8348 | /* d0 */ |
592d1631 L |
8349 | { Bad_Opcode }, |
8350 | { Bad_Opcode }, | |
8351 | { Bad_Opcode }, | |
8352 | { Bad_Opcode }, | |
8353 | { Bad_Opcode }, | |
8354 | { Bad_Opcode }, | |
8355 | { Bad_Opcode }, | |
8356 | { Bad_Opcode }, | |
85f10a01 | 8357 | /* d8 */ |
592d1631 L |
8358 | { Bad_Opcode }, |
8359 | { Bad_Opcode }, | |
8360 | { Bad_Opcode }, | |
8361 | { Bad_Opcode }, | |
8362 | { Bad_Opcode }, | |
8363 | { Bad_Opcode }, | |
8364 | { Bad_Opcode }, | |
8365 | { Bad_Opcode }, | |
85f10a01 | 8366 | /* e0 */ |
592d1631 L |
8367 | { Bad_Opcode }, |
8368 | { Bad_Opcode }, | |
8369 | { Bad_Opcode }, | |
8370 | { Bad_Opcode }, | |
8371 | { Bad_Opcode }, | |
8372 | { Bad_Opcode }, | |
8373 | { Bad_Opcode }, | |
8374 | { Bad_Opcode }, | |
85f10a01 | 8375 | /* e8 */ |
592d1631 L |
8376 | { Bad_Opcode }, |
8377 | { Bad_Opcode }, | |
8378 | { Bad_Opcode }, | |
8379 | { Bad_Opcode }, | |
8380 | { Bad_Opcode }, | |
8381 | { Bad_Opcode }, | |
8382 | { Bad_Opcode }, | |
8383 | { Bad_Opcode }, | |
85f10a01 | 8384 | /* f0 */ |
592d1631 L |
8385 | { Bad_Opcode }, |
8386 | { Bad_Opcode }, | |
8387 | { Bad_Opcode }, | |
8388 | { Bad_Opcode }, | |
8389 | { Bad_Opcode }, | |
8390 | { Bad_Opcode }, | |
8391 | { Bad_Opcode }, | |
8392 | { Bad_Opcode }, | |
85f10a01 | 8393 | /* f8 */ |
592d1631 L |
8394 | { Bad_Opcode }, |
8395 | { Bad_Opcode }, | |
8396 | { Bad_Opcode }, | |
8397 | { Bad_Opcode }, | |
8398 | { Bad_Opcode }, | |
8399 | { Bad_Opcode }, | |
8400 | { Bad_Opcode }, | |
8401 | { Bad_Opcode }, | |
85f10a01 | 8402 | }, |
c0f3af97 L |
8403 | }; |
8404 | ||
8405 | static const struct dis386 vex_table[][256] = { | |
8406 | /* VEX_0F */ | |
85f10a01 MM |
8407 | { |
8408 | /* 00 */ | |
592d1631 L |
8409 | { Bad_Opcode }, |
8410 | { Bad_Opcode }, | |
8411 | { Bad_Opcode }, | |
8412 | { Bad_Opcode }, | |
8413 | { Bad_Opcode }, | |
8414 | { Bad_Opcode }, | |
8415 | { Bad_Opcode }, | |
8416 | { Bad_Opcode }, | |
85f10a01 | 8417 | /* 08 */ |
592d1631 L |
8418 | { Bad_Opcode }, |
8419 | { Bad_Opcode }, | |
8420 | { Bad_Opcode }, | |
8421 | { Bad_Opcode }, | |
8422 | { Bad_Opcode }, | |
8423 | { Bad_Opcode }, | |
8424 | { Bad_Opcode }, | |
8425 | { Bad_Opcode }, | |
c0f3af97 | 8426 | /* 10 */ |
592a252b L |
8427 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8428 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8429 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8430 | { MOD_TABLE (MOD_VEX_0F13) }, | |
bf926894 JB |
8431 | { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
8432 | { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
592a252b L |
8433 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, |
8434 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8435 | /* 18 */ |
592d1631 L |
8436 | { Bad_Opcode }, |
8437 | { Bad_Opcode }, | |
8438 | { Bad_Opcode }, | |
8439 | { Bad_Opcode }, | |
8440 | { Bad_Opcode }, | |
8441 | { Bad_Opcode }, | |
8442 | { Bad_Opcode }, | |
8443 | { Bad_Opcode }, | |
c0f3af97 | 8444 | /* 20 */ |
592d1631 L |
8445 | { Bad_Opcode }, |
8446 | { Bad_Opcode }, | |
8447 | { Bad_Opcode }, | |
8448 | { Bad_Opcode }, | |
8449 | { Bad_Opcode }, | |
8450 | { Bad_Opcode }, | |
8451 | { Bad_Opcode }, | |
8452 | { Bad_Opcode }, | |
c0f3af97 | 8453 | /* 28 */ |
bf926894 JB |
8454 | { "vmovapX", { XM, EXx }, PREFIX_OPCODE }, |
8455 | { "vmovapX", { EXxS, XM }, PREFIX_OPCODE }, | |
592a252b L |
8456 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, |
8457 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8458 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8459 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8460 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8461 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8462 | /* 30 */ |
592d1631 L |
8463 | { Bad_Opcode }, |
8464 | { Bad_Opcode }, | |
8465 | { Bad_Opcode }, | |
8466 | { Bad_Opcode }, | |
8467 | { Bad_Opcode }, | |
8468 | { Bad_Opcode }, | |
8469 | { Bad_Opcode }, | |
8470 | { Bad_Opcode }, | |
4e7d34a6 | 8471 | /* 38 */ |
592d1631 L |
8472 | { Bad_Opcode }, |
8473 | { Bad_Opcode }, | |
8474 | { Bad_Opcode }, | |
8475 | { Bad_Opcode }, | |
8476 | { Bad_Opcode }, | |
8477 | { Bad_Opcode }, | |
8478 | { Bad_Opcode }, | |
8479 | { Bad_Opcode }, | |
d5d7db8e | 8480 | /* 40 */ |
592d1631 | 8481 | { Bad_Opcode }, |
43234a1e L |
8482 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8483 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8484 | { Bad_Opcode }, |
43234a1e L |
8485 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8486 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8487 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8488 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8489 | /* 48 */ |
592d1631 L |
8490 | { Bad_Opcode }, |
8491 | { Bad_Opcode }, | |
1ba585e8 | 8492 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 8493 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8494 | { Bad_Opcode }, |
8495 | { Bad_Opcode }, | |
8496 | { Bad_Opcode }, | |
8497 | { Bad_Opcode }, | |
d5d7db8e | 8498 | /* 50 */ |
592a252b L |
8499 | { MOD_TABLE (MOD_VEX_0F50) }, |
8500 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8501 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8502 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf926894 JB |
8503 | { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
8504 | { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
8505 | { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
8506 | { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
c0f3af97 | 8507 | /* 58 */ |
592a252b L |
8508 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8509 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8510 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8511 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8512 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8513 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8514 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8515 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8516 | /* 60 */ |
592a252b L |
8517 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8518 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8519 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8520 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8521 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8522 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8523 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8524 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8525 | /* 68 */ |
592a252b L |
8526 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8527 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8528 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8529 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8530 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8531 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8532 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8533 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8534 | /* 70 */ |
592a252b L |
8535 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8536 | { REG_TABLE (REG_VEX_0F71) }, | |
8537 | { REG_TABLE (REG_VEX_0F72) }, | |
8538 | { REG_TABLE (REG_VEX_0F73) }, | |
8539 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8540 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8541 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8542 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8543 | /* 78 */ |
592d1631 L |
8544 | { Bad_Opcode }, |
8545 | { Bad_Opcode }, | |
8546 | { Bad_Opcode }, | |
8547 | { Bad_Opcode }, | |
592a252b L |
8548 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8549 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8550 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8551 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8552 | /* 80 */ |
592d1631 L |
8553 | { Bad_Opcode }, |
8554 | { Bad_Opcode }, | |
8555 | { Bad_Opcode }, | |
8556 | { Bad_Opcode }, | |
8557 | { Bad_Opcode }, | |
8558 | { Bad_Opcode }, | |
8559 | { Bad_Opcode }, | |
8560 | { Bad_Opcode }, | |
c0f3af97 | 8561 | /* 88 */ |
592d1631 L |
8562 | { Bad_Opcode }, |
8563 | { Bad_Opcode }, | |
8564 | { Bad_Opcode }, | |
8565 | { Bad_Opcode }, | |
8566 | { Bad_Opcode }, | |
8567 | { Bad_Opcode }, | |
8568 | { Bad_Opcode }, | |
8569 | { Bad_Opcode }, | |
c0f3af97 | 8570 | /* 90 */ |
43234a1e L |
8571 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8572 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8573 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8574 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8575 | { Bad_Opcode }, |
8576 | { Bad_Opcode }, | |
8577 | { Bad_Opcode }, | |
8578 | { Bad_Opcode }, | |
c0f3af97 | 8579 | /* 98 */ |
43234a1e | 8580 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 8581 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
8582 | { Bad_Opcode }, |
8583 | { Bad_Opcode }, | |
8584 | { Bad_Opcode }, | |
8585 | { Bad_Opcode }, | |
8586 | { Bad_Opcode }, | |
8587 | { Bad_Opcode }, | |
c0f3af97 | 8588 | /* a0 */ |
592d1631 L |
8589 | { Bad_Opcode }, |
8590 | { Bad_Opcode }, | |
8591 | { Bad_Opcode }, | |
8592 | { Bad_Opcode }, | |
8593 | { Bad_Opcode }, | |
8594 | { Bad_Opcode }, | |
8595 | { Bad_Opcode }, | |
8596 | { Bad_Opcode }, | |
c0f3af97 | 8597 | /* a8 */ |
592d1631 L |
8598 | { Bad_Opcode }, |
8599 | { Bad_Opcode }, | |
8600 | { Bad_Opcode }, | |
8601 | { Bad_Opcode }, | |
8602 | { Bad_Opcode }, | |
8603 | { Bad_Opcode }, | |
592a252b | 8604 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8605 | { Bad_Opcode }, |
c0f3af97 | 8606 | /* b0 */ |
592d1631 L |
8607 | { Bad_Opcode }, |
8608 | { Bad_Opcode }, | |
8609 | { Bad_Opcode }, | |
8610 | { Bad_Opcode }, | |
8611 | { Bad_Opcode }, | |
8612 | { Bad_Opcode }, | |
8613 | { Bad_Opcode }, | |
8614 | { Bad_Opcode }, | |
c0f3af97 | 8615 | /* b8 */ |
592d1631 L |
8616 | { Bad_Opcode }, |
8617 | { Bad_Opcode }, | |
8618 | { Bad_Opcode }, | |
8619 | { Bad_Opcode }, | |
8620 | { Bad_Opcode }, | |
8621 | { Bad_Opcode }, | |
8622 | { Bad_Opcode }, | |
8623 | { Bad_Opcode }, | |
c0f3af97 | 8624 | /* c0 */ |
592d1631 L |
8625 | { Bad_Opcode }, |
8626 | { Bad_Opcode }, | |
592a252b | 8627 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8628 | { Bad_Opcode }, |
592a252b L |
8629 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8630 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
bf926894 | 8631 | { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE }, |
592d1631 | 8632 | { Bad_Opcode }, |
c0f3af97 | 8633 | /* c8 */ |
592d1631 L |
8634 | { Bad_Opcode }, |
8635 | { Bad_Opcode }, | |
8636 | { Bad_Opcode }, | |
8637 | { Bad_Opcode }, | |
8638 | { Bad_Opcode }, | |
8639 | { Bad_Opcode }, | |
8640 | { Bad_Opcode }, | |
8641 | { Bad_Opcode }, | |
c0f3af97 | 8642 | /* d0 */ |
592a252b L |
8643 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8644 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8645 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8646 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8647 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8648 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8649 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8650 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8651 | /* d8 */ |
592a252b L |
8652 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8653 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8654 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8655 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8656 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8657 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8658 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8659 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8660 | /* e0 */ |
592a252b L |
8661 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8662 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8663 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8664 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8665 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8666 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8667 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8668 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8669 | /* e8 */ |
592a252b L |
8670 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8671 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8672 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8673 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8674 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8675 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8676 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8677 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8678 | /* f0 */ |
592a252b L |
8679 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8680 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8681 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8682 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8683 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8684 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8685 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8686 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8687 | /* f8 */ |
592a252b L |
8688 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8689 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8690 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8691 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8692 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8693 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8694 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 8695 | { Bad_Opcode }, |
c0f3af97 L |
8696 | }, |
8697 | /* VEX_0F38 */ | |
8698 | { | |
8699 | /* 00 */ | |
592a252b L |
8700 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8701 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
8702 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
8703 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
8704 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
8705 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
8706 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
8707 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 8708 | /* 08 */ |
592a252b L |
8709 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8710 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
8711 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
8712 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
8713 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
8714 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
8715 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
8716 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 8717 | /* 10 */ |
592d1631 L |
8718 | { Bad_Opcode }, |
8719 | { Bad_Opcode }, | |
8720 | { Bad_Opcode }, | |
592a252b | 8721 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
8722 | { Bad_Opcode }, |
8723 | { Bad_Opcode }, | |
6c30d220 | 8724 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 8725 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 8726 | /* 18 */ |
592a252b L |
8727 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8728 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
8729 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 8730 | { Bad_Opcode }, |
592a252b L |
8731 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8732 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
8733 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 8734 | { Bad_Opcode }, |
c0f3af97 | 8735 | /* 20 */ |
592a252b L |
8736 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8737 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
8738 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
8739 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
8740 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
8741 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
8742 | { Bad_Opcode }, |
8743 | { Bad_Opcode }, | |
c0f3af97 | 8744 | /* 28 */ |
592a252b L |
8745 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8746 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
8747 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
8748 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
8749 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
8750 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
8751 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
8752 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 8753 | /* 30 */ |
592a252b L |
8754 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
8755 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
8756 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
8757 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
8758 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
8759 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 8760 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 8761 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 8762 | /* 38 */ |
592a252b L |
8763 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
8764 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
8765 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
8766 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
8767 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
8768 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
8769 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
8770 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 8771 | /* 40 */ |
592a252b L |
8772 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
8773 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
8774 | { Bad_Opcode }, |
8775 | { Bad_Opcode }, | |
8776 | { Bad_Opcode }, | |
6c30d220 L |
8777 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
8778 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
8779 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 8780 | /* 48 */ |
592d1631 L |
8781 | { Bad_Opcode }, |
8782 | { Bad_Opcode }, | |
8783 | { Bad_Opcode }, | |
8784 | { Bad_Opcode }, | |
8785 | { Bad_Opcode }, | |
8786 | { Bad_Opcode }, | |
8787 | { Bad_Opcode }, | |
8788 | { Bad_Opcode }, | |
c0f3af97 | 8789 | /* 50 */ |
592d1631 L |
8790 | { Bad_Opcode }, |
8791 | { Bad_Opcode }, | |
8792 | { Bad_Opcode }, | |
8793 | { Bad_Opcode }, | |
8794 | { Bad_Opcode }, | |
8795 | { Bad_Opcode }, | |
8796 | { Bad_Opcode }, | |
8797 | { Bad_Opcode }, | |
c0f3af97 | 8798 | /* 58 */ |
6c30d220 L |
8799 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
8800 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
8801 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
8802 | { Bad_Opcode }, |
8803 | { Bad_Opcode }, | |
8804 | { Bad_Opcode }, | |
8805 | { Bad_Opcode }, | |
8806 | { Bad_Opcode }, | |
c0f3af97 | 8807 | /* 60 */ |
592d1631 L |
8808 | { Bad_Opcode }, |
8809 | { Bad_Opcode }, | |
8810 | { Bad_Opcode }, | |
8811 | { Bad_Opcode }, | |
8812 | { Bad_Opcode }, | |
8813 | { Bad_Opcode }, | |
8814 | { Bad_Opcode }, | |
8815 | { Bad_Opcode }, | |
c0f3af97 | 8816 | /* 68 */ |
592d1631 L |
8817 | { Bad_Opcode }, |
8818 | { Bad_Opcode }, | |
8819 | { Bad_Opcode }, | |
8820 | { Bad_Opcode }, | |
8821 | { Bad_Opcode }, | |
8822 | { Bad_Opcode }, | |
8823 | { Bad_Opcode }, | |
8824 | { Bad_Opcode }, | |
c0f3af97 | 8825 | /* 70 */ |
592d1631 L |
8826 | { Bad_Opcode }, |
8827 | { Bad_Opcode }, | |
8828 | { Bad_Opcode }, | |
8829 | { Bad_Opcode }, | |
8830 | { Bad_Opcode }, | |
8831 | { Bad_Opcode }, | |
8832 | { Bad_Opcode }, | |
8833 | { Bad_Opcode }, | |
c0f3af97 | 8834 | /* 78 */ |
6c30d220 L |
8835 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
8836 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
8837 | { Bad_Opcode }, |
8838 | { Bad_Opcode }, | |
8839 | { Bad_Opcode }, | |
8840 | { Bad_Opcode }, | |
8841 | { Bad_Opcode }, | |
8842 | { Bad_Opcode }, | |
c0f3af97 | 8843 | /* 80 */ |
592d1631 L |
8844 | { Bad_Opcode }, |
8845 | { Bad_Opcode }, | |
8846 | { Bad_Opcode }, | |
8847 | { Bad_Opcode }, | |
8848 | { Bad_Opcode }, | |
8849 | { Bad_Opcode }, | |
8850 | { Bad_Opcode }, | |
8851 | { Bad_Opcode }, | |
c0f3af97 | 8852 | /* 88 */ |
592d1631 L |
8853 | { Bad_Opcode }, |
8854 | { Bad_Opcode }, | |
8855 | { Bad_Opcode }, | |
8856 | { Bad_Opcode }, | |
6c30d220 | 8857 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 8858 | { Bad_Opcode }, |
6c30d220 | 8859 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 8860 | { Bad_Opcode }, |
c0f3af97 | 8861 | /* 90 */ |
6c30d220 L |
8862 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
8863 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
8864 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
8865 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
8866 | { Bad_Opcode }, |
8867 | { Bad_Opcode }, | |
592a252b L |
8868 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
8869 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 8870 | /* 98 */ |
592a252b L |
8871 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
8872 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
8873 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
8874 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
8875 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
8876 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
8877 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
8878 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 8879 | /* a0 */ |
592d1631 L |
8880 | { Bad_Opcode }, |
8881 | { Bad_Opcode }, | |
8882 | { Bad_Opcode }, | |
8883 | { Bad_Opcode }, | |
8884 | { Bad_Opcode }, | |
8885 | { Bad_Opcode }, | |
592a252b L |
8886 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
8887 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 8888 | /* a8 */ |
592a252b L |
8889 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
8890 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
8891 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
8892 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
8893 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
8894 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
8895 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
8896 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 8897 | /* b0 */ |
592d1631 L |
8898 | { Bad_Opcode }, |
8899 | { Bad_Opcode }, | |
8900 | { Bad_Opcode }, | |
8901 | { Bad_Opcode }, | |
8902 | { Bad_Opcode }, | |
8903 | { Bad_Opcode }, | |
592a252b L |
8904 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
8905 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 8906 | /* b8 */ |
592a252b L |
8907 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
8908 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
8909 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
8910 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
8911 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
8912 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
8913 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
8914 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 8915 | /* c0 */ |
592d1631 L |
8916 | { Bad_Opcode }, |
8917 | { Bad_Opcode }, | |
8918 | { Bad_Opcode }, | |
8919 | { Bad_Opcode }, | |
8920 | { Bad_Opcode }, | |
8921 | { Bad_Opcode }, | |
8922 | { Bad_Opcode }, | |
8923 | { Bad_Opcode }, | |
c0f3af97 | 8924 | /* c8 */ |
592d1631 L |
8925 | { Bad_Opcode }, |
8926 | { Bad_Opcode }, | |
8927 | { Bad_Opcode }, | |
8928 | { Bad_Opcode }, | |
8929 | { Bad_Opcode }, | |
8930 | { Bad_Opcode }, | |
8931 | { Bad_Opcode }, | |
48521003 | 8932 | { PREFIX_TABLE (PREFIX_VEX_0F38CF) }, |
c0f3af97 | 8933 | /* d0 */ |
592d1631 L |
8934 | { Bad_Opcode }, |
8935 | { Bad_Opcode }, | |
8936 | { Bad_Opcode }, | |
8937 | { Bad_Opcode }, | |
8938 | { Bad_Opcode }, | |
8939 | { Bad_Opcode }, | |
8940 | { Bad_Opcode }, | |
8941 | { Bad_Opcode }, | |
c0f3af97 | 8942 | /* d8 */ |
592d1631 L |
8943 | { Bad_Opcode }, |
8944 | { Bad_Opcode }, | |
8945 | { Bad_Opcode }, | |
592a252b L |
8946 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
8947 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
8948 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
8949 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
8950 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 8951 | /* e0 */ |
592d1631 L |
8952 | { Bad_Opcode }, |
8953 | { Bad_Opcode }, | |
8954 | { Bad_Opcode }, | |
8955 | { Bad_Opcode }, | |
8956 | { Bad_Opcode }, | |
8957 | { Bad_Opcode }, | |
8958 | { Bad_Opcode }, | |
8959 | { Bad_Opcode }, | |
c0f3af97 | 8960 | /* e8 */ |
592d1631 L |
8961 | { Bad_Opcode }, |
8962 | { Bad_Opcode }, | |
8963 | { Bad_Opcode }, | |
8964 | { Bad_Opcode }, | |
8965 | { Bad_Opcode }, | |
8966 | { Bad_Opcode }, | |
8967 | { Bad_Opcode }, | |
8968 | { Bad_Opcode }, | |
c0f3af97 | 8969 | /* f0 */ |
592d1631 L |
8970 | { Bad_Opcode }, |
8971 | { Bad_Opcode }, | |
f12dc422 L |
8972 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
8973 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 8974 | { Bad_Opcode }, |
6c30d220 L |
8975 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
8976 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 8977 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 8978 | /* f8 */ |
592d1631 L |
8979 | { Bad_Opcode }, |
8980 | { Bad_Opcode }, | |
8981 | { Bad_Opcode }, | |
8982 | { Bad_Opcode }, | |
8983 | { Bad_Opcode }, | |
8984 | { Bad_Opcode }, | |
8985 | { Bad_Opcode }, | |
8986 | { Bad_Opcode }, | |
c0f3af97 L |
8987 | }, |
8988 | /* VEX_0F3A */ | |
8989 | { | |
8990 | /* 00 */ | |
6c30d220 L |
8991 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
8992 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
8993 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 8994 | { Bad_Opcode }, |
592a252b L |
8995 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
8996 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
8997 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 8998 | { Bad_Opcode }, |
c0f3af97 | 8999 | /* 08 */ |
592a252b L |
9000 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
9001 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
9002 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
9003 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
9004 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
9005 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
9006 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
9007 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 9008 | /* 10 */ |
592d1631 L |
9009 | { Bad_Opcode }, |
9010 | { Bad_Opcode }, | |
9011 | { Bad_Opcode }, | |
9012 | { Bad_Opcode }, | |
592a252b L |
9013 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
9014 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
9015 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
9016 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 9017 | /* 18 */ |
592a252b L |
9018 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
9019 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
9020 | { Bad_Opcode }, |
9021 | { Bad_Opcode }, | |
9022 | { Bad_Opcode }, | |
592a252b | 9023 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
9024 | { Bad_Opcode }, |
9025 | { Bad_Opcode }, | |
c0f3af97 | 9026 | /* 20 */ |
592a252b L |
9027 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
9028 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
9029 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
9030 | { Bad_Opcode }, |
9031 | { Bad_Opcode }, | |
9032 | { Bad_Opcode }, | |
9033 | { Bad_Opcode }, | |
9034 | { Bad_Opcode }, | |
c0f3af97 | 9035 | /* 28 */ |
592d1631 L |
9036 | { Bad_Opcode }, |
9037 | { Bad_Opcode }, | |
9038 | { Bad_Opcode }, | |
9039 | { Bad_Opcode }, | |
9040 | { Bad_Opcode }, | |
9041 | { Bad_Opcode }, | |
9042 | { Bad_Opcode }, | |
9043 | { Bad_Opcode }, | |
c0f3af97 | 9044 | /* 30 */ |
43234a1e | 9045 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
1ba585e8 | 9046 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
43234a1e | 9047 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
1ba585e8 | 9048 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
592d1631 L |
9049 | { Bad_Opcode }, |
9050 | { Bad_Opcode }, | |
9051 | { Bad_Opcode }, | |
9052 | { Bad_Opcode }, | |
c0f3af97 | 9053 | /* 38 */ |
6c30d220 L |
9054 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
9055 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
9056 | { Bad_Opcode }, |
9057 | { Bad_Opcode }, | |
9058 | { Bad_Opcode }, | |
9059 | { Bad_Opcode }, | |
9060 | { Bad_Opcode }, | |
9061 | { Bad_Opcode }, | |
c0f3af97 | 9062 | /* 40 */ |
592a252b L |
9063 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
9064 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
9065 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 9066 | { Bad_Opcode }, |
592a252b | 9067 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 9068 | { Bad_Opcode }, |
6c30d220 | 9069 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 9070 | { Bad_Opcode }, |
c0f3af97 | 9071 | /* 48 */ |
592a252b L |
9072 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
9073 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
9074 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
9075 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
9076 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
9077 | { Bad_Opcode }, |
9078 | { Bad_Opcode }, | |
9079 | { Bad_Opcode }, | |
c0f3af97 | 9080 | /* 50 */ |
592d1631 L |
9081 | { Bad_Opcode }, |
9082 | { Bad_Opcode }, | |
9083 | { Bad_Opcode }, | |
9084 | { Bad_Opcode }, | |
9085 | { Bad_Opcode }, | |
9086 | { Bad_Opcode }, | |
9087 | { Bad_Opcode }, | |
9088 | { Bad_Opcode }, | |
c0f3af97 | 9089 | /* 58 */ |
592d1631 L |
9090 | { Bad_Opcode }, |
9091 | { Bad_Opcode }, | |
9092 | { Bad_Opcode }, | |
9093 | { Bad_Opcode }, | |
592a252b L |
9094 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
9095 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
9096 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
9097 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 9098 | /* 60 */ |
592a252b L |
9099 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9100 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9101 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9102 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9103 | { Bad_Opcode }, |
9104 | { Bad_Opcode }, | |
9105 | { Bad_Opcode }, | |
9106 | { Bad_Opcode }, | |
c0f3af97 | 9107 | /* 68 */ |
592a252b L |
9108 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9109 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9110 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9111 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9112 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9113 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9114 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9115 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9116 | /* 70 */ |
592d1631 L |
9117 | { Bad_Opcode }, |
9118 | { Bad_Opcode }, | |
9119 | { Bad_Opcode }, | |
9120 | { Bad_Opcode }, | |
9121 | { Bad_Opcode }, | |
9122 | { Bad_Opcode }, | |
9123 | { Bad_Opcode }, | |
9124 | { Bad_Opcode }, | |
c0f3af97 | 9125 | /* 78 */ |
592a252b L |
9126 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9127 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9128 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9129 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9130 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9131 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9132 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9133 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9134 | /* 80 */ |
592d1631 L |
9135 | { Bad_Opcode }, |
9136 | { Bad_Opcode }, | |
9137 | { Bad_Opcode }, | |
9138 | { Bad_Opcode }, | |
9139 | { Bad_Opcode }, | |
9140 | { Bad_Opcode }, | |
9141 | { Bad_Opcode }, | |
9142 | { Bad_Opcode }, | |
c0f3af97 | 9143 | /* 88 */ |
592d1631 L |
9144 | { Bad_Opcode }, |
9145 | { Bad_Opcode }, | |
9146 | { Bad_Opcode }, | |
9147 | { Bad_Opcode }, | |
9148 | { Bad_Opcode }, | |
9149 | { Bad_Opcode }, | |
9150 | { Bad_Opcode }, | |
9151 | { Bad_Opcode }, | |
c0f3af97 | 9152 | /* 90 */ |
592d1631 L |
9153 | { Bad_Opcode }, |
9154 | { Bad_Opcode }, | |
9155 | { Bad_Opcode }, | |
9156 | { Bad_Opcode }, | |
9157 | { Bad_Opcode }, | |
9158 | { Bad_Opcode }, | |
9159 | { Bad_Opcode }, | |
9160 | { Bad_Opcode }, | |
c0f3af97 | 9161 | /* 98 */ |
592d1631 L |
9162 | { Bad_Opcode }, |
9163 | { Bad_Opcode }, | |
9164 | { Bad_Opcode }, | |
9165 | { Bad_Opcode }, | |
9166 | { Bad_Opcode }, | |
9167 | { Bad_Opcode }, | |
9168 | { Bad_Opcode }, | |
9169 | { Bad_Opcode }, | |
c0f3af97 | 9170 | /* a0 */ |
592d1631 L |
9171 | { Bad_Opcode }, |
9172 | { Bad_Opcode }, | |
9173 | { Bad_Opcode }, | |
9174 | { Bad_Opcode }, | |
9175 | { Bad_Opcode }, | |
9176 | { Bad_Opcode }, | |
9177 | { Bad_Opcode }, | |
9178 | { Bad_Opcode }, | |
c0f3af97 | 9179 | /* a8 */ |
592d1631 L |
9180 | { Bad_Opcode }, |
9181 | { Bad_Opcode }, | |
9182 | { Bad_Opcode }, | |
9183 | { Bad_Opcode }, | |
9184 | { Bad_Opcode }, | |
9185 | { Bad_Opcode }, | |
9186 | { Bad_Opcode }, | |
9187 | { Bad_Opcode }, | |
c0f3af97 | 9188 | /* b0 */ |
592d1631 L |
9189 | { Bad_Opcode }, |
9190 | { Bad_Opcode }, | |
9191 | { Bad_Opcode }, | |
9192 | { Bad_Opcode }, | |
9193 | { Bad_Opcode }, | |
9194 | { Bad_Opcode }, | |
9195 | { Bad_Opcode }, | |
9196 | { Bad_Opcode }, | |
c0f3af97 | 9197 | /* b8 */ |
592d1631 L |
9198 | { Bad_Opcode }, |
9199 | { Bad_Opcode }, | |
9200 | { Bad_Opcode }, | |
9201 | { Bad_Opcode }, | |
9202 | { Bad_Opcode }, | |
9203 | { Bad_Opcode }, | |
9204 | { Bad_Opcode }, | |
9205 | { Bad_Opcode }, | |
c0f3af97 | 9206 | /* c0 */ |
592d1631 L |
9207 | { Bad_Opcode }, |
9208 | { Bad_Opcode }, | |
9209 | { Bad_Opcode }, | |
9210 | { Bad_Opcode }, | |
9211 | { Bad_Opcode }, | |
9212 | { Bad_Opcode }, | |
9213 | { Bad_Opcode }, | |
9214 | { Bad_Opcode }, | |
c0f3af97 | 9215 | /* c8 */ |
592d1631 L |
9216 | { Bad_Opcode }, |
9217 | { Bad_Opcode }, | |
9218 | { Bad_Opcode }, | |
9219 | { Bad_Opcode }, | |
9220 | { Bad_Opcode }, | |
9221 | { Bad_Opcode }, | |
48521003 IT |
9222 | { PREFIX_TABLE(PREFIX_VEX_0F3ACE) }, |
9223 | { PREFIX_TABLE(PREFIX_VEX_0F3ACF) }, | |
c0f3af97 | 9224 | /* d0 */ |
592d1631 L |
9225 | { Bad_Opcode }, |
9226 | { Bad_Opcode }, | |
9227 | { Bad_Opcode }, | |
9228 | { Bad_Opcode }, | |
9229 | { Bad_Opcode }, | |
9230 | { Bad_Opcode }, | |
9231 | { Bad_Opcode }, | |
9232 | { Bad_Opcode }, | |
c0f3af97 | 9233 | /* d8 */ |
592d1631 L |
9234 | { Bad_Opcode }, |
9235 | { Bad_Opcode }, | |
9236 | { Bad_Opcode }, | |
9237 | { Bad_Opcode }, | |
9238 | { Bad_Opcode }, | |
9239 | { Bad_Opcode }, | |
9240 | { Bad_Opcode }, | |
592a252b | 9241 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9242 | /* e0 */ |
592d1631 L |
9243 | { Bad_Opcode }, |
9244 | { Bad_Opcode }, | |
9245 | { Bad_Opcode }, | |
9246 | { Bad_Opcode }, | |
9247 | { Bad_Opcode }, | |
9248 | { Bad_Opcode }, | |
9249 | { Bad_Opcode }, | |
9250 | { Bad_Opcode }, | |
c0f3af97 | 9251 | /* e8 */ |
592d1631 L |
9252 | { Bad_Opcode }, |
9253 | { Bad_Opcode }, | |
9254 | { Bad_Opcode }, | |
9255 | { Bad_Opcode }, | |
9256 | { Bad_Opcode }, | |
9257 | { Bad_Opcode }, | |
9258 | { Bad_Opcode }, | |
9259 | { Bad_Opcode }, | |
c0f3af97 | 9260 | /* f0 */ |
6c30d220 | 9261 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9262 | { Bad_Opcode }, |
9263 | { Bad_Opcode }, | |
9264 | { Bad_Opcode }, | |
9265 | { Bad_Opcode }, | |
9266 | { Bad_Opcode }, | |
9267 | { Bad_Opcode }, | |
9268 | { Bad_Opcode }, | |
c0f3af97 | 9269 | /* f8 */ |
592d1631 L |
9270 | { Bad_Opcode }, |
9271 | { Bad_Opcode }, | |
9272 | { Bad_Opcode }, | |
9273 | { Bad_Opcode }, | |
9274 | { Bad_Opcode }, | |
9275 | { Bad_Opcode }, | |
9276 | { Bad_Opcode }, | |
9277 | { Bad_Opcode }, | |
c0f3af97 L |
9278 | }, |
9279 | }; | |
9280 | ||
43234a1e | 9281 | #include "i386-dis-evex.h" |
ad692897 | 9282 | |
c0f3af97 | 9283 | static const struct dis386 vex_len_table[][2] = { |
18897deb | 9284 | /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */ |
c0f3af97 | 9285 | { |
18897deb | 9286 | { "vmovlpX", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9287 | }, |
9288 | ||
592a252b | 9289 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9290 | { |
ec6f095a | 9291 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9292 | }, |
9293 | ||
592a252b | 9294 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9295 | { |
bf926894 | 9296 | { "vmovlpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
9297 | }, |
9298 | ||
18897deb | 9299 | /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */ |
c0f3af97 | 9300 | { |
18897deb | 9301 | { "vmovhpX", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9302 | }, |
9303 | ||
592a252b | 9304 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9305 | { |
ec6f095a | 9306 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9307 | }, |
9308 | ||
592a252b | 9309 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9310 | { |
bf926894 | 9311 | { "vmovhpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
9312 | }, |
9313 | ||
43234a1e L |
9314 | /* VEX_LEN_0F41_P_0 */ |
9315 | { | |
9316 | { Bad_Opcode }, | |
9317 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9318 | }, | |
1ba585e8 IT |
9319 | /* VEX_LEN_0F41_P_2 */ |
9320 | { | |
9321 | { Bad_Opcode }, | |
9322 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
9323 | }, | |
43234a1e L |
9324 | /* VEX_LEN_0F42_P_0 */ |
9325 | { | |
9326 | { Bad_Opcode }, | |
9327 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9328 | }, | |
1ba585e8 IT |
9329 | /* VEX_LEN_0F42_P_2 */ |
9330 | { | |
9331 | { Bad_Opcode }, | |
9332 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
9333 | }, | |
43234a1e L |
9334 | /* VEX_LEN_0F44_P_0 */ |
9335 | { | |
9336 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9337 | }, | |
1ba585e8 IT |
9338 | /* VEX_LEN_0F44_P_2 */ |
9339 | { | |
9340 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
9341 | }, | |
43234a1e L |
9342 | /* VEX_LEN_0F45_P_0 */ |
9343 | { | |
9344 | { Bad_Opcode }, | |
9345 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9346 | }, | |
1ba585e8 IT |
9347 | /* VEX_LEN_0F45_P_2 */ |
9348 | { | |
9349 | { Bad_Opcode }, | |
9350 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
9351 | }, | |
43234a1e L |
9352 | /* VEX_LEN_0F46_P_0 */ |
9353 | { | |
9354 | { Bad_Opcode }, | |
9355 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9356 | }, | |
1ba585e8 IT |
9357 | /* VEX_LEN_0F46_P_2 */ |
9358 | { | |
9359 | { Bad_Opcode }, | |
9360 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
9361 | }, | |
43234a1e L |
9362 | /* VEX_LEN_0F47_P_0 */ |
9363 | { | |
9364 | { Bad_Opcode }, | |
9365 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9366 | }, | |
1ba585e8 IT |
9367 | /* VEX_LEN_0F47_P_2 */ |
9368 | { | |
9369 | { Bad_Opcode }, | |
9370 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
9371 | }, | |
9372 | /* VEX_LEN_0F4A_P_0 */ | |
9373 | { | |
9374 | { Bad_Opcode }, | |
9375 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
9376 | }, | |
9377 | /* VEX_LEN_0F4A_P_2 */ | |
9378 | { | |
9379 | { Bad_Opcode }, | |
9380 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
9381 | }, | |
9382 | /* VEX_LEN_0F4B_P_0 */ | |
9383 | { | |
9384 | { Bad_Opcode }, | |
9385 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
9386 | }, | |
43234a1e L |
9387 | /* VEX_LEN_0F4B_P_2 */ |
9388 | { | |
9389 | { Bad_Opcode }, | |
9390 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9391 | }, | |
9392 | ||
ec6f095a | 9393 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9394 | { |
ec6f095a | 9395 | { "vmovK", { XMScalar, Edq }, 0 }, |
c0f3af97 L |
9396 | }, |
9397 | ||
ec6f095a | 9398 | /* VEX_LEN_0F77_P_1 */ |
c0f3af97 | 9399 | { |
ec6f095a L |
9400 | { "vzeroupper", { XX }, 0 }, |
9401 | { "vzeroall", { XX }, 0 }, | |
c0f3af97 L |
9402 | }, |
9403 | ||
ec6f095a | 9404 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9405 | { |
ec6f095a | 9406 | { "vmovq", { XMScalar, EXqScalar }, 0 }, |
c0f3af97 L |
9407 | }, |
9408 | ||
ec6f095a | 9409 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9410 | { |
ec6f095a | 9411 | { "vmovK", { Edq, XMScalar }, 0 }, |
c0f3af97 L |
9412 | }, |
9413 | ||
ec6f095a | 9414 | /* VEX_LEN_0F90_P_0 */ |
c0f3af97 | 9415 | { |
ec6f095a | 9416 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, |
c0f3af97 L |
9417 | }, |
9418 | ||
ec6f095a | 9419 | /* VEX_LEN_0F90_P_2 */ |
c0f3af97 | 9420 | { |
ec6f095a | 9421 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, |
c0f3af97 L |
9422 | }, |
9423 | ||
ec6f095a | 9424 | /* VEX_LEN_0F91_P_0 */ |
c0f3af97 | 9425 | { |
ec6f095a | 9426 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, |
c0f3af97 L |
9427 | }, |
9428 | ||
ec6f095a | 9429 | /* VEX_LEN_0F91_P_2 */ |
c0f3af97 | 9430 | { |
ec6f095a | 9431 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, |
c0f3af97 L |
9432 | }, |
9433 | ||
ec6f095a | 9434 | /* VEX_LEN_0F92_P_0 */ |
c0f3af97 | 9435 | { |
ec6f095a | 9436 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, |
c0f3af97 L |
9437 | }, |
9438 | ||
ec6f095a | 9439 | /* VEX_LEN_0F92_P_2 */ |
c0f3af97 | 9440 | { |
ec6f095a | 9441 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, |
c0f3af97 L |
9442 | }, |
9443 | ||
ec6f095a | 9444 | /* VEX_LEN_0F92_P_3 */ |
c0f3af97 | 9445 | { |
58a211d2 | 9446 | { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) }, |
c0f3af97 L |
9447 | }, |
9448 | ||
ec6f095a | 9449 | /* VEX_LEN_0F93_P_0 */ |
c0f3af97 | 9450 | { |
ec6f095a | 9451 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, |
c0f3af97 L |
9452 | }, |
9453 | ||
ec6f095a | 9454 | /* VEX_LEN_0F93_P_2 */ |
c0f3af97 | 9455 | { |
ec6f095a | 9456 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, |
c0f3af97 L |
9457 | }, |
9458 | ||
ec6f095a | 9459 | /* VEX_LEN_0F93_P_3 */ |
c0f3af97 | 9460 | { |
58a211d2 | 9461 | { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) }, |
c0f3af97 L |
9462 | }, |
9463 | ||
ec6f095a | 9464 | /* VEX_LEN_0F98_P_0 */ |
43234a1e L |
9465 | { |
9466 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9467 | }, | |
9468 | ||
1ba585e8 IT |
9469 | /* VEX_LEN_0F98_P_2 */ |
9470 | { | |
9471 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
9472 | }, | |
9473 | ||
9474 | /* VEX_LEN_0F99_P_0 */ | |
9475 | { | |
9476 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
9477 | }, | |
9478 | ||
9479 | /* VEX_LEN_0F99_P_2 */ | |
9480 | { | |
9481 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
9482 | }, | |
9483 | ||
6c30d220 | 9484 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9485 | { |
ec6f095a | 9486 | { "vldmxcsr", { Md }, 0 }, |
c0f3af97 L |
9487 | }, |
9488 | ||
6c30d220 | 9489 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9490 | { |
ec6f095a | 9491 | { "vstmxcsr", { Md }, 0 }, |
c0f3af97 L |
9492 | }, |
9493 | ||
6c30d220 | 9494 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 9495 | { |
b50c9f31 | 9496 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
c0f3af97 L |
9497 | }, |
9498 | ||
6c30d220 | 9499 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 9500 | { |
b50c9f31 | 9501 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
c0f3af97 L |
9502 | }, |
9503 | ||
6c30d220 | 9504 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 9505 | { |
ec6f095a | 9506 | { "vmovq", { EXqScalarS, XMScalar }, 0 }, |
c0f3af97 L |
9507 | }, |
9508 | ||
6c30d220 | 9509 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 9510 | { |
ec6f095a | 9511 | { "vmaskmovdqu", { XM, XS }, 0 }, |
c0f3af97 L |
9512 | }, |
9513 | ||
6c30d220 | 9514 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 9515 | { |
6c30d220 L |
9516 | { Bad_Opcode }, |
9517 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
9518 | }, |
9519 | ||
6c30d220 | 9520 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 9521 | { |
6c30d220 L |
9522 | { Bad_Opcode }, |
9523 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
9524 | }, |
9525 | ||
6c30d220 | 9526 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 9527 | { |
6c30d220 L |
9528 | { Bad_Opcode }, |
9529 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
9530 | }, |
9531 | ||
6c30d220 | 9532 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 9533 | { |
6c30d220 L |
9534 | { Bad_Opcode }, |
9535 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
9536 | }, |
9537 | ||
592a252b | 9538 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 9539 | { |
ec6f095a | 9540 | { "vphminposuw", { XM, EXx }, 0 }, |
c0f3af97 L |
9541 | }, |
9542 | ||
6c30d220 L |
9543 | /* VEX_LEN_0F385A_P_2_M_0 */ |
9544 | { | |
9545 | { Bad_Opcode }, | |
9546 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
9547 | }, | |
9548 | ||
592a252b | 9549 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 9550 | { |
ec6f095a | 9551 | { "vaesimc", { XM, EXx }, 0 }, |
a5ff0eb2 L |
9552 | }, |
9553 | ||
f12dc422 L |
9554 | /* VEX_LEN_0F38F2_P_0 */ |
9555 | { | |
bf890a93 | 9556 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
f12dc422 L |
9557 | }, |
9558 | ||
9559 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
9560 | { | |
bf890a93 | 9561 | { "blsrS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9562 | }, |
9563 | ||
9564 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
9565 | { | |
bf890a93 | 9566 | { "blsmskS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9567 | }, |
9568 | ||
9569 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
9570 | { | |
bf890a93 | 9571 | { "blsiS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9572 | }, |
9573 | ||
6c30d220 L |
9574 | /* VEX_LEN_0F38F5_P_0 */ |
9575 | { | |
bf890a93 | 9576 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9577 | }, |
9578 | ||
9579 | /* VEX_LEN_0F38F5_P_1 */ | |
9580 | { | |
bf890a93 | 9581 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9582 | }, |
9583 | ||
9584 | /* VEX_LEN_0F38F5_P_3 */ | |
9585 | { | |
bf890a93 | 9586 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9587 | }, |
9588 | ||
9589 | /* VEX_LEN_0F38F6_P_3 */ | |
9590 | { | |
bf890a93 | 9591 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9592 | }, |
9593 | ||
f12dc422 L |
9594 | /* VEX_LEN_0F38F7_P_0 */ |
9595 | { | |
bf890a93 | 9596 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
9597 | }, |
9598 | ||
6c30d220 L |
9599 | /* VEX_LEN_0F38F7_P_1 */ |
9600 | { | |
bf890a93 | 9601 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9602 | }, |
9603 | ||
9604 | /* VEX_LEN_0F38F7_P_2 */ | |
9605 | { | |
bf890a93 | 9606 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9607 | }, |
9608 | ||
9609 | /* VEX_LEN_0F38F7_P_3 */ | |
9610 | { | |
bf890a93 | 9611 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9612 | }, |
9613 | ||
9614 | /* VEX_LEN_0F3A00_P_2 */ | |
9615 | { | |
9616 | { Bad_Opcode }, | |
9617 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
9618 | }, | |
9619 | ||
9620 | /* VEX_LEN_0F3A01_P_2 */ | |
9621 | { | |
9622 | { Bad_Opcode }, | |
9623 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
9624 | }, | |
9625 | ||
592a252b | 9626 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 9627 | { |
592d1631 | 9628 | { Bad_Opcode }, |
592a252b | 9629 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
9630 | }, |
9631 | ||
592a252b | 9632 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 9633 | { |
b50c9f31 | 9634 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
c0f3af97 L |
9635 | }, |
9636 | ||
592a252b | 9637 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 9638 | { |
b50c9f31 | 9639 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
c0f3af97 L |
9640 | }, |
9641 | ||
592a252b | 9642 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 | 9643 | { |
bf890a93 | 9644 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
c0f3af97 L |
9645 | }, |
9646 | ||
592a252b | 9647 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 | 9648 | { |
bf890a93 | 9649 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
c0f3af97 L |
9650 | }, |
9651 | ||
592a252b | 9652 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 9653 | { |
592d1631 | 9654 | { Bad_Opcode }, |
592a252b | 9655 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
9656 | }, |
9657 | ||
592a252b | 9658 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 9659 | { |
592d1631 | 9660 | { Bad_Opcode }, |
592a252b | 9661 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
9662 | }, |
9663 | ||
592a252b | 9664 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 9665 | { |
b50c9f31 | 9666 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
c0f3af97 L |
9667 | }, |
9668 | ||
592a252b | 9669 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 9670 | { |
ec6f095a | 9671 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
c0f3af97 L |
9672 | }, |
9673 | ||
592a252b | 9674 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 | 9675 | { |
bf890a93 | 9676 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
c0f3af97 L |
9677 | }, |
9678 | ||
43234a1e L |
9679 | /* VEX_LEN_0F3A30_P_2 */ |
9680 | { | |
9681 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
9682 | }, | |
9683 | ||
1ba585e8 IT |
9684 | /* VEX_LEN_0F3A31_P_2 */ |
9685 | { | |
9686 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, | |
9687 | }, | |
9688 | ||
43234a1e L |
9689 | /* VEX_LEN_0F3A32_P_2 */ |
9690 | { | |
9691 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
9692 | }, | |
9693 | ||
1ba585e8 IT |
9694 | /* VEX_LEN_0F3A33_P_2 */ |
9695 | { | |
9696 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, | |
9697 | }, | |
9698 | ||
6c30d220 | 9699 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 9700 | { |
6c30d220 L |
9701 | { Bad_Opcode }, |
9702 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
9703 | }, |
9704 | ||
6c30d220 | 9705 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 9706 | { |
6c30d220 L |
9707 | { Bad_Opcode }, |
9708 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
9709 | }, | |
9710 | ||
9711 | /* VEX_LEN_0F3A41_P_2 */ | |
9712 | { | |
ec6f095a | 9713 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
c0f3af97 L |
9714 | }, |
9715 | ||
6c30d220 | 9716 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 9717 | { |
6c30d220 L |
9718 | { Bad_Opcode }, |
9719 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
9720 | }, |
9721 | ||
592a252b | 9722 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 9723 | { |
15c7c1d8 | 9724 | { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
9725 | }, |
9726 | ||
592a252b | 9727 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 9728 | { |
15c7c1d8 | 9729 | { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
9730 | }, |
9731 | ||
592a252b | 9732 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 9733 | { |
ec6f095a | 9734 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9735 | }, |
9736 | ||
592a252b | 9737 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 9738 | { |
ec6f095a | 9739 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9740 | }, |
9741 | ||
592a252b | 9742 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 9743 | { |
3a2430e0 | 9744 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9745 | }, |
9746 | ||
592a252b | 9747 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 9748 | { |
3a2430e0 | 9749 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9750 | }, |
9751 | ||
592a252b | 9752 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 9753 | { |
3a2430e0 | 9754 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9755 | }, |
9756 | ||
592a252b | 9757 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 9758 | { |
3a2430e0 | 9759 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9760 | }, |
9761 | ||
592a252b | 9762 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 9763 | { |
3a2430e0 | 9764 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9765 | }, |
9766 | ||
592a252b | 9767 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 9768 | { |
3a2430e0 | 9769 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9770 | }, |
9771 | ||
592a252b | 9772 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 9773 | { |
3a2430e0 | 9774 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9775 | }, |
9776 | ||
592a252b | 9777 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 9778 | { |
3a2430e0 | 9779 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9780 | }, |
9781 | ||
592a252b | 9782 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 9783 | { |
ec6f095a | 9784 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
a5ff0eb2 | 9785 | }, |
4c807e72 | 9786 | |
6c30d220 L |
9787 | /* VEX_LEN_0F3AF0_P_3 */ |
9788 | { | |
bf890a93 | 9789 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
9790 | }, |
9791 | ||
ff688e1f L |
9792 | /* VEX_LEN_0FXOP_08_CC */ |
9793 | { | |
be92cb14 | 9794 | { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9795 | }, |
9796 | ||
9797 | /* VEX_LEN_0FXOP_08_CD */ | |
9798 | { | |
be92cb14 | 9799 | { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9800 | }, |
9801 | ||
9802 | /* VEX_LEN_0FXOP_08_CE */ | |
9803 | { | |
be92cb14 | 9804 | { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9805 | }, |
9806 | ||
9807 | /* VEX_LEN_0FXOP_08_CF */ | |
9808 | { | |
be92cb14 | 9809 | { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9810 | }, |
9811 | ||
9812 | /* VEX_LEN_0FXOP_08_EC */ | |
9813 | { | |
be92cb14 | 9814 | { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9815 | }, |
9816 | ||
9817 | /* VEX_LEN_0FXOP_08_ED */ | |
9818 | { | |
be92cb14 | 9819 | { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9820 | }, |
9821 | ||
9822 | /* VEX_LEN_0FXOP_08_EE */ | |
9823 | { | |
be92cb14 | 9824 | { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9825 | }, |
9826 | ||
9827 | /* VEX_LEN_0FXOP_08_EF */ | |
9828 | { | |
be92cb14 | 9829 | { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9830 | }, |
9831 | ||
592a252b | 9832 | /* VEX_LEN_0FXOP_09_80 */ |
5dd85c99 | 9833 | { |
bf890a93 IT |
9834 | { "vfrczps", { XM, EXxmm }, 0 }, |
9835 | { "vfrczps", { XM, EXymmq }, 0 }, | |
5dd85c99 | 9836 | }, |
4c807e72 | 9837 | |
592a252b | 9838 | /* VEX_LEN_0FXOP_09_81 */ |
5dd85c99 | 9839 | { |
bf890a93 IT |
9840 | { "vfrczpd", { XM, EXxmm }, 0 }, |
9841 | { "vfrczpd", { XM, EXymmq }, 0 }, | |
5dd85c99 | 9842 | }, |
331d2d0d L |
9843 | }; |
9844 | ||
ad692897 | 9845 | #include "i386-dis-evex-len.h" |
04e2a182 | 9846 | |
9e30b8e0 | 9847 | static const struct dis386 vex_w_table[][2] = { |
43234a1e L |
9848 | { |
9849 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
9850 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
9851 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
9852 | }, |
9853 | { | |
9854 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
9855 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
9856 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
9857 | }, |
9858 | { | |
9859 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
9860 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
9861 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
9862 | }, |
9863 | { | |
9864 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
9865 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
9866 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
9867 | }, |
9868 | { | |
9869 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
9870 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
9871 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
9872 | }, |
9873 | { | |
9874 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
9875 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
9876 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
9877 | }, |
9878 | { | |
ec6f095a L |
9879 | /* VEX_W_0F45_P_0_LEN_1 */ |
9880 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, | |
9881 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
9e30b8e0 L |
9882 | }, |
9883 | { | |
ec6f095a L |
9884 | /* VEX_W_0F45_P_2_LEN_1 */ |
9885 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, | |
9886 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
9e30b8e0 L |
9887 | }, |
9888 | { | |
ec6f095a L |
9889 | /* VEX_W_0F46_P_0_LEN_1 */ |
9890 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, | |
9891 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
9e30b8e0 L |
9892 | }, |
9893 | { | |
ec6f095a L |
9894 | /* VEX_W_0F46_P_2_LEN_1 */ |
9895 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, | |
9896 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
9e30b8e0 L |
9897 | }, |
9898 | { | |
ec6f095a L |
9899 | /* VEX_W_0F47_P_0_LEN_1 */ |
9900 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, | |
9901 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
9e30b8e0 L |
9902 | }, |
9903 | { | |
ec6f095a L |
9904 | /* VEX_W_0F47_P_2_LEN_1 */ |
9905 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, | |
9906 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
9e30b8e0 L |
9907 | }, |
9908 | { | |
ec6f095a L |
9909 | /* VEX_W_0F4A_P_0_LEN_1 */ |
9910 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, | |
9911 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
9e30b8e0 L |
9912 | }, |
9913 | { | |
ec6f095a L |
9914 | /* VEX_W_0F4A_P_2_LEN_1 */ |
9915 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, | |
9916 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
9e30b8e0 L |
9917 | }, |
9918 | { | |
ec6f095a L |
9919 | /* VEX_W_0F4B_P_0_LEN_1 */ |
9920 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, | |
9921 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
9e30b8e0 L |
9922 | }, |
9923 | { | |
ec6f095a L |
9924 | /* VEX_W_0F4B_P_2_LEN_1 */ |
9925 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, | |
9e30b8e0 L |
9926 | }, |
9927 | { | |
ec6f095a L |
9928 | /* VEX_W_0F90_P_0_LEN_0 */ |
9929 | { "kmovw", { MaskG, MaskE }, 0 }, | |
9930 | { "kmovq", { MaskG, MaskE }, 0 }, | |
9e30b8e0 L |
9931 | }, |
9932 | { | |
ec6f095a L |
9933 | /* VEX_W_0F90_P_2_LEN_0 */ |
9934 | { "kmovb", { MaskG, MaskBDE }, 0 }, | |
9935 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
9e30b8e0 L |
9936 | }, |
9937 | { | |
ec6f095a L |
9938 | /* VEX_W_0F91_P_0_LEN_0 */ |
9939 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, | |
9940 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
9e30b8e0 L |
9941 | }, |
9942 | { | |
ec6f095a L |
9943 | /* VEX_W_0F91_P_2_LEN_0 */ |
9944 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, | |
9945 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
9e30b8e0 L |
9946 | }, |
9947 | { | |
ec6f095a L |
9948 | /* VEX_W_0F92_P_0_LEN_0 */ |
9949 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, | |
9e30b8e0 L |
9950 | }, |
9951 | { | |
ec6f095a L |
9952 | /* VEX_W_0F92_P_2_LEN_0 */ |
9953 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, | |
9e30b8e0 | 9954 | }, |
9e30b8e0 | 9955 | { |
ec6f095a L |
9956 | /* VEX_W_0F93_P_0_LEN_0 */ |
9957 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, | |
9e30b8e0 L |
9958 | }, |
9959 | { | |
ec6f095a L |
9960 | /* VEX_W_0F93_P_2_LEN_0 */ |
9961 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, | |
9e30b8e0 | 9962 | }, |
9e30b8e0 | 9963 | { |
ec6f095a L |
9964 | /* VEX_W_0F98_P_0_LEN_0 */ |
9965 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, | |
9966 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
9e30b8e0 L |
9967 | }, |
9968 | { | |
ec6f095a L |
9969 | /* VEX_W_0F98_P_2_LEN_0 */ |
9970 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, | |
9971 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
9e30b8e0 L |
9972 | }, |
9973 | { | |
ec6f095a L |
9974 | /* VEX_W_0F99_P_0_LEN_0 */ |
9975 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, | |
9976 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
9e30b8e0 L |
9977 | }, |
9978 | { | |
ec6f095a L |
9979 | /* VEX_W_0F99_P_2_LEN_0 */ |
9980 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, | |
9981 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
9e30b8e0 | 9982 | }, |
9e30b8e0 | 9983 | { |
592a252b | 9984 | /* VEX_W_0F380C_P_2 */ |
bf890a93 | 9985 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
9986 | }, |
9987 | { | |
592a252b | 9988 | /* VEX_W_0F380D_P_2 */ |
bf890a93 | 9989 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
9990 | }, |
9991 | { | |
592a252b | 9992 | /* VEX_W_0F380E_P_2 */ |
bf890a93 | 9993 | { "vtestps", { XM, EXx }, 0 }, |
9e30b8e0 L |
9994 | }, |
9995 | { | |
592a252b | 9996 | /* VEX_W_0F380F_P_2 */ |
bf890a93 | 9997 | { "vtestpd", { XM, EXx }, 0 }, |
9e30b8e0 | 9998 | }, |
6c30d220 L |
9999 | { |
10000 | /* VEX_W_0F3816_P_2 */ | |
bf890a93 | 10001 | { "vpermps", { XM, Vex, EXx }, 0 }, |
6c30d220 | 10002 | }, |
bcf2684f | 10003 | { |
6c30d220 | 10004 | /* VEX_W_0F3818_P_2 */ |
bf890a93 | 10005 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
bcf2684f | 10006 | }, |
9e30b8e0 | 10007 | { |
6c30d220 | 10008 | /* VEX_W_0F3819_P_2 */ |
bf890a93 | 10009 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
9e30b8e0 L |
10010 | }, |
10011 | { | |
592a252b | 10012 | /* VEX_W_0F381A_P_2_M_0 */ |
bf890a93 | 10013 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
9e30b8e0 | 10014 | }, |
53aa04a0 | 10015 | { |
592a252b | 10016 | /* VEX_W_0F382C_P_2_M_0 */ |
bf890a93 | 10017 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
10018 | }, |
10019 | { | |
592a252b | 10020 | /* VEX_W_0F382D_P_2_M_0 */ |
bf890a93 | 10021 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
10022 | }, |
10023 | { | |
592a252b | 10024 | /* VEX_W_0F382E_P_2_M_0 */ |
bf890a93 | 10025 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
53aa04a0 L |
10026 | }, |
10027 | { | |
592a252b | 10028 | /* VEX_W_0F382F_P_2_M_0 */ |
bf890a93 | 10029 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
53aa04a0 | 10030 | }, |
6c30d220 L |
10031 | { |
10032 | /* VEX_W_0F3836_P_2 */ | |
bf890a93 | 10033 | { "vpermd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 | 10034 | }, |
6c30d220 L |
10035 | { |
10036 | /* VEX_W_0F3846_P_2 */ | |
bf890a93 | 10037 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
10038 | }, |
10039 | { | |
10040 | /* VEX_W_0F3858_P_2 */ | |
bf890a93 | 10041 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
6c30d220 L |
10042 | }, |
10043 | { | |
10044 | /* VEX_W_0F3859_P_2 */ | |
bf890a93 | 10045 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
6c30d220 L |
10046 | }, |
10047 | { | |
10048 | /* VEX_W_0F385A_P_2_M_0 */ | |
bf890a93 | 10049 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
6c30d220 L |
10050 | }, |
10051 | { | |
10052 | /* VEX_W_0F3878_P_2 */ | |
bf890a93 | 10053 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
6c30d220 L |
10054 | }, |
10055 | { | |
10056 | /* VEX_W_0F3879_P_2 */ | |
bf890a93 | 10057 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
6c30d220 | 10058 | }, |
48521003 IT |
10059 | { |
10060 | /* VEX_W_0F38CF_P_2 */ | |
10061 | { "vgf2p8mulb", { XM, Vex, EXx }, 0 }, | |
10062 | }, | |
6c30d220 L |
10063 | { |
10064 | /* VEX_W_0F3A00_P_2 */ | |
10065 | { Bad_Opcode }, | |
bf890a93 | 10066 | { "vpermq", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
10067 | }, |
10068 | { | |
10069 | /* VEX_W_0F3A01_P_2 */ | |
10070 | { Bad_Opcode }, | |
bf890a93 | 10071 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
10072 | }, |
10073 | { | |
10074 | /* VEX_W_0F3A02_P_2 */ | |
bf890a93 | 10075 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
6c30d220 | 10076 | }, |
9e30b8e0 | 10077 | { |
592a252b | 10078 | /* VEX_W_0F3A04_P_2 */ |
bf890a93 | 10079 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10080 | }, |
10081 | { | |
592a252b | 10082 | /* VEX_W_0F3A05_P_2 */ |
bf890a93 | 10083 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10084 | }, |
10085 | { | |
592a252b | 10086 | /* VEX_W_0F3A06_P_2 */ |
bf890a93 | 10087 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
9e30b8e0 | 10088 | }, |
9e30b8e0 | 10089 | { |
592a252b | 10090 | /* VEX_W_0F3A18_P_2 */ |
bf890a93 | 10091 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
9e30b8e0 L |
10092 | }, |
10093 | { | |
592a252b | 10094 | /* VEX_W_0F3A19_P_2 */ |
bf890a93 | 10095 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
9e30b8e0 | 10096 | }, |
43234a1e | 10097 | { |
1ba585e8 | 10098 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
ab4e4ed5 AF |
10099 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
10100 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, | |
43234a1e L |
10101 | }, |
10102 | { | |
1ba585e8 | 10103 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
ab4e4ed5 AF |
10104 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
10105 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, | |
1ba585e8 IT |
10106 | }, |
10107 | { | |
10108 | /* VEX_W_0F3A32_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10109 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
10110 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, | |
43234a1e | 10111 | }, |
1ba585e8 IT |
10112 | { |
10113 | /* VEX_W_0F3A33_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10114 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
10115 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, | |
1ba585e8 | 10116 | }, |
6c30d220 L |
10117 | { |
10118 | /* VEX_W_0F3A38_P_2 */ | |
bf890a93 | 10119 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
6c30d220 L |
10120 | }, |
10121 | { | |
10122 | /* VEX_W_0F3A39_P_2 */ | |
bf890a93 | 10123 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
6c30d220 | 10124 | }, |
6c30d220 L |
10125 | { |
10126 | /* VEX_W_0F3A46_P_2 */ | |
bf890a93 | 10127 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
6c30d220 | 10128 | }, |
a683cc34 | 10129 | { |
592a252b | 10130 | /* VEX_W_0F3A48_P_2 */ |
bf890a93 IT |
10131 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10132 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 SP |
10133 | }, |
10134 | { | |
592a252b | 10135 | /* VEX_W_0F3A49_P_2 */ |
bf890a93 IT |
10136 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10137 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 | 10138 | }, |
9e30b8e0 | 10139 | { |
592a252b | 10140 | /* VEX_W_0F3A4A_P_2 */ |
bf890a93 | 10141 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10142 | }, |
10143 | { | |
592a252b | 10144 | /* VEX_W_0F3A4B_P_2 */ |
bf890a93 | 10145 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10146 | }, |
10147 | { | |
592a252b | 10148 | /* VEX_W_0F3A4C_P_2 */ |
bf890a93 | 10149 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 | 10150 | }, |
48521003 IT |
10151 | { |
10152 | /* VEX_W_0F3ACE_P_2 */ | |
10153 | { Bad_Opcode }, | |
10154 | { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 }, | |
10155 | }, | |
10156 | { | |
10157 | /* VEX_W_0F3ACF_P_2 */ | |
10158 | { Bad_Opcode }, | |
10159 | { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 }, | |
10160 | }, | |
ad692897 L |
10161 | |
10162 | #include "i386-dis-evex-w.h" | |
9e30b8e0 L |
10163 | }; |
10164 | ||
10165 | static const struct dis386 mod_table[][2] = { | |
10166 | { | |
10167 | /* MOD_8D */ | |
bf890a93 | 10168 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 10169 | }, |
42164a71 L |
10170 | { |
10171 | /* MOD_C6_REG_7 */ | |
10172 | { Bad_Opcode }, | |
10173 | { RM_TABLE (RM_C6_REG_7) }, | |
10174 | }, | |
10175 | { | |
10176 | /* MOD_C7_REG_7 */ | |
10177 | { Bad_Opcode }, | |
10178 | { RM_TABLE (RM_C7_REG_7) }, | |
10179 | }, | |
4a357820 MZ |
10180 | { |
10181 | /* MOD_FF_REG_3 */ | |
8f570d62 | 10182 | { "{l|}call^", { indirEp }, 0 }, |
4a357820 MZ |
10183 | }, |
10184 | { | |
10185 | /* MOD_FF_REG_5 */ | |
8f570d62 | 10186 | { "{l|}jmp^", { indirEp }, 0 }, |
4a357820 | 10187 | }, |
9e30b8e0 L |
10188 | { |
10189 | /* MOD_0F01_REG_0 */ | |
10190 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
10191 | { RM_TABLE (RM_0F01_REG_0) }, | |
10192 | }, | |
10193 | { | |
10194 | /* MOD_0F01_REG_1 */ | |
10195 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
10196 | { RM_TABLE (RM_0F01_REG_1) }, | |
10197 | }, | |
10198 | { | |
10199 | /* MOD_0F01_REG_2 */ | |
10200 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
10201 | { RM_TABLE (RM_0F01_REG_2) }, | |
10202 | }, | |
10203 | { | |
10204 | /* MOD_0F01_REG_3 */ | |
10205 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
10206 | { RM_TABLE (RM_0F01_REG_3) }, | |
10207 | }, | |
8eab4136 L |
10208 | { |
10209 | /* MOD_0F01_REG_5 */ | |
f8687e93 JB |
10210 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) }, |
10211 | { RM_TABLE (RM_0F01_REG_5_MOD_3) }, | |
8eab4136 | 10212 | }, |
9e30b8e0 L |
10213 | { |
10214 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 10215 | { "invlpg", { Mb }, 0 }, |
f8687e93 | 10216 | { RM_TABLE (RM_0F01_REG_7_MOD_3) }, |
9e30b8e0 L |
10217 | }, |
10218 | { | |
10219 | /* MOD_0F12_PREFIX_0 */ | |
18897deb JB |
10220 | { "movlpX", { XM, EXq }, 0 }, |
10221 | { "movhlps", { XM, EXq }, 0 }, | |
10222 | }, | |
10223 | { | |
10224 | /* MOD_0F12_PREFIX_2 */ | |
10225 | { "movlpX", { XM, EXq }, 0 }, | |
9e30b8e0 L |
10226 | }, |
10227 | { | |
10228 | /* MOD_0F13 */ | |
507bd325 | 10229 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10230 | }, |
10231 | { | |
10232 | /* MOD_0F16_PREFIX_0 */ | |
18897deb | 10233 | { "movhpX", { XM, EXq }, 0 }, |
bf890a93 | 10234 | { "movlhps", { XM, EXq }, 0 }, |
9e30b8e0 | 10235 | }, |
18897deb JB |
10236 | { |
10237 | /* MOD_0F16_PREFIX_2 */ | |
10238 | { "movhpX", { XM, EXq }, 0 }, | |
10239 | }, | |
9e30b8e0 L |
10240 | { |
10241 | /* MOD_0F17 */ | |
507bd325 | 10242 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10243 | }, |
10244 | { | |
10245 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 10246 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
10247 | }, |
10248 | { | |
10249 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 10250 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
10251 | }, |
10252 | { | |
10253 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 10254 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
10255 | }, |
10256 | { | |
10257 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 10258 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 10259 | }, |
d7189fa5 RM |
10260 | { |
10261 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 10262 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10263 | }, |
10264 | { | |
10265 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 10266 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10267 | }, |
10268 | { | |
10269 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 10270 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10271 | }, |
10272 | { | |
10273 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 10274 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 10275 | }, |
7e8b059b L |
10276 | { |
10277 | /* MOD_0F1A_PREFIX_0 */ | |
d276ec69 | 10278 | { "bndldx", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10279 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10280 | }, |
10281 | { | |
10282 | /* MOD_0F1B_PREFIX_0 */ | |
d276ec69 | 10283 | { "bndstx", { Mv_bnd, Gbnd }, 0 }, |
bf890a93 | 10284 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10285 | }, |
10286 | { | |
10287 | /* MOD_0F1B_PREFIX_1 */ | |
d276ec69 | 10288 | { "bndmk", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10289 | { "nopQ", { Ev }, 0 }, |
7e8b059b | 10290 | }, |
c48935d7 IT |
10291 | { |
10292 | /* MOD_0F1C_PREFIX_0 */ | |
f8687e93 | 10293 | { REG_TABLE (REG_0F1C_P_0_MOD_0) }, |
c48935d7 IT |
10294 | { "nopQ", { Ev }, 0 }, |
10295 | }, | |
603555e5 L |
10296 | { |
10297 | /* MOD_0F1E_PREFIX_1 */ | |
10298 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 10299 | { REG_TABLE (REG_0F1E_P_1_MOD_3) }, |
603555e5 | 10300 | }, |
b844680a | 10301 | { |
92fddf8e | 10302 | /* MOD_0F24 */ |
7bb15c6f | 10303 | { Bad_Opcode }, |
bf890a93 | 10304 | { "movL", { Rd, Td }, 0 }, |
b844680a L |
10305 | }, |
10306 | { | |
92fddf8e | 10307 | /* MOD_0F26 */ |
592d1631 | 10308 | { Bad_Opcode }, |
bf890a93 | 10309 | { "movL", { Td, Rd }, 0 }, |
b844680a | 10310 | }, |
75c135a8 L |
10311 | { |
10312 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 10313 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10314 | }, |
10315 | { | |
10316 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 10317 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10318 | }, |
10319 | { | |
10320 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 10321 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10322 | }, |
10323 | { | |
10324 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 10325 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10326 | }, |
10327 | { | |
a5aaedb9 | 10328 | /* MOD_0F50 */ |
592d1631 | 10329 | { Bad_Opcode }, |
507bd325 | 10330 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 10331 | }, |
b844680a | 10332 | { |
1ceb70f8 | 10333 | /* MOD_0F71_REG_2 */ |
592d1631 | 10334 | { Bad_Opcode }, |
bf890a93 | 10335 | { "psrlw", { MS, Ib }, 0 }, |
b844680a L |
10336 | }, |
10337 | { | |
1ceb70f8 | 10338 | /* MOD_0F71_REG_4 */ |
592d1631 | 10339 | { Bad_Opcode }, |
bf890a93 | 10340 | { "psraw", { MS, Ib }, 0 }, |
b844680a L |
10341 | }, |
10342 | { | |
1ceb70f8 | 10343 | /* MOD_0F71_REG_6 */ |
592d1631 | 10344 | { Bad_Opcode }, |
bf890a93 | 10345 | { "psllw", { MS, Ib }, 0 }, |
b844680a L |
10346 | }, |
10347 | { | |
1ceb70f8 | 10348 | /* MOD_0F72_REG_2 */ |
592d1631 | 10349 | { Bad_Opcode }, |
bf890a93 | 10350 | { "psrld", { MS, Ib }, 0 }, |
b844680a L |
10351 | }, |
10352 | { | |
1ceb70f8 | 10353 | /* MOD_0F72_REG_4 */ |
592d1631 | 10354 | { Bad_Opcode }, |
bf890a93 | 10355 | { "psrad", { MS, Ib }, 0 }, |
b844680a L |
10356 | }, |
10357 | { | |
1ceb70f8 | 10358 | /* MOD_0F72_REG_6 */ |
592d1631 | 10359 | { Bad_Opcode }, |
bf890a93 | 10360 | { "pslld", { MS, Ib }, 0 }, |
b844680a L |
10361 | }, |
10362 | { | |
1ceb70f8 | 10363 | /* MOD_0F73_REG_2 */ |
592d1631 | 10364 | { Bad_Opcode }, |
bf890a93 | 10365 | { "psrlq", { MS, Ib }, 0 }, |
b844680a L |
10366 | }, |
10367 | { | |
1ceb70f8 | 10368 | /* MOD_0F73_REG_3 */ |
592d1631 | 10369 | { Bad_Opcode }, |
c0f3af97 L |
10370 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
10371 | }, | |
10372 | { | |
10373 | /* MOD_0F73_REG_6 */ | |
592d1631 | 10374 | { Bad_Opcode }, |
bf890a93 | 10375 | { "psllq", { MS, Ib }, 0 }, |
c0f3af97 L |
10376 | }, |
10377 | { | |
10378 | /* MOD_0F73_REG_7 */ | |
592d1631 | 10379 | { Bad_Opcode }, |
c0f3af97 L |
10380 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
10381 | }, | |
10382 | { | |
10383 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 10384 | { "fxsave", { FXSAVE }, 0 }, |
f8687e93 | 10385 | { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) }, |
c0f3af97 L |
10386 | }, |
10387 | { | |
10388 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 10389 | { "fxrstor", { FXSAVE }, 0 }, |
f8687e93 | 10390 | { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) }, |
c0f3af97 L |
10391 | }, |
10392 | { | |
10393 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 10394 | { "ldmxcsr", { Md }, 0 }, |
f8687e93 | 10395 | { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) }, |
c0f3af97 L |
10396 | }, |
10397 | { | |
10398 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 10399 | { "stmxcsr", { Md }, 0 }, |
f8687e93 | 10400 | { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) }, |
c0f3af97 L |
10401 | }, |
10402 | { | |
10403 | /* MOD_0FAE_REG_4 */ | |
f8687e93 JB |
10404 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) }, |
10405 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) }, | |
c0f3af97 L |
10406 | }, |
10407 | { | |
10408 | /* MOD_0FAE_REG_5 */ | |
f8687e93 JB |
10409 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) }, |
10410 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) }, | |
c0f3af97 L |
10411 | }, |
10412 | { | |
10413 | /* MOD_0FAE_REG_6 */ | |
f8687e93 JB |
10414 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) }, |
10415 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) }, | |
c0f3af97 L |
10416 | }, |
10417 | { | |
10418 | /* MOD_0FAE_REG_7 */ | |
f8687e93 JB |
10419 | { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) }, |
10420 | { RM_TABLE (RM_0FAE_REG_7_MOD_3) }, | |
c0f3af97 L |
10421 | }, |
10422 | { | |
10423 | /* MOD_0FB2 */ | |
bf890a93 | 10424 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10425 | }, |
10426 | { | |
10427 | /* MOD_0FB4 */ | |
bf890a93 | 10428 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10429 | }, |
10430 | { | |
10431 | /* MOD_0FB5 */ | |
bf890a93 | 10432 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 10433 | }, |
a8484f96 L |
10434 | { |
10435 | /* MOD_0FC3 */ | |
f8687e93 | 10436 | { PREFIX_TABLE (PREFIX_0FC3_MOD_0) }, |
a8484f96 | 10437 | }, |
963f3586 IT |
10438 | { |
10439 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 10440 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
10441 | }, |
10442 | { | |
10443 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 10444 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
10445 | }, |
10446 | { | |
10447 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 10448 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 10449 | }, |
c0f3af97 L |
10450 | { |
10451 | /* MOD_0FC7_REG_6 */ | |
f8687e93 JB |
10452 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) }, |
10453 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) } | |
c0f3af97 L |
10454 | }, |
10455 | { | |
10456 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 10457 | { "vmptrst", { Mq }, 0 }, |
f8687e93 | 10458 | { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) } |
c0f3af97 L |
10459 | }, |
10460 | { | |
10461 | /* MOD_0FD7 */ | |
592d1631 | 10462 | { Bad_Opcode }, |
bf890a93 | 10463 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
10464 | }, |
10465 | { | |
10466 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 10467 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
10468 | }, |
10469 | { | |
10470 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 10471 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
10472 | }, |
10473 | { | |
10474 | /* MOD_0F382A_PREFIX_2 */ | |
bf890a93 | 10475 | { "movntdqa", { XM, Mx }, 0 }, |
c0f3af97 | 10476 | }, |
603555e5 L |
10477 | { |
10478 | /* MOD_0F38F5_PREFIX_2 */ | |
10479 | { "wrussK", { M, Gdq }, PREFIX_OPCODE }, | |
10480 | }, | |
10481 | { | |
10482 | /* MOD_0F38F6_PREFIX_0 */ | |
10483 | { "wrssK", { M, Gdq }, PREFIX_OPCODE }, | |
10484 | }, | |
5d79adc4 L |
10485 | { |
10486 | /* MOD_0F38F8_PREFIX_1 */ | |
10487 | { "enqcmds", { Gva, M }, PREFIX_OPCODE }, | |
10488 | }, | |
c0a30a9f L |
10489 | { |
10490 | /* MOD_0F38F8_PREFIX_2 */ | |
10491 | { "movdir64b", { Gva, M }, PREFIX_OPCODE }, | |
10492 | }, | |
5d79adc4 L |
10493 | { |
10494 | /* MOD_0F38F8_PREFIX_3 */ | |
10495 | { "enqcmd", { Gva, M }, PREFIX_OPCODE }, | |
10496 | }, | |
c0a30a9f L |
10497 | { |
10498 | /* MOD_0F38F9_PREFIX_0 */ | |
77ad8092 | 10499 | { "movdiri", { Ev, Gv }, PREFIX_OPCODE }, |
c0a30a9f | 10500 | }, |
c0f3af97 L |
10501 | { |
10502 | /* MOD_62_32BIT */ | |
bf890a93 | 10503 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 10504 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
10505 | }, |
10506 | { | |
10507 | /* MOD_C4_32BIT */ | |
bf890a93 | 10508 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10509 | { VEX_C4_TABLE (VEX_0F) }, |
10510 | }, | |
10511 | { | |
10512 | /* MOD_C5_32BIT */ | |
bf890a93 | 10513 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10514 | { VEX_C5_TABLE (VEX_0F) }, |
10515 | }, | |
10516 | { | |
592a252b L |
10517 | /* MOD_VEX_0F12_PREFIX_0 */ |
10518 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
10519 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 | 10520 | }, |
18897deb JB |
10521 | { |
10522 | /* MOD_VEX_0F12_PREFIX_2 */ | |
10523 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) }, | |
10524 | }, | |
c0f3af97 | 10525 | { |
592a252b L |
10526 | /* MOD_VEX_0F13 */ |
10527 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
10528 | }, |
10529 | { | |
592a252b L |
10530 | /* MOD_VEX_0F16_PREFIX_0 */ |
10531 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
10532 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 | 10533 | }, |
18897deb JB |
10534 | { |
10535 | /* MOD_VEX_0F16_PREFIX_2 */ | |
10536 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) }, | |
10537 | }, | |
c0f3af97 | 10538 | { |
592a252b L |
10539 | /* MOD_VEX_0F17 */ |
10540 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
10541 | }, |
10542 | { | |
592a252b | 10543 | /* MOD_VEX_0F2B */ |
bf926894 | 10544 | { "vmovntpX", { Mx, XM }, PREFIX_OPCODE }, |
c0f3af97 | 10545 | }, |
ab4e4ed5 AF |
10546 | { |
10547 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
10548 | { Bad_Opcode }, | |
10549 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, | |
10550 | }, | |
10551 | { | |
10552 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
10553 | { Bad_Opcode }, | |
10554 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, | |
10555 | }, | |
10556 | { | |
10557 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
10558 | { Bad_Opcode }, | |
10559 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, | |
10560 | }, | |
10561 | { | |
10562 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
10563 | { Bad_Opcode }, | |
10564 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, | |
10565 | }, | |
10566 | { | |
10567 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
10568 | { Bad_Opcode }, | |
10569 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, | |
10570 | }, | |
10571 | { | |
10572 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
10573 | { Bad_Opcode }, | |
10574 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, | |
10575 | }, | |
10576 | { | |
10577 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
10578 | { Bad_Opcode }, | |
10579 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, | |
10580 | }, | |
10581 | { | |
10582 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
10583 | { Bad_Opcode }, | |
10584 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, | |
10585 | }, | |
10586 | { | |
10587 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
10588 | { Bad_Opcode }, | |
10589 | { "knotw", { MaskG, MaskR }, 0 }, | |
10590 | }, | |
10591 | { | |
10592 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
10593 | { Bad_Opcode }, | |
10594 | { "knotq", { MaskG, MaskR }, 0 }, | |
10595 | }, | |
10596 | { | |
10597 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
10598 | { Bad_Opcode }, | |
10599 | { "knotb", { MaskG, MaskR }, 0 }, | |
10600 | }, | |
10601 | { | |
10602 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
10603 | { Bad_Opcode }, | |
10604 | { "knotd", { MaskG, MaskR }, 0 }, | |
10605 | }, | |
10606 | { | |
10607 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
10608 | { Bad_Opcode }, | |
10609 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, | |
10610 | }, | |
10611 | { | |
10612 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
10613 | { Bad_Opcode }, | |
10614 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, | |
10615 | }, | |
10616 | { | |
10617 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
10618 | { Bad_Opcode }, | |
10619 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, | |
10620 | }, | |
10621 | { | |
10622 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
10623 | { Bad_Opcode }, | |
10624 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, | |
10625 | }, | |
10626 | { | |
10627 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
10628 | { Bad_Opcode }, | |
10629 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, | |
10630 | }, | |
10631 | { | |
10632 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
10633 | { Bad_Opcode }, | |
10634 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, | |
10635 | }, | |
10636 | { | |
10637 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
10638 | { Bad_Opcode }, | |
10639 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, | |
10640 | }, | |
10641 | { | |
10642 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
10643 | { Bad_Opcode }, | |
10644 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, | |
10645 | }, | |
10646 | { | |
10647 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
10648 | { Bad_Opcode }, | |
10649 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, | |
10650 | }, | |
10651 | { | |
10652 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
10653 | { Bad_Opcode }, | |
10654 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, | |
10655 | }, | |
10656 | { | |
10657 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
10658 | { Bad_Opcode }, | |
10659 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, | |
10660 | }, | |
10661 | { | |
10662 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
10663 | { Bad_Opcode }, | |
10664 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, | |
10665 | }, | |
10666 | { | |
10667 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
10668 | { Bad_Opcode }, | |
10669 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, | |
10670 | }, | |
10671 | { | |
10672 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
10673 | { Bad_Opcode }, | |
10674 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, | |
10675 | }, | |
10676 | { | |
10677 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
10678 | { Bad_Opcode }, | |
10679 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, | |
10680 | }, | |
10681 | { | |
10682 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
10683 | { Bad_Opcode }, | |
10684 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, | |
10685 | }, | |
10686 | { | |
10687 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
10688 | { Bad_Opcode }, | |
10689 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, | |
10690 | }, | |
10691 | { | |
10692 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
10693 | { Bad_Opcode }, | |
10694 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, | |
10695 | }, | |
10696 | { | |
10697 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
10698 | { Bad_Opcode }, | |
10699 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, | |
10700 | }, | |
c0f3af97 | 10701 | { |
592a252b | 10702 | /* MOD_VEX_0F50 */ |
592d1631 | 10703 | { Bad_Opcode }, |
bf926894 | 10704 | { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
c0f3af97 L |
10705 | }, |
10706 | { | |
592a252b | 10707 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 10708 | { Bad_Opcode }, |
592a252b | 10709 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
10710 | }, |
10711 | { | |
592a252b | 10712 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 10713 | { Bad_Opcode }, |
592a252b | 10714 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
10715 | }, |
10716 | { | |
592a252b | 10717 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 10718 | { Bad_Opcode }, |
592a252b | 10719 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
10720 | }, |
10721 | { | |
592a252b | 10722 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 10723 | { Bad_Opcode }, |
592a252b | 10724 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 10725 | }, |
d8faab4e | 10726 | { |
592a252b | 10727 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 10728 | { Bad_Opcode }, |
592a252b | 10729 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
10730 | }, |
10731 | { | |
592a252b | 10732 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 10733 | { Bad_Opcode }, |
592a252b | 10734 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 10735 | }, |
876d4bfa | 10736 | { |
592a252b | 10737 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 10738 | { Bad_Opcode }, |
592a252b | 10739 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
10740 | }, |
10741 | { | |
592a252b | 10742 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 10743 | { Bad_Opcode }, |
592a252b | 10744 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
10745 | }, |
10746 | { | |
592a252b | 10747 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 10748 | { Bad_Opcode }, |
592a252b | 10749 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
10750 | }, |
10751 | { | |
592a252b | 10752 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 10753 | { Bad_Opcode }, |
592a252b | 10754 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa | 10755 | }, |
ab4e4ed5 AF |
10756 | { |
10757 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
10758 | { "kmovw", { Ew, MaskG }, 0 }, | |
10759 | { Bad_Opcode }, | |
10760 | }, | |
10761 | { | |
10762 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
10763 | { "kmovq", { Eq, MaskG }, 0 }, | |
10764 | { Bad_Opcode }, | |
10765 | }, | |
10766 | { | |
10767 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
10768 | { "kmovb", { Eb, MaskG }, 0 }, | |
10769 | { Bad_Opcode }, | |
10770 | }, | |
10771 | { | |
10772 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
10773 | { "kmovd", { Ed, MaskG }, 0 }, | |
10774 | { Bad_Opcode }, | |
10775 | }, | |
10776 | { | |
10777 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
10778 | { Bad_Opcode }, | |
10779 | { "kmovw", { MaskG, Rdq }, 0 }, | |
10780 | }, | |
10781 | { | |
10782 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
10783 | { Bad_Opcode }, | |
10784 | { "kmovb", { MaskG, Rdq }, 0 }, | |
10785 | }, | |
10786 | { | |
58a211d2 | 10787 | /* MOD_VEX_0F92_P_3_LEN_0 */ |
ab4e4ed5 | 10788 | { Bad_Opcode }, |
58a211d2 | 10789 | { "kmovK", { MaskG, Rdq }, 0 }, |
ab4e4ed5 AF |
10790 | }, |
10791 | { | |
10792 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
10793 | { Bad_Opcode }, | |
10794 | { "kmovw", { Gdq, MaskR }, 0 }, | |
10795 | }, | |
10796 | { | |
10797 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
10798 | { Bad_Opcode }, | |
10799 | { "kmovb", { Gdq, MaskR }, 0 }, | |
10800 | }, | |
10801 | { | |
58a211d2 | 10802 | /* MOD_VEX_0F93_P_3_LEN_0 */ |
ab4e4ed5 | 10803 | { Bad_Opcode }, |
58a211d2 | 10804 | { "kmovK", { Gdq, MaskR }, 0 }, |
ab4e4ed5 AF |
10805 | }, |
10806 | { | |
10807 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
10808 | { Bad_Opcode }, | |
10809 | { "kortestw", { MaskG, MaskR }, 0 }, | |
10810 | }, | |
10811 | { | |
10812 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
10813 | { Bad_Opcode }, | |
10814 | { "kortestq", { MaskG, MaskR }, 0 }, | |
10815 | }, | |
10816 | { | |
10817 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
10818 | { Bad_Opcode }, | |
10819 | { "kortestb", { MaskG, MaskR }, 0 }, | |
10820 | }, | |
10821 | { | |
10822 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
10823 | { Bad_Opcode }, | |
10824 | { "kortestd", { MaskG, MaskR }, 0 }, | |
10825 | }, | |
10826 | { | |
10827 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
10828 | { Bad_Opcode }, | |
10829 | { "ktestw", { MaskG, MaskR }, 0 }, | |
10830 | }, | |
10831 | { | |
10832 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
10833 | { Bad_Opcode }, | |
10834 | { "ktestq", { MaskG, MaskR }, 0 }, | |
10835 | }, | |
10836 | { | |
10837 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
10838 | { Bad_Opcode }, | |
10839 | { "ktestb", { MaskG, MaskR }, 0 }, | |
10840 | }, | |
10841 | { | |
10842 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
10843 | { Bad_Opcode }, | |
10844 | { "ktestd", { MaskG, MaskR }, 0 }, | |
10845 | }, | |
876d4bfa | 10846 | { |
592a252b L |
10847 | /* MOD_VEX_0FAE_REG_2 */ |
10848 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 10849 | }, |
bbedc832 | 10850 | { |
592a252b L |
10851 | /* MOD_VEX_0FAE_REG_3 */ |
10852 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 10853 | }, |
144c41d9 | 10854 | { |
592a252b | 10855 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 10856 | { Bad_Opcode }, |
ec6f095a | 10857 | { "vpmovmskb", { Gdq, XS }, 0 }, |
144c41d9 | 10858 | }, |
1afd85e3 | 10859 | { |
592a252b | 10860 | /* MOD_VEX_0FE7_PREFIX_2 */ |
ec6f095a | 10861 | { "vmovntdq", { Mx, XM }, 0 }, |
1afd85e3 L |
10862 | }, |
10863 | { | |
592a252b | 10864 | /* MOD_VEX_0FF0_PREFIX_3 */ |
ec6f095a | 10865 | { "vlddqu", { XM, M }, 0 }, |
92fddf8e | 10866 | }, |
75c135a8 | 10867 | { |
592a252b L |
10868 | /* MOD_VEX_0F381A_PREFIX_2 */ |
10869 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 10870 | }, |
1afd85e3 | 10871 | { |
592a252b | 10872 | /* MOD_VEX_0F382A_PREFIX_2 */ |
ec6f095a | 10873 | { "vmovntdqa", { XM, Mx }, 0 }, |
1afd85e3 | 10874 | }, |
75c135a8 | 10875 | { |
592a252b L |
10876 | /* MOD_VEX_0F382C_PREFIX_2 */ |
10877 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 10878 | }, |
1afd85e3 | 10879 | { |
592a252b L |
10880 | /* MOD_VEX_0F382D_PREFIX_2 */ |
10881 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
10882 | }, |
10883 | { | |
592a252b L |
10884 | /* MOD_VEX_0F382E_PREFIX_2 */ |
10885 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
10886 | }, |
10887 | { | |
592a252b L |
10888 | /* MOD_VEX_0F382F_PREFIX_2 */ |
10889 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 10890 | }, |
6c30d220 L |
10891 | { |
10892 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
10893 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
10894 | }, | |
10895 | { | |
10896 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
bf890a93 | 10897 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
6c30d220 L |
10898 | }, |
10899 | { | |
10900 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
bf890a93 | 10901 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
6c30d220 | 10902 | }, |
ab4e4ed5 AF |
10903 | { |
10904 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ | |
10905 | { Bad_Opcode }, | |
10906 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, | |
10907 | }, | |
10908 | { | |
10909 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ | |
10910 | { Bad_Opcode }, | |
10911 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, | |
10912 | }, | |
10913 | { | |
10914 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ | |
10915 | { Bad_Opcode }, | |
10916 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, | |
10917 | }, | |
10918 | { | |
10919 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ | |
10920 | { Bad_Opcode }, | |
10921 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, | |
10922 | }, | |
10923 | { | |
10924 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ | |
10925 | { Bad_Opcode }, | |
10926 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, | |
10927 | }, | |
10928 | { | |
10929 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ | |
10930 | { Bad_Opcode }, | |
10931 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, | |
10932 | }, | |
10933 | { | |
10934 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ | |
10935 | { Bad_Opcode }, | |
10936 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, | |
10937 | }, | |
10938 | { | |
10939 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ | |
10940 | { Bad_Opcode }, | |
10941 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, | |
10942 | }, | |
ad692897 L |
10943 | |
10944 | #include "i386-dis-evex-mod.h" | |
b844680a L |
10945 | }; |
10946 | ||
1ceb70f8 | 10947 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
10948 | { |
10949 | /* RM_C6_REG_7 */ | |
bf890a93 | 10950 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
10951 | }, |
10952 | { | |
10953 | /* RM_C7_REG_7 */ | |
376cd056 | 10954 | { "xbeginT", { Skip_MODRM, Jdqw }, 0 }, |
42164a71 | 10955 | }, |
b844680a | 10956 | { |
1ceb70f8 | 10957 | /* RM_0F01_REG_0 */ |
a4e78aa5 | 10958 | { "enclv", { Skip_MODRM }, 0 }, |
bf890a93 IT |
10959 | { "vmcall", { Skip_MODRM }, 0 }, |
10960 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
10961 | { "vmresume", { Skip_MODRM }, 0 }, | |
10962 | { "vmxoff", { Skip_MODRM }, 0 }, | |
be3a8dca | 10963 | { "pconfig", { Skip_MODRM }, 0 }, |
b844680a L |
10964 | }, |
10965 | { | |
1ceb70f8 | 10966 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
10967 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
10968 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
10969 | { "clac", { Skip_MODRM }, 0 }, | |
10970 | { "stac", { Skip_MODRM }, 0 }, | |
2cf200a4 IT |
10971 | { Bad_Opcode }, |
10972 | { Bad_Opcode }, | |
10973 | { Bad_Opcode }, | |
bf890a93 | 10974 | { "encls", { Skip_MODRM }, 0 }, |
b844680a | 10975 | }, |
475a2301 L |
10976 | { |
10977 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
10978 | { "xgetbv", { Skip_MODRM }, 0 }, |
10979 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
10980 | { Bad_Opcode }, |
10981 | { Bad_Opcode }, | |
bf890a93 IT |
10982 | { "vmfunc", { Skip_MODRM }, 0 }, |
10983 | { "xend", { Skip_MODRM }, 0 }, | |
10984 | { "xtest", { Skip_MODRM }, 0 }, | |
10985 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 10986 | }, |
b844680a | 10987 | { |
1ceb70f8 | 10988 | /* RM_0F01_REG_3 */ |
bf890a93 | 10989 | { "vmrun", { Skip_MODRM }, 0 }, |
a847e322 | 10990 | { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) }, |
bf890a93 IT |
10991 | { "vmload", { Skip_MODRM }, 0 }, |
10992 | { "vmsave", { Skip_MODRM }, 0 }, | |
10993 | { "stgi", { Skip_MODRM }, 0 }, | |
10994 | { "clgi", { Skip_MODRM }, 0 }, | |
10995 | { "skinit", { Skip_MODRM }, 0 }, | |
10996 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 10997 | }, |
8eab4136 | 10998 | { |
f8687e93 JB |
10999 | /* RM_0F01_REG_5_MOD_3 */ |
11000 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) }, | |
bb651e8b | 11001 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) }, |
f8687e93 | 11002 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) }, |
8eab4136 L |
11003 | { Bad_Opcode }, |
11004 | { Bad_Opcode }, | |
11005 | { Bad_Opcode }, | |
11006 | { "rdpkru", { Skip_MODRM }, 0 }, | |
11007 | { "wrpkru", { Skip_MODRM }, 0 }, | |
11008 | }, | |
4e7d34a6 | 11009 | { |
f8687e93 | 11010 | /* RM_0F01_REG_7_MOD_3 */ |
bf890a93 IT |
11011 | { "swapgs", { Skip_MODRM }, 0 }, |
11012 | { "rdtscp", { Skip_MODRM }, 0 }, | |
267b8516 JB |
11013 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) }, |
11014 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) }, | |
bf890a93 | 11015 | { "clzero", { Skip_MODRM }, 0 }, |
142861df | 11016 | { "rdpru", { Skip_MODRM }, 0 }, |
b844680a | 11017 | }, |
603555e5 | 11018 | { |
f8687e93 | 11019 | /* RM_0F1E_P_1_MOD_3_REG_7 */ |
603555e5 L |
11020 | { "nopQ", { Ev }, 0 }, |
11021 | { "nopQ", { Ev }, 0 }, | |
11022 | { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, | |
11023 | { "endbr32", { Skip_MODRM }, PREFIX_OPCODE }, | |
11024 | { "nopQ", { Ev }, 0 }, | |
11025 | { "nopQ", { Ev }, 0 }, | |
11026 | { "nopQ", { Ev }, 0 }, | |
11027 | { "nopQ", { Ev }, 0 }, | |
11028 | }, | |
b844680a | 11029 | { |
f8687e93 | 11030 | /* RM_0FAE_REG_6_MOD_3 */ |
bf890a93 | 11031 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 11032 | }, |
bbedc832 | 11033 | { |
f8687e93 | 11034 | /* RM_0FAE_REG_7_MOD_3 */ |
b5cefcca L |
11035 | { "sfence", { Skip_MODRM }, 0 }, |
11036 | ||
144c41d9 | 11037 | }, |
b844680a L |
11038 | }; |
11039 | ||
c608c12e AM |
11040 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
11041 | ||
f16cd0d5 L |
11042 | /* We use the high bit to indicate different name for the same |
11043 | prefix. */ | |
f16cd0d5 | 11044 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
11045 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
11046 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 11047 | #define BND_PREFIX (0xf2 | 0x400) |
04ef582a | 11048 | #define NOTRACK_PREFIX (0x3e | 0x100) |
f16cd0d5 | 11049 | |
1d67fe3b TT |
11050 | /* Remember if the current op is a jump instruction. */ |
11051 | static bfd_boolean op_is_jump = FALSE; | |
11052 | ||
f16cd0d5 | 11053 | static int |
26ca5450 | 11054 | ckprefix (void) |
252b5132 | 11055 | { |
f16cd0d5 | 11056 | int newrex, i, length; |
52b15da3 | 11057 | rex = 0; |
252b5132 | 11058 | prefixes = 0; |
7d421014 | 11059 | used_prefixes = 0; |
52b15da3 | 11060 | rex_used = 0; |
f16cd0d5 L |
11061 | last_lock_prefix = -1; |
11062 | last_repz_prefix = -1; | |
11063 | last_repnz_prefix = -1; | |
11064 | last_data_prefix = -1; | |
11065 | last_addr_prefix = -1; | |
11066 | last_rex_prefix = -1; | |
11067 | last_seg_prefix = -1; | |
d9949a36 | 11068 | fwait_prefix = -1; |
285ca992 | 11069 | active_seg_prefix = 0; |
f310f33d L |
11070 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
11071 | all_prefixes[i] = 0; | |
11072 | i = 0; | |
f16cd0d5 L |
11073 | length = 0; |
11074 | /* The maximum instruction length is 15bytes. */ | |
11075 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
11076 | { |
11077 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 11078 | newrex = 0; |
252b5132 RH |
11079 | switch (*codep) |
11080 | { | |
52b15da3 JH |
11081 | /* REX prefixes family. */ |
11082 | case 0x40: | |
11083 | case 0x41: | |
11084 | case 0x42: | |
11085 | case 0x43: | |
11086 | case 0x44: | |
11087 | case 0x45: | |
11088 | case 0x46: | |
11089 | case 0x47: | |
11090 | case 0x48: | |
11091 | case 0x49: | |
11092 | case 0x4a: | |
11093 | case 0x4b: | |
11094 | case 0x4c: | |
11095 | case 0x4d: | |
11096 | case 0x4e: | |
11097 | case 0x4f: | |
f16cd0d5 L |
11098 | if (address_mode == mode_64bit) |
11099 | newrex = *codep; | |
11100 | else | |
11101 | return 1; | |
11102 | last_rex_prefix = i; | |
52b15da3 | 11103 | break; |
252b5132 RH |
11104 | case 0xf3: |
11105 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 11106 | last_repz_prefix = i; |
252b5132 RH |
11107 | break; |
11108 | case 0xf2: | |
11109 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 11110 | last_repnz_prefix = i; |
252b5132 RH |
11111 | break; |
11112 | case 0xf0: | |
11113 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 11114 | last_lock_prefix = i; |
252b5132 RH |
11115 | break; |
11116 | case 0x2e: | |
11117 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 11118 | last_seg_prefix = i; |
285ca992 | 11119 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
11120 | break; |
11121 | case 0x36: | |
11122 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 11123 | last_seg_prefix = i; |
285ca992 | 11124 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
11125 | break; |
11126 | case 0x3e: | |
11127 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 11128 | last_seg_prefix = i; |
285ca992 | 11129 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
11130 | break; |
11131 | case 0x26: | |
11132 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 11133 | last_seg_prefix = i; |
285ca992 | 11134 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
11135 | break; |
11136 | case 0x64: | |
11137 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 11138 | last_seg_prefix = i; |
285ca992 | 11139 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
11140 | break; |
11141 | case 0x65: | |
11142 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 11143 | last_seg_prefix = i; |
285ca992 | 11144 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
11145 | break; |
11146 | case 0x66: | |
11147 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 11148 | last_data_prefix = i; |
252b5132 RH |
11149 | break; |
11150 | case 0x67: | |
11151 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 11152 | last_addr_prefix = i; |
252b5132 | 11153 | break; |
5076851f | 11154 | case FWAIT_OPCODE: |
252b5132 RH |
11155 | /* fwait is really an instruction. If there are prefixes |
11156 | before the fwait, they belong to the fwait, *not* to the | |
11157 | following instruction. */ | |
d9949a36 | 11158 | fwait_prefix = i; |
3e7d61b2 | 11159 | if (prefixes || rex) |
252b5132 RH |
11160 | { |
11161 | prefixes |= PREFIX_FWAIT; | |
11162 | codep++; | |
6c067bbb RM |
11163 | /* This ensures that the previous REX prefixes are noticed |
11164 | as unused prefixes, as in the return case below. */ | |
11165 | rex_used = rex; | |
f16cd0d5 | 11166 | return 1; |
252b5132 RH |
11167 | } |
11168 | prefixes = PREFIX_FWAIT; | |
11169 | break; | |
11170 | default: | |
f16cd0d5 | 11171 | return 1; |
252b5132 | 11172 | } |
52b15da3 JH |
11173 | /* Rex is ignored when followed by another prefix. */ |
11174 | if (rex) | |
11175 | { | |
3e7d61b2 | 11176 | rex_used = rex; |
f16cd0d5 | 11177 | return 1; |
52b15da3 | 11178 | } |
f16cd0d5 | 11179 | if (*codep != FWAIT_OPCODE) |
4e9ac44a | 11180 | all_prefixes[i++] = *codep; |
52b15da3 | 11181 | rex = newrex; |
252b5132 | 11182 | codep++; |
f16cd0d5 L |
11183 | length++; |
11184 | } | |
11185 | return 0; | |
11186 | } | |
11187 | ||
7d421014 ILT |
11188 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
11189 | prefix byte. */ | |
11190 | ||
11191 | static const char * | |
26ca5450 | 11192 | prefix_name (int pref, int sizeflag) |
7d421014 | 11193 | { |
0003779b L |
11194 | static const char *rexes [16] = |
11195 | { | |
11196 | "rex", /* 0x40 */ | |
11197 | "rex.B", /* 0x41 */ | |
11198 | "rex.X", /* 0x42 */ | |
11199 | "rex.XB", /* 0x43 */ | |
11200 | "rex.R", /* 0x44 */ | |
11201 | "rex.RB", /* 0x45 */ | |
11202 | "rex.RX", /* 0x46 */ | |
11203 | "rex.RXB", /* 0x47 */ | |
11204 | "rex.W", /* 0x48 */ | |
11205 | "rex.WB", /* 0x49 */ | |
11206 | "rex.WX", /* 0x4a */ | |
11207 | "rex.WXB", /* 0x4b */ | |
11208 | "rex.WR", /* 0x4c */ | |
11209 | "rex.WRB", /* 0x4d */ | |
11210 | "rex.WRX", /* 0x4e */ | |
11211 | "rex.WRXB", /* 0x4f */ | |
11212 | }; | |
11213 | ||
7d421014 ILT |
11214 | switch (pref) |
11215 | { | |
52b15da3 JH |
11216 | /* REX prefixes family. */ |
11217 | case 0x40: | |
52b15da3 | 11218 | case 0x41: |
52b15da3 | 11219 | case 0x42: |
52b15da3 | 11220 | case 0x43: |
52b15da3 | 11221 | case 0x44: |
52b15da3 | 11222 | case 0x45: |
52b15da3 | 11223 | case 0x46: |
52b15da3 | 11224 | case 0x47: |
52b15da3 | 11225 | case 0x48: |
52b15da3 | 11226 | case 0x49: |
52b15da3 | 11227 | case 0x4a: |
52b15da3 | 11228 | case 0x4b: |
52b15da3 | 11229 | case 0x4c: |
52b15da3 | 11230 | case 0x4d: |
52b15da3 | 11231 | case 0x4e: |
52b15da3 | 11232 | case 0x4f: |
0003779b | 11233 | return rexes [pref - 0x40]; |
7d421014 ILT |
11234 | case 0xf3: |
11235 | return "repz"; | |
11236 | case 0xf2: | |
11237 | return "repnz"; | |
11238 | case 0xf0: | |
11239 | return "lock"; | |
11240 | case 0x2e: | |
11241 | return "cs"; | |
11242 | case 0x36: | |
11243 | return "ss"; | |
11244 | case 0x3e: | |
11245 | return "ds"; | |
11246 | case 0x26: | |
11247 | return "es"; | |
11248 | case 0x64: | |
11249 | return "fs"; | |
11250 | case 0x65: | |
11251 | return "gs"; | |
11252 | case 0x66: | |
11253 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
11254 | case 0x67: | |
cb712a9e | 11255 | if (address_mode == mode_64bit) |
db6eb5be | 11256 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 11257 | else |
2888cb7a | 11258 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
11259 | case FWAIT_OPCODE: |
11260 | return "fwait"; | |
f16cd0d5 L |
11261 | case REP_PREFIX: |
11262 | return "rep"; | |
42164a71 L |
11263 | case XACQUIRE_PREFIX: |
11264 | return "xacquire"; | |
11265 | case XRELEASE_PREFIX: | |
11266 | return "xrelease"; | |
7e8b059b L |
11267 | case BND_PREFIX: |
11268 | return "bnd"; | |
04ef582a L |
11269 | case NOTRACK_PREFIX: |
11270 | return "notrack"; | |
7d421014 ILT |
11271 | default: |
11272 | return NULL; | |
11273 | } | |
11274 | } | |
11275 | ||
ce518a5f L |
11276 | static char op_out[MAX_OPERANDS][100]; |
11277 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 11278 | static int two_source_ops; |
ce518a5f L |
11279 | static bfd_vma op_address[MAX_OPERANDS]; |
11280 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 11281 | static bfd_vma start_pc; |
ce518a5f | 11282 | |
252b5132 RH |
11283 | /* |
11284 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
11285 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
11286 | * section of the "Virtual 8086 Mode" chapter.) | |
11287 | * 'pc' should be the address of this instruction, it will | |
11288 | * be used to print the target address if this is a relative jump or call | |
11289 | * The function returns the length of this instruction in bytes. | |
11290 | */ | |
11291 | ||
252b5132 | 11292 | static char intel_syntax; |
9d141669 | 11293 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
11294 | static char open_char; |
11295 | static char close_char; | |
11296 | static char separator_char; | |
11297 | static char scale_char; | |
11298 | ||
5db04b09 L |
11299 | enum x86_64_isa |
11300 | { | |
d835a58b | 11301 | amd64 = 1, |
5db04b09 L |
11302 | intel64 |
11303 | }; | |
11304 | ||
11305 | static enum x86_64_isa isa64; | |
11306 | ||
e396998b AM |
11307 | /* Here for backwards compatibility. When gdb stops using |
11308 | print_insn_i386_att and print_insn_i386_intel these functions can | |
11309 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 11310 | int |
26ca5450 | 11311 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11312 | { |
11313 | intel_syntax = 0; | |
e396998b AM |
11314 | |
11315 | return print_insn (pc, info); | |
252b5132 RH |
11316 | } |
11317 | ||
11318 | int | |
26ca5450 | 11319 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11320 | { |
11321 | intel_syntax = 1; | |
e396998b AM |
11322 | |
11323 | return print_insn (pc, info); | |
252b5132 RH |
11324 | } |
11325 | ||
e396998b | 11326 | int |
26ca5450 | 11327 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
11328 | { |
11329 | intel_syntax = -1; | |
11330 | ||
11331 | return print_insn (pc, info); | |
11332 | } | |
11333 | ||
f59a29b9 L |
11334 | void |
11335 | print_i386_disassembler_options (FILE *stream) | |
11336 | { | |
11337 | fprintf (stream, _("\n\ | |
11338 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
11339 | with the -M switch (multiple options should be separated by commas):\n")); | |
11340 | ||
11341 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
11342 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
11343 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
11344 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
11345 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
11346 | fprintf (stream, _(" att-mnemonic\n" |
11347 | " Display instruction in AT&T mnemonic\n")); | |
11348 | fprintf (stream, _(" intel-mnemonic\n" | |
11349 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
11350 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
11351 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
11352 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
11353 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
11354 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
11355 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
11356 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
11357 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
11358 | } |
11359 | ||
592d1631 | 11360 | /* Bad opcode. */ |
bf890a93 | 11361 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 11362 | |
b844680a L |
11363 | /* Get a pointer to struct dis386 with a valid name. */ |
11364 | ||
11365 | static const struct dis386 * | |
8bb15339 | 11366 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 11367 | { |
91d6fa6a | 11368 | int vindex, vex_table_index; |
b844680a L |
11369 | |
11370 | if (dp->name != NULL) | |
11371 | return dp; | |
11372 | ||
11373 | switch (dp->op[0].bytemode) | |
11374 | { | |
1ceb70f8 L |
11375 | case USE_REG_TABLE: |
11376 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
11377 | break; | |
11378 | ||
11379 | case USE_MOD_TABLE: | |
91d6fa6a NC |
11380 | vindex = modrm.mod == 0x3 ? 1 : 0; |
11381 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
11382 | break; |
11383 | ||
11384 | case USE_RM_TABLE: | |
11385 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
11386 | break; |
11387 | ||
4e7d34a6 | 11388 | case USE_PREFIX_TABLE: |
c0f3af97 | 11389 | if (need_vex) |
b844680a | 11390 | { |
c0f3af97 L |
11391 | /* The prefix in VEX is implicit. */ |
11392 | switch (vex.prefix) | |
11393 | { | |
11394 | case 0: | |
91d6fa6a | 11395 | vindex = 0; |
c0f3af97 L |
11396 | break; |
11397 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 11398 | vindex = 1; |
c0f3af97 L |
11399 | break; |
11400 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 11401 | vindex = 2; |
c0f3af97 L |
11402 | break; |
11403 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 11404 | vindex = 3; |
c0f3af97 L |
11405 | break; |
11406 | default: | |
11407 | abort (); | |
11408 | break; | |
11409 | } | |
b844680a | 11410 | } |
7bb15c6f | 11411 | else |
b844680a | 11412 | { |
285ca992 L |
11413 | int last_prefix = -1; |
11414 | int prefix = 0; | |
91d6fa6a | 11415 | vindex = 0; |
285ca992 L |
11416 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
11417 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
11418 | last one wins. */ | |
11419 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 11420 | { |
285ca992 | 11421 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 11422 | { |
285ca992 L |
11423 | vindex = 1; |
11424 | prefix = PREFIX_REPZ; | |
11425 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
11426 | } |
11427 | else | |
b844680a | 11428 | { |
285ca992 L |
11429 | vindex = 3; |
11430 | prefix = PREFIX_REPNZ; | |
11431 | last_prefix = last_repnz_prefix; | |
b844680a | 11432 | } |
285ca992 | 11433 | |
507bd325 L |
11434 | /* Check if prefix should be ignored. */ |
11435 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
11436 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
11437 | & prefix) != 0) | |
285ca992 L |
11438 | vindex = 0; |
11439 | } | |
11440 | ||
11441 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
11442 | { | |
11443 | vindex = 2; | |
11444 | prefix = PREFIX_DATA; | |
11445 | last_prefix = last_data_prefix; | |
11446 | } | |
11447 | ||
11448 | if (vindex != 0) | |
11449 | { | |
11450 | used_prefixes |= prefix; | |
11451 | all_prefixes[last_prefix] = 0; | |
b844680a L |
11452 | } |
11453 | } | |
91d6fa6a | 11454 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
11455 | break; |
11456 | ||
4e7d34a6 | 11457 | case USE_X86_64_TABLE: |
91d6fa6a NC |
11458 | vindex = address_mode == mode_64bit ? 1 : 0; |
11459 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
11460 | break; |
11461 | ||
4e7d34a6 | 11462 | case USE_3BYTE_TABLE: |
8bb15339 | 11463 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
11464 | vindex = *codep++; |
11465 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 11466 | end_codep = codep; |
8bb15339 L |
11467 | modrm.mod = (*codep >> 6) & 3; |
11468 | modrm.reg = (*codep >> 3) & 7; | |
11469 | modrm.rm = *codep & 7; | |
11470 | break; | |
11471 | ||
c0f3af97 L |
11472 | case USE_VEX_LEN_TABLE: |
11473 | if (!need_vex) | |
11474 | abort (); | |
11475 | ||
11476 | switch (vex.length) | |
11477 | { | |
11478 | case 128: | |
91d6fa6a | 11479 | vindex = 0; |
c0f3af97 L |
11480 | break; |
11481 | case 256: | |
91d6fa6a | 11482 | vindex = 1; |
c0f3af97 L |
11483 | break; |
11484 | default: | |
11485 | abort (); | |
11486 | break; | |
11487 | } | |
11488 | ||
91d6fa6a | 11489 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
11490 | break; |
11491 | ||
04e2a182 L |
11492 | case USE_EVEX_LEN_TABLE: |
11493 | if (!vex.evex) | |
11494 | abort (); | |
11495 | ||
11496 | switch (vex.length) | |
11497 | { | |
11498 | case 128: | |
11499 | vindex = 0; | |
11500 | break; | |
11501 | case 256: | |
11502 | vindex = 1; | |
11503 | break; | |
11504 | case 512: | |
11505 | vindex = 2; | |
11506 | break; | |
11507 | default: | |
11508 | abort (); | |
11509 | break; | |
11510 | } | |
11511 | ||
11512 | dp = &evex_len_table[dp->op[1].bytemode][vindex]; | |
11513 | break; | |
11514 | ||
f88c9eb0 SP |
11515 | case USE_XOP_8F_TABLE: |
11516 | FETCH_DATA (info, codep + 3); | |
f88c9eb0 SP |
11517 | rex = ~(*codep >> 5) & 0x7; |
11518 | ||
11519 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
11520 | switch ((*codep & 0x1f)) | |
11521 | { | |
11522 | default: | |
f07af43e L |
11523 | dp = &bad_opcode; |
11524 | return dp; | |
5dd85c99 SP |
11525 | case 0x8: |
11526 | vex_table_index = XOP_08; | |
11527 | break; | |
f88c9eb0 SP |
11528 | case 0x9: |
11529 | vex_table_index = XOP_09; | |
11530 | break; | |
11531 | case 0xa: | |
11532 | vex_table_index = XOP_0A; | |
11533 | break; | |
11534 | } | |
11535 | codep++; | |
11536 | vex.w = *codep & 0x80; | |
11537 | if (vex.w && address_mode == mode_64bit) | |
11538 | rex |= REX_W; | |
11539 | ||
11540 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
abfcb414 | 11541 | if (address_mode != mode_64bit) |
f07af43e | 11542 | { |
abfcb414 AP |
11543 | /* In 16/32-bit mode REX_B is silently ignored. */ |
11544 | rex &= ~REX_B; | |
f07af43e | 11545 | } |
f88c9eb0 SP |
11546 | |
11547 | vex.length = (*codep & 0x4) ? 256 : 128; | |
11548 | switch ((*codep & 0x3)) | |
11549 | { | |
11550 | case 0: | |
f88c9eb0 SP |
11551 | break; |
11552 | case 1: | |
11553 | vex.prefix = DATA_PREFIX_OPCODE; | |
11554 | break; | |
11555 | case 2: | |
11556 | vex.prefix = REPE_PREFIX_OPCODE; | |
11557 | break; | |
11558 | case 3: | |
11559 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11560 | break; | |
11561 | } | |
11562 | need_vex = 1; | |
11563 | need_vex_reg = 1; | |
11564 | codep++; | |
91d6fa6a NC |
11565 | vindex = *codep++; |
11566 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 11567 | |
285ca992 | 11568 | end_codep = codep; |
c48244a5 SP |
11569 | FETCH_DATA (info, codep + 1); |
11570 | modrm.mod = (*codep >> 6) & 3; | |
11571 | modrm.reg = (*codep >> 3) & 7; | |
11572 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
11573 | break; |
11574 | ||
c0f3af97 | 11575 | case USE_VEX_C4_TABLE: |
43234a1e | 11576 | /* VEX prefix. */ |
c0f3af97 | 11577 | FETCH_DATA (info, codep + 3); |
c0f3af97 L |
11578 | rex = ~(*codep >> 5) & 0x7; |
11579 | switch ((*codep & 0x1f)) | |
11580 | { | |
11581 | default: | |
f07af43e L |
11582 | dp = &bad_opcode; |
11583 | return dp; | |
c0f3af97 | 11584 | case 0x1: |
f88c9eb0 | 11585 | vex_table_index = VEX_0F; |
c0f3af97 L |
11586 | break; |
11587 | case 0x2: | |
f88c9eb0 | 11588 | vex_table_index = VEX_0F38; |
c0f3af97 L |
11589 | break; |
11590 | case 0x3: | |
f88c9eb0 | 11591 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
11592 | break; |
11593 | } | |
11594 | codep++; | |
11595 | vex.w = *codep & 0x80; | |
9889cbb1 | 11596 | if (address_mode == mode_64bit) |
f07af43e | 11597 | { |
9889cbb1 L |
11598 | if (vex.w) |
11599 | rex |= REX_W; | |
9889cbb1 L |
11600 | } |
11601 | else | |
11602 | { | |
11603 | /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit | |
11604 | is ignored, other REX bits are 0 and the highest bit in | |
5f847646 | 11605 | VEX.vvvv is also ignored (but we mustn't clear it here). */ |
9889cbb1 | 11606 | rex = 0; |
f07af43e | 11607 | } |
5f847646 | 11608 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
11609 | vex.length = (*codep & 0x4) ? 256 : 128; |
11610 | switch ((*codep & 0x3)) | |
11611 | { | |
11612 | case 0: | |
c0f3af97 L |
11613 | break; |
11614 | case 1: | |
11615 | vex.prefix = DATA_PREFIX_OPCODE; | |
11616 | break; | |
11617 | case 2: | |
11618 | vex.prefix = REPE_PREFIX_OPCODE; | |
11619 | break; | |
11620 | case 3: | |
11621 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11622 | break; | |
11623 | } | |
11624 | need_vex = 1; | |
11625 | need_vex_reg = 1; | |
11626 | codep++; | |
91d6fa6a NC |
11627 | vindex = *codep++; |
11628 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 11629 | end_codep = codep; |
53c4d625 JB |
11630 | /* There is no MODRM byte for VEX0F 77. */ |
11631 | if (vex_table_index != VEX_0F || vindex != 0x77) | |
c0f3af97 L |
11632 | { |
11633 | FETCH_DATA (info, codep + 1); | |
11634 | modrm.mod = (*codep >> 6) & 3; | |
11635 | modrm.reg = (*codep >> 3) & 7; | |
11636 | modrm.rm = *codep & 7; | |
11637 | } | |
11638 | break; | |
11639 | ||
11640 | case USE_VEX_C5_TABLE: | |
43234a1e | 11641 | /* VEX prefix. */ |
c0f3af97 | 11642 | FETCH_DATA (info, codep + 2); |
c0f3af97 L |
11643 | rex = (*codep & 0x80) ? 0 : REX_R; |
11644 | ||
9889cbb1 L |
11645 | /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in |
11646 | VEX.vvvv is 1. */ | |
c0f3af97 | 11647 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
11648 | vex.length = (*codep & 0x4) ? 256 : 128; |
11649 | switch ((*codep & 0x3)) | |
11650 | { | |
11651 | case 0: | |
c0f3af97 L |
11652 | break; |
11653 | case 1: | |
11654 | vex.prefix = DATA_PREFIX_OPCODE; | |
11655 | break; | |
11656 | case 2: | |
11657 | vex.prefix = REPE_PREFIX_OPCODE; | |
11658 | break; | |
11659 | case 3: | |
11660 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11661 | break; | |
11662 | } | |
11663 | need_vex = 1; | |
11664 | need_vex_reg = 1; | |
11665 | codep++; | |
91d6fa6a NC |
11666 | vindex = *codep++; |
11667 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 11668 | end_codep = codep; |
53c4d625 JB |
11669 | /* There is no MODRM byte for VEX 77. */ |
11670 | if (vindex != 0x77) | |
c0f3af97 L |
11671 | { |
11672 | FETCH_DATA (info, codep + 1); | |
11673 | modrm.mod = (*codep >> 6) & 3; | |
11674 | modrm.reg = (*codep >> 3) & 7; | |
11675 | modrm.rm = *codep & 7; | |
11676 | } | |
11677 | break; | |
11678 | ||
9e30b8e0 L |
11679 | case USE_VEX_W_TABLE: |
11680 | if (!need_vex) | |
11681 | abort (); | |
11682 | ||
11683 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
11684 | break; | |
11685 | ||
43234a1e L |
11686 | case USE_EVEX_TABLE: |
11687 | two_source_ops = 0; | |
11688 | /* EVEX prefix. */ | |
11689 | vex.evex = 1; | |
11690 | FETCH_DATA (info, codep + 4); | |
43234a1e L |
11691 | /* The first byte after 0x62. */ |
11692 | rex = ~(*codep >> 5) & 0x7; | |
11693 | vex.r = *codep & 0x10; | |
11694 | switch ((*codep & 0xf)) | |
11695 | { | |
11696 | default: | |
11697 | return &bad_opcode; | |
11698 | case 0x1: | |
11699 | vex_table_index = EVEX_0F; | |
11700 | break; | |
11701 | case 0x2: | |
11702 | vex_table_index = EVEX_0F38; | |
11703 | break; | |
11704 | case 0x3: | |
11705 | vex_table_index = EVEX_0F3A; | |
11706 | break; | |
11707 | } | |
11708 | ||
11709 | /* The second byte after 0x62. */ | |
11710 | codep++; | |
11711 | vex.w = *codep & 0x80; | |
11712 | if (vex.w && address_mode == mode_64bit) | |
11713 | rex |= REX_W; | |
11714 | ||
11715 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
43234a1e L |
11716 | |
11717 | /* The U bit. */ | |
11718 | if (!(*codep & 0x4)) | |
11719 | return &bad_opcode; | |
11720 | ||
11721 | switch ((*codep & 0x3)) | |
11722 | { | |
11723 | case 0: | |
43234a1e L |
11724 | break; |
11725 | case 1: | |
11726 | vex.prefix = DATA_PREFIX_OPCODE; | |
11727 | break; | |
11728 | case 2: | |
11729 | vex.prefix = REPE_PREFIX_OPCODE; | |
11730 | break; | |
11731 | case 3: | |
11732 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11733 | break; | |
11734 | } | |
11735 | ||
11736 | /* The third byte after 0x62. */ | |
11737 | codep++; | |
11738 | ||
11739 | /* Remember the static rounding bits. */ | |
11740 | vex.ll = (*codep >> 5) & 3; | |
11741 | vex.b = (*codep & 0x10) != 0; | |
11742 | ||
11743 | vex.v = *codep & 0x8; | |
11744 | vex.mask_register_specifier = *codep & 0x7; | |
11745 | vex.zeroing = *codep & 0x80; | |
11746 | ||
5f847646 JB |
11747 | if (address_mode != mode_64bit) |
11748 | { | |
11749 | /* In 16/32-bit mode silently ignore following bits. */ | |
11750 | rex &= ~REX_B; | |
11751 | vex.r = 1; | |
11752 | vex.v = 1; | |
11753 | } | |
11754 | ||
43234a1e L |
11755 | need_vex = 1; |
11756 | need_vex_reg = 1; | |
11757 | codep++; | |
11758 | vindex = *codep++; | |
11759 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 11760 | end_codep = codep; |
43234a1e L |
11761 | FETCH_DATA (info, codep + 1); |
11762 | modrm.mod = (*codep >> 6) & 3; | |
11763 | modrm.reg = (*codep >> 3) & 7; | |
11764 | modrm.rm = *codep & 7; | |
11765 | ||
11766 | /* Set vector length. */ | |
11767 | if (modrm.mod == 3 && vex.b) | |
11768 | vex.length = 512; | |
11769 | else | |
11770 | { | |
11771 | switch (vex.ll) | |
11772 | { | |
11773 | case 0x0: | |
11774 | vex.length = 128; | |
11775 | break; | |
11776 | case 0x1: | |
11777 | vex.length = 256; | |
11778 | break; | |
11779 | case 0x2: | |
11780 | vex.length = 512; | |
11781 | break; | |
11782 | default: | |
11783 | return &bad_opcode; | |
11784 | } | |
11785 | } | |
11786 | break; | |
11787 | ||
592d1631 L |
11788 | case 0: |
11789 | dp = &bad_opcode; | |
11790 | break; | |
11791 | ||
b844680a | 11792 | default: |
d34b5006 | 11793 | abort (); |
b844680a L |
11794 | } |
11795 | ||
11796 | if (dp->name != NULL) | |
11797 | return dp; | |
11798 | else | |
8bb15339 | 11799 | return get_valid_dis386 (dp, info); |
b844680a L |
11800 | } |
11801 | ||
dfc8cf43 | 11802 | static void |
55cf16e1 | 11803 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
11804 | { |
11805 | /* If modrm.mod == 3, operand must be register. */ | |
11806 | if (need_modrm | |
55cf16e1 | 11807 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
11808 | && modrm.mod != 3 |
11809 | && modrm.rm == 4) | |
11810 | { | |
11811 | FETCH_DATA (info, codep + 2); | |
11812 | sib.index = (codep [1] >> 3) & 7; | |
11813 | sib.scale = (codep [1] >> 6) & 3; | |
11814 | sib.base = codep [1] & 7; | |
11815 | } | |
11816 | } | |
11817 | ||
e396998b | 11818 | static int |
26ca5450 | 11819 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 11820 | { |
2da11e11 | 11821 | const struct dis386 *dp; |
252b5132 | 11822 | int i; |
ce518a5f | 11823 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 11824 | int needcomma; |
df18fdba | 11825 | int sizeflag, orig_sizeflag; |
e396998b | 11826 | const char *p; |
252b5132 | 11827 | struct dis_private priv; |
f16cd0d5 | 11828 | int prefix_length; |
252b5132 | 11829 | |
d7921315 L |
11830 | priv.orig_sizeflag = AFLAG | DFLAG; |
11831 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 11832 | address_mode = mode_32bit; |
2da11e11 | 11833 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
11834 | { |
11835 | address_mode = mode_16bit; | |
11836 | priv.orig_sizeflag = 0; | |
11837 | } | |
2da11e11 | 11838 | else |
d7921315 L |
11839 | address_mode = mode_64bit; |
11840 | ||
11841 | if (intel_syntax == (char) -1) | |
11842 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
11843 | |
11844 | for (p = info->disassembler_options; p != NULL; ) | |
11845 | { | |
5db04b09 L |
11846 | if (CONST_STRNEQ (p, "amd64")) |
11847 | isa64 = amd64; | |
11848 | else if (CONST_STRNEQ (p, "intel64")) | |
11849 | isa64 = intel64; | |
11850 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 11851 | { |
cb712a9e | 11852 | address_mode = mode_64bit; |
2a1bb84c | 11853 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 11854 | } |
0112cd26 | 11855 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 11856 | { |
cb712a9e | 11857 | address_mode = mode_32bit; |
2a1bb84c | 11858 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 11859 | } |
0112cd26 | 11860 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 11861 | { |
cb712a9e | 11862 | address_mode = mode_16bit; |
2a1bb84c | 11863 | priv.orig_sizeflag &= ~(AFLAG | DFLAG); |
e396998b | 11864 | } |
0112cd26 | 11865 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
11866 | { |
11867 | intel_syntax = 1; | |
9d141669 L |
11868 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
11869 | intel_mnemonic = 1; | |
e396998b | 11870 | } |
0112cd26 | 11871 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
11872 | { |
11873 | intel_syntax = 0; | |
9d141669 L |
11874 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
11875 | intel_mnemonic = 0; | |
e396998b | 11876 | } |
0112cd26 | 11877 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 11878 | { |
f59a29b9 L |
11879 | if (address_mode == mode_64bit) |
11880 | { | |
11881 | if (p[4] == '3' && p[5] == '2') | |
11882 | priv.orig_sizeflag &= ~AFLAG; | |
11883 | else if (p[4] == '6' && p[5] == '4') | |
11884 | priv.orig_sizeflag |= AFLAG; | |
11885 | } | |
11886 | else | |
11887 | { | |
11888 | if (p[4] == '1' && p[5] == '6') | |
11889 | priv.orig_sizeflag &= ~AFLAG; | |
11890 | else if (p[4] == '3' && p[5] == '2') | |
11891 | priv.orig_sizeflag |= AFLAG; | |
11892 | } | |
e396998b | 11893 | } |
0112cd26 | 11894 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
11895 | { |
11896 | if (p[4] == '1' && p[5] == '6') | |
11897 | priv.orig_sizeflag &= ~DFLAG; | |
11898 | else if (p[4] == '3' && p[5] == '2') | |
11899 | priv.orig_sizeflag |= DFLAG; | |
11900 | } | |
0112cd26 | 11901 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
11902 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
11903 | ||
11904 | p = strchr (p, ','); | |
11905 | if (p != NULL) | |
11906 | p++; | |
11907 | } | |
11908 | ||
c0f92bf9 L |
11909 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
11910 | { | |
11911 | (*info->fprintf_func) (info->stream, | |
11912 | _("64-bit address is disabled")); | |
11913 | return -1; | |
11914 | } | |
11915 | ||
e396998b AM |
11916 | if (intel_syntax) |
11917 | { | |
11918 | names64 = intel_names64; | |
11919 | names32 = intel_names32; | |
11920 | names16 = intel_names16; | |
11921 | names8 = intel_names8; | |
11922 | names8rex = intel_names8rex; | |
11923 | names_seg = intel_names_seg; | |
b9733481 | 11924 | names_mm = intel_names_mm; |
7e8b059b | 11925 | names_bnd = intel_names_bnd; |
b9733481 L |
11926 | names_xmm = intel_names_xmm; |
11927 | names_ymm = intel_names_ymm; | |
43234a1e | 11928 | names_zmm = intel_names_zmm; |
db51cc60 L |
11929 | index64 = intel_index64; |
11930 | index32 = intel_index32; | |
43234a1e | 11931 | names_mask = intel_names_mask; |
e396998b AM |
11932 | index16 = intel_index16; |
11933 | open_char = '['; | |
11934 | close_char = ']'; | |
11935 | separator_char = '+'; | |
11936 | scale_char = '*'; | |
11937 | } | |
11938 | else | |
11939 | { | |
11940 | names64 = att_names64; | |
11941 | names32 = att_names32; | |
11942 | names16 = att_names16; | |
11943 | names8 = att_names8; | |
11944 | names8rex = att_names8rex; | |
11945 | names_seg = att_names_seg; | |
b9733481 | 11946 | names_mm = att_names_mm; |
7e8b059b | 11947 | names_bnd = att_names_bnd; |
b9733481 L |
11948 | names_xmm = att_names_xmm; |
11949 | names_ymm = att_names_ymm; | |
43234a1e | 11950 | names_zmm = att_names_zmm; |
db51cc60 L |
11951 | index64 = att_index64; |
11952 | index32 = att_index32; | |
43234a1e | 11953 | names_mask = att_names_mask; |
e396998b AM |
11954 | index16 = att_index16; |
11955 | open_char = '('; | |
11956 | close_char = ')'; | |
11957 | separator_char = ','; | |
11958 | scale_char = ','; | |
11959 | } | |
2da11e11 | 11960 | |
4fe53c98 | 11961 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
11962 | puts most long word instructions on a single line. Use 8 bytes |
11963 | for Intel L1OM. */ | |
d7921315 | 11964 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
11965 | info->bytes_per_line = 8; |
11966 | else | |
11967 | info->bytes_per_line = 7; | |
252b5132 | 11968 | |
26ca5450 | 11969 | info->private_data = &priv; |
252b5132 RH |
11970 | priv.max_fetched = priv.the_buffer; |
11971 | priv.insn_start = pc; | |
252b5132 RH |
11972 | |
11973 | obuf[0] = 0; | |
ce518a5f L |
11974 | for (i = 0; i < MAX_OPERANDS; ++i) |
11975 | { | |
11976 | op_out[i][0] = 0; | |
11977 | op_index[i] = -1; | |
11978 | } | |
252b5132 RH |
11979 | |
11980 | the_info = info; | |
11981 | start_pc = pc; | |
e396998b AM |
11982 | start_codep = priv.the_buffer; |
11983 | codep = priv.the_buffer; | |
252b5132 | 11984 | |
8df14d78 | 11985 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 11986 | { |
7d421014 ILT |
11987 | const char *name; |
11988 | ||
5076851f | 11989 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
11990 | means we have an incomplete instruction of some sort. Just |
11991 | print the first byte as a prefix or a .byte pseudo-op. */ | |
11992 | if (codep > priv.the_buffer) | |
5076851f | 11993 | { |
e396998b | 11994 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
11995 | if (name != NULL) |
11996 | (*info->fprintf_func) (info->stream, "%s", name); | |
11997 | else | |
5076851f | 11998 | { |
7d421014 ILT |
11999 | /* Just print the first byte as a .byte instruction. */ |
12000 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 12001 | (unsigned int) priv.the_buffer[0]); |
5076851f | 12002 | } |
5076851f | 12003 | |
7d421014 | 12004 | return 1; |
5076851f ILT |
12005 | } |
12006 | ||
12007 | return -1; | |
12008 | } | |
12009 | ||
52b15da3 | 12010 | obufp = obuf; |
f16cd0d5 L |
12011 | sizeflag = priv.orig_sizeflag; |
12012 | ||
12013 | if (!ckprefix () || rex_used) | |
12014 | { | |
12015 | /* Too many prefixes or unused REX prefixes. */ | |
12016 | for (i = 0; | |
f6dd4781 | 12017 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 12018 | i++) |
de882298 | 12019 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 12020 | i == 0 ? "" : " ", |
f16cd0d5 | 12021 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 12022 | return i; |
f16cd0d5 | 12023 | } |
252b5132 RH |
12024 | |
12025 | insn_codep = codep; | |
12026 | ||
12027 | FETCH_DATA (info, codep + 1); | |
12028 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
12029 | ||
3e7d61b2 | 12030 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 12031 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 12032 | { |
86a80a50 | 12033 | /* Handle prefixes before fwait. */ |
d9949a36 | 12034 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
12035 | i++) |
12036 | (*info->fprintf_func) (info->stream, "%s ", | |
12037 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 12038 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 12039 | return i + 1; |
252b5132 RH |
12040 | } |
12041 | ||
252b5132 RH |
12042 | if (*codep == 0x0f) |
12043 | { | |
eec0f4ca | 12044 | unsigned char threebyte; |
5f40e14d JS |
12045 | |
12046 | codep++; | |
12047 | FETCH_DATA (info, codep + 1); | |
12048 | threebyte = *codep; | |
eec0f4ca | 12049 | dp = &dis386_twobyte[threebyte]; |
252b5132 | 12050 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 12051 | codep++; |
252b5132 RH |
12052 | } |
12053 | else | |
12054 | { | |
6439fc28 | 12055 | dp = &dis386[*codep]; |
252b5132 | 12056 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 12057 | codep++; |
252b5132 | 12058 | } |
246c51aa | 12059 | |
df18fdba L |
12060 | /* Save sizeflag for printing the extra prefixes later before updating |
12061 | it for mnemonic and operand processing. The prefix names depend | |
12062 | only on the address mode. */ | |
12063 | orig_sizeflag = sizeflag; | |
c608c12e | 12064 | if (prefixes & PREFIX_ADDR) |
df18fdba | 12065 | sizeflag ^= AFLAG; |
b844680a | 12066 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 12067 | sizeflag ^= DFLAG; |
3ffd33cf | 12068 | |
285ca992 | 12069 | end_codep = codep; |
8bb15339 | 12070 | if (need_modrm) |
252b5132 RH |
12071 | { |
12072 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
12073 | modrm.mod = (*codep >> 6) & 3; |
12074 | modrm.reg = (*codep >> 3) & 7; | |
12075 | modrm.rm = *codep & 7; | |
252b5132 RH |
12076 | } |
12077 | ||
42d5f9c6 MS |
12078 | need_vex = 0; |
12079 | need_vex_reg = 0; | |
12080 | vex_w_done = 0; | |
caf0678c | 12081 | memset (&vex, 0, sizeof (vex)); |
55b126d4 | 12082 | |
ce518a5f | 12083 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 12084 | { |
55cf16e1 | 12085 | get_sib (info, sizeflag); |
252b5132 RH |
12086 | dofloat (sizeflag); |
12087 | } | |
12088 | else | |
12089 | { | |
8bb15339 | 12090 | dp = get_valid_dis386 (dp, info); |
b844680a | 12091 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 12092 | { |
55cf16e1 | 12093 | get_sib (info, sizeflag); |
ce518a5f L |
12094 | for (i = 0; i < MAX_OPERANDS; ++i) |
12095 | { | |
246c51aa | 12096 | obufp = op_out[i]; |
ce518a5f L |
12097 | op_ad = MAX_OPERANDS - 1 - i; |
12098 | if (dp->op[i].rtn) | |
12099 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
12100 | /* For EVEX instruction after the last operand masking |
12101 | should be printed. */ | |
12102 | if (i == 0 && vex.evex) | |
12103 | { | |
12104 | /* Don't print {%k0}. */ | |
12105 | if (vex.mask_register_specifier) | |
12106 | { | |
12107 | oappend ("{"); | |
12108 | oappend (names_mask[vex.mask_register_specifier]); | |
12109 | oappend ("}"); | |
12110 | } | |
12111 | if (vex.zeroing) | |
12112 | oappend ("{z}"); | |
12113 | } | |
ce518a5f | 12114 | } |
6439fc28 | 12115 | } |
252b5132 RH |
12116 | } |
12117 | ||
1d67fe3b TT |
12118 | /* Clear instruction information. */ |
12119 | if (the_info) | |
12120 | { | |
12121 | the_info->insn_info_valid = 0; | |
12122 | the_info->branch_delay_insns = 0; | |
12123 | the_info->data_size = 0; | |
12124 | the_info->insn_type = dis_noninsn; | |
12125 | the_info->target = 0; | |
12126 | the_info->target2 = 0; | |
12127 | } | |
12128 | ||
12129 | /* Reset jump operation indicator. */ | |
12130 | op_is_jump = FALSE; | |
12131 | ||
12132 | { | |
12133 | int jump_detection = 0; | |
12134 | ||
12135 | /* Extract flags. */ | |
12136 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12137 | { | |
12138 | if ((dp->op[i].rtn == OP_J) | |
12139 | || (dp->op[i].rtn == OP_indirE)) | |
12140 | jump_detection |= 1; | |
12141 | else if ((dp->op[i].rtn == BND_Fixup) | |
12142 | || (!dp->op[i].rtn && !dp->op[i].bytemode)) | |
12143 | jump_detection |= 2; | |
12144 | else if ((dp->op[i].bytemode == cond_jump_mode) | |
12145 | || (dp->op[i].bytemode == loop_jcxz_mode)) | |
12146 | jump_detection |= 4; | |
12147 | } | |
12148 | ||
12149 | /* Determine if this is a jump or branch. */ | |
12150 | if ((jump_detection & 0x3) == 0x3) | |
12151 | { | |
12152 | op_is_jump = TRUE; | |
12153 | if (jump_detection & 0x4) | |
12154 | the_info->insn_type = dis_condbranch; | |
12155 | else | |
12156 | the_info->insn_type = | |
12157 | (dp->name && !strncmp(dp->name, "call", 4)) | |
12158 | ? dis_jsr : dis_branch; | |
12159 | } | |
12160 | } | |
12161 | ||
63c6fc6c L |
12162 | /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which |
12163 | are all 0s in inverted form. */ | |
12164 | if (need_vex && vex.register_specifier != 0) | |
12165 | { | |
12166 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12167 | return end_codep - priv.the_buffer; | |
12168 | } | |
12169 | ||
d869730d | 12170 | /* Check if the REX prefix is used. */ |
73239888 | 12171 | if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0) |
f16cd0d5 L |
12172 | all_prefixes[last_rex_prefix] = 0; |
12173 | ||
5e6718e4 | 12174 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
12175 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
12176 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 12177 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
12178 | all_prefixes[last_seg_prefix] = 0; |
12179 | ||
5e6718e4 | 12180 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
12181 | if ((prefixes & PREFIX_ADDR) != 0 |
12182 | && (used_prefixes & PREFIX_ADDR) != 0) | |
12183 | all_prefixes[last_addr_prefix] = 0; | |
12184 | ||
df18fdba L |
12185 | /* Check if the DATA prefix is used. */ |
12186 | if ((prefixes & PREFIX_DATA) != 0 | |
73239888 JB |
12187 | && (used_prefixes & PREFIX_DATA) != 0 |
12188 | && !need_vex) | |
df18fdba | 12189 | all_prefixes[last_data_prefix] = 0; |
f16cd0d5 | 12190 | |
df18fdba | 12191 | /* Print the extra prefixes. */ |
f16cd0d5 | 12192 | prefix_length = 0; |
f310f33d | 12193 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
12194 | if (all_prefixes[i]) |
12195 | { | |
12196 | const char *name; | |
df18fdba | 12197 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
12198 | if (name == NULL) |
12199 | abort (); | |
12200 | prefix_length += strlen (name) + 1; | |
12201 | (*info->fprintf_func) (info->stream, "%s ", name); | |
12202 | } | |
b844680a | 12203 | |
285ca992 L |
12204 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
12205 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
12206 | used by putop and MMX/SSE operand and may be overriden by the | |
12207 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
12208 | separately. */ | |
3888916d | 12209 | if (dp->prefix_requirement == PREFIX_OPCODE |
bf926894 JB |
12210 | && (((need_vex |
12211 | ? vex.prefix == REPE_PREFIX_OPCODE | |
12212 | || vex.prefix == REPNE_PREFIX_OPCODE | |
12213 | : (prefixes | |
12214 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
285ca992 L |
12215 | && (used_prefixes |
12216 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
bf926894 JB |
12217 | || (((need_vex |
12218 | ? vex.prefix == DATA_PREFIX_OPCODE | |
12219 | : ((prefixes | |
12220 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
12221 | == PREFIX_DATA)) | |
97e6786a JB |
12222 | && (used_prefixes & PREFIX_DATA) == 0)) |
12223 | || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA)))) | |
285ca992 L |
12224 | { |
12225 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12226 | return end_codep - priv.the_buffer; | |
12227 | } | |
12228 | ||
f16cd0d5 L |
12229 | /* Check maximum code length. */ |
12230 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
12231 | { | |
12232 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12233 | return MAX_CODE_LENGTH; | |
12234 | } | |
b844680a | 12235 | |
ea397f5b | 12236 | obufp = mnemonicendp; |
f16cd0d5 | 12237 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
12238 | oappend (" "); |
12239 | oappend (" "); | |
12240 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
12241 | ||
12242 | /* The enter and bound instructions are printed with operands in the same | |
12243 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 12244 | if (intel_syntax || two_source_ops) |
252b5132 | 12245 | { |
185b1163 L |
12246 | bfd_vma riprel; |
12247 | ||
ce518a5f | 12248 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12249 | op_txt[i] = op_out[i]; |
246c51aa | 12250 | |
3a8547d2 JB |
12251 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
12252 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
12253 | { | |
12254 | op_txt[2] = op_out[3]; | |
12255 | op_txt[3] = op_out[2]; | |
12256 | } | |
12257 | ||
ce518a5f L |
12258 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
12259 | { | |
6c067bbb RM |
12260 | op_ad = op_index[i]; |
12261 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
12262 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
12263 | riprel = op_riprel[i]; |
12264 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
12265 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 12266 | } |
252b5132 RH |
12267 | } |
12268 | else | |
12269 | { | |
ce518a5f | 12270 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12271 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
12272 | } |
12273 | ||
ce518a5f L |
12274 | needcomma = 0; |
12275 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12276 | if (*op_txt[i]) | |
12277 | { | |
12278 | if (needcomma) | |
12279 | (*info->fprintf_func) (info->stream, ","); | |
12280 | if (op_index[i] != -1 && !op_riprel[i]) | |
1d67fe3b TT |
12281 | { |
12282 | bfd_vma target = (bfd_vma) op_address[op_index[i]]; | |
12283 | ||
12284 | if (the_info && op_is_jump) | |
12285 | { | |
12286 | the_info->insn_info_valid = 1; | |
12287 | the_info->branch_delay_insns = 0; | |
12288 | the_info->data_size = 0; | |
12289 | the_info->target = target; | |
12290 | the_info->target2 = 0; | |
12291 | } | |
12292 | (*info->print_address_func) (target, info); | |
12293 | } | |
ce518a5f L |
12294 | else |
12295 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
12296 | needcomma = 1; | |
12297 | } | |
050dfa73 | 12298 | |
ce518a5f | 12299 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
12300 | if (op_index[i] != -1 && op_riprel[i]) |
12301 | { | |
12302 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 12303 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 12304 | + op_address[op_index[i]]), info); |
185b1163 | 12305 | break; |
52b15da3 | 12306 | } |
e396998b | 12307 | return codep - priv.the_buffer; |
252b5132 RH |
12308 | } |
12309 | ||
6439fc28 | 12310 | static const char *float_mem[] = { |
252b5132 | 12311 | /* d8 */ |
7c52e0e8 L |
12312 | "fadd{s|}", |
12313 | "fmul{s|}", | |
12314 | "fcom{s|}", | |
12315 | "fcomp{s|}", | |
12316 | "fsub{s|}", | |
12317 | "fsubr{s|}", | |
12318 | "fdiv{s|}", | |
12319 | "fdivr{s|}", | |
db6eb5be | 12320 | /* d9 */ |
7c52e0e8 | 12321 | "fld{s|}", |
252b5132 | 12322 | "(bad)", |
7c52e0e8 L |
12323 | "fst{s|}", |
12324 | "fstp{s|}", | |
d1c36125 | 12325 | "fldenv{C|C}", |
252b5132 | 12326 | "fldcw", |
d1c36125 | 12327 | "fNstenv{C|C}", |
252b5132 RH |
12328 | "fNstcw", |
12329 | /* da */ | |
7c52e0e8 L |
12330 | "fiadd{l|}", |
12331 | "fimul{l|}", | |
12332 | "ficom{l|}", | |
12333 | "ficomp{l|}", | |
12334 | "fisub{l|}", | |
12335 | "fisubr{l|}", | |
12336 | "fidiv{l|}", | |
12337 | "fidivr{l|}", | |
252b5132 | 12338 | /* db */ |
7c52e0e8 L |
12339 | "fild{l|}", |
12340 | "fisttp{l|}", | |
12341 | "fist{l|}", | |
12342 | "fistp{l|}", | |
252b5132 | 12343 | "(bad)", |
464dc4af | 12344 | "fld{t|}", |
252b5132 | 12345 | "(bad)", |
464dc4af | 12346 | "fstp{t|}", |
252b5132 | 12347 | /* dc */ |
7c52e0e8 L |
12348 | "fadd{l|}", |
12349 | "fmul{l|}", | |
12350 | "fcom{l|}", | |
12351 | "fcomp{l|}", | |
12352 | "fsub{l|}", | |
12353 | "fsubr{l|}", | |
12354 | "fdiv{l|}", | |
12355 | "fdivr{l|}", | |
252b5132 | 12356 | /* dd */ |
7c52e0e8 L |
12357 | "fld{l|}", |
12358 | "fisttp{ll|}", | |
12359 | "fst{l||}", | |
12360 | "fstp{l|}", | |
d1c36125 | 12361 | "frstor{C|C}", |
252b5132 | 12362 | "(bad)", |
d1c36125 | 12363 | "fNsave{C|C}", |
252b5132 RH |
12364 | "fNstsw", |
12365 | /* de */ | |
ac465521 JB |
12366 | "fiadd{s|}", |
12367 | "fimul{s|}", | |
12368 | "ficom{s|}", | |
12369 | "ficomp{s|}", | |
12370 | "fisub{s|}", | |
12371 | "fisubr{s|}", | |
12372 | "fidiv{s|}", | |
12373 | "fidivr{s|}", | |
252b5132 | 12374 | /* df */ |
ac465521 JB |
12375 | "fild{s|}", |
12376 | "fisttp{s|}", | |
12377 | "fist{s|}", | |
12378 | "fistp{s|}", | |
252b5132 | 12379 | "fbld", |
7c52e0e8 | 12380 | "fild{ll|}", |
252b5132 | 12381 | "fbstp", |
7c52e0e8 | 12382 | "fistp{ll|}", |
1d9f512f AM |
12383 | }; |
12384 | ||
12385 | static const unsigned char float_mem_mode[] = { | |
12386 | /* d8 */ | |
12387 | d_mode, | |
12388 | d_mode, | |
12389 | d_mode, | |
12390 | d_mode, | |
12391 | d_mode, | |
12392 | d_mode, | |
12393 | d_mode, | |
12394 | d_mode, | |
12395 | /* d9 */ | |
12396 | d_mode, | |
12397 | 0, | |
12398 | d_mode, | |
12399 | d_mode, | |
12400 | 0, | |
12401 | w_mode, | |
12402 | 0, | |
12403 | w_mode, | |
12404 | /* da */ | |
12405 | d_mode, | |
12406 | d_mode, | |
12407 | d_mode, | |
12408 | d_mode, | |
12409 | d_mode, | |
12410 | d_mode, | |
12411 | d_mode, | |
12412 | d_mode, | |
12413 | /* db */ | |
12414 | d_mode, | |
12415 | d_mode, | |
12416 | d_mode, | |
12417 | d_mode, | |
12418 | 0, | |
9306ca4a | 12419 | t_mode, |
1d9f512f | 12420 | 0, |
9306ca4a | 12421 | t_mode, |
1d9f512f AM |
12422 | /* dc */ |
12423 | q_mode, | |
12424 | q_mode, | |
12425 | q_mode, | |
12426 | q_mode, | |
12427 | q_mode, | |
12428 | q_mode, | |
12429 | q_mode, | |
12430 | q_mode, | |
12431 | /* dd */ | |
12432 | q_mode, | |
12433 | q_mode, | |
12434 | q_mode, | |
12435 | q_mode, | |
12436 | 0, | |
12437 | 0, | |
12438 | 0, | |
12439 | w_mode, | |
12440 | /* de */ | |
12441 | w_mode, | |
12442 | w_mode, | |
12443 | w_mode, | |
12444 | w_mode, | |
12445 | w_mode, | |
12446 | w_mode, | |
12447 | w_mode, | |
12448 | w_mode, | |
12449 | /* df */ | |
12450 | w_mode, | |
12451 | w_mode, | |
12452 | w_mode, | |
12453 | w_mode, | |
9306ca4a | 12454 | t_mode, |
1d9f512f | 12455 | q_mode, |
9306ca4a | 12456 | t_mode, |
1d9f512f | 12457 | q_mode |
252b5132 RH |
12458 | }; |
12459 | ||
ce518a5f L |
12460 | #define ST { OP_ST, 0 } |
12461 | #define STi { OP_STi, 0 } | |
252b5132 | 12462 | |
48c97fa1 L |
12463 | #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 |
12464 | #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 | |
12465 | #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 | |
12466 | #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 | |
12467 | #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 | |
12468 | #define FGRPda_5 NULL, { { NULL, 6 } }, 0 | |
12469 | #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 | |
12470 | #define FGRPde_3 NULL, { { NULL, 8 } }, 0 | |
12471 | #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 | |
252b5132 | 12472 | |
2da11e11 | 12473 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
12474 | /* d8 */ |
12475 | { | |
bf890a93 IT |
12476 | { "fadd", { ST, STi }, 0 }, |
12477 | { "fmul", { ST, STi }, 0 }, | |
12478 | { "fcom", { STi }, 0 }, | |
12479 | { "fcomp", { STi }, 0 }, | |
12480 | { "fsub", { ST, STi }, 0 }, | |
12481 | { "fsubr", { ST, STi }, 0 }, | |
12482 | { "fdiv", { ST, STi }, 0 }, | |
12483 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
12484 | }, |
12485 | /* d9 */ | |
12486 | { | |
bf890a93 IT |
12487 | { "fld", { STi }, 0 }, |
12488 | { "fxch", { STi }, 0 }, | |
252b5132 | 12489 | { FGRPd9_2 }, |
592d1631 | 12490 | { Bad_Opcode }, |
252b5132 RH |
12491 | { FGRPd9_4 }, |
12492 | { FGRPd9_5 }, | |
12493 | { FGRPd9_6 }, | |
12494 | { FGRPd9_7 }, | |
12495 | }, | |
12496 | /* da */ | |
12497 | { | |
bf890a93 IT |
12498 | { "fcmovb", { ST, STi }, 0 }, |
12499 | { "fcmove", { ST, STi }, 0 }, | |
12500 | { "fcmovbe",{ ST, STi }, 0 }, | |
12501 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 12502 | { Bad_Opcode }, |
252b5132 | 12503 | { FGRPda_5 }, |
592d1631 L |
12504 | { Bad_Opcode }, |
12505 | { Bad_Opcode }, | |
252b5132 RH |
12506 | }, |
12507 | /* db */ | |
12508 | { | |
bf890a93 IT |
12509 | { "fcmovnb",{ ST, STi }, 0 }, |
12510 | { "fcmovne",{ ST, STi }, 0 }, | |
12511 | { "fcmovnbe",{ ST, STi }, 0 }, | |
12512 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 12513 | { FGRPdb_4 }, |
bf890a93 IT |
12514 | { "fucomi", { ST, STi }, 0 }, |
12515 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 12516 | { Bad_Opcode }, |
252b5132 RH |
12517 | }, |
12518 | /* dc */ | |
12519 | { | |
bf890a93 IT |
12520 | { "fadd", { STi, ST }, 0 }, |
12521 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
12522 | { Bad_Opcode }, |
12523 | { Bad_Opcode }, | |
d53e6b98 JB |
12524 | { "fsub{!M|r}", { STi, ST }, 0 }, |
12525 | { "fsub{M|}", { STi, ST }, 0 }, | |
12526 | { "fdiv{!M|r}", { STi, ST }, 0 }, | |
12527 | { "fdiv{M|}", { STi, ST }, 0 }, | |
252b5132 RH |
12528 | }, |
12529 | /* dd */ | |
12530 | { | |
bf890a93 | 12531 | { "ffree", { STi }, 0 }, |
592d1631 | 12532 | { Bad_Opcode }, |
bf890a93 IT |
12533 | { "fst", { STi }, 0 }, |
12534 | { "fstp", { STi }, 0 }, | |
12535 | { "fucom", { STi }, 0 }, | |
12536 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
12537 | { Bad_Opcode }, |
12538 | { Bad_Opcode }, | |
252b5132 RH |
12539 | }, |
12540 | /* de */ | |
12541 | { | |
bf890a93 IT |
12542 | { "faddp", { STi, ST }, 0 }, |
12543 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 12544 | { Bad_Opcode }, |
252b5132 | 12545 | { FGRPde_3 }, |
d53e6b98 JB |
12546 | { "fsub{!M|r}p", { STi, ST }, 0 }, |
12547 | { "fsub{M|}p", { STi, ST }, 0 }, | |
12548 | { "fdiv{!M|r}p", { STi, ST }, 0 }, | |
12549 | { "fdiv{M|}p", { STi, ST }, 0 }, | |
252b5132 RH |
12550 | }, |
12551 | /* df */ | |
12552 | { | |
bf890a93 | 12553 | { "ffreep", { STi }, 0 }, |
592d1631 L |
12554 | { Bad_Opcode }, |
12555 | { Bad_Opcode }, | |
12556 | { Bad_Opcode }, | |
252b5132 | 12557 | { FGRPdf_4 }, |
bf890a93 IT |
12558 | { "fucomip", { ST, STi }, 0 }, |
12559 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 12560 | { Bad_Opcode }, |
252b5132 RH |
12561 | }, |
12562 | }; | |
12563 | ||
252b5132 | 12564 | static char *fgrps[][8] = { |
48c97fa1 L |
12565 | /* Bad opcode 0 */ |
12566 | { | |
12567 | "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12568 | }, | |
12569 | ||
12570 | /* d9_2 1 */ | |
252b5132 RH |
12571 | { |
12572 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12573 | }, | |
12574 | ||
48c97fa1 | 12575 | /* d9_4 2 */ |
252b5132 RH |
12576 | { |
12577 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
12578 | }, | |
12579 | ||
48c97fa1 | 12580 | /* d9_5 3 */ |
252b5132 RH |
12581 | { |
12582 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
12583 | }, | |
12584 | ||
48c97fa1 | 12585 | /* d9_6 4 */ |
252b5132 RH |
12586 | { |
12587 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
12588 | }, | |
12589 | ||
48c97fa1 | 12590 | /* d9_7 5 */ |
252b5132 RH |
12591 | { |
12592 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
12593 | }, | |
12594 | ||
48c97fa1 | 12595 | /* da_5 6 */ |
252b5132 RH |
12596 | { |
12597 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12598 | }, | |
12599 | ||
48c97fa1 | 12600 | /* db_4 7 */ |
252b5132 | 12601 | { |
309d3373 JB |
12602 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
12603 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
12604 | }, |
12605 | ||
48c97fa1 | 12606 | /* de_3 8 */ |
252b5132 RH |
12607 | { |
12608 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12609 | }, | |
12610 | ||
48c97fa1 | 12611 | /* df_4 9 */ |
252b5132 RH |
12612 | { |
12613 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12614 | }, | |
12615 | }; | |
12616 | ||
b6169b20 L |
12617 | static void |
12618 | swap_operand (void) | |
12619 | { | |
12620 | mnemonicendp[0] = '.'; | |
12621 | mnemonicendp[1] = 's'; | |
12622 | mnemonicendp += 2; | |
12623 | } | |
12624 | ||
b844680a L |
12625 | static void |
12626 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
12627 | int sizeflag ATTRIBUTE_UNUSED) | |
12628 | { | |
12629 | /* Skip mod/rm byte. */ | |
12630 | MODRM_CHECK; | |
12631 | codep++; | |
12632 | } | |
12633 | ||
252b5132 | 12634 | static void |
26ca5450 | 12635 | dofloat (int sizeflag) |
252b5132 | 12636 | { |
2da11e11 | 12637 | const struct dis386 *dp; |
252b5132 RH |
12638 | unsigned char floatop; |
12639 | ||
12640 | floatop = codep[-1]; | |
12641 | ||
7967e09e | 12642 | if (modrm.mod != 3) |
252b5132 | 12643 | { |
7967e09e | 12644 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
12645 | |
12646 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 12647 | obufp = op_out[0]; |
6e50d963 | 12648 | op_ad = 2; |
1d9f512f | 12649 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
12650 | return; |
12651 | } | |
6608db57 | 12652 | /* Skip mod/rm byte. */ |
4bba6815 | 12653 | MODRM_CHECK; |
252b5132 RH |
12654 | codep++; |
12655 | ||
7967e09e | 12656 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
12657 | if (dp->name == NULL) |
12658 | { | |
7967e09e | 12659 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 12660 | |
6608db57 | 12661 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 12662 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 12663 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
12664 | } |
12665 | else | |
12666 | { | |
12667 | putop (dp->name, sizeflag); | |
12668 | ||
ce518a5f | 12669 | obufp = op_out[0]; |
6e50d963 | 12670 | op_ad = 2; |
ce518a5f L |
12671 | if (dp->op[0].rtn) |
12672 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 12673 | |
ce518a5f | 12674 | obufp = op_out[1]; |
6e50d963 | 12675 | op_ad = 1; |
ce518a5f L |
12676 | if (dp->op[1].rtn) |
12677 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
12678 | } |
12679 | } | |
12680 | ||
9ce09ba2 RM |
12681 | /* Like oappend (below), but S is a string starting with '%'. |
12682 | In Intel syntax, the '%' is elided. */ | |
12683 | static void | |
12684 | oappend_maybe_intel (const char *s) | |
12685 | { | |
12686 | oappend (s + intel_syntax); | |
12687 | } | |
12688 | ||
252b5132 | 12689 | static void |
26ca5450 | 12690 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12691 | { |
9ce09ba2 | 12692 | oappend_maybe_intel ("%st"); |
252b5132 RH |
12693 | } |
12694 | ||
252b5132 | 12695 | static void |
26ca5450 | 12696 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12697 | { |
7967e09e | 12698 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 12699 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
12700 | } |
12701 | ||
6608db57 | 12702 | /* Capital letters in template are macros. */ |
6439fc28 | 12703 | static int |
d3ce72d0 | 12704 | putop (const char *in_template, int sizeflag) |
252b5132 | 12705 | { |
2da11e11 | 12706 | const char *p; |
9306ca4a | 12707 | int alt = 0; |
9d141669 | 12708 | int cond = 1; |
98b528ac L |
12709 | unsigned int l = 0, len = 1; |
12710 | char last[4]; | |
12711 | ||
12712 | #define SAVE_LAST(c) \ | |
12713 | if (l < len && l < sizeof (last)) \ | |
12714 | last[l++] = c; \ | |
12715 | else \ | |
12716 | abort (); | |
252b5132 | 12717 | |
d3ce72d0 | 12718 | for (p = in_template; *p; p++) |
252b5132 RH |
12719 | { |
12720 | switch (*p) | |
12721 | { | |
12722 | default: | |
12723 | *obufp++ = *p; | |
12724 | break; | |
98b528ac L |
12725 | case '%': |
12726 | len++; | |
12727 | break; | |
9d141669 L |
12728 | case '!': |
12729 | cond = 0; | |
12730 | break; | |
6439fc28 | 12731 | case '{': |
6439fc28 | 12732 | if (intel_syntax) |
6439fc28 AM |
12733 | { |
12734 | while (*++p != '|') | |
7c52e0e8 L |
12735 | if (*p == '}' || *p == '\0') |
12736 | abort (); | |
d1c36125 | 12737 | alt = 1; |
6439fc28 | 12738 | } |
d1c36125 | 12739 | break; |
6439fc28 AM |
12740 | case '|': |
12741 | while (*++p != '}') | |
12742 | { | |
12743 | if (*p == '\0') | |
12744 | abort (); | |
12745 | } | |
12746 | break; | |
12747 | case '}': | |
d1c36125 | 12748 | alt = 0; |
6439fc28 | 12749 | break; |
252b5132 | 12750 | case 'A': |
db6eb5be AM |
12751 | if (intel_syntax) |
12752 | break; | |
7967e09e | 12753 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
12754 | *obufp++ = 'b'; |
12755 | break; | |
12756 | case 'B': | |
4b06377f L |
12757 | if (l == 0 && len == 1) |
12758 | { | |
dc1e8a47 | 12759 | case_B: |
4b06377f L |
12760 | if (intel_syntax) |
12761 | break; | |
12762 | if (sizeflag & SUFFIX_ALWAYS) | |
12763 | *obufp++ = 'b'; | |
12764 | } | |
12765 | else | |
12766 | { | |
12767 | if (l != 1 | |
12768 | || len != 2 | |
12769 | || last[0] != 'L') | |
12770 | { | |
12771 | SAVE_LAST (*p); | |
12772 | break; | |
12773 | } | |
12774 | ||
12775 | if (address_mode == mode_64bit | |
12776 | && !(prefixes & PREFIX_ADDR)) | |
12777 | { | |
12778 | *obufp++ = 'a'; | |
12779 | *obufp++ = 'b'; | |
12780 | *obufp++ = 's'; | |
12781 | } | |
12782 | ||
12783 | goto case_B; | |
12784 | } | |
252b5132 | 12785 | break; |
9306ca4a JB |
12786 | case 'C': |
12787 | if (intel_syntax && !alt) | |
12788 | break; | |
12789 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
12790 | { | |
12791 | if (sizeflag & DFLAG) | |
12792 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12793 | else | |
12794 | *obufp++ = intel_syntax ? 'w' : 's'; | |
12795 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12796 | } | |
12797 | break; | |
ed7841b3 JB |
12798 | case 'D': |
12799 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
12800 | break; | |
161a04f6 | 12801 | USED_REX (REX_W); |
7967e09e | 12802 | if (modrm.mod == 3) |
ed7841b3 | 12803 | { |
161a04f6 | 12804 | if (rex & REX_W) |
ed7841b3 | 12805 | *obufp++ = 'q'; |
ed7841b3 | 12806 | else |
f16cd0d5 L |
12807 | { |
12808 | if (sizeflag & DFLAG) | |
12809 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12810 | else | |
12811 | *obufp++ = 'w'; | |
12812 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12813 | } | |
ed7841b3 JB |
12814 | } |
12815 | else | |
12816 | *obufp++ = 'w'; | |
12817 | break; | |
252b5132 | 12818 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 12819 | if (address_mode == mode_64bit) |
c1a64871 JH |
12820 | { |
12821 | if (sizeflag & AFLAG) | |
12822 | *obufp++ = 'r'; | |
12823 | else | |
12824 | *obufp++ = 'e'; | |
12825 | } | |
12826 | else | |
12827 | if (sizeflag & AFLAG) | |
12828 | *obufp++ = 'e'; | |
3ffd33cf AM |
12829 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12830 | break; | |
12831 | case 'F': | |
db6eb5be AM |
12832 | if (intel_syntax) |
12833 | break; | |
e396998b | 12834 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
12835 | { |
12836 | if (sizeflag & AFLAG) | |
cb712a9e | 12837 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 12838 | else |
cb712a9e | 12839 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
12840 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12841 | } | |
252b5132 | 12842 | break; |
52fd6d94 JB |
12843 | case 'G': |
12844 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
12845 | break; | |
161a04f6 | 12846 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
12847 | *obufp++ = 'l'; |
12848 | else | |
12849 | *obufp++ = 'w'; | |
161a04f6 | 12850 | if (!(rex & REX_W)) |
52fd6d94 JB |
12851 | used_prefixes |= (prefixes & PREFIX_DATA); |
12852 | break; | |
5dd0794d | 12853 | case 'H': |
db6eb5be AM |
12854 | if (intel_syntax) |
12855 | break; | |
5dd0794d AM |
12856 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
12857 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
12858 | { | |
12859 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
12860 | *obufp++ = ','; | |
12861 | *obufp++ = 'p'; | |
12862 | if (prefixes & PREFIX_DS) | |
12863 | *obufp++ = 't'; | |
12864 | else | |
12865 | *obufp++ = 'n'; | |
12866 | } | |
12867 | break; | |
42903f7f L |
12868 | case 'K': |
12869 | USED_REX (REX_W); | |
12870 | if (rex & REX_W) | |
12871 | *obufp++ = 'q'; | |
12872 | else | |
12873 | *obufp++ = 'd'; | |
12874 | break; | |
6dd5059a | 12875 | case 'Z': |
04d824a4 JB |
12876 | if (l != 0 || len != 1) |
12877 | { | |
12878 | if (l != 1 || len != 2 || last[0] != 'X') | |
12879 | { | |
12880 | SAVE_LAST (*p); | |
12881 | break; | |
12882 | } | |
12883 | if (!need_vex || !vex.evex) | |
12884 | abort (); | |
12885 | if (intel_syntax | |
12886 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
12887 | break; | |
12888 | switch (vex.length) | |
12889 | { | |
12890 | case 128: | |
12891 | *obufp++ = 'x'; | |
12892 | break; | |
12893 | case 256: | |
12894 | *obufp++ = 'y'; | |
12895 | break; | |
12896 | case 512: | |
12897 | *obufp++ = 'z'; | |
12898 | break; | |
12899 | default: | |
12900 | abort (); | |
12901 | } | |
12902 | break; | |
12903 | } | |
6dd5059a L |
12904 | if (intel_syntax) |
12905 | break; | |
12906 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
12907 | { | |
12908 | *obufp++ = 'q'; | |
12909 | break; | |
12910 | } | |
12911 | /* Fall through. */ | |
98b528ac | 12912 | goto case_L; |
252b5132 | 12913 | case 'L': |
98b528ac L |
12914 | if (l != 0 || len != 1) |
12915 | { | |
12916 | SAVE_LAST (*p); | |
12917 | break; | |
12918 | } | |
dc1e8a47 | 12919 | case_L: |
db6eb5be AM |
12920 | if (intel_syntax) |
12921 | break; | |
252b5132 RH |
12922 | if (sizeflag & SUFFIX_ALWAYS) |
12923 | *obufp++ = 'l'; | |
252b5132 | 12924 | break; |
9d141669 L |
12925 | case 'M': |
12926 | if (intel_mnemonic != cond) | |
12927 | *obufp++ = 'r'; | |
12928 | break; | |
252b5132 RH |
12929 | case 'N': |
12930 | if ((prefixes & PREFIX_FWAIT) == 0) | |
12931 | *obufp++ = 'n'; | |
7d421014 ILT |
12932 | else |
12933 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 12934 | break; |
52b15da3 | 12935 | case 'O': |
161a04f6 L |
12936 | USED_REX (REX_W); |
12937 | if (rex & REX_W) | |
6439fc28 | 12938 | *obufp++ = 'o'; |
a35ca55a JB |
12939 | else if (intel_syntax && (sizeflag & DFLAG)) |
12940 | *obufp++ = 'q'; | |
52b15da3 JH |
12941 | else |
12942 | *obufp++ = 'd'; | |
161a04f6 | 12943 | if (!(rex & REX_W)) |
a35ca55a | 12944 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 12945 | break; |
07f5af7d L |
12946 | case '&': |
12947 | if (!intel_syntax | |
12948 | && address_mode == mode_64bit | |
12949 | && isa64 == intel64) | |
12950 | { | |
12951 | *obufp++ = 'q'; | |
12952 | break; | |
12953 | } | |
12954 | /* Fall through. */ | |
6439fc28 | 12955 | case 'T': |
d9e3625e L |
12956 | if (!intel_syntax |
12957 | && address_mode == mode_64bit | |
7bb15c6f | 12958 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
12959 | { |
12960 | *obufp++ = 'q'; | |
12961 | break; | |
12962 | } | |
6608db57 | 12963 | /* Fall through. */ |
4b4c407a | 12964 | goto case_P; |
252b5132 | 12965 | case 'P': |
4b4c407a | 12966 | if (l == 0 && len == 1) |
d9e3625e | 12967 | { |
dc1e8a47 | 12968 | case_P: |
4b4c407a | 12969 | if (intel_syntax) |
d9e3625e | 12970 | { |
4b4c407a L |
12971 | if ((rex & REX_W) == 0 |
12972 | && (prefixes & PREFIX_DATA)) | |
12973 | { | |
12974 | if ((sizeflag & DFLAG) == 0) | |
12975 | *obufp++ = 'w'; | |
12976 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12977 | } | |
12978 | break; | |
12979 | } | |
12980 | if ((prefixes & PREFIX_DATA) | |
12981 | || (rex & REX_W) | |
12982 | || (sizeflag & SUFFIX_ALWAYS)) | |
12983 | { | |
12984 | USED_REX (REX_W); | |
12985 | if (rex & REX_W) | |
12986 | *obufp++ = 'q'; | |
12987 | else | |
12988 | { | |
12989 | if (sizeflag & DFLAG) | |
12990 | *obufp++ = 'l'; | |
12991 | else | |
12992 | *obufp++ = 'w'; | |
12993 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12994 | } | |
d9e3625e | 12995 | } |
d9e3625e | 12996 | } |
4b4c407a | 12997 | else |
252b5132 | 12998 | { |
4b4c407a L |
12999 | if (l != 1 || len != 2 || last[0] != 'L') |
13000 | { | |
13001 | SAVE_LAST (*p); | |
13002 | break; | |
13003 | } | |
13004 | ||
13005 | if ((prefixes & PREFIX_DATA) | |
13006 | || (rex & REX_W) | |
13007 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 13008 | { |
4b4c407a L |
13009 | USED_REX (REX_W); |
13010 | if (rex & REX_W) | |
13011 | *obufp++ = 'q'; | |
13012 | else | |
13013 | { | |
13014 | if (sizeflag & DFLAG) | |
13015 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13016 | else | |
13017 | *obufp++ = 'w'; | |
13018 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13019 | } | |
52b15da3 | 13020 | } |
252b5132 RH |
13021 | } |
13022 | break; | |
6439fc28 | 13023 | case 'U': |
db6eb5be AM |
13024 | if (intel_syntax) |
13025 | break; | |
7bb15c6f | 13026 | if (address_mode == mode_64bit |
6c067bbb | 13027 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 13028 | { |
7967e09e | 13029 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 13030 | *obufp++ = 'q'; |
6439fc28 AM |
13031 | break; |
13032 | } | |
6608db57 | 13033 | /* Fall through. */ |
98b528ac | 13034 | goto case_Q; |
252b5132 | 13035 | case 'Q': |
98b528ac | 13036 | if (l == 0 && len == 1) |
252b5132 | 13037 | { |
dc1e8a47 | 13038 | case_Q: |
98b528ac L |
13039 | if (intel_syntax && !alt) |
13040 | break; | |
13041 | USED_REX (REX_W); | |
13042 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 13043 | { |
98b528ac L |
13044 | if (rex & REX_W) |
13045 | *obufp++ = 'q'; | |
52b15da3 | 13046 | else |
98b528ac L |
13047 | { |
13048 | if (sizeflag & DFLAG) | |
13049 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13050 | else | |
13051 | *obufp++ = 'w'; | |
f16cd0d5 | 13052 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 13053 | } |
52b15da3 | 13054 | } |
98b528ac L |
13055 | } |
13056 | else | |
13057 | { | |
13058 | if (l != 1 || len != 2 || last[0] != 'L') | |
13059 | { | |
13060 | SAVE_LAST (*p); | |
13061 | break; | |
13062 | } | |
589958d6 | 13063 | if ((intel_syntax && need_modrm) |
98b528ac L |
13064 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) |
13065 | break; | |
13066 | if ((rex & REX_W)) | |
13067 | { | |
13068 | USED_REX (REX_W); | |
13069 | *obufp++ = 'q'; | |
13070 | } | |
589958d6 JB |
13071 | else if((address_mode == mode_64bit && need_modrm) |
13072 | || (sizeflag & SUFFIX_ALWAYS)) | |
13073 | *obufp++ = intel_syntax? 'd' : 'l'; | |
252b5132 RH |
13074 | } |
13075 | break; | |
13076 | case 'R': | |
161a04f6 L |
13077 | USED_REX (REX_W); |
13078 | if (rex & REX_W) | |
a35ca55a JB |
13079 | *obufp++ = 'q'; |
13080 | else if (sizeflag & DFLAG) | |
c608c12e | 13081 | { |
a35ca55a | 13082 | if (intel_syntax) |
c608c12e | 13083 | *obufp++ = 'd'; |
c608c12e | 13084 | else |
a35ca55a | 13085 | *obufp++ = 'l'; |
c608c12e | 13086 | } |
252b5132 | 13087 | else |
a35ca55a JB |
13088 | *obufp++ = 'w'; |
13089 | if (intel_syntax && !p[1] | |
161a04f6 | 13090 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 13091 | *obufp++ = 'e'; |
161a04f6 | 13092 | if (!(rex & REX_W)) |
52b15da3 | 13093 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 13094 | break; |
1a114b12 | 13095 | case 'V': |
4b06377f | 13096 | if (l == 0 && len == 1) |
1a114b12 | 13097 | { |
4b06377f L |
13098 | if (intel_syntax) |
13099 | break; | |
7bb15c6f | 13100 | if (address_mode == mode_64bit |
6c067bbb | 13101 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
13102 | { |
13103 | if (sizeflag & SUFFIX_ALWAYS) | |
13104 | *obufp++ = 'q'; | |
13105 | break; | |
13106 | } | |
13107 | } | |
13108 | else | |
13109 | { | |
13110 | if (l != 1 | |
13111 | || len != 2 | |
13112 | || last[0] != 'L') | |
13113 | { | |
13114 | SAVE_LAST (*p); | |
13115 | break; | |
13116 | } | |
13117 | ||
13118 | if (rex & REX_W) | |
13119 | { | |
13120 | *obufp++ = 'a'; | |
13121 | *obufp++ = 'b'; | |
13122 | *obufp++ = 's'; | |
13123 | } | |
1a114b12 JB |
13124 | } |
13125 | /* Fall through. */ | |
4b06377f | 13126 | goto case_S; |
252b5132 | 13127 | case 'S': |
4b06377f | 13128 | if (l == 0 && len == 1) |
252b5132 | 13129 | { |
dc1e8a47 | 13130 | case_S: |
4b06377f L |
13131 | if (intel_syntax) |
13132 | break; | |
13133 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 13134 | { |
4b06377f L |
13135 | if (rex & REX_W) |
13136 | *obufp++ = 'q'; | |
52b15da3 | 13137 | else |
4b06377f L |
13138 | { |
13139 | if (sizeflag & DFLAG) | |
13140 | *obufp++ = 'l'; | |
13141 | else | |
13142 | *obufp++ = 'w'; | |
13143 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13144 | } | |
13145 | } | |
13146 | } | |
13147 | else | |
13148 | { | |
13149 | if (l != 1 | |
13150 | || len != 2 | |
13151 | || last[0] != 'L') | |
13152 | { | |
13153 | SAVE_LAST (*p); | |
13154 | break; | |
52b15da3 | 13155 | } |
4b06377f L |
13156 | |
13157 | if (address_mode == mode_64bit | |
13158 | && !(prefixes & PREFIX_ADDR)) | |
13159 | { | |
13160 | *obufp++ = 'a'; | |
13161 | *obufp++ = 'b'; | |
13162 | *obufp++ = 's'; | |
13163 | } | |
13164 | ||
13165 | goto case_S; | |
252b5132 | 13166 | } |
252b5132 | 13167 | break; |
041bd2e0 | 13168 | case 'X': |
c0f3af97 L |
13169 | if (l != 0 || len != 1) |
13170 | { | |
13171 | SAVE_LAST (*p); | |
13172 | break; | |
13173 | } | |
bf926894 JB |
13174 | if (need_vex |
13175 | ? vex.prefix == DATA_PREFIX_OPCODE | |
13176 | : prefixes & PREFIX_DATA) | |
c0f3af97 | 13177 | { |
bf926894 JB |
13178 | *obufp++ = 'd'; |
13179 | used_prefixes |= PREFIX_DATA; | |
c0f3af97 | 13180 | } |
041bd2e0 | 13181 | else |
bf926894 | 13182 | *obufp++ = 's'; |
041bd2e0 | 13183 | break; |
76f227a5 | 13184 | case 'Y': |
c0f3af97 | 13185 | if (l == 0 && len == 1) |
9646c87b | 13186 | abort (); |
c0f3af97 L |
13187 | else |
13188 | { | |
13189 | if (l != 1 || len != 2 || last[0] != 'X') | |
13190 | { | |
13191 | SAVE_LAST (*p); | |
13192 | break; | |
13193 | } | |
13194 | if (!need_vex) | |
13195 | abort (); | |
13196 | if (intel_syntax | |
04d824a4 | 13197 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
13198 | break; |
13199 | switch (vex.length) | |
13200 | { | |
13201 | case 128: | |
13202 | *obufp++ = 'x'; | |
13203 | break; | |
13204 | case 256: | |
13205 | *obufp++ = 'y'; | |
13206 | break; | |
04d824a4 JB |
13207 | case 512: |
13208 | if (!vex.evex) | |
c0f3af97 | 13209 | default: |
04d824a4 | 13210 | abort (); |
c0f3af97 | 13211 | } |
76f227a5 JH |
13212 | } |
13213 | break; | |
252b5132 | 13214 | case 'W': |
0bfee649 | 13215 | if (l == 0 && len == 1) |
a35ca55a | 13216 | { |
0bfee649 L |
13217 | /* operand size flag for cwtl, cbtw */ |
13218 | USED_REX (REX_W); | |
13219 | if (rex & REX_W) | |
13220 | { | |
13221 | if (intel_syntax) | |
13222 | *obufp++ = 'd'; | |
13223 | else | |
13224 | *obufp++ = 'l'; | |
13225 | } | |
13226 | else if (sizeflag & DFLAG) | |
13227 | *obufp++ = 'w'; | |
a35ca55a | 13228 | else |
0bfee649 L |
13229 | *obufp++ = 'b'; |
13230 | if (!(rex & REX_W)) | |
13231 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 13232 | } |
252b5132 | 13233 | else |
0bfee649 | 13234 | { |
6c30d220 L |
13235 | if (l != 1 |
13236 | || len != 2 | |
13237 | || (last[0] != 'X' | |
13238 | && last[0] != 'L')) | |
0bfee649 L |
13239 | { |
13240 | SAVE_LAST (*p); | |
13241 | break; | |
13242 | } | |
13243 | if (!need_vex) | |
13244 | abort (); | |
6c30d220 L |
13245 | if (last[0] == 'X') |
13246 | *obufp++ = vex.w ? 'd': 's'; | |
13247 | else | |
13248 | *obufp++ = vex.w ? 'q': 'd'; | |
0bfee649 | 13249 | } |
252b5132 | 13250 | break; |
a72d2af2 L |
13251 | case '^': |
13252 | if (intel_syntax) | |
13253 | break; | |
5990e377 JB |
13254 | if (isa64 == intel64 && (rex & REX_W)) |
13255 | { | |
13256 | USED_REX (REX_W); | |
13257 | *obufp++ = 'q'; | |
13258 | break; | |
13259 | } | |
a72d2af2 L |
13260 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) |
13261 | { | |
13262 | if (sizeflag & DFLAG) | |
13263 | *obufp++ = 'l'; | |
13264 | else | |
13265 | *obufp++ = 'w'; | |
13266 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13267 | } | |
13268 | break; | |
5db04b09 L |
13269 | case '@': |
13270 | if (intel_syntax) | |
13271 | break; | |
13272 | if (address_mode == mode_64bit | |
13273 | && (isa64 == intel64 | |
13274 | || ((sizeflag & DFLAG) || (rex & REX_W)))) | |
13275 | *obufp++ = 'q'; | |
13276 | else if ((prefixes & PREFIX_DATA)) | |
13277 | { | |
13278 | if (!(sizeflag & DFLAG)) | |
13279 | *obufp++ = 'w'; | |
13280 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13281 | } | |
13282 | break; | |
252b5132 RH |
13283 | } |
13284 | } | |
13285 | *obufp = 0; | |
ea397f5b | 13286 | mnemonicendp = obufp; |
6439fc28 | 13287 | return 0; |
252b5132 RH |
13288 | } |
13289 | ||
13290 | static void | |
26ca5450 | 13291 | oappend (const char *s) |
252b5132 | 13292 | { |
ea397f5b | 13293 | obufp = stpcpy (obufp, s); |
252b5132 RH |
13294 | } |
13295 | ||
13296 | static void | |
26ca5450 | 13297 | append_seg (void) |
252b5132 | 13298 | { |
285ca992 L |
13299 | /* Only print the active segment register. */ |
13300 | if (!active_seg_prefix) | |
13301 | return; | |
13302 | ||
13303 | used_prefixes |= active_seg_prefix; | |
13304 | switch (active_seg_prefix) | |
7d421014 | 13305 | { |
285ca992 | 13306 | case PREFIX_CS: |
9ce09ba2 | 13307 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
13308 | break; |
13309 | case PREFIX_DS: | |
9ce09ba2 | 13310 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
13311 | break; |
13312 | case PREFIX_SS: | |
9ce09ba2 | 13313 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
13314 | break; |
13315 | case PREFIX_ES: | |
9ce09ba2 | 13316 | oappend_maybe_intel ("%es:"); |
285ca992 L |
13317 | break; |
13318 | case PREFIX_FS: | |
9ce09ba2 | 13319 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
13320 | break; |
13321 | case PREFIX_GS: | |
9ce09ba2 | 13322 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
13323 | break; |
13324 | default: | |
13325 | break; | |
7d421014 | 13326 | } |
252b5132 RH |
13327 | } |
13328 | ||
13329 | static void | |
26ca5450 | 13330 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
13331 | { |
13332 | if (!intel_syntax) | |
13333 | oappend ("*"); | |
13334 | OP_E (bytemode, sizeflag); | |
13335 | } | |
13336 | ||
52b15da3 | 13337 | static void |
26ca5450 | 13338 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 13339 | { |
cb712a9e | 13340 | if (address_mode == mode_64bit) |
52b15da3 JH |
13341 | { |
13342 | if (hex) | |
13343 | { | |
13344 | char tmp[30]; | |
13345 | int i; | |
13346 | buf[0] = '0'; | |
13347 | buf[1] = 'x'; | |
13348 | sprintf_vma (tmp, disp); | |
6608db57 | 13349 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
13350 | strcpy (buf + 2, tmp + i); |
13351 | } | |
13352 | else | |
13353 | { | |
13354 | bfd_signed_vma v = disp; | |
13355 | char tmp[30]; | |
13356 | int i; | |
13357 | if (v < 0) | |
13358 | { | |
13359 | *(buf++) = '-'; | |
13360 | v = -disp; | |
6608db57 | 13361 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
13362 | if (v < 0) |
13363 | { | |
13364 | strcpy (buf, "9223372036854775808"); | |
13365 | return; | |
13366 | } | |
13367 | } | |
13368 | if (!v) | |
13369 | { | |
13370 | strcpy (buf, "0"); | |
13371 | return; | |
13372 | } | |
13373 | ||
13374 | i = 0; | |
13375 | tmp[29] = 0; | |
13376 | while (v) | |
13377 | { | |
6608db57 | 13378 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
13379 | v /= 10; |
13380 | i++; | |
13381 | } | |
13382 | strcpy (buf, tmp + 29 - i); | |
13383 | } | |
13384 | } | |
13385 | else | |
13386 | { | |
13387 | if (hex) | |
13388 | sprintf (buf, "0x%x", (unsigned int) disp); | |
13389 | else | |
13390 | sprintf (buf, "%d", (int) disp); | |
13391 | } | |
13392 | } | |
13393 | ||
5d669648 L |
13394 | /* Put DISP in BUF as signed hex number. */ |
13395 | ||
13396 | static void | |
13397 | print_displacement (char *buf, bfd_vma disp) | |
13398 | { | |
13399 | bfd_signed_vma val = disp; | |
13400 | char tmp[30]; | |
13401 | int i, j = 0; | |
13402 | ||
13403 | if (val < 0) | |
13404 | { | |
13405 | buf[j++] = '-'; | |
13406 | val = -disp; | |
13407 | ||
13408 | /* Check for possible overflow. */ | |
13409 | if (val < 0) | |
13410 | { | |
13411 | switch (address_mode) | |
13412 | { | |
13413 | case mode_64bit: | |
13414 | strcpy (buf + j, "0x8000000000000000"); | |
13415 | break; | |
13416 | case mode_32bit: | |
13417 | strcpy (buf + j, "0x80000000"); | |
13418 | break; | |
13419 | case mode_16bit: | |
13420 | strcpy (buf + j, "0x8000"); | |
13421 | break; | |
13422 | } | |
13423 | return; | |
13424 | } | |
13425 | } | |
13426 | ||
13427 | buf[j++] = '0'; | |
13428 | buf[j++] = 'x'; | |
13429 | ||
0af1713e | 13430 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
13431 | for (i = 0; tmp[i] == '0'; i++) |
13432 | continue; | |
13433 | if (tmp[i] == '\0') | |
13434 | i--; | |
13435 | strcpy (buf + j, tmp + i); | |
13436 | } | |
13437 | ||
3f31e633 JB |
13438 | static void |
13439 | intel_operand_size (int bytemode, int sizeflag) | |
13440 | { | |
43234a1e L |
13441 | if (vex.evex |
13442 | && vex.b | |
13443 | && (bytemode == x_mode | |
13444 | || bytemode == evex_half_bcst_xmmq_mode)) | |
13445 | { | |
13446 | if (vex.w) | |
13447 | oappend ("QWORD PTR "); | |
13448 | else | |
13449 | oappend ("DWORD PTR "); | |
13450 | return; | |
13451 | } | |
3f31e633 JB |
13452 | switch (bytemode) |
13453 | { | |
13454 | case b_mode: | |
b6169b20 | 13455 | case b_swap_mode: |
42903f7f | 13456 | case dqb_mode: |
1ba585e8 | 13457 | case db_mode: |
3f31e633 JB |
13458 | oappend ("BYTE PTR "); |
13459 | break; | |
13460 | case w_mode: | |
1ba585e8 | 13461 | case dw_mode: |
3f31e633 JB |
13462 | case dqw_mode: |
13463 | oappend ("WORD PTR "); | |
13464 | break; | |
07f5af7d L |
13465 | case indir_v_mode: |
13466 | if (address_mode == mode_64bit && isa64 == intel64) | |
13467 | { | |
13468 | oappend ("QWORD PTR "); | |
13469 | break; | |
13470 | } | |
1a0670f3 | 13471 | /* Fall through. */ |
1a114b12 | 13472 | case stack_v_mode: |
7bb15c6f | 13473 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
13474 | { |
13475 | oappend ("QWORD PTR "); | |
3f31e633 JB |
13476 | break; |
13477 | } | |
1a0670f3 | 13478 | /* Fall through. */ |
3f31e633 | 13479 | case v_mode: |
b6169b20 | 13480 | case v_swap_mode: |
3f31e633 | 13481 | case dq_mode: |
161a04f6 L |
13482 | USED_REX (REX_W); |
13483 | if (rex & REX_W) | |
3f31e633 | 13484 | oappend ("QWORD PTR "); |
3f31e633 | 13485 | else |
f16cd0d5 L |
13486 | { |
13487 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
13488 | oappend ("DWORD PTR "); | |
13489 | else | |
13490 | oappend ("WORD PTR "); | |
13491 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13492 | } | |
3f31e633 | 13493 | break; |
52fd6d94 | 13494 | case z_mode: |
161a04f6 | 13495 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
13496 | *obufp++ = 'D'; |
13497 | oappend ("WORD PTR "); | |
161a04f6 | 13498 | if (!(rex & REX_W)) |
52fd6d94 JB |
13499 | used_prefixes |= (prefixes & PREFIX_DATA); |
13500 | break; | |
34b772a6 JB |
13501 | case a_mode: |
13502 | if (sizeflag & DFLAG) | |
13503 | oappend ("QWORD PTR "); | |
13504 | else | |
13505 | oappend ("DWORD PTR "); | |
13506 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13507 | break; | |
bc31405e L |
13508 | case movsxd_mode: |
13509 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
13510 | oappend ("WORD PTR "); | |
13511 | else | |
13512 | oappend ("DWORD PTR "); | |
13513 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13514 | break; | |
3f31e633 | 13515 | case d_mode: |
539f890d L |
13516 | case d_scalar_mode: |
13517 | case d_scalar_swap_mode: | |
fa99fab2 | 13518 | case d_swap_mode: |
42903f7f | 13519 | case dqd_mode: |
3f31e633 JB |
13520 | oappend ("DWORD PTR "); |
13521 | break; | |
13522 | case q_mode: | |
539f890d L |
13523 | case q_scalar_mode: |
13524 | case q_scalar_swap_mode: | |
b6169b20 | 13525 | case q_swap_mode: |
3f31e633 JB |
13526 | oappend ("QWORD PTR "); |
13527 | break; | |
13528 | case m_mode: | |
cb712a9e | 13529 | if (address_mode == mode_64bit) |
3f31e633 JB |
13530 | oappend ("QWORD PTR "); |
13531 | else | |
13532 | oappend ("DWORD PTR "); | |
13533 | break; | |
13534 | case f_mode: | |
13535 | if (sizeflag & DFLAG) | |
13536 | oappend ("FWORD PTR "); | |
13537 | else | |
13538 | oappend ("DWORD PTR "); | |
13539 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13540 | break; | |
13541 | case t_mode: | |
13542 | oappend ("TBYTE PTR "); | |
13543 | break; | |
13544 | case x_mode: | |
b6169b20 | 13545 | case x_swap_mode: |
43234a1e L |
13546 | case evex_x_gscat_mode: |
13547 | case evex_x_nobcst_mode: | |
53467f57 IT |
13548 | case b_scalar_mode: |
13549 | case w_scalar_mode: | |
c0f3af97 L |
13550 | if (need_vex) |
13551 | { | |
13552 | switch (vex.length) | |
13553 | { | |
13554 | case 128: | |
13555 | oappend ("XMMWORD PTR "); | |
13556 | break; | |
13557 | case 256: | |
13558 | oappend ("YMMWORD PTR "); | |
13559 | break; | |
43234a1e L |
13560 | case 512: |
13561 | oappend ("ZMMWORD PTR "); | |
13562 | break; | |
c0f3af97 L |
13563 | default: |
13564 | abort (); | |
13565 | } | |
13566 | } | |
13567 | else | |
13568 | oappend ("XMMWORD PTR "); | |
13569 | break; | |
13570 | case xmm_mode: | |
3f31e633 JB |
13571 | oappend ("XMMWORD PTR "); |
13572 | break; | |
43234a1e L |
13573 | case ymm_mode: |
13574 | oappend ("YMMWORD PTR "); | |
13575 | break; | |
c0f3af97 | 13576 | case xmmq_mode: |
43234a1e | 13577 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
13578 | if (!need_vex) |
13579 | abort (); | |
13580 | ||
13581 | switch (vex.length) | |
13582 | { | |
13583 | case 128: | |
13584 | oappend ("QWORD PTR "); | |
13585 | break; | |
13586 | case 256: | |
13587 | oappend ("XMMWORD PTR "); | |
13588 | break; | |
43234a1e L |
13589 | case 512: |
13590 | oappend ("YMMWORD PTR "); | |
13591 | break; | |
c0f3af97 L |
13592 | default: |
13593 | abort (); | |
13594 | } | |
13595 | break; | |
6c30d220 L |
13596 | case xmm_mb_mode: |
13597 | if (!need_vex) | |
13598 | abort (); | |
13599 | ||
13600 | switch (vex.length) | |
13601 | { | |
13602 | case 128: | |
13603 | case 256: | |
43234a1e | 13604 | case 512: |
6c30d220 L |
13605 | oappend ("BYTE PTR "); |
13606 | break; | |
13607 | default: | |
13608 | abort (); | |
13609 | } | |
13610 | break; | |
13611 | case xmm_mw_mode: | |
13612 | if (!need_vex) | |
13613 | abort (); | |
13614 | ||
13615 | switch (vex.length) | |
13616 | { | |
13617 | case 128: | |
13618 | case 256: | |
43234a1e | 13619 | case 512: |
6c30d220 L |
13620 | oappend ("WORD PTR "); |
13621 | break; | |
13622 | default: | |
13623 | abort (); | |
13624 | } | |
13625 | break; | |
13626 | case xmm_md_mode: | |
13627 | if (!need_vex) | |
13628 | abort (); | |
13629 | ||
13630 | switch (vex.length) | |
13631 | { | |
13632 | case 128: | |
13633 | case 256: | |
43234a1e | 13634 | case 512: |
6c30d220 L |
13635 | oappend ("DWORD PTR "); |
13636 | break; | |
13637 | default: | |
13638 | abort (); | |
13639 | } | |
13640 | break; | |
13641 | case xmm_mq_mode: | |
13642 | if (!need_vex) | |
13643 | abort (); | |
13644 | ||
13645 | switch (vex.length) | |
13646 | { | |
13647 | case 128: | |
13648 | case 256: | |
43234a1e | 13649 | case 512: |
6c30d220 L |
13650 | oappend ("QWORD PTR "); |
13651 | break; | |
13652 | default: | |
13653 | abort (); | |
13654 | } | |
13655 | break; | |
13656 | case xmmdw_mode: | |
13657 | if (!need_vex) | |
13658 | abort (); | |
13659 | ||
13660 | switch (vex.length) | |
13661 | { | |
13662 | case 128: | |
13663 | oappend ("WORD PTR "); | |
13664 | break; | |
13665 | case 256: | |
13666 | oappend ("DWORD PTR "); | |
13667 | break; | |
43234a1e L |
13668 | case 512: |
13669 | oappend ("QWORD PTR "); | |
13670 | break; | |
6c30d220 L |
13671 | default: |
13672 | abort (); | |
13673 | } | |
13674 | break; | |
13675 | case xmmqd_mode: | |
13676 | if (!need_vex) | |
13677 | abort (); | |
13678 | ||
13679 | switch (vex.length) | |
13680 | { | |
13681 | case 128: | |
13682 | oappend ("DWORD PTR "); | |
13683 | break; | |
13684 | case 256: | |
13685 | oappend ("QWORD PTR "); | |
13686 | break; | |
43234a1e L |
13687 | case 512: |
13688 | oappend ("XMMWORD PTR "); | |
13689 | break; | |
6c30d220 L |
13690 | default: |
13691 | abort (); | |
13692 | } | |
13693 | break; | |
c0f3af97 L |
13694 | case ymmq_mode: |
13695 | if (!need_vex) | |
13696 | abort (); | |
13697 | ||
13698 | switch (vex.length) | |
13699 | { | |
13700 | case 128: | |
13701 | oappend ("QWORD PTR "); | |
13702 | break; | |
13703 | case 256: | |
13704 | oappend ("YMMWORD PTR "); | |
13705 | break; | |
43234a1e L |
13706 | case 512: |
13707 | oappend ("ZMMWORD PTR "); | |
13708 | break; | |
c0f3af97 L |
13709 | default: |
13710 | abort (); | |
13711 | } | |
13712 | break; | |
6c30d220 L |
13713 | case ymmxmm_mode: |
13714 | if (!need_vex) | |
13715 | abort (); | |
13716 | ||
13717 | switch (vex.length) | |
13718 | { | |
13719 | case 128: | |
13720 | case 256: | |
13721 | oappend ("XMMWORD PTR "); | |
13722 | break; | |
13723 | default: | |
13724 | abort (); | |
13725 | } | |
13726 | break; | |
fb9c77c7 L |
13727 | case o_mode: |
13728 | oappend ("OWORD PTR "); | |
13729 | break; | |
1c480963 | 13730 | case vex_scalar_w_dq_mode: |
0bfee649 L |
13731 | if (!need_vex) |
13732 | abort (); | |
13733 | ||
13734 | if (vex.w) | |
13735 | oappend ("QWORD PTR "); | |
13736 | else | |
13737 | oappend ("DWORD PTR "); | |
13738 | break; | |
43234a1e L |
13739 | case vex_vsib_d_w_dq_mode: |
13740 | case vex_vsib_q_w_dq_mode: | |
13741 | if (!need_vex) | |
13742 | abort (); | |
13743 | ||
13744 | if (!vex.evex) | |
13745 | { | |
13746 | if (vex.w) | |
13747 | oappend ("QWORD PTR "); | |
13748 | else | |
13749 | oappend ("DWORD PTR "); | |
13750 | } | |
13751 | else | |
13752 | { | |
b28d1bda IT |
13753 | switch (vex.length) |
13754 | { | |
13755 | case 128: | |
13756 | oappend ("XMMWORD PTR "); | |
13757 | break; | |
13758 | case 256: | |
13759 | oappend ("YMMWORD PTR "); | |
13760 | break; | |
13761 | case 512: | |
13762 | oappend ("ZMMWORD PTR "); | |
13763 | break; | |
13764 | default: | |
13765 | abort (); | |
13766 | } | |
43234a1e L |
13767 | } |
13768 | break; | |
5fc35d96 IT |
13769 | case vex_vsib_q_w_d_mode: |
13770 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 13771 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
13772 | abort (); |
13773 | ||
b28d1bda IT |
13774 | switch (vex.length) |
13775 | { | |
13776 | case 128: | |
13777 | oappend ("QWORD PTR "); | |
13778 | break; | |
13779 | case 256: | |
13780 | oappend ("XMMWORD PTR "); | |
13781 | break; | |
13782 | case 512: | |
13783 | oappend ("YMMWORD PTR "); | |
13784 | break; | |
13785 | default: | |
13786 | abort (); | |
13787 | } | |
5fc35d96 IT |
13788 | |
13789 | break; | |
1ba585e8 IT |
13790 | case mask_bd_mode: |
13791 | if (!need_vex || vex.length != 128) | |
13792 | abort (); | |
13793 | if (vex.w) | |
13794 | oappend ("DWORD PTR "); | |
13795 | else | |
13796 | oappend ("BYTE PTR "); | |
13797 | break; | |
43234a1e L |
13798 | case mask_mode: |
13799 | if (!need_vex) | |
13800 | abort (); | |
1ba585e8 IT |
13801 | if (vex.w) |
13802 | oappend ("QWORD PTR "); | |
13803 | else | |
13804 | oappend ("WORD PTR "); | |
43234a1e | 13805 | break; |
6c75cc62 | 13806 | case v_bnd_mode: |
d276ec69 | 13807 | case v_bndmk_mode: |
3f31e633 JB |
13808 | default: |
13809 | break; | |
13810 | } | |
13811 | } | |
13812 | ||
252b5132 | 13813 | static void |
c0f3af97 | 13814 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 13815 | { |
c0f3af97 L |
13816 | int reg = modrm.rm; |
13817 | const char **names; | |
252b5132 | 13818 | |
c0f3af97 L |
13819 | USED_REX (REX_B); |
13820 | if ((rex & REX_B)) | |
13821 | reg += 8; | |
252b5132 | 13822 | |
b6169b20 | 13823 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 | 13824 | && (bytemode == b_swap_mode |
9f79e886 | 13825 | || bytemode == bnd_swap_mode |
60227d64 | 13826 | || bytemode == v_swap_mode)) |
b6169b20 L |
13827 | swap_operand (); |
13828 | ||
c0f3af97 | 13829 | switch (bytemode) |
252b5132 | 13830 | { |
c0f3af97 | 13831 | case b_mode: |
b6169b20 | 13832 | case b_swap_mode: |
c0f3af97 L |
13833 | USED_REX (0); |
13834 | if (rex) | |
13835 | names = names8rex; | |
13836 | else | |
13837 | names = names8; | |
13838 | break; | |
13839 | case w_mode: | |
13840 | names = names16; | |
13841 | break; | |
13842 | case d_mode: | |
1ba585e8 IT |
13843 | case dw_mode: |
13844 | case db_mode: | |
c0f3af97 L |
13845 | names = names32; |
13846 | break; | |
13847 | case q_mode: | |
13848 | names = names64; | |
13849 | break; | |
13850 | case m_mode: | |
6c75cc62 | 13851 | case v_bnd_mode: |
c0f3af97 L |
13852 | names = address_mode == mode_64bit ? names64 : names32; |
13853 | break; | |
7e8b059b | 13854 | case bnd_mode: |
9f79e886 | 13855 | case bnd_swap_mode: |
0d96e4df L |
13856 | if (reg > 0x3) |
13857 | { | |
13858 | oappend ("(bad)"); | |
13859 | return; | |
13860 | } | |
7e8b059b L |
13861 | names = names_bnd; |
13862 | break; | |
07f5af7d L |
13863 | case indir_v_mode: |
13864 | if (address_mode == mode_64bit && isa64 == intel64) | |
13865 | { | |
13866 | names = names64; | |
13867 | break; | |
13868 | } | |
1a0670f3 | 13869 | /* Fall through. */ |
c0f3af97 | 13870 | case stack_v_mode: |
7bb15c6f | 13871 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 13872 | { |
c0f3af97 | 13873 | names = names64; |
252b5132 | 13874 | break; |
252b5132 | 13875 | } |
c0f3af97 | 13876 | bytemode = v_mode; |
1a0670f3 | 13877 | /* Fall through. */ |
c0f3af97 | 13878 | case v_mode: |
b6169b20 | 13879 | case v_swap_mode: |
c0f3af97 L |
13880 | case dq_mode: |
13881 | case dqb_mode: | |
13882 | case dqd_mode: | |
13883 | case dqw_mode: | |
13884 | USED_REX (REX_W); | |
13885 | if (rex & REX_W) | |
13886 | names = names64; | |
c0f3af97 | 13887 | else |
f16cd0d5 | 13888 | { |
7bb15c6f | 13889 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
13890 | || (bytemode != v_mode |
13891 | && bytemode != v_swap_mode)) | |
13892 | names = names32; | |
13893 | else | |
13894 | names = names16; | |
13895 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13896 | } | |
c0f3af97 | 13897 | break; |
bc31405e L |
13898 | case movsxd_mode: |
13899 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
13900 | names = names16; | |
13901 | else | |
13902 | names = names32; | |
13903 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13904 | break; | |
de89d0a3 IT |
13905 | case va_mode: |
13906 | names = (address_mode == mode_64bit | |
13907 | ? names64 : names32); | |
13908 | if (!(prefixes & PREFIX_ADDR)) | |
aa178437 IT |
13909 | names = (address_mode == mode_16bit |
13910 | ? names16 : names); | |
de89d0a3 IT |
13911 | else |
13912 | { | |
13913 | /* Remove "addr16/addr32". */ | |
13914 | all_prefixes[last_addr_prefix] = 0; | |
13915 | names = (address_mode != mode_32bit | |
13916 | ? names32 : names16); | |
13917 | used_prefixes |= PREFIX_ADDR; | |
13918 | } | |
13919 | break; | |
1ba585e8 | 13920 | case mask_bd_mode: |
43234a1e | 13921 | case mask_mode: |
9889cbb1 L |
13922 | if (reg > 0x7) |
13923 | { | |
13924 | oappend ("(bad)"); | |
13925 | return; | |
13926 | } | |
43234a1e L |
13927 | names = names_mask; |
13928 | break; | |
c0f3af97 L |
13929 | case 0: |
13930 | return; | |
13931 | default: | |
13932 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
13933 | return; |
13934 | } | |
c0f3af97 L |
13935 | oappend (names[reg]); |
13936 | } | |
13937 | ||
13938 | static void | |
c1e679ec | 13939 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
13940 | { |
13941 | bfd_vma disp = 0; | |
13942 | int add = (rex & REX_B) ? 8 : 0; | |
13943 | int riprel = 0; | |
43234a1e L |
13944 | int shift; |
13945 | ||
13946 | if (vex.evex) | |
13947 | { | |
13948 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
13949 | if (vex.b | |
13950 | && bytemode != x_mode | |
90a915bf | 13951 | && bytemode != xmmq_mode |
43234a1e L |
13952 | && bytemode != evex_half_bcst_xmmq_mode) |
13953 | { | |
13954 | BadOp (); | |
13955 | return; | |
13956 | } | |
13957 | switch (bytemode) | |
13958 | { | |
1ba585e8 IT |
13959 | case dqw_mode: |
13960 | case dw_mode: | |
1ba585e8 IT |
13961 | shift = 1; |
13962 | break; | |
13963 | case dqb_mode: | |
13964 | case db_mode: | |
13965 | shift = 0; | |
13966 | break; | |
b50c9f31 JB |
13967 | case dq_mode: |
13968 | if (address_mode != mode_64bit) | |
13969 | { | |
13970 | shift = 2; | |
13971 | break; | |
13972 | } | |
13973 | /* fall through */ | |
4102be5c | 13974 | case vex_scalar_w_dq_mode: |
43234a1e | 13975 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 13976 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 13977 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 13978 | case vex_vsib_q_w_d_mode: |
43234a1e | 13979 | case evex_x_gscat_mode: |
43234a1e L |
13980 | shift = vex.w ? 3 : 2; |
13981 | break; | |
43234a1e L |
13982 | case x_mode: |
13983 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 13984 | case xmmq_mode: |
43234a1e L |
13985 | if (vex.b) |
13986 | { | |
13987 | shift = vex.w ? 3 : 2; | |
13988 | break; | |
13989 | } | |
1a0670f3 | 13990 | /* Fall through. */ |
43234a1e L |
13991 | case xmmqd_mode: |
13992 | case xmmdw_mode: | |
43234a1e L |
13993 | case ymmq_mode: |
13994 | case evex_x_nobcst_mode: | |
13995 | case x_swap_mode: | |
13996 | switch (vex.length) | |
13997 | { | |
13998 | case 128: | |
13999 | shift = 4; | |
14000 | break; | |
14001 | case 256: | |
14002 | shift = 5; | |
14003 | break; | |
14004 | case 512: | |
14005 | shift = 6; | |
14006 | break; | |
14007 | default: | |
14008 | abort (); | |
14009 | } | |
14010 | break; | |
14011 | case ymm_mode: | |
14012 | shift = 5; | |
14013 | break; | |
14014 | case xmm_mode: | |
14015 | shift = 4; | |
14016 | break; | |
14017 | case xmm_mq_mode: | |
14018 | case q_mode: | |
14019 | case q_scalar_mode: | |
14020 | case q_swap_mode: | |
14021 | case q_scalar_swap_mode: | |
14022 | shift = 3; | |
14023 | break; | |
14024 | case dqd_mode: | |
14025 | case xmm_md_mode: | |
14026 | case d_mode: | |
14027 | case d_scalar_mode: | |
14028 | case d_swap_mode: | |
14029 | case d_scalar_swap_mode: | |
14030 | shift = 2; | |
14031 | break; | |
5074ad8a | 14032 | case w_scalar_mode: |
43234a1e L |
14033 | case xmm_mw_mode: |
14034 | shift = 1; | |
14035 | break; | |
5074ad8a | 14036 | case b_scalar_mode: |
43234a1e L |
14037 | case xmm_mb_mode: |
14038 | shift = 0; | |
14039 | break; | |
14040 | default: | |
14041 | abort (); | |
14042 | } | |
14043 | /* Make necessary corrections to shift for modes that need it. | |
14044 | For these modes we currently have shift 4, 5 or 6 depending on | |
14045 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
14046 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
14047 | xmmq_mode). In case of broadcast enabled the corrections | |
14048 | aren't needed, as element size is always 32 or 64 bits. */ | |
90a915bf IT |
14049 | if (!vex.b |
14050 | && (bytemode == xmmq_mode | |
14051 | || bytemode == evex_half_bcst_xmmq_mode)) | |
43234a1e L |
14052 | shift -= 1; |
14053 | else if (bytemode == xmmqd_mode) | |
14054 | shift -= 2; | |
14055 | else if (bytemode == xmmdw_mode) | |
14056 | shift -= 3; | |
b28d1bda IT |
14057 | else if (bytemode == ymmq_mode && vex.length == 128) |
14058 | shift -= 1; | |
43234a1e L |
14059 | } |
14060 | else | |
14061 | shift = 0; | |
252b5132 | 14062 | |
c0f3af97 | 14063 | USED_REX (REX_B); |
3f31e633 JB |
14064 | if (intel_syntax) |
14065 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
14066 | append_seg (); |
14067 | ||
5d669648 | 14068 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 14069 | { |
5d669648 L |
14070 | /* 32/64 bit address mode */ |
14071 | int havedisp; | |
252b5132 RH |
14072 | int havesib; |
14073 | int havebase; | |
0f7da397 | 14074 | int haveindex; |
20afcfb7 | 14075 | int needindex; |
1bc60e56 | 14076 | int needaddr32; |
82c18208 | 14077 | int base, rbase; |
91d6fa6a | 14078 | int vindex = 0; |
252b5132 | 14079 | int scale = 0; |
7e8b059b L |
14080 | int addr32flag = !((sizeflag & AFLAG) |
14081 | || bytemode == v_bnd_mode | |
d276ec69 | 14082 | || bytemode == v_bndmk_mode |
9f79e886 JB |
14083 | || bytemode == bnd_mode |
14084 | || bytemode == bnd_swap_mode); | |
6c30d220 L |
14085 | const char **indexes64 = names64; |
14086 | const char **indexes32 = names32; | |
252b5132 RH |
14087 | |
14088 | havesib = 0; | |
14089 | havebase = 1; | |
0f7da397 | 14090 | haveindex = 0; |
7967e09e | 14091 | base = modrm.rm; |
252b5132 RH |
14092 | |
14093 | if (base == 4) | |
14094 | { | |
14095 | havesib = 1; | |
dfc8cf43 | 14096 | vindex = sib.index; |
161a04f6 L |
14097 | USED_REX (REX_X); |
14098 | if (rex & REX_X) | |
91d6fa6a | 14099 | vindex += 8; |
6c30d220 L |
14100 | switch (bytemode) |
14101 | { | |
14102 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 14103 | case vex_vsib_d_w_d_mode: |
6c30d220 | 14104 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 14105 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
14106 | if (!need_vex) |
14107 | abort (); | |
43234a1e L |
14108 | if (vex.evex) |
14109 | { | |
14110 | if (!vex.v) | |
14111 | vindex += 16; | |
14112 | } | |
6c30d220 L |
14113 | |
14114 | haveindex = 1; | |
14115 | switch (vex.length) | |
14116 | { | |
14117 | case 128: | |
7bb15c6f | 14118 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
14119 | break; |
14120 | case 256: | |
5fc35d96 IT |
14121 | if (!vex.w |
14122 | || bytemode == vex_vsib_q_w_dq_mode | |
14123 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 14124 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 14125 | else |
7bb15c6f | 14126 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 14127 | break; |
43234a1e | 14128 | case 512: |
5fc35d96 IT |
14129 | if (!vex.w |
14130 | || bytemode == vex_vsib_q_w_dq_mode | |
14131 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
14132 | indexes64 = indexes32 = names_zmm; |
14133 | else | |
14134 | indexes64 = indexes32 = names_ymm; | |
14135 | break; | |
6c30d220 L |
14136 | default: |
14137 | abort (); | |
14138 | } | |
14139 | break; | |
14140 | default: | |
14141 | haveindex = vindex != 4; | |
14142 | break; | |
14143 | } | |
14144 | scale = sib.scale; | |
14145 | base = sib.base; | |
252b5132 RH |
14146 | codep++; |
14147 | } | |
82c18208 | 14148 | rbase = base + add; |
252b5132 | 14149 | |
7967e09e | 14150 | switch (modrm.mod) |
252b5132 RH |
14151 | { |
14152 | case 0: | |
82c18208 | 14153 | if (base == 5) |
252b5132 RH |
14154 | { |
14155 | havebase = 0; | |
cb712a9e | 14156 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
14157 | riprel = 1; |
14158 | disp = get32s (); | |
d276ec69 JB |
14159 | if (riprel && bytemode == v_bndmk_mode) |
14160 | { | |
14161 | oappend ("(bad)"); | |
14162 | return; | |
14163 | } | |
252b5132 RH |
14164 | } |
14165 | break; | |
14166 | case 1: | |
14167 | FETCH_DATA (the_info, codep + 1); | |
14168 | disp = *codep++; | |
14169 | if ((disp & 0x80) != 0) | |
14170 | disp -= 0x100; | |
43234a1e L |
14171 | if (vex.evex && shift > 0) |
14172 | disp <<= shift; | |
252b5132 RH |
14173 | break; |
14174 | case 2: | |
52b15da3 | 14175 | disp = get32s (); |
252b5132 RH |
14176 | break; |
14177 | } | |
14178 | ||
1bc60e56 L |
14179 | needindex = 0; |
14180 | needaddr32 = 0; | |
14181 | if (havesib | |
14182 | && !havebase | |
14183 | && !haveindex | |
14184 | && address_mode != mode_16bit) | |
14185 | { | |
14186 | if (address_mode == mode_64bit) | |
14187 | { | |
14188 | /* Display eiz instead of addr32. */ | |
14189 | needindex = addr32flag; | |
14190 | needaddr32 = 1; | |
14191 | } | |
14192 | else | |
14193 | { | |
14194 | /* In 32-bit mode, we need index register to tell [offset] | |
14195 | from [eiz*1 + offset]. */ | |
14196 | needindex = 1; | |
14197 | } | |
14198 | } | |
14199 | ||
20afcfb7 L |
14200 | havedisp = (havebase |
14201 | || needindex | |
14202 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 14203 | |
252b5132 | 14204 | if (!intel_syntax) |
82c18208 | 14205 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14206 | { |
5d669648 L |
14207 | if (havedisp || riprel) |
14208 | print_displacement (scratchbuf, disp); | |
14209 | else | |
14210 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 14211 | oappend (scratchbuf); |
52b15da3 JH |
14212 | if (riprel) |
14213 | { | |
14214 | set_op (disp, 1); | |
28596323 | 14215 | oappend (!addr32flag ? "(%rip)" : "(%eip)"); |
52b15da3 | 14216 | } |
db6eb5be | 14217 | } |
2da11e11 | 14218 | |
c1dc7af5 | 14219 | if ((havebase || haveindex || needindex || needaddr32 || riprel) |
a23b33b3 JB |
14220 | && (address_mode != mode_64bit |
14221 | || ((bytemode != v_bnd_mode) | |
14222 | && (bytemode != v_bndmk_mode) | |
14223 | && (bytemode != bnd_mode) | |
14224 | && (bytemode != bnd_swap_mode)))) | |
87767711 JB |
14225 | used_prefixes |= PREFIX_ADDR; |
14226 | ||
5d669648 | 14227 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 14228 | { |
252b5132 | 14229 | *obufp++ = open_char; |
52b15da3 | 14230 | if (intel_syntax && riprel) |
185b1163 L |
14231 | { |
14232 | set_op (disp, 1); | |
28596323 | 14233 | oappend (!addr32flag ? "rip" : "eip"); |
185b1163 | 14234 | } |
db6eb5be | 14235 | *obufp = '\0'; |
252b5132 | 14236 | if (havebase) |
7e8b059b | 14237 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 14238 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
14239 | if (havesib) |
14240 | { | |
db51cc60 L |
14241 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
14242 | print index to tell base + index from base. */ | |
14243 | if (scale != 0 | |
20afcfb7 | 14244 | || needindex |
db51cc60 L |
14245 | || haveindex |
14246 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 14247 | { |
9306ca4a | 14248 | if (!intel_syntax || havebase) |
db6eb5be | 14249 | { |
9306ca4a JB |
14250 | *obufp++ = separator_char; |
14251 | *obufp = '\0'; | |
db6eb5be | 14252 | } |
db51cc60 | 14253 | if (haveindex) |
7e8b059b | 14254 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 14255 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 14256 | else |
7e8b059b | 14257 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
14258 | ? index64 : index32); |
14259 | ||
db6eb5be AM |
14260 | *obufp++ = scale_char; |
14261 | *obufp = '\0'; | |
14262 | sprintf (scratchbuf, "%d", 1 << scale); | |
14263 | oappend (scratchbuf); | |
14264 | } | |
252b5132 | 14265 | } |
185b1163 | 14266 | if (intel_syntax |
82c18208 | 14267 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 14268 | { |
db51cc60 | 14269 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14270 | { |
14271 | *obufp++ = '+'; | |
14272 | *obufp = '\0'; | |
14273 | } | |
05203043 | 14274 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
14275 | { |
14276 | *obufp++ = '-'; | |
14277 | *obufp = '\0'; | |
14278 | disp = - (bfd_signed_vma) disp; | |
14279 | } | |
14280 | ||
db51cc60 L |
14281 | if (havedisp) |
14282 | print_displacement (scratchbuf, disp); | |
14283 | else | |
14284 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
14285 | oappend (scratchbuf); |
14286 | } | |
252b5132 RH |
14287 | |
14288 | *obufp++ = close_char; | |
db6eb5be | 14289 | *obufp = '\0'; |
252b5132 RH |
14290 | } |
14291 | else if (intel_syntax) | |
db6eb5be | 14292 | { |
82c18208 | 14293 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14294 | { |
285ca992 | 14295 | if (!active_seg_prefix) |
252b5132 | 14296 | { |
d708bcba | 14297 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14298 | oappend (":"); |
14299 | } | |
52b15da3 | 14300 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
14301 | oappend (scratchbuf); |
14302 | } | |
14303 | } | |
252b5132 | 14304 | } |
a23b33b3 JB |
14305 | else if (bytemode == v_bnd_mode |
14306 | || bytemode == v_bndmk_mode | |
14307 | || bytemode == bnd_mode | |
14308 | || bytemode == bnd_swap_mode) | |
14309 | { | |
14310 | oappend ("(bad)"); | |
14311 | return; | |
14312 | } | |
252b5132 | 14313 | else |
f16cd0d5 L |
14314 | { |
14315 | /* 16 bit address mode */ | |
14316 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 14317 | switch (modrm.mod) |
252b5132 RH |
14318 | { |
14319 | case 0: | |
7967e09e | 14320 | if (modrm.rm == 6) |
252b5132 RH |
14321 | { |
14322 | disp = get16 (); | |
14323 | if ((disp & 0x8000) != 0) | |
14324 | disp -= 0x10000; | |
14325 | } | |
14326 | break; | |
14327 | case 1: | |
14328 | FETCH_DATA (the_info, codep + 1); | |
14329 | disp = *codep++; | |
14330 | if ((disp & 0x80) != 0) | |
14331 | disp -= 0x100; | |
65f3ed04 JB |
14332 | if (vex.evex && shift > 0) |
14333 | disp <<= shift; | |
252b5132 RH |
14334 | break; |
14335 | case 2: | |
14336 | disp = get16 (); | |
14337 | if ((disp & 0x8000) != 0) | |
14338 | disp -= 0x10000; | |
14339 | break; | |
14340 | } | |
14341 | ||
14342 | if (!intel_syntax) | |
7967e09e | 14343 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 14344 | { |
5d669648 | 14345 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
14346 | oappend (scratchbuf); |
14347 | } | |
252b5132 | 14348 | |
7967e09e | 14349 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
14350 | { |
14351 | *obufp++ = open_char; | |
db6eb5be | 14352 | *obufp = '\0'; |
7967e09e | 14353 | oappend (index16[modrm.rm]); |
5d669648 L |
14354 | if (intel_syntax |
14355 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 14356 | { |
5d669648 | 14357 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14358 | { |
14359 | *obufp++ = '+'; | |
14360 | *obufp = '\0'; | |
14361 | } | |
7967e09e | 14362 | else if (modrm.mod != 1) |
3d456fa1 JB |
14363 | { |
14364 | *obufp++ = '-'; | |
14365 | *obufp = '\0'; | |
14366 | disp = - (bfd_signed_vma) disp; | |
14367 | } | |
14368 | ||
5d669648 | 14369 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
14370 | oappend (scratchbuf); |
14371 | } | |
14372 | ||
db6eb5be AM |
14373 | *obufp++ = close_char; |
14374 | *obufp = '\0'; | |
252b5132 | 14375 | } |
3d456fa1 JB |
14376 | else if (intel_syntax) |
14377 | { | |
285ca992 | 14378 | if (!active_seg_prefix) |
3d456fa1 JB |
14379 | { |
14380 | oappend (names_seg[ds_reg - es_reg]); | |
14381 | oappend (":"); | |
14382 | } | |
14383 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
14384 | oappend (scratchbuf); | |
14385 | } | |
252b5132 | 14386 | } |
43234a1e L |
14387 | if (vex.evex && vex.b |
14388 | && (bytemode == x_mode | |
90a915bf | 14389 | || bytemode == xmmq_mode |
43234a1e L |
14390 | || bytemode == evex_half_bcst_xmmq_mode)) |
14391 | { | |
90a915bf IT |
14392 | if (vex.w |
14393 | || bytemode == xmmq_mode | |
14394 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
14395 | { |
14396 | switch (vex.length) | |
14397 | { | |
14398 | case 128: | |
14399 | oappend ("{1to2}"); | |
14400 | break; | |
14401 | case 256: | |
14402 | oappend ("{1to4}"); | |
14403 | break; | |
14404 | case 512: | |
14405 | oappend ("{1to8}"); | |
14406 | break; | |
14407 | default: | |
14408 | abort (); | |
14409 | } | |
14410 | } | |
43234a1e | 14411 | else |
b28d1bda IT |
14412 | { |
14413 | switch (vex.length) | |
14414 | { | |
14415 | case 128: | |
14416 | oappend ("{1to4}"); | |
14417 | break; | |
14418 | case 256: | |
14419 | oappend ("{1to8}"); | |
14420 | break; | |
14421 | case 512: | |
14422 | oappend ("{1to16}"); | |
14423 | break; | |
14424 | default: | |
14425 | abort (); | |
14426 | } | |
14427 | } | |
43234a1e | 14428 | } |
252b5132 RH |
14429 | } |
14430 | ||
c0f3af97 | 14431 | static void |
8b3f93e7 | 14432 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
14433 | { |
14434 | /* Skip mod/rm byte. */ | |
14435 | MODRM_CHECK; | |
14436 | codep++; | |
14437 | ||
14438 | if (modrm.mod == 3) | |
14439 | OP_E_register (bytemode, sizeflag); | |
14440 | else | |
c1e679ec | 14441 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
14442 | } |
14443 | ||
252b5132 | 14444 | static void |
26ca5450 | 14445 | OP_G (int bytemode, int sizeflag) |
252b5132 | 14446 | { |
52b15da3 | 14447 | int add = 0; |
c0a30a9f | 14448 | const char **names; |
161a04f6 L |
14449 | USED_REX (REX_R); |
14450 | if (rex & REX_R) | |
52b15da3 | 14451 | add += 8; |
252b5132 RH |
14452 | switch (bytemode) |
14453 | { | |
14454 | case b_mode: | |
52b15da3 JH |
14455 | USED_REX (0); |
14456 | if (rex) | |
7967e09e | 14457 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 14458 | else |
7967e09e | 14459 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
14460 | break; |
14461 | case w_mode: | |
7967e09e | 14462 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
14463 | break; |
14464 | case d_mode: | |
1ba585e8 IT |
14465 | case db_mode: |
14466 | case dw_mode: | |
7967e09e | 14467 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
14468 | break; |
14469 | case q_mode: | |
7967e09e | 14470 | oappend (names64[modrm.reg + add]); |
252b5132 | 14471 | break; |
7e8b059b | 14472 | case bnd_mode: |
0d96e4df L |
14473 | if (modrm.reg > 0x3) |
14474 | { | |
14475 | oappend ("(bad)"); | |
14476 | return; | |
14477 | } | |
7e8b059b L |
14478 | oappend (names_bnd[modrm.reg]); |
14479 | break; | |
252b5132 | 14480 | case v_mode: |
9306ca4a | 14481 | case dq_mode: |
42903f7f L |
14482 | case dqb_mode: |
14483 | case dqd_mode: | |
9306ca4a | 14484 | case dqw_mode: |
bc31405e | 14485 | case movsxd_mode: |
161a04f6 L |
14486 | USED_REX (REX_W); |
14487 | if (rex & REX_W) | |
7967e09e | 14488 | oappend (names64[modrm.reg + add]); |
252b5132 | 14489 | else |
f16cd0d5 | 14490 | { |
bc31405e L |
14491 | if ((sizeflag & DFLAG) |
14492 | || (bytemode != v_mode && bytemode != movsxd_mode)) | |
f16cd0d5 L |
14493 | oappend (names32[modrm.reg + add]); |
14494 | else | |
14495 | oappend (names16[modrm.reg + add]); | |
14496 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14497 | } | |
252b5132 | 14498 | break; |
c0a30a9f L |
14499 | case va_mode: |
14500 | names = (address_mode == mode_64bit | |
14501 | ? names64 : names32); | |
14502 | if (!(prefixes & PREFIX_ADDR)) | |
14503 | { | |
14504 | if (address_mode == mode_16bit) | |
14505 | names = names16; | |
14506 | } | |
14507 | else | |
14508 | { | |
14509 | /* Remove "addr16/addr32". */ | |
14510 | all_prefixes[last_addr_prefix] = 0; | |
14511 | names = (address_mode != mode_32bit | |
14512 | ? names32 : names16); | |
14513 | used_prefixes |= PREFIX_ADDR; | |
14514 | } | |
14515 | oappend (names[modrm.reg + add]); | |
14516 | break; | |
90700ea2 | 14517 | case m_mode: |
cb712a9e | 14518 | if (address_mode == mode_64bit) |
7967e09e | 14519 | oappend (names64[modrm.reg + add]); |
90700ea2 | 14520 | else |
7967e09e | 14521 | oappend (names32[modrm.reg + add]); |
90700ea2 | 14522 | break; |
1ba585e8 | 14523 | case mask_bd_mode: |
43234a1e | 14524 | case mask_mode: |
9889cbb1 L |
14525 | if ((modrm.reg + add) > 0x7) |
14526 | { | |
14527 | oappend ("(bad)"); | |
14528 | return; | |
14529 | } | |
43234a1e L |
14530 | oappend (names_mask[modrm.reg + add]); |
14531 | break; | |
252b5132 RH |
14532 | default: |
14533 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14534 | break; | |
14535 | } | |
14536 | } | |
14537 | ||
52b15da3 | 14538 | static bfd_vma |
26ca5450 | 14539 | get64 (void) |
52b15da3 | 14540 | { |
5dd0794d | 14541 | bfd_vma x; |
52b15da3 | 14542 | #ifdef BFD64 |
5dd0794d AM |
14543 | unsigned int a; |
14544 | unsigned int b; | |
14545 | ||
52b15da3 JH |
14546 | FETCH_DATA (the_info, codep + 8); |
14547 | a = *codep++ & 0xff; | |
14548 | a |= (*codep++ & 0xff) << 8; | |
14549 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 14550 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 14551 | b = *codep++ & 0xff; |
52b15da3 JH |
14552 | b |= (*codep++ & 0xff) << 8; |
14553 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 14554 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
14555 | x = a + ((bfd_vma) b << 32); |
14556 | #else | |
6608db57 | 14557 | abort (); |
5dd0794d | 14558 | x = 0; |
52b15da3 JH |
14559 | #endif |
14560 | return x; | |
14561 | } | |
14562 | ||
14563 | static bfd_signed_vma | |
26ca5450 | 14564 | get32 (void) |
252b5132 | 14565 | { |
52b15da3 | 14566 | bfd_signed_vma x = 0; |
252b5132 RH |
14567 | |
14568 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
14569 | x = *codep++ & (bfd_signed_vma) 0xff; |
14570 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14571 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14572 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14573 | return x; | |
14574 | } | |
14575 | ||
14576 | static bfd_signed_vma | |
26ca5450 | 14577 | get32s (void) |
52b15da3 JH |
14578 | { |
14579 | bfd_signed_vma x = 0; | |
14580 | ||
14581 | FETCH_DATA (the_info, codep + 4); | |
14582 | x = *codep++ & (bfd_signed_vma) 0xff; | |
14583 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14584 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14585 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14586 | ||
14587 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
14588 | ||
252b5132 RH |
14589 | return x; |
14590 | } | |
14591 | ||
14592 | static int | |
26ca5450 | 14593 | get16 (void) |
252b5132 RH |
14594 | { |
14595 | int x = 0; | |
14596 | ||
14597 | FETCH_DATA (the_info, codep + 2); | |
14598 | x = *codep++ & 0xff; | |
14599 | x |= (*codep++ & 0xff) << 8; | |
14600 | return x; | |
14601 | } | |
14602 | ||
14603 | static void | |
26ca5450 | 14604 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
14605 | { |
14606 | op_index[op_ad] = op_ad; | |
cb712a9e | 14607 | if (address_mode == mode_64bit) |
7081ff04 AJ |
14608 | { |
14609 | op_address[op_ad] = op; | |
14610 | op_riprel[op_ad] = riprel; | |
14611 | } | |
14612 | else | |
14613 | { | |
14614 | /* Mask to get a 32-bit address. */ | |
14615 | op_address[op_ad] = op & 0xffffffff; | |
14616 | op_riprel[op_ad] = riprel & 0xffffffff; | |
14617 | } | |
252b5132 RH |
14618 | } |
14619 | ||
14620 | static void | |
26ca5450 | 14621 | OP_REG (int code, int sizeflag) |
252b5132 | 14622 | { |
2da11e11 | 14623 | const char *s; |
9b60702d | 14624 | int add; |
de882298 RM |
14625 | |
14626 | switch (code) | |
14627 | { | |
14628 | case es_reg: case ss_reg: case cs_reg: | |
14629 | case ds_reg: case fs_reg: case gs_reg: | |
14630 | oappend (names_seg[code - es_reg]); | |
14631 | return; | |
14632 | } | |
14633 | ||
161a04f6 L |
14634 | USED_REX (REX_B); |
14635 | if (rex & REX_B) | |
52b15da3 | 14636 | add = 8; |
9b60702d L |
14637 | else |
14638 | add = 0; | |
52b15da3 JH |
14639 | |
14640 | switch (code) | |
14641 | { | |
52b15da3 JH |
14642 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
14643 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14644 | s = names16[code - ax_reg + add]; | |
14645 | break; | |
52b15da3 JH |
14646 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
14647 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
14648 | USED_REX (0); | |
14649 | if (rex) | |
14650 | s = names8rex[code - al_reg + add]; | |
14651 | else | |
14652 | s = names8[code - al_reg]; | |
14653 | break; | |
6439fc28 AM |
14654 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
14655 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 14656 | if (address_mode == mode_64bit |
6c067bbb | 14657 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
14658 | { |
14659 | s = names64[code - rAX_reg + add]; | |
14660 | break; | |
14661 | } | |
14662 | code += eAX_reg - rAX_reg; | |
6608db57 | 14663 | /* Fall through. */ |
52b15da3 JH |
14664 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
14665 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14666 | USED_REX (REX_W); |
14667 | if (rex & REX_W) | |
52b15da3 | 14668 | s = names64[code - eAX_reg + add]; |
52b15da3 | 14669 | else |
f16cd0d5 L |
14670 | { |
14671 | if (sizeflag & DFLAG) | |
14672 | s = names32[code - eAX_reg + add]; | |
14673 | else | |
14674 | s = names16[code - eAX_reg + add]; | |
14675 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14676 | } | |
52b15da3 | 14677 | break; |
52b15da3 JH |
14678 | default: |
14679 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14680 | break; | |
14681 | } | |
14682 | oappend (s); | |
14683 | } | |
14684 | ||
14685 | static void | |
26ca5450 | 14686 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
14687 | { |
14688 | const char *s; | |
252b5132 RH |
14689 | |
14690 | switch (code) | |
14691 | { | |
14692 | case indir_dx_reg: | |
d708bcba | 14693 | if (intel_syntax) |
52fd6d94 | 14694 | s = "dx"; |
d708bcba | 14695 | else |
db6eb5be | 14696 | s = "(%dx)"; |
252b5132 RH |
14697 | break; |
14698 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
14699 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14700 | s = names16[code - ax_reg]; | |
14701 | break; | |
14702 | case es_reg: case ss_reg: case cs_reg: | |
14703 | case ds_reg: case fs_reg: case gs_reg: | |
14704 | s = names_seg[code - es_reg]; | |
14705 | break; | |
14706 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
14707 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
14708 | USED_REX (0); |
14709 | if (rex) | |
14710 | s = names8rex[code - al_reg]; | |
14711 | else | |
14712 | s = names8[code - al_reg]; | |
252b5132 RH |
14713 | break; |
14714 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
14715 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14716 | USED_REX (REX_W); |
14717 | if (rex & REX_W) | |
52b15da3 | 14718 | s = names64[code - eAX_reg]; |
252b5132 | 14719 | else |
f16cd0d5 L |
14720 | { |
14721 | if (sizeflag & DFLAG) | |
14722 | s = names32[code - eAX_reg]; | |
14723 | else | |
14724 | s = names16[code - eAX_reg]; | |
14725 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14726 | } | |
252b5132 | 14727 | break; |
52fd6d94 | 14728 | case z_mode_ax_reg: |
161a04f6 | 14729 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14730 | s = *names32; |
14731 | else | |
14732 | s = *names16; | |
161a04f6 | 14733 | if (!(rex & REX_W)) |
52fd6d94 JB |
14734 | used_prefixes |= (prefixes & PREFIX_DATA); |
14735 | break; | |
252b5132 RH |
14736 | default: |
14737 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14738 | break; | |
14739 | } | |
14740 | oappend (s); | |
14741 | } | |
14742 | ||
14743 | static void | |
26ca5450 | 14744 | OP_I (int bytemode, int sizeflag) |
252b5132 | 14745 | { |
52b15da3 JH |
14746 | bfd_signed_vma op; |
14747 | bfd_signed_vma mask = -1; | |
252b5132 RH |
14748 | |
14749 | switch (bytemode) | |
14750 | { | |
14751 | case b_mode: | |
14752 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
14753 | op = *codep++; |
14754 | mask = 0xff; | |
14755 | break; | |
252b5132 | 14756 | case v_mode: |
161a04f6 L |
14757 | USED_REX (REX_W); |
14758 | if (rex & REX_W) | |
52b15da3 | 14759 | op = get32s (); |
252b5132 | 14760 | else |
52b15da3 | 14761 | { |
f16cd0d5 L |
14762 | if (sizeflag & DFLAG) |
14763 | { | |
14764 | op = get32 (); | |
14765 | mask = 0xffffffff; | |
14766 | } | |
14767 | else | |
14768 | { | |
14769 | op = get16 (); | |
14770 | mask = 0xfffff; | |
14771 | } | |
14772 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 14773 | } |
252b5132 | 14774 | break; |
c1dc7af5 JB |
14775 | case d_mode: |
14776 | mask = 0xffffffff; | |
14777 | op = get32 (); | |
14778 | break; | |
252b5132 | 14779 | case w_mode: |
52b15da3 | 14780 | mask = 0xfffff; |
252b5132 RH |
14781 | op = get16 (); |
14782 | break; | |
9306ca4a JB |
14783 | case const_1_mode: |
14784 | if (intel_syntax) | |
6c067bbb | 14785 | oappend ("1"); |
9306ca4a | 14786 | return; |
252b5132 RH |
14787 | default: |
14788 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14789 | return; | |
14790 | } | |
14791 | ||
52b15da3 JH |
14792 | op &= mask; |
14793 | scratchbuf[0] = '$'; | |
d708bcba | 14794 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 14795 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
14796 | scratchbuf[0] = '\0'; |
14797 | } | |
14798 | ||
14799 | static void | |
26ca5450 | 14800 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 | 14801 | { |
a280ab8e | 14802 | if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W)) |
6439fc28 AM |
14803 | { |
14804 | OP_I (bytemode, sizeflag); | |
14805 | return; | |
14806 | } | |
14807 | ||
a280ab8e | 14808 | USED_REX (REX_W); |
52b15da3 | 14809 | |
52b15da3 | 14810 | scratchbuf[0] = '$'; |
a280ab8e | 14811 | print_operand_value (scratchbuf + 1, 1, get64 ()); |
9ce09ba2 | 14812 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14813 | scratchbuf[0] = '\0'; |
14814 | } | |
14815 | ||
14816 | static void | |
26ca5450 | 14817 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 14818 | { |
52b15da3 | 14819 | bfd_signed_vma op; |
252b5132 RH |
14820 | |
14821 | switch (bytemode) | |
14822 | { | |
14823 | case b_mode: | |
e3949f17 | 14824 | case b_T_mode: |
252b5132 RH |
14825 | FETCH_DATA (the_info, codep + 1); |
14826 | op = *codep++; | |
14827 | if ((op & 0x80) != 0) | |
14828 | op -= 0x100; | |
e3949f17 L |
14829 | if (bytemode == b_T_mode) |
14830 | { | |
14831 | if (address_mode != mode_64bit | |
7bb15c6f | 14832 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 14833 | { |
6c067bbb RM |
14834 | /* The operand-size prefix is overridden by a REX prefix. */ |
14835 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
14836 | op &= 0xffffffff; |
14837 | else | |
14838 | op &= 0xffff; | |
14839 | } | |
14840 | } | |
14841 | else | |
14842 | { | |
14843 | if (!(rex & REX_W)) | |
14844 | { | |
14845 | if (sizeflag & DFLAG) | |
14846 | op &= 0xffffffff; | |
14847 | else | |
14848 | op &= 0xffff; | |
14849 | } | |
14850 | } | |
252b5132 RH |
14851 | break; |
14852 | case v_mode: | |
7bb15c6f RM |
14853 | /* The operand-size prefix is overridden by a REX prefix. */ |
14854 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 14855 | op = get32s (); |
252b5132 | 14856 | else |
d9e3625e | 14857 | op = get16 (); |
252b5132 RH |
14858 | break; |
14859 | default: | |
14860 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14861 | return; | |
14862 | } | |
52b15da3 JH |
14863 | |
14864 | scratchbuf[0] = '$'; | |
14865 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 14866 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14867 | } |
14868 | ||
14869 | static void | |
26ca5450 | 14870 | OP_J (int bytemode, int sizeflag) |
252b5132 | 14871 | { |
52b15da3 | 14872 | bfd_vma disp; |
7081ff04 | 14873 | bfd_vma mask = -1; |
65ca155d | 14874 | bfd_vma segment = 0; |
252b5132 RH |
14875 | |
14876 | switch (bytemode) | |
14877 | { | |
14878 | case b_mode: | |
14879 | FETCH_DATA (the_info, codep + 1); | |
14880 | disp = *codep++; | |
14881 | if ((disp & 0x80) != 0) | |
14882 | disp -= 0x100; | |
14883 | break; | |
14884 | case v_mode: | |
d835a58b | 14885 | if (isa64 != intel64) |
376cd056 | 14886 | case dqw_mode: |
5db04b09 L |
14887 | USED_REX (REX_W); |
14888 | if ((sizeflag & DFLAG) | |
14889 | || (address_mode == mode_64bit | |
d835a58b | 14890 | && ((isa64 == intel64 && bytemode != dqw_mode) |
376cd056 | 14891 | || (rex & REX_W)))) |
52b15da3 | 14892 | disp = get32s (); |
252b5132 RH |
14893 | else |
14894 | { | |
14895 | disp = get16 (); | |
206717e8 L |
14896 | if ((disp & 0x8000) != 0) |
14897 | disp -= 0x10000; | |
65ca155d L |
14898 | /* In 16bit mode, address is wrapped around at 64k within |
14899 | the same segment. Otherwise, a data16 prefix on a jump | |
14900 | instruction means that the pc is masked to 16 bits after | |
14901 | the displacement is added! */ | |
14902 | mask = 0xffff; | |
14903 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 14904 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 14905 | & ~((bfd_vma) 0xffff)); |
252b5132 | 14906 | } |
5db04b09 | 14907 | if (address_mode != mode_64bit |
d835a58b | 14908 | || (isa64 != intel64 && !(rex & REX_W))) |
f16cd0d5 | 14909 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
14910 | break; |
14911 | default: | |
14912 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14913 | return; | |
14914 | } | |
42d5f9c6 | 14915 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
14916 | set_op (disp, 0); |
14917 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
14918 | oappend (scratchbuf); |
14919 | } | |
14920 | ||
252b5132 | 14921 | static void |
ed7841b3 | 14922 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 14923 | { |
ed7841b3 | 14924 | if (bytemode == w_mode) |
7967e09e | 14925 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 14926 | else |
7967e09e | 14927 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
14928 | } |
14929 | ||
14930 | static void | |
26ca5450 | 14931 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
14932 | { |
14933 | int seg, offset; | |
14934 | ||
c608c12e | 14935 | if (sizeflag & DFLAG) |
252b5132 | 14936 | { |
c608c12e AM |
14937 | offset = get32 (); |
14938 | seg = get16 (); | |
252b5132 | 14939 | } |
c608c12e AM |
14940 | else |
14941 | { | |
14942 | offset = get16 (); | |
14943 | seg = get16 (); | |
14944 | } | |
7d421014 | 14945 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 14946 | if (intel_syntax) |
3f31e633 | 14947 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
14948 | else |
14949 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 14950 | oappend (scratchbuf); |
252b5132 RH |
14951 | } |
14952 | ||
252b5132 | 14953 | static void |
3f31e633 | 14954 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 14955 | { |
52b15da3 | 14956 | bfd_vma off; |
252b5132 | 14957 | |
3f31e633 JB |
14958 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
14959 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
14960 | append_seg (); |
14961 | ||
cb712a9e | 14962 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
14963 | off = get32 (); |
14964 | else | |
14965 | off = get16 (); | |
14966 | ||
14967 | if (intel_syntax) | |
14968 | { | |
285ca992 | 14969 | if (!active_seg_prefix) |
252b5132 | 14970 | { |
d708bcba | 14971 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14972 | oappend (":"); |
14973 | } | |
14974 | } | |
52b15da3 JH |
14975 | print_operand_value (scratchbuf, 1, off); |
14976 | oappend (scratchbuf); | |
14977 | } | |
6439fc28 | 14978 | |
52b15da3 | 14979 | static void |
3f31e633 | 14980 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
14981 | { |
14982 | bfd_vma off; | |
14983 | ||
539e75ad L |
14984 | if (address_mode != mode_64bit |
14985 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
14986 | { |
14987 | OP_OFF (bytemode, sizeflag); | |
14988 | return; | |
14989 | } | |
14990 | ||
3f31e633 JB |
14991 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
14992 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
14993 | append_seg (); |
14994 | ||
6608db57 | 14995 | off = get64 (); |
52b15da3 JH |
14996 | |
14997 | if (intel_syntax) | |
14998 | { | |
285ca992 | 14999 | if (!active_seg_prefix) |
52b15da3 | 15000 | { |
d708bcba | 15001 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
15002 | oappend (":"); |
15003 | } | |
15004 | } | |
15005 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
15006 | oappend (scratchbuf); |
15007 | } | |
15008 | ||
15009 | static void | |
26ca5450 | 15010 | ptr_reg (int code, int sizeflag) |
252b5132 | 15011 | { |
2da11e11 | 15012 | const char *s; |
d708bcba | 15013 | |
1d9f512f | 15014 | *obufp++ = open_char; |
20f0a1fc | 15015 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 15016 | if (address_mode == mode_64bit) |
c1a64871 JH |
15017 | { |
15018 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 15019 | s = names32[code - eAX_reg]; |
c1a64871 | 15020 | else |
db6eb5be | 15021 | s = names64[code - eAX_reg]; |
c1a64871 | 15022 | } |
52b15da3 | 15023 | else if (sizeflag & AFLAG) |
252b5132 RH |
15024 | s = names32[code - eAX_reg]; |
15025 | else | |
15026 | s = names16[code - eAX_reg]; | |
15027 | oappend (s); | |
1d9f512f AM |
15028 | *obufp++ = close_char; |
15029 | *obufp = 0; | |
252b5132 RH |
15030 | } |
15031 | ||
15032 | static void | |
26ca5450 | 15033 | OP_ESreg (int code, int sizeflag) |
252b5132 | 15034 | { |
9306ca4a | 15035 | if (intel_syntax) |
52fd6d94 JB |
15036 | { |
15037 | switch (codep[-1]) | |
15038 | { | |
15039 | case 0x6d: /* insw/insl */ | |
15040 | intel_operand_size (z_mode, sizeflag); | |
15041 | break; | |
15042 | case 0xa5: /* movsw/movsl/movsq */ | |
15043 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15044 | case 0xab: /* stosw/stosl */ | |
15045 | case 0xaf: /* scasw/scasl */ | |
15046 | intel_operand_size (v_mode, sizeflag); | |
15047 | break; | |
15048 | default: | |
15049 | intel_operand_size (b_mode, sizeflag); | |
15050 | } | |
15051 | } | |
9ce09ba2 | 15052 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
15053 | ptr_reg (code, sizeflag); |
15054 | } | |
15055 | ||
15056 | static void | |
26ca5450 | 15057 | OP_DSreg (int code, int sizeflag) |
252b5132 | 15058 | { |
9306ca4a | 15059 | if (intel_syntax) |
52fd6d94 JB |
15060 | { |
15061 | switch (codep[-1]) | |
15062 | { | |
15063 | case 0x6f: /* outsw/outsl */ | |
15064 | intel_operand_size (z_mode, sizeflag); | |
15065 | break; | |
15066 | case 0xa5: /* movsw/movsl/movsq */ | |
15067 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15068 | case 0xad: /* lodsw/lodsl/lodsq */ | |
15069 | intel_operand_size (v_mode, sizeflag); | |
15070 | break; | |
15071 | default: | |
15072 | intel_operand_size (b_mode, sizeflag); | |
15073 | } | |
15074 | } | |
285ca992 L |
15075 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
15076 | default segment register DS is printed. */ | |
15077 | if (!active_seg_prefix) | |
15078 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 15079 | append_seg (); |
252b5132 RH |
15080 | ptr_reg (code, sizeflag); |
15081 | } | |
15082 | ||
252b5132 | 15083 | static void |
26ca5450 | 15084 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15085 | { |
9b60702d | 15086 | int add; |
161a04f6 | 15087 | if (rex & REX_R) |
c4a530c5 | 15088 | { |
161a04f6 | 15089 | USED_REX (REX_R); |
c4a530c5 JB |
15090 | add = 8; |
15091 | } | |
cb712a9e | 15092 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 15093 | { |
f16cd0d5 | 15094 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
15095 | used_prefixes |= PREFIX_LOCK; |
15096 | add = 8; | |
15097 | } | |
9b60702d L |
15098 | else |
15099 | add = 0; | |
7967e09e | 15100 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 15101 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15102 | } |
15103 | ||
252b5132 | 15104 | static void |
26ca5450 | 15105 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15106 | { |
9b60702d | 15107 | int add; |
161a04f6 L |
15108 | USED_REX (REX_R); |
15109 | if (rex & REX_R) | |
52b15da3 | 15110 | add = 8; |
9b60702d L |
15111 | else |
15112 | add = 0; | |
d708bcba | 15113 | if (intel_syntax) |
7967e09e | 15114 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 15115 | else |
7967e09e | 15116 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
15117 | oappend (scratchbuf); |
15118 | } | |
15119 | ||
252b5132 | 15120 | static void |
26ca5450 | 15121 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15122 | { |
7967e09e | 15123 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 15124 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15125 | } |
15126 | ||
15127 | static void | |
6f74c397 | 15128 | OP_R (int bytemode, int sizeflag) |
252b5132 | 15129 | { |
68f34464 L |
15130 | /* Skip mod/rm byte. */ |
15131 | MODRM_CHECK; | |
15132 | codep++; | |
15133 | OP_E_register (bytemode, sizeflag); | |
252b5132 RH |
15134 | } |
15135 | ||
15136 | static void | |
26ca5450 | 15137 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15138 | { |
b9733481 L |
15139 | int reg = modrm.reg; |
15140 | const char **names; | |
15141 | ||
041bd2e0 JH |
15142 | used_prefixes |= (prefixes & PREFIX_DATA); |
15143 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 15144 | { |
b9733481 | 15145 | names = names_xmm; |
161a04f6 L |
15146 | USED_REX (REX_R); |
15147 | if (rex & REX_R) | |
b9733481 | 15148 | reg += 8; |
20f0a1fc | 15149 | } |
041bd2e0 | 15150 | else |
b9733481 L |
15151 | names = names_mm; |
15152 | oappend (names[reg]); | |
252b5132 RH |
15153 | } |
15154 | ||
c608c12e | 15155 | static void |
c0f3af97 | 15156 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 15157 | { |
b9733481 L |
15158 | int reg = modrm.reg; |
15159 | const char **names; | |
15160 | ||
161a04f6 L |
15161 | USED_REX (REX_R); |
15162 | if (rex & REX_R) | |
b9733481 | 15163 | reg += 8; |
43234a1e L |
15164 | if (vex.evex) |
15165 | { | |
15166 | if (!vex.r) | |
15167 | reg += 16; | |
15168 | } | |
15169 | ||
539f890d L |
15170 | if (need_vex |
15171 | && bytemode != xmm_mode | |
43234a1e L |
15172 | && bytemode != xmmq_mode |
15173 | && bytemode != evex_half_bcst_xmmq_mode | |
15174 | && bytemode != ymm_mode | |
539f890d | 15175 | && bytemode != scalar_mode) |
c0f3af97 L |
15176 | { |
15177 | switch (vex.length) | |
15178 | { | |
15179 | case 128: | |
b9733481 | 15180 | names = names_xmm; |
c0f3af97 L |
15181 | break; |
15182 | case 256: | |
5fc35d96 IT |
15183 | if (vex.w |
15184 | || (bytemode != vex_vsib_q_w_dq_mode | |
15185 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
15186 | names = names_ymm; |
15187 | else | |
15188 | names = names_xmm; | |
c0f3af97 | 15189 | break; |
43234a1e L |
15190 | case 512: |
15191 | names = names_zmm; | |
15192 | break; | |
c0f3af97 L |
15193 | default: |
15194 | abort (); | |
15195 | } | |
15196 | } | |
43234a1e L |
15197 | else if (bytemode == xmmq_mode |
15198 | || bytemode == evex_half_bcst_xmmq_mode) | |
15199 | { | |
15200 | switch (vex.length) | |
15201 | { | |
15202 | case 128: | |
15203 | case 256: | |
15204 | names = names_xmm; | |
15205 | break; | |
15206 | case 512: | |
15207 | names = names_ymm; | |
15208 | break; | |
15209 | default: | |
15210 | abort (); | |
15211 | } | |
15212 | } | |
15213 | else if (bytemode == ymm_mode) | |
15214 | names = names_ymm; | |
c0f3af97 | 15215 | else |
b9733481 L |
15216 | names = names_xmm; |
15217 | oappend (names[reg]); | |
c608c12e AM |
15218 | } |
15219 | ||
252b5132 | 15220 | static void |
26ca5450 | 15221 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 15222 | { |
b9733481 L |
15223 | int reg; |
15224 | const char **names; | |
15225 | ||
7967e09e | 15226 | if (modrm.mod != 3) |
252b5132 | 15227 | { |
b6169b20 L |
15228 | if (intel_syntax |
15229 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
15230 | { |
15231 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15232 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15233 | } |
252b5132 RH |
15234 | OP_E (bytemode, sizeflag); |
15235 | return; | |
15236 | } | |
15237 | ||
b6169b20 L |
15238 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
15239 | swap_operand (); | |
15240 | ||
6608db57 | 15241 | /* Skip mod/rm byte. */ |
4bba6815 | 15242 | MODRM_CHECK; |
252b5132 | 15243 | codep++; |
041bd2e0 | 15244 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 15245 | reg = modrm.rm; |
041bd2e0 | 15246 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 15247 | { |
b9733481 | 15248 | names = names_xmm; |
161a04f6 L |
15249 | USED_REX (REX_B); |
15250 | if (rex & REX_B) | |
b9733481 | 15251 | reg += 8; |
20f0a1fc | 15252 | } |
041bd2e0 | 15253 | else |
b9733481 L |
15254 | names = names_mm; |
15255 | oappend (names[reg]); | |
252b5132 RH |
15256 | } |
15257 | ||
246c51aa L |
15258 | /* cvt* are the only instructions in sse2 which have |
15259 | both SSE and MMX operands and also have 0x66 prefix | |
15260 | in their opcode. 0x66 was originally used to differentiate | |
15261 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
15262 | cvt* separately using OP_EMC and OP_MXC */ |
15263 | static void | |
15264 | OP_EMC (int bytemode, int sizeflag) | |
15265 | { | |
7967e09e | 15266 | if (modrm.mod != 3) |
4d9567e0 MM |
15267 | { |
15268 | if (intel_syntax && bytemode == v_mode) | |
15269 | { | |
15270 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15271 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15272 | } |
4d9567e0 MM |
15273 | OP_E (bytemode, sizeflag); |
15274 | return; | |
15275 | } | |
246c51aa | 15276 | |
4d9567e0 MM |
15277 | /* Skip mod/rm byte. */ |
15278 | MODRM_CHECK; | |
15279 | codep++; | |
15280 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15281 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
15282 | } |
15283 | ||
15284 | static void | |
15285 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15286 | { | |
15287 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15288 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
15289 | } |
15290 | ||
c608c12e | 15291 | static void |
26ca5450 | 15292 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 15293 | { |
b9733481 L |
15294 | int reg; |
15295 | const char **names; | |
d6f574e0 L |
15296 | |
15297 | /* Skip mod/rm byte. */ | |
15298 | MODRM_CHECK; | |
15299 | codep++; | |
15300 | ||
7967e09e | 15301 | if (modrm.mod != 3) |
c608c12e | 15302 | { |
c1e679ec | 15303 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
15304 | return; |
15305 | } | |
d6f574e0 | 15306 | |
b9733481 | 15307 | reg = modrm.rm; |
161a04f6 L |
15308 | USED_REX (REX_B); |
15309 | if (rex & REX_B) | |
b9733481 | 15310 | reg += 8; |
43234a1e L |
15311 | if (vex.evex) |
15312 | { | |
15313 | USED_REX (REX_X); | |
15314 | if ((rex & REX_X)) | |
15315 | reg += 16; | |
15316 | } | |
c608c12e | 15317 | |
b6169b20 | 15318 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
15319 | && (bytemode == x_swap_mode |
15320 | || bytemode == d_swap_mode | |
7bb15c6f | 15321 | || bytemode == d_scalar_swap_mode |
539f890d L |
15322 | || bytemode == q_swap_mode |
15323 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
15324 | swap_operand (); |
15325 | ||
c0f3af97 L |
15326 | if (need_vex |
15327 | && bytemode != xmm_mode | |
6c30d220 L |
15328 | && bytemode != xmmdw_mode |
15329 | && bytemode != xmmqd_mode | |
15330 | && bytemode != xmm_mb_mode | |
15331 | && bytemode != xmm_mw_mode | |
15332 | && bytemode != xmm_md_mode | |
15333 | && bytemode != xmm_mq_mode | |
539f890d | 15334 | && bytemode != xmmq_mode |
43234a1e L |
15335 | && bytemode != evex_half_bcst_xmmq_mode |
15336 | && bytemode != ymm_mode | |
539f890d | 15337 | && bytemode != d_scalar_mode |
7bb15c6f | 15338 | && bytemode != d_scalar_swap_mode |
539f890d | 15339 | && bytemode != q_scalar_mode |
1c480963 L |
15340 | && bytemode != q_scalar_swap_mode |
15341 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
15342 | { |
15343 | switch (vex.length) | |
15344 | { | |
15345 | case 128: | |
b9733481 | 15346 | names = names_xmm; |
c0f3af97 L |
15347 | break; |
15348 | case 256: | |
b9733481 | 15349 | names = names_ymm; |
c0f3af97 | 15350 | break; |
43234a1e L |
15351 | case 512: |
15352 | names = names_zmm; | |
15353 | break; | |
c0f3af97 L |
15354 | default: |
15355 | abort (); | |
15356 | } | |
15357 | } | |
43234a1e L |
15358 | else if (bytemode == xmmq_mode |
15359 | || bytemode == evex_half_bcst_xmmq_mode) | |
15360 | { | |
15361 | switch (vex.length) | |
15362 | { | |
15363 | case 128: | |
15364 | case 256: | |
15365 | names = names_xmm; | |
15366 | break; | |
15367 | case 512: | |
15368 | names = names_ymm; | |
15369 | break; | |
15370 | default: | |
15371 | abort (); | |
15372 | } | |
15373 | } | |
15374 | else if (bytemode == ymm_mode) | |
15375 | names = names_ymm; | |
c0f3af97 | 15376 | else |
b9733481 L |
15377 | names = names_xmm; |
15378 | oappend (names[reg]); | |
c608c12e AM |
15379 | } |
15380 | ||
252b5132 | 15381 | static void |
26ca5450 | 15382 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 15383 | { |
7967e09e | 15384 | if (modrm.mod == 3) |
2da11e11 AM |
15385 | OP_EM (bytemode, sizeflag); |
15386 | else | |
6608db57 | 15387 | BadOp (); |
252b5132 RH |
15388 | } |
15389 | ||
992aaec9 | 15390 | static void |
26ca5450 | 15391 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 15392 | { |
7967e09e | 15393 | if (modrm.mod == 3) |
992aaec9 AM |
15394 | OP_EX (bytemode, sizeflag); |
15395 | else | |
6608db57 | 15396 | BadOp (); |
992aaec9 AM |
15397 | } |
15398 | ||
cc0ec051 AM |
15399 | static void |
15400 | OP_M (int bytemode, int sizeflag) | |
15401 | { | |
7967e09e | 15402 | if (modrm.mod == 3) |
75413a22 L |
15403 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
15404 | BadOp (); | |
cc0ec051 AM |
15405 | else |
15406 | OP_E (bytemode, sizeflag); | |
15407 | } | |
15408 | ||
15409 | static void | |
15410 | OP_0f07 (int bytemode, int sizeflag) | |
15411 | { | |
7967e09e | 15412 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
15413 | BadOp (); |
15414 | else | |
15415 | OP_E (bytemode, sizeflag); | |
15416 | } | |
15417 | ||
46e883c5 | 15418 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 15419 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 15420 | |
cc0ec051 | 15421 | static void |
46e883c5 | 15422 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 15423 | { |
8b38ad71 L |
15424 | if ((prefixes & PREFIX_DATA) != 0 |
15425 | || (rex != 0 | |
15426 | && rex != 0x48 | |
15427 | && address_mode == mode_64bit)) | |
46e883c5 L |
15428 | OP_REG (bytemode, sizeflag); |
15429 | else | |
15430 | strcpy (obuf, "nop"); | |
15431 | } | |
15432 | ||
15433 | static void | |
15434 | NOP_Fixup2 (int bytemode, int sizeflag) | |
15435 | { | |
8b38ad71 L |
15436 | if ((prefixes & PREFIX_DATA) != 0 |
15437 | || (rex != 0 | |
15438 | && rex != 0x48 | |
15439 | && address_mode == mode_64bit)) | |
46e883c5 | 15440 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
15441 | } |
15442 | ||
84037f8c | 15443 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
15444 | /* 00 */ NULL, NULL, NULL, NULL, |
15445 | /* 04 */ NULL, NULL, NULL, NULL, | |
15446 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15447 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
15448 | /* 10 */ NULL, NULL, NULL, NULL, |
15449 | /* 14 */ NULL, NULL, NULL, NULL, | |
15450 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15451 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
15452 | /* 20 */ NULL, NULL, NULL, NULL, |
15453 | /* 24 */ NULL, NULL, NULL, NULL, | |
15454 | /* 28 */ NULL, NULL, NULL, NULL, | |
15455 | /* 2C */ NULL, NULL, NULL, NULL, | |
15456 | /* 30 */ NULL, NULL, NULL, NULL, | |
15457 | /* 34 */ NULL, NULL, NULL, NULL, | |
15458 | /* 38 */ NULL, NULL, NULL, NULL, | |
15459 | /* 3C */ NULL, NULL, NULL, NULL, | |
15460 | /* 40 */ NULL, NULL, NULL, NULL, | |
15461 | /* 44 */ NULL, NULL, NULL, NULL, | |
15462 | /* 48 */ NULL, NULL, NULL, NULL, | |
15463 | /* 4C */ NULL, NULL, NULL, NULL, | |
15464 | /* 50 */ NULL, NULL, NULL, NULL, | |
15465 | /* 54 */ NULL, NULL, NULL, NULL, | |
15466 | /* 58 */ NULL, NULL, NULL, NULL, | |
15467 | /* 5C */ NULL, NULL, NULL, NULL, | |
15468 | /* 60 */ NULL, NULL, NULL, NULL, | |
15469 | /* 64 */ NULL, NULL, NULL, NULL, | |
15470 | /* 68 */ NULL, NULL, NULL, NULL, | |
15471 | /* 6C */ NULL, NULL, NULL, NULL, | |
15472 | /* 70 */ NULL, NULL, NULL, NULL, | |
15473 | /* 74 */ NULL, NULL, NULL, NULL, | |
15474 | /* 78 */ NULL, NULL, NULL, NULL, | |
15475 | /* 7C */ NULL, NULL, NULL, NULL, | |
15476 | /* 80 */ NULL, NULL, NULL, NULL, | |
15477 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
15478 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
15479 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
15480 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
15481 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
15482 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
15483 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
15484 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
15485 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
15486 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
15487 | /* AC */ NULL, NULL, "pfacc", NULL, | |
15488 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 15489 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 15490 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
15491 | /* BC */ NULL, NULL, NULL, "pavgusb", |
15492 | /* C0 */ NULL, NULL, NULL, NULL, | |
15493 | /* C4 */ NULL, NULL, NULL, NULL, | |
15494 | /* C8 */ NULL, NULL, NULL, NULL, | |
15495 | /* CC */ NULL, NULL, NULL, NULL, | |
15496 | /* D0 */ NULL, NULL, NULL, NULL, | |
15497 | /* D4 */ NULL, NULL, NULL, NULL, | |
15498 | /* D8 */ NULL, NULL, NULL, NULL, | |
15499 | /* DC */ NULL, NULL, NULL, NULL, | |
15500 | /* E0 */ NULL, NULL, NULL, NULL, | |
15501 | /* E4 */ NULL, NULL, NULL, NULL, | |
15502 | /* E8 */ NULL, NULL, NULL, NULL, | |
15503 | /* EC */ NULL, NULL, NULL, NULL, | |
15504 | /* F0 */ NULL, NULL, NULL, NULL, | |
15505 | /* F4 */ NULL, NULL, NULL, NULL, | |
15506 | /* F8 */ NULL, NULL, NULL, NULL, | |
15507 | /* FC */ NULL, NULL, NULL, NULL, | |
15508 | }; | |
15509 | ||
15510 | static void | |
26ca5450 | 15511 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
15512 | { |
15513 | const char *mnemonic; | |
15514 | ||
15515 | FETCH_DATA (the_info, codep + 1); | |
15516 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
15517 | place where an 8-bit immediate would normally go. ie. the last | |
15518 | byte of the instruction. */ | |
ea397f5b | 15519 | obufp = mnemonicendp; |
c608c12e | 15520 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 15521 | if (mnemonic) |
2da11e11 | 15522 | oappend (mnemonic); |
252b5132 RH |
15523 | else |
15524 | { | |
15525 | /* Since a variable sized modrm/sib chunk is between the start | |
15526 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
15527 | all the modrm processing first, and don't know until now that | |
15528 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
15529 | op_out[0][0] = '\0'; |
15530 | op_out[1][0] = '\0'; | |
6608db57 | 15531 | BadOp (); |
252b5132 | 15532 | } |
ea397f5b | 15533 | mnemonicendp = obufp; |
252b5132 | 15534 | } |
c608c12e | 15535 | |
ea397f5b L |
15536 | static struct op simd_cmp_op[] = |
15537 | { | |
15538 | { STRING_COMMA_LEN ("eq") }, | |
15539 | { STRING_COMMA_LEN ("lt") }, | |
15540 | { STRING_COMMA_LEN ("le") }, | |
15541 | { STRING_COMMA_LEN ("unord") }, | |
15542 | { STRING_COMMA_LEN ("neq") }, | |
15543 | { STRING_COMMA_LEN ("nlt") }, | |
15544 | { STRING_COMMA_LEN ("nle") }, | |
15545 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
15546 | }; |
15547 | ||
15548 | static void | |
ad19981d | 15549 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
15550 | { |
15551 | unsigned int cmp_type; | |
15552 | ||
15553 | FETCH_DATA (the_info, codep + 1); | |
15554 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 15555 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 15556 | { |
ad19981d | 15557 | char suffix [3]; |
ea397f5b | 15558 | char *p = mnemonicendp - 2; |
ad19981d L |
15559 | suffix[0] = p[0]; |
15560 | suffix[1] = p[1]; | |
15561 | suffix[2] = '\0'; | |
ea397f5b L |
15562 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
15563 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
15564 | } |
15565 | else | |
15566 | { | |
ad19981d L |
15567 | /* We have a reserved extension byte. Output it directly. */ |
15568 | scratchbuf[0] = '$'; | |
15569 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 15570 | oappend_maybe_intel (scratchbuf); |
ad19981d | 15571 | scratchbuf[0] = '\0'; |
c608c12e AM |
15572 | } |
15573 | } | |
15574 | ||
9916071f | 15575 | static void |
7abb8d81 | 15576 | OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
9916071f | 15577 | { |
7abb8d81 | 15578 | /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */ |
b844680a L |
15579 | if (!intel_syntax) |
15580 | { | |
081e283f JB |
15581 | strcpy (op_out[0], names32[0]); |
15582 | strcpy (op_out[1], names32[1]); | |
7abb8d81 | 15583 | if (bytemode == eBX_reg) |
081e283f | 15584 | strcpy (op_out[2], names32[3]); |
b844680a L |
15585 | two_source_ops = 1; |
15586 | } | |
15587 | /* Skip mod/rm byte. */ | |
15588 | MODRM_CHECK; | |
15589 | codep++; | |
15590 | } | |
15591 | ||
15592 | static void | |
15593 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
15594 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 15595 | { |
081e283f | 15596 | /* monitor %{e,r,}ax,%ecx,%edx" */ |
b844680a | 15597 | if (!intel_syntax) |
ca164297 | 15598 | { |
cb712a9e L |
15599 | const char **names = (address_mode == mode_64bit |
15600 | ? names64 : names32); | |
1d9f512f | 15601 | |
081e283f | 15602 | if (prefixes & PREFIX_ADDR) |
ca164297 | 15603 | { |
b844680a | 15604 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 15605 | all_prefixes[last_addr_prefix] = 0; |
081e283f JB |
15606 | names = (address_mode != mode_32bit |
15607 | ? names32 : names16); | |
b844680a | 15608 | used_prefixes |= PREFIX_ADDR; |
ca164297 | 15609 | } |
081e283f JB |
15610 | else if (address_mode == mode_16bit) |
15611 | names = names16; | |
15612 | strcpy (op_out[0], names[0]); | |
15613 | strcpy (op_out[1], names32[1]); | |
15614 | strcpy (op_out[2], names32[2]); | |
b844680a | 15615 | two_source_ops = 1; |
ca164297 | 15616 | } |
b844680a L |
15617 | /* Skip mod/rm byte. */ |
15618 | MODRM_CHECK; | |
15619 | codep++; | |
30123838 JB |
15620 | } |
15621 | ||
6608db57 KH |
15622 | static void |
15623 | BadOp (void) | |
2da11e11 | 15624 | { |
6608db57 KH |
15625 | /* Throw away prefixes and 1st. opcode byte. */ |
15626 | codep = insn_codep + 1; | |
2da11e11 AM |
15627 | oappend ("(bad)"); |
15628 | } | |
4cc91dba | 15629 | |
35c52694 L |
15630 | static void |
15631 | REP_Fixup (int bytemode, int sizeflag) | |
15632 | { | |
15633 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
15634 | lods and stos. */ | |
35c52694 | 15635 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 15636 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
15637 | |
15638 | switch (bytemode) | |
15639 | { | |
15640 | case al_reg: | |
15641 | case eAX_reg: | |
15642 | case indir_dx_reg: | |
15643 | OP_IMREG (bytemode, sizeflag); | |
15644 | break; | |
15645 | case eDI_reg: | |
15646 | OP_ESreg (bytemode, sizeflag); | |
15647 | break; | |
15648 | case eSI_reg: | |
15649 | OP_DSreg (bytemode, sizeflag); | |
15650 | break; | |
15651 | default: | |
15652 | abort (); | |
15653 | break; | |
15654 | } | |
15655 | } | |
f5804c90 | 15656 | |
d835a58b JB |
15657 | static void |
15658 | SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15659 | { | |
15660 | if ( isa64 != amd64 ) | |
15661 | return; | |
15662 | ||
15663 | obufp = obuf; | |
15664 | BadOp (); | |
15665 | mnemonicendp = obufp; | |
15666 | ++codep; | |
15667 | } | |
15668 | ||
7e8b059b L |
15669 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
15670 | "bnd". */ | |
15671 | ||
15672 | static void | |
15673 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15674 | { | |
15675 | if (prefixes & PREFIX_REPNZ) | |
15676 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
15677 | } | |
15678 | ||
04ef582a L |
15679 | /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as |
15680 | "notrack". */ | |
15681 | ||
15682 | static void | |
15683 | NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
15684 | int sizeflag ATTRIBUTE_UNUSED) | |
15685 | { | |
9fef80d6 | 15686 | if (active_seg_prefix == PREFIX_DS |
04ef582a L |
15687 | && (address_mode != mode_64bit || last_data_prefix < 0)) |
15688 | { | |
4e9ac44a | 15689 | /* NOTRACK prefix is only valid on indirect branch instructions. |
9fef80d6 | 15690 | NB: DATA prefix is unsupported for Intel64. */ |
04ef582a L |
15691 | active_seg_prefix = 0; |
15692 | all_prefixes[last_seg_prefix] = NOTRACK_PREFIX; | |
15693 | } | |
15694 | } | |
15695 | ||
42164a71 L |
15696 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
15697 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
15698 | */ | |
15699 | ||
15700 | static void | |
15701 | HLE_Fixup1 (int bytemode, int sizeflag) | |
15702 | { | |
15703 | if (modrm.mod != 3 | |
15704 | && (prefixes & PREFIX_LOCK) != 0) | |
15705 | { | |
15706 | if (prefixes & PREFIX_REPZ) | |
15707 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15708 | if (prefixes & PREFIX_REPNZ) | |
15709 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15710 | } | |
15711 | ||
15712 | OP_E (bytemode, sizeflag); | |
15713 | } | |
15714 | ||
15715 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
15716 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
15717 | */ | |
15718 | ||
15719 | static void | |
15720 | HLE_Fixup2 (int bytemode, int sizeflag) | |
15721 | { | |
15722 | if (modrm.mod != 3) | |
15723 | { | |
15724 | if (prefixes & PREFIX_REPZ) | |
15725 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15726 | if (prefixes & PREFIX_REPNZ) | |
15727 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15728 | } | |
15729 | ||
15730 | OP_E (bytemode, sizeflag); | |
15731 | } | |
15732 | ||
15733 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
15734 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
15735 | ||
15736 | static void | |
15737 | HLE_Fixup3 (int bytemode, int sizeflag) | |
15738 | { | |
15739 | if (modrm.mod != 3 | |
15740 | && last_repz_prefix > last_repnz_prefix | |
15741 | && (prefixes & PREFIX_REPZ) != 0) | |
15742 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15743 | ||
15744 | OP_E (bytemode, sizeflag); | |
15745 | } | |
15746 | ||
f5804c90 L |
15747 | static void |
15748 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
15749 | { | |
161a04f6 L |
15750 | USED_REX (REX_W); |
15751 | if (rex & REX_W) | |
f5804c90 L |
15752 | { |
15753 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
15754 | char *p = mnemonicendp - 2; |
15755 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 15756 | bytemode = o_mode; |
f5804c90 | 15757 | } |
42164a71 L |
15758 | else if ((prefixes & PREFIX_LOCK) != 0) |
15759 | { | |
15760 | if (prefixes & PREFIX_REPZ) | |
15761 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15762 | if (prefixes & PREFIX_REPNZ) | |
15763 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15764 | } | |
15765 | ||
f5804c90 L |
15766 | OP_M (bytemode, sizeflag); |
15767 | } | |
42903f7f L |
15768 | |
15769 | static void | |
15770 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
15771 | { | |
b9733481 L |
15772 | const char **names; |
15773 | ||
c0f3af97 L |
15774 | if (need_vex) |
15775 | { | |
15776 | switch (vex.length) | |
15777 | { | |
15778 | case 128: | |
b9733481 | 15779 | names = names_xmm; |
c0f3af97 L |
15780 | break; |
15781 | case 256: | |
b9733481 | 15782 | names = names_ymm; |
c0f3af97 L |
15783 | break; |
15784 | default: | |
15785 | abort (); | |
15786 | } | |
15787 | } | |
15788 | else | |
b9733481 L |
15789 | names = names_xmm; |
15790 | oappend (names[reg]); | |
42903f7f | 15791 | } |
381d071f L |
15792 | |
15793 | static void | |
15794 | CRC32_Fixup (int bytemode, int sizeflag) | |
15795 | { | |
15796 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 15797 | char *p = mnemonicendp; |
381d071f L |
15798 | |
15799 | switch (bytemode) | |
15800 | { | |
15801 | case b_mode: | |
20592a94 | 15802 | if (intel_syntax) |
ea397f5b | 15803 | goto skip; |
20592a94 | 15804 | |
381d071f L |
15805 | *p++ = 'b'; |
15806 | break; | |
15807 | case v_mode: | |
20592a94 | 15808 | if (intel_syntax) |
ea397f5b | 15809 | goto skip; |
20592a94 | 15810 | |
381d071f L |
15811 | USED_REX (REX_W); |
15812 | if (rex & REX_W) | |
15813 | *p++ = 'q'; | |
7bb15c6f | 15814 | else |
f16cd0d5 L |
15815 | { |
15816 | if (sizeflag & DFLAG) | |
15817 | *p++ = 'l'; | |
15818 | else | |
15819 | *p++ = 'w'; | |
15820 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15821 | } | |
381d071f L |
15822 | break; |
15823 | default: | |
15824 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15825 | break; | |
15826 | } | |
ea397f5b | 15827 | mnemonicendp = p; |
381d071f L |
15828 | *p = '\0'; |
15829 | ||
dc1e8a47 | 15830 | skip: |
381d071f L |
15831 | if (modrm.mod == 3) |
15832 | { | |
15833 | int add; | |
15834 | ||
15835 | /* Skip mod/rm byte. */ | |
15836 | MODRM_CHECK; | |
15837 | codep++; | |
15838 | ||
15839 | USED_REX (REX_B); | |
15840 | add = (rex & REX_B) ? 8 : 0; | |
15841 | if (bytemode == b_mode) | |
15842 | { | |
15843 | USED_REX (0); | |
15844 | if (rex) | |
15845 | oappend (names8rex[modrm.rm + add]); | |
15846 | else | |
15847 | oappend (names8[modrm.rm + add]); | |
15848 | } | |
15849 | else | |
15850 | { | |
15851 | USED_REX (REX_W); | |
15852 | if (rex & REX_W) | |
15853 | oappend (names64[modrm.rm + add]); | |
15854 | else if ((prefixes & PREFIX_DATA)) | |
15855 | oappend (names16[modrm.rm + add]); | |
15856 | else | |
15857 | oappend (names32[modrm.rm + add]); | |
15858 | } | |
15859 | } | |
15860 | else | |
9344ff29 | 15861 | OP_E (bytemode, sizeflag); |
381d071f | 15862 | } |
85f10a01 | 15863 | |
eacc9c89 L |
15864 | static void |
15865 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
15866 | { | |
15867 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
15868 | USED_REX (REX_W); | |
15869 | if (rex & REX_W) | |
15870 | { | |
15871 | char *p = mnemonicendp; | |
15872 | *p++ = '6'; | |
15873 | *p++ = '4'; | |
15874 | *p = '\0'; | |
15875 | mnemonicendp = p; | |
15876 | } | |
15877 | OP_M (bytemode, sizeflag); | |
15878 | } | |
15879 | ||
15c7c1d8 JB |
15880 | static void |
15881 | PCMPESTR_Fixup (int bytemode, int sizeflag) | |
15882 | { | |
15883 | /* Add proper suffix to "{,v}pcmpestr{i,m}". */ | |
15884 | if (!intel_syntax) | |
15885 | { | |
15886 | char *p = mnemonicendp; | |
15887 | ||
15888 | USED_REX (REX_W); | |
15889 | if (rex & REX_W) | |
15890 | *p++ = 'q'; | |
15891 | else if (sizeflag & SUFFIX_ALWAYS) | |
15892 | *p++ = 'l'; | |
15893 | ||
15894 | *p = '\0'; | |
15895 | mnemonicendp = p; | |
15896 | } | |
15897 | ||
15898 | OP_EX (bytemode, sizeflag); | |
15899 | } | |
15900 | ||
c0f3af97 L |
15901 | /* Display the destination register operand for instructions with |
15902 | VEX. */ | |
15903 | ||
15904 | static void | |
15905 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
15906 | { | |
539f890d | 15907 | int reg; |
b9733481 L |
15908 | const char **names; |
15909 | ||
c0f3af97 L |
15910 | if (!need_vex) |
15911 | abort (); | |
15912 | ||
15913 | if (!need_vex_reg) | |
15914 | return; | |
15915 | ||
539f890d | 15916 | reg = vex.register_specifier; |
63c6fc6c | 15917 | vex.register_specifier = 0; |
5f847646 JB |
15918 | if (address_mode != mode_64bit) |
15919 | reg &= 7; | |
15920 | else if (vex.evex && !vex.v) | |
15921 | reg += 16; | |
43234a1e | 15922 | |
539f890d L |
15923 | if (bytemode == vex_scalar_mode) |
15924 | { | |
15925 | oappend (names_xmm[reg]); | |
15926 | return; | |
15927 | } | |
15928 | ||
c0f3af97 L |
15929 | switch (vex.length) |
15930 | { | |
15931 | case 128: | |
15932 | switch (bytemode) | |
15933 | { | |
15934 | case vex_mode: | |
15935 | case vex128_mode: | |
6c30d220 | 15936 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15937 | case vex_vsib_q_w_d_mode: |
cb21baef L |
15938 | names = names_xmm; |
15939 | break; | |
15940 | case dq_mode: | |
390a6789 | 15941 | if (rex & REX_W) |
cb21baef L |
15942 | names = names64; |
15943 | else | |
15944 | names = names32; | |
c0f3af97 | 15945 | break; |
1ba585e8 | 15946 | case mask_bd_mode: |
43234a1e | 15947 | case mask_mode: |
9889cbb1 L |
15948 | if (reg > 0x7) |
15949 | { | |
15950 | oappend ("(bad)"); | |
15951 | return; | |
15952 | } | |
43234a1e L |
15953 | names = names_mask; |
15954 | break; | |
c0f3af97 L |
15955 | default: |
15956 | abort (); | |
15957 | return; | |
15958 | } | |
c0f3af97 L |
15959 | break; |
15960 | case 256: | |
15961 | switch (bytemode) | |
15962 | { | |
15963 | case vex_mode: | |
15964 | case vex256_mode: | |
6c30d220 L |
15965 | names = names_ymm; |
15966 | break; | |
15967 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 15968 | case vex_vsib_q_w_d_mode: |
6c30d220 | 15969 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 15970 | break; |
1ba585e8 | 15971 | case mask_bd_mode: |
43234a1e | 15972 | case mask_mode: |
9889cbb1 L |
15973 | if (reg > 0x7) |
15974 | { | |
15975 | oappend ("(bad)"); | |
15976 | return; | |
15977 | } | |
43234a1e L |
15978 | names = names_mask; |
15979 | break; | |
c0f3af97 | 15980 | default: |
a37a2806 NC |
15981 | /* See PR binutils/20893 for a reproducer. */ |
15982 | oappend ("(bad)"); | |
c0f3af97 L |
15983 | return; |
15984 | } | |
c0f3af97 | 15985 | break; |
43234a1e L |
15986 | case 512: |
15987 | names = names_zmm; | |
15988 | break; | |
c0f3af97 L |
15989 | default: |
15990 | abort (); | |
15991 | break; | |
15992 | } | |
539f890d | 15993 | oappend (names[reg]); |
c0f3af97 L |
15994 | } |
15995 | ||
922d8de8 DR |
15996 | /* Get the VEX immediate byte without moving codep. */ |
15997 | ||
15998 | static unsigned char | |
ccc5981b | 15999 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
16000 | { |
16001 | int bytes_before_imm = 0; | |
16002 | ||
922d8de8 DR |
16003 | if (modrm.mod != 3) |
16004 | { | |
16005 | /* There are SIB/displacement bytes. */ | |
16006 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
6c067bbb | 16007 | { |
922d8de8 | 16008 | /* 32/64 bit address mode */ |
6c067bbb | 16009 | int base = modrm.rm; |
922d8de8 DR |
16010 | |
16011 | /* Check SIB byte. */ | |
6c067bbb RM |
16012 | if (base == 4) |
16013 | { | |
16014 | FETCH_DATA (the_info, codep + 1); | |
16015 | base = *codep & 7; | |
16016 | /* When decoding the third source, don't increase | |
16017 | bytes_before_imm as this has already been incremented | |
16018 | by one in OP_E_memory while decoding the second | |
16019 | source operand. */ | |
16020 | if (opnum == 0) | |
16021 | bytes_before_imm++; | |
16022 | } | |
16023 | ||
16024 | /* Don't increase bytes_before_imm when decoding the third source, | |
16025 | it has already been incremented by OP_E_memory while decoding | |
16026 | the second source operand. */ | |
16027 | if (opnum == 0) | |
16028 | { | |
16029 | switch (modrm.mod) | |
16030 | { | |
16031 | case 0: | |
16032 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
16033 | SIB == 5, there is a 4 byte displacement. */ | |
16034 | if (base != 5) | |
16035 | /* No displacement. */ | |
16036 | break; | |
1a0670f3 | 16037 | /* Fall through. */ |
6c067bbb RM |
16038 | case 2: |
16039 | /* 4 byte displacement. */ | |
16040 | bytes_before_imm += 4; | |
16041 | break; | |
16042 | case 1: | |
16043 | /* 1 byte displacement. */ | |
16044 | bytes_before_imm++; | |
16045 | break; | |
16046 | } | |
16047 | } | |
16048 | } | |
922d8de8 | 16049 | else |
02e647f9 SP |
16050 | { |
16051 | /* 16 bit address mode */ | |
6c067bbb RM |
16052 | /* Don't increase bytes_before_imm when decoding the third source, |
16053 | it has already been incremented by OP_E_memory while decoding | |
16054 | the second source operand. */ | |
16055 | if (opnum == 0) | |
16056 | { | |
02e647f9 SP |
16057 | switch (modrm.mod) |
16058 | { | |
16059 | case 0: | |
16060 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
16061 | if (modrm.rm != 6) | |
16062 | /* No displacement. */ | |
16063 | break; | |
1a0670f3 | 16064 | /* Fall through. */ |
02e647f9 SP |
16065 | case 2: |
16066 | /* 2 byte displacement. */ | |
16067 | bytes_before_imm += 2; | |
16068 | break; | |
16069 | case 1: | |
16070 | /* 1 byte displacement: when decoding the third source, | |
16071 | don't increase bytes_before_imm as this has already | |
16072 | been incremented by one in OP_E_memory while decoding | |
16073 | the second source operand. */ | |
16074 | if (opnum == 0) | |
16075 | bytes_before_imm++; | |
ccc5981b | 16076 | |
02e647f9 SP |
16077 | break; |
16078 | } | |
922d8de8 DR |
16079 | } |
16080 | } | |
16081 | } | |
16082 | ||
16083 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
16084 | return codep [bytes_before_imm]; | |
16085 | } | |
16086 | ||
16087 | static void | |
16088 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
16089 | { | |
b9733481 L |
16090 | const char **names; |
16091 | ||
922d8de8 DR |
16092 | if (reg == -1 && modrm.mod != 3) |
16093 | { | |
16094 | OP_E_memory (bytemode, sizeflag); | |
16095 | return; | |
16096 | } | |
16097 | else | |
16098 | { | |
16099 | if (reg == -1) | |
16100 | { | |
16101 | reg = modrm.rm; | |
16102 | USED_REX (REX_B); | |
16103 | if (rex & REX_B) | |
16104 | reg += 8; | |
16105 | } | |
5f847646 JB |
16106 | if (address_mode != mode_64bit) |
16107 | reg &= 7; | |
922d8de8 DR |
16108 | } |
16109 | ||
16110 | switch (vex.length) | |
16111 | { | |
16112 | case 128: | |
b9733481 | 16113 | names = names_xmm; |
922d8de8 DR |
16114 | break; |
16115 | case 256: | |
b9733481 | 16116 | names = names_ymm; |
922d8de8 DR |
16117 | break; |
16118 | default: | |
16119 | abort (); | |
16120 | } | |
b9733481 | 16121 | oappend (names[reg]); |
922d8de8 DR |
16122 | } |
16123 | ||
a683cc34 SP |
16124 | static void |
16125 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
16126 | { | |
16127 | int reg = -1; | |
16128 | static unsigned char vex_imm8; | |
16129 | ||
16130 | if (vex_w_done == 0) | |
16131 | { | |
16132 | vex_w_done = 1; | |
16133 | ||
16134 | /* Skip mod/rm byte. */ | |
16135 | MODRM_CHECK; | |
16136 | codep++; | |
16137 | ||
16138 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
16139 | ||
16140 | if (vex.w) | |
16141 | reg = vex_imm8 >> 4; | |
16142 | ||
16143 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16144 | } | |
16145 | else if (vex_w_done == 1) | |
16146 | { | |
16147 | vex_w_done = 2; | |
16148 | ||
16149 | if (!vex.w) | |
16150 | reg = vex_imm8 >> 4; | |
16151 | ||
16152 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16153 | } | |
16154 | else | |
16155 | { | |
16156 | /* Output the imm8 directly. */ | |
16157 | scratchbuf[0] = '$'; | |
16158 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
9ce09ba2 | 16159 | oappend_maybe_intel (scratchbuf); |
a683cc34 SP |
16160 | scratchbuf[0] = '\0'; |
16161 | codep++; | |
16162 | } | |
16163 | } | |
16164 | ||
5dd85c99 SP |
16165 | static void |
16166 | OP_Vex_2src (int bytemode, int sizeflag) | |
16167 | { | |
16168 | if (modrm.mod == 3) | |
16169 | { | |
b9733481 | 16170 | int reg = modrm.rm; |
5dd85c99 | 16171 | USED_REX (REX_B); |
b9733481 L |
16172 | if (rex & REX_B) |
16173 | reg += 8; | |
16174 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
16175 | } |
16176 | else | |
16177 | { | |
16178 | if (intel_syntax | |
16179 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
16180 | { | |
16181 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16182 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16183 | } | |
16184 | OP_E (bytemode, sizeflag); | |
16185 | } | |
16186 | } | |
16187 | ||
16188 | static void | |
16189 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
16190 | { | |
16191 | if (modrm.mod == 3) | |
16192 | { | |
16193 | /* Skip mod/rm byte. */ | |
16194 | MODRM_CHECK; | |
16195 | codep++; | |
16196 | } | |
16197 | ||
16198 | if (vex.w) | |
5f847646 JB |
16199 | { |
16200 | unsigned int reg = vex.register_specifier; | |
63c6fc6c | 16201 | vex.register_specifier = 0; |
5f847646 JB |
16202 | |
16203 | if (address_mode != mode_64bit) | |
16204 | reg &= 7; | |
16205 | oappend (names_xmm[reg]); | |
16206 | } | |
5dd85c99 SP |
16207 | else |
16208 | OP_Vex_2src (bytemode, sizeflag); | |
16209 | } | |
16210 | ||
16211 | static void | |
16212 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
16213 | { | |
16214 | if (vex.w) | |
16215 | OP_Vex_2src (bytemode, sizeflag); | |
16216 | else | |
5f847646 JB |
16217 | { |
16218 | unsigned int reg = vex.register_specifier; | |
63c6fc6c | 16219 | vex.register_specifier = 0; |
5f847646 JB |
16220 | |
16221 | if (address_mode != mode_64bit) | |
16222 | reg &= 7; | |
16223 | oappend (names_xmm[reg]); | |
16224 | } | |
5dd85c99 SP |
16225 | } |
16226 | ||
922d8de8 DR |
16227 | static void |
16228 | OP_EX_VexW (int bytemode, int sizeflag) | |
16229 | { | |
16230 | int reg = -1; | |
16231 | ||
16232 | if (!vex_w_done) | |
16233 | { | |
41effecb SP |
16234 | /* Skip mod/rm byte. */ |
16235 | MODRM_CHECK; | |
16236 | codep++; | |
16237 | ||
922d8de8 | 16238 | if (vex.w) |
ccc5981b | 16239 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
16240 | } |
16241 | else | |
16242 | { | |
16243 | if (!vex.w) | |
ccc5981b | 16244 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
16245 | } |
16246 | ||
16247 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
922d8de8 | 16248 | |
3a2430e0 JB |
16249 | if (vex_w_done) |
16250 | codep++; | |
16251 | vex_w_done = 1; | |
922d8de8 DR |
16252 | } |
16253 | ||
c0f3af97 L |
16254 | static void |
16255 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16256 | { | |
16257 | int reg; | |
b9733481 L |
16258 | const char **names; |
16259 | ||
c0f3af97 L |
16260 | FETCH_DATA (the_info, codep + 1); |
16261 | reg = *codep++; | |
16262 | ||
16263 | if (bytemode != x_mode) | |
16264 | abort (); | |
16265 | ||
c0f3af97 | 16266 | reg >>= 4; |
5f847646 JB |
16267 | if (address_mode != mode_64bit) |
16268 | reg &= 7; | |
dae39acc | 16269 | |
c0f3af97 L |
16270 | switch (vex.length) |
16271 | { | |
16272 | case 128: | |
b9733481 | 16273 | names = names_xmm; |
c0f3af97 L |
16274 | break; |
16275 | case 256: | |
b9733481 | 16276 | names = names_ymm; |
c0f3af97 L |
16277 | break; |
16278 | default: | |
16279 | abort (); | |
16280 | } | |
b9733481 | 16281 | oappend (names[reg]); |
c0f3af97 L |
16282 | } |
16283 | ||
922d8de8 DR |
16284 | static void |
16285 | OP_XMM_VexW (int bytemode, int sizeflag) | |
16286 | { | |
16287 | /* Turn off the REX.W bit since it is used for swapping operands | |
16288 | now. */ | |
16289 | rex &= ~REX_W; | |
16290 | OP_XMM (bytemode, sizeflag); | |
16291 | } | |
16292 | ||
c0f3af97 L |
16293 | static void |
16294 | OP_EX_Vex (int bytemode, int sizeflag) | |
16295 | { | |
16296 | if (modrm.mod != 3) | |
63c6fc6c | 16297 | need_vex_reg = 0; |
c0f3af97 L |
16298 | OP_EX (bytemode, sizeflag); |
16299 | } | |
16300 | ||
16301 | static void | |
16302 | OP_XMM_Vex (int bytemode, int sizeflag) | |
16303 | { | |
16304 | if (modrm.mod != 3) | |
63c6fc6c | 16305 | need_vex_reg = 0; |
c0f3af97 L |
16306 | OP_XMM (bytemode, sizeflag); |
16307 | } | |
16308 | ||
ea397f5b L |
16309 | static struct op vex_cmp_op[] = |
16310 | { | |
16311 | { STRING_COMMA_LEN ("eq") }, | |
16312 | { STRING_COMMA_LEN ("lt") }, | |
16313 | { STRING_COMMA_LEN ("le") }, | |
16314 | { STRING_COMMA_LEN ("unord") }, | |
16315 | { STRING_COMMA_LEN ("neq") }, | |
16316 | { STRING_COMMA_LEN ("nlt") }, | |
16317 | { STRING_COMMA_LEN ("nle") }, | |
16318 | { STRING_COMMA_LEN ("ord") }, | |
16319 | { STRING_COMMA_LEN ("eq_uq") }, | |
16320 | { STRING_COMMA_LEN ("nge") }, | |
16321 | { STRING_COMMA_LEN ("ngt") }, | |
16322 | { STRING_COMMA_LEN ("false") }, | |
16323 | { STRING_COMMA_LEN ("neq_oq") }, | |
16324 | { STRING_COMMA_LEN ("ge") }, | |
16325 | { STRING_COMMA_LEN ("gt") }, | |
16326 | { STRING_COMMA_LEN ("true") }, | |
16327 | { STRING_COMMA_LEN ("eq_os") }, | |
16328 | { STRING_COMMA_LEN ("lt_oq") }, | |
16329 | { STRING_COMMA_LEN ("le_oq") }, | |
16330 | { STRING_COMMA_LEN ("unord_s") }, | |
16331 | { STRING_COMMA_LEN ("neq_us") }, | |
16332 | { STRING_COMMA_LEN ("nlt_uq") }, | |
16333 | { STRING_COMMA_LEN ("nle_uq") }, | |
16334 | { STRING_COMMA_LEN ("ord_s") }, | |
16335 | { STRING_COMMA_LEN ("eq_us") }, | |
16336 | { STRING_COMMA_LEN ("nge_uq") }, | |
16337 | { STRING_COMMA_LEN ("ngt_uq") }, | |
16338 | { STRING_COMMA_LEN ("false_os") }, | |
16339 | { STRING_COMMA_LEN ("neq_os") }, | |
16340 | { STRING_COMMA_LEN ("ge_oq") }, | |
16341 | { STRING_COMMA_LEN ("gt_oq") }, | |
16342 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
16343 | }; |
16344 | ||
16345 | static void | |
16346 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16347 | { | |
16348 | unsigned int cmp_type; | |
16349 | ||
16350 | FETCH_DATA (the_info, codep + 1); | |
16351 | cmp_type = *codep++ & 0xff; | |
16352 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
16353 | { | |
16354 | char suffix [3]; | |
ea397f5b | 16355 | char *p = mnemonicendp - 2; |
c0f3af97 L |
16356 | suffix[0] = p[0]; |
16357 | suffix[1] = p[1]; | |
16358 | suffix[2] = '\0'; | |
ea397f5b L |
16359 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
16360 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
16361 | } |
16362 | else | |
16363 | { | |
16364 | /* We have a reserved extension byte. Output it directly. */ | |
16365 | scratchbuf[0] = '$'; | |
16366 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16367 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16368 | scratchbuf[0] = '\0'; |
16369 | } | |
16370 | } | |
16371 | ||
43234a1e L |
16372 | static void |
16373 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16374 | int sizeflag ATTRIBUTE_UNUSED) | |
16375 | { | |
16376 | unsigned int cmp_type; | |
16377 | ||
16378 | if (!vex.evex) | |
16379 | abort (); | |
16380 | ||
16381 | FETCH_DATA (the_info, codep + 1); | |
16382 | cmp_type = *codep++ & 0xff; | |
16383 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
16384 | If it's the case, print suffix, otherwise - print the immediate. */ | |
16385 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
16386 | && cmp_type != 3 | |
16387 | && cmp_type != 7) | |
16388 | { | |
16389 | char suffix [3]; | |
16390 | char *p = mnemonicendp - 2; | |
16391 | ||
16392 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
16393 | if (p[0] == 'p') | |
16394 | { | |
16395 | p++; | |
16396 | suffix[0] = p[0]; | |
16397 | suffix[1] = '\0'; | |
16398 | } | |
16399 | else | |
16400 | { | |
16401 | suffix[0] = p[0]; | |
16402 | suffix[1] = p[1]; | |
16403 | suffix[2] = '\0'; | |
16404 | } | |
16405 | ||
16406 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
16407 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
16408 | } | |
be92cb14 JB |
16409 | else |
16410 | { | |
16411 | /* We have a reserved extension byte. Output it directly. */ | |
16412 | scratchbuf[0] = '$'; | |
16413 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
16414 | oappend_maybe_intel (scratchbuf); | |
16415 | scratchbuf[0] = '\0'; | |
16416 | } | |
16417 | } | |
16418 | ||
16419 | static const struct op xop_cmp_op[] = | |
16420 | { | |
16421 | { STRING_COMMA_LEN ("lt") }, | |
16422 | { STRING_COMMA_LEN ("le") }, | |
16423 | { STRING_COMMA_LEN ("gt") }, | |
16424 | { STRING_COMMA_LEN ("ge") }, | |
16425 | { STRING_COMMA_LEN ("eq") }, | |
16426 | { STRING_COMMA_LEN ("neq") }, | |
16427 | { STRING_COMMA_LEN ("false") }, | |
16428 | { STRING_COMMA_LEN ("true") } | |
16429 | }; | |
16430 | ||
16431 | static void | |
16432 | VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16433 | int sizeflag ATTRIBUTE_UNUSED) | |
16434 | { | |
16435 | unsigned int cmp_type; | |
16436 | ||
16437 | FETCH_DATA (the_info, codep + 1); | |
16438 | cmp_type = *codep++ & 0xff; | |
16439 | if (cmp_type < ARRAY_SIZE (xop_cmp_op)) | |
16440 | { | |
16441 | char suffix[3]; | |
16442 | char *p = mnemonicendp - 2; | |
16443 | ||
16444 | /* vpcom* can have both one- and two-lettered suffix. */ | |
16445 | if (p[0] == 'm') | |
16446 | { | |
16447 | p++; | |
16448 | suffix[0] = p[0]; | |
16449 | suffix[1] = '\0'; | |
16450 | } | |
16451 | else | |
16452 | { | |
16453 | suffix[0] = p[0]; | |
16454 | suffix[1] = p[1]; | |
16455 | suffix[2] = '\0'; | |
16456 | } | |
16457 | ||
16458 | sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); | |
16459 | mnemonicendp += xop_cmp_op[cmp_type].len; | |
16460 | } | |
43234a1e L |
16461 | else |
16462 | { | |
16463 | /* We have a reserved extension byte. Output it directly. */ | |
16464 | scratchbuf[0] = '$'; | |
16465 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16466 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
16467 | scratchbuf[0] = '\0'; |
16468 | } | |
16469 | } | |
16470 | ||
ea397f5b L |
16471 | static const struct op pclmul_op[] = |
16472 | { | |
16473 | { STRING_COMMA_LEN ("lql") }, | |
16474 | { STRING_COMMA_LEN ("hql") }, | |
16475 | { STRING_COMMA_LEN ("lqh") }, | |
16476 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
16477 | }; |
16478 | ||
16479 | static void | |
16480 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16481 | int sizeflag ATTRIBUTE_UNUSED) | |
16482 | { | |
16483 | unsigned int pclmul_type; | |
16484 | ||
16485 | FETCH_DATA (the_info, codep + 1); | |
16486 | pclmul_type = *codep++ & 0xff; | |
16487 | switch (pclmul_type) | |
16488 | { | |
16489 | case 0x10: | |
16490 | pclmul_type = 2; | |
16491 | break; | |
16492 | case 0x11: | |
16493 | pclmul_type = 3; | |
16494 | break; | |
16495 | default: | |
16496 | break; | |
7bb15c6f | 16497 | } |
c0f3af97 L |
16498 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
16499 | { | |
16500 | char suffix [4]; | |
ea397f5b | 16501 | char *p = mnemonicendp - 3; |
c0f3af97 L |
16502 | suffix[0] = p[0]; |
16503 | suffix[1] = p[1]; | |
16504 | suffix[2] = p[2]; | |
16505 | suffix[3] = '\0'; | |
ea397f5b L |
16506 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
16507 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
16508 | } |
16509 | else | |
16510 | { | |
16511 | /* We have a reserved extension byte. Output it directly. */ | |
16512 | scratchbuf[0] = '$'; | |
16513 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 16514 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16515 | scratchbuf[0] = '\0'; |
16516 | } | |
16517 | } | |
16518 | ||
f1f8f695 L |
16519 | static void |
16520 | MOVBE_Fixup (int bytemode, int sizeflag) | |
16521 | { | |
16522 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 16523 | char *p = mnemonicendp; |
f1f8f695 L |
16524 | |
16525 | switch (bytemode) | |
16526 | { | |
16527 | case v_mode: | |
16528 | if (intel_syntax) | |
ea397f5b | 16529 | goto skip; |
f1f8f695 L |
16530 | |
16531 | USED_REX (REX_W); | |
16532 | if (sizeflag & SUFFIX_ALWAYS) | |
16533 | { | |
16534 | if (rex & REX_W) | |
16535 | *p++ = 'q'; | |
f1f8f695 | 16536 | else |
f16cd0d5 L |
16537 | { |
16538 | if (sizeflag & DFLAG) | |
16539 | *p++ = 'l'; | |
16540 | else | |
16541 | *p++ = 'w'; | |
16542 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16543 | } | |
f1f8f695 | 16544 | } |
f1f8f695 L |
16545 | break; |
16546 | default: | |
16547 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16548 | break; | |
16549 | } | |
ea397f5b | 16550 | mnemonicendp = p; |
f1f8f695 L |
16551 | *p = '\0'; |
16552 | ||
dc1e8a47 | 16553 | skip: |
f1f8f695 L |
16554 | OP_M (bytemode, sizeflag); |
16555 | } | |
f88c9eb0 | 16556 | |
bc31405e L |
16557 | static void |
16558 | MOVSXD_Fixup (int bytemode, int sizeflag) | |
16559 | { | |
16560 | /* Add proper suffix to "movsxd". */ | |
16561 | char *p = mnemonicendp; | |
16562 | ||
16563 | switch (bytemode) | |
16564 | { | |
16565 | case movsxd_mode: | |
16566 | if (intel_syntax) | |
16567 | { | |
16568 | *p++ = 'x'; | |
16569 | *p++ = 'd'; | |
16570 | goto skip; | |
16571 | } | |
16572 | ||
16573 | USED_REX (REX_W); | |
16574 | if (rex & REX_W) | |
16575 | { | |
16576 | *p++ = 'l'; | |
16577 | *p++ = 'q'; | |
16578 | } | |
16579 | else | |
16580 | { | |
16581 | *p++ = 'x'; | |
16582 | *p++ = 'd'; | |
16583 | } | |
16584 | break; | |
16585 | default: | |
16586 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16587 | break; | |
16588 | } | |
16589 | ||
dc1e8a47 | 16590 | skip: |
bc31405e L |
16591 | mnemonicendp = p; |
16592 | *p = '\0'; | |
16593 | OP_E (bytemode, sizeflag); | |
16594 | } | |
16595 | ||
f88c9eb0 SP |
16596 | static void |
16597 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16598 | { | |
16599 | int reg; | |
16600 | const char **names; | |
16601 | ||
16602 | /* Skip mod/rm byte. */ | |
16603 | MODRM_CHECK; | |
16604 | codep++; | |
16605 | ||
390a6789 | 16606 | if (rex & REX_W) |
f88c9eb0 | 16607 | names = names64; |
f88c9eb0 | 16608 | else |
ce7d077e | 16609 | names = names32; |
f88c9eb0 SP |
16610 | |
16611 | reg = modrm.rm; | |
16612 | USED_REX (REX_B); | |
16613 | if (rex & REX_B) | |
16614 | reg += 8; | |
16615 | ||
16616 | oappend (names[reg]); | |
16617 | } | |
16618 | ||
16619 | static void | |
16620 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16621 | { | |
16622 | const char **names; | |
5f847646 | 16623 | unsigned int reg = vex.register_specifier; |
63c6fc6c | 16624 | vex.register_specifier = 0; |
f88c9eb0 | 16625 | |
390a6789 | 16626 | if (rex & REX_W) |
f88c9eb0 | 16627 | names = names64; |
f88c9eb0 | 16628 | else |
ce7d077e | 16629 | names = names32; |
f88c9eb0 | 16630 | |
5f847646 JB |
16631 | if (address_mode != mode_64bit) |
16632 | reg &= 7; | |
16633 | oappend (names[reg]); | |
f88c9eb0 | 16634 | } |
43234a1e L |
16635 | |
16636 | static void | |
16637 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16638 | { | |
16639 | if (!vex.evex | |
1ba585e8 | 16640 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
16641 | abort (); |
16642 | ||
16643 | USED_REX (REX_R); | |
16644 | if ((rex & REX_R) != 0 || !vex.r) | |
16645 | { | |
16646 | BadOp (); | |
16647 | return; | |
16648 | } | |
16649 | ||
16650 | oappend (names_mask [modrm.reg]); | |
16651 | } | |
16652 | ||
16653 | static void | |
16654 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16655 | { | |
16656 | if (!vex.evex | |
16657 | || (bytemode != evex_rounding_mode | |
70df6fc9 | 16658 | && bytemode != evex_rounding_64_mode |
43234a1e L |
16659 | && bytemode != evex_sae_mode)) |
16660 | abort (); | |
16661 | if (modrm.mod == 3 && vex.b) | |
16662 | switch (bytemode) | |
16663 | { | |
70df6fc9 L |
16664 | case evex_rounding_64_mode: |
16665 | if (address_mode != mode_64bit) | |
16666 | { | |
16667 | oappend ("(bad)"); | |
16668 | break; | |
16669 | } | |
16670 | /* Fall through. */ | |
43234a1e L |
16671 | case evex_rounding_mode: |
16672 | oappend (names_rounding[vex.ll]); | |
16673 | break; | |
16674 | case evex_sae_mode: | |
16675 | oappend ("{sae}"); | |
16676 | break; | |
16677 | default: | |
16678 | break; | |
16679 | } | |
16680 | } |