Commit | Line | Data |
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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
219d1afa | 2 | Copyright (C) 1988-2018 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
88c1242d | 36 | #include "disassemble.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
252b5132 RH |
40 | |
41 | #include <setjmp.h> | |
42 | ||
26ca5450 AJ |
43 | static int print_insn (bfd_vma, disassemble_info *); |
44 | static void dofloat (int); | |
45 | static void OP_ST (int, int); | |
46 | static void OP_STi (int, int); | |
47 | static int putop (const char *, int); | |
48 | static void oappend (const char *); | |
49 | static void append_seg (void); | |
50 | static void OP_indirE (int, int); | |
51 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 52 | static void OP_E_register (int, int); |
c1e679ec | 53 | static void OP_E_memory (int, int); |
5d669648 | 54 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
55 | static void OP_E (int, int); |
56 | static void OP_G (int, int); | |
57 | static bfd_vma get64 (void); | |
58 | static bfd_signed_vma get32 (void); | |
59 | static bfd_signed_vma get32s (void); | |
60 | static int get16 (void); | |
61 | static void set_op (bfd_vma, int); | |
b844680a | 62 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
63 | static void OP_REG (int, int); |
64 | static void OP_IMREG (int, int); | |
65 | static void OP_I (int, int); | |
66 | static void OP_I64 (int, int); | |
67 | static void OP_sI (int, int); | |
68 | static void OP_J (int, int); | |
69 | static void OP_SEG (int, int); | |
70 | static void OP_DIR (int, int); | |
71 | static void OP_OFF (int, int); | |
72 | static void OP_OFF64 (int, int); | |
73 | static void ptr_reg (int, int); | |
74 | static void OP_ESreg (int, int); | |
75 | static void OP_DSreg (int, int); | |
76 | static void OP_C (int, int); | |
77 | static void OP_D (int, int); | |
78 | static void OP_T (int, int); | |
6f74c397 | 79 | static void OP_R (int, int); |
26ca5450 AJ |
80 | static void OP_MMX (int, int); |
81 | static void OP_XMM (int, int); | |
82 | static void OP_EM (int, int); | |
83 | static void OP_EX (int, int); | |
4d9567e0 MM |
84 | static void OP_EMC (int,int); |
85 | static void OP_MXC (int,int); | |
26ca5450 AJ |
86 | static void OP_MS (int, int); |
87 | static void OP_XS (int, int); | |
cc0ec051 | 88 | static void OP_M (int, int); |
c0f3af97 L |
89 | static void OP_VEX (int, int); |
90 | static void OP_EX_Vex (int, int); | |
922d8de8 | 91 | static void OP_EX_VexW (int, int); |
a683cc34 | 92 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 93 | static void OP_XMM_Vex (int, int); |
922d8de8 | 94 | static void OP_XMM_VexW (int, int); |
43234a1e | 95 | static void OP_Rounding (int, int); |
c0f3af97 L |
96 | static void OP_REG_VexI4 (int, int); |
97 | static void PCLMUL_Fixup (int, int); | |
c0f3af97 L |
98 | static void VZERO_Fixup (int, int); |
99 | static void VCMP_Fixup (int, int); | |
43234a1e | 100 | static void VPCMP_Fixup (int, int); |
be92cb14 | 101 | static void VPCOM_Fixup (int, int); |
cc0ec051 | 102 | static void OP_0f07 (int, int); |
b844680a L |
103 | static void OP_Monitor (int, int); |
104 | static void OP_Mwait (int, int); | |
9916071f | 105 | static void OP_Mwaitx (int, int); |
46e883c5 L |
106 | static void NOP_Fixup1 (int, int); |
107 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 108 | static void OP_3DNowSuffix (int, int); |
ad19981d | 109 | static void CMP_Fixup (int, int); |
26ca5450 | 110 | static void BadOp (void); |
35c52694 | 111 | static void REP_Fixup (int, int); |
7e8b059b | 112 | static void BND_Fixup (int, int); |
04ef582a | 113 | static void NOTRACK_Fixup (int, int); |
42164a71 L |
114 | static void HLE_Fixup1 (int, int); |
115 | static void HLE_Fixup2 (int, int); | |
116 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 117 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 118 | static void XMM_Fixup (int, int); |
381d071f | 119 | static void CRC32_Fixup (int, int); |
eacc9c89 | 120 | static void FXSAVE_Fixup (int, int); |
15c7c1d8 | 121 | static void PCMPESTR_Fixup (int, int); |
f88c9eb0 SP |
122 | static void OP_LWPCB_E (int, int); |
123 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
124 | static void OP_Vex_2src_1 (int, int); |
125 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 126 | |
f1f8f695 | 127 | static void MOVBE_Fixup (int, int); |
252b5132 | 128 | |
43234a1e L |
129 | static void OP_Mask (int, int); |
130 | ||
6608db57 | 131 | struct dis_private { |
252b5132 RH |
132 | /* Points to first byte not fetched. */ |
133 | bfd_byte *max_fetched; | |
0b1cf022 | 134 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 135 | bfd_vma insn_start; |
e396998b | 136 | int orig_sizeflag; |
8df14d78 | 137 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
138 | }; |
139 | ||
cb712a9e L |
140 | enum address_mode |
141 | { | |
142 | mode_16bit, | |
143 | mode_32bit, | |
144 | mode_64bit | |
145 | }; | |
146 | ||
147 | enum address_mode address_mode; | |
52b15da3 | 148 | |
5076851f ILT |
149 | /* Flags for the prefixes for the current instruction. See below. */ |
150 | static int prefixes; | |
151 | ||
52b15da3 JH |
152 | /* REX prefix the current instruction. See below. */ |
153 | static int rex; | |
154 | /* Bits of REX we've already used. */ | |
155 | static int rex_used; | |
d869730d | 156 | /* REX bits in original REX prefix ignored. */ |
c0f3af97 | 157 | static int rex_ignored; |
52b15da3 JH |
158 | /* Mark parts used in the REX prefix. When we are testing for |
159 | empty prefix (for 8bit register REX extension), just mask it | |
160 | out. Otherwise test for REX bit is excuse for existence of REX | |
161 | only in case value is nonzero. */ | |
162 | #define USED_REX(value) \ | |
163 | { \ | |
164 | if (value) \ | |
161a04f6 L |
165 | { \ |
166 | if ((rex & value)) \ | |
167 | rex_used |= (value) | REX_OPCODE; \ | |
168 | } \ | |
52b15da3 | 169 | else \ |
161a04f6 | 170 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
171 | } |
172 | ||
7d421014 ILT |
173 | /* Flags for prefixes which we somehow handled when printing the |
174 | current instruction. */ | |
175 | static int used_prefixes; | |
176 | ||
5076851f ILT |
177 | /* Flags stored in PREFIXES. */ |
178 | #define PREFIX_REPZ 1 | |
179 | #define PREFIX_REPNZ 2 | |
180 | #define PREFIX_LOCK 4 | |
181 | #define PREFIX_CS 8 | |
182 | #define PREFIX_SS 0x10 | |
183 | #define PREFIX_DS 0x20 | |
184 | #define PREFIX_ES 0x40 | |
185 | #define PREFIX_FS 0x80 | |
186 | #define PREFIX_GS 0x100 | |
187 | #define PREFIX_DATA 0x200 | |
188 | #define PREFIX_ADDR 0x400 | |
189 | #define PREFIX_FWAIT 0x800 | |
190 | ||
252b5132 RH |
191 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
192 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
193 | on error. */ | |
194 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 195 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
196 | ? 1 : fetch_data ((info), (addr))) |
197 | ||
198 | static int | |
26ca5450 | 199 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
200 | { |
201 | int status; | |
6608db57 | 202 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
203 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
204 | ||
0b1cf022 | 205 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
206 | status = (*info->read_memory_func) (start, |
207 | priv->max_fetched, | |
208 | addr - priv->max_fetched, | |
209 | info); | |
210 | else | |
211 | status = -1; | |
252b5132 RH |
212 | if (status != 0) |
213 | { | |
7d421014 | 214 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
215 | print_insn_i386 will do something sensible. Otherwise, print |
216 | an error. We do that here because this is where we know | |
217 | STATUS. */ | |
7d421014 | 218 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 219 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 220 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
221 | } |
222 | else | |
223 | priv->max_fetched = addr; | |
224 | return 1; | |
225 | } | |
226 | ||
bf890a93 | 227 | /* Possible values for prefix requirement. */ |
507bd325 L |
228 | #define PREFIX_IGNORED_SHIFT 16 |
229 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
230 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
231 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
232 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
233 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
234 | ||
235 | /* Opcode prefixes. */ | |
236 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
237 | | PREFIX_REPNZ \ | |
238 | | PREFIX_DATA) | |
239 | ||
240 | /* Prefixes ignored. */ | |
241 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
242 | | PREFIX_IGNORED_REPNZ \ | |
243 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 244 | |
ce518a5f | 245 | #define XX { NULL, 0 } |
507bd325 | 246 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
247 | |
248 | #define Eb { OP_E, b_mode } | |
7e8b059b | 249 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 250 | #define EbS { OP_E, b_swap_mode } |
9f79e886 | 251 | #define EbndS { OP_E, bnd_swap_mode } |
ce518a5f | 252 | #define Ev { OP_E, v_mode } |
7e8b059b | 253 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 254 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
255 | #define Ed { OP_E, d_mode } |
256 | #define Edq { OP_E, dq_mode } | |
257 | #define Edqw { OP_E, dqw_mode } | |
42903f7f | 258 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
259 | #define Edb { OP_E, db_mode } |
260 | #define Edw { OP_E, dw_mode } | |
42903f7f | 261 | #define Edqd { OP_E, dqd_mode } |
09335d05 | 262 | #define Eq { OP_E, q_mode } |
07f5af7d | 263 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
264 | #define indirEp { OP_indirE, f_mode } |
265 | #define stackEv { OP_E, stack_v_mode } | |
266 | #define Em { OP_E, m_mode } | |
267 | #define Ew { OP_E, w_mode } | |
268 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 269 | #define Ma { OP_M, a_mode } |
b844680a | 270 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 271 | #define Md { OP_M, d_mode } |
f1f8f695 | 272 | #define Mo { OP_M, o_mode } |
ce518a5f L |
273 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
274 | #define Mq { OP_M, q_mode } | |
4ee52178 | 275 | #define Mx { OP_M, x_mode } |
c0f3af97 | 276 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 277 | #define Gb { OP_G, b_mode } |
7e8b059b | 278 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
279 | #define Gv { OP_G, v_mode } |
280 | #define Gd { OP_G, d_mode } | |
281 | #define Gdq { OP_G, dq_mode } | |
282 | #define Gm { OP_G, m_mode } | |
283 | #define Gw { OP_G, w_mode } | |
6f74c397 | 284 | #define Rd { OP_R, d_mode } |
43234a1e | 285 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 286 | #define Rm { OP_R, m_mode } |
ce518a5f L |
287 | #define Ib { OP_I, b_mode } |
288 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 289 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 290 | #define Iv { OP_I, v_mode } |
7bb15c6f | 291 | #define sIv { OP_sI, v_mode } |
ce518a5f L |
292 | #define Iq { OP_I, q_mode } |
293 | #define Iv64 { OP_I64, v_mode } | |
294 | #define Iw { OP_I, w_mode } | |
295 | #define I1 { OP_I, const_1_mode } | |
296 | #define Jb { OP_J, b_mode } | |
297 | #define Jv { OP_J, v_mode } | |
298 | #define Cm { OP_C, m_mode } | |
299 | #define Dm { OP_D, m_mode } | |
300 | #define Td { OP_T, d_mode } | |
b844680a | 301 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
302 | |
303 | #define RMeAX { OP_REG, eAX_reg } | |
304 | #define RMeBX { OP_REG, eBX_reg } | |
305 | #define RMeCX { OP_REG, eCX_reg } | |
306 | #define RMeDX { OP_REG, eDX_reg } | |
307 | #define RMeSP { OP_REG, eSP_reg } | |
308 | #define RMeBP { OP_REG, eBP_reg } | |
309 | #define RMeSI { OP_REG, eSI_reg } | |
310 | #define RMeDI { OP_REG, eDI_reg } | |
311 | #define RMrAX { OP_REG, rAX_reg } | |
312 | #define RMrBX { OP_REG, rBX_reg } | |
313 | #define RMrCX { OP_REG, rCX_reg } | |
314 | #define RMrDX { OP_REG, rDX_reg } | |
315 | #define RMrSP { OP_REG, rSP_reg } | |
316 | #define RMrBP { OP_REG, rBP_reg } | |
317 | #define RMrSI { OP_REG, rSI_reg } | |
318 | #define RMrDI { OP_REG, rDI_reg } | |
319 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
320 | #define RMCL { OP_REG, cl_reg } |
321 | #define RMDL { OP_REG, dl_reg } | |
322 | #define RMBL { OP_REG, bl_reg } | |
323 | #define RMAH { OP_REG, ah_reg } | |
324 | #define RMCH { OP_REG, ch_reg } | |
325 | #define RMDH { OP_REG, dh_reg } | |
326 | #define RMBH { OP_REG, bh_reg } | |
327 | #define RMAX { OP_REG, ax_reg } | |
328 | #define RMDX { OP_REG, dx_reg } | |
329 | ||
330 | #define eAX { OP_IMREG, eAX_reg } | |
331 | #define eBX { OP_IMREG, eBX_reg } | |
332 | #define eCX { OP_IMREG, eCX_reg } | |
333 | #define eDX { OP_IMREG, eDX_reg } | |
334 | #define eSP { OP_IMREG, eSP_reg } | |
335 | #define eBP { OP_IMREG, eBP_reg } | |
336 | #define eSI { OP_IMREG, eSI_reg } | |
337 | #define eDI { OP_IMREG, eDI_reg } | |
338 | #define AL { OP_IMREG, al_reg } | |
339 | #define CL { OP_IMREG, cl_reg } | |
340 | #define DL { OP_IMREG, dl_reg } | |
341 | #define BL { OP_IMREG, bl_reg } | |
342 | #define AH { OP_IMREG, ah_reg } | |
343 | #define CH { OP_IMREG, ch_reg } | |
344 | #define DH { OP_IMREG, dh_reg } | |
345 | #define BH { OP_IMREG, bh_reg } | |
346 | #define AX { OP_IMREG, ax_reg } | |
347 | #define DX { OP_IMREG, dx_reg } | |
348 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
349 | #define indirDX { OP_IMREG, indir_dx_reg } | |
350 | ||
351 | #define Sw { OP_SEG, w_mode } | |
352 | #define Sv { OP_SEG, v_mode } | |
353 | #define Ap { OP_DIR, 0 } | |
354 | #define Ob { OP_OFF64, b_mode } | |
355 | #define Ov { OP_OFF64, v_mode } | |
356 | #define Xb { OP_DSreg, eSI_reg } | |
357 | #define Xv { OP_DSreg, eSI_reg } | |
358 | #define Xz { OP_DSreg, eSI_reg } | |
359 | #define Yb { OP_ESreg, eDI_reg } | |
360 | #define Yv { OP_ESreg, eDI_reg } | |
361 | #define DSBX { OP_DSreg, eBX_reg } | |
362 | ||
363 | #define es { OP_REG, es_reg } | |
364 | #define ss { OP_REG, ss_reg } | |
365 | #define cs { OP_REG, cs_reg } | |
366 | #define ds { OP_REG, ds_reg } | |
367 | #define fs { OP_REG, fs_reg } | |
368 | #define gs { OP_REG, gs_reg } | |
369 | ||
370 | #define MX { OP_MMX, 0 } | |
371 | #define XM { OP_XMM, 0 } | |
539f890d | 372 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 373 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 374 | #define XMM { OP_XMM, xmm_mode } |
43234a1e | 375 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 376 | #define EM { OP_EM, v_mode } |
b6169b20 | 377 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 378 | #define EMd { OP_EM, d_mode } |
14051056 | 379 | #define EMx { OP_EM, x_mode } |
53467f57 | 380 | #define EXbScalar { OP_EX, b_scalar_mode } |
8976381e | 381 | #define EXw { OP_EX, w_mode } |
53467f57 | 382 | #define EXwScalar { OP_EX, w_scalar_mode } |
09a2c6cf | 383 | #define EXd { OP_EX, d_mode } |
539f890d | 384 | #define EXdScalar { OP_EX, d_scalar_mode } |
fa99fab2 | 385 | #define EXdS { OP_EX, d_swap_mode } |
43234a1e | 386 | #define EXdScalarS { OP_EX, d_scalar_swap_mode } |
09a2c6cf | 387 | #define EXq { OP_EX, q_mode } |
539f890d L |
388 | #define EXqScalar { OP_EX, q_scalar_mode } |
389 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } | |
b6169b20 | 390 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 391 | #define EXx { OP_EX, x_mode } |
b6169b20 | 392 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 393 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 394 | #define EXymm { OP_EX, ymm_mode } |
c0f3af97 | 395 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 396 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
397 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
398 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
399 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
400 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
43234a1e | 401 | #define EXxmm_mdq { OP_EX, xmm_mdq_mode } |
6c30d220 L |
402 | #define EXxmmdw { OP_EX, xmmdw_mode } |
403 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 404 | #define EXymmq { OP_EX, ymmq_mode } |
0bfee649 | 405 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
1c480963 | 406 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
407 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
408 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
409 | #define MS { OP_MS, v_mode } |
410 | #define XS { OP_XS, v_mode } | |
09335d05 | 411 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 412 | #define MXC { OP_MXC, 0 } |
ce518a5f | 413 | #define OPSUF { OP_3DNowSuffix, 0 } |
ad19981d | 414 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 415 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 416 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
417 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
418 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 419 | |
c0f3af97 | 420 | #define Vex { OP_VEX, vex_mode } |
539f890d | 421 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 422 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
423 | #define Vex128 { OP_VEX, vex128_mode } |
424 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 425 | #define VexGdq { OP_VEX, dq_mode } |
c0f3af97 | 426 | #define EXdVex { OP_EX_Vex, d_mode } |
fa99fab2 | 427 | #define EXdVexS { OP_EX_Vex, d_swap_mode } |
539f890d | 428 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
c0f3af97 | 429 | #define EXqVex { OP_EX_Vex, q_mode } |
fa99fab2 | 430 | #define EXqVexS { OP_EX_Vex, q_swap_mode } |
539f890d | 431 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
922d8de8 DR |
432 | #define EXVexW { OP_EX_VexW, x_mode } |
433 | #define EXdVexW { OP_EX_VexW, d_mode } | |
434 | #define EXqVexW { OP_EX_VexW, q_mode } | |
a683cc34 | 435 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
c0f3af97 | 436 | #define XMVex { OP_XMM_Vex, 0 } |
539f890d | 437 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 438 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
439 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
440 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
441 | #define VZERO { VZERO_Fixup, 0 } | |
442 | #define VCMP { VCMP_Fixup, 0 } | |
43234a1e | 443 | #define VPCMP { VPCMP_Fixup, 0 } |
be92cb14 | 444 | #define VPCOM { VPCOM_Fixup, 0 } |
43234a1e L |
445 | |
446 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
447 | #define EXxEVexS { OP_Rounding, evex_sae_mode } | |
448 | ||
449 | #define XMask { OP_Mask, mask_mode } | |
450 | #define MaskG { OP_G, mask_mode } | |
451 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 452 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e L |
453 | #define MaskR { OP_R, mask_mode } |
454 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 455 | |
6c30d220 | 456 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 457 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 458 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 459 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 460 | |
35c52694 | 461 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
462 | #define Xbr { REP_Fixup, eSI_reg } |
463 | #define Xvr { REP_Fixup, eSI_reg } | |
464 | #define Ybr { REP_Fixup, eDI_reg } | |
465 | #define Yvr { REP_Fixup, eDI_reg } | |
466 | #define Yzr { REP_Fixup, eDI_reg } | |
467 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
468 | #define ALr { REP_Fixup, al_reg } | |
469 | #define eAXr { REP_Fixup, eAX_reg } | |
470 | ||
42164a71 L |
471 | /* Used handle HLE prefix for lockable instructions. */ |
472 | #define Ebh1 { HLE_Fixup1, b_mode } | |
473 | #define Evh1 { HLE_Fixup1, v_mode } | |
474 | #define Ebh2 { HLE_Fixup2, b_mode } | |
475 | #define Evh2 { HLE_Fixup2, v_mode } | |
476 | #define Ebh3 { HLE_Fixup3, b_mode } | |
477 | #define Evh3 { HLE_Fixup3, v_mode } | |
478 | ||
7e8b059b | 479 | #define BND { BND_Fixup, 0 } |
04ef582a | 480 | #define NOTRACK { NOTRACK_Fixup, 0 } |
7e8b059b | 481 | |
ce518a5f L |
482 | #define cond_jump_flag { NULL, cond_jump_mode } |
483 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 484 | |
252b5132 | 485 | /* bits in sizeflag */ |
252b5132 | 486 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
487 | #define AFLAG 2 |
488 | #define DFLAG 1 | |
489 | ||
51e7da1b L |
490 | enum |
491 | { | |
492 | /* byte operand */ | |
493 | b_mode = 1, | |
494 | /* byte operand with operand swapped */ | |
3873ba12 | 495 | b_swap_mode, |
e3949f17 L |
496 | /* byte operand, sign extend like 'T' suffix */ |
497 | b_T_mode, | |
51e7da1b | 498 | /* operand size depends on prefixes */ |
3873ba12 | 499 | v_mode, |
51e7da1b | 500 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 501 | v_swap_mode, |
51e7da1b | 502 | /* word operand */ |
3873ba12 | 503 | w_mode, |
51e7da1b | 504 | /* double word operand */ |
3873ba12 | 505 | d_mode, |
51e7da1b | 506 | /* double word operand with operand swapped */ |
3873ba12 | 507 | d_swap_mode, |
51e7da1b | 508 | /* quad word operand */ |
3873ba12 | 509 | q_mode, |
51e7da1b | 510 | /* quad word operand with operand swapped */ |
3873ba12 | 511 | q_swap_mode, |
51e7da1b | 512 | /* ten-byte operand */ |
3873ba12 | 513 | t_mode, |
43234a1e L |
514 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
515 | broadcast enabled. */ | |
3873ba12 | 516 | x_mode, |
43234a1e L |
517 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
518 | evex_x_gscat_mode, | |
519 | /* Similar to x_mode, but with disabled broadcast. */ | |
520 | evex_x_nobcst_mode, | |
521 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
522 | in EVEX. */ | |
3873ba12 | 523 | x_swap_mode, |
51e7da1b | 524 | /* 16-byte XMM operand */ |
3873ba12 | 525 | xmm_mode, |
43234a1e L |
526 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
527 | memory operand (depending on vector length). Broadcast isn't | |
528 | allowed. */ | |
3873ba12 | 529 | xmmq_mode, |
43234a1e L |
530 | /* Same as xmmq_mode, but broadcast is allowed. */ |
531 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
532 | /* XMM register or byte memory operand */ |
533 | xmm_mb_mode, | |
534 | /* XMM register or word memory operand */ | |
535 | xmm_mw_mode, | |
536 | /* XMM register or double word memory operand */ | |
537 | xmm_md_mode, | |
538 | /* XMM register or quad word memory operand */ | |
539 | xmm_mq_mode, | |
43234a1e L |
540 | /* XMM register or double/quad word memory operand, depending on |
541 | VEX.W. */ | |
542 | xmm_mdq_mode, | |
543 | /* 16-byte XMM, word, double word or quad word operand. */ | |
6c30d220 | 544 | xmmdw_mode, |
43234a1e | 545 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 546 | xmmqd_mode, |
43234a1e L |
547 | /* 32-byte YMM operand */ |
548 | ymm_mode, | |
549 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 550 | ymmq_mode, |
6c30d220 L |
551 | /* 32-byte YMM or 16-byte word operand */ |
552 | ymmxmm_mode, | |
51e7da1b | 553 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 554 | m_mode, |
51e7da1b | 555 | /* pair of v_mode operands */ |
3873ba12 L |
556 | a_mode, |
557 | cond_jump_mode, | |
558 | loop_jcxz_mode, | |
7e8b059b | 559 | v_bnd_mode, |
51e7da1b | 560 | /* operand size depends on REX prefixes. */ |
3873ba12 | 561 | dq_mode, |
51e7da1b | 562 | /* registers like dq_mode, memory like w_mode. */ |
3873ba12 | 563 | dqw_mode, |
9f79e886 | 564 | /* bounds operand */ |
7e8b059b | 565 | bnd_mode, |
9f79e886 JB |
566 | /* bounds operand with operand swapped */ |
567 | bnd_swap_mode, | |
51e7da1b | 568 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
569 | f_mode, |
570 | const_1_mode, | |
07f5af7d L |
571 | /* v_mode for indirect branch opcodes. */ |
572 | indir_v_mode, | |
51e7da1b | 573 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 574 | stack_v_mode, |
51e7da1b | 575 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 576 | z_mode, |
51e7da1b | 577 | /* 16-byte operand */ |
3873ba12 | 578 | o_mode, |
51e7da1b | 579 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 580 | dqb_mode, |
1ba585e8 IT |
581 | /* registers like d_mode, memory like b_mode. */ |
582 | db_mode, | |
583 | /* registers like d_mode, memory like w_mode. */ | |
584 | dw_mode, | |
51e7da1b | 585 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 586 | dqd_mode, |
51e7da1b | 587 | /* normal vex mode */ |
3873ba12 | 588 | vex_mode, |
51e7da1b | 589 | /* 128bit vex mode */ |
3873ba12 | 590 | vex128_mode, |
51e7da1b | 591 | /* 256bit vex mode */ |
3873ba12 | 592 | vex256_mode, |
51e7da1b | 593 | /* operand size depends on the VEX.W bit. */ |
3873ba12 | 594 | vex_w_dq_mode, |
d55ee72f | 595 | |
6c30d220 L |
596 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
597 | vex_vsib_d_w_dq_mode, | |
5fc35d96 IT |
598 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
599 | vex_vsib_d_w_d_mode, | |
6c30d220 L |
600 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ |
601 | vex_vsib_q_w_dq_mode, | |
5fc35d96 IT |
602 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
603 | vex_vsib_q_w_d_mode, | |
6c30d220 | 604 | |
539f890d L |
605 | /* scalar, ignore vector length. */ |
606 | scalar_mode, | |
53467f57 IT |
607 | /* like b_mode, ignore vector length. */ |
608 | b_scalar_mode, | |
609 | /* like w_mode, ignore vector length. */ | |
610 | w_scalar_mode, | |
539f890d L |
611 | /* like d_mode, ignore vector length. */ |
612 | d_scalar_mode, | |
613 | /* like d_swap_mode, ignore vector length. */ | |
614 | d_scalar_swap_mode, | |
615 | /* like q_mode, ignore vector length. */ | |
616 | q_scalar_mode, | |
617 | /* like q_swap_mode, ignore vector length. */ | |
618 | q_scalar_swap_mode, | |
619 | /* like vex_mode, ignore vector length. */ | |
620 | vex_scalar_mode, | |
1c480963 L |
621 | /* like vex_w_dq_mode, ignore vector length. */ |
622 | vex_scalar_w_dq_mode, | |
539f890d | 623 | |
43234a1e L |
624 | /* Static rounding. */ |
625 | evex_rounding_mode, | |
626 | /* Supress all exceptions. */ | |
627 | evex_sae_mode, | |
628 | ||
629 | /* Mask register operand. */ | |
630 | mask_mode, | |
1ba585e8 IT |
631 | /* Mask register operand. */ |
632 | mask_bd_mode, | |
43234a1e | 633 | |
3873ba12 L |
634 | es_reg, |
635 | cs_reg, | |
636 | ss_reg, | |
637 | ds_reg, | |
638 | fs_reg, | |
639 | gs_reg, | |
d55ee72f | 640 | |
3873ba12 L |
641 | eAX_reg, |
642 | eCX_reg, | |
643 | eDX_reg, | |
644 | eBX_reg, | |
645 | eSP_reg, | |
646 | eBP_reg, | |
647 | eSI_reg, | |
648 | eDI_reg, | |
d55ee72f | 649 | |
3873ba12 L |
650 | al_reg, |
651 | cl_reg, | |
652 | dl_reg, | |
653 | bl_reg, | |
654 | ah_reg, | |
655 | ch_reg, | |
656 | dh_reg, | |
657 | bh_reg, | |
d55ee72f | 658 | |
3873ba12 L |
659 | ax_reg, |
660 | cx_reg, | |
661 | dx_reg, | |
662 | bx_reg, | |
663 | sp_reg, | |
664 | bp_reg, | |
665 | si_reg, | |
666 | di_reg, | |
d55ee72f | 667 | |
3873ba12 L |
668 | rAX_reg, |
669 | rCX_reg, | |
670 | rDX_reg, | |
671 | rBX_reg, | |
672 | rSP_reg, | |
673 | rBP_reg, | |
674 | rSI_reg, | |
675 | rDI_reg, | |
d55ee72f | 676 | |
3873ba12 L |
677 | z_mode_ax_reg, |
678 | indir_dx_reg | |
51e7da1b | 679 | }; |
252b5132 | 680 | |
51e7da1b L |
681 | enum |
682 | { | |
683 | FLOATCODE = 1, | |
3873ba12 L |
684 | USE_REG_TABLE, |
685 | USE_MOD_TABLE, | |
686 | USE_RM_TABLE, | |
687 | USE_PREFIX_TABLE, | |
688 | USE_X86_64_TABLE, | |
689 | USE_3BYTE_TABLE, | |
f88c9eb0 | 690 | USE_XOP_8F_TABLE, |
3873ba12 L |
691 | USE_VEX_C4_TABLE, |
692 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 693 | USE_VEX_LEN_TABLE, |
43234a1e L |
694 | USE_VEX_W_TABLE, |
695 | USE_EVEX_TABLE | |
51e7da1b | 696 | }; |
6439fc28 | 697 | |
bf890a93 | 698 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 699 | |
bf890a93 IT |
700 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
701 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
702 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
703 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
704 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
705 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
706 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
707 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 708 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 709 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
710 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
711 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
712 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 713 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 714 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
1ceb70f8 | 715 | |
51e7da1b L |
716 | enum |
717 | { | |
718 | REG_80 = 0, | |
3873ba12 | 719 | REG_81, |
7148c369 | 720 | REG_83, |
3873ba12 L |
721 | REG_8F, |
722 | REG_C0, | |
723 | REG_C1, | |
724 | REG_C6, | |
725 | REG_C7, | |
726 | REG_D0, | |
727 | REG_D1, | |
728 | REG_D2, | |
729 | REG_D3, | |
730 | REG_F6, | |
731 | REG_F7, | |
732 | REG_FE, | |
733 | REG_FF, | |
734 | REG_0F00, | |
735 | REG_0F01, | |
736 | REG_0F0D, | |
737 | REG_0F18, | |
603555e5 | 738 | REG_0F1E_MOD_3, |
3873ba12 L |
739 | REG_0F71, |
740 | REG_0F72, | |
741 | REG_0F73, | |
742 | REG_0FA6, | |
743 | REG_0FA7, | |
744 | REG_0FAE, | |
745 | REG_0FBA, | |
746 | REG_0FC7, | |
592a252b L |
747 | REG_VEX_0F71, |
748 | REG_VEX_0F72, | |
749 | REG_VEX_0F73, | |
750 | REG_VEX_0FAE, | |
f12dc422 | 751 | REG_VEX_0F38F3, |
f88c9eb0 | 752 | REG_XOP_LWPCB, |
2a2a0f38 QN |
753 | REG_XOP_LWP, |
754 | REG_XOP_TBM_01, | |
43234a1e L |
755 | REG_XOP_TBM_02, |
756 | ||
1ba585e8 | 757 | REG_EVEX_0F71, |
43234a1e L |
758 | REG_EVEX_0F72, |
759 | REG_EVEX_0F73, | |
760 | REG_EVEX_0F38C6, | |
761 | REG_EVEX_0F38C7 | |
51e7da1b | 762 | }; |
1ceb70f8 | 763 | |
51e7da1b L |
764 | enum |
765 | { | |
766 | MOD_8D = 0, | |
42164a71 L |
767 | MOD_C6_REG_7, |
768 | MOD_C7_REG_7, | |
4a357820 MZ |
769 | MOD_FF_REG_3, |
770 | MOD_FF_REG_5, | |
3873ba12 L |
771 | MOD_0F01_REG_0, |
772 | MOD_0F01_REG_1, | |
773 | MOD_0F01_REG_2, | |
774 | MOD_0F01_REG_3, | |
8eab4136 | 775 | MOD_0F01_REG_5, |
3873ba12 L |
776 | MOD_0F01_REG_7, |
777 | MOD_0F12_PREFIX_0, | |
778 | MOD_0F13, | |
779 | MOD_0F16_PREFIX_0, | |
780 | MOD_0F17, | |
781 | MOD_0F18_REG_0, | |
782 | MOD_0F18_REG_1, | |
783 | MOD_0F18_REG_2, | |
784 | MOD_0F18_REG_3, | |
d7189fa5 RM |
785 | MOD_0F18_REG_4, |
786 | MOD_0F18_REG_5, | |
787 | MOD_0F18_REG_6, | |
788 | MOD_0F18_REG_7, | |
7e8b059b L |
789 | MOD_0F1A_PREFIX_0, |
790 | MOD_0F1B_PREFIX_0, | |
791 | MOD_0F1B_PREFIX_1, | |
603555e5 | 792 | MOD_0F1E_PREFIX_1, |
3873ba12 L |
793 | MOD_0F24, |
794 | MOD_0F26, | |
795 | MOD_0F2B_PREFIX_0, | |
796 | MOD_0F2B_PREFIX_1, | |
797 | MOD_0F2B_PREFIX_2, | |
798 | MOD_0F2B_PREFIX_3, | |
799 | MOD_0F51, | |
800 | MOD_0F71_REG_2, | |
801 | MOD_0F71_REG_4, | |
802 | MOD_0F71_REG_6, | |
803 | MOD_0F72_REG_2, | |
804 | MOD_0F72_REG_4, | |
805 | MOD_0F72_REG_6, | |
806 | MOD_0F73_REG_2, | |
807 | MOD_0F73_REG_3, | |
808 | MOD_0F73_REG_6, | |
809 | MOD_0F73_REG_7, | |
810 | MOD_0FAE_REG_0, | |
811 | MOD_0FAE_REG_1, | |
812 | MOD_0FAE_REG_2, | |
813 | MOD_0FAE_REG_3, | |
814 | MOD_0FAE_REG_4, | |
815 | MOD_0FAE_REG_5, | |
816 | MOD_0FAE_REG_6, | |
817 | MOD_0FAE_REG_7, | |
818 | MOD_0FB2, | |
819 | MOD_0FB4, | |
820 | MOD_0FB5, | |
a8484f96 | 821 | MOD_0FC3, |
963f3586 IT |
822 | MOD_0FC7_REG_3, |
823 | MOD_0FC7_REG_4, | |
824 | MOD_0FC7_REG_5, | |
3873ba12 L |
825 | MOD_0FC7_REG_6, |
826 | MOD_0FC7_REG_7, | |
827 | MOD_0FD7, | |
828 | MOD_0FE7_PREFIX_2, | |
829 | MOD_0FF0_PREFIX_3, | |
830 | MOD_0F382A_PREFIX_2, | |
603555e5 L |
831 | MOD_0F38F5_PREFIX_2, |
832 | MOD_0F38F6_PREFIX_0, | |
3873ba12 L |
833 | MOD_62_32BIT, |
834 | MOD_C4_32BIT, | |
835 | MOD_C5_32BIT, | |
592a252b L |
836 | MOD_VEX_0F12_PREFIX_0, |
837 | MOD_VEX_0F13, | |
838 | MOD_VEX_0F16_PREFIX_0, | |
839 | MOD_VEX_0F17, | |
840 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
841 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
842 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
843 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
844 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
845 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
846 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
847 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
848 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
849 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
850 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
851 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
852 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
853 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
854 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
855 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
856 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
857 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
858 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
859 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
860 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
861 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
862 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
863 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
864 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
865 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
866 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
867 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
868 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
869 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
870 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
871 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
872 | MOD_VEX_0F50, |
873 | MOD_VEX_0F71_REG_2, | |
874 | MOD_VEX_0F71_REG_4, | |
875 | MOD_VEX_0F71_REG_6, | |
876 | MOD_VEX_0F72_REG_2, | |
877 | MOD_VEX_0F72_REG_4, | |
878 | MOD_VEX_0F72_REG_6, | |
879 | MOD_VEX_0F73_REG_2, | |
880 | MOD_VEX_0F73_REG_3, | |
881 | MOD_VEX_0F73_REG_6, | |
882 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
883 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
884 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
885 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
886 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
887 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
888 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
889 | MOD_VEX_W_0_0F92_P_3_LEN_0, | |
890 | MOD_VEX_W_1_0F92_P_3_LEN_0, | |
891 | MOD_VEX_W_0_0F93_P_0_LEN_0, | |
892 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
893 | MOD_VEX_W_0_0F93_P_3_LEN_0, | |
894 | MOD_VEX_W_1_0F93_P_3_LEN_0, | |
895 | MOD_VEX_W_0_0F98_P_0_LEN_0, | |
896 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
897 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
898 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
899 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
900 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
901 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
902 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
903 | MOD_VEX_0FAE_REG_2, |
904 | MOD_VEX_0FAE_REG_3, | |
905 | MOD_VEX_0FD7_PREFIX_2, | |
906 | MOD_VEX_0FE7_PREFIX_2, | |
907 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
908 | MOD_VEX_0F381A_PREFIX_2, |
909 | MOD_VEX_0F382A_PREFIX_2, | |
910 | MOD_VEX_0F382C_PREFIX_2, | |
911 | MOD_VEX_0F382D_PREFIX_2, | |
912 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
913 | MOD_VEX_0F382F_PREFIX_2, |
914 | MOD_VEX_0F385A_PREFIX_2, | |
915 | MOD_VEX_0F388C_PREFIX_2, | |
916 | MOD_VEX_0F388E_PREFIX_2, | |
ab4e4ed5 AF |
917 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
918 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
919 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, | |
920 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
921 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, | |
922 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
923 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, | |
924 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, | |
43234a1e L |
925 | |
926 | MOD_EVEX_0F10_PREFIX_1, | |
927 | MOD_EVEX_0F10_PREFIX_3, | |
928 | MOD_EVEX_0F11_PREFIX_1, | |
929 | MOD_EVEX_0F11_PREFIX_3, | |
930 | MOD_EVEX_0F12_PREFIX_0, | |
931 | MOD_EVEX_0F16_PREFIX_0, | |
932 | MOD_EVEX_0F38C6_REG_1, | |
933 | MOD_EVEX_0F38C6_REG_2, | |
934 | MOD_EVEX_0F38C6_REG_5, | |
935 | MOD_EVEX_0F38C6_REG_6, | |
936 | MOD_EVEX_0F38C7_REG_1, | |
937 | MOD_EVEX_0F38C7_REG_2, | |
938 | MOD_EVEX_0F38C7_REG_5, | |
939 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 940 | }; |
1ceb70f8 | 941 | |
51e7da1b L |
942 | enum |
943 | { | |
42164a71 L |
944 | RM_C6_REG_7 = 0, |
945 | RM_C7_REG_7, | |
946 | RM_0F01_REG_0, | |
3873ba12 L |
947 | RM_0F01_REG_1, |
948 | RM_0F01_REG_2, | |
949 | RM_0F01_REG_3, | |
8eab4136 | 950 | RM_0F01_REG_5, |
3873ba12 | 951 | RM_0F01_REG_7, |
603555e5 | 952 | RM_0F1E_MOD_3_REG_7, |
3873ba12 L |
953 | RM_0FAE_REG_6, |
954 | RM_0FAE_REG_7 | |
51e7da1b | 955 | }; |
1ceb70f8 | 956 | |
51e7da1b L |
957 | enum |
958 | { | |
959 | PREFIX_90 = 0, | |
603555e5 | 960 | PREFIX_MOD_0_0F01_REG_5, |
2234eee6 | 961 | PREFIX_MOD_3_0F01_REG_5_RM_0, |
603555e5 | 962 | PREFIX_MOD_3_0F01_REG_5_RM_2, |
3233d7d0 | 963 | PREFIX_0F09, |
3873ba12 L |
964 | PREFIX_0F10, |
965 | PREFIX_0F11, | |
966 | PREFIX_0F12, | |
967 | PREFIX_0F16, | |
7e8b059b L |
968 | PREFIX_0F1A, |
969 | PREFIX_0F1B, | |
603555e5 | 970 | PREFIX_0F1E, |
3873ba12 L |
971 | PREFIX_0F2A, |
972 | PREFIX_0F2B, | |
973 | PREFIX_0F2C, | |
974 | PREFIX_0F2D, | |
975 | PREFIX_0F2E, | |
976 | PREFIX_0F2F, | |
977 | PREFIX_0F51, | |
978 | PREFIX_0F52, | |
979 | PREFIX_0F53, | |
980 | PREFIX_0F58, | |
981 | PREFIX_0F59, | |
982 | PREFIX_0F5A, | |
983 | PREFIX_0F5B, | |
984 | PREFIX_0F5C, | |
985 | PREFIX_0F5D, | |
986 | PREFIX_0F5E, | |
987 | PREFIX_0F5F, | |
988 | PREFIX_0F60, | |
989 | PREFIX_0F61, | |
990 | PREFIX_0F62, | |
991 | PREFIX_0F6C, | |
992 | PREFIX_0F6D, | |
993 | PREFIX_0F6F, | |
994 | PREFIX_0F70, | |
995 | PREFIX_0F73_REG_3, | |
996 | PREFIX_0F73_REG_7, | |
997 | PREFIX_0F78, | |
998 | PREFIX_0F79, | |
999 | PREFIX_0F7C, | |
1000 | PREFIX_0F7D, | |
1001 | PREFIX_0F7E, | |
1002 | PREFIX_0F7F, | |
c7b8aa3a L |
1003 | PREFIX_0FAE_REG_0, |
1004 | PREFIX_0FAE_REG_1, | |
1005 | PREFIX_0FAE_REG_2, | |
1006 | PREFIX_0FAE_REG_3, | |
6b40c462 L |
1007 | PREFIX_MOD_0_0FAE_REG_4, |
1008 | PREFIX_MOD_3_0FAE_REG_4, | |
603555e5 | 1009 | PREFIX_MOD_0_0FAE_REG_5, |
2234eee6 | 1010 | PREFIX_MOD_3_0FAE_REG_5, |
c5e7287a | 1011 | PREFIX_0FAE_REG_6, |
963f3586 | 1012 | PREFIX_0FAE_REG_7, |
3873ba12 | 1013 | PREFIX_0FB8, |
f12dc422 | 1014 | PREFIX_0FBC, |
3873ba12 L |
1015 | PREFIX_0FBD, |
1016 | PREFIX_0FC2, | |
a8484f96 | 1017 | PREFIX_MOD_0_0FC3, |
f24bcbaa L |
1018 | PREFIX_MOD_0_0FC7_REG_6, |
1019 | PREFIX_MOD_3_0FC7_REG_6, | |
1020 | PREFIX_MOD_3_0FC7_REG_7, | |
3873ba12 L |
1021 | PREFIX_0FD0, |
1022 | PREFIX_0FD6, | |
1023 | PREFIX_0FE6, | |
1024 | PREFIX_0FE7, | |
1025 | PREFIX_0FF0, | |
1026 | PREFIX_0FF7, | |
1027 | PREFIX_0F3810, | |
1028 | PREFIX_0F3814, | |
1029 | PREFIX_0F3815, | |
1030 | PREFIX_0F3817, | |
1031 | PREFIX_0F3820, | |
1032 | PREFIX_0F3821, | |
1033 | PREFIX_0F3822, | |
1034 | PREFIX_0F3823, | |
1035 | PREFIX_0F3824, | |
1036 | PREFIX_0F3825, | |
1037 | PREFIX_0F3828, | |
1038 | PREFIX_0F3829, | |
1039 | PREFIX_0F382A, | |
1040 | PREFIX_0F382B, | |
1041 | PREFIX_0F3830, | |
1042 | PREFIX_0F3831, | |
1043 | PREFIX_0F3832, | |
1044 | PREFIX_0F3833, | |
1045 | PREFIX_0F3834, | |
1046 | PREFIX_0F3835, | |
1047 | PREFIX_0F3837, | |
1048 | PREFIX_0F3838, | |
1049 | PREFIX_0F3839, | |
1050 | PREFIX_0F383A, | |
1051 | PREFIX_0F383B, | |
1052 | PREFIX_0F383C, | |
1053 | PREFIX_0F383D, | |
1054 | PREFIX_0F383E, | |
1055 | PREFIX_0F383F, | |
1056 | PREFIX_0F3840, | |
1057 | PREFIX_0F3841, | |
1058 | PREFIX_0F3880, | |
1059 | PREFIX_0F3881, | |
6c30d220 | 1060 | PREFIX_0F3882, |
a0046408 L |
1061 | PREFIX_0F38C8, |
1062 | PREFIX_0F38C9, | |
1063 | PREFIX_0F38CA, | |
1064 | PREFIX_0F38CB, | |
1065 | PREFIX_0F38CC, | |
1066 | PREFIX_0F38CD, | |
48521003 | 1067 | PREFIX_0F38CF, |
3873ba12 L |
1068 | PREFIX_0F38DB, |
1069 | PREFIX_0F38DC, | |
1070 | PREFIX_0F38DD, | |
1071 | PREFIX_0F38DE, | |
1072 | PREFIX_0F38DF, | |
1073 | PREFIX_0F38F0, | |
1074 | PREFIX_0F38F1, | |
603555e5 | 1075 | PREFIX_0F38F5, |
e2e1fcde | 1076 | PREFIX_0F38F6, |
3873ba12 L |
1077 | PREFIX_0F3A08, |
1078 | PREFIX_0F3A09, | |
1079 | PREFIX_0F3A0A, | |
1080 | PREFIX_0F3A0B, | |
1081 | PREFIX_0F3A0C, | |
1082 | PREFIX_0F3A0D, | |
1083 | PREFIX_0F3A0E, | |
1084 | PREFIX_0F3A14, | |
1085 | PREFIX_0F3A15, | |
1086 | PREFIX_0F3A16, | |
1087 | PREFIX_0F3A17, | |
1088 | PREFIX_0F3A20, | |
1089 | PREFIX_0F3A21, | |
1090 | PREFIX_0F3A22, | |
1091 | PREFIX_0F3A40, | |
1092 | PREFIX_0F3A41, | |
1093 | PREFIX_0F3A42, | |
1094 | PREFIX_0F3A44, | |
1095 | PREFIX_0F3A60, | |
1096 | PREFIX_0F3A61, | |
1097 | PREFIX_0F3A62, | |
1098 | PREFIX_0F3A63, | |
a0046408 | 1099 | PREFIX_0F3ACC, |
48521003 IT |
1100 | PREFIX_0F3ACE, |
1101 | PREFIX_0F3ACF, | |
3873ba12 | 1102 | PREFIX_0F3ADF, |
592a252b L |
1103 | PREFIX_VEX_0F10, |
1104 | PREFIX_VEX_0F11, | |
1105 | PREFIX_VEX_0F12, | |
1106 | PREFIX_VEX_0F16, | |
1107 | PREFIX_VEX_0F2A, | |
1108 | PREFIX_VEX_0F2C, | |
1109 | PREFIX_VEX_0F2D, | |
1110 | PREFIX_VEX_0F2E, | |
1111 | PREFIX_VEX_0F2F, | |
43234a1e L |
1112 | PREFIX_VEX_0F41, |
1113 | PREFIX_VEX_0F42, | |
1114 | PREFIX_VEX_0F44, | |
1115 | PREFIX_VEX_0F45, | |
1116 | PREFIX_VEX_0F46, | |
1117 | PREFIX_VEX_0F47, | |
1ba585e8 | 1118 | PREFIX_VEX_0F4A, |
43234a1e | 1119 | PREFIX_VEX_0F4B, |
592a252b L |
1120 | PREFIX_VEX_0F51, |
1121 | PREFIX_VEX_0F52, | |
1122 | PREFIX_VEX_0F53, | |
1123 | PREFIX_VEX_0F58, | |
1124 | PREFIX_VEX_0F59, | |
1125 | PREFIX_VEX_0F5A, | |
1126 | PREFIX_VEX_0F5B, | |
1127 | PREFIX_VEX_0F5C, | |
1128 | PREFIX_VEX_0F5D, | |
1129 | PREFIX_VEX_0F5E, | |
1130 | PREFIX_VEX_0F5F, | |
1131 | PREFIX_VEX_0F60, | |
1132 | PREFIX_VEX_0F61, | |
1133 | PREFIX_VEX_0F62, | |
1134 | PREFIX_VEX_0F63, | |
1135 | PREFIX_VEX_0F64, | |
1136 | PREFIX_VEX_0F65, | |
1137 | PREFIX_VEX_0F66, | |
1138 | PREFIX_VEX_0F67, | |
1139 | PREFIX_VEX_0F68, | |
1140 | PREFIX_VEX_0F69, | |
1141 | PREFIX_VEX_0F6A, | |
1142 | PREFIX_VEX_0F6B, | |
1143 | PREFIX_VEX_0F6C, | |
1144 | PREFIX_VEX_0F6D, | |
1145 | PREFIX_VEX_0F6E, | |
1146 | PREFIX_VEX_0F6F, | |
1147 | PREFIX_VEX_0F70, | |
1148 | PREFIX_VEX_0F71_REG_2, | |
1149 | PREFIX_VEX_0F71_REG_4, | |
1150 | PREFIX_VEX_0F71_REG_6, | |
1151 | PREFIX_VEX_0F72_REG_2, | |
1152 | PREFIX_VEX_0F72_REG_4, | |
1153 | PREFIX_VEX_0F72_REG_6, | |
1154 | PREFIX_VEX_0F73_REG_2, | |
1155 | PREFIX_VEX_0F73_REG_3, | |
1156 | PREFIX_VEX_0F73_REG_6, | |
1157 | PREFIX_VEX_0F73_REG_7, | |
1158 | PREFIX_VEX_0F74, | |
1159 | PREFIX_VEX_0F75, | |
1160 | PREFIX_VEX_0F76, | |
1161 | PREFIX_VEX_0F77, | |
1162 | PREFIX_VEX_0F7C, | |
1163 | PREFIX_VEX_0F7D, | |
1164 | PREFIX_VEX_0F7E, | |
1165 | PREFIX_VEX_0F7F, | |
43234a1e L |
1166 | PREFIX_VEX_0F90, |
1167 | PREFIX_VEX_0F91, | |
1168 | PREFIX_VEX_0F92, | |
1169 | PREFIX_VEX_0F93, | |
1170 | PREFIX_VEX_0F98, | |
1ba585e8 | 1171 | PREFIX_VEX_0F99, |
592a252b L |
1172 | PREFIX_VEX_0FC2, |
1173 | PREFIX_VEX_0FC4, | |
1174 | PREFIX_VEX_0FC5, | |
1175 | PREFIX_VEX_0FD0, | |
1176 | PREFIX_VEX_0FD1, | |
1177 | PREFIX_VEX_0FD2, | |
1178 | PREFIX_VEX_0FD3, | |
1179 | PREFIX_VEX_0FD4, | |
1180 | PREFIX_VEX_0FD5, | |
1181 | PREFIX_VEX_0FD6, | |
1182 | PREFIX_VEX_0FD7, | |
1183 | PREFIX_VEX_0FD8, | |
1184 | PREFIX_VEX_0FD9, | |
1185 | PREFIX_VEX_0FDA, | |
1186 | PREFIX_VEX_0FDB, | |
1187 | PREFIX_VEX_0FDC, | |
1188 | PREFIX_VEX_0FDD, | |
1189 | PREFIX_VEX_0FDE, | |
1190 | PREFIX_VEX_0FDF, | |
1191 | PREFIX_VEX_0FE0, | |
1192 | PREFIX_VEX_0FE1, | |
1193 | PREFIX_VEX_0FE2, | |
1194 | PREFIX_VEX_0FE3, | |
1195 | PREFIX_VEX_0FE4, | |
1196 | PREFIX_VEX_0FE5, | |
1197 | PREFIX_VEX_0FE6, | |
1198 | PREFIX_VEX_0FE7, | |
1199 | PREFIX_VEX_0FE8, | |
1200 | PREFIX_VEX_0FE9, | |
1201 | PREFIX_VEX_0FEA, | |
1202 | PREFIX_VEX_0FEB, | |
1203 | PREFIX_VEX_0FEC, | |
1204 | PREFIX_VEX_0FED, | |
1205 | PREFIX_VEX_0FEE, | |
1206 | PREFIX_VEX_0FEF, | |
1207 | PREFIX_VEX_0FF0, | |
1208 | PREFIX_VEX_0FF1, | |
1209 | PREFIX_VEX_0FF2, | |
1210 | PREFIX_VEX_0FF3, | |
1211 | PREFIX_VEX_0FF4, | |
1212 | PREFIX_VEX_0FF5, | |
1213 | PREFIX_VEX_0FF6, | |
1214 | PREFIX_VEX_0FF7, | |
1215 | PREFIX_VEX_0FF8, | |
1216 | PREFIX_VEX_0FF9, | |
1217 | PREFIX_VEX_0FFA, | |
1218 | PREFIX_VEX_0FFB, | |
1219 | PREFIX_VEX_0FFC, | |
1220 | PREFIX_VEX_0FFD, | |
1221 | PREFIX_VEX_0FFE, | |
1222 | PREFIX_VEX_0F3800, | |
1223 | PREFIX_VEX_0F3801, | |
1224 | PREFIX_VEX_0F3802, | |
1225 | PREFIX_VEX_0F3803, | |
1226 | PREFIX_VEX_0F3804, | |
1227 | PREFIX_VEX_0F3805, | |
1228 | PREFIX_VEX_0F3806, | |
1229 | PREFIX_VEX_0F3807, | |
1230 | PREFIX_VEX_0F3808, | |
1231 | PREFIX_VEX_0F3809, | |
1232 | PREFIX_VEX_0F380A, | |
1233 | PREFIX_VEX_0F380B, | |
1234 | PREFIX_VEX_0F380C, | |
1235 | PREFIX_VEX_0F380D, | |
1236 | PREFIX_VEX_0F380E, | |
1237 | PREFIX_VEX_0F380F, | |
1238 | PREFIX_VEX_0F3813, | |
6c30d220 | 1239 | PREFIX_VEX_0F3816, |
592a252b L |
1240 | PREFIX_VEX_0F3817, |
1241 | PREFIX_VEX_0F3818, | |
1242 | PREFIX_VEX_0F3819, | |
1243 | PREFIX_VEX_0F381A, | |
1244 | PREFIX_VEX_0F381C, | |
1245 | PREFIX_VEX_0F381D, | |
1246 | PREFIX_VEX_0F381E, | |
1247 | PREFIX_VEX_0F3820, | |
1248 | PREFIX_VEX_0F3821, | |
1249 | PREFIX_VEX_0F3822, | |
1250 | PREFIX_VEX_0F3823, | |
1251 | PREFIX_VEX_0F3824, | |
1252 | PREFIX_VEX_0F3825, | |
1253 | PREFIX_VEX_0F3828, | |
1254 | PREFIX_VEX_0F3829, | |
1255 | PREFIX_VEX_0F382A, | |
1256 | PREFIX_VEX_0F382B, | |
1257 | PREFIX_VEX_0F382C, | |
1258 | PREFIX_VEX_0F382D, | |
1259 | PREFIX_VEX_0F382E, | |
1260 | PREFIX_VEX_0F382F, | |
1261 | PREFIX_VEX_0F3830, | |
1262 | PREFIX_VEX_0F3831, | |
1263 | PREFIX_VEX_0F3832, | |
1264 | PREFIX_VEX_0F3833, | |
1265 | PREFIX_VEX_0F3834, | |
1266 | PREFIX_VEX_0F3835, | |
6c30d220 | 1267 | PREFIX_VEX_0F3836, |
592a252b L |
1268 | PREFIX_VEX_0F3837, |
1269 | PREFIX_VEX_0F3838, | |
1270 | PREFIX_VEX_0F3839, | |
1271 | PREFIX_VEX_0F383A, | |
1272 | PREFIX_VEX_0F383B, | |
1273 | PREFIX_VEX_0F383C, | |
1274 | PREFIX_VEX_0F383D, | |
1275 | PREFIX_VEX_0F383E, | |
1276 | PREFIX_VEX_0F383F, | |
1277 | PREFIX_VEX_0F3840, | |
1278 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1279 | PREFIX_VEX_0F3845, |
1280 | PREFIX_VEX_0F3846, | |
1281 | PREFIX_VEX_0F3847, | |
1282 | PREFIX_VEX_0F3858, | |
1283 | PREFIX_VEX_0F3859, | |
1284 | PREFIX_VEX_0F385A, | |
1285 | PREFIX_VEX_0F3878, | |
1286 | PREFIX_VEX_0F3879, | |
1287 | PREFIX_VEX_0F388C, | |
1288 | PREFIX_VEX_0F388E, | |
1289 | PREFIX_VEX_0F3890, | |
1290 | PREFIX_VEX_0F3891, | |
1291 | PREFIX_VEX_0F3892, | |
1292 | PREFIX_VEX_0F3893, | |
592a252b L |
1293 | PREFIX_VEX_0F3896, |
1294 | PREFIX_VEX_0F3897, | |
1295 | PREFIX_VEX_0F3898, | |
1296 | PREFIX_VEX_0F3899, | |
1297 | PREFIX_VEX_0F389A, | |
1298 | PREFIX_VEX_0F389B, | |
1299 | PREFIX_VEX_0F389C, | |
1300 | PREFIX_VEX_0F389D, | |
1301 | PREFIX_VEX_0F389E, | |
1302 | PREFIX_VEX_0F389F, | |
1303 | PREFIX_VEX_0F38A6, | |
1304 | PREFIX_VEX_0F38A7, | |
1305 | PREFIX_VEX_0F38A8, | |
1306 | PREFIX_VEX_0F38A9, | |
1307 | PREFIX_VEX_0F38AA, | |
1308 | PREFIX_VEX_0F38AB, | |
1309 | PREFIX_VEX_0F38AC, | |
1310 | PREFIX_VEX_0F38AD, | |
1311 | PREFIX_VEX_0F38AE, | |
1312 | PREFIX_VEX_0F38AF, | |
1313 | PREFIX_VEX_0F38B6, | |
1314 | PREFIX_VEX_0F38B7, | |
1315 | PREFIX_VEX_0F38B8, | |
1316 | PREFIX_VEX_0F38B9, | |
1317 | PREFIX_VEX_0F38BA, | |
1318 | PREFIX_VEX_0F38BB, | |
1319 | PREFIX_VEX_0F38BC, | |
1320 | PREFIX_VEX_0F38BD, | |
1321 | PREFIX_VEX_0F38BE, | |
1322 | PREFIX_VEX_0F38BF, | |
48521003 | 1323 | PREFIX_VEX_0F38CF, |
592a252b L |
1324 | PREFIX_VEX_0F38DB, |
1325 | PREFIX_VEX_0F38DC, | |
1326 | PREFIX_VEX_0F38DD, | |
1327 | PREFIX_VEX_0F38DE, | |
1328 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1329 | PREFIX_VEX_0F38F2, |
1330 | PREFIX_VEX_0F38F3_REG_1, | |
1331 | PREFIX_VEX_0F38F3_REG_2, | |
1332 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1333 | PREFIX_VEX_0F38F5, |
1334 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1335 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1336 | PREFIX_VEX_0F3A00, |
1337 | PREFIX_VEX_0F3A01, | |
1338 | PREFIX_VEX_0F3A02, | |
592a252b L |
1339 | PREFIX_VEX_0F3A04, |
1340 | PREFIX_VEX_0F3A05, | |
1341 | PREFIX_VEX_0F3A06, | |
1342 | PREFIX_VEX_0F3A08, | |
1343 | PREFIX_VEX_0F3A09, | |
1344 | PREFIX_VEX_0F3A0A, | |
1345 | PREFIX_VEX_0F3A0B, | |
1346 | PREFIX_VEX_0F3A0C, | |
1347 | PREFIX_VEX_0F3A0D, | |
1348 | PREFIX_VEX_0F3A0E, | |
1349 | PREFIX_VEX_0F3A0F, | |
1350 | PREFIX_VEX_0F3A14, | |
1351 | PREFIX_VEX_0F3A15, | |
1352 | PREFIX_VEX_0F3A16, | |
1353 | PREFIX_VEX_0F3A17, | |
1354 | PREFIX_VEX_0F3A18, | |
1355 | PREFIX_VEX_0F3A19, | |
1356 | PREFIX_VEX_0F3A1D, | |
1357 | PREFIX_VEX_0F3A20, | |
1358 | PREFIX_VEX_0F3A21, | |
1359 | PREFIX_VEX_0F3A22, | |
43234a1e | 1360 | PREFIX_VEX_0F3A30, |
1ba585e8 | 1361 | PREFIX_VEX_0F3A31, |
43234a1e | 1362 | PREFIX_VEX_0F3A32, |
1ba585e8 | 1363 | PREFIX_VEX_0F3A33, |
6c30d220 L |
1364 | PREFIX_VEX_0F3A38, |
1365 | PREFIX_VEX_0F3A39, | |
592a252b L |
1366 | PREFIX_VEX_0F3A40, |
1367 | PREFIX_VEX_0F3A41, | |
1368 | PREFIX_VEX_0F3A42, | |
1369 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1370 | PREFIX_VEX_0F3A46, |
592a252b L |
1371 | PREFIX_VEX_0F3A48, |
1372 | PREFIX_VEX_0F3A49, | |
1373 | PREFIX_VEX_0F3A4A, | |
1374 | PREFIX_VEX_0F3A4B, | |
1375 | PREFIX_VEX_0F3A4C, | |
1376 | PREFIX_VEX_0F3A5C, | |
1377 | PREFIX_VEX_0F3A5D, | |
1378 | PREFIX_VEX_0F3A5E, | |
1379 | PREFIX_VEX_0F3A5F, | |
1380 | PREFIX_VEX_0F3A60, | |
1381 | PREFIX_VEX_0F3A61, | |
1382 | PREFIX_VEX_0F3A62, | |
1383 | PREFIX_VEX_0F3A63, | |
1384 | PREFIX_VEX_0F3A68, | |
1385 | PREFIX_VEX_0F3A69, | |
1386 | PREFIX_VEX_0F3A6A, | |
1387 | PREFIX_VEX_0F3A6B, | |
1388 | PREFIX_VEX_0F3A6C, | |
1389 | PREFIX_VEX_0F3A6D, | |
1390 | PREFIX_VEX_0F3A6E, | |
1391 | PREFIX_VEX_0F3A6F, | |
1392 | PREFIX_VEX_0F3A78, | |
1393 | PREFIX_VEX_0F3A79, | |
1394 | PREFIX_VEX_0F3A7A, | |
1395 | PREFIX_VEX_0F3A7B, | |
1396 | PREFIX_VEX_0F3A7C, | |
1397 | PREFIX_VEX_0F3A7D, | |
1398 | PREFIX_VEX_0F3A7E, | |
1399 | PREFIX_VEX_0F3A7F, | |
48521003 IT |
1400 | PREFIX_VEX_0F3ACE, |
1401 | PREFIX_VEX_0F3ACF, | |
6c30d220 | 1402 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1403 | PREFIX_VEX_0F3AF0, |
1404 | ||
1405 | PREFIX_EVEX_0F10, | |
1406 | PREFIX_EVEX_0F11, | |
1407 | PREFIX_EVEX_0F12, | |
1408 | PREFIX_EVEX_0F13, | |
1409 | PREFIX_EVEX_0F14, | |
1410 | PREFIX_EVEX_0F15, | |
1411 | PREFIX_EVEX_0F16, | |
1412 | PREFIX_EVEX_0F17, | |
1413 | PREFIX_EVEX_0F28, | |
1414 | PREFIX_EVEX_0F29, | |
1415 | PREFIX_EVEX_0F2A, | |
1416 | PREFIX_EVEX_0F2B, | |
1417 | PREFIX_EVEX_0F2C, | |
1418 | PREFIX_EVEX_0F2D, | |
1419 | PREFIX_EVEX_0F2E, | |
1420 | PREFIX_EVEX_0F2F, | |
1421 | PREFIX_EVEX_0F51, | |
90a915bf IT |
1422 | PREFIX_EVEX_0F54, |
1423 | PREFIX_EVEX_0F55, | |
1424 | PREFIX_EVEX_0F56, | |
1425 | PREFIX_EVEX_0F57, | |
43234a1e L |
1426 | PREFIX_EVEX_0F58, |
1427 | PREFIX_EVEX_0F59, | |
1428 | PREFIX_EVEX_0F5A, | |
1429 | PREFIX_EVEX_0F5B, | |
1430 | PREFIX_EVEX_0F5C, | |
1431 | PREFIX_EVEX_0F5D, | |
1432 | PREFIX_EVEX_0F5E, | |
1433 | PREFIX_EVEX_0F5F, | |
1ba585e8 IT |
1434 | PREFIX_EVEX_0F60, |
1435 | PREFIX_EVEX_0F61, | |
43234a1e | 1436 | PREFIX_EVEX_0F62, |
1ba585e8 IT |
1437 | PREFIX_EVEX_0F63, |
1438 | PREFIX_EVEX_0F64, | |
1439 | PREFIX_EVEX_0F65, | |
43234a1e | 1440 | PREFIX_EVEX_0F66, |
1ba585e8 IT |
1441 | PREFIX_EVEX_0F67, |
1442 | PREFIX_EVEX_0F68, | |
1443 | PREFIX_EVEX_0F69, | |
43234a1e | 1444 | PREFIX_EVEX_0F6A, |
1ba585e8 | 1445 | PREFIX_EVEX_0F6B, |
43234a1e L |
1446 | PREFIX_EVEX_0F6C, |
1447 | PREFIX_EVEX_0F6D, | |
1448 | PREFIX_EVEX_0F6E, | |
1449 | PREFIX_EVEX_0F6F, | |
1450 | PREFIX_EVEX_0F70, | |
1ba585e8 IT |
1451 | PREFIX_EVEX_0F71_REG_2, |
1452 | PREFIX_EVEX_0F71_REG_4, | |
1453 | PREFIX_EVEX_0F71_REG_6, | |
43234a1e L |
1454 | PREFIX_EVEX_0F72_REG_0, |
1455 | PREFIX_EVEX_0F72_REG_1, | |
1456 | PREFIX_EVEX_0F72_REG_2, | |
1457 | PREFIX_EVEX_0F72_REG_4, | |
1458 | PREFIX_EVEX_0F72_REG_6, | |
1459 | PREFIX_EVEX_0F73_REG_2, | |
1ba585e8 | 1460 | PREFIX_EVEX_0F73_REG_3, |
43234a1e | 1461 | PREFIX_EVEX_0F73_REG_6, |
1ba585e8 IT |
1462 | PREFIX_EVEX_0F73_REG_7, |
1463 | PREFIX_EVEX_0F74, | |
1464 | PREFIX_EVEX_0F75, | |
43234a1e L |
1465 | PREFIX_EVEX_0F76, |
1466 | PREFIX_EVEX_0F78, | |
1467 | PREFIX_EVEX_0F79, | |
1468 | PREFIX_EVEX_0F7A, | |
1469 | PREFIX_EVEX_0F7B, | |
1470 | PREFIX_EVEX_0F7E, | |
1471 | PREFIX_EVEX_0F7F, | |
1472 | PREFIX_EVEX_0FC2, | |
1ba585e8 IT |
1473 | PREFIX_EVEX_0FC4, |
1474 | PREFIX_EVEX_0FC5, | |
43234a1e | 1475 | PREFIX_EVEX_0FC6, |
1ba585e8 | 1476 | PREFIX_EVEX_0FD1, |
43234a1e L |
1477 | PREFIX_EVEX_0FD2, |
1478 | PREFIX_EVEX_0FD3, | |
1479 | PREFIX_EVEX_0FD4, | |
1ba585e8 | 1480 | PREFIX_EVEX_0FD5, |
43234a1e | 1481 | PREFIX_EVEX_0FD6, |
1ba585e8 IT |
1482 | PREFIX_EVEX_0FD8, |
1483 | PREFIX_EVEX_0FD9, | |
1484 | PREFIX_EVEX_0FDA, | |
43234a1e | 1485 | PREFIX_EVEX_0FDB, |
1ba585e8 IT |
1486 | PREFIX_EVEX_0FDC, |
1487 | PREFIX_EVEX_0FDD, | |
1488 | PREFIX_EVEX_0FDE, | |
43234a1e | 1489 | PREFIX_EVEX_0FDF, |
1ba585e8 IT |
1490 | PREFIX_EVEX_0FE0, |
1491 | PREFIX_EVEX_0FE1, | |
43234a1e | 1492 | PREFIX_EVEX_0FE2, |
1ba585e8 IT |
1493 | PREFIX_EVEX_0FE3, |
1494 | PREFIX_EVEX_0FE4, | |
1495 | PREFIX_EVEX_0FE5, | |
43234a1e L |
1496 | PREFIX_EVEX_0FE6, |
1497 | PREFIX_EVEX_0FE7, | |
1ba585e8 IT |
1498 | PREFIX_EVEX_0FE8, |
1499 | PREFIX_EVEX_0FE9, | |
1500 | PREFIX_EVEX_0FEA, | |
43234a1e | 1501 | PREFIX_EVEX_0FEB, |
1ba585e8 IT |
1502 | PREFIX_EVEX_0FEC, |
1503 | PREFIX_EVEX_0FED, | |
1504 | PREFIX_EVEX_0FEE, | |
43234a1e | 1505 | PREFIX_EVEX_0FEF, |
1ba585e8 | 1506 | PREFIX_EVEX_0FF1, |
43234a1e L |
1507 | PREFIX_EVEX_0FF2, |
1508 | PREFIX_EVEX_0FF3, | |
1509 | PREFIX_EVEX_0FF4, | |
1ba585e8 IT |
1510 | PREFIX_EVEX_0FF5, |
1511 | PREFIX_EVEX_0FF6, | |
1512 | PREFIX_EVEX_0FF8, | |
1513 | PREFIX_EVEX_0FF9, | |
43234a1e L |
1514 | PREFIX_EVEX_0FFA, |
1515 | PREFIX_EVEX_0FFB, | |
1ba585e8 IT |
1516 | PREFIX_EVEX_0FFC, |
1517 | PREFIX_EVEX_0FFD, | |
43234a1e | 1518 | PREFIX_EVEX_0FFE, |
1ba585e8 IT |
1519 | PREFIX_EVEX_0F3800, |
1520 | PREFIX_EVEX_0F3804, | |
1521 | PREFIX_EVEX_0F380B, | |
43234a1e L |
1522 | PREFIX_EVEX_0F380C, |
1523 | PREFIX_EVEX_0F380D, | |
1ba585e8 | 1524 | PREFIX_EVEX_0F3810, |
43234a1e L |
1525 | PREFIX_EVEX_0F3811, |
1526 | PREFIX_EVEX_0F3812, | |
1527 | PREFIX_EVEX_0F3813, | |
1528 | PREFIX_EVEX_0F3814, | |
1529 | PREFIX_EVEX_0F3815, | |
1530 | PREFIX_EVEX_0F3816, | |
1531 | PREFIX_EVEX_0F3818, | |
1532 | PREFIX_EVEX_0F3819, | |
1533 | PREFIX_EVEX_0F381A, | |
1534 | PREFIX_EVEX_0F381B, | |
1ba585e8 IT |
1535 | PREFIX_EVEX_0F381C, |
1536 | PREFIX_EVEX_0F381D, | |
43234a1e L |
1537 | PREFIX_EVEX_0F381E, |
1538 | PREFIX_EVEX_0F381F, | |
1ba585e8 | 1539 | PREFIX_EVEX_0F3820, |
43234a1e L |
1540 | PREFIX_EVEX_0F3821, |
1541 | PREFIX_EVEX_0F3822, | |
1542 | PREFIX_EVEX_0F3823, | |
1543 | PREFIX_EVEX_0F3824, | |
1544 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1545 | PREFIX_EVEX_0F3826, |
43234a1e L |
1546 | PREFIX_EVEX_0F3827, |
1547 | PREFIX_EVEX_0F3828, | |
1548 | PREFIX_EVEX_0F3829, | |
1549 | PREFIX_EVEX_0F382A, | |
1ba585e8 | 1550 | PREFIX_EVEX_0F382B, |
43234a1e L |
1551 | PREFIX_EVEX_0F382C, |
1552 | PREFIX_EVEX_0F382D, | |
1ba585e8 | 1553 | PREFIX_EVEX_0F3830, |
43234a1e L |
1554 | PREFIX_EVEX_0F3831, |
1555 | PREFIX_EVEX_0F3832, | |
1556 | PREFIX_EVEX_0F3833, | |
1557 | PREFIX_EVEX_0F3834, | |
1558 | PREFIX_EVEX_0F3835, | |
1559 | PREFIX_EVEX_0F3836, | |
1560 | PREFIX_EVEX_0F3837, | |
1ba585e8 | 1561 | PREFIX_EVEX_0F3838, |
43234a1e L |
1562 | PREFIX_EVEX_0F3839, |
1563 | PREFIX_EVEX_0F383A, | |
1564 | PREFIX_EVEX_0F383B, | |
1ba585e8 | 1565 | PREFIX_EVEX_0F383C, |
43234a1e | 1566 | PREFIX_EVEX_0F383D, |
1ba585e8 | 1567 | PREFIX_EVEX_0F383E, |
43234a1e L |
1568 | PREFIX_EVEX_0F383F, |
1569 | PREFIX_EVEX_0F3840, | |
1570 | PREFIX_EVEX_0F3842, | |
1571 | PREFIX_EVEX_0F3843, | |
1572 | PREFIX_EVEX_0F3844, | |
1573 | PREFIX_EVEX_0F3845, | |
1574 | PREFIX_EVEX_0F3846, | |
1575 | PREFIX_EVEX_0F3847, | |
1576 | PREFIX_EVEX_0F384C, | |
1577 | PREFIX_EVEX_0F384D, | |
1578 | PREFIX_EVEX_0F384E, | |
1579 | PREFIX_EVEX_0F384F, | |
8cfcb765 IT |
1580 | PREFIX_EVEX_0F3850, |
1581 | PREFIX_EVEX_0F3851, | |
47acf0bd IT |
1582 | PREFIX_EVEX_0F3852, |
1583 | PREFIX_EVEX_0F3853, | |
ee6872be | 1584 | PREFIX_EVEX_0F3854, |
620214f7 | 1585 | PREFIX_EVEX_0F3855, |
43234a1e L |
1586 | PREFIX_EVEX_0F3858, |
1587 | PREFIX_EVEX_0F3859, | |
1588 | PREFIX_EVEX_0F385A, | |
1589 | PREFIX_EVEX_0F385B, | |
53467f57 IT |
1590 | PREFIX_EVEX_0F3862, |
1591 | PREFIX_EVEX_0F3863, | |
43234a1e L |
1592 | PREFIX_EVEX_0F3864, |
1593 | PREFIX_EVEX_0F3865, | |
1ba585e8 | 1594 | PREFIX_EVEX_0F3866, |
53467f57 IT |
1595 | PREFIX_EVEX_0F3870, |
1596 | PREFIX_EVEX_0F3871, | |
1597 | PREFIX_EVEX_0F3872, | |
1598 | PREFIX_EVEX_0F3873, | |
1ba585e8 | 1599 | PREFIX_EVEX_0F3875, |
43234a1e L |
1600 | PREFIX_EVEX_0F3876, |
1601 | PREFIX_EVEX_0F3877, | |
1ba585e8 IT |
1602 | PREFIX_EVEX_0F3878, |
1603 | PREFIX_EVEX_0F3879, | |
1604 | PREFIX_EVEX_0F387A, | |
1605 | PREFIX_EVEX_0F387B, | |
43234a1e | 1606 | PREFIX_EVEX_0F387C, |
1ba585e8 | 1607 | PREFIX_EVEX_0F387D, |
43234a1e L |
1608 | PREFIX_EVEX_0F387E, |
1609 | PREFIX_EVEX_0F387F, | |
14f195c9 | 1610 | PREFIX_EVEX_0F3883, |
43234a1e L |
1611 | PREFIX_EVEX_0F3888, |
1612 | PREFIX_EVEX_0F3889, | |
1613 | PREFIX_EVEX_0F388A, | |
1614 | PREFIX_EVEX_0F388B, | |
1ba585e8 | 1615 | PREFIX_EVEX_0F388D, |
ee6872be | 1616 | PREFIX_EVEX_0F388F, |
43234a1e L |
1617 | PREFIX_EVEX_0F3890, |
1618 | PREFIX_EVEX_0F3891, | |
1619 | PREFIX_EVEX_0F3892, | |
1620 | PREFIX_EVEX_0F3893, | |
1621 | PREFIX_EVEX_0F3896, | |
1622 | PREFIX_EVEX_0F3897, | |
1623 | PREFIX_EVEX_0F3898, | |
1624 | PREFIX_EVEX_0F3899, | |
1625 | PREFIX_EVEX_0F389A, | |
1626 | PREFIX_EVEX_0F389B, | |
1627 | PREFIX_EVEX_0F389C, | |
1628 | PREFIX_EVEX_0F389D, | |
1629 | PREFIX_EVEX_0F389E, | |
1630 | PREFIX_EVEX_0F389F, | |
1631 | PREFIX_EVEX_0F38A0, | |
1632 | PREFIX_EVEX_0F38A1, | |
1633 | PREFIX_EVEX_0F38A2, | |
1634 | PREFIX_EVEX_0F38A3, | |
1635 | PREFIX_EVEX_0F38A6, | |
1636 | PREFIX_EVEX_0F38A7, | |
1637 | PREFIX_EVEX_0F38A8, | |
1638 | PREFIX_EVEX_0F38A9, | |
1639 | PREFIX_EVEX_0F38AA, | |
1640 | PREFIX_EVEX_0F38AB, | |
1641 | PREFIX_EVEX_0F38AC, | |
1642 | PREFIX_EVEX_0F38AD, | |
1643 | PREFIX_EVEX_0F38AE, | |
1644 | PREFIX_EVEX_0F38AF, | |
2cc1b5aa IT |
1645 | PREFIX_EVEX_0F38B4, |
1646 | PREFIX_EVEX_0F38B5, | |
43234a1e L |
1647 | PREFIX_EVEX_0F38B6, |
1648 | PREFIX_EVEX_0F38B7, | |
1649 | PREFIX_EVEX_0F38B8, | |
1650 | PREFIX_EVEX_0F38B9, | |
1651 | PREFIX_EVEX_0F38BA, | |
1652 | PREFIX_EVEX_0F38BB, | |
1653 | PREFIX_EVEX_0F38BC, | |
1654 | PREFIX_EVEX_0F38BD, | |
1655 | PREFIX_EVEX_0F38BE, | |
1656 | PREFIX_EVEX_0F38BF, | |
1657 | PREFIX_EVEX_0F38C4, | |
1658 | PREFIX_EVEX_0F38C6_REG_1, | |
1659 | PREFIX_EVEX_0F38C6_REG_2, | |
1660 | PREFIX_EVEX_0F38C6_REG_5, | |
1661 | PREFIX_EVEX_0F38C6_REG_6, | |
1662 | PREFIX_EVEX_0F38C7_REG_1, | |
1663 | PREFIX_EVEX_0F38C7_REG_2, | |
1664 | PREFIX_EVEX_0F38C7_REG_5, | |
1665 | PREFIX_EVEX_0F38C7_REG_6, | |
1666 | PREFIX_EVEX_0F38C8, | |
1667 | PREFIX_EVEX_0F38CA, | |
1668 | PREFIX_EVEX_0F38CB, | |
1669 | PREFIX_EVEX_0F38CC, | |
1670 | PREFIX_EVEX_0F38CD, | |
48521003 | 1671 | PREFIX_EVEX_0F38CF, |
8dcf1fad IT |
1672 | PREFIX_EVEX_0F38DC, |
1673 | PREFIX_EVEX_0F38DD, | |
1674 | PREFIX_EVEX_0F38DE, | |
1675 | PREFIX_EVEX_0F38DF, | |
43234a1e L |
1676 | |
1677 | PREFIX_EVEX_0F3A00, | |
1678 | PREFIX_EVEX_0F3A01, | |
1679 | PREFIX_EVEX_0F3A03, | |
1680 | PREFIX_EVEX_0F3A04, | |
1681 | PREFIX_EVEX_0F3A05, | |
1682 | PREFIX_EVEX_0F3A08, | |
1683 | PREFIX_EVEX_0F3A09, | |
1684 | PREFIX_EVEX_0F3A0A, | |
1685 | PREFIX_EVEX_0F3A0B, | |
1ba585e8 IT |
1686 | PREFIX_EVEX_0F3A0F, |
1687 | PREFIX_EVEX_0F3A14, | |
1688 | PREFIX_EVEX_0F3A15, | |
90a915bf | 1689 | PREFIX_EVEX_0F3A16, |
43234a1e L |
1690 | PREFIX_EVEX_0F3A17, |
1691 | PREFIX_EVEX_0F3A18, | |
1692 | PREFIX_EVEX_0F3A19, | |
1693 | PREFIX_EVEX_0F3A1A, | |
1694 | PREFIX_EVEX_0F3A1B, | |
1695 | PREFIX_EVEX_0F3A1D, | |
1696 | PREFIX_EVEX_0F3A1E, | |
1697 | PREFIX_EVEX_0F3A1F, | |
1ba585e8 | 1698 | PREFIX_EVEX_0F3A20, |
43234a1e | 1699 | PREFIX_EVEX_0F3A21, |
90a915bf | 1700 | PREFIX_EVEX_0F3A22, |
43234a1e L |
1701 | PREFIX_EVEX_0F3A23, |
1702 | PREFIX_EVEX_0F3A25, | |
1703 | PREFIX_EVEX_0F3A26, | |
1704 | PREFIX_EVEX_0F3A27, | |
1705 | PREFIX_EVEX_0F3A38, | |
1706 | PREFIX_EVEX_0F3A39, | |
1707 | PREFIX_EVEX_0F3A3A, | |
1708 | PREFIX_EVEX_0F3A3B, | |
1ba585e8 IT |
1709 | PREFIX_EVEX_0F3A3E, |
1710 | PREFIX_EVEX_0F3A3F, | |
1711 | PREFIX_EVEX_0F3A42, | |
43234a1e | 1712 | PREFIX_EVEX_0F3A43, |
ff1982d5 | 1713 | PREFIX_EVEX_0F3A44, |
90a915bf IT |
1714 | PREFIX_EVEX_0F3A50, |
1715 | PREFIX_EVEX_0F3A51, | |
43234a1e | 1716 | PREFIX_EVEX_0F3A54, |
90a915bf IT |
1717 | PREFIX_EVEX_0F3A55, |
1718 | PREFIX_EVEX_0F3A56, | |
1719 | PREFIX_EVEX_0F3A57, | |
1720 | PREFIX_EVEX_0F3A66, | |
53467f57 IT |
1721 | PREFIX_EVEX_0F3A67, |
1722 | PREFIX_EVEX_0F3A70, | |
1723 | PREFIX_EVEX_0F3A71, | |
1724 | PREFIX_EVEX_0F3A72, | |
48521003 IT |
1725 | PREFIX_EVEX_0F3A73, |
1726 | PREFIX_EVEX_0F3ACE, | |
1727 | PREFIX_EVEX_0F3ACF | |
51e7da1b | 1728 | }; |
4e7d34a6 | 1729 | |
51e7da1b L |
1730 | enum |
1731 | { | |
1732 | X86_64_06 = 0, | |
3873ba12 L |
1733 | X86_64_07, |
1734 | X86_64_0D, | |
1735 | X86_64_16, | |
1736 | X86_64_17, | |
1737 | X86_64_1E, | |
1738 | X86_64_1F, | |
1739 | X86_64_27, | |
1740 | X86_64_2F, | |
1741 | X86_64_37, | |
1742 | X86_64_3F, | |
1743 | X86_64_60, | |
1744 | X86_64_61, | |
1745 | X86_64_62, | |
1746 | X86_64_63, | |
1747 | X86_64_6D, | |
1748 | X86_64_6F, | |
d039fef3 | 1749 | X86_64_82, |
3873ba12 L |
1750 | X86_64_9A, |
1751 | X86_64_C4, | |
1752 | X86_64_C5, | |
1753 | X86_64_CE, | |
1754 | X86_64_D4, | |
1755 | X86_64_D5, | |
a72d2af2 L |
1756 | X86_64_E8, |
1757 | X86_64_E9, | |
3873ba12 L |
1758 | X86_64_EA, |
1759 | X86_64_0F01_REG_0, | |
1760 | X86_64_0F01_REG_1, | |
1761 | X86_64_0F01_REG_2, | |
1762 | X86_64_0F01_REG_3 | |
51e7da1b | 1763 | }; |
4e7d34a6 | 1764 | |
51e7da1b L |
1765 | enum |
1766 | { | |
1767 | THREE_BYTE_0F38 = 0, | |
1f334aeb | 1768 | THREE_BYTE_0F3A |
51e7da1b | 1769 | }; |
4e7d34a6 | 1770 | |
f88c9eb0 SP |
1771 | enum |
1772 | { | |
5dd85c99 SP |
1773 | XOP_08 = 0, |
1774 | XOP_09, | |
f88c9eb0 SP |
1775 | XOP_0A |
1776 | }; | |
1777 | ||
51e7da1b L |
1778 | enum |
1779 | { | |
1780 | VEX_0F = 0, | |
3873ba12 L |
1781 | VEX_0F38, |
1782 | VEX_0F3A | |
51e7da1b | 1783 | }; |
c0f3af97 | 1784 | |
43234a1e L |
1785 | enum |
1786 | { | |
1787 | EVEX_0F = 0, | |
1788 | EVEX_0F38, | |
1789 | EVEX_0F3A | |
1790 | }; | |
1791 | ||
51e7da1b L |
1792 | enum |
1793 | { | |
592a252b L |
1794 | VEX_LEN_0F10_P_1 = 0, |
1795 | VEX_LEN_0F10_P_3, | |
1796 | VEX_LEN_0F11_P_1, | |
1797 | VEX_LEN_0F11_P_3, | |
1798 | VEX_LEN_0F12_P_0_M_0, | |
1799 | VEX_LEN_0F12_P_0_M_1, | |
1800 | VEX_LEN_0F12_P_2, | |
1801 | VEX_LEN_0F13_M_0, | |
1802 | VEX_LEN_0F16_P_0_M_0, | |
1803 | VEX_LEN_0F16_P_0_M_1, | |
1804 | VEX_LEN_0F16_P_2, | |
1805 | VEX_LEN_0F17_M_0, | |
1806 | VEX_LEN_0F2A_P_1, | |
1807 | VEX_LEN_0F2A_P_3, | |
1808 | VEX_LEN_0F2C_P_1, | |
1809 | VEX_LEN_0F2C_P_3, | |
1810 | VEX_LEN_0F2D_P_1, | |
1811 | VEX_LEN_0F2D_P_3, | |
1812 | VEX_LEN_0F2E_P_0, | |
1813 | VEX_LEN_0F2E_P_2, | |
1814 | VEX_LEN_0F2F_P_0, | |
1815 | VEX_LEN_0F2F_P_2, | |
43234a1e | 1816 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1817 | VEX_LEN_0F41_P_2, |
43234a1e | 1818 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1819 | VEX_LEN_0F42_P_2, |
43234a1e | 1820 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1821 | VEX_LEN_0F44_P_2, |
43234a1e | 1822 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1823 | VEX_LEN_0F45_P_2, |
43234a1e | 1824 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1825 | VEX_LEN_0F46_P_2, |
43234a1e | 1826 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1827 | VEX_LEN_0F47_P_2, |
1828 | VEX_LEN_0F4A_P_0, | |
1829 | VEX_LEN_0F4A_P_2, | |
1830 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1831 | VEX_LEN_0F4B_P_2, |
592a252b L |
1832 | VEX_LEN_0F51_P_1, |
1833 | VEX_LEN_0F51_P_3, | |
1834 | VEX_LEN_0F52_P_1, | |
1835 | VEX_LEN_0F53_P_1, | |
1836 | VEX_LEN_0F58_P_1, | |
1837 | VEX_LEN_0F58_P_3, | |
1838 | VEX_LEN_0F59_P_1, | |
1839 | VEX_LEN_0F59_P_3, | |
1840 | VEX_LEN_0F5A_P_1, | |
1841 | VEX_LEN_0F5A_P_3, | |
1842 | VEX_LEN_0F5C_P_1, | |
1843 | VEX_LEN_0F5C_P_3, | |
1844 | VEX_LEN_0F5D_P_1, | |
1845 | VEX_LEN_0F5D_P_3, | |
1846 | VEX_LEN_0F5E_P_1, | |
1847 | VEX_LEN_0F5E_P_3, | |
1848 | VEX_LEN_0F5F_P_1, | |
1849 | VEX_LEN_0F5F_P_3, | |
592a252b | 1850 | VEX_LEN_0F6E_P_2, |
592a252b L |
1851 | VEX_LEN_0F7E_P_1, |
1852 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1853 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1854 | VEX_LEN_0F90_P_2, |
43234a1e | 1855 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1856 | VEX_LEN_0F91_P_2, |
43234a1e | 1857 | VEX_LEN_0F92_P_0, |
90a915bf | 1858 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1859 | VEX_LEN_0F92_P_3, |
43234a1e | 1860 | VEX_LEN_0F93_P_0, |
90a915bf | 1861 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1862 | VEX_LEN_0F93_P_3, |
43234a1e | 1863 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1864 | VEX_LEN_0F98_P_2, |
1865 | VEX_LEN_0F99_P_0, | |
1866 | VEX_LEN_0F99_P_2, | |
592a252b L |
1867 | VEX_LEN_0FAE_R_2_M_0, |
1868 | VEX_LEN_0FAE_R_3_M_0, | |
1869 | VEX_LEN_0FC2_P_1, | |
1870 | VEX_LEN_0FC2_P_3, | |
1871 | VEX_LEN_0FC4_P_2, | |
1872 | VEX_LEN_0FC5_P_2, | |
592a252b | 1873 | VEX_LEN_0FD6_P_2, |
592a252b | 1874 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1875 | VEX_LEN_0F3816_P_2, |
1876 | VEX_LEN_0F3819_P_2, | |
592a252b | 1877 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1878 | VEX_LEN_0F3836_P_2, |
592a252b | 1879 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1880 | VEX_LEN_0F385A_P_2_M_0, |
592a252b | 1881 | VEX_LEN_0F38DB_P_2, |
f12dc422 L |
1882 | VEX_LEN_0F38F2_P_0, |
1883 | VEX_LEN_0F38F3_R_1_P_0, | |
1884 | VEX_LEN_0F38F3_R_2_P_0, | |
1885 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1886 | VEX_LEN_0F38F5_P_0, |
1887 | VEX_LEN_0F38F5_P_1, | |
1888 | VEX_LEN_0F38F5_P_3, | |
1889 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1890 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1891 | VEX_LEN_0F38F7_P_1, |
1892 | VEX_LEN_0F38F7_P_2, | |
1893 | VEX_LEN_0F38F7_P_3, | |
1894 | VEX_LEN_0F3A00_P_2, | |
1895 | VEX_LEN_0F3A01_P_2, | |
592a252b L |
1896 | VEX_LEN_0F3A06_P_2, |
1897 | VEX_LEN_0F3A0A_P_2, | |
1898 | VEX_LEN_0F3A0B_P_2, | |
592a252b L |
1899 | VEX_LEN_0F3A14_P_2, |
1900 | VEX_LEN_0F3A15_P_2, | |
1901 | VEX_LEN_0F3A16_P_2, | |
1902 | VEX_LEN_0F3A17_P_2, | |
1903 | VEX_LEN_0F3A18_P_2, | |
1904 | VEX_LEN_0F3A19_P_2, | |
1905 | VEX_LEN_0F3A20_P_2, | |
1906 | VEX_LEN_0F3A21_P_2, | |
1907 | VEX_LEN_0F3A22_P_2, | |
43234a1e | 1908 | VEX_LEN_0F3A30_P_2, |
1ba585e8 | 1909 | VEX_LEN_0F3A31_P_2, |
43234a1e | 1910 | VEX_LEN_0F3A32_P_2, |
1ba585e8 | 1911 | VEX_LEN_0F3A33_P_2, |
6c30d220 L |
1912 | VEX_LEN_0F3A38_P_2, |
1913 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1914 | VEX_LEN_0F3A41_P_2, |
6c30d220 | 1915 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1916 | VEX_LEN_0F3A60_P_2, |
1917 | VEX_LEN_0F3A61_P_2, | |
1918 | VEX_LEN_0F3A62_P_2, | |
1919 | VEX_LEN_0F3A63_P_2, | |
1920 | VEX_LEN_0F3A6A_P_2, | |
1921 | VEX_LEN_0F3A6B_P_2, | |
1922 | VEX_LEN_0F3A6E_P_2, | |
1923 | VEX_LEN_0F3A6F_P_2, | |
1924 | VEX_LEN_0F3A7A_P_2, | |
1925 | VEX_LEN_0F3A7B_P_2, | |
1926 | VEX_LEN_0F3A7E_P_2, | |
1927 | VEX_LEN_0F3A7F_P_2, | |
1928 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1929 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1930 | VEX_LEN_0FXOP_08_CC, |
1931 | VEX_LEN_0FXOP_08_CD, | |
1932 | VEX_LEN_0FXOP_08_CE, | |
1933 | VEX_LEN_0FXOP_08_CF, | |
1934 | VEX_LEN_0FXOP_08_EC, | |
1935 | VEX_LEN_0FXOP_08_ED, | |
1936 | VEX_LEN_0FXOP_08_EE, | |
1937 | VEX_LEN_0FXOP_08_EF, | |
592a252b L |
1938 | VEX_LEN_0FXOP_09_80, |
1939 | VEX_LEN_0FXOP_09_81 | |
51e7da1b | 1940 | }; |
c0f3af97 | 1941 | |
9e30b8e0 L |
1942 | enum |
1943 | { | |
592a252b L |
1944 | VEX_W_0F10_P_0 = 0, |
1945 | VEX_W_0F10_P_1, | |
1946 | VEX_W_0F10_P_2, | |
1947 | VEX_W_0F10_P_3, | |
1948 | VEX_W_0F11_P_0, | |
1949 | VEX_W_0F11_P_1, | |
1950 | VEX_W_0F11_P_2, | |
1951 | VEX_W_0F11_P_3, | |
1952 | VEX_W_0F12_P_0_M_0, | |
1953 | VEX_W_0F12_P_0_M_1, | |
1954 | VEX_W_0F12_P_1, | |
1955 | VEX_W_0F12_P_2, | |
1956 | VEX_W_0F12_P_3, | |
1957 | VEX_W_0F13_M_0, | |
1958 | VEX_W_0F14, | |
1959 | VEX_W_0F15, | |
1960 | VEX_W_0F16_P_0_M_0, | |
1961 | VEX_W_0F16_P_0_M_1, | |
1962 | VEX_W_0F16_P_1, | |
1963 | VEX_W_0F16_P_2, | |
1964 | VEX_W_0F17_M_0, | |
1965 | VEX_W_0F28, | |
1966 | VEX_W_0F29, | |
1967 | VEX_W_0F2B_M_0, | |
1968 | VEX_W_0F2E_P_0, | |
1969 | VEX_W_0F2E_P_2, | |
1970 | VEX_W_0F2F_P_0, | |
1971 | VEX_W_0F2F_P_2, | |
43234a1e | 1972 | VEX_W_0F41_P_0_LEN_1, |
1ba585e8 | 1973 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1974 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1975 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1976 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1977 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1978 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1979 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1980 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1981 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1982 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1983 | VEX_W_0F47_P_2_LEN_1, |
1984 | VEX_W_0F4A_P_0_LEN_1, | |
1985 | VEX_W_0F4A_P_2_LEN_1, | |
1986 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1987 | VEX_W_0F4B_P_2_LEN_1, |
592a252b L |
1988 | VEX_W_0F50_M_0, |
1989 | VEX_W_0F51_P_0, | |
1990 | VEX_W_0F51_P_1, | |
1991 | VEX_W_0F51_P_2, | |
1992 | VEX_W_0F51_P_3, | |
1993 | VEX_W_0F52_P_0, | |
1994 | VEX_W_0F52_P_1, | |
1995 | VEX_W_0F53_P_0, | |
1996 | VEX_W_0F53_P_1, | |
1997 | VEX_W_0F58_P_0, | |
1998 | VEX_W_0F58_P_1, | |
1999 | VEX_W_0F58_P_2, | |
2000 | VEX_W_0F58_P_3, | |
2001 | VEX_W_0F59_P_0, | |
2002 | VEX_W_0F59_P_1, | |
2003 | VEX_W_0F59_P_2, | |
2004 | VEX_W_0F59_P_3, | |
2005 | VEX_W_0F5A_P_0, | |
2006 | VEX_W_0F5A_P_1, | |
2007 | VEX_W_0F5A_P_3, | |
2008 | VEX_W_0F5B_P_0, | |
2009 | VEX_W_0F5B_P_1, | |
2010 | VEX_W_0F5B_P_2, | |
2011 | VEX_W_0F5C_P_0, | |
2012 | VEX_W_0F5C_P_1, | |
2013 | VEX_W_0F5C_P_2, | |
2014 | VEX_W_0F5C_P_3, | |
2015 | VEX_W_0F5D_P_0, | |
2016 | VEX_W_0F5D_P_1, | |
2017 | VEX_W_0F5D_P_2, | |
2018 | VEX_W_0F5D_P_3, | |
2019 | VEX_W_0F5E_P_0, | |
2020 | VEX_W_0F5E_P_1, | |
2021 | VEX_W_0F5E_P_2, | |
2022 | VEX_W_0F5E_P_3, | |
2023 | VEX_W_0F5F_P_0, | |
2024 | VEX_W_0F5F_P_1, | |
2025 | VEX_W_0F5F_P_2, | |
2026 | VEX_W_0F5F_P_3, | |
2027 | VEX_W_0F60_P_2, | |
2028 | VEX_W_0F61_P_2, | |
2029 | VEX_W_0F62_P_2, | |
2030 | VEX_W_0F63_P_2, | |
2031 | VEX_W_0F64_P_2, | |
2032 | VEX_W_0F65_P_2, | |
2033 | VEX_W_0F66_P_2, | |
2034 | VEX_W_0F67_P_2, | |
2035 | VEX_W_0F68_P_2, | |
2036 | VEX_W_0F69_P_2, | |
2037 | VEX_W_0F6A_P_2, | |
2038 | VEX_W_0F6B_P_2, | |
2039 | VEX_W_0F6C_P_2, | |
2040 | VEX_W_0F6D_P_2, | |
2041 | VEX_W_0F6F_P_1, | |
2042 | VEX_W_0F6F_P_2, | |
2043 | VEX_W_0F70_P_1, | |
2044 | VEX_W_0F70_P_2, | |
2045 | VEX_W_0F70_P_3, | |
2046 | VEX_W_0F71_R_2_P_2, | |
2047 | VEX_W_0F71_R_4_P_2, | |
2048 | VEX_W_0F71_R_6_P_2, | |
2049 | VEX_W_0F72_R_2_P_2, | |
2050 | VEX_W_0F72_R_4_P_2, | |
2051 | VEX_W_0F72_R_6_P_2, | |
2052 | VEX_W_0F73_R_2_P_2, | |
2053 | VEX_W_0F73_R_3_P_2, | |
2054 | VEX_W_0F73_R_6_P_2, | |
2055 | VEX_W_0F73_R_7_P_2, | |
2056 | VEX_W_0F74_P_2, | |
2057 | VEX_W_0F75_P_2, | |
2058 | VEX_W_0F76_P_2, | |
2059 | VEX_W_0F77_P_0, | |
2060 | VEX_W_0F7C_P_2, | |
2061 | VEX_W_0F7C_P_3, | |
2062 | VEX_W_0F7D_P_2, | |
2063 | VEX_W_0F7D_P_3, | |
2064 | VEX_W_0F7E_P_1, | |
2065 | VEX_W_0F7F_P_1, | |
2066 | VEX_W_0F7F_P_2, | |
43234a1e | 2067 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 2068 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 2069 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 2070 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 2071 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 2072 | VEX_W_0F92_P_2_LEN_0, |
1ba585e8 | 2073 | VEX_W_0F92_P_3_LEN_0, |
43234a1e | 2074 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 2075 | VEX_W_0F93_P_2_LEN_0, |
1ba585e8 | 2076 | VEX_W_0F93_P_3_LEN_0, |
43234a1e | 2077 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
2078 | VEX_W_0F98_P_2_LEN_0, |
2079 | VEX_W_0F99_P_0_LEN_0, | |
2080 | VEX_W_0F99_P_2_LEN_0, | |
592a252b L |
2081 | VEX_W_0FAE_R_2_M_0, |
2082 | VEX_W_0FAE_R_3_M_0, | |
2083 | VEX_W_0FC2_P_0, | |
2084 | VEX_W_0FC2_P_1, | |
2085 | VEX_W_0FC2_P_2, | |
2086 | VEX_W_0FC2_P_3, | |
2087 | VEX_W_0FC4_P_2, | |
2088 | VEX_W_0FC5_P_2, | |
2089 | VEX_W_0FD0_P_2, | |
2090 | VEX_W_0FD0_P_3, | |
2091 | VEX_W_0FD1_P_2, | |
2092 | VEX_W_0FD2_P_2, | |
2093 | VEX_W_0FD3_P_2, | |
2094 | VEX_W_0FD4_P_2, | |
2095 | VEX_W_0FD5_P_2, | |
2096 | VEX_W_0FD6_P_2, | |
2097 | VEX_W_0FD7_P_2_M_1, | |
2098 | VEX_W_0FD8_P_2, | |
2099 | VEX_W_0FD9_P_2, | |
2100 | VEX_W_0FDA_P_2, | |
2101 | VEX_W_0FDB_P_2, | |
2102 | VEX_W_0FDC_P_2, | |
2103 | VEX_W_0FDD_P_2, | |
2104 | VEX_W_0FDE_P_2, | |
2105 | VEX_W_0FDF_P_2, | |
2106 | VEX_W_0FE0_P_2, | |
2107 | VEX_W_0FE1_P_2, | |
2108 | VEX_W_0FE2_P_2, | |
2109 | VEX_W_0FE3_P_2, | |
2110 | VEX_W_0FE4_P_2, | |
2111 | VEX_W_0FE5_P_2, | |
2112 | VEX_W_0FE6_P_1, | |
2113 | VEX_W_0FE6_P_2, | |
2114 | VEX_W_0FE6_P_3, | |
2115 | VEX_W_0FE7_P_2_M_0, | |
2116 | VEX_W_0FE8_P_2, | |
2117 | VEX_W_0FE9_P_2, | |
2118 | VEX_W_0FEA_P_2, | |
2119 | VEX_W_0FEB_P_2, | |
2120 | VEX_W_0FEC_P_2, | |
2121 | VEX_W_0FED_P_2, | |
2122 | VEX_W_0FEE_P_2, | |
2123 | VEX_W_0FEF_P_2, | |
2124 | VEX_W_0FF0_P_3_M_0, | |
2125 | VEX_W_0FF1_P_2, | |
2126 | VEX_W_0FF2_P_2, | |
2127 | VEX_W_0FF3_P_2, | |
2128 | VEX_W_0FF4_P_2, | |
2129 | VEX_W_0FF5_P_2, | |
2130 | VEX_W_0FF6_P_2, | |
2131 | VEX_W_0FF7_P_2, | |
2132 | VEX_W_0FF8_P_2, | |
2133 | VEX_W_0FF9_P_2, | |
2134 | VEX_W_0FFA_P_2, | |
2135 | VEX_W_0FFB_P_2, | |
2136 | VEX_W_0FFC_P_2, | |
2137 | VEX_W_0FFD_P_2, | |
2138 | VEX_W_0FFE_P_2, | |
2139 | VEX_W_0F3800_P_2, | |
2140 | VEX_W_0F3801_P_2, | |
2141 | VEX_W_0F3802_P_2, | |
2142 | VEX_W_0F3803_P_2, | |
2143 | VEX_W_0F3804_P_2, | |
2144 | VEX_W_0F3805_P_2, | |
2145 | VEX_W_0F3806_P_2, | |
2146 | VEX_W_0F3807_P_2, | |
2147 | VEX_W_0F3808_P_2, | |
2148 | VEX_W_0F3809_P_2, | |
2149 | VEX_W_0F380A_P_2, | |
2150 | VEX_W_0F380B_P_2, | |
2151 | VEX_W_0F380C_P_2, | |
2152 | VEX_W_0F380D_P_2, | |
2153 | VEX_W_0F380E_P_2, | |
2154 | VEX_W_0F380F_P_2, | |
6c30d220 | 2155 | VEX_W_0F3816_P_2, |
592a252b | 2156 | VEX_W_0F3817_P_2, |
6c30d220 L |
2157 | VEX_W_0F3818_P_2, |
2158 | VEX_W_0F3819_P_2, | |
592a252b L |
2159 | VEX_W_0F381A_P_2_M_0, |
2160 | VEX_W_0F381C_P_2, | |
2161 | VEX_W_0F381D_P_2, | |
2162 | VEX_W_0F381E_P_2, | |
2163 | VEX_W_0F3820_P_2, | |
2164 | VEX_W_0F3821_P_2, | |
2165 | VEX_W_0F3822_P_2, | |
2166 | VEX_W_0F3823_P_2, | |
2167 | VEX_W_0F3824_P_2, | |
2168 | VEX_W_0F3825_P_2, | |
2169 | VEX_W_0F3828_P_2, | |
2170 | VEX_W_0F3829_P_2, | |
2171 | VEX_W_0F382A_P_2_M_0, | |
2172 | VEX_W_0F382B_P_2, | |
2173 | VEX_W_0F382C_P_2_M_0, | |
2174 | VEX_W_0F382D_P_2_M_0, | |
2175 | VEX_W_0F382E_P_2_M_0, | |
2176 | VEX_W_0F382F_P_2_M_0, | |
2177 | VEX_W_0F3830_P_2, | |
2178 | VEX_W_0F3831_P_2, | |
2179 | VEX_W_0F3832_P_2, | |
2180 | VEX_W_0F3833_P_2, | |
2181 | VEX_W_0F3834_P_2, | |
2182 | VEX_W_0F3835_P_2, | |
6c30d220 | 2183 | VEX_W_0F3836_P_2, |
592a252b L |
2184 | VEX_W_0F3837_P_2, |
2185 | VEX_W_0F3838_P_2, | |
2186 | VEX_W_0F3839_P_2, | |
2187 | VEX_W_0F383A_P_2, | |
2188 | VEX_W_0F383B_P_2, | |
2189 | VEX_W_0F383C_P_2, | |
2190 | VEX_W_0F383D_P_2, | |
2191 | VEX_W_0F383E_P_2, | |
2192 | VEX_W_0F383F_P_2, | |
2193 | VEX_W_0F3840_P_2, | |
2194 | VEX_W_0F3841_P_2, | |
6c30d220 L |
2195 | VEX_W_0F3846_P_2, |
2196 | VEX_W_0F3858_P_2, | |
2197 | VEX_W_0F3859_P_2, | |
2198 | VEX_W_0F385A_P_2_M_0, | |
2199 | VEX_W_0F3878_P_2, | |
2200 | VEX_W_0F3879_P_2, | |
48521003 | 2201 | VEX_W_0F38CF_P_2, |
592a252b | 2202 | VEX_W_0F38DB_P_2, |
6c30d220 L |
2203 | VEX_W_0F3A00_P_2, |
2204 | VEX_W_0F3A01_P_2, | |
2205 | VEX_W_0F3A02_P_2, | |
592a252b L |
2206 | VEX_W_0F3A04_P_2, |
2207 | VEX_W_0F3A05_P_2, | |
2208 | VEX_W_0F3A06_P_2, | |
2209 | VEX_W_0F3A08_P_2, | |
2210 | VEX_W_0F3A09_P_2, | |
2211 | VEX_W_0F3A0A_P_2, | |
2212 | VEX_W_0F3A0B_P_2, | |
2213 | VEX_W_0F3A0C_P_2, | |
2214 | VEX_W_0F3A0D_P_2, | |
2215 | VEX_W_0F3A0E_P_2, | |
2216 | VEX_W_0F3A0F_P_2, | |
2217 | VEX_W_0F3A14_P_2, | |
2218 | VEX_W_0F3A15_P_2, | |
2219 | VEX_W_0F3A18_P_2, | |
2220 | VEX_W_0F3A19_P_2, | |
2221 | VEX_W_0F3A20_P_2, | |
2222 | VEX_W_0F3A21_P_2, | |
43234a1e | 2223 | VEX_W_0F3A30_P_2_LEN_0, |
1ba585e8 | 2224 | VEX_W_0F3A31_P_2_LEN_0, |
43234a1e | 2225 | VEX_W_0F3A32_P_2_LEN_0, |
1ba585e8 | 2226 | VEX_W_0F3A33_P_2_LEN_0, |
6c30d220 L |
2227 | VEX_W_0F3A38_P_2, |
2228 | VEX_W_0F3A39_P_2, | |
592a252b L |
2229 | VEX_W_0F3A40_P_2, |
2230 | VEX_W_0F3A41_P_2, | |
2231 | VEX_W_0F3A42_P_2, | |
6c30d220 | 2232 | VEX_W_0F3A46_P_2, |
592a252b L |
2233 | VEX_W_0F3A48_P_2, |
2234 | VEX_W_0F3A49_P_2, | |
2235 | VEX_W_0F3A4A_P_2, | |
2236 | VEX_W_0F3A4B_P_2, | |
2237 | VEX_W_0F3A4C_P_2, | |
592a252b L |
2238 | VEX_W_0F3A62_P_2, |
2239 | VEX_W_0F3A63_P_2, | |
48521003 IT |
2240 | VEX_W_0F3ACE_P_2, |
2241 | VEX_W_0F3ACF_P_2, | |
43234a1e L |
2242 | VEX_W_0F3ADF_P_2, |
2243 | ||
2244 | EVEX_W_0F10_P_0, | |
2245 | EVEX_W_0F10_P_1_M_0, | |
2246 | EVEX_W_0F10_P_1_M_1, | |
2247 | EVEX_W_0F10_P_2, | |
2248 | EVEX_W_0F10_P_3_M_0, | |
2249 | EVEX_W_0F10_P_3_M_1, | |
2250 | EVEX_W_0F11_P_0, | |
2251 | EVEX_W_0F11_P_1_M_0, | |
2252 | EVEX_W_0F11_P_1_M_1, | |
2253 | EVEX_W_0F11_P_2, | |
2254 | EVEX_W_0F11_P_3_M_0, | |
2255 | EVEX_W_0F11_P_3_M_1, | |
2256 | EVEX_W_0F12_P_0_M_0, | |
2257 | EVEX_W_0F12_P_0_M_1, | |
2258 | EVEX_W_0F12_P_1, | |
2259 | EVEX_W_0F12_P_2, | |
2260 | EVEX_W_0F12_P_3, | |
2261 | EVEX_W_0F13_P_0, | |
2262 | EVEX_W_0F13_P_2, | |
2263 | EVEX_W_0F14_P_0, | |
2264 | EVEX_W_0F14_P_2, | |
2265 | EVEX_W_0F15_P_0, | |
2266 | EVEX_W_0F15_P_2, | |
2267 | EVEX_W_0F16_P_0_M_0, | |
2268 | EVEX_W_0F16_P_0_M_1, | |
2269 | EVEX_W_0F16_P_1, | |
2270 | EVEX_W_0F16_P_2, | |
2271 | EVEX_W_0F17_P_0, | |
2272 | EVEX_W_0F17_P_2, | |
2273 | EVEX_W_0F28_P_0, | |
2274 | EVEX_W_0F28_P_2, | |
2275 | EVEX_W_0F29_P_0, | |
2276 | EVEX_W_0F29_P_2, | |
2277 | EVEX_W_0F2A_P_1, | |
2278 | EVEX_W_0F2A_P_3, | |
2279 | EVEX_W_0F2B_P_0, | |
2280 | EVEX_W_0F2B_P_2, | |
2281 | EVEX_W_0F2E_P_0, | |
2282 | EVEX_W_0F2E_P_2, | |
2283 | EVEX_W_0F2F_P_0, | |
2284 | EVEX_W_0F2F_P_2, | |
2285 | EVEX_W_0F51_P_0, | |
2286 | EVEX_W_0F51_P_1, | |
2287 | EVEX_W_0F51_P_2, | |
2288 | EVEX_W_0F51_P_3, | |
90a915bf IT |
2289 | EVEX_W_0F54_P_0, |
2290 | EVEX_W_0F54_P_2, | |
2291 | EVEX_W_0F55_P_0, | |
2292 | EVEX_W_0F55_P_2, | |
2293 | EVEX_W_0F56_P_0, | |
2294 | EVEX_W_0F56_P_2, | |
2295 | EVEX_W_0F57_P_0, | |
2296 | EVEX_W_0F57_P_2, | |
43234a1e L |
2297 | EVEX_W_0F58_P_0, |
2298 | EVEX_W_0F58_P_1, | |
2299 | EVEX_W_0F58_P_2, | |
2300 | EVEX_W_0F58_P_3, | |
2301 | EVEX_W_0F59_P_0, | |
2302 | EVEX_W_0F59_P_1, | |
2303 | EVEX_W_0F59_P_2, | |
2304 | EVEX_W_0F59_P_3, | |
2305 | EVEX_W_0F5A_P_0, | |
2306 | EVEX_W_0F5A_P_1, | |
2307 | EVEX_W_0F5A_P_2, | |
2308 | EVEX_W_0F5A_P_3, | |
2309 | EVEX_W_0F5B_P_0, | |
2310 | EVEX_W_0F5B_P_1, | |
2311 | EVEX_W_0F5B_P_2, | |
2312 | EVEX_W_0F5C_P_0, | |
2313 | EVEX_W_0F5C_P_1, | |
2314 | EVEX_W_0F5C_P_2, | |
2315 | EVEX_W_0F5C_P_3, | |
2316 | EVEX_W_0F5D_P_0, | |
2317 | EVEX_W_0F5D_P_1, | |
2318 | EVEX_W_0F5D_P_2, | |
2319 | EVEX_W_0F5D_P_3, | |
2320 | EVEX_W_0F5E_P_0, | |
2321 | EVEX_W_0F5E_P_1, | |
2322 | EVEX_W_0F5E_P_2, | |
2323 | EVEX_W_0F5E_P_3, | |
2324 | EVEX_W_0F5F_P_0, | |
2325 | EVEX_W_0F5F_P_1, | |
2326 | EVEX_W_0F5F_P_2, | |
2327 | EVEX_W_0F5F_P_3, | |
2328 | EVEX_W_0F62_P_2, | |
2329 | EVEX_W_0F66_P_2, | |
2330 | EVEX_W_0F6A_P_2, | |
1ba585e8 | 2331 | EVEX_W_0F6B_P_2, |
43234a1e L |
2332 | EVEX_W_0F6C_P_2, |
2333 | EVEX_W_0F6D_P_2, | |
2334 | EVEX_W_0F6E_P_2, | |
2335 | EVEX_W_0F6F_P_1, | |
2336 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 2337 | EVEX_W_0F6F_P_3, |
43234a1e L |
2338 | EVEX_W_0F70_P_2, |
2339 | EVEX_W_0F72_R_2_P_2, | |
2340 | EVEX_W_0F72_R_6_P_2, | |
2341 | EVEX_W_0F73_R_2_P_2, | |
2342 | EVEX_W_0F73_R_6_P_2, | |
2343 | EVEX_W_0F76_P_2, | |
2344 | EVEX_W_0F78_P_0, | |
90a915bf | 2345 | EVEX_W_0F78_P_2, |
43234a1e | 2346 | EVEX_W_0F79_P_0, |
90a915bf | 2347 | EVEX_W_0F79_P_2, |
43234a1e | 2348 | EVEX_W_0F7A_P_1, |
90a915bf | 2349 | EVEX_W_0F7A_P_2, |
43234a1e L |
2350 | EVEX_W_0F7A_P_3, |
2351 | EVEX_W_0F7B_P_1, | |
90a915bf | 2352 | EVEX_W_0F7B_P_2, |
43234a1e L |
2353 | EVEX_W_0F7B_P_3, |
2354 | EVEX_W_0F7E_P_1, | |
2355 | EVEX_W_0F7E_P_2, | |
2356 | EVEX_W_0F7F_P_1, | |
2357 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 2358 | EVEX_W_0F7F_P_3, |
43234a1e L |
2359 | EVEX_W_0FC2_P_0, |
2360 | EVEX_W_0FC2_P_1, | |
2361 | EVEX_W_0FC2_P_2, | |
2362 | EVEX_W_0FC2_P_3, | |
2363 | EVEX_W_0FC6_P_0, | |
2364 | EVEX_W_0FC6_P_2, | |
2365 | EVEX_W_0FD2_P_2, | |
2366 | EVEX_W_0FD3_P_2, | |
2367 | EVEX_W_0FD4_P_2, | |
2368 | EVEX_W_0FD6_P_2, | |
2369 | EVEX_W_0FE6_P_1, | |
2370 | EVEX_W_0FE6_P_2, | |
2371 | EVEX_W_0FE6_P_3, | |
2372 | EVEX_W_0FE7_P_2, | |
2373 | EVEX_W_0FF2_P_2, | |
2374 | EVEX_W_0FF3_P_2, | |
2375 | EVEX_W_0FF4_P_2, | |
2376 | EVEX_W_0FFA_P_2, | |
2377 | EVEX_W_0FFB_P_2, | |
2378 | EVEX_W_0FFE_P_2, | |
2379 | EVEX_W_0F380C_P_2, | |
2380 | EVEX_W_0F380D_P_2, | |
1ba585e8 IT |
2381 | EVEX_W_0F3810_P_1, |
2382 | EVEX_W_0F3810_P_2, | |
43234a1e | 2383 | EVEX_W_0F3811_P_1, |
1ba585e8 | 2384 | EVEX_W_0F3811_P_2, |
43234a1e | 2385 | EVEX_W_0F3812_P_1, |
1ba585e8 | 2386 | EVEX_W_0F3812_P_2, |
43234a1e L |
2387 | EVEX_W_0F3813_P_1, |
2388 | EVEX_W_0F3813_P_2, | |
2389 | EVEX_W_0F3814_P_1, | |
2390 | EVEX_W_0F3815_P_1, | |
2391 | EVEX_W_0F3818_P_2, | |
2392 | EVEX_W_0F3819_P_2, | |
2393 | EVEX_W_0F381A_P_2, | |
2394 | EVEX_W_0F381B_P_2, | |
2395 | EVEX_W_0F381E_P_2, | |
2396 | EVEX_W_0F381F_P_2, | |
1ba585e8 | 2397 | EVEX_W_0F3820_P_1, |
43234a1e L |
2398 | EVEX_W_0F3821_P_1, |
2399 | EVEX_W_0F3822_P_1, | |
2400 | EVEX_W_0F3823_P_1, | |
2401 | EVEX_W_0F3824_P_1, | |
2402 | EVEX_W_0F3825_P_1, | |
2403 | EVEX_W_0F3825_P_2, | |
1ba585e8 IT |
2404 | EVEX_W_0F3826_P_1, |
2405 | EVEX_W_0F3826_P_2, | |
2406 | EVEX_W_0F3828_P_1, | |
43234a1e | 2407 | EVEX_W_0F3828_P_2, |
1ba585e8 | 2408 | EVEX_W_0F3829_P_1, |
43234a1e L |
2409 | EVEX_W_0F3829_P_2, |
2410 | EVEX_W_0F382A_P_1, | |
2411 | EVEX_W_0F382A_P_2, | |
1ba585e8 IT |
2412 | EVEX_W_0F382B_P_2, |
2413 | EVEX_W_0F3830_P_1, | |
43234a1e L |
2414 | EVEX_W_0F3831_P_1, |
2415 | EVEX_W_0F3832_P_1, | |
2416 | EVEX_W_0F3833_P_1, | |
2417 | EVEX_W_0F3834_P_1, | |
2418 | EVEX_W_0F3835_P_1, | |
2419 | EVEX_W_0F3835_P_2, | |
2420 | EVEX_W_0F3837_P_2, | |
90a915bf IT |
2421 | EVEX_W_0F3838_P_1, |
2422 | EVEX_W_0F3839_P_1, | |
43234a1e L |
2423 | EVEX_W_0F383A_P_1, |
2424 | EVEX_W_0F3840_P_2, | |
ee6872be | 2425 | EVEX_W_0F3854_P_2, |
620214f7 | 2426 | EVEX_W_0F3855_P_2, |
43234a1e L |
2427 | EVEX_W_0F3858_P_2, |
2428 | EVEX_W_0F3859_P_2, | |
2429 | EVEX_W_0F385A_P_2, | |
2430 | EVEX_W_0F385B_P_2, | |
53467f57 IT |
2431 | EVEX_W_0F3862_P_2, |
2432 | EVEX_W_0F3863_P_2, | |
1ba585e8 | 2433 | EVEX_W_0F3866_P_2, |
53467f57 IT |
2434 | EVEX_W_0F3870_P_2, |
2435 | EVEX_W_0F3871_P_2, | |
2436 | EVEX_W_0F3872_P_2, | |
2437 | EVEX_W_0F3873_P_2, | |
1ba585e8 IT |
2438 | EVEX_W_0F3875_P_2, |
2439 | EVEX_W_0F3878_P_2, | |
2440 | EVEX_W_0F3879_P_2, | |
2441 | EVEX_W_0F387A_P_2, | |
2442 | EVEX_W_0F387B_P_2, | |
2443 | EVEX_W_0F387D_P_2, | |
14f195c9 | 2444 | EVEX_W_0F3883_P_2, |
1ba585e8 | 2445 | EVEX_W_0F388D_P_2, |
43234a1e L |
2446 | EVEX_W_0F3891_P_2, |
2447 | EVEX_W_0F3893_P_2, | |
2448 | EVEX_W_0F38A1_P_2, | |
2449 | EVEX_W_0F38A3_P_2, | |
2450 | EVEX_W_0F38C7_R_1_P_2, | |
2451 | EVEX_W_0F38C7_R_2_P_2, | |
2452 | EVEX_W_0F38C7_R_5_P_2, | |
2453 | EVEX_W_0F38C7_R_6_P_2, | |
2454 | ||
2455 | EVEX_W_0F3A00_P_2, | |
2456 | EVEX_W_0F3A01_P_2, | |
2457 | EVEX_W_0F3A04_P_2, | |
2458 | EVEX_W_0F3A05_P_2, | |
2459 | EVEX_W_0F3A08_P_2, | |
2460 | EVEX_W_0F3A09_P_2, | |
2461 | EVEX_W_0F3A0A_P_2, | |
2462 | EVEX_W_0F3A0B_P_2, | |
90a915bf | 2463 | EVEX_W_0F3A16_P_2, |
43234a1e L |
2464 | EVEX_W_0F3A18_P_2, |
2465 | EVEX_W_0F3A19_P_2, | |
2466 | EVEX_W_0F3A1A_P_2, | |
2467 | EVEX_W_0F3A1B_P_2, | |
2468 | EVEX_W_0F3A1D_P_2, | |
2469 | EVEX_W_0F3A21_P_2, | |
90a915bf | 2470 | EVEX_W_0F3A22_P_2, |
43234a1e L |
2471 | EVEX_W_0F3A23_P_2, |
2472 | EVEX_W_0F3A38_P_2, | |
2473 | EVEX_W_0F3A39_P_2, | |
2474 | EVEX_W_0F3A3A_P_2, | |
2475 | EVEX_W_0F3A3B_P_2, | |
1ba585e8 IT |
2476 | EVEX_W_0F3A3E_P_2, |
2477 | EVEX_W_0F3A3F_P_2, | |
2478 | EVEX_W_0F3A42_P_2, | |
90a915bf IT |
2479 | EVEX_W_0F3A43_P_2, |
2480 | EVEX_W_0F3A50_P_2, | |
2481 | EVEX_W_0F3A51_P_2, | |
2482 | EVEX_W_0F3A56_P_2, | |
2483 | EVEX_W_0F3A57_P_2, | |
2484 | EVEX_W_0F3A66_P_2, | |
53467f57 IT |
2485 | EVEX_W_0F3A67_P_2, |
2486 | EVEX_W_0F3A70_P_2, | |
2487 | EVEX_W_0F3A71_P_2, | |
2488 | EVEX_W_0F3A72_P_2, | |
48521003 IT |
2489 | EVEX_W_0F3A73_P_2, |
2490 | EVEX_W_0F3ACE_P_2, | |
2491 | EVEX_W_0F3ACF_P_2 | |
9e30b8e0 L |
2492 | }; |
2493 | ||
26ca5450 | 2494 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2495 | |
2496 | struct dis386 { | |
2da11e11 | 2497 | const char *name; |
ce518a5f L |
2498 | struct |
2499 | { | |
2500 | op_rtn rtn; | |
2501 | int bytemode; | |
2502 | } op[MAX_OPERANDS]; | |
bf890a93 | 2503 | unsigned int prefix_requirement; |
252b5132 RH |
2504 | }; |
2505 | ||
2506 | /* Upper case letters in the instruction names here are macros. | |
2507 | 'A' => print 'b' if no register operands or suffix_always is true | |
2508 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2509 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2510 | size prefix |
ed7841b3 | 2511 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2512 | suffix_always is true |
252b5132 | 2513 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2514 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2515 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2516 | 'H' => print ",pt" or ",pn" branch hint |
9306ca4a | 2517 | 'I' => honor following macro letter even in Intel mode (implemented only |
98b528ac | 2518 | for some of the macro letters) |
9306ca4a | 2519 | 'J' => print 'l' |
42903f7f | 2520 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2521 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2522 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2523 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2524 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2525 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2526 | or suffix_always is true. print 'q' if rex prefix is present. |
2527 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2528 | is true | |
a35ca55a | 2529 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2530 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
a72d2af2 L |
2531 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
2532 | prefix and behave as 'P' otherwise | |
2533 | 'U' => print 'q' in 64bit mode if instruction has no operand size | |
2534 | prefix and behave as 'Q' otherwise | |
2535 | 'V' => print 'q' in 64bit mode if instruction has no operand size | |
2536 | prefix and behave as 'S' otherwise | |
a35ca55a | 2537 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2538 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
8a72226a L |
2539 | 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and |
2540 | suffix_always is true. | |
6dd5059a | 2541 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2542 | '!' => change condition from true to false or from false to true. |
98b528ac | 2543 | '%' => add 1 upper case letter to the macro. |
a72d2af2 L |
2544 | '^' => print 'w' or 'l' depending on operand size prefix or |
2545 | suffix_always is true (lcall/ljmp). | |
5db04b09 L |
2546 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
2547 | on operand size prefix. | |
07f5af7d L |
2548 | '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction |
2549 | has no operand size prefix for AMD64 ISA, behave as 'P' | |
2550 | otherwise | |
98b528ac L |
2551 | |
2552 | 2 upper case letter macros: | |
04d824a4 JB |
2553 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
2554 | operands and no broadcast. | |
2555 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
2556 | register operands and no broadcast. | |
4b06377f L |
2557 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
2558 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand | |
98b528ac | 2559 | or suffix_always is true |
4b06377f L |
2560 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2561 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2562 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2563 | "LW" => print 'd', 'q' depending on the VEX.W bit |
4b4c407a L |
2564 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2565 | an operand size prefix, or suffix_always is true. print | |
2566 | 'q' if rex prefix is present. | |
52b15da3 | 2567 | |
6439fc28 AM |
2568 | Many of the above letters print nothing in Intel mode. See "putop" |
2569 | for the details. | |
52b15da3 | 2570 | |
6439fc28 | 2571 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2572 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2573 | |
6439fc28 | 2574 | static const struct dis386 dis386[] = { |
252b5132 | 2575 | /* 00 */ |
bf890a93 IT |
2576 | { "addB", { Ebh1, Gb }, 0 }, |
2577 | { "addS", { Evh1, Gv }, 0 }, | |
2578 | { "addB", { Gb, EbS }, 0 }, | |
2579 | { "addS", { Gv, EvS }, 0 }, | |
2580 | { "addB", { AL, Ib }, 0 }, | |
2581 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2582 | { X86_64_TABLE (X86_64_06) }, |
2583 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2584 | /* 08 */ |
bf890a93 IT |
2585 | { "orB", { Ebh1, Gb }, 0 }, |
2586 | { "orS", { Evh1, Gv }, 0 }, | |
2587 | { "orB", { Gb, EbS }, 0 }, | |
2588 | { "orS", { Gv, EvS }, 0 }, | |
2589 | { "orB", { AL, Ib }, 0 }, | |
2590 | { "orS", { eAX, Iv }, 0 }, | |
4e7d34a6 | 2591 | { X86_64_TABLE (X86_64_0D) }, |
592d1631 | 2592 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2593 | /* 10 */ |
bf890a93 IT |
2594 | { "adcB", { Ebh1, Gb }, 0 }, |
2595 | { "adcS", { Evh1, Gv }, 0 }, | |
2596 | { "adcB", { Gb, EbS }, 0 }, | |
2597 | { "adcS", { Gv, EvS }, 0 }, | |
2598 | { "adcB", { AL, Ib }, 0 }, | |
2599 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2600 | { X86_64_TABLE (X86_64_16) }, |
2601 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2602 | /* 18 */ |
bf890a93 IT |
2603 | { "sbbB", { Ebh1, Gb }, 0 }, |
2604 | { "sbbS", { Evh1, Gv }, 0 }, | |
2605 | { "sbbB", { Gb, EbS }, 0 }, | |
2606 | { "sbbS", { Gv, EvS }, 0 }, | |
2607 | { "sbbB", { AL, Ib }, 0 }, | |
2608 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2609 | { X86_64_TABLE (X86_64_1E) }, |
2610 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2611 | /* 20 */ |
bf890a93 IT |
2612 | { "andB", { Ebh1, Gb }, 0 }, |
2613 | { "andS", { Evh1, Gv }, 0 }, | |
2614 | { "andB", { Gb, EbS }, 0 }, | |
2615 | { "andS", { Gv, EvS }, 0 }, | |
2616 | { "andB", { AL, Ib }, 0 }, | |
2617 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 2618 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2619 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2620 | /* 28 */ |
bf890a93 IT |
2621 | { "subB", { Ebh1, Gb }, 0 }, |
2622 | { "subS", { Evh1, Gv }, 0 }, | |
2623 | { "subB", { Gb, EbS }, 0 }, | |
2624 | { "subS", { Gv, EvS }, 0 }, | |
2625 | { "subB", { AL, Ib }, 0 }, | |
2626 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 2627 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2628 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2629 | /* 30 */ |
bf890a93 IT |
2630 | { "xorB", { Ebh1, Gb }, 0 }, |
2631 | { "xorS", { Evh1, Gv }, 0 }, | |
2632 | { "xorB", { Gb, EbS }, 0 }, | |
2633 | { "xorS", { Gv, EvS }, 0 }, | |
2634 | { "xorB", { AL, Ib }, 0 }, | |
2635 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 2636 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2637 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2638 | /* 38 */ |
bf890a93 IT |
2639 | { "cmpB", { Eb, Gb }, 0 }, |
2640 | { "cmpS", { Ev, Gv }, 0 }, | |
2641 | { "cmpB", { Gb, EbS }, 0 }, | |
2642 | { "cmpS", { Gv, EvS }, 0 }, | |
2643 | { "cmpB", { AL, Ib }, 0 }, | |
2644 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 2645 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2646 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2647 | /* 40 */ |
bf890a93 IT |
2648 | { "inc{S|}", { RMeAX }, 0 }, |
2649 | { "inc{S|}", { RMeCX }, 0 }, | |
2650 | { "inc{S|}", { RMeDX }, 0 }, | |
2651 | { "inc{S|}", { RMeBX }, 0 }, | |
2652 | { "inc{S|}", { RMeSP }, 0 }, | |
2653 | { "inc{S|}", { RMeBP }, 0 }, | |
2654 | { "inc{S|}", { RMeSI }, 0 }, | |
2655 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 2656 | /* 48 */ |
bf890a93 IT |
2657 | { "dec{S|}", { RMeAX }, 0 }, |
2658 | { "dec{S|}", { RMeCX }, 0 }, | |
2659 | { "dec{S|}", { RMeDX }, 0 }, | |
2660 | { "dec{S|}", { RMeBX }, 0 }, | |
2661 | { "dec{S|}", { RMeSP }, 0 }, | |
2662 | { "dec{S|}", { RMeBP }, 0 }, | |
2663 | { "dec{S|}", { RMeSI }, 0 }, | |
2664 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 2665 | /* 50 */ |
bf890a93 IT |
2666 | { "pushV", { RMrAX }, 0 }, |
2667 | { "pushV", { RMrCX }, 0 }, | |
2668 | { "pushV", { RMrDX }, 0 }, | |
2669 | { "pushV", { RMrBX }, 0 }, | |
2670 | { "pushV", { RMrSP }, 0 }, | |
2671 | { "pushV", { RMrBP }, 0 }, | |
2672 | { "pushV", { RMrSI }, 0 }, | |
2673 | { "pushV", { RMrDI }, 0 }, | |
252b5132 | 2674 | /* 58 */ |
bf890a93 IT |
2675 | { "popV", { RMrAX }, 0 }, |
2676 | { "popV", { RMrCX }, 0 }, | |
2677 | { "popV", { RMrDX }, 0 }, | |
2678 | { "popV", { RMrBX }, 0 }, | |
2679 | { "popV", { RMrSP }, 0 }, | |
2680 | { "popV", { RMrBP }, 0 }, | |
2681 | { "popV", { RMrSI }, 0 }, | |
2682 | { "popV", { RMrDI }, 0 }, | |
252b5132 | 2683 | /* 60 */ |
4e7d34a6 L |
2684 | { X86_64_TABLE (X86_64_60) }, |
2685 | { X86_64_TABLE (X86_64_61) }, | |
2686 | { X86_64_TABLE (X86_64_62) }, | |
2687 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2688 | { Bad_Opcode }, /* seg fs */ |
2689 | { Bad_Opcode }, /* seg gs */ | |
2690 | { Bad_Opcode }, /* op size prefix */ | |
2691 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2692 | /* 68 */ |
bf890a93 IT |
2693 | { "pushT", { sIv }, 0 }, |
2694 | { "imulS", { Gv, Ev, Iv }, 0 }, | |
2695 | { "pushT", { sIbT }, 0 }, | |
2696 | { "imulS", { Gv, Ev, sIb }, 0 }, | |
2697 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 2698 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 2699 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 2700 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2701 | /* 70 */ |
bf890a93 IT |
2702 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2703 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
2704 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
2705 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2706 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2707 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
2708 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2709 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2710 | /* 78 */ |
bf890a93 IT |
2711 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2712 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
2713 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2714 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2715 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
2716 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2717 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
2718 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2719 | /* 80 */ |
1ceb70f8 L |
2720 | { REG_TABLE (REG_80) }, |
2721 | { REG_TABLE (REG_81) }, | |
d039fef3 | 2722 | { X86_64_TABLE (X86_64_82) }, |
7148c369 | 2723 | { REG_TABLE (REG_83) }, |
bf890a93 IT |
2724 | { "testB", { Eb, Gb }, 0 }, |
2725 | { "testS", { Ev, Gv }, 0 }, | |
2726 | { "xchgB", { Ebh2, Gb }, 0 }, | |
2727 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 2728 | /* 88 */ |
bf890a93 IT |
2729 | { "movB", { Ebh3, Gb }, 0 }, |
2730 | { "movS", { Evh3, Gv }, 0 }, | |
2731 | { "movB", { Gb, EbS }, 0 }, | |
2732 | { "movS", { Gv, EvS }, 0 }, | |
2733 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 2734 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 2735 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 2736 | { REG_TABLE (REG_8F) }, |
252b5132 | 2737 | /* 90 */ |
1ceb70f8 | 2738 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
2739 | { "xchgS", { RMeCX, eAX }, 0 }, |
2740 | { "xchgS", { RMeDX, eAX }, 0 }, | |
2741 | { "xchgS", { RMeBX, eAX }, 0 }, | |
2742 | { "xchgS", { RMeSP, eAX }, 0 }, | |
2743 | { "xchgS", { RMeBP, eAX }, 0 }, | |
2744 | { "xchgS", { RMeSI, eAX }, 0 }, | |
2745 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 2746 | /* 98 */ |
bf890a93 IT |
2747 | { "cW{t|}R", { XX }, 0 }, |
2748 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2749 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2750 | { Bad_Opcode }, /* fwait */ |
bf890a93 IT |
2751 | { "pushfT", { XX }, 0 }, |
2752 | { "popfT", { XX }, 0 }, | |
2753 | { "sahf", { XX }, 0 }, | |
2754 | { "lahf", { XX }, 0 }, | |
252b5132 | 2755 | /* a0 */ |
bf890a93 IT |
2756 | { "mov%LB", { AL, Ob }, 0 }, |
2757 | { "mov%LS", { eAX, Ov }, 0 }, | |
2758 | { "mov%LB", { Ob, AL }, 0 }, | |
2759 | { "mov%LS", { Ov, eAX }, 0 }, | |
2760 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2761 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2762 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2763 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2764 | /* a8 */ |
bf890a93 IT |
2765 | { "testB", { AL, Ib }, 0 }, |
2766 | { "testS", { eAX, Iv }, 0 }, | |
2767 | { "stosB", { Ybr, AL }, 0 }, | |
2768 | { "stosS", { Yvr, eAX }, 0 }, | |
2769 | { "lodsB", { ALr, Xb }, 0 }, | |
2770 | { "lodsS", { eAXr, Xv }, 0 }, | |
2771 | { "scasB", { AL, Yb }, 0 }, | |
2772 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2773 | /* b0 */ |
bf890a93 IT |
2774 | { "movB", { RMAL, Ib }, 0 }, |
2775 | { "movB", { RMCL, Ib }, 0 }, | |
2776 | { "movB", { RMDL, Ib }, 0 }, | |
2777 | { "movB", { RMBL, Ib }, 0 }, | |
2778 | { "movB", { RMAH, Ib }, 0 }, | |
2779 | { "movB", { RMCH, Ib }, 0 }, | |
2780 | { "movB", { RMDH, Ib }, 0 }, | |
2781 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2782 | /* b8 */ |
bf890a93 IT |
2783 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2784 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2785 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2786 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2787 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2788 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2789 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2790 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2791 | /* c0 */ |
1ceb70f8 L |
2792 | { REG_TABLE (REG_C0) }, |
2793 | { REG_TABLE (REG_C1) }, | |
bf890a93 IT |
2794 | { "retT", { Iw, BND }, 0 }, |
2795 | { "retT", { BND }, 0 }, | |
4e7d34a6 L |
2796 | { X86_64_TABLE (X86_64_C4) }, |
2797 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2798 | { REG_TABLE (REG_C6) }, |
2799 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2800 | /* c8 */ |
bf890a93 IT |
2801 | { "enterT", { Iw, Ib }, 0 }, |
2802 | { "leaveT", { XX }, 0 }, | |
2803 | { "Jret{|f}P", { Iw }, 0 }, | |
2804 | { "Jret{|f}P", { XX }, 0 }, | |
2805 | { "int3", { XX }, 0 }, | |
2806 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2807 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2808 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2809 | /* d0 */ |
1ceb70f8 L |
2810 | { REG_TABLE (REG_D0) }, |
2811 | { REG_TABLE (REG_D1) }, | |
2812 | { REG_TABLE (REG_D2) }, | |
2813 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2814 | { X86_64_TABLE (X86_64_D4) }, |
2815 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2816 | { Bad_Opcode }, |
bf890a93 | 2817 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2818 | /* d8 */ |
2819 | { FLOAT }, | |
2820 | { FLOAT }, | |
2821 | { FLOAT }, | |
2822 | { FLOAT }, | |
2823 | { FLOAT }, | |
2824 | { FLOAT }, | |
2825 | { FLOAT }, | |
2826 | { FLOAT }, | |
2827 | /* e0 */ | |
bf890a93 IT |
2828 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2829 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2830 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2831 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2832 | { "inB", { AL, Ib }, 0 }, | |
2833 | { "inG", { zAX, Ib }, 0 }, | |
2834 | { "outB", { Ib, AL }, 0 }, | |
2835 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2836 | /* e8 */ |
a72d2af2 L |
2837 | { X86_64_TABLE (X86_64_E8) }, |
2838 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2839 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2840 | { "jmp", { Jb, BND }, 0 }, |
2841 | { "inB", { AL, indirDX }, 0 }, | |
2842 | { "inG", { zAX, indirDX }, 0 }, | |
2843 | { "outB", { indirDX, AL }, 0 }, | |
2844 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2845 | /* f0 */ |
592d1631 | 2846 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2847 | { "icebp", { XX }, 0 }, |
592d1631 L |
2848 | { Bad_Opcode }, /* repne */ |
2849 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2850 | { "hlt", { XX }, 0 }, |
2851 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2852 | { REG_TABLE (REG_F6) }, |
2853 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2854 | /* f8 */ |
bf890a93 IT |
2855 | { "clc", { XX }, 0 }, |
2856 | { "stc", { XX }, 0 }, | |
2857 | { "cli", { XX }, 0 }, | |
2858 | { "sti", { XX }, 0 }, | |
2859 | { "cld", { XX }, 0 }, | |
2860 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2861 | { REG_TABLE (REG_FE) }, |
2862 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2863 | }; |
2864 | ||
6439fc28 | 2865 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2866 | /* 00 */ |
1ceb70f8 L |
2867 | { REG_TABLE (REG_0F00 ) }, |
2868 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2869 | { "larS", { Gv, Ew }, 0 }, |
2870 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2871 | { Bad_Opcode }, |
bf890a93 IT |
2872 | { "syscall", { XX }, 0 }, |
2873 | { "clts", { XX }, 0 }, | |
2874 | { "sysret%LP", { XX }, 0 }, | |
252b5132 | 2875 | /* 08 */ |
bf890a93 | 2876 | { "invd", { XX }, 0 }, |
3233d7d0 | 2877 | { PREFIX_TABLE (PREFIX_0F09) }, |
592d1631 | 2878 | { Bad_Opcode }, |
bf890a93 | 2879 | { "ud2", { XX }, 0 }, |
592d1631 | 2880 | { Bad_Opcode }, |
b5b1fc4f | 2881 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2882 | { "femms", { XX }, 0 }, |
2883 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2884 | /* 10 */ |
1ceb70f8 L |
2885 | { PREFIX_TABLE (PREFIX_0F10) }, |
2886 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2887 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2888 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2889 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2890 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2891 | { PREFIX_TABLE (PREFIX_0F16) }, |
2892 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2893 | /* 18 */ |
1ceb70f8 | 2894 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2895 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2896 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2897 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
bf890a93 IT |
2898 | { "nopQ", { Ev }, 0 }, |
2899 | { "nopQ", { Ev }, 0 }, | |
603555e5 | 2900 | { PREFIX_TABLE (PREFIX_0F1E) }, |
bf890a93 | 2901 | { "nopQ", { Ev }, 0 }, |
252b5132 | 2902 | /* 20 */ |
bf890a93 IT |
2903 | { "movZ", { Rm, Cm }, 0 }, |
2904 | { "movZ", { Rm, Dm }, 0 }, | |
2905 | { "movZ", { Cm, Rm }, 0 }, | |
2906 | { "movZ", { Dm, Rm }, 0 }, | |
1ceb70f8 | 2907 | { MOD_TABLE (MOD_0F24) }, |
592d1631 | 2908 | { Bad_Opcode }, |
1ceb70f8 | 2909 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2910 | { Bad_Opcode }, |
252b5132 | 2911 | /* 28 */ |
507bd325 L |
2912 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2913 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2914 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2915 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2916 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2917 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2918 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2919 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2920 | /* 30 */ |
bf890a93 IT |
2921 | { "wrmsr", { XX }, 0 }, |
2922 | { "rdtsc", { XX }, 0 }, | |
2923 | { "rdmsr", { XX }, 0 }, | |
2924 | { "rdpmc", { XX }, 0 }, | |
2925 | { "sysenter", { XX }, 0 }, | |
2926 | { "sysexit", { XX }, 0 }, | |
592d1631 | 2927 | { Bad_Opcode }, |
bf890a93 | 2928 | { "getsec", { XX }, 0 }, |
252b5132 | 2929 | /* 38 */ |
507bd325 | 2930 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2931 | { Bad_Opcode }, |
507bd325 | 2932 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2933 | { Bad_Opcode }, |
2934 | { Bad_Opcode }, | |
2935 | { Bad_Opcode }, | |
2936 | { Bad_Opcode }, | |
2937 | { Bad_Opcode }, | |
252b5132 | 2938 | /* 40 */ |
bf890a93 IT |
2939 | { "cmovoS", { Gv, Ev }, 0 }, |
2940 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2941 | { "cmovbS", { Gv, Ev }, 0 }, | |
2942 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2943 | { "cmoveS", { Gv, Ev }, 0 }, | |
2944 | { "cmovneS", { Gv, Ev }, 0 }, | |
2945 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2946 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2947 | /* 48 */ |
bf890a93 IT |
2948 | { "cmovsS", { Gv, Ev }, 0 }, |
2949 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2950 | { "cmovpS", { Gv, Ev }, 0 }, | |
2951 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2952 | { "cmovlS", { Gv, Ev }, 0 }, | |
2953 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2954 | { "cmovleS", { Gv, Ev }, 0 }, | |
2955 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2956 | /* 50 */ |
75c135a8 | 2957 | { MOD_TABLE (MOD_0F51) }, |
1ceb70f8 L |
2958 | { PREFIX_TABLE (PREFIX_0F51) }, |
2959 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2960 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2961 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2962 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2963 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2964 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2965 | /* 58 */ |
1ceb70f8 L |
2966 | { PREFIX_TABLE (PREFIX_0F58) }, |
2967 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2968 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2969 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2970 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2971 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2972 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2973 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2974 | /* 60 */ |
1ceb70f8 L |
2975 | { PREFIX_TABLE (PREFIX_0F60) }, |
2976 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2977 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2978 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2979 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2980 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2981 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2982 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2983 | /* 68 */ |
507bd325 L |
2984 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2985 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2986 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2987 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2988 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2989 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
507bd325 | 2990 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2991 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2992 | /* 70 */ |
1ceb70f8 L |
2993 | { PREFIX_TABLE (PREFIX_0F70) }, |
2994 | { REG_TABLE (REG_0F71) }, | |
2995 | { REG_TABLE (REG_0F72) }, | |
2996 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
2997 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2998 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
2999 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
3000 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 3001 | /* 78 */ |
1ceb70f8 L |
3002 | { PREFIX_TABLE (PREFIX_0F78) }, |
3003 | { PREFIX_TABLE (PREFIX_0F79) }, | |
1f334aeb | 3004 | { Bad_Opcode }, |
592d1631 | 3005 | { Bad_Opcode }, |
1ceb70f8 L |
3006 | { PREFIX_TABLE (PREFIX_0F7C) }, |
3007 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
3008 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
3009 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 3010 | /* 80 */ |
bf890a93 IT |
3011 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
3012 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
3013 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
3014 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
3015 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
3016 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
3017 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
3018 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 3019 | /* 88 */ |
bf890a93 IT |
3020 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
3021 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
3022 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
3023 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
3024 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
3025 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
3026 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
3027 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 3028 | /* 90 */ |
bf890a93 IT |
3029 | { "seto", { Eb }, 0 }, |
3030 | { "setno", { Eb }, 0 }, | |
3031 | { "setb", { Eb }, 0 }, | |
3032 | { "setae", { Eb }, 0 }, | |
3033 | { "sete", { Eb }, 0 }, | |
3034 | { "setne", { Eb }, 0 }, | |
3035 | { "setbe", { Eb }, 0 }, | |
3036 | { "seta", { Eb }, 0 }, | |
252b5132 | 3037 | /* 98 */ |
bf890a93 IT |
3038 | { "sets", { Eb }, 0 }, |
3039 | { "setns", { Eb }, 0 }, | |
3040 | { "setp", { Eb }, 0 }, | |
3041 | { "setnp", { Eb }, 0 }, | |
3042 | { "setl", { Eb }, 0 }, | |
3043 | { "setge", { Eb }, 0 }, | |
3044 | { "setle", { Eb }, 0 }, | |
3045 | { "setg", { Eb }, 0 }, | |
252b5132 | 3046 | /* a0 */ |
bf890a93 IT |
3047 | { "pushT", { fs }, 0 }, |
3048 | { "popT", { fs }, 0 }, | |
3049 | { "cpuid", { XX }, 0 }, | |
3050 | { "btS", { Ev, Gv }, 0 }, | |
3051 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
3052 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
3053 | { REG_TABLE (REG_0FA6) }, |
3054 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 3055 | /* a8 */ |
bf890a93 IT |
3056 | { "pushT", { gs }, 0 }, |
3057 | { "popT", { gs }, 0 }, | |
3058 | { "rsm", { XX }, 0 }, | |
3059 | { "btsS", { Evh1, Gv }, 0 }, | |
3060 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
3061 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 3062 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 3063 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 3064 | /* b0 */ |
bf890a93 IT |
3065 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
3066 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 3067 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 3068 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
3069 | { MOD_TABLE (MOD_0FB4) }, |
3070 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
3071 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
3072 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 3073 | /* b8 */ |
1ceb70f8 | 3074 | { PREFIX_TABLE (PREFIX_0FB8) }, |
66f1eba0 | 3075 | { "ud1S", { Gv, Ev }, 0 }, |
1ceb70f8 | 3076 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 3077 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 3078 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 3079 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
3080 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
3081 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 3082 | /* c0 */ |
bf890a93 IT |
3083 | { "xaddB", { Ebh1, Gb }, 0 }, |
3084 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 3085 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 3086 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
3087 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
3088 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
3089 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 3090 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 3091 | /* c8 */ |
bf890a93 IT |
3092 | { "bswap", { RMeAX }, 0 }, |
3093 | { "bswap", { RMeCX }, 0 }, | |
3094 | { "bswap", { RMeDX }, 0 }, | |
3095 | { "bswap", { RMeBX }, 0 }, | |
3096 | { "bswap", { RMeSP }, 0 }, | |
3097 | { "bswap", { RMeBP }, 0 }, | |
3098 | { "bswap", { RMeSI }, 0 }, | |
3099 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 3100 | /* d0 */ |
1ceb70f8 | 3101 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
3102 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
3103 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
3104 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
3105 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
3106 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 3107 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 3108 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 3109 | /* d8 */ |
507bd325 L |
3110 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
3111 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
3112 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
3113 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
3114 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
3115 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
3116 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
3117 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 3118 | /* e0 */ |
507bd325 L |
3119 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
3120 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
3121 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
3122 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
3123 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
3124 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
3125 | { PREFIX_TABLE (PREFIX_0FE6) }, |
3126 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 3127 | /* e8 */ |
507bd325 L |
3128 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
3129 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
3130 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
3131 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
3132 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
3133 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
3134 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
3135 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 3136 | /* f0 */ |
1ceb70f8 | 3137 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
3138 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
3139 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
3140 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
3141 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
3142 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
3143 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 3144 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 3145 | /* f8 */ |
507bd325 L |
3146 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
3147 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
3148 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
3149 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
3150 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
3151 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
3152 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
66f1eba0 | 3153 | { "ud0S", { Gv, Ev }, 0 }, |
252b5132 RH |
3154 | }; |
3155 | ||
3156 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
3157 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
3158 | /* ------------------------------- */ | |
3159 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
3160 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
3161 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
3162 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
3163 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
3164 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
3165 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
3166 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
3167 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
3168 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
3169 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
3170 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
3171 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
3172 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
3173 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
3174 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
3175 | /* ------------------------------- */ | |
3176 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
3177 | }; |
3178 | ||
3179 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
3180 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
3181 | /* ------------------------------- */ | |
252b5132 | 3182 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 3183 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 3184 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 3185 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 3186 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
3187 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
3188 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 3189 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
3190 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
3191 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 3192 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
66f1eba0 | 3193 | /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ |
252b5132 | 3194 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 3195 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 3196 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
66f1eba0 | 3197 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ |
c608c12e AM |
3198 | /* ------------------------------- */ |
3199 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
3200 | }; | |
3201 | ||
252b5132 RH |
3202 | static char obuf[100]; |
3203 | static char *obufp; | |
ea397f5b | 3204 | static char *mnemonicendp; |
252b5132 RH |
3205 | static char scratchbuf[100]; |
3206 | static unsigned char *start_codep; | |
3207 | static unsigned char *insn_codep; | |
3208 | static unsigned char *codep; | |
285ca992 | 3209 | static unsigned char *end_codep; |
f16cd0d5 L |
3210 | static int last_lock_prefix; |
3211 | static int last_repz_prefix; | |
3212 | static int last_repnz_prefix; | |
3213 | static int last_data_prefix; | |
3214 | static int last_addr_prefix; | |
3215 | static int last_rex_prefix; | |
3216 | static int last_seg_prefix; | |
d9949a36 | 3217 | static int fwait_prefix; |
285ca992 L |
3218 | /* The active segment register prefix. */ |
3219 | static int active_seg_prefix; | |
f16cd0d5 L |
3220 | #define MAX_CODE_LENGTH 15 |
3221 | /* We can up to 14 prefixes since the maximum instruction length is | |
3222 | 15bytes. */ | |
3223 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 3224 | static disassemble_info *the_info; |
7967e09e L |
3225 | static struct |
3226 | { | |
3227 | int mod; | |
7967e09e | 3228 | int reg; |
484c222e | 3229 | int rm; |
7967e09e L |
3230 | } |
3231 | modrm; | |
4bba6815 | 3232 | static unsigned char need_modrm; |
dfc8cf43 L |
3233 | static struct |
3234 | { | |
3235 | int scale; | |
3236 | int index; | |
3237 | int base; | |
3238 | } | |
3239 | sib; | |
c0f3af97 L |
3240 | static struct |
3241 | { | |
3242 | int register_specifier; | |
3243 | int length; | |
3244 | int prefix; | |
3245 | int w; | |
43234a1e L |
3246 | int evex; |
3247 | int r; | |
3248 | int v; | |
3249 | int mask_register_specifier; | |
3250 | int zeroing; | |
3251 | int ll; | |
3252 | int b; | |
c0f3af97 L |
3253 | } |
3254 | vex; | |
3255 | static unsigned char need_vex; | |
3256 | static unsigned char need_vex_reg; | |
dae39acc | 3257 | static unsigned char vex_w_done; |
252b5132 | 3258 | |
ea397f5b L |
3259 | struct op |
3260 | { | |
3261 | const char *name; | |
3262 | unsigned int len; | |
3263 | }; | |
3264 | ||
4bba6815 AM |
3265 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
3266 | values are stale. Hitting this abort likely indicates that you | |
3267 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
3268 | #define MODRM_CHECK if (!need_modrm) abort () | |
3269 | ||
d708bcba AM |
3270 | static const char **names64; |
3271 | static const char **names32; | |
3272 | static const char **names16; | |
3273 | static const char **names8; | |
3274 | static const char **names8rex; | |
3275 | static const char **names_seg; | |
db51cc60 L |
3276 | static const char *index64; |
3277 | static const char *index32; | |
d708bcba | 3278 | static const char **index16; |
7e8b059b | 3279 | static const char **names_bnd; |
d708bcba AM |
3280 | |
3281 | static const char *intel_names64[] = { | |
3282 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
3283 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
3284 | }; | |
3285 | static const char *intel_names32[] = { | |
3286 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
3287 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
3288 | }; | |
3289 | static const char *intel_names16[] = { | |
3290 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
3291 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
3292 | }; | |
3293 | static const char *intel_names8[] = { | |
3294 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
3295 | }; | |
3296 | static const char *intel_names8rex[] = { | |
3297 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
3298 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
3299 | }; | |
3300 | static const char *intel_names_seg[] = { | |
3301 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
3302 | }; | |
db51cc60 L |
3303 | static const char *intel_index64 = "riz"; |
3304 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
3305 | static const char *intel_index16[] = { |
3306 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
3307 | }; | |
3308 | ||
3309 | static const char *att_names64[] = { | |
3310 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
3311 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
3312 | }; | |
d708bcba AM |
3313 | static const char *att_names32[] = { |
3314 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 3315 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 3316 | }; |
d708bcba AM |
3317 | static const char *att_names16[] = { |
3318 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 3319 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 3320 | }; |
d708bcba AM |
3321 | static const char *att_names8[] = { |
3322 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 3323 | }; |
d708bcba AM |
3324 | static const char *att_names8rex[] = { |
3325 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
3326 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
3327 | }; | |
d708bcba AM |
3328 | static const char *att_names_seg[] = { |
3329 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 3330 | }; |
db51cc60 L |
3331 | static const char *att_index64 = "%riz"; |
3332 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
3333 | static const char *att_index16[] = { |
3334 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
3335 | }; |
3336 | ||
b9733481 L |
3337 | static const char **names_mm; |
3338 | static const char *intel_names_mm[] = { | |
3339 | "mm0", "mm1", "mm2", "mm3", | |
3340 | "mm4", "mm5", "mm6", "mm7" | |
3341 | }; | |
3342 | static const char *att_names_mm[] = { | |
3343 | "%mm0", "%mm1", "%mm2", "%mm3", | |
3344 | "%mm4", "%mm5", "%mm6", "%mm7" | |
3345 | }; | |
3346 | ||
7e8b059b L |
3347 | static const char *intel_names_bnd[] = { |
3348 | "bnd0", "bnd1", "bnd2", "bnd3" | |
3349 | }; | |
3350 | ||
3351 | static const char *att_names_bnd[] = { | |
3352 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
3353 | }; | |
3354 | ||
b9733481 L |
3355 | static const char **names_xmm; |
3356 | static const char *intel_names_xmm[] = { | |
3357 | "xmm0", "xmm1", "xmm2", "xmm3", | |
3358 | "xmm4", "xmm5", "xmm6", "xmm7", | |
3359 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
3360 | "xmm12", "xmm13", "xmm14", "xmm15", |
3361 | "xmm16", "xmm17", "xmm18", "xmm19", | |
3362 | "xmm20", "xmm21", "xmm22", "xmm23", | |
3363 | "xmm24", "xmm25", "xmm26", "xmm27", | |
3364 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
3365 | }; |
3366 | static const char *att_names_xmm[] = { | |
3367 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3368 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3369 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3370 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3371 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3372 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3373 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3374 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3375 | }; |
3376 | ||
3377 | static const char **names_ymm; | |
3378 | static const char *intel_names_ymm[] = { | |
3379 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3380 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3381 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3382 | "ymm12", "ymm13", "ymm14", "ymm15", |
3383 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3384 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3385 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3386 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3387 | }; |
3388 | static const char *att_names_ymm[] = { | |
3389 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3390 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3391 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3392 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3393 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3394 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3395 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3396 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3397 | }; | |
3398 | ||
3399 | static const char **names_zmm; | |
3400 | static const char *intel_names_zmm[] = { | |
3401 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3402 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3403 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3404 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3405 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3406 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3407 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3408 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3409 | }; | |
3410 | static const char *att_names_zmm[] = { | |
3411 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3412 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3413 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3414 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3415 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3416 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3417 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3418 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3419 | }; | |
3420 | ||
3421 | static const char **names_mask; | |
3422 | static const char *intel_names_mask[] = { | |
3423 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3424 | }; | |
3425 | static const char *att_names_mask[] = { | |
3426 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3427 | }; | |
3428 | ||
3429 | static const char *names_rounding[] = | |
3430 | { | |
3431 | "{rn-sae}", | |
3432 | "{rd-sae}", | |
3433 | "{ru-sae}", | |
3434 | "{rz-sae}" | |
b9733481 L |
3435 | }; |
3436 | ||
1ceb70f8 L |
3437 | static const struct dis386 reg_table[][8] = { |
3438 | /* REG_80 */ | |
252b5132 | 3439 | { |
bf890a93 IT |
3440 | { "addA", { Ebh1, Ib }, 0 }, |
3441 | { "orA", { Ebh1, Ib }, 0 }, | |
3442 | { "adcA", { Ebh1, Ib }, 0 }, | |
3443 | { "sbbA", { Ebh1, Ib }, 0 }, | |
3444 | { "andA", { Ebh1, Ib }, 0 }, | |
3445 | { "subA", { Ebh1, Ib }, 0 }, | |
3446 | { "xorA", { Ebh1, Ib }, 0 }, | |
3447 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 3448 | }, |
1ceb70f8 | 3449 | /* REG_81 */ |
252b5132 | 3450 | { |
bf890a93 IT |
3451 | { "addQ", { Evh1, Iv }, 0 }, |
3452 | { "orQ", { Evh1, Iv }, 0 }, | |
3453 | { "adcQ", { Evh1, Iv }, 0 }, | |
3454 | { "sbbQ", { Evh1, Iv }, 0 }, | |
3455 | { "andQ", { Evh1, Iv }, 0 }, | |
3456 | { "subQ", { Evh1, Iv }, 0 }, | |
3457 | { "xorQ", { Evh1, Iv }, 0 }, | |
3458 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 3459 | }, |
7148c369 | 3460 | /* REG_83 */ |
252b5132 | 3461 | { |
bf890a93 IT |
3462 | { "addQ", { Evh1, sIb }, 0 }, |
3463 | { "orQ", { Evh1, sIb }, 0 }, | |
3464 | { "adcQ", { Evh1, sIb }, 0 }, | |
3465 | { "sbbQ", { Evh1, sIb }, 0 }, | |
3466 | { "andQ", { Evh1, sIb }, 0 }, | |
3467 | { "subQ", { Evh1, sIb }, 0 }, | |
3468 | { "xorQ", { Evh1, sIb }, 0 }, | |
3469 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 3470 | }, |
1ceb70f8 | 3471 | /* REG_8F */ |
4e7d34a6 | 3472 | { |
bf890a93 | 3473 | { "popU", { stackEv }, 0 }, |
c48244a5 | 3474 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3475 | { Bad_Opcode }, |
3476 | { Bad_Opcode }, | |
3477 | { Bad_Opcode }, | |
f88c9eb0 | 3478 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3479 | }, |
1ceb70f8 | 3480 | /* REG_C0 */ |
252b5132 | 3481 | { |
bf890a93 IT |
3482 | { "rolA", { Eb, Ib }, 0 }, |
3483 | { "rorA", { Eb, Ib }, 0 }, | |
3484 | { "rclA", { Eb, Ib }, 0 }, | |
3485 | { "rcrA", { Eb, Ib }, 0 }, | |
3486 | { "shlA", { Eb, Ib }, 0 }, | |
3487 | { "shrA", { Eb, Ib }, 0 }, | |
e4bdd679 | 3488 | { "shlA", { Eb, Ib }, 0 }, |
bf890a93 | 3489 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 3490 | }, |
1ceb70f8 | 3491 | /* REG_C1 */ |
252b5132 | 3492 | { |
bf890a93 IT |
3493 | { "rolQ", { Ev, Ib }, 0 }, |
3494 | { "rorQ", { Ev, Ib }, 0 }, | |
3495 | { "rclQ", { Ev, Ib }, 0 }, | |
3496 | { "rcrQ", { Ev, Ib }, 0 }, | |
3497 | { "shlQ", { Ev, Ib }, 0 }, | |
3498 | { "shrQ", { Ev, Ib }, 0 }, | |
e4bdd679 | 3499 | { "shlQ", { Ev, Ib }, 0 }, |
bf890a93 | 3500 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 3501 | }, |
1ceb70f8 | 3502 | /* REG_C6 */ |
4e7d34a6 | 3503 | { |
bf890a93 | 3504 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
3505 | { Bad_Opcode }, |
3506 | { Bad_Opcode }, | |
3507 | { Bad_Opcode }, | |
3508 | { Bad_Opcode }, | |
3509 | { Bad_Opcode }, | |
3510 | { Bad_Opcode }, | |
3511 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3512 | }, |
1ceb70f8 | 3513 | /* REG_C7 */ |
4e7d34a6 | 3514 | { |
bf890a93 | 3515 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
3516 | { Bad_Opcode }, |
3517 | { Bad_Opcode }, | |
3518 | { Bad_Opcode }, | |
3519 | { Bad_Opcode }, | |
3520 | { Bad_Opcode }, | |
3521 | { Bad_Opcode }, | |
3522 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3523 | }, |
1ceb70f8 | 3524 | /* REG_D0 */ |
252b5132 | 3525 | { |
bf890a93 IT |
3526 | { "rolA", { Eb, I1 }, 0 }, |
3527 | { "rorA", { Eb, I1 }, 0 }, | |
3528 | { "rclA", { Eb, I1 }, 0 }, | |
3529 | { "rcrA", { Eb, I1 }, 0 }, | |
3530 | { "shlA", { Eb, I1 }, 0 }, | |
3531 | { "shrA", { Eb, I1 }, 0 }, | |
e4bdd679 | 3532 | { "shlA", { Eb, I1 }, 0 }, |
bf890a93 | 3533 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 3534 | }, |
1ceb70f8 | 3535 | /* REG_D1 */ |
252b5132 | 3536 | { |
bf890a93 IT |
3537 | { "rolQ", { Ev, I1 }, 0 }, |
3538 | { "rorQ", { Ev, I1 }, 0 }, | |
3539 | { "rclQ", { Ev, I1 }, 0 }, | |
3540 | { "rcrQ", { Ev, I1 }, 0 }, | |
3541 | { "shlQ", { Ev, I1 }, 0 }, | |
3542 | { "shrQ", { Ev, I1 }, 0 }, | |
e4bdd679 | 3543 | { "shlQ", { Ev, I1 }, 0 }, |
bf890a93 | 3544 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 3545 | }, |
1ceb70f8 | 3546 | /* REG_D2 */ |
252b5132 | 3547 | { |
bf890a93 IT |
3548 | { "rolA", { Eb, CL }, 0 }, |
3549 | { "rorA", { Eb, CL }, 0 }, | |
3550 | { "rclA", { Eb, CL }, 0 }, | |
3551 | { "rcrA", { Eb, CL }, 0 }, | |
3552 | { "shlA", { Eb, CL }, 0 }, | |
3553 | { "shrA", { Eb, CL }, 0 }, | |
e4bdd679 | 3554 | { "shlA", { Eb, CL }, 0 }, |
bf890a93 | 3555 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 3556 | }, |
1ceb70f8 | 3557 | /* REG_D3 */ |
252b5132 | 3558 | { |
bf890a93 IT |
3559 | { "rolQ", { Ev, CL }, 0 }, |
3560 | { "rorQ", { Ev, CL }, 0 }, | |
3561 | { "rclQ", { Ev, CL }, 0 }, | |
3562 | { "rcrQ", { Ev, CL }, 0 }, | |
3563 | { "shlQ", { Ev, CL }, 0 }, | |
3564 | { "shrQ", { Ev, CL }, 0 }, | |
e4bdd679 | 3565 | { "shlQ", { Ev, CL }, 0 }, |
bf890a93 | 3566 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 3567 | }, |
1ceb70f8 | 3568 | /* REG_F6 */ |
252b5132 | 3569 | { |
bf890a93 | 3570 | { "testA", { Eb, Ib }, 0 }, |
7db2c588 | 3571 | { "testA", { Eb, Ib }, 0 }, |
bf890a93 IT |
3572 | { "notA", { Ebh1 }, 0 }, |
3573 | { "negA", { Ebh1 }, 0 }, | |
3574 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
3575 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
3576 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
3577 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 3578 | }, |
1ceb70f8 | 3579 | /* REG_F7 */ |
252b5132 | 3580 | { |
bf890a93 | 3581 | { "testQ", { Ev, Iv }, 0 }, |
7db2c588 | 3582 | { "testQ", { Ev, Iv }, 0 }, |
bf890a93 IT |
3583 | { "notQ", { Evh1 }, 0 }, |
3584 | { "negQ", { Evh1 }, 0 }, | |
3585 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
3586 | { "imulQ", { Ev }, 0 }, | |
3587 | { "divQ", { Ev }, 0 }, | |
3588 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 3589 | }, |
1ceb70f8 | 3590 | /* REG_FE */ |
252b5132 | 3591 | { |
bf890a93 IT |
3592 | { "incA", { Ebh1 }, 0 }, |
3593 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 3594 | }, |
1ceb70f8 | 3595 | /* REG_FF */ |
252b5132 | 3596 | { |
bf890a93 IT |
3597 | { "incQ", { Evh1 }, 0 }, |
3598 | { "decQ", { Evh1 }, 0 }, | |
9fef80d6 | 3599 | { "call{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3600 | { MOD_TABLE (MOD_FF_REG_3) }, |
9fef80d6 | 3601 | { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3602 | { MOD_TABLE (MOD_FF_REG_5) }, |
bf890a93 | 3603 | { "pushU", { stackEv }, 0 }, |
592d1631 | 3604 | { Bad_Opcode }, |
252b5132 | 3605 | }, |
1ceb70f8 | 3606 | /* REG_0F00 */ |
252b5132 | 3607 | { |
bf890a93 IT |
3608 | { "sldtD", { Sv }, 0 }, |
3609 | { "strD", { Sv }, 0 }, | |
3610 | { "lldt", { Ew }, 0 }, | |
3611 | { "ltr", { Ew }, 0 }, | |
3612 | { "verr", { Ew }, 0 }, | |
3613 | { "verw", { Ew }, 0 }, | |
592d1631 L |
3614 | { Bad_Opcode }, |
3615 | { Bad_Opcode }, | |
252b5132 | 3616 | }, |
1ceb70f8 | 3617 | /* REG_0F01 */ |
252b5132 | 3618 | { |
1ceb70f8 L |
3619 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3620 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3621 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3622 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 3623 | { "smswD", { Sv }, 0 }, |
8eab4136 | 3624 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 3625 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 3626 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3627 | }, |
b5b1fc4f | 3628 | /* REG_0F0D */ |
252b5132 | 3629 | { |
bf890a93 IT |
3630 | { "prefetch", { Mb }, 0 }, |
3631 | { "prefetchw", { Mb }, 0 }, | |
3632 | { "prefetchwt1", { Mb }, 0 }, | |
3633 | { "prefetch", { Mb }, 0 }, | |
3634 | { "prefetch", { Mb }, 0 }, | |
3635 | { "prefetch", { Mb }, 0 }, | |
3636 | { "prefetch", { Mb }, 0 }, | |
3637 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 3638 | }, |
1ceb70f8 | 3639 | /* REG_0F18 */ |
252b5132 | 3640 | { |
1ceb70f8 L |
3641 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3642 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3643 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3644 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3645 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3646 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3647 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3648 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3649 | }, |
603555e5 L |
3650 | /* REG_0F1E_MOD_3 */ |
3651 | { | |
3652 | { "nopQ", { Ev }, 0 }, | |
3653 | { "rdsspK", { Rdq }, PREFIX_OPCODE }, | |
3654 | { "nopQ", { Ev }, 0 }, | |
3655 | { "nopQ", { Ev }, 0 }, | |
3656 | { "nopQ", { Ev }, 0 }, | |
3657 | { "nopQ", { Ev }, 0 }, | |
3658 | { "nopQ", { Ev }, 0 }, | |
3659 | { RM_TABLE (RM_0F1E_MOD_3_REG_7) }, | |
3660 | }, | |
1ceb70f8 | 3661 | /* REG_0F71 */ |
a6bd098c | 3662 | { |
592d1631 L |
3663 | { Bad_Opcode }, |
3664 | { Bad_Opcode }, | |
1ceb70f8 | 3665 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3666 | { Bad_Opcode }, |
1ceb70f8 | 3667 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3668 | { Bad_Opcode }, |
1ceb70f8 | 3669 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3670 | }, |
1ceb70f8 | 3671 | /* REG_0F72 */ |
a6bd098c | 3672 | { |
592d1631 L |
3673 | { Bad_Opcode }, |
3674 | { Bad_Opcode }, | |
1ceb70f8 | 3675 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3676 | { Bad_Opcode }, |
1ceb70f8 | 3677 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3678 | { Bad_Opcode }, |
1ceb70f8 | 3679 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3680 | }, |
1ceb70f8 | 3681 | /* REG_0F73 */ |
252b5132 | 3682 | { |
592d1631 L |
3683 | { Bad_Opcode }, |
3684 | { Bad_Opcode }, | |
1ceb70f8 L |
3685 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3686 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3687 | { Bad_Opcode }, |
3688 | { Bad_Opcode }, | |
1ceb70f8 L |
3689 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3690 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3691 | }, |
1ceb70f8 | 3692 | /* REG_0FA6 */ |
252b5132 | 3693 | { |
bf890a93 IT |
3694 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3695 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
3696 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3697 | }, |
1ceb70f8 | 3698 | /* REG_0FA7 */ |
4e7d34a6 | 3699 | { |
bf890a93 IT |
3700 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3701 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
3702 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
3703 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
3704 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
3705 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3706 | }, |
1ceb70f8 | 3707 | /* REG_0FAE */ |
4e7d34a6 | 3708 | { |
1ceb70f8 L |
3709 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3710 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3711 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3712 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3713 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3714 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3715 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3716 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3717 | }, |
1ceb70f8 | 3718 | /* REG_0FBA */ |
252b5132 | 3719 | { |
592d1631 L |
3720 | { Bad_Opcode }, |
3721 | { Bad_Opcode }, | |
3722 | { Bad_Opcode }, | |
3723 | { Bad_Opcode }, | |
bf890a93 IT |
3724 | { "btQ", { Ev, Ib }, 0 }, |
3725 | { "btsQ", { Evh1, Ib }, 0 }, | |
3726 | { "btrQ", { Evh1, Ib }, 0 }, | |
3727 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3728 | }, |
1ceb70f8 | 3729 | /* REG_0FC7 */ |
c608c12e | 3730 | { |
592d1631 | 3731 | { Bad_Opcode }, |
bf890a93 | 3732 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3733 | { Bad_Opcode }, |
963f3586 IT |
3734 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3735 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3736 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3737 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3738 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3739 | }, |
592a252b | 3740 | /* REG_VEX_0F71 */ |
c0f3af97 | 3741 | { |
592d1631 L |
3742 | { Bad_Opcode }, |
3743 | { Bad_Opcode }, | |
592a252b | 3744 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3745 | { Bad_Opcode }, |
592a252b | 3746 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3747 | { Bad_Opcode }, |
592a252b | 3748 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3749 | }, |
592a252b | 3750 | /* REG_VEX_0F72 */ |
c0f3af97 | 3751 | { |
592d1631 L |
3752 | { Bad_Opcode }, |
3753 | { Bad_Opcode }, | |
592a252b | 3754 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3755 | { Bad_Opcode }, |
592a252b | 3756 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3757 | { Bad_Opcode }, |
592a252b | 3758 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3759 | }, |
592a252b | 3760 | /* REG_VEX_0F73 */ |
c0f3af97 | 3761 | { |
592d1631 L |
3762 | { Bad_Opcode }, |
3763 | { Bad_Opcode }, | |
592a252b L |
3764 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3765 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3766 | { Bad_Opcode }, |
3767 | { Bad_Opcode }, | |
592a252b L |
3768 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3769 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3770 | }, |
592a252b | 3771 | /* REG_VEX_0FAE */ |
c0f3af97 | 3772 | { |
592d1631 L |
3773 | { Bad_Opcode }, |
3774 | { Bad_Opcode }, | |
592a252b L |
3775 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3776 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3777 | }, |
f12dc422 L |
3778 | /* REG_VEX_0F38F3 */ |
3779 | { | |
3780 | { Bad_Opcode }, | |
3781 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3782 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3783 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3784 | }, | |
f88c9eb0 SP |
3785 | /* REG_XOP_LWPCB */ |
3786 | { | |
bf890a93 IT |
3787 | { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3788 | { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, | |
f88c9eb0 SP |
3789 | }, |
3790 | /* REG_XOP_LWP */ | |
3791 | { | |
bf890a93 IT |
3792 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, |
3793 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, | |
f88c9eb0 | 3794 | }, |
2a2a0f38 QN |
3795 | /* REG_XOP_TBM_01 */ |
3796 | { | |
3797 | { Bad_Opcode }, | |
bf890a93 IT |
3798 | { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3799 | { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3800 | { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3801 | { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3802 | { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3803 | { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3804 | { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
2a2a0f38 QN |
3805 | }, |
3806 | /* REG_XOP_TBM_02 */ | |
3807 | { | |
3808 | { Bad_Opcode }, | |
bf890a93 | 3809 | { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, |
2a2a0f38 QN |
3810 | { Bad_Opcode }, |
3811 | { Bad_Opcode }, | |
3812 | { Bad_Opcode }, | |
3813 | { Bad_Opcode }, | |
bf890a93 | 3814 | { "blci", { { OP_LWP_E, 0 }, Ev }, 0 }, |
2a2a0f38 | 3815 | }, |
43234a1e L |
3816 | #define NEED_REG_TABLE |
3817 | #include "i386-dis-evex.h" | |
3818 | #undef NEED_REG_TABLE | |
4e7d34a6 L |
3819 | }; |
3820 | ||
1ceb70f8 L |
3821 | static const struct dis386 prefix_table[][4] = { |
3822 | /* PREFIX_90 */ | |
252b5132 | 3823 | { |
bf890a93 IT |
3824 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3825 | { "pause", { XX }, 0 }, | |
3826 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3827 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3828 | }, |
4e7d34a6 | 3829 | |
603555e5 L |
3830 | /* PREFIX_MOD_0_0F01_REG_5 */ |
3831 | { | |
3832 | { Bad_Opcode }, | |
3833 | { "rstorssp", { Mq }, PREFIX_OPCODE }, | |
3834 | }, | |
3835 | ||
2234eee6 | 3836 | /* PREFIX_MOD_3_0F01_REG_5_RM_0 */ |
603555e5 L |
3837 | { |
3838 | { Bad_Opcode }, | |
2234eee6 | 3839 | { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3840 | }, |
3841 | ||
3842 | /* PREFIX_MOD_3_0F01_REG_5_RM_2 */ | |
3843 | { | |
3844 | { Bad_Opcode }, | |
c2f76402 | 3845 | { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3846 | }, |
3847 | ||
3233d7d0 IT |
3848 | /* PREFIX_0F09 */ |
3849 | { | |
3850 | { "wbinvd", { XX }, 0 }, | |
3851 | { "wbnoinvd", { XX }, 0 }, | |
3852 | }, | |
3853 | ||
1ceb70f8 | 3854 | /* PREFIX_0F10 */ |
cc0ec051 | 3855 | { |
507bd325 L |
3856 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3857 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3858 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3859 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3860 | }, |
4e7d34a6 | 3861 | |
1ceb70f8 | 3862 | /* PREFIX_0F11 */ |
30d1c836 | 3863 | { |
507bd325 L |
3864 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3865 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3866 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3867 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3868 | }, |
252b5132 | 3869 | |
1ceb70f8 | 3870 | /* PREFIX_0F12 */ |
c608c12e | 3871 | { |
1ceb70f8 | 3872 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 L |
3873 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
3874 | { "movlpd", { XM, EXq }, PREFIX_OPCODE }, | |
3875 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3876 | }, |
4e7d34a6 | 3877 | |
1ceb70f8 | 3878 | /* PREFIX_0F16 */ |
c608c12e | 3879 | { |
1ceb70f8 | 3880 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 L |
3881 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
3882 | { "movhpd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3883 | }, |
4e7d34a6 | 3884 | |
7e8b059b L |
3885 | /* PREFIX_0F1A */ |
3886 | { | |
3887 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3888 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3889 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3890 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3891 | }, |
3892 | ||
3893 | /* PREFIX_0F1B */ | |
3894 | { | |
3895 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3896 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
9f79e886 | 3897 | { "bndmov", { EbndS, Gbnd }, 0 }, |
bf890a93 | 3898 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
7e8b059b L |
3899 | }, |
3900 | ||
603555e5 L |
3901 | /* PREFIX_0F1E */ |
3902 | { | |
3903 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3904 | { MOD_TABLE (MOD_0F1E_PREFIX_1) }, | |
3905 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3906 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3907 | }, | |
3908 | ||
1ceb70f8 | 3909 | /* PREFIX_0F2A */ |
c608c12e | 3910 | { |
507bd325 L |
3911 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
3912 | { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE }, | |
3913 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, | |
bf890a93 | 3914 | { "cvtsi2sd%LQ", { XM, Ev }, 0 }, |
c608c12e | 3915 | }, |
4e7d34a6 | 3916 | |
1ceb70f8 | 3917 | /* PREFIX_0F2B */ |
c608c12e | 3918 | { |
75c135a8 L |
3919 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3920 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3921 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3922 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3923 | }, |
4e7d34a6 | 3924 | |
1ceb70f8 | 3925 | /* PREFIX_0F2C */ |
c608c12e | 3926 | { |
507bd325 L |
3927 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
3928 | { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE }, | |
3929 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, | |
3930 | { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3931 | }, |
4e7d34a6 | 3932 | |
1ceb70f8 | 3933 | /* PREFIX_0F2D */ |
c608c12e | 3934 | { |
507bd325 L |
3935 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
3936 | { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE }, | |
3937 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, | |
3938 | { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3939 | }, |
4e7d34a6 | 3940 | |
1ceb70f8 | 3941 | /* PREFIX_0F2E */ |
c608c12e | 3942 | { |
bf890a93 | 3943 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3944 | { Bad_Opcode }, |
bf890a93 | 3945 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3946 | }, |
4e7d34a6 | 3947 | |
1ceb70f8 | 3948 | /* PREFIX_0F2F */ |
c608c12e | 3949 | { |
bf890a93 | 3950 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3951 | { Bad_Opcode }, |
bf890a93 | 3952 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3953 | }, |
4e7d34a6 | 3954 | |
1ceb70f8 | 3955 | /* PREFIX_0F51 */ |
c608c12e | 3956 | { |
507bd325 L |
3957 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3958 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3959 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3960 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3961 | }, |
4e7d34a6 | 3962 | |
1ceb70f8 | 3963 | /* PREFIX_0F52 */ |
c608c12e | 3964 | { |
507bd325 L |
3965 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3966 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3967 | }, |
4e7d34a6 | 3968 | |
1ceb70f8 | 3969 | /* PREFIX_0F53 */ |
c608c12e | 3970 | { |
507bd325 L |
3971 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3972 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3973 | }, |
4e7d34a6 | 3974 | |
1ceb70f8 | 3975 | /* PREFIX_0F58 */ |
c608c12e | 3976 | { |
507bd325 L |
3977 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3978 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
3979 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
3980 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3981 | }, |
4e7d34a6 | 3982 | |
1ceb70f8 | 3983 | /* PREFIX_0F59 */ |
c608c12e | 3984 | { |
507bd325 L |
3985 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3986 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
3987 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
3988 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3989 | }, |
4e7d34a6 | 3990 | |
1ceb70f8 | 3991 | /* PREFIX_0F5A */ |
041bd2e0 | 3992 | { |
507bd325 L |
3993 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3994 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
3995 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
3996 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3997 | }, |
4e7d34a6 | 3998 | |
1ceb70f8 | 3999 | /* PREFIX_0F5B */ |
041bd2e0 | 4000 | { |
507bd325 L |
4001 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
4002 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
4003 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 4004 | }, |
4e7d34a6 | 4005 | |
1ceb70f8 | 4006 | /* PREFIX_0F5C */ |
041bd2e0 | 4007 | { |
507bd325 L |
4008 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
4009 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
4010 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
4011 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 4012 | }, |
4e7d34a6 | 4013 | |
1ceb70f8 | 4014 | /* PREFIX_0F5D */ |
041bd2e0 | 4015 | { |
507bd325 L |
4016 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
4017 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
4018 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
4019 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 4020 | }, |
4e7d34a6 | 4021 | |
1ceb70f8 | 4022 | /* PREFIX_0F5E */ |
041bd2e0 | 4023 | { |
507bd325 L |
4024 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
4025 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
4026 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
4027 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 4028 | }, |
4e7d34a6 | 4029 | |
1ceb70f8 | 4030 | /* PREFIX_0F5F */ |
041bd2e0 | 4031 | { |
507bd325 L |
4032 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
4033 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
4034 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
4035 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 4036 | }, |
4e7d34a6 | 4037 | |
1ceb70f8 | 4038 | /* PREFIX_0F60 */ |
041bd2e0 | 4039 | { |
507bd325 | 4040 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 4041 | { Bad_Opcode }, |
507bd325 | 4042 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 4043 | }, |
4e7d34a6 | 4044 | |
1ceb70f8 | 4045 | /* PREFIX_0F61 */ |
041bd2e0 | 4046 | { |
507bd325 | 4047 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 4048 | { Bad_Opcode }, |
507bd325 | 4049 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 4050 | }, |
4e7d34a6 | 4051 | |
1ceb70f8 | 4052 | /* PREFIX_0F62 */ |
041bd2e0 | 4053 | { |
507bd325 | 4054 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 4055 | { Bad_Opcode }, |
507bd325 | 4056 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 4057 | }, |
4e7d34a6 | 4058 | |
1ceb70f8 | 4059 | /* PREFIX_0F6C */ |
041bd2e0 | 4060 | { |
592d1631 L |
4061 | { Bad_Opcode }, |
4062 | { Bad_Opcode }, | |
507bd325 | 4063 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
0f17484f | 4064 | }, |
4e7d34a6 | 4065 | |
1ceb70f8 | 4066 | /* PREFIX_0F6D */ |
0f17484f | 4067 | { |
592d1631 L |
4068 | { Bad_Opcode }, |
4069 | { Bad_Opcode }, | |
507bd325 | 4070 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
041bd2e0 | 4071 | }, |
4e7d34a6 | 4072 | |
1ceb70f8 | 4073 | /* PREFIX_0F6F */ |
ca164297 | 4074 | { |
507bd325 L |
4075 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
4076 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
4077 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 4078 | }, |
4e7d34a6 | 4079 | |
1ceb70f8 | 4080 | /* PREFIX_0F70 */ |
4e7d34a6 | 4081 | { |
507bd325 L |
4082 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
4083 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4084 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
4085 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4086 | }, |
4087 | ||
92fddf8e L |
4088 | /* PREFIX_0F73_REG_3 */ |
4089 | { | |
592d1631 L |
4090 | { Bad_Opcode }, |
4091 | { Bad_Opcode }, | |
bf890a93 | 4092 | { "psrldq", { XS, Ib }, 0 }, |
92fddf8e L |
4093 | }, |
4094 | ||
4095 | /* PREFIX_0F73_REG_7 */ | |
4096 | { | |
592d1631 L |
4097 | { Bad_Opcode }, |
4098 | { Bad_Opcode }, | |
bf890a93 | 4099 | { "pslldq", { XS, Ib }, 0 }, |
92fddf8e L |
4100 | }, |
4101 | ||
1ceb70f8 | 4102 | /* PREFIX_0F78 */ |
4e7d34a6 | 4103 | { |
bf890a93 | 4104 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 4105 | { Bad_Opcode }, |
bf890a93 IT |
4106 | {"extrq", { XS, Ib, Ib }, 0 }, |
4107 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
4108 | }, |
4109 | ||
1ceb70f8 | 4110 | /* PREFIX_0F79 */ |
4e7d34a6 | 4111 | { |
bf890a93 | 4112 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 4113 | { Bad_Opcode }, |
bf890a93 IT |
4114 | {"extrq", { XM, XS }, 0 }, |
4115 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
4116 | }, |
4117 | ||
1ceb70f8 | 4118 | /* PREFIX_0F7C */ |
ca164297 | 4119 | { |
592d1631 L |
4120 | { Bad_Opcode }, |
4121 | { Bad_Opcode }, | |
507bd325 L |
4122 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
4123 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 4124 | }, |
4e7d34a6 | 4125 | |
1ceb70f8 | 4126 | /* PREFIX_0F7D */ |
ca164297 | 4127 | { |
592d1631 L |
4128 | { Bad_Opcode }, |
4129 | { Bad_Opcode }, | |
507bd325 L |
4130 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
4131 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 4132 | }, |
4e7d34a6 | 4133 | |
1ceb70f8 | 4134 | /* PREFIX_0F7E */ |
ca164297 | 4135 | { |
507bd325 L |
4136 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
4137 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
4138 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 4139 | }, |
4e7d34a6 | 4140 | |
1ceb70f8 | 4141 | /* PREFIX_0F7F */ |
ca164297 | 4142 | { |
507bd325 L |
4143 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
4144 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
4145 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 4146 | }, |
4e7d34a6 | 4147 | |
c7b8aa3a L |
4148 | /* PREFIX_0FAE_REG_0 */ |
4149 | { | |
4150 | { Bad_Opcode }, | |
bf890a93 | 4151 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
4152 | }, |
4153 | ||
4154 | /* PREFIX_0FAE_REG_1 */ | |
4155 | { | |
4156 | { Bad_Opcode }, | |
bf890a93 | 4157 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
4158 | }, |
4159 | ||
4160 | /* PREFIX_0FAE_REG_2 */ | |
4161 | { | |
4162 | { Bad_Opcode }, | |
bf890a93 | 4163 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
4164 | }, |
4165 | ||
4166 | /* PREFIX_0FAE_REG_3 */ | |
4167 | { | |
4168 | { Bad_Opcode }, | |
bf890a93 | 4169 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
4170 | }, |
4171 | ||
6b40c462 L |
4172 | /* PREFIX_MOD_0_0FAE_REG_4 */ |
4173 | { | |
4174 | { "xsave", { FXSAVE }, 0 }, | |
4175 | { "ptwrite%LQ", { Edq }, 0 }, | |
4176 | }, | |
4177 | ||
4178 | /* PREFIX_MOD_3_0FAE_REG_4 */ | |
4179 | { | |
4180 | { Bad_Opcode }, | |
4181 | { "ptwrite%LQ", { Edq }, 0 }, | |
4182 | }, | |
4183 | ||
603555e5 L |
4184 | /* PREFIX_MOD_0_0FAE_REG_5 */ |
4185 | { | |
4186 | { "xrstor", { FXSAVE }, PREFIX_OPCODE }, | |
2234eee6 L |
4187 | }, |
4188 | ||
4189 | /* PREFIX_MOD_3_0FAE_REG_5 */ | |
4190 | { | |
4191 | { "lfence", { Skip_MODRM }, 0 }, | |
4192 | { "incsspK", { Rdq }, PREFIX_OPCODE }, | |
603555e5 L |
4193 | }, |
4194 | ||
c5e7287a IT |
4195 | /* PREFIX_0FAE_REG_6 */ |
4196 | { | |
603555e5 L |
4197 | { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, |
4198 | { "clrssbsy", { Mq }, PREFIX_OPCODE }, | |
4199 | { "clwb", { Mb }, PREFIX_OPCODE }, | |
c5e7287a IT |
4200 | }, |
4201 | ||
963f3586 IT |
4202 | /* PREFIX_0FAE_REG_7 */ |
4203 | { | |
bf890a93 | 4204 | { "clflush", { Mb }, 0 }, |
963f3586 | 4205 | { Bad_Opcode }, |
bf890a93 | 4206 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
4207 | }, |
4208 | ||
1ceb70f8 | 4209 | /* PREFIX_0FB8 */ |
ca164297 | 4210 | { |
592d1631 | 4211 | { Bad_Opcode }, |
bf890a93 | 4212 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 4213 | }, |
4e7d34a6 | 4214 | |
f12dc422 L |
4215 | /* PREFIX_0FBC */ |
4216 | { | |
bf890a93 IT |
4217 | { "bsfS", { Gv, Ev }, 0 }, |
4218 | { "tzcntS", { Gv, Ev }, 0 }, | |
4219 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
4220 | }, |
4221 | ||
1ceb70f8 | 4222 | /* PREFIX_0FBD */ |
050dfa73 | 4223 | { |
bf890a93 IT |
4224 | { "bsrS", { Gv, Ev }, 0 }, |
4225 | { "lzcntS", { Gv, Ev }, 0 }, | |
4226 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
4227 | }, |
4228 | ||
1ceb70f8 | 4229 | /* PREFIX_0FC2 */ |
050dfa73 | 4230 | { |
507bd325 L |
4231 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
4232 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
4233 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
4234 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 4235 | }, |
246c51aa | 4236 | |
a8484f96 | 4237 | /* PREFIX_MOD_0_0FC3 */ |
4ee52178 | 4238 | { |
a8484f96 | 4239 | { "movntiS", { Ev, Gv }, PREFIX_OPCODE }, |
4ee52178 L |
4240 | }, |
4241 | ||
f24bcbaa | 4242 | /* PREFIX_MOD_0_0FC7_REG_6 */ |
92fddf8e | 4243 | { |
bf890a93 IT |
4244 | { "vmptrld",{ Mq }, 0 }, |
4245 | { "vmxon", { Mq }, 0 }, | |
4246 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
4247 | }, |
4248 | ||
f24bcbaa L |
4249 | /* PREFIX_MOD_3_0FC7_REG_6 */ |
4250 | { | |
4251 | { "rdrand", { Ev }, 0 }, | |
4252 | { Bad_Opcode }, | |
4253 | { "rdrand", { Ev }, 0 } | |
4254 | }, | |
4255 | ||
4256 | /* PREFIX_MOD_3_0FC7_REG_7 */ | |
4257 | { | |
4258 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 4259 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
4260 | { "rdseed", { Ev }, 0 }, |
4261 | }, | |
4262 | ||
1ceb70f8 | 4263 | /* PREFIX_0FD0 */ |
050dfa73 | 4264 | { |
592d1631 L |
4265 | { Bad_Opcode }, |
4266 | { Bad_Opcode }, | |
bf890a93 IT |
4267 | { "addsubpd", { XM, EXx }, 0 }, |
4268 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 4269 | }, |
050dfa73 | 4270 | |
1ceb70f8 | 4271 | /* PREFIX_0FD6 */ |
050dfa73 | 4272 | { |
592d1631 | 4273 | { Bad_Opcode }, |
bf890a93 IT |
4274 | { "movq2dq",{ XM, MS }, 0 }, |
4275 | { "movq", { EXqS, XM }, 0 }, | |
4276 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
4277 | }, |
4278 | ||
1ceb70f8 | 4279 | /* PREFIX_0FE6 */ |
7918206c | 4280 | { |
592d1631 | 4281 | { Bad_Opcode }, |
507bd325 L |
4282 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
4283 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
4284 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 4285 | }, |
8b38ad71 | 4286 | |
1ceb70f8 | 4287 | /* PREFIX_0FE7 */ |
8b38ad71 | 4288 | { |
507bd325 | 4289 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 4290 | { Bad_Opcode }, |
75c135a8 | 4291 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
4292 | }, |
4293 | ||
1ceb70f8 | 4294 | /* PREFIX_0FF0 */ |
4e7d34a6 | 4295 | { |
592d1631 L |
4296 | { Bad_Opcode }, |
4297 | { Bad_Opcode }, | |
4298 | { Bad_Opcode }, | |
1ceb70f8 | 4299 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
4300 | }, |
4301 | ||
1ceb70f8 | 4302 | /* PREFIX_0FF7 */ |
4e7d34a6 | 4303 | { |
507bd325 | 4304 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 4305 | { Bad_Opcode }, |
507bd325 | 4306 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 4307 | }, |
42903f7f | 4308 | |
1ceb70f8 | 4309 | /* PREFIX_0F3810 */ |
42903f7f | 4310 | { |
592d1631 L |
4311 | { Bad_Opcode }, |
4312 | { Bad_Opcode }, | |
507bd325 | 4313 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4314 | }, |
4315 | ||
1ceb70f8 | 4316 | /* PREFIX_0F3814 */ |
42903f7f | 4317 | { |
592d1631 L |
4318 | { Bad_Opcode }, |
4319 | { Bad_Opcode }, | |
507bd325 | 4320 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4321 | }, |
4322 | ||
1ceb70f8 | 4323 | /* PREFIX_0F3815 */ |
42903f7f | 4324 | { |
592d1631 L |
4325 | { Bad_Opcode }, |
4326 | { Bad_Opcode }, | |
507bd325 | 4327 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4328 | }, |
4329 | ||
1ceb70f8 | 4330 | /* PREFIX_0F3817 */ |
42903f7f | 4331 | { |
592d1631 L |
4332 | { Bad_Opcode }, |
4333 | { Bad_Opcode }, | |
507bd325 | 4334 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4335 | }, |
4336 | ||
1ceb70f8 | 4337 | /* PREFIX_0F3820 */ |
42903f7f | 4338 | { |
592d1631 L |
4339 | { Bad_Opcode }, |
4340 | { Bad_Opcode }, | |
507bd325 | 4341 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4342 | }, |
4343 | ||
1ceb70f8 | 4344 | /* PREFIX_0F3821 */ |
42903f7f | 4345 | { |
592d1631 L |
4346 | { Bad_Opcode }, |
4347 | { Bad_Opcode }, | |
507bd325 | 4348 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4349 | }, |
4350 | ||
1ceb70f8 | 4351 | /* PREFIX_0F3822 */ |
42903f7f | 4352 | { |
592d1631 L |
4353 | { Bad_Opcode }, |
4354 | { Bad_Opcode }, | |
507bd325 | 4355 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4356 | }, |
4357 | ||
1ceb70f8 | 4358 | /* PREFIX_0F3823 */ |
42903f7f | 4359 | { |
592d1631 L |
4360 | { Bad_Opcode }, |
4361 | { Bad_Opcode }, | |
507bd325 | 4362 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4363 | }, |
4364 | ||
1ceb70f8 | 4365 | /* PREFIX_0F3824 */ |
42903f7f | 4366 | { |
592d1631 L |
4367 | { Bad_Opcode }, |
4368 | { Bad_Opcode }, | |
507bd325 | 4369 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4370 | }, |
4371 | ||
1ceb70f8 | 4372 | /* PREFIX_0F3825 */ |
42903f7f | 4373 | { |
592d1631 L |
4374 | { Bad_Opcode }, |
4375 | { Bad_Opcode }, | |
507bd325 | 4376 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4377 | }, |
4378 | ||
1ceb70f8 | 4379 | /* PREFIX_0F3828 */ |
42903f7f | 4380 | { |
592d1631 L |
4381 | { Bad_Opcode }, |
4382 | { Bad_Opcode }, | |
507bd325 | 4383 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4384 | }, |
4385 | ||
1ceb70f8 | 4386 | /* PREFIX_0F3829 */ |
42903f7f | 4387 | { |
592d1631 L |
4388 | { Bad_Opcode }, |
4389 | { Bad_Opcode }, | |
507bd325 | 4390 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4391 | }, |
4392 | ||
1ceb70f8 | 4393 | /* PREFIX_0F382A */ |
42903f7f | 4394 | { |
592d1631 L |
4395 | { Bad_Opcode }, |
4396 | { Bad_Opcode }, | |
75c135a8 | 4397 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
4398 | }, |
4399 | ||
1ceb70f8 | 4400 | /* PREFIX_0F382B */ |
42903f7f | 4401 | { |
592d1631 L |
4402 | { Bad_Opcode }, |
4403 | { Bad_Opcode }, | |
507bd325 | 4404 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4405 | }, |
4406 | ||
1ceb70f8 | 4407 | /* PREFIX_0F3830 */ |
42903f7f | 4408 | { |
592d1631 L |
4409 | { Bad_Opcode }, |
4410 | { Bad_Opcode }, | |
507bd325 | 4411 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4412 | }, |
4413 | ||
1ceb70f8 | 4414 | /* PREFIX_0F3831 */ |
42903f7f | 4415 | { |
592d1631 L |
4416 | { Bad_Opcode }, |
4417 | { Bad_Opcode }, | |
507bd325 | 4418 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4419 | }, |
4420 | ||
1ceb70f8 | 4421 | /* PREFIX_0F3832 */ |
42903f7f | 4422 | { |
592d1631 L |
4423 | { Bad_Opcode }, |
4424 | { Bad_Opcode }, | |
507bd325 | 4425 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4426 | }, |
4427 | ||
1ceb70f8 | 4428 | /* PREFIX_0F3833 */ |
42903f7f | 4429 | { |
592d1631 L |
4430 | { Bad_Opcode }, |
4431 | { Bad_Opcode }, | |
507bd325 | 4432 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4433 | }, |
4434 | ||
1ceb70f8 | 4435 | /* PREFIX_0F3834 */ |
42903f7f | 4436 | { |
592d1631 L |
4437 | { Bad_Opcode }, |
4438 | { Bad_Opcode }, | |
507bd325 | 4439 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4440 | }, |
4441 | ||
1ceb70f8 | 4442 | /* PREFIX_0F3835 */ |
42903f7f | 4443 | { |
592d1631 L |
4444 | { Bad_Opcode }, |
4445 | { Bad_Opcode }, | |
507bd325 | 4446 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4447 | }, |
4448 | ||
1ceb70f8 | 4449 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4450 | { |
592d1631 L |
4451 | { Bad_Opcode }, |
4452 | { Bad_Opcode }, | |
507bd325 | 4453 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
4e7d34a6 L |
4454 | }, |
4455 | ||
1ceb70f8 | 4456 | /* PREFIX_0F3838 */ |
42903f7f | 4457 | { |
592d1631 L |
4458 | { Bad_Opcode }, |
4459 | { Bad_Opcode }, | |
507bd325 | 4460 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4461 | }, |
4462 | ||
1ceb70f8 | 4463 | /* PREFIX_0F3839 */ |
42903f7f | 4464 | { |
592d1631 L |
4465 | { Bad_Opcode }, |
4466 | { Bad_Opcode }, | |
507bd325 | 4467 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4468 | }, |
4469 | ||
1ceb70f8 | 4470 | /* PREFIX_0F383A */ |
42903f7f | 4471 | { |
592d1631 L |
4472 | { Bad_Opcode }, |
4473 | { Bad_Opcode }, | |
507bd325 | 4474 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4475 | }, |
4476 | ||
1ceb70f8 | 4477 | /* PREFIX_0F383B */ |
42903f7f | 4478 | { |
592d1631 L |
4479 | { Bad_Opcode }, |
4480 | { Bad_Opcode }, | |
507bd325 | 4481 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4482 | }, |
4483 | ||
1ceb70f8 | 4484 | /* PREFIX_0F383C */ |
42903f7f | 4485 | { |
592d1631 L |
4486 | { Bad_Opcode }, |
4487 | { Bad_Opcode }, | |
507bd325 | 4488 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4489 | }, |
4490 | ||
1ceb70f8 | 4491 | /* PREFIX_0F383D */ |
42903f7f | 4492 | { |
592d1631 L |
4493 | { Bad_Opcode }, |
4494 | { Bad_Opcode }, | |
507bd325 | 4495 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4496 | }, |
4497 | ||
1ceb70f8 | 4498 | /* PREFIX_0F383E */ |
42903f7f | 4499 | { |
592d1631 L |
4500 | { Bad_Opcode }, |
4501 | { Bad_Opcode }, | |
507bd325 | 4502 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4503 | }, |
4504 | ||
1ceb70f8 | 4505 | /* PREFIX_0F383F */ |
42903f7f | 4506 | { |
592d1631 L |
4507 | { Bad_Opcode }, |
4508 | { Bad_Opcode }, | |
507bd325 | 4509 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4510 | }, |
4511 | ||
1ceb70f8 | 4512 | /* PREFIX_0F3840 */ |
42903f7f | 4513 | { |
592d1631 L |
4514 | { Bad_Opcode }, |
4515 | { Bad_Opcode }, | |
507bd325 | 4516 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4517 | }, |
4518 | ||
1ceb70f8 | 4519 | /* PREFIX_0F3841 */ |
42903f7f | 4520 | { |
592d1631 L |
4521 | { Bad_Opcode }, |
4522 | { Bad_Opcode }, | |
507bd325 | 4523 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4524 | }, |
4525 | ||
f1f8f695 L |
4526 | /* PREFIX_0F3880 */ |
4527 | { | |
592d1631 L |
4528 | { Bad_Opcode }, |
4529 | { Bad_Opcode }, | |
507bd325 | 4530 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4531 | }, |
4532 | ||
4533 | /* PREFIX_0F3881 */ | |
4534 | { | |
592d1631 L |
4535 | { Bad_Opcode }, |
4536 | { Bad_Opcode }, | |
507bd325 | 4537 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4538 | }, |
4539 | ||
6c30d220 L |
4540 | /* PREFIX_0F3882 */ |
4541 | { | |
4542 | { Bad_Opcode }, | |
4543 | { Bad_Opcode }, | |
507bd325 | 4544 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
6c30d220 L |
4545 | }, |
4546 | ||
a0046408 L |
4547 | /* PREFIX_0F38C8 */ |
4548 | { | |
507bd325 | 4549 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4550 | }, |
4551 | ||
4552 | /* PREFIX_0F38C9 */ | |
4553 | { | |
507bd325 | 4554 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4555 | }, |
4556 | ||
4557 | /* PREFIX_0F38CA */ | |
4558 | { | |
507bd325 | 4559 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4560 | }, |
4561 | ||
4562 | /* PREFIX_0F38CB */ | |
4563 | { | |
507bd325 | 4564 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
a0046408 L |
4565 | }, |
4566 | ||
4567 | /* PREFIX_0F38CC */ | |
4568 | { | |
507bd325 | 4569 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4570 | }, |
4571 | ||
4572 | /* PREFIX_0F38CD */ | |
4573 | { | |
507bd325 | 4574 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4575 | }, |
4576 | ||
48521003 IT |
4577 | /* PREFIX_0F38CF */ |
4578 | { | |
4579 | { Bad_Opcode }, | |
4580 | { Bad_Opcode }, | |
4581 | { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE }, | |
4582 | }, | |
4583 | ||
c0f3af97 L |
4584 | /* PREFIX_0F38DB */ |
4585 | { | |
592d1631 L |
4586 | { Bad_Opcode }, |
4587 | { Bad_Opcode }, | |
507bd325 | 4588 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4589 | }, |
4590 | ||
4591 | /* PREFIX_0F38DC */ | |
4592 | { | |
592d1631 L |
4593 | { Bad_Opcode }, |
4594 | { Bad_Opcode }, | |
507bd325 | 4595 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4596 | }, |
4597 | ||
4598 | /* PREFIX_0F38DD */ | |
4599 | { | |
592d1631 L |
4600 | { Bad_Opcode }, |
4601 | { Bad_Opcode }, | |
507bd325 | 4602 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4603 | }, |
4604 | ||
4605 | /* PREFIX_0F38DE */ | |
4606 | { | |
592d1631 L |
4607 | { Bad_Opcode }, |
4608 | { Bad_Opcode }, | |
507bd325 | 4609 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4610 | }, |
4611 | ||
4612 | /* PREFIX_0F38DF */ | |
4613 | { | |
592d1631 L |
4614 | { Bad_Opcode }, |
4615 | { Bad_Opcode }, | |
507bd325 | 4616 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4617 | }, |
4618 | ||
1ceb70f8 | 4619 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4620 | { |
507bd325 | 4621 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
592d1631 | 4622 | { Bad_Opcode }, |
507bd325 L |
4623 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4624 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4625 | }, |
4626 | ||
1ceb70f8 | 4627 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4628 | { |
507bd325 | 4629 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
592d1631 | 4630 | { Bad_Opcode }, |
507bd325 L |
4631 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4632 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4633 | }, |
4634 | ||
603555e5 | 4635 | /* PREFIX_0F38F5 */ |
e2e1fcde L |
4636 | { |
4637 | { Bad_Opcode }, | |
603555e5 L |
4638 | { Bad_Opcode }, |
4639 | { MOD_TABLE (MOD_0F38F5_PREFIX_2) }, | |
4640 | }, | |
4641 | ||
4642 | /* PREFIX_0F38F6 */ | |
4643 | { | |
4644 | { MOD_TABLE (MOD_0F38F6_PREFIX_0) }, | |
507bd325 L |
4645 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4646 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
4647 | { Bad_Opcode }, |
4648 | }, | |
4649 | ||
1ceb70f8 | 4650 | /* PREFIX_0F3A08 */ |
42903f7f | 4651 | { |
592d1631 L |
4652 | { Bad_Opcode }, |
4653 | { Bad_Opcode }, | |
507bd325 | 4654 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4655 | }, |
4656 | ||
1ceb70f8 | 4657 | /* PREFIX_0F3A09 */ |
42903f7f | 4658 | { |
592d1631 L |
4659 | { Bad_Opcode }, |
4660 | { Bad_Opcode }, | |
507bd325 | 4661 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4662 | }, |
4663 | ||
1ceb70f8 | 4664 | /* PREFIX_0F3A0A */ |
42903f7f | 4665 | { |
592d1631 L |
4666 | { Bad_Opcode }, |
4667 | { Bad_Opcode }, | |
507bd325 | 4668 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4669 | }, |
4670 | ||
1ceb70f8 | 4671 | /* PREFIX_0F3A0B */ |
42903f7f | 4672 | { |
592d1631 L |
4673 | { Bad_Opcode }, |
4674 | { Bad_Opcode }, | |
507bd325 | 4675 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4676 | }, |
4677 | ||
1ceb70f8 | 4678 | /* PREFIX_0F3A0C */ |
42903f7f | 4679 | { |
592d1631 L |
4680 | { Bad_Opcode }, |
4681 | { Bad_Opcode }, | |
507bd325 | 4682 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4683 | }, |
4684 | ||
1ceb70f8 | 4685 | /* PREFIX_0F3A0D */ |
42903f7f | 4686 | { |
592d1631 L |
4687 | { Bad_Opcode }, |
4688 | { Bad_Opcode }, | |
507bd325 | 4689 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4690 | }, |
4691 | ||
1ceb70f8 | 4692 | /* PREFIX_0F3A0E */ |
42903f7f | 4693 | { |
592d1631 L |
4694 | { Bad_Opcode }, |
4695 | { Bad_Opcode }, | |
507bd325 | 4696 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4697 | }, |
4698 | ||
1ceb70f8 | 4699 | /* PREFIX_0F3A14 */ |
42903f7f | 4700 | { |
592d1631 L |
4701 | { Bad_Opcode }, |
4702 | { Bad_Opcode }, | |
507bd325 | 4703 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4704 | }, |
4705 | ||
1ceb70f8 | 4706 | /* PREFIX_0F3A15 */ |
42903f7f | 4707 | { |
592d1631 L |
4708 | { Bad_Opcode }, |
4709 | { Bad_Opcode }, | |
507bd325 | 4710 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4711 | }, |
4712 | ||
1ceb70f8 | 4713 | /* PREFIX_0F3A16 */ |
42903f7f | 4714 | { |
592d1631 L |
4715 | { Bad_Opcode }, |
4716 | { Bad_Opcode }, | |
507bd325 | 4717 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4718 | }, |
4719 | ||
1ceb70f8 | 4720 | /* PREFIX_0F3A17 */ |
42903f7f | 4721 | { |
592d1631 L |
4722 | { Bad_Opcode }, |
4723 | { Bad_Opcode }, | |
507bd325 | 4724 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4725 | }, |
4726 | ||
1ceb70f8 | 4727 | /* PREFIX_0F3A20 */ |
42903f7f | 4728 | { |
592d1631 L |
4729 | { Bad_Opcode }, |
4730 | { Bad_Opcode }, | |
507bd325 | 4731 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4732 | }, |
4733 | ||
1ceb70f8 | 4734 | /* PREFIX_0F3A21 */ |
42903f7f | 4735 | { |
592d1631 L |
4736 | { Bad_Opcode }, |
4737 | { Bad_Opcode }, | |
507bd325 | 4738 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4739 | }, |
4740 | ||
1ceb70f8 | 4741 | /* PREFIX_0F3A22 */ |
42903f7f | 4742 | { |
592d1631 L |
4743 | { Bad_Opcode }, |
4744 | { Bad_Opcode }, | |
507bd325 | 4745 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4746 | }, |
4747 | ||
1ceb70f8 | 4748 | /* PREFIX_0F3A40 */ |
42903f7f | 4749 | { |
592d1631 L |
4750 | { Bad_Opcode }, |
4751 | { Bad_Opcode }, | |
507bd325 | 4752 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4753 | }, |
4754 | ||
1ceb70f8 | 4755 | /* PREFIX_0F3A41 */ |
42903f7f | 4756 | { |
592d1631 L |
4757 | { Bad_Opcode }, |
4758 | { Bad_Opcode }, | |
507bd325 | 4759 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4760 | }, |
4761 | ||
1ceb70f8 | 4762 | /* PREFIX_0F3A42 */ |
42903f7f | 4763 | { |
592d1631 L |
4764 | { Bad_Opcode }, |
4765 | { Bad_Opcode }, | |
507bd325 | 4766 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f | 4767 | }, |
381d071f | 4768 | |
c0f3af97 L |
4769 | /* PREFIX_0F3A44 */ |
4770 | { | |
592d1631 L |
4771 | { Bad_Opcode }, |
4772 | { Bad_Opcode }, | |
507bd325 | 4773 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
c0f3af97 L |
4774 | }, |
4775 | ||
1ceb70f8 | 4776 | /* PREFIX_0F3A60 */ |
381d071f | 4777 | { |
592d1631 L |
4778 | { Bad_Opcode }, |
4779 | { Bad_Opcode }, | |
15c7c1d8 | 4780 | { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4781 | }, |
4782 | ||
1ceb70f8 | 4783 | /* PREFIX_0F3A61 */ |
381d071f | 4784 | { |
592d1631 L |
4785 | { Bad_Opcode }, |
4786 | { Bad_Opcode }, | |
15c7c1d8 | 4787 | { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4788 | }, |
4789 | ||
1ceb70f8 | 4790 | /* PREFIX_0F3A62 */ |
381d071f | 4791 | { |
592d1631 L |
4792 | { Bad_Opcode }, |
4793 | { Bad_Opcode }, | |
507bd325 | 4794 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4795 | }, |
4796 | ||
1ceb70f8 | 4797 | /* PREFIX_0F3A63 */ |
381d071f | 4798 | { |
592d1631 L |
4799 | { Bad_Opcode }, |
4800 | { Bad_Opcode }, | |
507bd325 | 4801 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f | 4802 | }, |
09a2c6cf | 4803 | |
a0046408 L |
4804 | /* PREFIX_0F3ACC */ |
4805 | { | |
507bd325 | 4806 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
a0046408 L |
4807 | }, |
4808 | ||
48521003 IT |
4809 | /* PREFIX_0F3ACE */ |
4810 | { | |
4811 | { Bad_Opcode }, | |
4812 | { Bad_Opcode }, | |
4813 | { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4814 | }, | |
4815 | ||
4816 | /* PREFIX_0F3ACF */ | |
4817 | { | |
4818 | { Bad_Opcode }, | |
4819 | { Bad_Opcode }, | |
4820 | { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4821 | }, | |
4822 | ||
c0f3af97 | 4823 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4824 | { |
592d1631 L |
4825 | { Bad_Opcode }, |
4826 | { Bad_Opcode }, | |
507bd325 | 4827 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
09a2c6cf L |
4828 | }, |
4829 | ||
592a252b | 4830 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4831 | { |
592a252b L |
4832 | { VEX_W_TABLE (VEX_W_0F10_P_0) }, |
4833 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, | |
4834 | { VEX_W_TABLE (VEX_W_0F10_P_2) }, | |
4835 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, | |
09a2c6cf L |
4836 | }, |
4837 | ||
592a252b | 4838 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4839 | { |
592a252b L |
4840 | { VEX_W_TABLE (VEX_W_0F11_P_0) }, |
4841 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, | |
4842 | { VEX_W_TABLE (VEX_W_0F11_P_2) }, | |
4843 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, | |
09a2c6cf L |
4844 | }, |
4845 | ||
592a252b | 4846 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4847 | { |
592a252b L |
4848 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
4849 | { VEX_W_TABLE (VEX_W_0F12_P_1) }, | |
4850 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, | |
4851 | { VEX_W_TABLE (VEX_W_0F12_P_3) }, | |
09a2c6cf L |
4852 | }, |
4853 | ||
592a252b | 4854 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4855 | { |
592a252b L |
4856 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
4857 | { VEX_W_TABLE (VEX_W_0F16_P_1) }, | |
4858 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, | |
5f754f58 | 4859 | }, |
7c52e0e8 | 4860 | |
592a252b | 4861 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4862 | { |
592d1631 | 4863 | { Bad_Opcode }, |
592a252b | 4864 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, |
592d1631 | 4865 | { Bad_Opcode }, |
592a252b | 4866 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, |
5f754f58 | 4867 | }, |
7c52e0e8 | 4868 | |
592a252b | 4869 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4870 | { |
592d1631 | 4871 | { Bad_Opcode }, |
592a252b | 4872 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, |
592d1631 | 4873 | { Bad_Opcode }, |
592a252b | 4874 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, |
5f754f58 | 4875 | }, |
7c52e0e8 | 4876 | |
592a252b | 4877 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4878 | { |
592d1631 | 4879 | { Bad_Opcode }, |
592a252b | 4880 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, |
592d1631 | 4881 | { Bad_Opcode }, |
592a252b | 4882 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, |
7c52e0e8 L |
4883 | }, |
4884 | ||
592a252b | 4885 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4886 | { |
592a252b | 4887 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, |
592d1631 | 4888 | { Bad_Opcode }, |
592a252b | 4889 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, |
7c52e0e8 L |
4890 | }, |
4891 | ||
592a252b | 4892 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4893 | { |
592a252b | 4894 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, |
592d1631 | 4895 | { Bad_Opcode }, |
592a252b | 4896 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, |
7c52e0e8 L |
4897 | }, |
4898 | ||
43234a1e L |
4899 | /* PREFIX_VEX_0F41 */ |
4900 | { | |
4901 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
4902 | { Bad_Opcode }, |
4903 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
4904 | }, |
4905 | ||
4906 | /* PREFIX_VEX_0F42 */ | |
4907 | { | |
4908 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
4909 | { Bad_Opcode }, |
4910 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
4911 | }, |
4912 | ||
4913 | /* PREFIX_VEX_0F44 */ | |
4914 | { | |
4915 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
1ba585e8 IT |
4916 | { Bad_Opcode }, |
4917 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, | |
43234a1e L |
4918 | }, |
4919 | ||
4920 | /* PREFIX_VEX_0F45 */ | |
4921 | { | |
4922 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
1ba585e8 IT |
4923 | { Bad_Opcode }, |
4924 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, | |
43234a1e L |
4925 | }, |
4926 | ||
4927 | /* PREFIX_VEX_0F46 */ | |
4928 | { | |
4929 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
1ba585e8 IT |
4930 | { Bad_Opcode }, |
4931 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, | |
43234a1e L |
4932 | }, |
4933 | ||
4934 | /* PREFIX_VEX_0F47 */ | |
4935 | { | |
4936 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
1ba585e8 IT |
4937 | { Bad_Opcode }, |
4938 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, | |
43234a1e L |
4939 | }, |
4940 | ||
1ba585e8 | 4941 | /* PREFIX_VEX_0F4A */ |
43234a1e | 4942 | { |
1ba585e8 | 4943 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 4944 | { Bad_Opcode }, |
1ba585e8 IT |
4945 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
4946 | }, | |
4947 | ||
4948 | /* PREFIX_VEX_0F4B */ | |
4949 | { | |
4950 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, | |
43234a1e L |
4951 | { Bad_Opcode }, |
4952 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
4953 | }, | |
4954 | ||
592a252b | 4955 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 4956 | { |
592a252b L |
4957 | { VEX_W_TABLE (VEX_W_0F51_P_0) }, |
4958 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, | |
4959 | { VEX_W_TABLE (VEX_W_0F51_P_2) }, | |
4960 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, | |
7c52e0e8 L |
4961 | }, |
4962 | ||
592a252b | 4963 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 4964 | { |
592a252b L |
4965 | { VEX_W_TABLE (VEX_W_0F52_P_0) }, |
4966 | { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, | |
7c52e0e8 L |
4967 | }, |
4968 | ||
592a252b | 4969 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 4970 | { |
592a252b L |
4971 | { VEX_W_TABLE (VEX_W_0F53_P_0) }, |
4972 | { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, | |
7c52e0e8 L |
4973 | }, |
4974 | ||
592a252b | 4975 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 4976 | { |
592a252b L |
4977 | { VEX_W_TABLE (VEX_W_0F58_P_0) }, |
4978 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, | |
4979 | { VEX_W_TABLE (VEX_W_0F58_P_2) }, | |
4980 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, | |
7c52e0e8 L |
4981 | }, |
4982 | ||
592a252b | 4983 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 4984 | { |
592a252b L |
4985 | { VEX_W_TABLE (VEX_W_0F59_P_0) }, |
4986 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, | |
4987 | { VEX_W_TABLE (VEX_W_0F59_P_2) }, | |
4988 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, | |
7c52e0e8 L |
4989 | }, |
4990 | ||
592a252b | 4991 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 4992 | { |
592a252b L |
4993 | { VEX_W_TABLE (VEX_W_0F5A_P_0) }, |
4994 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, | |
bf890a93 | 4995 | { "vcvtpd2ps%XY", { XMM, EXx }, 0 }, |
592a252b | 4996 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, |
7c52e0e8 L |
4997 | }, |
4998 | ||
592a252b | 4999 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 5000 | { |
592a252b L |
5001 | { VEX_W_TABLE (VEX_W_0F5B_P_0) }, |
5002 | { VEX_W_TABLE (VEX_W_0F5B_P_1) }, | |
5003 | { VEX_W_TABLE (VEX_W_0F5B_P_2) }, | |
7c52e0e8 L |
5004 | }, |
5005 | ||
592a252b | 5006 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 5007 | { |
592a252b L |
5008 | { VEX_W_TABLE (VEX_W_0F5C_P_0) }, |
5009 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, | |
5010 | { VEX_W_TABLE (VEX_W_0F5C_P_2) }, | |
5011 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, | |
7c52e0e8 L |
5012 | }, |
5013 | ||
592a252b | 5014 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 5015 | { |
592a252b L |
5016 | { VEX_W_TABLE (VEX_W_0F5D_P_0) }, |
5017 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, | |
5018 | { VEX_W_TABLE (VEX_W_0F5D_P_2) }, | |
5019 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, | |
7c52e0e8 L |
5020 | }, |
5021 | ||
592a252b | 5022 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 5023 | { |
592a252b L |
5024 | { VEX_W_TABLE (VEX_W_0F5E_P_0) }, |
5025 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, | |
5026 | { VEX_W_TABLE (VEX_W_0F5E_P_2) }, | |
5027 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, | |
7c52e0e8 L |
5028 | }, |
5029 | ||
592a252b | 5030 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 5031 | { |
592a252b L |
5032 | { VEX_W_TABLE (VEX_W_0F5F_P_0) }, |
5033 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, | |
5034 | { VEX_W_TABLE (VEX_W_0F5F_P_2) }, | |
5035 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, | |
7c52e0e8 L |
5036 | }, |
5037 | ||
592a252b | 5038 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 5039 | { |
592d1631 L |
5040 | { Bad_Opcode }, |
5041 | { Bad_Opcode }, | |
6c30d220 | 5042 | { VEX_W_TABLE (VEX_W_0F60_P_2) }, |
7c52e0e8 L |
5043 | }, |
5044 | ||
592a252b | 5045 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 5046 | { |
592d1631 L |
5047 | { Bad_Opcode }, |
5048 | { Bad_Opcode }, | |
6c30d220 | 5049 | { VEX_W_TABLE (VEX_W_0F61_P_2) }, |
7c52e0e8 L |
5050 | }, |
5051 | ||
592a252b | 5052 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 5053 | { |
592d1631 L |
5054 | { Bad_Opcode }, |
5055 | { Bad_Opcode }, | |
6c30d220 | 5056 | { VEX_W_TABLE (VEX_W_0F62_P_2) }, |
7c52e0e8 L |
5057 | }, |
5058 | ||
592a252b | 5059 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 5060 | { |
592d1631 L |
5061 | { Bad_Opcode }, |
5062 | { Bad_Opcode }, | |
6c30d220 | 5063 | { VEX_W_TABLE (VEX_W_0F63_P_2) }, |
7c52e0e8 L |
5064 | }, |
5065 | ||
592a252b | 5066 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 5067 | { |
592d1631 L |
5068 | { Bad_Opcode }, |
5069 | { Bad_Opcode }, | |
6c30d220 | 5070 | { VEX_W_TABLE (VEX_W_0F64_P_2) }, |
7c52e0e8 L |
5071 | }, |
5072 | ||
592a252b | 5073 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 5074 | { |
592d1631 L |
5075 | { Bad_Opcode }, |
5076 | { Bad_Opcode }, | |
6c30d220 | 5077 | { VEX_W_TABLE (VEX_W_0F65_P_2) }, |
7c52e0e8 L |
5078 | }, |
5079 | ||
592a252b | 5080 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 5081 | { |
592d1631 L |
5082 | { Bad_Opcode }, |
5083 | { Bad_Opcode }, | |
6c30d220 | 5084 | { VEX_W_TABLE (VEX_W_0F66_P_2) }, |
7c52e0e8 | 5085 | }, |
6439fc28 | 5086 | |
592a252b | 5087 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 5088 | { |
592d1631 L |
5089 | { Bad_Opcode }, |
5090 | { Bad_Opcode }, | |
6c30d220 | 5091 | { VEX_W_TABLE (VEX_W_0F67_P_2) }, |
c0f3af97 L |
5092 | }, |
5093 | ||
592a252b | 5094 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 5095 | { |
592d1631 L |
5096 | { Bad_Opcode }, |
5097 | { Bad_Opcode }, | |
6c30d220 | 5098 | { VEX_W_TABLE (VEX_W_0F68_P_2) }, |
c0f3af97 L |
5099 | }, |
5100 | ||
592a252b | 5101 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 5102 | { |
592d1631 L |
5103 | { Bad_Opcode }, |
5104 | { Bad_Opcode }, | |
6c30d220 | 5105 | { VEX_W_TABLE (VEX_W_0F69_P_2) }, |
c0f3af97 L |
5106 | }, |
5107 | ||
592a252b | 5108 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 5109 | { |
592d1631 L |
5110 | { Bad_Opcode }, |
5111 | { Bad_Opcode }, | |
6c30d220 | 5112 | { VEX_W_TABLE (VEX_W_0F6A_P_2) }, |
c0f3af97 L |
5113 | }, |
5114 | ||
592a252b | 5115 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 5116 | { |
592d1631 L |
5117 | { Bad_Opcode }, |
5118 | { Bad_Opcode }, | |
6c30d220 | 5119 | { VEX_W_TABLE (VEX_W_0F6B_P_2) }, |
c0f3af97 L |
5120 | }, |
5121 | ||
592a252b | 5122 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 5123 | { |
592d1631 L |
5124 | { Bad_Opcode }, |
5125 | { Bad_Opcode }, | |
6c30d220 | 5126 | { VEX_W_TABLE (VEX_W_0F6C_P_2) }, |
c0f3af97 L |
5127 | }, |
5128 | ||
592a252b | 5129 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 5130 | { |
592d1631 L |
5131 | { Bad_Opcode }, |
5132 | { Bad_Opcode }, | |
6c30d220 | 5133 | { VEX_W_TABLE (VEX_W_0F6D_P_2) }, |
c0f3af97 L |
5134 | }, |
5135 | ||
592a252b | 5136 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 5137 | { |
592d1631 L |
5138 | { Bad_Opcode }, |
5139 | { Bad_Opcode }, | |
592a252b | 5140 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
5141 | }, |
5142 | ||
592a252b | 5143 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 5144 | { |
592d1631 | 5145 | { Bad_Opcode }, |
592a252b L |
5146 | { VEX_W_TABLE (VEX_W_0F6F_P_1) }, |
5147 | { VEX_W_TABLE (VEX_W_0F6F_P_2) }, | |
c0f3af97 L |
5148 | }, |
5149 | ||
592a252b | 5150 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 5151 | { |
592d1631 | 5152 | { Bad_Opcode }, |
6c30d220 L |
5153 | { VEX_W_TABLE (VEX_W_0F70_P_1) }, |
5154 | { VEX_W_TABLE (VEX_W_0F70_P_2) }, | |
5155 | { VEX_W_TABLE (VEX_W_0F70_P_3) }, | |
c0f3af97 L |
5156 | }, |
5157 | ||
592a252b | 5158 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 5159 | { |
592d1631 L |
5160 | { Bad_Opcode }, |
5161 | { Bad_Opcode }, | |
6c30d220 | 5162 | { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, |
c0f3af97 L |
5163 | }, |
5164 | ||
592a252b | 5165 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 5166 | { |
592d1631 L |
5167 | { Bad_Opcode }, |
5168 | { Bad_Opcode }, | |
6c30d220 | 5169 | { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, |
c0f3af97 L |
5170 | }, |
5171 | ||
592a252b | 5172 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 5173 | { |
592d1631 L |
5174 | { Bad_Opcode }, |
5175 | { Bad_Opcode }, | |
6c30d220 | 5176 | { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, |
c0f3af97 L |
5177 | }, |
5178 | ||
592a252b | 5179 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 5180 | { |
592d1631 L |
5181 | { Bad_Opcode }, |
5182 | { Bad_Opcode }, | |
6c30d220 | 5183 | { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, |
c0f3af97 L |
5184 | }, |
5185 | ||
592a252b | 5186 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 5187 | { |
592d1631 L |
5188 | { Bad_Opcode }, |
5189 | { Bad_Opcode }, | |
6c30d220 | 5190 | { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, |
c0f3af97 L |
5191 | }, |
5192 | ||
592a252b | 5193 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 5194 | { |
592d1631 L |
5195 | { Bad_Opcode }, |
5196 | { Bad_Opcode }, | |
6c30d220 | 5197 | { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, |
c0f3af97 L |
5198 | }, |
5199 | ||
592a252b | 5200 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 5201 | { |
592d1631 L |
5202 | { Bad_Opcode }, |
5203 | { Bad_Opcode }, | |
6c30d220 | 5204 | { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, |
c0f3af97 L |
5205 | }, |
5206 | ||
592a252b | 5207 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 5208 | { |
592d1631 L |
5209 | { Bad_Opcode }, |
5210 | { Bad_Opcode }, | |
6c30d220 | 5211 | { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, |
c0f3af97 L |
5212 | }, |
5213 | ||
592a252b | 5214 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 5215 | { |
592d1631 L |
5216 | { Bad_Opcode }, |
5217 | { Bad_Opcode }, | |
6c30d220 | 5218 | { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, |
c0f3af97 L |
5219 | }, |
5220 | ||
592a252b | 5221 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 5222 | { |
592d1631 L |
5223 | { Bad_Opcode }, |
5224 | { Bad_Opcode }, | |
6c30d220 | 5225 | { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, |
c0f3af97 L |
5226 | }, |
5227 | ||
592a252b | 5228 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 5229 | { |
592d1631 L |
5230 | { Bad_Opcode }, |
5231 | { Bad_Opcode }, | |
6c30d220 | 5232 | { VEX_W_TABLE (VEX_W_0F74_P_2) }, |
c0f3af97 L |
5233 | }, |
5234 | ||
592a252b | 5235 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 5236 | { |
592d1631 L |
5237 | { Bad_Opcode }, |
5238 | { Bad_Opcode }, | |
6c30d220 | 5239 | { VEX_W_TABLE (VEX_W_0F75_P_2) }, |
c0f3af97 L |
5240 | }, |
5241 | ||
592a252b | 5242 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 5243 | { |
592d1631 L |
5244 | { Bad_Opcode }, |
5245 | { Bad_Opcode }, | |
6c30d220 | 5246 | { VEX_W_TABLE (VEX_W_0F76_P_2) }, |
c0f3af97 L |
5247 | }, |
5248 | ||
592a252b | 5249 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 5250 | { |
592a252b | 5251 | { VEX_W_TABLE (VEX_W_0F77_P_0) }, |
c0f3af97 L |
5252 | }, |
5253 | ||
592a252b | 5254 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 5255 | { |
592d1631 L |
5256 | { Bad_Opcode }, |
5257 | { Bad_Opcode }, | |
592a252b L |
5258 | { VEX_W_TABLE (VEX_W_0F7C_P_2) }, |
5259 | { VEX_W_TABLE (VEX_W_0F7C_P_3) }, | |
c0f3af97 L |
5260 | }, |
5261 | ||
592a252b | 5262 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 5263 | { |
592d1631 L |
5264 | { Bad_Opcode }, |
5265 | { Bad_Opcode }, | |
592a252b L |
5266 | { VEX_W_TABLE (VEX_W_0F7D_P_2) }, |
5267 | { VEX_W_TABLE (VEX_W_0F7D_P_3) }, | |
c0f3af97 L |
5268 | }, |
5269 | ||
592a252b | 5270 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 5271 | { |
592d1631 | 5272 | { Bad_Opcode }, |
592a252b L |
5273 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
5274 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
5275 | }, |
5276 | ||
592a252b | 5277 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 5278 | { |
592d1631 | 5279 | { Bad_Opcode }, |
592a252b L |
5280 | { VEX_W_TABLE (VEX_W_0F7F_P_1) }, |
5281 | { VEX_W_TABLE (VEX_W_0F7F_P_2) }, | |
c0f3af97 L |
5282 | }, |
5283 | ||
43234a1e L |
5284 | /* PREFIX_VEX_0F90 */ |
5285 | { | |
5286 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
1ba585e8 IT |
5287 | { Bad_Opcode }, |
5288 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, | |
43234a1e L |
5289 | }, |
5290 | ||
5291 | /* PREFIX_VEX_0F91 */ | |
5292 | { | |
5293 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
1ba585e8 IT |
5294 | { Bad_Opcode }, |
5295 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, | |
43234a1e L |
5296 | }, |
5297 | ||
5298 | /* PREFIX_VEX_0F92 */ | |
5299 | { | |
5300 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
1ba585e8 | 5301 | { Bad_Opcode }, |
90a915bf | 5302 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
1ba585e8 | 5303 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
43234a1e L |
5304 | }, |
5305 | ||
5306 | /* PREFIX_VEX_0F93 */ | |
5307 | { | |
5308 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
1ba585e8 | 5309 | { Bad_Opcode }, |
90a915bf | 5310 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
1ba585e8 | 5311 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
43234a1e L |
5312 | }, |
5313 | ||
5314 | /* PREFIX_VEX_0F98 */ | |
5315 | { | |
5316 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
1ba585e8 IT |
5317 | { Bad_Opcode }, |
5318 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, | |
5319 | }, | |
5320 | ||
5321 | /* PREFIX_VEX_0F99 */ | |
5322 | { | |
5323 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, | |
5324 | { Bad_Opcode }, | |
5325 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, | |
43234a1e L |
5326 | }, |
5327 | ||
592a252b | 5328 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 5329 | { |
592a252b L |
5330 | { VEX_W_TABLE (VEX_W_0FC2_P_0) }, |
5331 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, | |
5332 | { VEX_W_TABLE (VEX_W_0FC2_P_2) }, | |
5333 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, | |
c0f3af97 L |
5334 | }, |
5335 | ||
592a252b | 5336 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 5337 | { |
592d1631 L |
5338 | { Bad_Opcode }, |
5339 | { Bad_Opcode }, | |
592a252b | 5340 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
5341 | }, |
5342 | ||
592a252b | 5343 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 5344 | { |
592d1631 L |
5345 | { Bad_Opcode }, |
5346 | { Bad_Opcode }, | |
592a252b | 5347 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
5348 | }, |
5349 | ||
592a252b | 5350 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 5351 | { |
592d1631 L |
5352 | { Bad_Opcode }, |
5353 | { Bad_Opcode }, | |
592a252b L |
5354 | { VEX_W_TABLE (VEX_W_0FD0_P_2) }, |
5355 | { VEX_W_TABLE (VEX_W_0FD0_P_3) }, | |
c0f3af97 L |
5356 | }, |
5357 | ||
592a252b | 5358 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 5359 | { |
592d1631 L |
5360 | { Bad_Opcode }, |
5361 | { Bad_Opcode }, | |
6c30d220 | 5362 | { VEX_W_TABLE (VEX_W_0FD1_P_2) }, |
c0f3af97 L |
5363 | }, |
5364 | ||
592a252b | 5365 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 5366 | { |
592d1631 L |
5367 | { Bad_Opcode }, |
5368 | { Bad_Opcode }, | |
6c30d220 | 5369 | { VEX_W_TABLE (VEX_W_0FD2_P_2) }, |
c0f3af97 L |
5370 | }, |
5371 | ||
592a252b | 5372 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 5373 | { |
592d1631 L |
5374 | { Bad_Opcode }, |
5375 | { Bad_Opcode }, | |
6c30d220 | 5376 | { VEX_W_TABLE (VEX_W_0FD3_P_2) }, |
c0f3af97 L |
5377 | }, |
5378 | ||
592a252b | 5379 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 5380 | { |
592d1631 L |
5381 | { Bad_Opcode }, |
5382 | { Bad_Opcode }, | |
6c30d220 | 5383 | { VEX_W_TABLE (VEX_W_0FD4_P_2) }, |
c0f3af97 L |
5384 | }, |
5385 | ||
592a252b | 5386 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 5387 | { |
592d1631 L |
5388 | { Bad_Opcode }, |
5389 | { Bad_Opcode }, | |
6c30d220 | 5390 | { VEX_W_TABLE (VEX_W_0FD5_P_2) }, |
c0f3af97 L |
5391 | }, |
5392 | ||
592a252b | 5393 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 5394 | { |
592d1631 L |
5395 | { Bad_Opcode }, |
5396 | { Bad_Opcode }, | |
592a252b | 5397 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
5398 | }, |
5399 | ||
592a252b | 5400 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 5401 | { |
592d1631 L |
5402 | { Bad_Opcode }, |
5403 | { Bad_Opcode }, | |
592a252b | 5404 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
5405 | }, |
5406 | ||
592a252b | 5407 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 5408 | { |
592d1631 L |
5409 | { Bad_Opcode }, |
5410 | { Bad_Opcode }, | |
6c30d220 | 5411 | { VEX_W_TABLE (VEX_W_0FD8_P_2) }, |
c0f3af97 L |
5412 | }, |
5413 | ||
592a252b | 5414 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 5415 | { |
592d1631 L |
5416 | { Bad_Opcode }, |
5417 | { Bad_Opcode }, | |
6c30d220 | 5418 | { VEX_W_TABLE (VEX_W_0FD9_P_2) }, |
c0f3af97 L |
5419 | }, |
5420 | ||
592a252b | 5421 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 5422 | { |
592d1631 L |
5423 | { Bad_Opcode }, |
5424 | { Bad_Opcode }, | |
6c30d220 | 5425 | { VEX_W_TABLE (VEX_W_0FDA_P_2) }, |
c0f3af97 L |
5426 | }, |
5427 | ||
592a252b | 5428 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 5429 | { |
592d1631 L |
5430 | { Bad_Opcode }, |
5431 | { Bad_Opcode }, | |
6c30d220 | 5432 | { VEX_W_TABLE (VEX_W_0FDB_P_2) }, |
c0f3af97 L |
5433 | }, |
5434 | ||
592a252b | 5435 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 5436 | { |
592d1631 L |
5437 | { Bad_Opcode }, |
5438 | { Bad_Opcode }, | |
6c30d220 | 5439 | { VEX_W_TABLE (VEX_W_0FDC_P_2) }, |
c0f3af97 L |
5440 | }, |
5441 | ||
592a252b | 5442 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 5443 | { |
592d1631 L |
5444 | { Bad_Opcode }, |
5445 | { Bad_Opcode }, | |
6c30d220 | 5446 | { VEX_W_TABLE (VEX_W_0FDD_P_2) }, |
c0f3af97 L |
5447 | }, |
5448 | ||
592a252b | 5449 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 5450 | { |
592d1631 L |
5451 | { Bad_Opcode }, |
5452 | { Bad_Opcode }, | |
6c30d220 | 5453 | { VEX_W_TABLE (VEX_W_0FDE_P_2) }, |
c0f3af97 L |
5454 | }, |
5455 | ||
592a252b | 5456 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 5457 | { |
592d1631 L |
5458 | { Bad_Opcode }, |
5459 | { Bad_Opcode }, | |
6c30d220 | 5460 | { VEX_W_TABLE (VEX_W_0FDF_P_2) }, |
c0f3af97 L |
5461 | }, |
5462 | ||
592a252b | 5463 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 5464 | { |
592d1631 L |
5465 | { Bad_Opcode }, |
5466 | { Bad_Opcode }, | |
6c30d220 | 5467 | { VEX_W_TABLE (VEX_W_0FE0_P_2) }, |
c0f3af97 L |
5468 | }, |
5469 | ||
592a252b | 5470 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 5471 | { |
592d1631 L |
5472 | { Bad_Opcode }, |
5473 | { Bad_Opcode }, | |
6c30d220 | 5474 | { VEX_W_TABLE (VEX_W_0FE1_P_2) }, |
c0f3af97 L |
5475 | }, |
5476 | ||
592a252b | 5477 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 5478 | { |
592d1631 L |
5479 | { Bad_Opcode }, |
5480 | { Bad_Opcode }, | |
6c30d220 | 5481 | { VEX_W_TABLE (VEX_W_0FE2_P_2) }, |
c0f3af97 L |
5482 | }, |
5483 | ||
592a252b | 5484 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 5485 | { |
592d1631 L |
5486 | { Bad_Opcode }, |
5487 | { Bad_Opcode }, | |
6c30d220 | 5488 | { VEX_W_TABLE (VEX_W_0FE3_P_2) }, |
c0f3af97 L |
5489 | }, |
5490 | ||
592a252b | 5491 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 5492 | { |
592d1631 L |
5493 | { Bad_Opcode }, |
5494 | { Bad_Opcode }, | |
6c30d220 | 5495 | { VEX_W_TABLE (VEX_W_0FE4_P_2) }, |
c0f3af97 L |
5496 | }, |
5497 | ||
592a252b | 5498 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 5499 | { |
592d1631 L |
5500 | { Bad_Opcode }, |
5501 | { Bad_Opcode }, | |
6c30d220 | 5502 | { VEX_W_TABLE (VEX_W_0FE5_P_2) }, |
c0f3af97 L |
5503 | }, |
5504 | ||
592a252b | 5505 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 5506 | { |
592d1631 | 5507 | { Bad_Opcode }, |
592a252b L |
5508 | { VEX_W_TABLE (VEX_W_0FE6_P_1) }, |
5509 | { VEX_W_TABLE (VEX_W_0FE6_P_2) }, | |
5510 | { VEX_W_TABLE (VEX_W_0FE6_P_3) }, | |
c0f3af97 L |
5511 | }, |
5512 | ||
592a252b | 5513 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5514 | { |
592d1631 L |
5515 | { Bad_Opcode }, |
5516 | { Bad_Opcode }, | |
592a252b | 5517 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5518 | }, |
5519 | ||
592a252b | 5520 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5521 | { |
592d1631 L |
5522 | { Bad_Opcode }, |
5523 | { Bad_Opcode }, | |
6c30d220 | 5524 | { VEX_W_TABLE (VEX_W_0FE8_P_2) }, |
c0f3af97 L |
5525 | }, |
5526 | ||
592a252b | 5527 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5528 | { |
592d1631 L |
5529 | { Bad_Opcode }, |
5530 | { Bad_Opcode }, | |
6c30d220 | 5531 | { VEX_W_TABLE (VEX_W_0FE9_P_2) }, |
c0f3af97 L |
5532 | }, |
5533 | ||
592a252b | 5534 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5535 | { |
592d1631 L |
5536 | { Bad_Opcode }, |
5537 | { Bad_Opcode }, | |
6c30d220 | 5538 | { VEX_W_TABLE (VEX_W_0FEA_P_2) }, |
c0f3af97 L |
5539 | }, |
5540 | ||
592a252b | 5541 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5542 | { |
592d1631 L |
5543 | { Bad_Opcode }, |
5544 | { Bad_Opcode }, | |
6c30d220 | 5545 | { VEX_W_TABLE (VEX_W_0FEB_P_2) }, |
c0f3af97 L |
5546 | }, |
5547 | ||
592a252b | 5548 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5549 | { |
592d1631 L |
5550 | { Bad_Opcode }, |
5551 | { Bad_Opcode }, | |
6c30d220 | 5552 | { VEX_W_TABLE (VEX_W_0FEC_P_2) }, |
c0f3af97 L |
5553 | }, |
5554 | ||
592a252b | 5555 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5556 | { |
592d1631 L |
5557 | { Bad_Opcode }, |
5558 | { Bad_Opcode }, | |
6c30d220 | 5559 | { VEX_W_TABLE (VEX_W_0FED_P_2) }, |
c0f3af97 L |
5560 | }, |
5561 | ||
592a252b | 5562 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5563 | { |
592d1631 L |
5564 | { Bad_Opcode }, |
5565 | { Bad_Opcode }, | |
6c30d220 | 5566 | { VEX_W_TABLE (VEX_W_0FEE_P_2) }, |
c0f3af97 L |
5567 | }, |
5568 | ||
592a252b | 5569 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5570 | { |
592d1631 L |
5571 | { Bad_Opcode }, |
5572 | { Bad_Opcode }, | |
6c30d220 | 5573 | { VEX_W_TABLE (VEX_W_0FEF_P_2) }, |
c0f3af97 L |
5574 | }, |
5575 | ||
592a252b | 5576 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5577 | { |
592d1631 L |
5578 | { Bad_Opcode }, |
5579 | { Bad_Opcode }, | |
5580 | { Bad_Opcode }, | |
592a252b | 5581 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5582 | }, |
5583 | ||
592a252b | 5584 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5585 | { |
592d1631 L |
5586 | { Bad_Opcode }, |
5587 | { Bad_Opcode }, | |
6c30d220 | 5588 | { VEX_W_TABLE (VEX_W_0FF1_P_2) }, |
c0f3af97 L |
5589 | }, |
5590 | ||
592a252b | 5591 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5592 | { |
592d1631 L |
5593 | { Bad_Opcode }, |
5594 | { Bad_Opcode }, | |
6c30d220 | 5595 | { VEX_W_TABLE (VEX_W_0FF2_P_2) }, |
c0f3af97 L |
5596 | }, |
5597 | ||
592a252b | 5598 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5599 | { |
592d1631 L |
5600 | { Bad_Opcode }, |
5601 | { Bad_Opcode }, | |
6c30d220 | 5602 | { VEX_W_TABLE (VEX_W_0FF3_P_2) }, |
c0f3af97 L |
5603 | }, |
5604 | ||
592a252b | 5605 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5606 | { |
592d1631 L |
5607 | { Bad_Opcode }, |
5608 | { Bad_Opcode }, | |
6c30d220 | 5609 | { VEX_W_TABLE (VEX_W_0FF4_P_2) }, |
c0f3af97 L |
5610 | }, |
5611 | ||
592a252b | 5612 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5613 | { |
592d1631 L |
5614 | { Bad_Opcode }, |
5615 | { Bad_Opcode }, | |
6c30d220 | 5616 | { VEX_W_TABLE (VEX_W_0FF5_P_2) }, |
c0f3af97 L |
5617 | }, |
5618 | ||
592a252b | 5619 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5620 | { |
592d1631 L |
5621 | { Bad_Opcode }, |
5622 | { Bad_Opcode }, | |
6c30d220 | 5623 | { VEX_W_TABLE (VEX_W_0FF6_P_2) }, |
c0f3af97 L |
5624 | }, |
5625 | ||
592a252b | 5626 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5627 | { |
592d1631 L |
5628 | { Bad_Opcode }, |
5629 | { Bad_Opcode }, | |
592a252b | 5630 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5631 | }, |
5632 | ||
592a252b | 5633 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5634 | { |
592d1631 L |
5635 | { Bad_Opcode }, |
5636 | { Bad_Opcode }, | |
6c30d220 | 5637 | { VEX_W_TABLE (VEX_W_0FF8_P_2) }, |
c0f3af97 L |
5638 | }, |
5639 | ||
592a252b | 5640 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5641 | { |
592d1631 L |
5642 | { Bad_Opcode }, |
5643 | { Bad_Opcode }, | |
6c30d220 | 5644 | { VEX_W_TABLE (VEX_W_0FF9_P_2) }, |
c0f3af97 L |
5645 | }, |
5646 | ||
592a252b | 5647 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5648 | { |
592d1631 L |
5649 | { Bad_Opcode }, |
5650 | { Bad_Opcode }, | |
6c30d220 | 5651 | { VEX_W_TABLE (VEX_W_0FFA_P_2) }, |
c0f3af97 L |
5652 | }, |
5653 | ||
592a252b | 5654 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5655 | { |
592d1631 L |
5656 | { Bad_Opcode }, |
5657 | { Bad_Opcode }, | |
6c30d220 | 5658 | { VEX_W_TABLE (VEX_W_0FFB_P_2) }, |
c0f3af97 L |
5659 | }, |
5660 | ||
592a252b | 5661 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5662 | { |
592d1631 L |
5663 | { Bad_Opcode }, |
5664 | { Bad_Opcode }, | |
6c30d220 | 5665 | { VEX_W_TABLE (VEX_W_0FFC_P_2) }, |
c0f3af97 L |
5666 | }, |
5667 | ||
592a252b | 5668 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5669 | { |
592d1631 L |
5670 | { Bad_Opcode }, |
5671 | { Bad_Opcode }, | |
6c30d220 | 5672 | { VEX_W_TABLE (VEX_W_0FFD_P_2) }, |
c0f3af97 L |
5673 | }, |
5674 | ||
592a252b | 5675 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5676 | { |
592d1631 L |
5677 | { Bad_Opcode }, |
5678 | { Bad_Opcode }, | |
6c30d220 | 5679 | { VEX_W_TABLE (VEX_W_0FFE_P_2) }, |
c0f3af97 L |
5680 | }, |
5681 | ||
592a252b | 5682 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5683 | { |
592d1631 L |
5684 | { Bad_Opcode }, |
5685 | { Bad_Opcode }, | |
6c30d220 | 5686 | { VEX_W_TABLE (VEX_W_0F3800_P_2) }, |
c0f3af97 L |
5687 | }, |
5688 | ||
592a252b | 5689 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5690 | { |
592d1631 L |
5691 | { Bad_Opcode }, |
5692 | { Bad_Opcode }, | |
6c30d220 | 5693 | { VEX_W_TABLE (VEX_W_0F3801_P_2) }, |
c0f3af97 L |
5694 | }, |
5695 | ||
592a252b | 5696 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5697 | { |
592d1631 L |
5698 | { Bad_Opcode }, |
5699 | { Bad_Opcode }, | |
6c30d220 | 5700 | { VEX_W_TABLE (VEX_W_0F3802_P_2) }, |
c0f3af97 L |
5701 | }, |
5702 | ||
592a252b | 5703 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5704 | { |
592d1631 L |
5705 | { Bad_Opcode }, |
5706 | { Bad_Opcode }, | |
6c30d220 | 5707 | { VEX_W_TABLE (VEX_W_0F3803_P_2) }, |
c0f3af97 L |
5708 | }, |
5709 | ||
592a252b | 5710 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5711 | { |
592d1631 L |
5712 | { Bad_Opcode }, |
5713 | { Bad_Opcode }, | |
6c30d220 | 5714 | { VEX_W_TABLE (VEX_W_0F3804_P_2) }, |
c0f3af97 L |
5715 | }, |
5716 | ||
592a252b | 5717 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5718 | { |
592d1631 L |
5719 | { Bad_Opcode }, |
5720 | { Bad_Opcode }, | |
6c30d220 | 5721 | { VEX_W_TABLE (VEX_W_0F3805_P_2) }, |
c0f3af97 L |
5722 | }, |
5723 | ||
592a252b | 5724 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5725 | { |
592d1631 L |
5726 | { Bad_Opcode }, |
5727 | { Bad_Opcode }, | |
6c30d220 | 5728 | { VEX_W_TABLE (VEX_W_0F3806_P_2) }, |
c0f3af97 L |
5729 | }, |
5730 | ||
592a252b | 5731 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5732 | { |
592d1631 L |
5733 | { Bad_Opcode }, |
5734 | { Bad_Opcode }, | |
6c30d220 | 5735 | { VEX_W_TABLE (VEX_W_0F3807_P_2) }, |
c0f3af97 L |
5736 | }, |
5737 | ||
592a252b | 5738 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5739 | { |
592d1631 L |
5740 | { Bad_Opcode }, |
5741 | { Bad_Opcode }, | |
6c30d220 | 5742 | { VEX_W_TABLE (VEX_W_0F3808_P_2) }, |
c0f3af97 L |
5743 | }, |
5744 | ||
592a252b | 5745 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5746 | { |
592d1631 L |
5747 | { Bad_Opcode }, |
5748 | { Bad_Opcode }, | |
6c30d220 | 5749 | { VEX_W_TABLE (VEX_W_0F3809_P_2) }, |
c0f3af97 L |
5750 | }, |
5751 | ||
592a252b | 5752 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5753 | { |
592d1631 L |
5754 | { Bad_Opcode }, |
5755 | { Bad_Opcode }, | |
6c30d220 | 5756 | { VEX_W_TABLE (VEX_W_0F380A_P_2) }, |
c0f3af97 L |
5757 | }, |
5758 | ||
592a252b | 5759 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5760 | { |
592d1631 L |
5761 | { Bad_Opcode }, |
5762 | { Bad_Opcode }, | |
6c30d220 | 5763 | { VEX_W_TABLE (VEX_W_0F380B_P_2) }, |
c0f3af97 L |
5764 | }, |
5765 | ||
592a252b | 5766 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5767 | { |
592d1631 L |
5768 | { Bad_Opcode }, |
5769 | { Bad_Opcode }, | |
592a252b | 5770 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5771 | }, |
5772 | ||
592a252b | 5773 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5774 | { |
592d1631 L |
5775 | { Bad_Opcode }, |
5776 | { Bad_Opcode }, | |
592a252b | 5777 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5778 | }, |
5779 | ||
592a252b | 5780 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5781 | { |
592d1631 L |
5782 | { Bad_Opcode }, |
5783 | { Bad_Opcode }, | |
592a252b | 5784 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5785 | }, |
5786 | ||
592a252b | 5787 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5788 | { |
592d1631 L |
5789 | { Bad_Opcode }, |
5790 | { Bad_Opcode }, | |
592a252b | 5791 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5792 | }, |
5793 | ||
592a252b | 5794 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5795 | { |
5796 | { Bad_Opcode }, | |
5797 | { Bad_Opcode }, | |
bf890a93 | 5798 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, |
c7b8aa3a L |
5799 | }, |
5800 | ||
6c30d220 L |
5801 | /* PREFIX_VEX_0F3816 */ |
5802 | { | |
5803 | { Bad_Opcode }, | |
5804 | { Bad_Opcode }, | |
5805 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5806 | }, | |
5807 | ||
592a252b | 5808 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5809 | { |
592d1631 L |
5810 | { Bad_Opcode }, |
5811 | { Bad_Opcode }, | |
592a252b | 5812 | { VEX_W_TABLE (VEX_W_0F3817_P_2) }, |
c0f3af97 L |
5813 | }, |
5814 | ||
592a252b | 5815 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5816 | { |
592d1631 L |
5817 | { Bad_Opcode }, |
5818 | { Bad_Opcode }, | |
6c30d220 | 5819 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5820 | }, |
5821 | ||
592a252b | 5822 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5823 | { |
592d1631 L |
5824 | { Bad_Opcode }, |
5825 | { Bad_Opcode }, | |
6c30d220 | 5826 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5827 | }, |
5828 | ||
592a252b | 5829 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5830 | { |
592d1631 L |
5831 | { Bad_Opcode }, |
5832 | { Bad_Opcode }, | |
592a252b | 5833 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5834 | }, |
5835 | ||
592a252b | 5836 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5837 | { |
592d1631 L |
5838 | { Bad_Opcode }, |
5839 | { Bad_Opcode }, | |
6c30d220 | 5840 | { VEX_W_TABLE (VEX_W_0F381C_P_2) }, |
c0f3af97 L |
5841 | }, |
5842 | ||
592a252b | 5843 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5844 | { |
592d1631 L |
5845 | { Bad_Opcode }, |
5846 | { Bad_Opcode }, | |
6c30d220 | 5847 | { VEX_W_TABLE (VEX_W_0F381D_P_2) }, |
c0f3af97 L |
5848 | }, |
5849 | ||
592a252b | 5850 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5851 | { |
592d1631 L |
5852 | { Bad_Opcode }, |
5853 | { Bad_Opcode }, | |
6c30d220 | 5854 | { VEX_W_TABLE (VEX_W_0F381E_P_2) }, |
c0f3af97 L |
5855 | }, |
5856 | ||
592a252b | 5857 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5858 | { |
592d1631 L |
5859 | { Bad_Opcode }, |
5860 | { Bad_Opcode }, | |
6c30d220 | 5861 | { VEX_W_TABLE (VEX_W_0F3820_P_2) }, |
c0f3af97 L |
5862 | }, |
5863 | ||
592a252b | 5864 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5865 | { |
592d1631 L |
5866 | { Bad_Opcode }, |
5867 | { Bad_Opcode }, | |
6c30d220 | 5868 | { VEX_W_TABLE (VEX_W_0F3821_P_2) }, |
c0f3af97 L |
5869 | }, |
5870 | ||
592a252b | 5871 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5872 | { |
592d1631 L |
5873 | { Bad_Opcode }, |
5874 | { Bad_Opcode }, | |
6c30d220 | 5875 | { VEX_W_TABLE (VEX_W_0F3822_P_2) }, |
c0f3af97 L |
5876 | }, |
5877 | ||
592a252b | 5878 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5879 | { |
592d1631 L |
5880 | { Bad_Opcode }, |
5881 | { Bad_Opcode }, | |
6c30d220 | 5882 | { VEX_W_TABLE (VEX_W_0F3823_P_2) }, |
c0f3af97 L |
5883 | }, |
5884 | ||
592a252b | 5885 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5886 | { |
592d1631 L |
5887 | { Bad_Opcode }, |
5888 | { Bad_Opcode }, | |
6c30d220 | 5889 | { VEX_W_TABLE (VEX_W_0F3824_P_2) }, |
c0f3af97 L |
5890 | }, |
5891 | ||
592a252b | 5892 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5893 | { |
592d1631 L |
5894 | { Bad_Opcode }, |
5895 | { Bad_Opcode }, | |
6c30d220 | 5896 | { VEX_W_TABLE (VEX_W_0F3825_P_2) }, |
c0f3af97 L |
5897 | }, |
5898 | ||
592a252b | 5899 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5900 | { |
592d1631 L |
5901 | { Bad_Opcode }, |
5902 | { Bad_Opcode }, | |
6c30d220 | 5903 | { VEX_W_TABLE (VEX_W_0F3828_P_2) }, |
c0f3af97 L |
5904 | }, |
5905 | ||
592a252b | 5906 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5907 | { |
592d1631 L |
5908 | { Bad_Opcode }, |
5909 | { Bad_Opcode }, | |
6c30d220 | 5910 | { VEX_W_TABLE (VEX_W_0F3829_P_2) }, |
c0f3af97 L |
5911 | }, |
5912 | ||
592a252b | 5913 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5914 | { |
592d1631 L |
5915 | { Bad_Opcode }, |
5916 | { Bad_Opcode }, | |
592a252b | 5917 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5918 | }, |
5919 | ||
592a252b | 5920 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5921 | { |
592d1631 L |
5922 | { Bad_Opcode }, |
5923 | { Bad_Opcode }, | |
6c30d220 | 5924 | { VEX_W_TABLE (VEX_W_0F382B_P_2) }, |
c0f3af97 L |
5925 | }, |
5926 | ||
592a252b | 5927 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5928 | { |
592d1631 L |
5929 | { Bad_Opcode }, |
5930 | { Bad_Opcode }, | |
592a252b | 5931 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5932 | }, |
5933 | ||
592a252b | 5934 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5935 | { |
592d1631 L |
5936 | { Bad_Opcode }, |
5937 | { Bad_Opcode }, | |
592a252b | 5938 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5939 | }, |
5940 | ||
592a252b | 5941 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5942 | { |
592d1631 L |
5943 | { Bad_Opcode }, |
5944 | { Bad_Opcode }, | |
592a252b | 5945 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5946 | }, |
5947 | ||
592a252b | 5948 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5949 | { |
592d1631 L |
5950 | { Bad_Opcode }, |
5951 | { Bad_Opcode }, | |
592a252b | 5952 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
5953 | }, |
5954 | ||
592a252b | 5955 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 5956 | { |
592d1631 L |
5957 | { Bad_Opcode }, |
5958 | { Bad_Opcode }, | |
6c30d220 | 5959 | { VEX_W_TABLE (VEX_W_0F3830_P_2) }, |
c0f3af97 L |
5960 | }, |
5961 | ||
592a252b | 5962 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 5963 | { |
592d1631 L |
5964 | { Bad_Opcode }, |
5965 | { Bad_Opcode }, | |
6c30d220 | 5966 | { VEX_W_TABLE (VEX_W_0F3831_P_2) }, |
c0f3af97 L |
5967 | }, |
5968 | ||
592a252b | 5969 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 5970 | { |
592d1631 L |
5971 | { Bad_Opcode }, |
5972 | { Bad_Opcode }, | |
6c30d220 | 5973 | { VEX_W_TABLE (VEX_W_0F3832_P_2) }, |
c0f3af97 L |
5974 | }, |
5975 | ||
592a252b | 5976 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 5977 | { |
592d1631 L |
5978 | { Bad_Opcode }, |
5979 | { Bad_Opcode }, | |
6c30d220 | 5980 | { VEX_W_TABLE (VEX_W_0F3833_P_2) }, |
c0f3af97 L |
5981 | }, |
5982 | ||
592a252b | 5983 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 5984 | { |
592d1631 L |
5985 | { Bad_Opcode }, |
5986 | { Bad_Opcode }, | |
6c30d220 | 5987 | { VEX_W_TABLE (VEX_W_0F3834_P_2) }, |
c0f3af97 L |
5988 | }, |
5989 | ||
592a252b | 5990 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 5991 | { |
592d1631 L |
5992 | { Bad_Opcode }, |
5993 | { Bad_Opcode }, | |
6c30d220 L |
5994 | { VEX_W_TABLE (VEX_W_0F3835_P_2) }, |
5995 | }, | |
5996 | ||
5997 | /* PREFIX_VEX_0F3836 */ | |
5998 | { | |
5999 | { Bad_Opcode }, | |
6000 | { Bad_Opcode }, | |
6001 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
6002 | }, |
6003 | ||
592a252b | 6004 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 6005 | { |
592d1631 L |
6006 | { Bad_Opcode }, |
6007 | { Bad_Opcode }, | |
6c30d220 | 6008 | { VEX_W_TABLE (VEX_W_0F3837_P_2) }, |
c0f3af97 L |
6009 | }, |
6010 | ||
592a252b | 6011 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 6012 | { |
592d1631 L |
6013 | { Bad_Opcode }, |
6014 | { Bad_Opcode }, | |
6c30d220 | 6015 | { VEX_W_TABLE (VEX_W_0F3838_P_2) }, |
c0f3af97 L |
6016 | }, |
6017 | ||
592a252b | 6018 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 6019 | { |
592d1631 L |
6020 | { Bad_Opcode }, |
6021 | { Bad_Opcode }, | |
6c30d220 | 6022 | { VEX_W_TABLE (VEX_W_0F3839_P_2) }, |
c0f3af97 L |
6023 | }, |
6024 | ||
592a252b | 6025 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 6026 | { |
592d1631 L |
6027 | { Bad_Opcode }, |
6028 | { Bad_Opcode }, | |
6c30d220 | 6029 | { VEX_W_TABLE (VEX_W_0F383A_P_2) }, |
c0f3af97 L |
6030 | }, |
6031 | ||
592a252b | 6032 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 6033 | { |
592d1631 L |
6034 | { Bad_Opcode }, |
6035 | { Bad_Opcode }, | |
6c30d220 | 6036 | { VEX_W_TABLE (VEX_W_0F383B_P_2) }, |
c0f3af97 L |
6037 | }, |
6038 | ||
592a252b | 6039 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 6040 | { |
592d1631 L |
6041 | { Bad_Opcode }, |
6042 | { Bad_Opcode }, | |
6c30d220 | 6043 | { VEX_W_TABLE (VEX_W_0F383C_P_2) }, |
c0f3af97 L |
6044 | }, |
6045 | ||
592a252b | 6046 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 6047 | { |
592d1631 L |
6048 | { Bad_Opcode }, |
6049 | { Bad_Opcode }, | |
6c30d220 | 6050 | { VEX_W_TABLE (VEX_W_0F383D_P_2) }, |
c0f3af97 L |
6051 | }, |
6052 | ||
592a252b | 6053 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 6054 | { |
592d1631 L |
6055 | { Bad_Opcode }, |
6056 | { Bad_Opcode }, | |
6c30d220 | 6057 | { VEX_W_TABLE (VEX_W_0F383E_P_2) }, |
c0f3af97 L |
6058 | }, |
6059 | ||
592a252b | 6060 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 6061 | { |
592d1631 L |
6062 | { Bad_Opcode }, |
6063 | { Bad_Opcode }, | |
6c30d220 | 6064 | { VEX_W_TABLE (VEX_W_0F383F_P_2) }, |
c0f3af97 L |
6065 | }, |
6066 | ||
592a252b | 6067 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 6068 | { |
592d1631 L |
6069 | { Bad_Opcode }, |
6070 | { Bad_Opcode }, | |
6c30d220 | 6071 | { VEX_W_TABLE (VEX_W_0F3840_P_2) }, |
c0f3af97 L |
6072 | }, |
6073 | ||
592a252b | 6074 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 6075 | { |
592d1631 L |
6076 | { Bad_Opcode }, |
6077 | { Bad_Opcode }, | |
592a252b | 6078 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
6079 | }, |
6080 | ||
6c30d220 L |
6081 | /* PREFIX_VEX_0F3845 */ |
6082 | { | |
6083 | { Bad_Opcode }, | |
6084 | { Bad_Opcode }, | |
bf890a93 | 6085 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
6086 | }, |
6087 | ||
6088 | /* PREFIX_VEX_0F3846 */ | |
6089 | { | |
6090 | { Bad_Opcode }, | |
6091 | { Bad_Opcode }, | |
6092 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
6093 | }, | |
6094 | ||
6095 | /* PREFIX_VEX_0F3847 */ | |
6096 | { | |
6097 | { Bad_Opcode }, | |
6098 | { Bad_Opcode }, | |
bf890a93 | 6099 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
6100 | }, |
6101 | ||
6102 | /* PREFIX_VEX_0F3858 */ | |
6103 | { | |
6104 | { Bad_Opcode }, | |
6105 | { Bad_Opcode }, | |
6106 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
6107 | }, | |
6108 | ||
6109 | /* PREFIX_VEX_0F3859 */ | |
6110 | { | |
6111 | { Bad_Opcode }, | |
6112 | { Bad_Opcode }, | |
6113 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
6114 | }, | |
6115 | ||
6116 | /* PREFIX_VEX_0F385A */ | |
6117 | { | |
6118 | { Bad_Opcode }, | |
6119 | { Bad_Opcode }, | |
6120 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
6121 | }, | |
6122 | ||
6123 | /* PREFIX_VEX_0F3878 */ | |
6124 | { | |
6125 | { Bad_Opcode }, | |
6126 | { Bad_Opcode }, | |
6127 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
6128 | }, | |
6129 | ||
6130 | /* PREFIX_VEX_0F3879 */ | |
6131 | { | |
6132 | { Bad_Opcode }, | |
6133 | { Bad_Opcode }, | |
6134 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
6135 | }, | |
6136 | ||
6137 | /* PREFIX_VEX_0F388C */ | |
6138 | { | |
6139 | { Bad_Opcode }, | |
6140 | { Bad_Opcode }, | |
f7002f42 | 6141 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
6142 | }, |
6143 | ||
6144 | /* PREFIX_VEX_0F388E */ | |
6145 | { | |
6146 | { Bad_Opcode }, | |
6147 | { Bad_Opcode }, | |
f7002f42 | 6148 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
6149 | }, |
6150 | ||
6151 | /* PREFIX_VEX_0F3890 */ | |
6152 | { | |
6153 | { Bad_Opcode }, | |
6154 | { Bad_Opcode }, | |
bf890a93 | 6155 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
6156 | }, |
6157 | ||
6158 | /* PREFIX_VEX_0F3891 */ | |
6159 | { | |
6160 | { Bad_Opcode }, | |
6161 | { Bad_Opcode }, | |
bf890a93 | 6162 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6163 | }, |
6164 | ||
6165 | /* PREFIX_VEX_0F3892 */ | |
6166 | { | |
6167 | { Bad_Opcode }, | |
6168 | { Bad_Opcode }, | |
bf890a93 | 6169 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
6170 | }, |
6171 | ||
6172 | /* PREFIX_VEX_0F3893 */ | |
6173 | { | |
6174 | { Bad_Opcode }, | |
6175 | { Bad_Opcode }, | |
bf890a93 | 6176 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6177 | }, |
6178 | ||
592a252b | 6179 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 6180 | { |
592d1631 L |
6181 | { Bad_Opcode }, |
6182 | { Bad_Opcode }, | |
bf890a93 | 6183 | { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6184 | }, |
6185 | ||
592a252b | 6186 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 6187 | { |
592d1631 L |
6188 | { Bad_Opcode }, |
6189 | { Bad_Opcode }, | |
bf890a93 | 6190 | { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6191 | }, |
6192 | ||
592a252b | 6193 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 6194 | { |
592d1631 L |
6195 | { Bad_Opcode }, |
6196 | { Bad_Opcode }, | |
bf890a93 | 6197 | { "vfmadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6198 | }, |
6199 | ||
592a252b | 6200 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 6201 | { |
592d1631 L |
6202 | { Bad_Opcode }, |
6203 | { Bad_Opcode }, | |
bf890a93 | 6204 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
a5ff0eb2 L |
6205 | }, |
6206 | ||
592a252b | 6207 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 6208 | { |
592d1631 L |
6209 | { Bad_Opcode }, |
6210 | { Bad_Opcode }, | |
bf890a93 | 6211 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6212 | }, |
6213 | ||
592a252b | 6214 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 6215 | { |
592d1631 L |
6216 | { Bad_Opcode }, |
6217 | { Bad_Opcode }, | |
bf890a93 | 6218 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6219 | }, |
6220 | ||
592a252b | 6221 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 6222 | { |
592d1631 L |
6223 | { Bad_Opcode }, |
6224 | { Bad_Opcode }, | |
bf890a93 | 6225 | { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6226 | }, |
6227 | ||
592a252b | 6228 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 6229 | { |
592d1631 L |
6230 | { Bad_Opcode }, |
6231 | { Bad_Opcode }, | |
bf890a93 | 6232 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6233 | }, |
6234 | ||
592a252b | 6235 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 6236 | { |
592d1631 L |
6237 | { Bad_Opcode }, |
6238 | { Bad_Opcode }, | |
bf890a93 | 6239 | { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6240 | }, |
6241 | ||
592a252b | 6242 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 6243 | { |
592d1631 L |
6244 | { Bad_Opcode }, |
6245 | { Bad_Opcode }, | |
bf890a93 | 6246 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6247 | }, |
6248 | ||
592a252b | 6249 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 6250 | { |
592d1631 L |
6251 | { Bad_Opcode }, |
6252 | { Bad_Opcode }, | |
bf890a93 | 6253 | { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 }, |
592d1631 | 6254 | { Bad_Opcode }, |
c0f3af97 L |
6255 | }, |
6256 | ||
592a252b | 6257 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 6258 | { |
592d1631 L |
6259 | { Bad_Opcode }, |
6260 | { Bad_Opcode }, | |
bf890a93 | 6261 | { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6262 | }, |
6263 | ||
592a252b | 6264 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 6265 | { |
592d1631 L |
6266 | { Bad_Opcode }, |
6267 | { Bad_Opcode }, | |
bf890a93 | 6268 | { "vfmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6269 | }, |
6270 | ||
592a252b | 6271 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 6272 | { |
592d1631 L |
6273 | { Bad_Opcode }, |
6274 | { Bad_Opcode }, | |
bf890a93 | 6275 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6276 | }, |
6277 | ||
592a252b | 6278 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 6279 | { |
592d1631 L |
6280 | { Bad_Opcode }, |
6281 | { Bad_Opcode }, | |
bf890a93 | 6282 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6283 | }, |
6284 | ||
592a252b | 6285 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 6286 | { |
592d1631 L |
6287 | { Bad_Opcode }, |
6288 | { Bad_Opcode }, | |
bf890a93 | 6289 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6290 | }, |
6291 | ||
592a252b | 6292 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 6293 | { |
592d1631 L |
6294 | { Bad_Opcode }, |
6295 | { Bad_Opcode }, | |
bf890a93 | 6296 | { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6297 | }, |
6298 | ||
592a252b | 6299 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 6300 | { |
592d1631 L |
6301 | { Bad_Opcode }, |
6302 | { Bad_Opcode }, | |
bf890a93 | 6303 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6304 | }, |
6305 | ||
592a252b | 6306 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 6307 | { |
592d1631 L |
6308 | { Bad_Opcode }, |
6309 | { Bad_Opcode }, | |
bf890a93 | 6310 | { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6311 | }, |
6312 | ||
592a252b | 6313 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 6314 | { |
592d1631 L |
6315 | { Bad_Opcode }, |
6316 | { Bad_Opcode }, | |
bf890a93 | 6317 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6318 | }, |
6319 | ||
592a252b | 6320 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 6321 | { |
592d1631 L |
6322 | { Bad_Opcode }, |
6323 | { Bad_Opcode }, | |
bf890a93 | 6324 | { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6325 | }, |
6326 | ||
592a252b | 6327 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 6328 | { |
592d1631 L |
6329 | { Bad_Opcode }, |
6330 | { Bad_Opcode }, | |
bf890a93 | 6331 | { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6332 | }, |
6333 | ||
592a252b | 6334 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 6335 | { |
592d1631 L |
6336 | { Bad_Opcode }, |
6337 | { Bad_Opcode }, | |
bf890a93 | 6338 | { "vfmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6339 | }, |
6340 | ||
592a252b | 6341 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 6342 | { |
592d1631 L |
6343 | { Bad_Opcode }, |
6344 | { Bad_Opcode }, | |
bf890a93 | 6345 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6346 | }, |
6347 | ||
592a252b | 6348 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 6349 | { |
592d1631 L |
6350 | { Bad_Opcode }, |
6351 | { Bad_Opcode }, | |
bf890a93 | 6352 | { "vfmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6353 | }, |
6354 | ||
592a252b | 6355 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 6356 | { |
592d1631 L |
6357 | { Bad_Opcode }, |
6358 | { Bad_Opcode }, | |
bf890a93 | 6359 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6360 | }, |
6361 | ||
592a252b | 6362 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 6363 | { |
592d1631 L |
6364 | { Bad_Opcode }, |
6365 | { Bad_Opcode }, | |
bf890a93 | 6366 | { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6367 | }, |
6368 | ||
592a252b | 6369 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 6370 | { |
592d1631 L |
6371 | { Bad_Opcode }, |
6372 | { Bad_Opcode }, | |
bf890a93 | 6373 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6374 | }, |
6375 | ||
592a252b | 6376 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 6377 | { |
592d1631 L |
6378 | { Bad_Opcode }, |
6379 | { Bad_Opcode }, | |
bf890a93 | 6380 | { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6381 | }, |
6382 | ||
592a252b | 6383 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 6384 | { |
592d1631 L |
6385 | { Bad_Opcode }, |
6386 | { Bad_Opcode }, | |
bf890a93 | 6387 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6388 | }, |
6389 | ||
48521003 IT |
6390 | /* PREFIX_VEX_0F38CF */ |
6391 | { | |
6392 | { Bad_Opcode }, | |
6393 | { Bad_Opcode }, | |
6394 | { VEX_W_TABLE (VEX_W_0F38CF_P_2) }, | |
6395 | }, | |
6396 | ||
592a252b | 6397 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 6398 | { |
592d1631 L |
6399 | { Bad_Opcode }, |
6400 | { Bad_Opcode }, | |
592a252b | 6401 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
6402 | }, |
6403 | ||
592a252b | 6404 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 6405 | { |
592d1631 L |
6406 | { Bad_Opcode }, |
6407 | { Bad_Opcode }, | |
8dcf1fad | 6408 | { "vaesenc", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6409 | }, |
6410 | ||
592a252b | 6411 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 6412 | { |
592d1631 L |
6413 | { Bad_Opcode }, |
6414 | { Bad_Opcode }, | |
8dcf1fad | 6415 | { "vaesenclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6416 | }, |
6417 | ||
592a252b | 6418 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 6419 | { |
592d1631 L |
6420 | { Bad_Opcode }, |
6421 | { Bad_Opcode }, | |
8dcf1fad | 6422 | { "vaesdec", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6423 | }, |
6424 | ||
592a252b | 6425 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 6426 | { |
592d1631 L |
6427 | { Bad_Opcode }, |
6428 | { Bad_Opcode }, | |
8dcf1fad | 6429 | { "vaesdeclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6430 | }, |
6431 | ||
f12dc422 L |
6432 | /* PREFIX_VEX_0F38F2 */ |
6433 | { | |
6434 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
6435 | }, | |
6436 | ||
6437 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
6438 | { | |
6439 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
6440 | }, | |
6441 | ||
6442 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
6443 | { | |
6444 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
6445 | }, | |
6446 | ||
6447 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
6448 | { | |
6449 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
6450 | }, | |
6451 | ||
6c30d220 L |
6452 | /* PREFIX_VEX_0F38F5 */ |
6453 | { | |
6454 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
6455 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
6456 | { Bad_Opcode }, | |
6457 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
6458 | }, | |
6459 | ||
6460 | /* PREFIX_VEX_0F38F6 */ | |
6461 | { | |
6462 | { Bad_Opcode }, | |
6463 | { Bad_Opcode }, | |
6464 | { Bad_Opcode }, | |
6465 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
6466 | }, | |
6467 | ||
f12dc422 L |
6468 | /* PREFIX_VEX_0F38F7 */ |
6469 | { | |
6470 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
6471 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6472 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
6473 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
6474 | }, | |
6475 | ||
6476 | /* PREFIX_VEX_0F3A00 */ | |
6477 | { | |
6478 | { Bad_Opcode }, | |
6479 | { Bad_Opcode }, | |
6480 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
6481 | }, | |
6482 | ||
6483 | /* PREFIX_VEX_0F3A01 */ | |
6484 | { | |
6485 | { Bad_Opcode }, | |
6486 | { Bad_Opcode }, | |
6487 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
6488 | }, | |
6489 | ||
6490 | /* PREFIX_VEX_0F3A02 */ | |
6491 | { | |
6492 | { Bad_Opcode }, | |
6493 | { Bad_Opcode }, | |
6494 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
6495 | }, |
6496 | ||
592a252b | 6497 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 6498 | { |
592d1631 L |
6499 | { Bad_Opcode }, |
6500 | { Bad_Opcode }, | |
592a252b | 6501 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
6502 | }, |
6503 | ||
592a252b | 6504 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 6505 | { |
592d1631 L |
6506 | { Bad_Opcode }, |
6507 | { Bad_Opcode }, | |
592a252b | 6508 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
6509 | }, |
6510 | ||
592a252b | 6511 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 6512 | { |
592d1631 L |
6513 | { Bad_Opcode }, |
6514 | { Bad_Opcode }, | |
592a252b | 6515 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
6516 | }, |
6517 | ||
592a252b | 6518 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6519 | { |
592d1631 L |
6520 | { Bad_Opcode }, |
6521 | { Bad_Opcode }, | |
592a252b | 6522 | { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, |
c0f3af97 L |
6523 | }, |
6524 | ||
592a252b | 6525 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6526 | { |
592d1631 L |
6527 | { Bad_Opcode }, |
6528 | { Bad_Opcode }, | |
592a252b | 6529 | { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, |
c0f3af97 L |
6530 | }, |
6531 | ||
592a252b | 6532 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6533 | { |
592d1631 L |
6534 | { Bad_Opcode }, |
6535 | { Bad_Opcode }, | |
592a252b | 6536 | { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, |
0bfee649 L |
6537 | }, |
6538 | ||
592a252b | 6539 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6540 | { |
592d1631 L |
6541 | { Bad_Opcode }, |
6542 | { Bad_Opcode }, | |
592a252b | 6543 | { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, |
0bfee649 L |
6544 | }, |
6545 | ||
592a252b | 6546 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6547 | { |
592d1631 L |
6548 | { Bad_Opcode }, |
6549 | { Bad_Opcode }, | |
592a252b | 6550 | { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, |
0bfee649 L |
6551 | }, |
6552 | ||
592a252b | 6553 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6554 | { |
592d1631 L |
6555 | { Bad_Opcode }, |
6556 | { Bad_Opcode }, | |
592a252b | 6557 | { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, |
c0f3af97 L |
6558 | }, |
6559 | ||
592a252b | 6560 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6561 | { |
592d1631 L |
6562 | { Bad_Opcode }, |
6563 | { Bad_Opcode }, | |
6c30d220 | 6564 | { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, |
0bfee649 L |
6565 | }, |
6566 | ||
592a252b | 6567 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6568 | { |
592d1631 L |
6569 | { Bad_Opcode }, |
6570 | { Bad_Opcode }, | |
6c30d220 | 6571 | { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, |
0bfee649 L |
6572 | }, |
6573 | ||
592a252b | 6574 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6575 | { |
592d1631 L |
6576 | { Bad_Opcode }, |
6577 | { Bad_Opcode }, | |
592a252b | 6578 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6579 | }, |
6580 | ||
592a252b | 6581 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6582 | { |
592d1631 L |
6583 | { Bad_Opcode }, |
6584 | { Bad_Opcode }, | |
592a252b | 6585 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6586 | }, |
6587 | ||
592a252b | 6588 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6589 | { |
592d1631 L |
6590 | { Bad_Opcode }, |
6591 | { Bad_Opcode }, | |
592a252b | 6592 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6593 | }, |
6594 | ||
592a252b | 6595 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6596 | { |
592d1631 L |
6597 | { Bad_Opcode }, |
6598 | { Bad_Opcode }, | |
592a252b | 6599 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6600 | }, |
6601 | ||
592a252b | 6602 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6603 | { |
592d1631 L |
6604 | { Bad_Opcode }, |
6605 | { Bad_Opcode }, | |
592a252b | 6606 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6607 | }, |
6608 | ||
592a252b | 6609 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6610 | { |
592d1631 L |
6611 | { Bad_Opcode }, |
6612 | { Bad_Opcode }, | |
592a252b | 6613 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6614 | }, |
6615 | ||
592a252b | 6616 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6617 | { |
6618 | { Bad_Opcode }, | |
6619 | { Bad_Opcode }, | |
bf890a93 | 6620 | { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 }, |
c7b8aa3a L |
6621 | }, |
6622 | ||
592a252b | 6623 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6624 | { |
592d1631 L |
6625 | { Bad_Opcode }, |
6626 | { Bad_Opcode }, | |
592a252b | 6627 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6628 | }, |
6629 | ||
592a252b | 6630 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6631 | { |
592d1631 L |
6632 | { Bad_Opcode }, |
6633 | { Bad_Opcode }, | |
592a252b | 6634 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6635 | }, |
6636 | ||
592a252b | 6637 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6638 | { |
592d1631 L |
6639 | { Bad_Opcode }, |
6640 | { Bad_Opcode }, | |
592a252b | 6641 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6642 | }, |
6643 | ||
43234a1e L |
6644 | /* PREFIX_VEX_0F3A30 */ |
6645 | { | |
6646 | { Bad_Opcode }, | |
6647 | { Bad_Opcode }, | |
6648 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6649 | }, | |
6650 | ||
1ba585e8 IT |
6651 | /* PREFIX_VEX_0F3A31 */ |
6652 | { | |
6653 | { Bad_Opcode }, | |
6654 | { Bad_Opcode }, | |
6655 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, | |
6656 | }, | |
6657 | ||
43234a1e L |
6658 | /* PREFIX_VEX_0F3A32 */ |
6659 | { | |
6660 | { Bad_Opcode }, | |
6661 | { Bad_Opcode }, | |
6662 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6663 | }, | |
6664 | ||
1ba585e8 IT |
6665 | /* PREFIX_VEX_0F3A33 */ |
6666 | { | |
6667 | { Bad_Opcode }, | |
6668 | { Bad_Opcode }, | |
6669 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, | |
6670 | }, | |
6671 | ||
6c30d220 L |
6672 | /* PREFIX_VEX_0F3A38 */ |
6673 | { | |
6674 | { Bad_Opcode }, | |
6675 | { Bad_Opcode }, | |
6676 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6677 | }, | |
6678 | ||
6679 | /* PREFIX_VEX_0F3A39 */ | |
6680 | { | |
6681 | { Bad_Opcode }, | |
6682 | { Bad_Opcode }, | |
6683 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6684 | }, | |
6685 | ||
592a252b | 6686 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6687 | { |
592d1631 L |
6688 | { Bad_Opcode }, |
6689 | { Bad_Opcode }, | |
592a252b | 6690 | { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, |
c0f3af97 L |
6691 | }, |
6692 | ||
592a252b | 6693 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6694 | { |
592d1631 L |
6695 | { Bad_Opcode }, |
6696 | { Bad_Opcode }, | |
592a252b | 6697 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6698 | }, |
6699 | ||
592a252b | 6700 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6701 | { |
592d1631 L |
6702 | { Bad_Opcode }, |
6703 | { Bad_Opcode }, | |
6c30d220 | 6704 | { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, |
c0f3af97 L |
6705 | }, |
6706 | ||
592a252b | 6707 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6708 | { |
592d1631 L |
6709 | { Bad_Opcode }, |
6710 | { Bad_Opcode }, | |
ff1982d5 | 6711 | { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 }, |
ce2f5b3c L |
6712 | }, |
6713 | ||
6c30d220 L |
6714 | /* PREFIX_VEX_0F3A46 */ |
6715 | { | |
6716 | { Bad_Opcode }, | |
6717 | { Bad_Opcode }, | |
6718 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6719 | }, | |
6720 | ||
592a252b | 6721 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6722 | { |
6723 | { Bad_Opcode }, | |
6724 | { Bad_Opcode }, | |
592a252b | 6725 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
6726 | }, |
6727 | ||
592a252b | 6728 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6729 | { |
6730 | { Bad_Opcode }, | |
6731 | { Bad_Opcode }, | |
592a252b | 6732 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
6733 | }, |
6734 | ||
592a252b | 6735 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6736 | { |
592d1631 L |
6737 | { Bad_Opcode }, |
6738 | { Bad_Opcode }, | |
592a252b | 6739 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6740 | }, |
6741 | ||
592a252b | 6742 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6743 | { |
592d1631 L |
6744 | { Bad_Opcode }, |
6745 | { Bad_Opcode }, | |
592a252b | 6746 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6747 | }, |
6748 | ||
592a252b | 6749 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6750 | { |
592d1631 L |
6751 | { Bad_Opcode }, |
6752 | { Bad_Opcode }, | |
6c30d220 | 6753 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6754 | }, |
6755 | ||
592a252b | 6756 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6757 | { |
592d1631 L |
6758 | { Bad_Opcode }, |
6759 | { Bad_Opcode }, | |
3a2430e0 | 6760 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6761 | }, |
6762 | ||
592a252b | 6763 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6764 | { |
592d1631 L |
6765 | { Bad_Opcode }, |
6766 | { Bad_Opcode }, | |
3a2430e0 | 6767 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6768 | }, |
6769 | ||
592a252b | 6770 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6771 | { |
592d1631 L |
6772 | { Bad_Opcode }, |
6773 | { Bad_Opcode }, | |
3a2430e0 | 6774 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6775 | }, |
6776 | ||
592a252b | 6777 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6778 | { |
592d1631 L |
6779 | { Bad_Opcode }, |
6780 | { Bad_Opcode }, | |
3a2430e0 | 6781 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6782 | }, |
6783 | ||
592a252b | 6784 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6785 | { |
592d1631 L |
6786 | { Bad_Opcode }, |
6787 | { Bad_Opcode }, | |
592a252b | 6788 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6789 | { Bad_Opcode }, |
c0f3af97 L |
6790 | }, |
6791 | ||
592a252b | 6792 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6793 | { |
592d1631 L |
6794 | { Bad_Opcode }, |
6795 | { Bad_Opcode }, | |
592a252b | 6796 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6797 | }, |
6798 | ||
592a252b | 6799 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6800 | { |
592d1631 L |
6801 | { Bad_Opcode }, |
6802 | { Bad_Opcode }, | |
592a252b | 6803 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6804 | }, |
6805 | ||
592a252b | 6806 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6807 | { |
592d1631 L |
6808 | { Bad_Opcode }, |
6809 | { Bad_Opcode }, | |
592a252b | 6810 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6811 | }, |
a5ff0eb2 | 6812 | |
592a252b | 6813 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6814 | { |
592d1631 L |
6815 | { Bad_Opcode }, |
6816 | { Bad_Opcode }, | |
3a2430e0 | 6817 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6818 | }, |
6819 | ||
592a252b | 6820 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6821 | { |
592d1631 L |
6822 | { Bad_Opcode }, |
6823 | { Bad_Opcode }, | |
3a2430e0 | 6824 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6825 | }, |
6826 | ||
592a252b | 6827 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6828 | { |
592d1631 L |
6829 | { Bad_Opcode }, |
6830 | { Bad_Opcode }, | |
592a252b | 6831 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
6832 | }, |
6833 | ||
592a252b | 6834 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6835 | { |
592d1631 L |
6836 | { Bad_Opcode }, |
6837 | { Bad_Opcode }, | |
592a252b | 6838 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
6839 | }, |
6840 | ||
592a252b | 6841 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6842 | { |
592d1631 L |
6843 | { Bad_Opcode }, |
6844 | { Bad_Opcode }, | |
3a2430e0 | 6845 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6846 | }, |
6847 | ||
592a252b | 6848 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6849 | { |
592d1631 L |
6850 | { Bad_Opcode }, |
6851 | { Bad_Opcode }, | |
3a2430e0 | 6852 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6853 | }, |
6854 | ||
592a252b | 6855 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6856 | { |
592d1631 L |
6857 | { Bad_Opcode }, |
6858 | { Bad_Opcode }, | |
592a252b | 6859 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
6860 | }, |
6861 | ||
592a252b | 6862 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6863 | { |
592d1631 L |
6864 | { Bad_Opcode }, |
6865 | { Bad_Opcode }, | |
592a252b | 6866 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
6867 | }, |
6868 | ||
592a252b | 6869 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6870 | { |
592d1631 L |
6871 | { Bad_Opcode }, |
6872 | { Bad_Opcode }, | |
3a2430e0 | 6873 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6874 | }, |
6875 | ||
592a252b | 6876 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6877 | { |
592d1631 L |
6878 | { Bad_Opcode }, |
6879 | { Bad_Opcode }, | |
3a2430e0 | 6880 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6881 | }, |
6882 | ||
592a252b | 6883 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6884 | { |
592d1631 L |
6885 | { Bad_Opcode }, |
6886 | { Bad_Opcode }, | |
592a252b | 6887 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
6888 | }, |
6889 | ||
592a252b | 6890 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6891 | { |
592d1631 L |
6892 | { Bad_Opcode }, |
6893 | { Bad_Opcode }, | |
592a252b | 6894 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
6895 | }, |
6896 | ||
592a252b | 6897 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6898 | { |
592d1631 L |
6899 | { Bad_Opcode }, |
6900 | { Bad_Opcode }, | |
3a2430e0 | 6901 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 6902 | { Bad_Opcode }, |
922d8de8 DR |
6903 | }, |
6904 | ||
592a252b | 6905 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6906 | { |
592d1631 L |
6907 | { Bad_Opcode }, |
6908 | { Bad_Opcode }, | |
3a2430e0 | 6909 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6910 | }, |
6911 | ||
592a252b | 6912 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6913 | { |
592d1631 L |
6914 | { Bad_Opcode }, |
6915 | { Bad_Opcode }, | |
592a252b | 6916 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
6917 | }, |
6918 | ||
592a252b | 6919 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6920 | { |
592d1631 L |
6921 | { Bad_Opcode }, |
6922 | { Bad_Opcode }, | |
592a252b | 6923 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
6924 | }, |
6925 | ||
48521003 IT |
6926 | /* PREFIX_VEX_0F3ACE */ |
6927 | { | |
6928 | { Bad_Opcode }, | |
6929 | { Bad_Opcode }, | |
6930 | { VEX_W_TABLE (VEX_W_0F3ACE_P_2) }, | |
6931 | }, | |
6932 | ||
6933 | /* PREFIX_VEX_0F3ACF */ | |
6934 | { | |
6935 | { Bad_Opcode }, | |
6936 | { Bad_Opcode }, | |
6937 | { VEX_W_TABLE (VEX_W_0F3ACF_P_2) }, | |
6938 | }, | |
6939 | ||
592a252b | 6940 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6941 | { |
592d1631 L |
6942 | { Bad_Opcode }, |
6943 | { Bad_Opcode }, | |
592a252b | 6944 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6945 | }, |
6c30d220 L |
6946 | |
6947 | /* PREFIX_VEX_0F3AF0 */ | |
6948 | { | |
6949 | { Bad_Opcode }, | |
6950 | { Bad_Opcode }, | |
6951 | { Bad_Opcode }, | |
6952 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
6953 | }, | |
43234a1e L |
6954 | |
6955 | #define NEED_PREFIX_TABLE | |
6956 | #include "i386-dis-evex.h" | |
6957 | #undef NEED_PREFIX_TABLE | |
c0f3af97 L |
6958 | }; |
6959 | ||
6960 | static const struct dis386 x86_64_table[][2] = { | |
6961 | /* X86_64_06 */ | |
6962 | { | |
bf890a93 | 6963 | { "pushP", { es }, 0 }, |
c0f3af97 L |
6964 | }, |
6965 | ||
6966 | /* X86_64_07 */ | |
6967 | { | |
bf890a93 | 6968 | { "popP", { es }, 0 }, |
c0f3af97 L |
6969 | }, |
6970 | ||
6971 | /* X86_64_0D */ | |
6972 | { | |
bf890a93 | 6973 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
6974 | }, |
6975 | ||
6976 | /* X86_64_16 */ | |
6977 | { | |
bf890a93 | 6978 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
6979 | }, |
6980 | ||
6981 | /* X86_64_17 */ | |
6982 | { | |
bf890a93 | 6983 | { "popP", { ss }, 0 }, |
c0f3af97 L |
6984 | }, |
6985 | ||
6986 | /* X86_64_1E */ | |
6987 | { | |
bf890a93 | 6988 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
6989 | }, |
6990 | ||
6991 | /* X86_64_1F */ | |
6992 | { | |
bf890a93 | 6993 | { "popP", { ds }, 0 }, |
c0f3af97 L |
6994 | }, |
6995 | ||
6996 | /* X86_64_27 */ | |
6997 | { | |
bf890a93 | 6998 | { "daa", { XX }, 0 }, |
c0f3af97 L |
6999 | }, |
7000 | ||
7001 | /* X86_64_2F */ | |
7002 | { | |
bf890a93 | 7003 | { "das", { XX }, 0 }, |
c0f3af97 L |
7004 | }, |
7005 | ||
7006 | /* X86_64_37 */ | |
7007 | { | |
bf890a93 | 7008 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
7009 | }, |
7010 | ||
7011 | /* X86_64_3F */ | |
7012 | { | |
bf890a93 | 7013 | { "aas", { XX }, 0 }, |
c0f3af97 L |
7014 | }, |
7015 | ||
7016 | /* X86_64_60 */ | |
7017 | { | |
bf890a93 | 7018 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
7019 | }, |
7020 | ||
7021 | /* X86_64_61 */ | |
7022 | { | |
bf890a93 | 7023 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
7024 | }, |
7025 | ||
7026 | /* X86_64_62 */ | |
7027 | { | |
7028 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 7029 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
7030 | }, |
7031 | ||
7032 | /* X86_64_63 */ | |
7033 | { | |
bf890a93 IT |
7034 | { "arpl", { Ew, Gw }, 0 }, |
7035 | { "movs{lq|xd}", { Gv, Ed }, 0 }, | |
c0f3af97 L |
7036 | }, |
7037 | ||
7038 | /* X86_64_6D */ | |
7039 | { | |
bf890a93 IT |
7040 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
7041 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
7042 | }, |
7043 | ||
7044 | /* X86_64_6F */ | |
7045 | { | |
bf890a93 IT |
7046 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
7047 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
7048 | }, |
7049 | ||
d039fef3 | 7050 | /* X86_64_82 */ |
8b89fe14 | 7051 | { |
de194d85 | 7052 | /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ |
d039fef3 | 7053 | { REG_TABLE (REG_80) }, |
8b89fe14 L |
7054 | }, |
7055 | ||
c0f3af97 L |
7056 | /* X86_64_9A */ |
7057 | { | |
bf890a93 | 7058 | { "Jcall{T|}", { Ap }, 0 }, |
c0f3af97 L |
7059 | }, |
7060 | ||
7061 | /* X86_64_C4 */ | |
7062 | { | |
7063 | { MOD_TABLE (MOD_C4_32BIT) }, | |
7064 | { VEX_C4_TABLE (VEX_0F) }, | |
7065 | }, | |
7066 | ||
7067 | /* X86_64_C5 */ | |
7068 | { | |
7069 | { MOD_TABLE (MOD_C5_32BIT) }, | |
7070 | { VEX_C5_TABLE (VEX_0F) }, | |
7071 | }, | |
7072 | ||
7073 | /* X86_64_CE */ | |
7074 | { | |
bf890a93 | 7075 | { "into", { XX }, 0 }, |
c0f3af97 L |
7076 | }, |
7077 | ||
7078 | /* X86_64_D4 */ | |
7079 | { | |
bf890a93 | 7080 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
7081 | }, |
7082 | ||
7083 | /* X86_64_D5 */ | |
7084 | { | |
bf890a93 | 7085 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
7086 | }, |
7087 | ||
a72d2af2 L |
7088 | /* X86_64_E8 */ |
7089 | { | |
7090 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 7091 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
7092 | }, |
7093 | ||
7094 | /* X86_64_E9 */ | |
7095 | { | |
7096 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 7097 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
7098 | }, |
7099 | ||
c0f3af97 L |
7100 | /* X86_64_EA */ |
7101 | { | |
bf890a93 | 7102 | { "Jjmp{T|}", { Ap }, 0 }, |
c0f3af97 L |
7103 | }, |
7104 | ||
7105 | /* X86_64_0F01_REG_0 */ | |
7106 | { | |
bf890a93 IT |
7107 | { "sgdt{Q|IQ}", { M }, 0 }, |
7108 | { "sgdt", { M }, 0 }, | |
c0f3af97 L |
7109 | }, |
7110 | ||
7111 | /* X86_64_0F01_REG_1 */ | |
7112 | { | |
bf890a93 IT |
7113 | { "sidt{Q|IQ}", { M }, 0 }, |
7114 | { "sidt", { M }, 0 }, | |
c0f3af97 L |
7115 | }, |
7116 | ||
7117 | /* X86_64_0F01_REG_2 */ | |
7118 | { | |
bf890a93 IT |
7119 | { "lgdt{Q|Q}", { M }, 0 }, |
7120 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
7121 | }, |
7122 | ||
7123 | /* X86_64_0F01_REG_3 */ | |
7124 | { | |
bf890a93 IT |
7125 | { "lidt{Q|Q}", { M }, 0 }, |
7126 | { "lidt", { M }, 0 }, | |
c0f3af97 L |
7127 | }, |
7128 | }; | |
7129 | ||
7130 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
7131 | |
7132 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
7133 | { |
7134 | /* 00 */ | |
507bd325 L |
7135 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
7136 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
7137 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
7138 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
7139 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
7140 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
7141 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
7142 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 7143 | /* 08 */ |
507bd325 L |
7144 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
7145 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
7146 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
7147 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
7148 | { Bad_Opcode }, |
7149 | { Bad_Opcode }, | |
7150 | { Bad_Opcode }, | |
7151 | { Bad_Opcode }, | |
f88c9eb0 SP |
7152 | /* 10 */ |
7153 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
7154 | { Bad_Opcode }, |
7155 | { Bad_Opcode }, | |
7156 | { Bad_Opcode }, | |
f88c9eb0 SP |
7157 | { PREFIX_TABLE (PREFIX_0F3814) }, |
7158 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 7159 | { Bad_Opcode }, |
f88c9eb0 SP |
7160 | { PREFIX_TABLE (PREFIX_0F3817) }, |
7161 | /* 18 */ | |
592d1631 L |
7162 | { Bad_Opcode }, |
7163 | { Bad_Opcode }, | |
7164 | { Bad_Opcode }, | |
7165 | { Bad_Opcode }, | |
507bd325 L |
7166 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
7167 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
7168 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 7169 | { Bad_Opcode }, |
f88c9eb0 SP |
7170 | /* 20 */ |
7171 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
7172 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
7173 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
7174 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
7175 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
7176 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
7177 | { Bad_Opcode }, |
7178 | { Bad_Opcode }, | |
f88c9eb0 SP |
7179 | /* 28 */ |
7180 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
7181 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
7182 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
7183 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
7184 | { Bad_Opcode }, |
7185 | { Bad_Opcode }, | |
7186 | { Bad_Opcode }, | |
7187 | { Bad_Opcode }, | |
f88c9eb0 SP |
7188 | /* 30 */ |
7189 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
7190 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
7191 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
7192 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
7193 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
7194 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 7195 | { Bad_Opcode }, |
f88c9eb0 SP |
7196 | { PREFIX_TABLE (PREFIX_0F3837) }, |
7197 | /* 38 */ | |
7198 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
7199 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
7200 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
7201 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
7202 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
7203 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
7204 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
7205 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
7206 | /* 40 */ | |
7207 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
7208 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
7209 | { Bad_Opcode }, |
7210 | { Bad_Opcode }, | |
7211 | { Bad_Opcode }, | |
7212 | { Bad_Opcode }, | |
7213 | { Bad_Opcode }, | |
7214 | { Bad_Opcode }, | |
f88c9eb0 | 7215 | /* 48 */ |
592d1631 L |
7216 | { Bad_Opcode }, |
7217 | { Bad_Opcode }, | |
7218 | { Bad_Opcode }, | |
7219 | { Bad_Opcode }, | |
7220 | { Bad_Opcode }, | |
7221 | { Bad_Opcode }, | |
7222 | { Bad_Opcode }, | |
7223 | { Bad_Opcode }, | |
f88c9eb0 | 7224 | /* 50 */ |
592d1631 L |
7225 | { Bad_Opcode }, |
7226 | { Bad_Opcode }, | |
7227 | { Bad_Opcode }, | |
7228 | { Bad_Opcode }, | |
7229 | { Bad_Opcode }, | |
7230 | { Bad_Opcode }, | |
7231 | { Bad_Opcode }, | |
7232 | { Bad_Opcode }, | |
f88c9eb0 | 7233 | /* 58 */ |
592d1631 L |
7234 | { Bad_Opcode }, |
7235 | { Bad_Opcode }, | |
7236 | { Bad_Opcode }, | |
7237 | { Bad_Opcode }, | |
7238 | { Bad_Opcode }, | |
7239 | { Bad_Opcode }, | |
7240 | { Bad_Opcode }, | |
7241 | { Bad_Opcode }, | |
f88c9eb0 | 7242 | /* 60 */ |
592d1631 L |
7243 | { Bad_Opcode }, |
7244 | { Bad_Opcode }, | |
7245 | { Bad_Opcode }, | |
7246 | { Bad_Opcode }, | |
7247 | { Bad_Opcode }, | |
7248 | { Bad_Opcode }, | |
7249 | { Bad_Opcode }, | |
7250 | { Bad_Opcode }, | |
f88c9eb0 | 7251 | /* 68 */ |
592d1631 L |
7252 | { Bad_Opcode }, |
7253 | { Bad_Opcode }, | |
7254 | { Bad_Opcode }, | |
7255 | { Bad_Opcode }, | |
7256 | { Bad_Opcode }, | |
7257 | { Bad_Opcode }, | |
7258 | { Bad_Opcode }, | |
7259 | { Bad_Opcode }, | |
f88c9eb0 | 7260 | /* 70 */ |
592d1631 L |
7261 | { Bad_Opcode }, |
7262 | { Bad_Opcode }, | |
7263 | { Bad_Opcode }, | |
7264 | { Bad_Opcode }, | |
7265 | { Bad_Opcode }, | |
7266 | { Bad_Opcode }, | |
7267 | { Bad_Opcode }, | |
7268 | { Bad_Opcode }, | |
f88c9eb0 | 7269 | /* 78 */ |
592d1631 L |
7270 | { Bad_Opcode }, |
7271 | { Bad_Opcode }, | |
7272 | { Bad_Opcode }, | |
7273 | { Bad_Opcode }, | |
7274 | { Bad_Opcode }, | |
7275 | { Bad_Opcode }, | |
7276 | { Bad_Opcode }, | |
7277 | { Bad_Opcode }, | |
f88c9eb0 SP |
7278 | /* 80 */ |
7279 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
7280 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 7281 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
7282 | { Bad_Opcode }, |
7283 | { Bad_Opcode }, | |
7284 | { Bad_Opcode }, | |
7285 | { Bad_Opcode }, | |
7286 | { Bad_Opcode }, | |
f88c9eb0 | 7287 | /* 88 */ |
592d1631 L |
7288 | { Bad_Opcode }, |
7289 | { Bad_Opcode }, | |
7290 | { Bad_Opcode }, | |
7291 | { Bad_Opcode }, | |
7292 | { Bad_Opcode }, | |
7293 | { Bad_Opcode }, | |
7294 | { Bad_Opcode }, | |
7295 | { Bad_Opcode }, | |
f88c9eb0 | 7296 | /* 90 */ |
592d1631 L |
7297 | { Bad_Opcode }, |
7298 | { Bad_Opcode }, | |
7299 | { Bad_Opcode }, | |
7300 | { Bad_Opcode }, | |
7301 | { Bad_Opcode }, | |
7302 | { Bad_Opcode }, | |
7303 | { Bad_Opcode }, | |
7304 | { Bad_Opcode }, | |
f88c9eb0 | 7305 | /* 98 */ |
592d1631 L |
7306 | { Bad_Opcode }, |
7307 | { Bad_Opcode }, | |
7308 | { Bad_Opcode }, | |
7309 | { Bad_Opcode }, | |
7310 | { Bad_Opcode }, | |
7311 | { Bad_Opcode }, | |
7312 | { Bad_Opcode }, | |
7313 | { Bad_Opcode }, | |
f88c9eb0 | 7314 | /* a0 */ |
592d1631 L |
7315 | { Bad_Opcode }, |
7316 | { Bad_Opcode }, | |
7317 | { Bad_Opcode }, | |
7318 | { Bad_Opcode }, | |
7319 | { Bad_Opcode }, | |
7320 | { Bad_Opcode }, | |
7321 | { Bad_Opcode }, | |
7322 | { Bad_Opcode }, | |
f88c9eb0 | 7323 | /* a8 */ |
592d1631 L |
7324 | { Bad_Opcode }, |
7325 | { Bad_Opcode }, | |
7326 | { Bad_Opcode }, | |
7327 | { Bad_Opcode }, | |
7328 | { Bad_Opcode }, | |
7329 | { Bad_Opcode }, | |
7330 | { Bad_Opcode }, | |
7331 | { Bad_Opcode }, | |
f88c9eb0 | 7332 | /* b0 */ |
592d1631 L |
7333 | { Bad_Opcode }, |
7334 | { Bad_Opcode }, | |
7335 | { Bad_Opcode }, | |
7336 | { Bad_Opcode }, | |
7337 | { Bad_Opcode }, | |
7338 | { Bad_Opcode }, | |
7339 | { Bad_Opcode }, | |
7340 | { Bad_Opcode }, | |
f88c9eb0 | 7341 | /* b8 */ |
592d1631 L |
7342 | { Bad_Opcode }, |
7343 | { Bad_Opcode }, | |
7344 | { Bad_Opcode }, | |
7345 | { Bad_Opcode }, | |
7346 | { Bad_Opcode }, | |
7347 | { Bad_Opcode }, | |
7348 | { Bad_Opcode }, | |
7349 | { Bad_Opcode }, | |
f88c9eb0 | 7350 | /* c0 */ |
592d1631 L |
7351 | { Bad_Opcode }, |
7352 | { Bad_Opcode }, | |
7353 | { Bad_Opcode }, | |
7354 | { Bad_Opcode }, | |
7355 | { Bad_Opcode }, | |
7356 | { Bad_Opcode }, | |
7357 | { Bad_Opcode }, | |
7358 | { Bad_Opcode }, | |
f88c9eb0 | 7359 | /* c8 */ |
a0046408 L |
7360 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7361 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
7362 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
7363 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
7364 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
7365 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 | 7366 | { Bad_Opcode }, |
48521003 | 7367 | { PREFIX_TABLE (PREFIX_0F38CF) }, |
f88c9eb0 | 7368 | /* d0 */ |
592d1631 L |
7369 | { Bad_Opcode }, |
7370 | { Bad_Opcode }, | |
7371 | { Bad_Opcode }, | |
7372 | { Bad_Opcode }, | |
7373 | { Bad_Opcode }, | |
7374 | { Bad_Opcode }, | |
7375 | { Bad_Opcode }, | |
7376 | { Bad_Opcode }, | |
f88c9eb0 | 7377 | /* d8 */ |
592d1631 L |
7378 | { Bad_Opcode }, |
7379 | { Bad_Opcode }, | |
7380 | { Bad_Opcode }, | |
f88c9eb0 SP |
7381 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7382 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
7383 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
7384 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
7385 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
7386 | /* e0 */ | |
592d1631 L |
7387 | { Bad_Opcode }, |
7388 | { Bad_Opcode }, | |
7389 | { Bad_Opcode }, | |
7390 | { Bad_Opcode }, | |
7391 | { Bad_Opcode }, | |
7392 | { Bad_Opcode }, | |
7393 | { Bad_Opcode }, | |
7394 | { Bad_Opcode }, | |
f88c9eb0 | 7395 | /* e8 */ |
592d1631 L |
7396 | { Bad_Opcode }, |
7397 | { Bad_Opcode }, | |
7398 | { Bad_Opcode }, | |
7399 | { Bad_Opcode }, | |
7400 | { Bad_Opcode }, | |
7401 | { Bad_Opcode }, | |
7402 | { Bad_Opcode }, | |
7403 | { Bad_Opcode }, | |
f88c9eb0 SP |
7404 | /* f0 */ |
7405 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
7406 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
7407 | { Bad_Opcode }, |
7408 | { Bad_Opcode }, | |
7409 | { Bad_Opcode }, | |
603555e5 | 7410 | { PREFIX_TABLE (PREFIX_0F38F5) }, |
e2e1fcde | 7411 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 7412 | { Bad_Opcode }, |
f88c9eb0 | 7413 | /* f8 */ |
592d1631 L |
7414 | { Bad_Opcode }, |
7415 | { Bad_Opcode }, | |
7416 | { Bad_Opcode }, | |
7417 | { Bad_Opcode }, | |
7418 | { Bad_Opcode }, | |
7419 | { Bad_Opcode }, | |
7420 | { Bad_Opcode }, | |
7421 | { Bad_Opcode }, | |
f88c9eb0 SP |
7422 | }, |
7423 | /* THREE_BYTE_0F3A */ | |
7424 | { | |
7425 | /* 00 */ | |
592d1631 L |
7426 | { Bad_Opcode }, |
7427 | { Bad_Opcode }, | |
7428 | { Bad_Opcode }, | |
7429 | { Bad_Opcode }, | |
7430 | { Bad_Opcode }, | |
7431 | { Bad_Opcode }, | |
7432 | { Bad_Opcode }, | |
7433 | { Bad_Opcode }, | |
f88c9eb0 SP |
7434 | /* 08 */ |
7435 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
7436 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
7437 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
7438 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
7439 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
7440 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
7441 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
507bd325 | 7442 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 7443 | /* 10 */ |
592d1631 L |
7444 | { Bad_Opcode }, |
7445 | { Bad_Opcode }, | |
7446 | { Bad_Opcode }, | |
7447 | { Bad_Opcode }, | |
f88c9eb0 SP |
7448 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7449 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
7450 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
7451 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
7452 | /* 18 */ | |
592d1631 L |
7453 | { Bad_Opcode }, |
7454 | { Bad_Opcode }, | |
7455 | { Bad_Opcode }, | |
7456 | { Bad_Opcode }, | |
7457 | { Bad_Opcode }, | |
7458 | { Bad_Opcode }, | |
7459 | { Bad_Opcode }, | |
7460 | { Bad_Opcode }, | |
f88c9eb0 SP |
7461 | /* 20 */ |
7462 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
7463 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
7464 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
7465 | { Bad_Opcode }, |
7466 | { Bad_Opcode }, | |
7467 | { Bad_Opcode }, | |
7468 | { Bad_Opcode }, | |
7469 | { Bad_Opcode }, | |
f88c9eb0 | 7470 | /* 28 */ |
592d1631 L |
7471 | { Bad_Opcode }, |
7472 | { Bad_Opcode }, | |
7473 | { Bad_Opcode }, | |
7474 | { Bad_Opcode }, | |
7475 | { Bad_Opcode }, | |
7476 | { Bad_Opcode }, | |
7477 | { Bad_Opcode }, | |
7478 | { Bad_Opcode }, | |
f88c9eb0 | 7479 | /* 30 */ |
592d1631 L |
7480 | { Bad_Opcode }, |
7481 | { Bad_Opcode }, | |
7482 | { Bad_Opcode }, | |
7483 | { Bad_Opcode }, | |
7484 | { Bad_Opcode }, | |
7485 | { Bad_Opcode }, | |
7486 | { Bad_Opcode }, | |
7487 | { Bad_Opcode }, | |
f88c9eb0 | 7488 | /* 38 */ |
592d1631 L |
7489 | { Bad_Opcode }, |
7490 | { Bad_Opcode }, | |
7491 | { Bad_Opcode }, | |
7492 | { Bad_Opcode }, | |
7493 | { Bad_Opcode }, | |
7494 | { Bad_Opcode }, | |
7495 | { Bad_Opcode }, | |
7496 | { Bad_Opcode }, | |
f88c9eb0 SP |
7497 | /* 40 */ |
7498 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
7499 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
7500 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 7501 | { Bad_Opcode }, |
f88c9eb0 | 7502 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
7503 | { Bad_Opcode }, |
7504 | { Bad_Opcode }, | |
7505 | { Bad_Opcode }, | |
f88c9eb0 | 7506 | /* 48 */ |
592d1631 L |
7507 | { Bad_Opcode }, |
7508 | { Bad_Opcode }, | |
7509 | { Bad_Opcode }, | |
7510 | { Bad_Opcode }, | |
7511 | { Bad_Opcode }, | |
7512 | { Bad_Opcode }, | |
7513 | { Bad_Opcode }, | |
7514 | { Bad_Opcode }, | |
f88c9eb0 | 7515 | /* 50 */ |
592d1631 L |
7516 | { Bad_Opcode }, |
7517 | { Bad_Opcode }, | |
7518 | { Bad_Opcode }, | |
7519 | { Bad_Opcode }, | |
7520 | { Bad_Opcode }, | |
7521 | { Bad_Opcode }, | |
7522 | { Bad_Opcode }, | |
7523 | { Bad_Opcode }, | |
f88c9eb0 | 7524 | /* 58 */ |
592d1631 L |
7525 | { Bad_Opcode }, |
7526 | { Bad_Opcode }, | |
7527 | { Bad_Opcode }, | |
7528 | { Bad_Opcode }, | |
7529 | { Bad_Opcode }, | |
7530 | { Bad_Opcode }, | |
7531 | { Bad_Opcode }, | |
7532 | { Bad_Opcode }, | |
f88c9eb0 SP |
7533 | /* 60 */ |
7534 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
7535 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
7536 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
7537 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
7538 | { Bad_Opcode }, |
7539 | { Bad_Opcode }, | |
7540 | { Bad_Opcode }, | |
7541 | { Bad_Opcode }, | |
f88c9eb0 | 7542 | /* 68 */ |
592d1631 L |
7543 | { Bad_Opcode }, |
7544 | { Bad_Opcode }, | |
7545 | { Bad_Opcode }, | |
7546 | { Bad_Opcode }, | |
7547 | { Bad_Opcode }, | |
7548 | { Bad_Opcode }, | |
7549 | { Bad_Opcode }, | |
7550 | { Bad_Opcode }, | |
f88c9eb0 | 7551 | /* 70 */ |
592d1631 L |
7552 | { Bad_Opcode }, |
7553 | { Bad_Opcode }, | |
7554 | { Bad_Opcode }, | |
7555 | { Bad_Opcode }, | |
7556 | { Bad_Opcode }, | |
7557 | { Bad_Opcode }, | |
7558 | { Bad_Opcode }, | |
7559 | { Bad_Opcode }, | |
f88c9eb0 | 7560 | /* 78 */ |
592d1631 L |
7561 | { Bad_Opcode }, |
7562 | { Bad_Opcode }, | |
7563 | { Bad_Opcode }, | |
7564 | { Bad_Opcode }, | |
7565 | { Bad_Opcode }, | |
7566 | { Bad_Opcode }, | |
7567 | { Bad_Opcode }, | |
7568 | { Bad_Opcode }, | |
f88c9eb0 | 7569 | /* 80 */ |
592d1631 L |
7570 | { Bad_Opcode }, |
7571 | { Bad_Opcode }, | |
7572 | { Bad_Opcode }, | |
7573 | { Bad_Opcode }, | |
7574 | { Bad_Opcode }, | |
7575 | { Bad_Opcode }, | |
7576 | { Bad_Opcode }, | |
7577 | { Bad_Opcode }, | |
f88c9eb0 | 7578 | /* 88 */ |
592d1631 L |
7579 | { Bad_Opcode }, |
7580 | { Bad_Opcode }, | |
7581 | { Bad_Opcode }, | |
7582 | { Bad_Opcode }, | |
7583 | { Bad_Opcode }, | |
7584 | { Bad_Opcode }, | |
7585 | { Bad_Opcode }, | |
7586 | { Bad_Opcode }, | |
f88c9eb0 | 7587 | /* 90 */ |
592d1631 L |
7588 | { Bad_Opcode }, |
7589 | { Bad_Opcode }, | |
7590 | { Bad_Opcode }, | |
7591 | { Bad_Opcode }, | |
7592 | { Bad_Opcode }, | |
7593 | { Bad_Opcode }, | |
7594 | { Bad_Opcode }, | |
7595 | { Bad_Opcode }, | |
f88c9eb0 | 7596 | /* 98 */ |
592d1631 L |
7597 | { Bad_Opcode }, |
7598 | { Bad_Opcode }, | |
7599 | { Bad_Opcode }, | |
7600 | { Bad_Opcode }, | |
7601 | { Bad_Opcode }, | |
7602 | { Bad_Opcode }, | |
7603 | { Bad_Opcode }, | |
7604 | { Bad_Opcode }, | |
f88c9eb0 | 7605 | /* a0 */ |
592d1631 L |
7606 | { Bad_Opcode }, |
7607 | { Bad_Opcode }, | |
7608 | { Bad_Opcode }, | |
7609 | { Bad_Opcode }, | |
7610 | { Bad_Opcode }, | |
7611 | { Bad_Opcode }, | |
7612 | { Bad_Opcode }, | |
7613 | { Bad_Opcode }, | |
f88c9eb0 | 7614 | /* a8 */ |
592d1631 L |
7615 | { Bad_Opcode }, |
7616 | { Bad_Opcode }, | |
7617 | { Bad_Opcode }, | |
7618 | { Bad_Opcode }, | |
7619 | { Bad_Opcode }, | |
7620 | { Bad_Opcode }, | |
7621 | { Bad_Opcode }, | |
7622 | { Bad_Opcode }, | |
f88c9eb0 | 7623 | /* b0 */ |
592d1631 L |
7624 | { Bad_Opcode }, |
7625 | { Bad_Opcode }, | |
7626 | { Bad_Opcode }, | |
7627 | { Bad_Opcode }, | |
7628 | { Bad_Opcode }, | |
7629 | { Bad_Opcode }, | |
7630 | { Bad_Opcode }, | |
7631 | { Bad_Opcode }, | |
f88c9eb0 | 7632 | /* b8 */ |
592d1631 L |
7633 | { Bad_Opcode }, |
7634 | { Bad_Opcode }, | |
7635 | { Bad_Opcode }, | |
7636 | { Bad_Opcode }, | |
7637 | { Bad_Opcode }, | |
7638 | { Bad_Opcode }, | |
7639 | { Bad_Opcode }, | |
7640 | { Bad_Opcode }, | |
f88c9eb0 | 7641 | /* c0 */ |
592d1631 L |
7642 | { Bad_Opcode }, |
7643 | { Bad_Opcode }, | |
7644 | { Bad_Opcode }, | |
7645 | { Bad_Opcode }, | |
7646 | { Bad_Opcode }, | |
7647 | { Bad_Opcode }, | |
7648 | { Bad_Opcode }, | |
7649 | { Bad_Opcode }, | |
f88c9eb0 | 7650 | /* c8 */ |
592d1631 L |
7651 | { Bad_Opcode }, |
7652 | { Bad_Opcode }, | |
7653 | { Bad_Opcode }, | |
7654 | { Bad_Opcode }, | |
a0046408 | 7655 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 | 7656 | { Bad_Opcode }, |
48521003 IT |
7657 | { PREFIX_TABLE (PREFIX_0F3ACE) }, |
7658 | { PREFIX_TABLE (PREFIX_0F3ACF) }, | |
f88c9eb0 | 7659 | /* d0 */ |
592d1631 L |
7660 | { Bad_Opcode }, |
7661 | { Bad_Opcode }, | |
7662 | { Bad_Opcode }, | |
7663 | { Bad_Opcode }, | |
7664 | { Bad_Opcode }, | |
7665 | { Bad_Opcode }, | |
7666 | { Bad_Opcode }, | |
7667 | { Bad_Opcode }, | |
f88c9eb0 | 7668 | /* d8 */ |
592d1631 L |
7669 | { Bad_Opcode }, |
7670 | { Bad_Opcode }, | |
7671 | { Bad_Opcode }, | |
7672 | { Bad_Opcode }, | |
7673 | { Bad_Opcode }, | |
7674 | { Bad_Opcode }, | |
7675 | { Bad_Opcode }, | |
f88c9eb0 SP |
7676 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7677 | /* e0 */ | |
592d1631 L |
7678 | { Bad_Opcode }, |
7679 | { Bad_Opcode }, | |
7680 | { Bad_Opcode }, | |
7681 | { Bad_Opcode }, | |
7682 | { Bad_Opcode }, | |
592d1631 L |
7683 | { Bad_Opcode }, |
7684 | { Bad_Opcode }, | |
7685 | { Bad_Opcode }, | |
85f10a01 | 7686 | /* e8 */ |
592d1631 L |
7687 | { Bad_Opcode }, |
7688 | { Bad_Opcode }, | |
7689 | { Bad_Opcode }, | |
7690 | { Bad_Opcode }, | |
7691 | { Bad_Opcode }, | |
7692 | { Bad_Opcode }, | |
7693 | { Bad_Opcode }, | |
7694 | { Bad_Opcode }, | |
85f10a01 | 7695 | /* f0 */ |
592d1631 L |
7696 | { Bad_Opcode }, |
7697 | { Bad_Opcode }, | |
7698 | { Bad_Opcode }, | |
7699 | { Bad_Opcode }, | |
7700 | { Bad_Opcode }, | |
7701 | { Bad_Opcode }, | |
7702 | { Bad_Opcode }, | |
7703 | { Bad_Opcode }, | |
85f10a01 | 7704 | /* f8 */ |
592d1631 L |
7705 | { Bad_Opcode }, |
7706 | { Bad_Opcode }, | |
7707 | { Bad_Opcode }, | |
7708 | { Bad_Opcode }, | |
7709 | { Bad_Opcode }, | |
7710 | { Bad_Opcode }, | |
7711 | { Bad_Opcode }, | |
7712 | { Bad_Opcode }, | |
85f10a01 | 7713 | }, |
f88c9eb0 SP |
7714 | }; |
7715 | ||
7716 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7717 | /* XOP_08 */ |
85f10a01 MM |
7718 | { |
7719 | /* 00 */ | |
592d1631 L |
7720 | { Bad_Opcode }, |
7721 | { Bad_Opcode }, | |
7722 | { Bad_Opcode }, | |
7723 | { Bad_Opcode }, | |
7724 | { Bad_Opcode }, | |
7725 | { Bad_Opcode }, | |
7726 | { Bad_Opcode }, | |
7727 | { Bad_Opcode }, | |
85f10a01 | 7728 | /* 08 */ |
592d1631 L |
7729 | { Bad_Opcode }, |
7730 | { Bad_Opcode }, | |
7731 | { Bad_Opcode }, | |
7732 | { Bad_Opcode }, | |
7733 | { Bad_Opcode }, | |
7734 | { Bad_Opcode }, | |
7735 | { Bad_Opcode }, | |
7736 | { Bad_Opcode }, | |
85f10a01 | 7737 | /* 10 */ |
3929df09 | 7738 | { Bad_Opcode }, |
592d1631 L |
7739 | { Bad_Opcode }, |
7740 | { Bad_Opcode }, | |
7741 | { Bad_Opcode }, | |
7742 | { Bad_Opcode }, | |
7743 | { Bad_Opcode }, | |
7744 | { Bad_Opcode }, | |
7745 | { Bad_Opcode }, | |
85f10a01 | 7746 | /* 18 */ |
592d1631 L |
7747 | { Bad_Opcode }, |
7748 | { Bad_Opcode }, | |
7749 | { Bad_Opcode }, | |
7750 | { Bad_Opcode }, | |
7751 | { Bad_Opcode }, | |
7752 | { Bad_Opcode }, | |
7753 | { Bad_Opcode }, | |
7754 | { Bad_Opcode }, | |
85f10a01 | 7755 | /* 20 */ |
592d1631 L |
7756 | { Bad_Opcode }, |
7757 | { Bad_Opcode }, | |
7758 | { Bad_Opcode }, | |
7759 | { Bad_Opcode }, | |
7760 | { Bad_Opcode }, | |
7761 | { Bad_Opcode }, | |
7762 | { Bad_Opcode }, | |
7763 | { Bad_Opcode }, | |
85f10a01 | 7764 | /* 28 */ |
592d1631 L |
7765 | { Bad_Opcode }, |
7766 | { Bad_Opcode }, | |
7767 | { Bad_Opcode }, | |
7768 | { Bad_Opcode }, | |
7769 | { Bad_Opcode }, | |
7770 | { Bad_Opcode }, | |
7771 | { Bad_Opcode }, | |
7772 | { Bad_Opcode }, | |
c0f3af97 | 7773 | /* 30 */ |
592d1631 L |
7774 | { Bad_Opcode }, |
7775 | { Bad_Opcode }, | |
7776 | { Bad_Opcode }, | |
7777 | { Bad_Opcode }, | |
7778 | { Bad_Opcode }, | |
7779 | { Bad_Opcode }, | |
7780 | { Bad_Opcode }, | |
7781 | { Bad_Opcode }, | |
c0f3af97 | 7782 | /* 38 */ |
592d1631 L |
7783 | { Bad_Opcode }, |
7784 | { Bad_Opcode }, | |
7785 | { Bad_Opcode }, | |
7786 | { Bad_Opcode }, | |
7787 | { Bad_Opcode }, | |
7788 | { Bad_Opcode }, | |
7789 | { Bad_Opcode }, | |
7790 | { Bad_Opcode }, | |
c0f3af97 | 7791 | /* 40 */ |
592d1631 L |
7792 | { Bad_Opcode }, |
7793 | { Bad_Opcode }, | |
7794 | { Bad_Opcode }, | |
7795 | { Bad_Opcode }, | |
7796 | { Bad_Opcode }, | |
7797 | { Bad_Opcode }, | |
7798 | { Bad_Opcode }, | |
7799 | { Bad_Opcode }, | |
85f10a01 | 7800 | /* 48 */ |
592d1631 L |
7801 | { Bad_Opcode }, |
7802 | { Bad_Opcode }, | |
7803 | { Bad_Opcode }, | |
7804 | { Bad_Opcode }, | |
7805 | { Bad_Opcode }, | |
7806 | { Bad_Opcode }, | |
7807 | { Bad_Opcode }, | |
7808 | { Bad_Opcode }, | |
c0f3af97 | 7809 | /* 50 */ |
592d1631 L |
7810 | { Bad_Opcode }, |
7811 | { Bad_Opcode }, | |
7812 | { Bad_Opcode }, | |
7813 | { Bad_Opcode }, | |
7814 | { Bad_Opcode }, | |
7815 | { Bad_Opcode }, | |
7816 | { Bad_Opcode }, | |
7817 | { Bad_Opcode }, | |
85f10a01 | 7818 | /* 58 */ |
592d1631 L |
7819 | { Bad_Opcode }, |
7820 | { Bad_Opcode }, | |
7821 | { Bad_Opcode }, | |
7822 | { Bad_Opcode }, | |
7823 | { Bad_Opcode }, | |
7824 | { Bad_Opcode }, | |
7825 | { Bad_Opcode }, | |
7826 | { Bad_Opcode }, | |
c1e679ec | 7827 | /* 60 */ |
592d1631 L |
7828 | { Bad_Opcode }, |
7829 | { Bad_Opcode }, | |
7830 | { Bad_Opcode }, | |
7831 | { Bad_Opcode }, | |
7832 | { Bad_Opcode }, | |
7833 | { Bad_Opcode }, | |
7834 | { Bad_Opcode }, | |
7835 | { Bad_Opcode }, | |
c0f3af97 | 7836 | /* 68 */ |
592d1631 L |
7837 | { Bad_Opcode }, |
7838 | { Bad_Opcode }, | |
7839 | { Bad_Opcode }, | |
7840 | { Bad_Opcode }, | |
7841 | { Bad_Opcode }, | |
7842 | { Bad_Opcode }, | |
7843 | { Bad_Opcode }, | |
7844 | { Bad_Opcode }, | |
85f10a01 | 7845 | /* 70 */ |
592d1631 L |
7846 | { Bad_Opcode }, |
7847 | { Bad_Opcode }, | |
7848 | { Bad_Opcode }, | |
7849 | { Bad_Opcode }, | |
7850 | { Bad_Opcode }, | |
7851 | { Bad_Opcode }, | |
7852 | { Bad_Opcode }, | |
7853 | { Bad_Opcode }, | |
85f10a01 | 7854 | /* 78 */ |
592d1631 L |
7855 | { Bad_Opcode }, |
7856 | { Bad_Opcode }, | |
7857 | { Bad_Opcode }, | |
7858 | { Bad_Opcode }, | |
7859 | { Bad_Opcode }, | |
7860 | { Bad_Opcode }, | |
7861 | { Bad_Opcode }, | |
7862 | { Bad_Opcode }, | |
85f10a01 | 7863 | /* 80 */ |
592d1631 L |
7864 | { Bad_Opcode }, |
7865 | { Bad_Opcode }, | |
7866 | { Bad_Opcode }, | |
7867 | { Bad_Opcode }, | |
7868 | { Bad_Opcode }, | |
3a2430e0 JB |
7869 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7870 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7871 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7872 | /* 88 */ |
592d1631 L |
7873 | { Bad_Opcode }, |
7874 | { Bad_Opcode }, | |
7875 | { Bad_Opcode }, | |
7876 | { Bad_Opcode }, | |
7877 | { Bad_Opcode }, | |
7878 | { Bad_Opcode }, | |
3a2430e0 JB |
7879 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7880 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7881 | /* 90 */ |
592d1631 L |
7882 | { Bad_Opcode }, |
7883 | { Bad_Opcode }, | |
7884 | { Bad_Opcode }, | |
7885 | { Bad_Opcode }, | |
7886 | { Bad_Opcode }, | |
3a2430e0 JB |
7887 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7888 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7889 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7890 | /* 98 */ |
592d1631 L |
7891 | { Bad_Opcode }, |
7892 | { Bad_Opcode }, | |
7893 | { Bad_Opcode }, | |
7894 | { Bad_Opcode }, | |
7895 | { Bad_Opcode }, | |
7896 | { Bad_Opcode }, | |
3a2430e0 JB |
7897 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7898 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7899 | /* a0 */ |
592d1631 L |
7900 | { Bad_Opcode }, |
7901 | { Bad_Opcode }, | |
3a2430e0 JB |
7902 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7903 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
592d1631 L |
7904 | { Bad_Opcode }, |
7905 | { Bad_Opcode }, | |
3a2430e0 | 7906 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7907 | { Bad_Opcode }, |
5dd85c99 | 7908 | /* a8 */ |
592d1631 L |
7909 | { Bad_Opcode }, |
7910 | { Bad_Opcode }, | |
7911 | { Bad_Opcode }, | |
7912 | { Bad_Opcode }, | |
7913 | { Bad_Opcode }, | |
7914 | { Bad_Opcode }, | |
7915 | { Bad_Opcode }, | |
7916 | { Bad_Opcode }, | |
5dd85c99 | 7917 | /* b0 */ |
592d1631 L |
7918 | { Bad_Opcode }, |
7919 | { Bad_Opcode }, | |
7920 | { Bad_Opcode }, | |
7921 | { Bad_Opcode }, | |
7922 | { Bad_Opcode }, | |
7923 | { Bad_Opcode }, | |
3a2430e0 | 7924 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7925 | { Bad_Opcode }, |
5dd85c99 | 7926 | /* b8 */ |
592d1631 L |
7927 | { Bad_Opcode }, |
7928 | { Bad_Opcode }, | |
7929 | { Bad_Opcode }, | |
7930 | { Bad_Opcode }, | |
7931 | { Bad_Opcode }, | |
7932 | { Bad_Opcode }, | |
7933 | { Bad_Opcode }, | |
7934 | { Bad_Opcode }, | |
5dd85c99 | 7935 | /* c0 */ |
bf890a93 IT |
7936 | { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, |
7937 | { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, | |
7938 | { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, | |
7939 | { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, | |
592d1631 L |
7940 | { Bad_Opcode }, |
7941 | { Bad_Opcode }, | |
7942 | { Bad_Opcode }, | |
7943 | { Bad_Opcode }, | |
5dd85c99 | 7944 | /* c8 */ |
592d1631 L |
7945 | { Bad_Opcode }, |
7946 | { Bad_Opcode }, | |
7947 | { Bad_Opcode }, | |
7948 | { Bad_Opcode }, | |
ff688e1f L |
7949 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
7950 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
7951 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
7952 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 7953 | /* d0 */ |
592d1631 L |
7954 | { Bad_Opcode }, |
7955 | { Bad_Opcode }, | |
7956 | { Bad_Opcode }, | |
7957 | { Bad_Opcode }, | |
7958 | { Bad_Opcode }, | |
7959 | { Bad_Opcode }, | |
7960 | { Bad_Opcode }, | |
7961 | { Bad_Opcode }, | |
5dd85c99 | 7962 | /* d8 */ |
592d1631 L |
7963 | { Bad_Opcode }, |
7964 | { Bad_Opcode }, | |
7965 | { Bad_Opcode }, | |
7966 | { Bad_Opcode }, | |
7967 | { Bad_Opcode }, | |
7968 | { Bad_Opcode }, | |
7969 | { Bad_Opcode }, | |
7970 | { Bad_Opcode }, | |
5dd85c99 | 7971 | /* e0 */ |
592d1631 L |
7972 | { Bad_Opcode }, |
7973 | { Bad_Opcode }, | |
7974 | { Bad_Opcode }, | |
7975 | { Bad_Opcode }, | |
7976 | { Bad_Opcode }, | |
7977 | { Bad_Opcode }, | |
7978 | { Bad_Opcode }, | |
7979 | { Bad_Opcode }, | |
5dd85c99 | 7980 | /* e8 */ |
592d1631 L |
7981 | { Bad_Opcode }, |
7982 | { Bad_Opcode }, | |
7983 | { Bad_Opcode }, | |
7984 | { Bad_Opcode }, | |
ff688e1f L |
7985 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
7986 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
7987 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
7988 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 7989 | /* f0 */ |
592d1631 L |
7990 | { Bad_Opcode }, |
7991 | { Bad_Opcode }, | |
7992 | { Bad_Opcode }, | |
7993 | { Bad_Opcode }, | |
7994 | { Bad_Opcode }, | |
7995 | { Bad_Opcode }, | |
7996 | { Bad_Opcode }, | |
7997 | { Bad_Opcode }, | |
5dd85c99 | 7998 | /* f8 */ |
592d1631 L |
7999 | { Bad_Opcode }, |
8000 | { Bad_Opcode }, | |
8001 | { Bad_Opcode }, | |
8002 | { Bad_Opcode }, | |
8003 | { Bad_Opcode }, | |
8004 | { Bad_Opcode }, | |
8005 | { Bad_Opcode }, | |
8006 | { Bad_Opcode }, | |
5dd85c99 SP |
8007 | }, |
8008 | /* XOP_09 */ | |
8009 | { | |
8010 | /* 00 */ | |
592d1631 | 8011 | { Bad_Opcode }, |
2a2a0f38 QN |
8012 | { REG_TABLE (REG_XOP_TBM_01) }, |
8013 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
8014 | { Bad_Opcode }, |
8015 | { Bad_Opcode }, | |
8016 | { Bad_Opcode }, | |
8017 | { Bad_Opcode }, | |
8018 | { Bad_Opcode }, | |
5dd85c99 | 8019 | /* 08 */ |
592d1631 L |
8020 | { Bad_Opcode }, |
8021 | { Bad_Opcode }, | |
8022 | { Bad_Opcode }, | |
8023 | { Bad_Opcode }, | |
8024 | { Bad_Opcode }, | |
8025 | { Bad_Opcode }, | |
8026 | { Bad_Opcode }, | |
8027 | { Bad_Opcode }, | |
5dd85c99 | 8028 | /* 10 */ |
592d1631 L |
8029 | { Bad_Opcode }, |
8030 | { Bad_Opcode }, | |
5dd85c99 | 8031 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
8032 | { Bad_Opcode }, |
8033 | { Bad_Opcode }, | |
8034 | { Bad_Opcode }, | |
8035 | { Bad_Opcode }, | |
8036 | { Bad_Opcode }, | |
5dd85c99 | 8037 | /* 18 */ |
592d1631 L |
8038 | { Bad_Opcode }, |
8039 | { Bad_Opcode }, | |
8040 | { Bad_Opcode }, | |
8041 | { Bad_Opcode }, | |
8042 | { Bad_Opcode }, | |
8043 | { Bad_Opcode }, | |
8044 | { Bad_Opcode }, | |
8045 | { Bad_Opcode }, | |
5dd85c99 | 8046 | /* 20 */ |
592d1631 L |
8047 | { Bad_Opcode }, |
8048 | { Bad_Opcode }, | |
8049 | { Bad_Opcode }, | |
8050 | { Bad_Opcode }, | |
8051 | { Bad_Opcode }, | |
8052 | { Bad_Opcode }, | |
8053 | { Bad_Opcode }, | |
8054 | { Bad_Opcode }, | |
5dd85c99 | 8055 | /* 28 */ |
592d1631 L |
8056 | { Bad_Opcode }, |
8057 | { Bad_Opcode }, | |
8058 | { Bad_Opcode }, | |
8059 | { Bad_Opcode }, | |
8060 | { Bad_Opcode }, | |
8061 | { Bad_Opcode }, | |
8062 | { Bad_Opcode }, | |
8063 | { Bad_Opcode }, | |
5dd85c99 | 8064 | /* 30 */ |
592d1631 L |
8065 | { Bad_Opcode }, |
8066 | { Bad_Opcode }, | |
8067 | { Bad_Opcode }, | |
8068 | { Bad_Opcode }, | |
8069 | { Bad_Opcode }, | |
8070 | { Bad_Opcode }, | |
8071 | { Bad_Opcode }, | |
8072 | { Bad_Opcode }, | |
5dd85c99 | 8073 | /* 38 */ |
592d1631 L |
8074 | { Bad_Opcode }, |
8075 | { Bad_Opcode }, | |
8076 | { Bad_Opcode }, | |
8077 | { Bad_Opcode }, | |
8078 | { Bad_Opcode }, | |
8079 | { Bad_Opcode }, | |
8080 | { Bad_Opcode }, | |
8081 | { Bad_Opcode }, | |
5dd85c99 | 8082 | /* 40 */ |
592d1631 L |
8083 | { Bad_Opcode }, |
8084 | { Bad_Opcode }, | |
8085 | { Bad_Opcode }, | |
8086 | { Bad_Opcode }, | |
8087 | { Bad_Opcode }, | |
8088 | { Bad_Opcode }, | |
8089 | { Bad_Opcode }, | |
8090 | { Bad_Opcode }, | |
5dd85c99 | 8091 | /* 48 */ |
592d1631 L |
8092 | { Bad_Opcode }, |
8093 | { Bad_Opcode }, | |
8094 | { Bad_Opcode }, | |
8095 | { Bad_Opcode }, | |
8096 | { Bad_Opcode }, | |
8097 | { Bad_Opcode }, | |
8098 | { Bad_Opcode }, | |
8099 | { Bad_Opcode }, | |
5dd85c99 | 8100 | /* 50 */ |
592d1631 L |
8101 | { Bad_Opcode }, |
8102 | { Bad_Opcode }, | |
8103 | { Bad_Opcode }, | |
8104 | { Bad_Opcode }, | |
8105 | { Bad_Opcode }, | |
8106 | { Bad_Opcode }, | |
8107 | { Bad_Opcode }, | |
8108 | { Bad_Opcode }, | |
5dd85c99 | 8109 | /* 58 */ |
592d1631 L |
8110 | { Bad_Opcode }, |
8111 | { Bad_Opcode }, | |
8112 | { Bad_Opcode }, | |
8113 | { Bad_Opcode }, | |
8114 | { Bad_Opcode }, | |
8115 | { Bad_Opcode }, | |
8116 | { Bad_Opcode }, | |
8117 | { Bad_Opcode }, | |
5dd85c99 | 8118 | /* 60 */ |
592d1631 L |
8119 | { Bad_Opcode }, |
8120 | { Bad_Opcode }, | |
8121 | { Bad_Opcode }, | |
8122 | { Bad_Opcode }, | |
8123 | { Bad_Opcode }, | |
8124 | { Bad_Opcode }, | |
8125 | { Bad_Opcode }, | |
8126 | { Bad_Opcode }, | |
5dd85c99 | 8127 | /* 68 */ |
592d1631 L |
8128 | { Bad_Opcode }, |
8129 | { Bad_Opcode }, | |
8130 | { Bad_Opcode }, | |
8131 | { Bad_Opcode }, | |
8132 | { Bad_Opcode }, | |
8133 | { Bad_Opcode }, | |
8134 | { Bad_Opcode }, | |
8135 | { Bad_Opcode }, | |
5dd85c99 | 8136 | /* 70 */ |
592d1631 L |
8137 | { Bad_Opcode }, |
8138 | { Bad_Opcode }, | |
8139 | { Bad_Opcode }, | |
8140 | { Bad_Opcode }, | |
8141 | { Bad_Opcode }, | |
8142 | { Bad_Opcode }, | |
8143 | { Bad_Opcode }, | |
8144 | { Bad_Opcode }, | |
5dd85c99 | 8145 | /* 78 */ |
592d1631 L |
8146 | { Bad_Opcode }, |
8147 | { Bad_Opcode }, | |
8148 | { Bad_Opcode }, | |
8149 | { Bad_Opcode }, | |
8150 | { Bad_Opcode }, | |
8151 | { Bad_Opcode }, | |
8152 | { Bad_Opcode }, | |
8153 | { Bad_Opcode }, | |
5dd85c99 | 8154 | /* 80 */ |
592a252b L |
8155 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
8156 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, | |
bf890a93 IT |
8157 | { "vfrczss", { XM, EXd }, 0 }, |
8158 | { "vfrczsd", { XM, EXq }, 0 }, | |
592d1631 L |
8159 | { Bad_Opcode }, |
8160 | { Bad_Opcode }, | |
8161 | { Bad_Opcode }, | |
8162 | { Bad_Opcode }, | |
5dd85c99 | 8163 | /* 88 */ |
592d1631 L |
8164 | { Bad_Opcode }, |
8165 | { Bad_Opcode }, | |
8166 | { Bad_Opcode }, | |
8167 | { Bad_Opcode }, | |
8168 | { Bad_Opcode }, | |
8169 | { Bad_Opcode }, | |
8170 | { Bad_Opcode }, | |
8171 | { Bad_Opcode }, | |
5dd85c99 | 8172 | /* 90 */ |
bf890a93 IT |
8173 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8174 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8175 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8176 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8177 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8178 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8179 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8180 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
5dd85c99 | 8181 | /* 98 */ |
bf890a93 IT |
8182 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8183 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8184 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8185 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
592d1631 L |
8186 | { Bad_Opcode }, |
8187 | { Bad_Opcode }, | |
8188 | { Bad_Opcode }, | |
8189 | { Bad_Opcode }, | |
5dd85c99 | 8190 | /* a0 */ |
592d1631 L |
8191 | { Bad_Opcode }, |
8192 | { Bad_Opcode }, | |
8193 | { Bad_Opcode }, | |
8194 | { Bad_Opcode }, | |
8195 | { Bad_Opcode }, | |
8196 | { Bad_Opcode }, | |
8197 | { Bad_Opcode }, | |
8198 | { Bad_Opcode }, | |
5dd85c99 | 8199 | /* a8 */ |
592d1631 L |
8200 | { Bad_Opcode }, |
8201 | { Bad_Opcode }, | |
8202 | { Bad_Opcode }, | |
8203 | { Bad_Opcode }, | |
8204 | { Bad_Opcode }, | |
8205 | { Bad_Opcode }, | |
8206 | { Bad_Opcode }, | |
8207 | { Bad_Opcode }, | |
5dd85c99 | 8208 | /* b0 */ |
592d1631 L |
8209 | { Bad_Opcode }, |
8210 | { Bad_Opcode }, | |
8211 | { Bad_Opcode }, | |
8212 | { Bad_Opcode }, | |
8213 | { Bad_Opcode }, | |
8214 | { Bad_Opcode }, | |
8215 | { Bad_Opcode }, | |
8216 | { Bad_Opcode }, | |
5dd85c99 | 8217 | /* b8 */ |
592d1631 L |
8218 | { Bad_Opcode }, |
8219 | { Bad_Opcode }, | |
8220 | { Bad_Opcode }, | |
8221 | { Bad_Opcode }, | |
8222 | { Bad_Opcode }, | |
8223 | { Bad_Opcode }, | |
8224 | { Bad_Opcode }, | |
8225 | { Bad_Opcode }, | |
5dd85c99 | 8226 | /* c0 */ |
592d1631 | 8227 | { Bad_Opcode }, |
bf890a93 IT |
8228 | { "vphaddbw", { XM, EXxmm }, 0 }, |
8229 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
8230 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8231 | { Bad_Opcode }, |
8232 | { Bad_Opcode }, | |
bf890a93 IT |
8233 | { "vphaddwd", { XM, EXxmm }, 0 }, |
8234 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8235 | /* c8 */ |
592d1631 L |
8236 | { Bad_Opcode }, |
8237 | { Bad_Opcode }, | |
8238 | { Bad_Opcode }, | |
bf890a93 | 8239 | { "vphadddq", { XM, EXxmm }, 0 }, |
592d1631 L |
8240 | { Bad_Opcode }, |
8241 | { Bad_Opcode }, | |
8242 | { Bad_Opcode }, | |
8243 | { Bad_Opcode }, | |
5dd85c99 | 8244 | /* d0 */ |
592d1631 | 8245 | { Bad_Opcode }, |
bf890a93 IT |
8246 | { "vphaddubw", { XM, EXxmm }, 0 }, |
8247 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
8248 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8249 | { Bad_Opcode }, |
8250 | { Bad_Opcode }, | |
bf890a93 IT |
8251 | { "vphadduwd", { XM, EXxmm }, 0 }, |
8252 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8253 | /* d8 */ |
592d1631 L |
8254 | { Bad_Opcode }, |
8255 | { Bad_Opcode }, | |
8256 | { Bad_Opcode }, | |
bf890a93 | 8257 | { "vphaddudq", { XM, EXxmm }, 0 }, |
592d1631 L |
8258 | { Bad_Opcode }, |
8259 | { Bad_Opcode }, | |
8260 | { Bad_Opcode }, | |
8261 | { Bad_Opcode }, | |
5dd85c99 | 8262 | /* e0 */ |
592d1631 | 8263 | { Bad_Opcode }, |
bf890a93 IT |
8264 | { "vphsubbw", { XM, EXxmm }, 0 }, |
8265 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
8266 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8267 | { Bad_Opcode }, |
8268 | { Bad_Opcode }, | |
8269 | { Bad_Opcode }, | |
8270 | { Bad_Opcode }, | |
4e7d34a6 | 8271 | /* e8 */ |
592d1631 L |
8272 | { Bad_Opcode }, |
8273 | { Bad_Opcode }, | |
8274 | { Bad_Opcode }, | |
8275 | { Bad_Opcode }, | |
8276 | { Bad_Opcode }, | |
8277 | { Bad_Opcode }, | |
8278 | { Bad_Opcode }, | |
8279 | { Bad_Opcode }, | |
4e7d34a6 | 8280 | /* f0 */ |
592d1631 L |
8281 | { Bad_Opcode }, |
8282 | { Bad_Opcode }, | |
8283 | { Bad_Opcode }, | |
8284 | { Bad_Opcode }, | |
8285 | { Bad_Opcode }, | |
8286 | { Bad_Opcode }, | |
8287 | { Bad_Opcode }, | |
8288 | { Bad_Opcode }, | |
4e7d34a6 | 8289 | /* f8 */ |
592d1631 L |
8290 | { Bad_Opcode }, |
8291 | { Bad_Opcode }, | |
8292 | { Bad_Opcode }, | |
8293 | { Bad_Opcode }, | |
8294 | { Bad_Opcode }, | |
8295 | { Bad_Opcode }, | |
8296 | { Bad_Opcode }, | |
8297 | { Bad_Opcode }, | |
4e7d34a6 | 8298 | }, |
f88c9eb0 | 8299 | /* XOP_0A */ |
4e7d34a6 L |
8300 | { |
8301 | /* 00 */ | |
592d1631 L |
8302 | { Bad_Opcode }, |
8303 | { Bad_Opcode }, | |
8304 | { Bad_Opcode }, | |
8305 | { Bad_Opcode }, | |
8306 | { Bad_Opcode }, | |
8307 | { Bad_Opcode }, | |
8308 | { Bad_Opcode }, | |
8309 | { Bad_Opcode }, | |
4e7d34a6 | 8310 | /* 08 */ |
592d1631 L |
8311 | { Bad_Opcode }, |
8312 | { Bad_Opcode }, | |
8313 | { Bad_Opcode }, | |
8314 | { Bad_Opcode }, | |
8315 | { Bad_Opcode }, | |
8316 | { Bad_Opcode }, | |
8317 | { Bad_Opcode }, | |
8318 | { Bad_Opcode }, | |
4e7d34a6 | 8319 | /* 10 */ |
bf890a93 | 8320 | { "bextr", { Gv, Ev, Iq }, 0 }, |
592d1631 | 8321 | { Bad_Opcode }, |
f88c9eb0 | 8322 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
8323 | { Bad_Opcode }, |
8324 | { Bad_Opcode }, | |
8325 | { Bad_Opcode }, | |
8326 | { Bad_Opcode }, | |
8327 | { Bad_Opcode }, | |
4e7d34a6 | 8328 | /* 18 */ |
592d1631 L |
8329 | { Bad_Opcode }, |
8330 | { Bad_Opcode }, | |
8331 | { Bad_Opcode }, | |
8332 | { Bad_Opcode }, | |
8333 | { Bad_Opcode }, | |
8334 | { Bad_Opcode }, | |
8335 | { Bad_Opcode }, | |
8336 | { Bad_Opcode }, | |
4e7d34a6 | 8337 | /* 20 */ |
592d1631 L |
8338 | { Bad_Opcode }, |
8339 | { Bad_Opcode }, | |
8340 | { Bad_Opcode }, | |
8341 | { Bad_Opcode }, | |
8342 | { Bad_Opcode }, | |
8343 | { Bad_Opcode }, | |
8344 | { Bad_Opcode }, | |
8345 | { Bad_Opcode }, | |
4e7d34a6 | 8346 | /* 28 */ |
592d1631 L |
8347 | { Bad_Opcode }, |
8348 | { Bad_Opcode }, | |
8349 | { Bad_Opcode }, | |
8350 | { Bad_Opcode }, | |
8351 | { Bad_Opcode }, | |
8352 | { Bad_Opcode }, | |
8353 | { Bad_Opcode }, | |
8354 | { Bad_Opcode }, | |
4e7d34a6 | 8355 | /* 30 */ |
592d1631 L |
8356 | { Bad_Opcode }, |
8357 | { Bad_Opcode }, | |
8358 | { Bad_Opcode }, | |
8359 | { Bad_Opcode }, | |
8360 | { Bad_Opcode }, | |
8361 | { Bad_Opcode }, | |
8362 | { Bad_Opcode }, | |
8363 | { Bad_Opcode }, | |
c0f3af97 | 8364 | /* 38 */ |
592d1631 L |
8365 | { Bad_Opcode }, |
8366 | { Bad_Opcode }, | |
8367 | { Bad_Opcode }, | |
8368 | { Bad_Opcode }, | |
8369 | { Bad_Opcode }, | |
8370 | { Bad_Opcode }, | |
8371 | { Bad_Opcode }, | |
8372 | { Bad_Opcode }, | |
c0f3af97 | 8373 | /* 40 */ |
592d1631 L |
8374 | { Bad_Opcode }, |
8375 | { Bad_Opcode }, | |
8376 | { Bad_Opcode }, | |
8377 | { Bad_Opcode }, | |
8378 | { Bad_Opcode }, | |
8379 | { Bad_Opcode }, | |
8380 | { Bad_Opcode }, | |
8381 | { Bad_Opcode }, | |
c1e679ec | 8382 | /* 48 */ |
592d1631 L |
8383 | { Bad_Opcode }, |
8384 | { Bad_Opcode }, | |
8385 | { Bad_Opcode }, | |
8386 | { Bad_Opcode }, | |
8387 | { Bad_Opcode }, | |
8388 | { Bad_Opcode }, | |
8389 | { Bad_Opcode }, | |
8390 | { Bad_Opcode }, | |
c1e679ec | 8391 | /* 50 */ |
592d1631 L |
8392 | { Bad_Opcode }, |
8393 | { Bad_Opcode }, | |
8394 | { Bad_Opcode }, | |
8395 | { Bad_Opcode }, | |
8396 | { Bad_Opcode }, | |
8397 | { Bad_Opcode }, | |
8398 | { Bad_Opcode }, | |
8399 | { Bad_Opcode }, | |
4e7d34a6 | 8400 | /* 58 */ |
592d1631 L |
8401 | { Bad_Opcode }, |
8402 | { Bad_Opcode }, | |
8403 | { Bad_Opcode }, | |
8404 | { Bad_Opcode }, | |
8405 | { Bad_Opcode }, | |
8406 | { Bad_Opcode }, | |
8407 | { Bad_Opcode }, | |
8408 | { Bad_Opcode }, | |
4e7d34a6 | 8409 | /* 60 */ |
592d1631 L |
8410 | { Bad_Opcode }, |
8411 | { Bad_Opcode }, | |
8412 | { Bad_Opcode }, | |
8413 | { Bad_Opcode }, | |
8414 | { Bad_Opcode }, | |
8415 | { Bad_Opcode }, | |
8416 | { Bad_Opcode }, | |
8417 | { Bad_Opcode }, | |
4e7d34a6 | 8418 | /* 68 */ |
592d1631 L |
8419 | { Bad_Opcode }, |
8420 | { Bad_Opcode }, | |
8421 | { Bad_Opcode }, | |
8422 | { Bad_Opcode }, | |
8423 | { Bad_Opcode }, | |
8424 | { Bad_Opcode }, | |
8425 | { Bad_Opcode }, | |
8426 | { Bad_Opcode }, | |
4e7d34a6 | 8427 | /* 70 */ |
592d1631 L |
8428 | { Bad_Opcode }, |
8429 | { Bad_Opcode }, | |
8430 | { Bad_Opcode }, | |
8431 | { Bad_Opcode }, | |
8432 | { Bad_Opcode }, | |
8433 | { Bad_Opcode }, | |
8434 | { Bad_Opcode }, | |
8435 | { Bad_Opcode }, | |
4e7d34a6 | 8436 | /* 78 */ |
592d1631 L |
8437 | { Bad_Opcode }, |
8438 | { Bad_Opcode }, | |
8439 | { Bad_Opcode }, | |
8440 | { Bad_Opcode }, | |
8441 | { Bad_Opcode }, | |
8442 | { Bad_Opcode }, | |
8443 | { Bad_Opcode }, | |
8444 | { Bad_Opcode }, | |
4e7d34a6 | 8445 | /* 80 */ |
592d1631 L |
8446 | { Bad_Opcode }, |
8447 | { Bad_Opcode }, | |
8448 | { Bad_Opcode }, | |
8449 | { Bad_Opcode }, | |
8450 | { Bad_Opcode }, | |
8451 | { Bad_Opcode }, | |
8452 | { Bad_Opcode }, | |
8453 | { Bad_Opcode }, | |
4e7d34a6 | 8454 | /* 88 */ |
592d1631 L |
8455 | { Bad_Opcode }, |
8456 | { Bad_Opcode }, | |
8457 | { Bad_Opcode }, | |
8458 | { Bad_Opcode }, | |
8459 | { Bad_Opcode }, | |
8460 | { Bad_Opcode }, | |
8461 | { Bad_Opcode }, | |
8462 | { Bad_Opcode }, | |
4e7d34a6 | 8463 | /* 90 */ |
592d1631 L |
8464 | { Bad_Opcode }, |
8465 | { Bad_Opcode }, | |
8466 | { Bad_Opcode }, | |
8467 | { Bad_Opcode }, | |
8468 | { Bad_Opcode }, | |
8469 | { Bad_Opcode }, | |
8470 | { Bad_Opcode }, | |
8471 | { Bad_Opcode }, | |
4e7d34a6 | 8472 | /* 98 */ |
592d1631 L |
8473 | { Bad_Opcode }, |
8474 | { Bad_Opcode }, | |
8475 | { Bad_Opcode }, | |
8476 | { Bad_Opcode }, | |
8477 | { Bad_Opcode }, | |
8478 | { Bad_Opcode }, | |
8479 | { Bad_Opcode }, | |
8480 | { Bad_Opcode }, | |
4e7d34a6 | 8481 | /* a0 */ |
592d1631 L |
8482 | { Bad_Opcode }, |
8483 | { Bad_Opcode }, | |
8484 | { Bad_Opcode }, | |
8485 | { Bad_Opcode }, | |
8486 | { Bad_Opcode }, | |
8487 | { Bad_Opcode }, | |
8488 | { Bad_Opcode }, | |
8489 | { Bad_Opcode }, | |
4e7d34a6 | 8490 | /* a8 */ |
592d1631 L |
8491 | { Bad_Opcode }, |
8492 | { Bad_Opcode }, | |
8493 | { Bad_Opcode }, | |
8494 | { Bad_Opcode }, | |
8495 | { Bad_Opcode }, | |
8496 | { Bad_Opcode }, | |
8497 | { Bad_Opcode }, | |
8498 | { Bad_Opcode }, | |
d5d7db8e | 8499 | /* b0 */ |
592d1631 L |
8500 | { Bad_Opcode }, |
8501 | { Bad_Opcode }, | |
8502 | { Bad_Opcode }, | |
8503 | { Bad_Opcode }, | |
8504 | { Bad_Opcode }, | |
8505 | { Bad_Opcode }, | |
8506 | { Bad_Opcode }, | |
8507 | { Bad_Opcode }, | |
85f10a01 | 8508 | /* b8 */ |
592d1631 L |
8509 | { Bad_Opcode }, |
8510 | { Bad_Opcode }, | |
8511 | { Bad_Opcode }, | |
8512 | { Bad_Opcode }, | |
8513 | { Bad_Opcode }, | |
8514 | { Bad_Opcode }, | |
8515 | { Bad_Opcode }, | |
8516 | { Bad_Opcode }, | |
85f10a01 | 8517 | /* c0 */ |
592d1631 L |
8518 | { Bad_Opcode }, |
8519 | { Bad_Opcode }, | |
8520 | { Bad_Opcode }, | |
8521 | { Bad_Opcode }, | |
8522 | { Bad_Opcode }, | |
8523 | { Bad_Opcode }, | |
8524 | { Bad_Opcode }, | |
8525 | { Bad_Opcode }, | |
85f10a01 | 8526 | /* c8 */ |
592d1631 L |
8527 | { Bad_Opcode }, |
8528 | { Bad_Opcode }, | |
8529 | { Bad_Opcode }, | |
8530 | { Bad_Opcode }, | |
8531 | { Bad_Opcode }, | |
8532 | { Bad_Opcode }, | |
8533 | { Bad_Opcode }, | |
8534 | { Bad_Opcode }, | |
85f10a01 | 8535 | /* d0 */ |
592d1631 L |
8536 | { Bad_Opcode }, |
8537 | { Bad_Opcode }, | |
8538 | { Bad_Opcode }, | |
8539 | { Bad_Opcode }, | |
8540 | { Bad_Opcode }, | |
8541 | { Bad_Opcode }, | |
8542 | { Bad_Opcode }, | |
8543 | { Bad_Opcode }, | |
85f10a01 | 8544 | /* d8 */ |
592d1631 L |
8545 | { Bad_Opcode }, |
8546 | { Bad_Opcode }, | |
8547 | { Bad_Opcode }, | |
8548 | { Bad_Opcode }, | |
8549 | { Bad_Opcode }, | |
8550 | { Bad_Opcode }, | |
8551 | { Bad_Opcode }, | |
8552 | { Bad_Opcode }, | |
85f10a01 | 8553 | /* e0 */ |
592d1631 L |
8554 | { Bad_Opcode }, |
8555 | { Bad_Opcode }, | |
8556 | { Bad_Opcode }, | |
8557 | { Bad_Opcode }, | |
8558 | { Bad_Opcode }, | |
8559 | { Bad_Opcode }, | |
8560 | { Bad_Opcode }, | |
8561 | { Bad_Opcode }, | |
85f10a01 | 8562 | /* e8 */ |
592d1631 L |
8563 | { Bad_Opcode }, |
8564 | { Bad_Opcode }, | |
8565 | { Bad_Opcode }, | |
8566 | { Bad_Opcode }, | |
8567 | { Bad_Opcode }, | |
8568 | { Bad_Opcode }, | |
8569 | { Bad_Opcode }, | |
8570 | { Bad_Opcode }, | |
85f10a01 | 8571 | /* f0 */ |
592d1631 L |
8572 | { Bad_Opcode }, |
8573 | { Bad_Opcode }, | |
8574 | { Bad_Opcode }, | |
8575 | { Bad_Opcode }, | |
8576 | { Bad_Opcode }, | |
8577 | { Bad_Opcode }, | |
8578 | { Bad_Opcode }, | |
8579 | { Bad_Opcode }, | |
85f10a01 | 8580 | /* f8 */ |
592d1631 L |
8581 | { Bad_Opcode }, |
8582 | { Bad_Opcode }, | |
8583 | { Bad_Opcode }, | |
8584 | { Bad_Opcode }, | |
8585 | { Bad_Opcode }, | |
8586 | { Bad_Opcode }, | |
8587 | { Bad_Opcode }, | |
8588 | { Bad_Opcode }, | |
85f10a01 | 8589 | }, |
c0f3af97 L |
8590 | }; |
8591 | ||
8592 | static const struct dis386 vex_table[][256] = { | |
8593 | /* VEX_0F */ | |
85f10a01 MM |
8594 | { |
8595 | /* 00 */ | |
592d1631 L |
8596 | { Bad_Opcode }, |
8597 | { Bad_Opcode }, | |
8598 | { Bad_Opcode }, | |
8599 | { Bad_Opcode }, | |
8600 | { Bad_Opcode }, | |
8601 | { Bad_Opcode }, | |
8602 | { Bad_Opcode }, | |
8603 | { Bad_Opcode }, | |
85f10a01 | 8604 | /* 08 */ |
592d1631 L |
8605 | { Bad_Opcode }, |
8606 | { Bad_Opcode }, | |
8607 | { Bad_Opcode }, | |
8608 | { Bad_Opcode }, | |
8609 | { Bad_Opcode }, | |
8610 | { Bad_Opcode }, | |
8611 | { Bad_Opcode }, | |
8612 | { Bad_Opcode }, | |
c0f3af97 | 8613 | /* 10 */ |
592a252b L |
8614 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8615 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8616 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8617 | { MOD_TABLE (MOD_VEX_0F13) }, | |
8618 | { VEX_W_TABLE (VEX_W_0F14) }, | |
8619 | { VEX_W_TABLE (VEX_W_0F15) }, | |
8620 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, | |
8621 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8622 | /* 18 */ |
592d1631 L |
8623 | { Bad_Opcode }, |
8624 | { Bad_Opcode }, | |
8625 | { Bad_Opcode }, | |
8626 | { Bad_Opcode }, | |
8627 | { Bad_Opcode }, | |
8628 | { Bad_Opcode }, | |
8629 | { Bad_Opcode }, | |
8630 | { Bad_Opcode }, | |
c0f3af97 | 8631 | /* 20 */ |
592d1631 L |
8632 | { Bad_Opcode }, |
8633 | { Bad_Opcode }, | |
8634 | { Bad_Opcode }, | |
8635 | { Bad_Opcode }, | |
8636 | { Bad_Opcode }, | |
8637 | { Bad_Opcode }, | |
8638 | { Bad_Opcode }, | |
8639 | { Bad_Opcode }, | |
c0f3af97 | 8640 | /* 28 */ |
592a252b L |
8641 | { VEX_W_TABLE (VEX_W_0F28) }, |
8642 | { VEX_W_TABLE (VEX_W_0F29) }, | |
8643 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, | |
8644 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8645 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8646 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8647 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8648 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8649 | /* 30 */ |
592d1631 L |
8650 | { Bad_Opcode }, |
8651 | { Bad_Opcode }, | |
8652 | { Bad_Opcode }, | |
8653 | { Bad_Opcode }, | |
8654 | { Bad_Opcode }, | |
8655 | { Bad_Opcode }, | |
8656 | { Bad_Opcode }, | |
8657 | { Bad_Opcode }, | |
4e7d34a6 | 8658 | /* 38 */ |
592d1631 L |
8659 | { Bad_Opcode }, |
8660 | { Bad_Opcode }, | |
8661 | { Bad_Opcode }, | |
8662 | { Bad_Opcode }, | |
8663 | { Bad_Opcode }, | |
8664 | { Bad_Opcode }, | |
8665 | { Bad_Opcode }, | |
8666 | { Bad_Opcode }, | |
d5d7db8e | 8667 | /* 40 */ |
592d1631 | 8668 | { Bad_Opcode }, |
43234a1e L |
8669 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8670 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8671 | { Bad_Opcode }, |
43234a1e L |
8672 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8673 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8674 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8675 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8676 | /* 48 */ |
592d1631 L |
8677 | { Bad_Opcode }, |
8678 | { Bad_Opcode }, | |
1ba585e8 | 8679 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 8680 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8681 | { Bad_Opcode }, |
8682 | { Bad_Opcode }, | |
8683 | { Bad_Opcode }, | |
8684 | { Bad_Opcode }, | |
d5d7db8e | 8685 | /* 50 */ |
592a252b L |
8686 | { MOD_TABLE (MOD_VEX_0F50) }, |
8687 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8688 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8689 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf890a93 IT |
8690 | { "vandpX", { XM, Vex, EXx }, 0 }, |
8691 | { "vandnpX", { XM, Vex, EXx }, 0 }, | |
8692 | { "vorpX", { XM, Vex, EXx }, 0 }, | |
8693 | { "vxorpX", { XM, Vex, EXx }, 0 }, | |
c0f3af97 | 8694 | /* 58 */ |
592a252b L |
8695 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8696 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8697 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8698 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8699 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8700 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8701 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8702 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8703 | /* 60 */ |
592a252b L |
8704 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8705 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8706 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8707 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8708 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8709 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8710 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8711 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8712 | /* 68 */ |
592a252b L |
8713 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8714 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8715 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8716 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8717 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8718 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8719 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8720 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8721 | /* 70 */ |
592a252b L |
8722 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8723 | { REG_TABLE (REG_VEX_0F71) }, | |
8724 | { REG_TABLE (REG_VEX_0F72) }, | |
8725 | { REG_TABLE (REG_VEX_0F73) }, | |
8726 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8727 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8728 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8729 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8730 | /* 78 */ |
592d1631 L |
8731 | { Bad_Opcode }, |
8732 | { Bad_Opcode }, | |
8733 | { Bad_Opcode }, | |
8734 | { Bad_Opcode }, | |
592a252b L |
8735 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8736 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8737 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8738 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8739 | /* 80 */ |
592d1631 L |
8740 | { Bad_Opcode }, |
8741 | { Bad_Opcode }, | |
8742 | { Bad_Opcode }, | |
8743 | { Bad_Opcode }, | |
8744 | { Bad_Opcode }, | |
8745 | { Bad_Opcode }, | |
8746 | { Bad_Opcode }, | |
8747 | { Bad_Opcode }, | |
c0f3af97 | 8748 | /* 88 */ |
592d1631 L |
8749 | { Bad_Opcode }, |
8750 | { Bad_Opcode }, | |
8751 | { Bad_Opcode }, | |
8752 | { Bad_Opcode }, | |
8753 | { Bad_Opcode }, | |
8754 | { Bad_Opcode }, | |
8755 | { Bad_Opcode }, | |
8756 | { Bad_Opcode }, | |
c0f3af97 | 8757 | /* 90 */ |
43234a1e L |
8758 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8759 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8760 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8761 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8762 | { Bad_Opcode }, |
8763 | { Bad_Opcode }, | |
8764 | { Bad_Opcode }, | |
8765 | { Bad_Opcode }, | |
c0f3af97 | 8766 | /* 98 */ |
43234a1e | 8767 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 8768 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
8769 | { Bad_Opcode }, |
8770 | { Bad_Opcode }, | |
8771 | { Bad_Opcode }, | |
8772 | { Bad_Opcode }, | |
8773 | { Bad_Opcode }, | |
8774 | { Bad_Opcode }, | |
c0f3af97 | 8775 | /* a0 */ |
592d1631 L |
8776 | { Bad_Opcode }, |
8777 | { Bad_Opcode }, | |
8778 | { Bad_Opcode }, | |
8779 | { Bad_Opcode }, | |
8780 | { Bad_Opcode }, | |
8781 | { Bad_Opcode }, | |
8782 | { Bad_Opcode }, | |
8783 | { Bad_Opcode }, | |
c0f3af97 | 8784 | /* a8 */ |
592d1631 L |
8785 | { Bad_Opcode }, |
8786 | { Bad_Opcode }, | |
8787 | { Bad_Opcode }, | |
8788 | { Bad_Opcode }, | |
8789 | { Bad_Opcode }, | |
8790 | { Bad_Opcode }, | |
592a252b | 8791 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8792 | { Bad_Opcode }, |
c0f3af97 | 8793 | /* b0 */ |
592d1631 L |
8794 | { Bad_Opcode }, |
8795 | { Bad_Opcode }, | |
8796 | { Bad_Opcode }, | |
8797 | { Bad_Opcode }, | |
8798 | { Bad_Opcode }, | |
8799 | { Bad_Opcode }, | |
8800 | { Bad_Opcode }, | |
8801 | { Bad_Opcode }, | |
c0f3af97 | 8802 | /* b8 */ |
592d1631 L |
8803 | { Bad_Opcode }, |
8804 | { Bad_Opcode }, | |
8805 | { Bad_Opcode }, | |
8806 | { Bad_Opcode }, | |
8807 | { Bad_Opcode }, | |
8808 | { Bad_Opcode }, | |
8809 | { Bad_Opcode }, | |
8810 | { Bad_Opcode }, | |
c0f3af97 | 8811 | /* c0 */ |
592d1631 L |
8812 | { Bad_Opcode }, |
8813 | { Bad_Opcode }, | |
592a252b | 8814 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8815 | { Bad_Opcode }, |
592a252b L |
8816 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8817 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
bf890a93 | 8818 | { "vshufpX", { XM, Vex, EXx, Ib }, 0 }, |
592d1631 | 8819 | { Bad_Opcode }, |
c0f3af97 | 8820 | /* c8 */ |
592d1631 L |
8821 | { Bad_Opcode }, |
8822 | { Bad_Opcode }, | |
8823 | { Bad_Opcode }, | |
8824 | { Bad_Opcode }, | |
8825 | { Bad_Opcode }, | |
8826 | { Bad_Opcode }, | |
8827 | { Bad_Opcode }, | |
8828 | { Bad_Opcode }, | |
c0f3af97 | 8829 | /* d0 */ |
592a252b L |
8830 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8831 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8832 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8833 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8834 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8835 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8836 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8837 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8838 | /* d8 */ |
592a252b L |
8839 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8840 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8841 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8842 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8843 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8844 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8845 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8846 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8847 | /* e0 */ |
592a252b L |
8848 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8849 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8850 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8851 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8852 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8853 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8854 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8855 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8856 | /* e8 */ |
592a252b L |
8857 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8858 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8859 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8860 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8861 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8862 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8863 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8864 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8865 | /* f0 */ |
592a252b L |
8866 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8867 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8868 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8869 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8870 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8871 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8872 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8873 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8874 | /* f8 */ |
592a252b L |
8875 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8876 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8877 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8878 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8879 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8880 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8881 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 8882 | { Bad_Opcode }, |
c0f3af97 L |
8883 | }, |
8884 | /* VEX_0F38 */ | |
8885 | { | |
8886 | /* 00 */ | |
592a252b L |
8887 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8888 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
8889 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
8890 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
8891 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
8892 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
8893 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
8894 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 8895 | /* 08 */ |
592a252b L |
8896 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8897 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
8898 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
8899 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
8900 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
8901 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
8902 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
8903 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 8904 | /* 10 */ |
592d1631 L |
8905 | { Bad_Opcode }, |
8906 | { Bad_Opcode }, | |
8907 | { Bad_Opcode }, | |
592a252b | 8908 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
8909 | { Bad_Opcode }, |
8910 | { Bad_Opcode }, | |
6c30d220 | 8911 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 8912 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 8913 | /* 18 */ |
592a252b L |
8914 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8915 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
8916 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 8917 | { Bad_Opcode }, |
592a252b L |
8918 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8919 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
8920 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 8921 | { Bad_Opcode }, |
c0f3af97 | 8922 | /* 20 */ |
592a252b L |
8923 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8924 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
8925 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
8926 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
8927 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
8928 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
8929 | { Bad_Opcode }, |
8930 | { Bad_Opcode }, | |
c0f3af97 | 8931 | /* 28 */ |
592a252b L |
8932 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8933 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
8934 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
8935 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
8936 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
8937 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
8938 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
8939 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 8940 | /* 30 */ |
592a252b L |
8941 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
8942 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
8943 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
8944 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
8945 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
8946 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 8947 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 8948 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 8949 | /* 38 */ |
592a252b L |
8950 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
8951 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
8952 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
8953 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
8954 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
8955 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
8956 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
8957 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 8958 | /* 40 */ |
592a252b L |
8959 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
8960 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
8961 | { Bad_Opcode }, |
8962 | { Bad_Opcode }, | |
8963 | { Bad_Opcode }, | |
6c30d220 L |
8964 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
8965 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
8966 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 8967 | /* 48 */ |
592d1631 L |
8968 | { Bad_Opcode }, |
8969 | { Bad_Opcode }, | |
8970 | { Bad_Opcode }, | |
8971 | { Bad_Opcode }, | |
8972 | { Bad_Opcode }, | |
8973 | { Bad_Opcode }, | |
8974 | { Bad_Opcode }, | |
8975 | { Bad_Opcode }, | |
c0f3af97 | 8976 | /* 50 */ |
592d1631 L |
8977 | { Bad_Opcode }, |
8978 | { Bad_Opcode }, | |
8979 | { Bad_Opcode }, | |
8980 | { Bad_Opcode }, | |
8981 | { Bad_Opcode }, | |
8982 | { Bad_Opcode }, | |
8983 | { Bad_Opcode }, | |
8984 | { Bad_Opcode }, | |
c0f3af97 | 8985 | /* 58 */ |
6c30d220 L |
8986 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
8987 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
8988 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
8989 | { Bad_Opcode }, |
8990 | { Bad_Opcode }, | |
8991 | { Bad_Opcode }, | |
8992 | { Bad_Opcode }, | |
8993 | { Bad_Opcode }, | |
c0f3af97 | 8994 | /* 60 */ |
592d1631 L |
8995 | { Bad_Opcode }, |
8996 | { Bad_Opcode }, | |
8997 | { Bad_Opcode }, | |
8998 | { Bad_Opcode }, | |
8999 | { Bad_Opcode }, | |
9000 | { Bad_Opcode }, | |
9001 | { Bad_Opcode }, | |
9002 | { Bad_Opcode }, | |
c0f3af97 | 9003 | /* 68 */ |
592d1631 L |
9004 | { Bad_Opcode }, |
9005 | { Bad_Opcode }, | |
9006 | { Bad_Opcode }, | |
9007 | { Bad_Opcode }, | |
9008 | { Bad_Opcode }, | |
9009 | { Bad_Opcode }, | |
9010 | { Bad_Opcode }, | |
9011 | { Bad_Opcode }, | |
c0f3af97 | 9012 | /* 70 */ |
592d1631 L |
9013 | { Bad_Opcode }, |
9014 | { Bad_Opcode }, | |
9015 | { Bad_Opcode }, | |
9016 | { Bad_Opcode }, | |
9017 | { Bad_Opcode }, | |
9018 | { Bad_Opcode }, | |
9019 | { Bad_Opcode }, | |
9020 | { Bad_Opcode }, | |
c0f3af97 | 9021 | /* 78 */ |
6c30d220 L |
9022 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
9023 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
9024 | { Bad_Opcode }, |
9025 | { Bad_Opcode }, | |
9026 | { Bad_Opcode }, | |
9027 | { Bad_Opcode }, | |
9028 | { Bad_Opcode }, | |
9029 | { Bad_Opcode }, | |
c0f3af97 | 9030 | /* 80 */ |
592d1631 L |
9031 | { Bad_Opcode }, |
9032 | { Bad_Opcode }, | |
9033 | { Bad_Opcode }, | |
9034 | { Bad_Opcode }, | |
9035 | { Bad_Opcode }, | |
9036 | { Bad_Opcode }, | |
9037 | { Bad_Opcode }, | |
9038 | { Bad_Opcode }, | |
c0f3af97 | 9039 | /* 88 */ |
592d1631 L |
9040 | { Bad_Opcode }, |
9041 | { Bad_Opcode }, | |
9042 | { Bad_Opcode }, | |
9043 | { Bad_Opcode }, | |
6c30d220 | 9044 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 9045 | { Bad_Opcode }, |
6c30d220 | 9046 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 9047 | { Bad_Opcode }, |
c0f3af97 | 9048 | /* 90 */ |
6c30d220 L |
9049 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
9050 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
9051 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
9052 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
9053 | { Bad_Opcode }, |
9054 | { Bad_Opcode }, | |
592a252b L |
9055 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
9056 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 9057 | /* 98 */ |
592a252b L |
9058 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
9059 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
9060 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
9061 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
9062 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
9063 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
9064 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
9065 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 9066 | /* a0 */ |
592d1631 L |
9067 | { Bad_Opcode }, |
9068 | { Bad_Opcode }, | |
9069 | { Bad_Opcode }, | |
9070 | { Bad_Opcode }, | |
9071 | { Bad_Opcode }, | |
9072 | { Bad_Opcode }, | |
592a252b L |
9073 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
9074 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 9075 | /* a8 */ |
592a252b L |
9076 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
9077 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
9078 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
9079 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
9080 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
9081 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
9082 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
9083 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 9084 | /* b0 */ |
592d1631 L |
9085 | { Bad_Opcode }, |
9086 | { Bad_Opcode }, | |
9087 | { Bad_Opcode }, | |
9088 | { Bad_Opcode }, | |
9089 | { Bad_Opcode }, | |
9090 | { Bad_Opcode }, | |
592a252b L |
9091 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
9092 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 9093 | /* b8 */ |
592a252b L |
9094 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
9095 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
9096 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
9097 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
9098 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
9099 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
9100 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
9101 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 9102 | /* c0 */ |
592d1631 L |
9103 | { Bad_Opcode }, |
9104 | { Bad_Opcode }, | |
9105 | { Bad_Opcode }, | |
9106 | { Bad_Opcode }, | |
9107 | { Bad_Opcode }, | |
9108 | { Bad_Opcode }, | |
9109 | { Bad_Opcode }, | |
9110 | { Bad_Opcode }, | |
c0f3af97 | 9111 | /* c8 */ |
592d1631 L |
9112 | { Bad_Opcode }, |
9113 | { Bad_Opcode }, | |
9114 | { Bad_Opcode }, | |
9115 | { Bad_Opcode }, | |
9116 | { Bad_Opcode }, | |
9117 | { Bad_Opcode }, | |
9118 | { Bad_Opcode }, | |
48521003 | 9119 | { PREFIX_TABLE (PREFIX_VEX_0F38CF) }, |
c0f3af97 | 9120 | /* d0 */ |
592d1631 L |
9121 | { Bad_Opcode }, |
9122 | { Bad_Opcode }, | |
9123 | { Bad_Opcode }, | |
9124 | { Bad_Opcode }, | |
9125 | { Bad_Opcode }, | |
9126 | { Bad_Opcode }, | |
9127 | { Bad_Opcode }, | |
9128 | { Bad_Opcode }, | |
c0f3af97 | 9129 | /* d8 */ |
592d1631 L |
9130 | { Bad_Opcode }, |
9131 | { Bad_Opcode }, | |
9132 | { Bad_Opcode }, | |
592a252b L |
9133 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
9134 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
9135 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
9136 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
9137 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 9138 | /* e0 */ |
592d1631 L |
9139 | { Bad_Opcode }, |
9140 | { Bad_Opcode }, | |
9141 | { Bad_Opcode }, | |
9142 | { Bad_Opcode }, | |
9143 | { Bad_Opcode }, | |
9144 | { Bad_Opcode }, | |
9145 | { Bad_Opcode }, | |
9146 | { Bad_Opcode }, | |
c0f3af97 | 9147 | /* e8 */ |
592d1631 L |
9148 | { Bad_Opcode }, |
9149 | { Bad_Opcode }, | |
9150 | { Bad_Opcode }, | |
9151 | { Bad_Opcode }, | |
9152 | { Bad_Opcode }, | |
9153 | { Bad_Opcode }, | |
9154 | { Bad_Opcode }, | |
9155 | { Bad_Opcode }, | |
c0f3af97 | 9156 | /* f0 */ |
592d1631 L |
9157 | { Bad_Opcode }, |
9158 | { Bad_Opcode }, | |
f12dc422 L |
9159 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
9160 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 9161 | { Bad_Opcode }, |
6c30d220 L |
9162 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
9163 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 9164 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 9165 | /* f8 */ |
592d1631 L |
9166 | { Bad_Opcode }, |
9167 | { Bad_Opcode }, | |
9168 | { Bad_Opcode }, | |
9169 | { Bad_Opcode }, | |
9170 | { Bad_Opcode }, | |
9171 | { Bad_Opcode }, | |
9172 | { Bad_Opcode }, | |
9173 | { Bad_Opcode }, | |
c0f3af97 L |
9174 | }, |
9175 | /* VEX_0F3A */ | |
9176 | { | |
9177 | /* 00 */ | |
6c30d220 L |
9178 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
9179 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
9180 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 9181 | { Bad_Opcode }, |
592a252b L |
9182 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
9183 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
9184 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 9185 | { Bad_Opcode }, |
c0f3af97 | 9186 | /* 08 */ |
592a252b L |
9187 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
9188 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
9189 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
9190 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
9191 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
9192 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
9193 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
9194 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 9195 | /* 10 */ |
592d1631 L |
9196 | { Bad_Opcode }, |
9197 | { Bad_Opcode }, | |
9198 | { Bad_Opcode }, | |
9199 | { Bad_Opcode }, | |
592a252b L |
9200 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
9201 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
9202 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
9203 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 9204 | /* 18 */ |
592a252b L |
9205 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
9206 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
9207 | { Bad_Opcode }, |
9208 | { Bad_Opcode }, | |
9209 | { Bad_Opcode }, | |
592a252b | 9210 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
9211 | { Bad_Opcode }, |
9212 | { Bad_Opcode }, | |
c0f3af97 | 9213 | /* 20 */ |
592a252b L |
9214 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
9215 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
9216 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
9217 | { Bad_Opcode }, |
9218 | { Bad_Opcode }, | |
9219 | { Bad_Opcode }, | |
9220 | { Bad_Opcode }, | |
9221 | { Bad_Opcode }, | |
c0f3af97 | 9222 | /* 28 */ |
592d1631 L |
9223 | { Bad_Opcode }, |
9224 | { Bad_Opcode }, | |
9225 | { Bad_Opcode }, | |
9226 | { Bad_Opcode }, | |
9227 | { Bad_Opcode }, | |
9228 | { Bad_Opcode }, | |
9229 | { Bad_Opcode }, | |
9230 | { Bad_Opcode }, | |
c0f3af97 | 9231 | /* 30 */ |
43234a1e | 9232 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
1ba585e8 | 9233 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
43234a1e | 9234 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
1ba585e8 | 9235 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
592d1631 L |
9236 | { Bad_Opcode }, |
9237 | { Bad_Opcode }, | |
9238 | { Bad_Opcode }, | |
9239 | { Bad_Opcode }, | |
c0f3af97 | 9240 | /* 38 */ |
6c30d220 L |
9241 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
9242 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
9243 | { Bad_Opcode }, |
9244 | { Bad_Opcode }, | |
9245 | { Bad_Opcode }, | |
9246 | { Bad_Opcode }, | |
9247 | { Bad_Opcode }, | |
9248 | { Bad_Opcode }, | |
c0f3af97 | 9249 | /* 40 */ |
592a252b L |
9250 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
9251 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
9252 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 9253 | { Bad_Opcode }, |
592a252b | 9254 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 9255 | { Bad_Opcode }, |
6c30d220 | 9256 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 9257 | { Bad_Opcode }, |
c0f3af97 | 9258 | /* 48 */ |
592a252b L |
9259 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
9260 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
9261 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
9262 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
9263 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
9264 | { Bad_Opcode }, |
9265 | { Bad_Opcode }, | |
9266 | { Bad_Opcode }, | |
c0f3af97 | 9267 | /* 50 */ |
592d1631 L |
9268 | { Bad_Opcode }, |
9269 | { Bad_Opcode }, | |
9270 | { Bad_Opcode }, | |
9271 | { Bad_Opcode }, | |
9272 | { Bad_Opcode }, | |
9273 | { Bad_Opcode }, | |
9274 | { Bad_Opcode }, | |
9275 | { Bad_Opcode }, | |
c0f3af97 | 9276 | /* 58 */ |
592d1631 L |
9277 | { Bad_Opcode }, |
9278 | { Bad_Opcode }, | |
9279 | { Bad_Opcode }, | |
9280 | { Bad_Opcode }, | |
592a252b L |
9281 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
9282 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
9283 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
9284 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 9285 | /* 60 */ |
592a252b L |
9286 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9287 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9288 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9289 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9290 | { Bad_Opcode }, |
9291 | { Bad_Opcode }, | |
9292 | { Bad_Opcode }, | |
9293 | { Bad_Opcode }, | |
c0f3af97 | 9294 | /* 68 */ |
592a252b L |
9295 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9296 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9297 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9298 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9299 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9300 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9301 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9302 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9303 | /* 70 */ |
592d1631 L |
9304 | { Bad_Opcode }, |
9305 | { Bad_Opcode }, | |
9306 | { Bad_Opcode }, | |
9307 | { Bad_Opcode }, | |
9308 | { Bad_Opcode }, | |
9309 | { Bad_Opcode }, | |
9310 | { Bad_Opcode }, | |
9311 | { Bad_Opcode }, | |
c0f3af97 | 9312 | /* 78 */ |
592a252b L |
9313 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9314 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9315 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9316 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9317 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9318 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9319 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9320 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9321 | /* 80 */ |
592d1631 L |
9322 | { Bad_Opcode }, |
9323 | { Bad_Opcode }, | |
9324 | { Bad_Opcode }, | |
9325 | { Bad_Opcode }, | |
9326 | { Bad_Opcode }, | |
9327 | { Bad_Opcode }, | |
9328 | { Bad_Opcode }, | |
9329 | { Bad_Opcode }, | |
c0f3af97 | 9330 | /* 88 */ |
592d1631 L |
9331 | { Bad_Opcode }, |
9332 | { Bad_Opcode }, | |
9333 | { Bad_Opcode }, | |
9334 | { Bad_Opcode }, | |
9335 | { Bad_Opcode }, | |
9336 | { Bad_Opcode }, | |
9337 | { Bad_Opcode }, | |
9338 | { Bad_Opcode }, | |
c0f3af97 | 9339 | /* 90 */ |
592d1631 L |
9340 | { Bad_Opcode }, |
9341 | { Bad_Opcode }, | |
9342 | { Bad_Opcode }, | |
9343 | { Bad_Opcode }, | |
9344 | { Bad_Opcode }, | |
9345 | { Bad_Opcode }, | |
9346 | { Bad_Opcode }, | |
9347 | { Bad_Opcode }, | |
c0f3af97 | 9348 | /* 98 */ |
592d1631 L |
9349 | { Bad_Opcode }, |
9350 | { Bad_Opcode }, | |
9351 | { Bad_Opcode }, | |
9352 | { Bad_Opcode }, | |
9353 | { Bad_Opcode }, | |
9354 | { Bad_Opcode }, | |
9355 | { Bad_Opcode }, | |
9356 | { Bad_Opcode }, | |
c0f3af97 | 9357 | /* a0 */ |
592d1631 L |
9358 | { Bad_Opcode }, |
9359 | { Bad_Opcode }, | |
9360 | { Bad_Opcode }, | |
9361 | { Bad_Opcode }, | |
9362 | { Bad_Opcode }, | |
9363 | { Bad_Opcode }, | |
9364 | { Bad_Opcode }, | |
9365 | { Bad_Opcode }, | |
c0f3af97 | 9366 | /* a8 */ |
592d1631 L |
9367 | { Bad_Opcode }, |
9368 | { Bad_Opcode }, | |
9369 | { Bad_Opcode }, | |
9370 | { Bad_Opcode }, | |
9371 | { Bad_Opcode }, | |
9372 | { Bad_Opcode }, | |
9373 | { Bad_Opcode }, | |
9374 | { Bad_Opcode }, | |
c0f3af97 | 9375 | /* b0 */ |
592d1631 L |
9376 | { Bad_Opcode }, |
9377 | { Bad_Opcode }, | |
9378 | { Bad_Opcode }, | |
9379 | { Bad_Opcode }, | |
9380 | { Bad_Opcode }, | |
9381 | { Bad_Opcode }, | |
9382 | { Bad_Opcode }, | |
9383 | { Bad_Opcode }, | |
c0f3af97 | 9384 | /* b8 */ |
592d1631 L |
9385 | { Bad_Opcode }, |
9386 | { Bad_Opcode }, | |
9387 | { Bad_Opcode }, | |
9388 | { Bad_Opcode }, | |
9389 | { Bad_Opcode }, | |
9390 | { Bad_Opcode }, | |
9391 | { Bad_Opcode }, | |
9392 | { Bad_Opcode }, | |
c0f3af97 | 9393 | /* c0 */ |
592d1631 L |
9394 | { Bad_Opcode }, |
9395 | { Bad_Opcode }, | |
9396 | { Bad_Opcode }, | |
9397 | { Bad_Opcode }, | |
9398 | { Bad_Opcode }, | |
9399 | { Bad_Opcode }, | |
9400 | { Bad_Opcode }, | |
9401 | { Bad_Opcode }, | |
c0f3af97 | 9402 | /* c8 */ |
592d1631 L |
9403 | { Bad_Opcode }, |
9404 | { Bad_Opcode }, | |
9405 | { Bad_Opcode }, | |
9406 | { Bad_Opcode }, | |
9407 | { Bad_Opcode }, | |
9408 | { Bad_Opcode }, | |
48521003 IT |
9409 | { PREFIX_TABLE(PREFIX_VEX_0F3ACE) }, |
9410 | { PREFIX_TABLE(PREFIX_VEX_0F3ACF) }, | |
c0f3af97 | 9411 | /* d0 */ |
592d1631 L |
9412 | { Bad_Opcode }, |
9413 | { Bad_Opcode }, | |
9414 | { Bad_Opcode }, | |
9415 | { Bad_Opcode }, | |
9416 | { Bad_Opcode }, | |
9417 | { Bad_Opcode }, | |
9418 | { Bad_Opcode }, | |
9419 | { Bad_Opcode }, | |
c0f3af97 | 9420 | /* d8 */ |
592d1631 L |
9421 | { Bad_Opcode }, |
9422 | { Bad_Opcode }, | |
9423 | { Bad_Opcode }, | |
9424 | { Bad_Opcode }, | |
9425 | { Bad_Opcode }, | |
9426 | { Bad_Opcode }, | |
9427 | { Bad_Opcode }, | |
592a252b | 9428 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9429 | /* e0 */ |
592d1631 L |
9430 | { Bad_Opcode }, |
9431 | { Bad_Opcode }, | |
9432 | { Bad_Opcode }, | |
9433 | { Bad_Opcode }, | |
9434 | { Bad_Opcode }, | |
9435 | { Bad_Opcode }, | |
9436 | { Bad_Opcode }, | |
9437 | { Bad_Opcode }, | |
c0f3af97 | 9438 | /* e8 */ |
592d1631 L |
9439 | { Bad_Opcode }, |
9440 | { Bad_Opcode }, | |
9441 | { Bad_Opcode }, | |
9442 | { Bad_Opcode }, | |
9443 | { Bad_Opcode }, | |
9444 | { Bad_Opcode }, | |
9445 | { Bad_Opcode }, | |
9446 | { Bad_Opcode }, | |
c0f3af97 | 9447 | /* f0 */ |
6c30d220 | 9448 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9449 | { Bad_Opcode }, |
9450 | { Bad_Opcode }, | |
9451 | { Bad_Opcode }, | |
9452 | { Bad_Opcode }, | |
9453 | { Bad_Opcode }, | |
9454 | { Bad_Opcode }, | |
9455 | { Bad_Opcode }, | |
c0f3af97 | 9456 | /* f8 */ |
592d1631 L |
9457 | { Bad_Opcode }, |
9458 | { Bad_Opcode }, | |
9459 | { Bad_Opcode }, | |
9460 | { Bad_Opcode }, | |
9461 | { Bad_Opcode }, | |
9462 | { Bad_Opcode }, | |
9463 | { Bad_Opcode }, | |
9464 | { Bad_Opcode }, | |
c0f3af97 L |
9465 | }, |
9466 | }; | |
9467 | ||
43234a1e L |
9468 | #define NEED_OPCODE_TABLE |
9469 | #include "i386-dis-evex.h" | |
9470 | #undef NEED_OPCODE_TABLE | |
c0f3af97 | 9471 | static const struct dis386 vex_len_table[][2] = { |
592a252b | 9472 | /* VEX_LEN_0F10_P_1 */ |
c0f3af97 | 9473 | { |
592a252b L |
9474 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, |
9475 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, | |
c0f3af97 L |
9476 | }, |
9477 | ||
592a252b | 9478 | /* VEX_LEN_0F10_P_3 */ |
c0f3af97 | 9479 | { |
592a252b L |
9480 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, |
9481 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, | |
c0f3af97 L |
9482 | }, |
9483 | ||
592a252b | 9484 | /* VEX_LEN_0F11_P_1 */ |
c0f3af97 | 9485 | { |
592a252b L |
9486 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, |
9487 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, | |
c0f3af97 L |
9488 | }, |
9489 | ||
592a252b | 9490 | /* VEX_LEN_0F11_P_3 */ |
c0f3af97 | 9491 | { |
592a252b L |
9492 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, |
9493 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, | |
c0f3af97 L |
9494 | }, |
9495 | ||
592a252b | 9496 | /* VEX_LEN_0F12_P_0_M_0 */ |
c0f3af97 | 9497 | { |
592a252b | 9498 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, |
c0f3af97 L |
9499 | }, |
9500 | ||
592a252b | 9501 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9502 | { |
592a252b | 9503 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, |
c0f3af97 L |
9504 | }, |
9505 | ||
592a252b | 9506 | /* VEX_LEN_0F12_P_2 */ |
c0f3af97 | 9507 | { |
592a252b | 9508 | { VEX_W_TABLE (VEX_W_0F12_P_2) }, |
c0f3af97 L |
9509 | }, |
9510 | ||
592a252b | 9511 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9512 | { |
592a252b | 9513 | { VEX_W_TABLE (VEX_W_0F13_M_0) }, |
c0f3af97 L |
9514 | }, |
9515 | ||
592a252b | 9516 | /* VEX_LEN_0F16_P_0_M_0 */ |
c0f3af97 | 9517 | { |
592a252b | 9518 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, |
c0f3af97 L |
9519 | }, |
9520 | ||
592a252b | 9521 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9522 | { |
592a252b | 9523 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, |
c0f3af97 L |
9524 | }, |
9525 | ||
592a252b | 9526 | /* VEX_LEN_0F16_P_2 */ |
c0f3af97 | 9527 | { |
592a252b | 9528 | { VEX_W_TABLE (VEX_W_0F16_P_2) }, |
c0f3af97 L |
9529 | }, |
9530 | ||
592a252b | 9531 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9532 | { |
592a252b | 9533 | { VEX_W_TABLE (VEX_W_0F17_M_0) }, |
c0f3af97 L |
9534 | }, |
9535 | ||
592a252b | 9536 | /* VEX_LEN_0F2A_P_1 */ |
c0f3af97 | 9537 | { |
bf890a93 IT |
9538 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9539 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, | |
c0f3af97 L |
9540 | }, |
9541 | ||
592a252b | 9542 | /* VEX_LEN_0F2A_P_3 */ |
c0f3af97 | 9543 | { |
bf890a93 IT |
9544 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9545 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, | |
c0f3af97 L |
9546 | }, |
9547 | ||
592a252b | 9548 | /* VEX_LEN_0F2C_P_1 */ |
c0f3af97 | 9549 | { |
bf890a93 IT |
9550 | { "vcvttss2siY", { Gv, EXdScalar }, 0 }, |
9551 | { "vcvttss2siY", { Gv, EXdScalar }, 0 }, | |
c0f3af97 L |
9552 | }, |
9553 | ||
592a252b | 9554 | /* VEX_LEN_0F2C_P_3 */ |
c0f3af97 | 9555 | { |
bf890a93 IT |
9556 | { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, |
9557 | { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, | |
c0f3af97 L |
9558 | }, |
9559 | ||
592a252b | 9560 | /* VEX_LEN_0F2D_P_1 */ |
c0f3af97 | 9561 | { |
bf890a93 IT |
9562 | { "vcvtss2siY", { Gv, EXdScalar }, 0 }, |
9563 | { "vcvtss2siY", { Gv, EXdScalar }, 0 }, | |
c0f3af97 L |
9564 | }, |
9565 | ||
592a252b | 9566 | /* VEX_LEN_0F2D_P_3 */ |
c0f3af97 | 9567 | { |
bf890a93 IT |
9568 | { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, |
9569 | { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, | |
c0f3af97 L |
9570 | }, |
9571 | ||
592a252b | 9572 | /* VEX_LEN_0F2E_P_0 */ |
c0f3af97 | 9573 | { |
592a252b L |
9574 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, |
9575 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, | |
c0f3af97 L |
9576 | }, |
9577 | ||
592a252b | 9578 | /* VEX_LEN_0F2E_P_2 */ |
c0f3af97 | 9579 | { |
592a252b L |
9580 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, |
9581 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, | |
c0f3af97 L |
9582 | }, |
9583 | ||
592a252b | 9584 | /* VEX_LEN_0F2F_P_0 */ |
c0f3af97 | 9585 | { |
592a252b L |
9586 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, |
9587 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, | |
c0f3af97 L |
9588 | }, |
9589 | ||
592a252b | 9590 | /* VEX_LEN_0F2F_P_2 */ |
c0f3af97 | 9591 | { |
592a252b L |
9592 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, |
9593 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, | |
c0f3af97 L |
9594 | }, |
9595 | ||
43234a1e L |
9596 | /* VEX_LEN_0F41_P_0 */ |
9597 | { | |
9598 | { Bad_Opcode }, | |
9599 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9600 | }, | |
1ba585e8 IT |
9601 | /* VEX_LEN_0F41_P_2 */ |
9602 | { | |
9603 | { Bad_Opcode }, | |
9604 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
9605 | }, | |
43234a1e L |
9606 | /* VEX_LEN_0F42_P_0 */ |
9607 | { | |
9608 | { Bad_Opcode }, | |
9609 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9610 | }, | |
1ba585e8 IT |
9611 | /* VEX_LEN_0F42_P_2 */ |
9612 | { | |
9613 | { Bad_Opcode }, | |
9614 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
9615 | }, | |
43234a1e L |
9616 | /* VEX_LEN_0F44_P_0 */ |
9617 | { | |
9618 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9619 | }, | |
1ba585e8 IT |
9620 | /* VEX_LEN_0F44_P_2 */ |
9621 | { | |
9622 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
9623 | }, | |
43234a1e L |
9624 | /* VEX_LEN_0F45_P_0 */ |
9625 | { | |
9626 | { Bad_Opcode }, | |
9627 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9628 | }, | |
1ba585e8 IT |
9629 | /* VEX_LEN_0F45_P_2 */ |
9630 | { | |
9631 | { Bad_Opcode }, | |
9632 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
9633 | }, | |
43234a1e L |
9634 | /* VEX_LEN_0F46_P_0 */ |
9635 | { | |
9636 | { Bad_Opcode }, | |
9637 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9638 | }, | |
1ba585e8 IT |
9639 | /* VEX_LEN_0F46_P_2 */ |
9640 | { | |
9641 | { Bad_Opcode }, | |
9642 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
9643 | }, | |
43234a1e L |
9644 | /* VEX_LEN_0F47_P_0 */ |
9645 | { | |
9646 | { Bad_Opcode }, | |
9647 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9648 | }, | |
1ba585e8 IT |
9649 | /* VEX_LEN_0F47_P_2 */ |
9650 | { | |
9651 | { Bad_Opcode }, | |
9652 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
9653 | }, | |
9654 | /* VEX_LEN_0F4A_P_0 */ | |
9655 | { | |
9656 | { Bad_Opcode }, | |
9657 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
9658 | }, | |
9659 | /* VEX_LEN_0F4A_P_2 */ | |
9660 | { | |
9661 | { Bad_Opcode }, | |
9662 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
9663 | }, | |
9664 | /* VEX_LEN_0F4B_P_0 */ | |
9665 | { | |
9666 | { Bad_Opcode }, | |
9667 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
9668 | }, | |
43234a1e L |
9669 | /* VEX_LEN_0F4B_P_2 */ |
9670 | { | |
9671 | { Bad_Opcode }, | |
9672 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9673 | }, | |
9674 | ||
592a252b | 9675 | /* VEX_LEN_0F51_P_1 */ |
c0f3af97 | 9676 | { |
592a252b L |
9677 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, |
9678 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, | |
c0f3af97 L |
9679 | }, |
9680 | ||
592a252b | 9681 | /* VEX_LEN_0F51_P_3 */ |
c0f3af97 | 9682 | { |
592a252b L |
9683 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, |
9684 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, | |
c0f3af97 L |
9685 | }, |
9686 | ||
592a252b | 9687 | /* VEX_LEN_0F52_P_1 */ |
c0f3af97 | 9688 | { |
592a252b L |
9689 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, |
9690 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, | |
c0f3af97 L |
9691 | }, |
9692 | ||
592a252b | 9693 | /* VEX_LEN_0F53_P_1 */ |
c0f3af97 | 9694 | { |
592a252b L |
9695 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, |
9696 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, | |
c0f3af97 L |
9697 | }, |
9698 | ||
592a252b | 9699 | /* VEX_LEN_0F58_P_1 */ |
c0f3af97 | 9700 | { |
592a252b L |
9701 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, |
9702 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, | |
c0f3af97 L |
9703 | }, |
9704 | ||
592a252b | 9705 | /* VEX_LEN_0F58_P_3 */ |
c0f3af97 | 9706 | { |
592a252b L |
9707 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, |
9708 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, | |
c0f3af97 L |
9709 | }, |
9710 | ||
592a252b | 9711 | /* VEX_LEN_0F59_P_1 */ |
c0f3af97 | 9712 | { |
592a252b L |
9713 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, |
9714 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, | |
c0f3af97 L |
9715 | }, |
9716 | ||
592a252b | 9717 | /* VEX_LEN_0F59_P_3 */ |
c0f3af97 | 9718 | { |
592a252b L |
9719 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, |
9720 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, | |
c0f3af97 L |
9721 | }, |
9722 | ||
592a252b | 9723 | /* VEX_LEN_0F5A_P_1 */ |
c0f3af97 | 9724 | { |
592a252b L |
9725 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, |
9726 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, | |
c0f3af97 L |
9727 | }, |
9728 | ||
592a252b | 9729 | /* VEX_LEN_0F5A_P_3 */ |
c0f3af97 | 9730 | { |
592a252b L |
9731 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, |
9732 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, | |
c0f3af97 L |
9733 | }, |
9734 | ||
592a252b | 9735 | /* VEX_LEN_0F5C_P_1 */ |
c0f3af97 | 9736 | { |
592a252b L |
9737 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, |
9738 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, | |
c0f3af97 L |
9739 | }, |
9740 | ||
592a252b | 9741 | /* VEX_LEN_0F5C_P_3 */ |
c0f3af97 | 9742 | { |
592a252b L |
9743 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, |
9744 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, | |
c0f3af97 L |
9745 | }, |
9746 | ||
592a252b | 9747 | /* VEX_LEN_0F5D_P_1 */ |
c0f3af97 | 9748 | { |
592a252b L |
9749 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, |
9750 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, | |
c0f3af97 L |
9751 | }, |
9752 | ||
592a252b | 9753 | /* VEX_LEN_0F5D_P_3 */ |
c0f3af97 | 9754 | { |
592a252b L |
9755 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, |
9756 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, | |
c0f3af97 L |
9757 | }, |
9758 | ||
592a252b | 9759 | /* VEX_LEN_0F5E_P_1 */ |
c0f3af97 | 9760 | { |
592a252b L |
9761 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, |
9762 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, | |
c0f3af97 L |
9763 | }, |
9764 | ||
592a252b | 9765 | /* VEX_LEN_0F5E_P_3 */ |
c0f3af97 | 9766 | { |
592a252b L |
9767 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, |
9768 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, | |
c0f3af97 L |
9769 | }, |
9770 | ||
592a252b | 9771 | /* VEX_LEN_0F5F_P_1 */ |
c0f3af97 | 9772 | { |
592a252b L |
9773 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, |
9774 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, | |
c0f3af97 L |
9775 | }, |
9776 | ||
592a252b | 9777 | /* VEX_LEN_0F5F_P_3 */ |
c0f3af97 | 9778 | { |
592a252b L |
9779 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
9780 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, | |
c0f3af97 L |
9781 | }, |
9782 | ||
592a252b | 9783 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9784 | { |
bf890a93 IT |
9785 | { "vmovK", { XMScalar, Edq }, 0 }, |
9786 | { "vmovK", { XMScalar, Edq }, 0 }, | |
c0f3af97 L |
9787 | }, |
9788 | ||
592a252b | 9789 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9790 | { |
592a252b L |
9791 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
9792 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, | |
c0f3af97 L |
9793 | }, |
9794 | ||
592a252b | 9795 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9796 | { |
bf890a93 IT |
9797 | { "vmovK", { Edq, XMScalar }, 0 }, |
9798 | { "vmovK", { Edq, XMScalar }, 0 }, | |
c0f3af97 L |
9799 | }, |
9800 | ||
43234a1e L |
9801 | /* VEX_LEN_0F90_P_0 */ |
9802 | { | |
9803 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, | |
9804 | }, | |
9805 | ||
1ba585e8 IT |
9806 | /* VEX_LEN_0F90_P_2 */ |
9807 | { | |
9808 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, | |
9809 | }, | |
9810 | ||
43234a1e L |
9811 | /* VEX_LEN_0F91_P_0 */ |
9812 | { | |
9813 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, | |
9814 | }, | |
9815 | ||
1ba585e8 IT |
9816 | /* VEX_LEN_0F91_P_2 */ |
9817 | { | |
9818 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, | |
9819 | }, | |
9820 | ||
43234a1e L |
9821 | /* VEX_LEN_0F92_P_0 */ |
9822 | { | |
9823 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, | |
9824 | }, | |
9825 | ||
90a915bf IT |
9826 | /* VEX_LEN_0F92_P_2 */ |
9827 | { | |
9828 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, | |
9829 | }, | |
9830 | ||
1ba585e8 IT |
9831 | /* VEX_LEN_0F92_P_3 */ |
9832 | { | |
9833 | { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) }, | |
9834 | }, | |
9835 | ||
43234a1e L |
9836 | /* VEX_LEN_0F93_P_0 */ |
9837 | { | |
9838 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, | |
9839 | }, | |
9840 | ||
90a915bf IT |
9841 | /* VEX_LEN_0F93_P_2 */ |
9842 | { | |
9843 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, | |
9844 | }, | |
9845 | ||
1ba585e8 IT |
9846 | /* VEX_LEN_0F93_P_3 */ |
9847 | { | |
9848 | { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) }, | |
9849 | }, | |
9850 | ||
43234a1e L |
9851 | /* VEX_LEN_0F98_P_0 */ |
9852 | { | |
9853 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9854 | }, | |
9855 | ||
1ba585e8 IT |
9856 | /* VEX_LEN_0F98_P_2 */ |
9857 | { | |
9858 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
9859 | }, | |
9860 | ||
9861 | /* VEX_LEN_0F99_P_0 */ | |
9862 | { | |
9863 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
9864 | }, | |
9865 | ||
9866 | /* VEX_LEN_0F99_P_2 */ | |
9867 | { | |
9868 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
9869 | }, | |
9870 | ||
6c30d220 | 9871 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9872 | { |
6c30d220 | 9873 | { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, |
c0f3af97 L |
9874 | }, |
9875 | ||
6c30d220 | 9876 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9877 | { |
6c30d220 | 9878 | { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, |
c0f3af97 L |
9879 | }, |
9880 | ||
6c30d220 | 9881 | /* VEX_LEN_0FC2_P_1 */ |
c0f3af97 | 9882 | { |
6c30d220 L |
9883 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, |
9884 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, | |
c0f3af97 L |
9885 | }, |
9886 | ||
6c30d220 | 9887 | /* VEX_LEN_0FC2_P_3 */ |
c0f3af97 | 9888 | { |
6c30d220 L |
9889 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, |
9890 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, | |
c0f3af97 L |
9891 | }, |
9892 | ||
6c30d220 | 9893 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 9894 | { |
6c30d220 | 9895 | { VEX_W_TABLE (VEX_W_0FC4_P_2) }, |
c0f3af97 L |
9896 | }, |
9897 | ||
6c30d220 | 9898 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 9899 | { |
6c30d220 | 9900 | { VEX_W_TABLE (VEX_W_0FC5_P_2) }, |
c0f3af97 L |
9901 | }, |
9902 | ||
6c30d220 | 9903 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 9904 | { |
6c30d220 L |
9905 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, |
9906 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, | |
c0f3af97 L |
9907 | }, |
9908 | ||
6c30d220 | 9909 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 9910 | { |
6c30d220 | 9911 | { VEX_W_TABLE (VEX_W_0FF7_P_2) }, |
c0f3af97 L |
9912 | }, |
9913 | ||
6c30d220 | 9914 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 9915 | { |
6c30d220 L |
9916 | { Bad_Opcode }, |
9917 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
9918 | }, |
9919 | ||
6c30d220 | 9920 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 9921 | { |
6c30d220 L |
9922 | { Bad_Opcode }, |
9923 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
9924 | }, |
9925 | ||
6c30d220 | 9926 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 9927 | { |
6c30d220 L |
9928 | { Bad_Opcode }, |
9929 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
9930 | }, |
9931 | ||
6c30d220 | 9932 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 9933 | { |
6c30d220 L |
9934 | { Bad_Opcode }, |
9935 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
9936 | }, |
9937 | ||
592a252b | 9938 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 9939 | { |
592a252b | 9940 | { VEX_W_TABLE (VEX_W_0F3841_P_2) }, |
c0f3af97 L |
9941 | }, |
9942 | ||
6c30d220 L |
9943 | /* VEX_LEN_0F385A_P_2_M_0 */ |
9944 | { | |
9945 | { Bad_Opcode }, | |
9946 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
9947 | }, | |
9948 | ||
592a252b | 9949 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 9950 | { |
592a252b | 9951 | { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, |
a5ff0eb2 L |
9952 | }, |
9953 | ||
f12dc422 L |
9954 | /* VEX_LEN_0F38F2_P_0 */ |
9955 | { | |
bf890a93 | 9956 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
f12dc422 L |
9957 | }, |
9958 | ||
9959 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
9960 | { | |
bf890a93 | 9961 | { "blsrS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9962 | }, |
9963 | ||
9964 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
9965 | { | |
bf890a93 | 9966 | { "blsmskS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9967 | }, |
9968 | ||
9969 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
9970 | { | |
bf890a93 | 9971 | { "blsiS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9972 | }, |
9973 | ||
6c30d220 L |
9974 | /* VEX_LEN_0F38F5_P_0 */ |
9975 | { | |
bf890a93 | 9976 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9977 | }, |
9978 | ||
9979 | /* VEX_LEN_0F38F5_P_1 */ | |
9980 | { | |
bf890a93 | 9981 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9982 | }, |
9983 | ||
9984 | /* VEX_LEN_0F38F5_P_3 */ | |
9985 | { | |
bf890a93 | 9986 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9987 | }, |
9988 | ||
9989 | /* VEX_LEN_0F38F6_P_3 */ | |
9990 | { | |
bf890a93 | 9991 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9992 | }, |
9993 | ||
f12dc422 L |
9994 | /* VEX_LEN_0F38F7_P_0 */ |
9995 | { | |
bf890a93 | 9996 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
9997 | }, |
9998 | ||
6c30d220 L |
9999 | /* VEX_LEN_0F38F7_P_1 */ |
10000 | { | |
bf890a93 | 10001 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10002 | }, |
10003 | ||
10004 | /* VEX_LEN_0F38F7_P_2 */ | |
10005 | { | |
bf890a93 | 10006 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10007 | }, |
10008 | ||
10009 | /* VEX_LEN_0F38F7_P_3 */ | |
10010 | { | |
bf890a93 | 10011 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10012 | }, |
10013 | ||
10014 | /* VEX_LEN_0F3A00_P_2 */ | |
10015 | { | |
10016 | { Bad_Opcode }, | |
10017 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
10018 | }, | |
10019 | ||
10020 | /* VEX_LEN_0F3A01_P_2 */ | |
10021 | { | |
10022 | { Bad_Opcode }, | |
10023 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
10024 | }, | |
10025 | ||
592a252b | 10026 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 10027 | { |
592d1631 | 10028 | { Bad_Opcode }, |
592a252b | 10029 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
10030 | }, |
10031 | ||
592a252b | 10032 | /* VEX_LEN_0F3A0A_P_2 */ |
c0f3af97 | 10033 | { |
592a252b L |
10034 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, |
10035 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, | |
c0f3af97 L |
10036 | }, |
10037 | ||
592a252b | 10038 | /* VEX_LEN_0F3A0B_P_2 */ |
c0f3af97 | 10039 | { |
592a252b L |
10040 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, |
10041 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, | |
c0f3af97 L |
10042 | }, |
10043 | ||
592a252b | 10044 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 10045 | { |
592a252b | 10046 | { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, |
c0f3af97 L |
10047 | }, |
10048 | ||
592a252b | 10049 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 10050 | { |
592a252b | 10051 | { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, |
c0f3af97 L |
10052 | }, |
10053 | ||
592a252b | 10054 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 | 10055 | { |
bf890a93 | 10056 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
c0f3af97 L |
10057 | }, |
10058 | ||
592a252b | 10059 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 | 10060 | { |
bf890a93 | 10061 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
c0f3af97 L |
10062 | }, |
10063 | ||
592a252b | 10064 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 10065 | { |
592d1631 | 10066 | { Bad_Opcode }, |
592a252b | 10067 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
10068 | }, |
10069 | ||
592a252b | 10070 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 10071 | { |
592d1631 | 10072 | { Bad_Opcode }, |
592a252b | 10073 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
10074 | }, |
10075 | ||
592a252b | 10076 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 10077 | { |
592a252b | 10078 | { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, |
c0f3af97 L |
10079 | }, |
10080 | ||
592a252b | 10081 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 10082 | { |
592a252b | 10083 | { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, |
c0f3af97 L |
10084 | }, |
10085 | ||
592a252b | 10086 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 | 10087 | { |
bf890a93 | 10088 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
c0f3af97 L |
10089 | }, |
10090 | ||
43234a1e L |
10091 | /* VEX_LEN_0F3A30_P_2 */ |
10092 | { | |
10093 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
10094 | }, | |
10095 | ||
1ba585e8 IT |
10096 | /* VEX_LEN_0F3A31_P_2 */ |
10097 | { | |
10098 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, | |
10099 | }, | |
10100 | ||
43234a1e L |
10101 | /* VEX_LEN_0F3A32_P_2 */ |
10102 | { | |
10103 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
10104 | }, | |
10105 | ||
1ba585e8 IT |
10106 | /* VEX_LEN_0F3A33_P_2 */ |
10107 | { | |
10108 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, | |
10109 | }, | |
10110 | ||
6c30d220 | 10111 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 10112 | { |
6c30d220 L |
10113 | { Bad_Opcode }, |
10114 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
10115 | }, |
10116 | ||
6c30d220 | 10117 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 10118 | { |
6c30d220 L |
10119 | { Bad_Opcode }, |
10120 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
10121 | }, | |
10122 | ||
10123 | /* VEX_LEN_0F3A41_P_2 */ | |
10124 | { | |
10125 | { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, | |
c0f3af97 L |
10126 | }, |
10127 | ||
6c30d220 | 10128 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 10129 | { |
6c30d220 L |
10130 | { Bad_Opcode }, |
10131 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
10132 | }, |
10133 | ||
592a252b | 10134 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 10135 | { |
15c7c1d8 | 10136 | { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
10137 | }, |
10138 | ||
592a252b | 10139 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 10140 | { |
15c7c1d8 | 10141 | { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
10142 | }, |
10143 | ||
592a252b | 10144 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 10145 | { |
592a252b | 10146 | { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, |
c0f3af97 L |
10147 | }, |
10148 | ||
592a252b | 10149 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 10150 | { |
592a252b | 10151 | { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, |
c0f3af97 L |
10152 | }, |
10153 | ||
592a252b | 10154 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 10155 | { |
3a2430e0 | 10156 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
10157 | }, |
10158 | ||
592a252b | 10159 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 10160 | { |
3a2430e0 | 10161 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
10162 | }, |
10163 | ||
592a252b | 10164 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 10165 | { |
3a2430e0 | 10166 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
10167 | }, |
10168 | ||
592a252b | 10169 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 10170 | { |
3a2430e0 | 10171 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
10172 | }, |
10173 | ||
592a252b | 10174 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 10175 | { |
3a2430e0 | 10176 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
10177 | }, |
10178 | ||
592a252b | 10179 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 10180 | { |
3a2430e0 | 10181 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
10182 | }, |
10183 | ||
592a252b | 10184 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 10185 | { |
3a2430e0 | 10186 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
10187 | }, |
10188 | ||
592a252b | 10189 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 10190 | { |
3a2430e0 | 10191 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
10192 | }, |
10193 | ||
592a252b | 10194 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 10195 | { |
592a252b | 10196 | { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, |
a5ff0eb2 | 10197 | }, |
4c807e72 | 10198 | |
6c30d220 L |
10199 | /* VEX_LEN_0F3AF0_P_3 */ |
10200 | { | |
bf890a93 | 10201 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
10202 | }, |
10203 | ||
ff688e1f L |
10204 | /* VEX_LEN_0FXOP_08_CC */ |
10205 | { | |
be92cb14 | 10206 | { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10207 | }, |
10208 | ||
10209 | /* VEX_LEN_0FXOP_08_CD */ | |
10210 | { | |
be92cb14 | 10211 | { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10212 | }, |
10213 | ||
10214 | /* VEX_LEN_0FXOP_08_CE */ | |
10215 | { | |
be92cb14 | 10216 | { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10217 | }, |
10218 | ||
10219 | /* VEX_LEN_0FXOP_08_CF */ | |
10220 | { | |
be92cb14 | 10221 | { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10222 | }, |
10223 | ||
10224 | /* VEX_LEN_0FXOP_08_EC */ | |
10225 | { | |
be92cb14 | 10226 | { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10227 | }, |
10228 | ||
10229 | /* VEX_LEN_0FXOP_08_ED */ | |
10230 | { | |
be92cb14 | 10231 | { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10232 | }, |
10233 | ||
10234 | /* VEX_LEN_0FXOP_08_EE */ | |
10235 | { | |
be92cb14 | 10236 | { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10237 | }, |
10238 | ||
10239 | /* VEX_LEN_0FXOP_08_EF */ | |
10240 | { | |
be92cb14 | 10241 | { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10242 | }, |
10243 | ||
592a252b | 10244 | /* VEX_LEN_0FXOP_09_80 */ |
5dd85c99 | 10245 | { |
bf890a93 IT |
10246 | { "vfrczps", { XM, EXxmm }, 0 }, |
10247 | { "vfrczps", { XM, EXymmq }, 0 }, | |
5dd85c99 | 10248 | }, |
4c807e72 | 10249 | |
592a252b | 10250 | /* VEX_LEN_0FXOP_09_81 */ |
5dd85c99 | 10251 | { |
bf890a93 IT |
10252 | { "vfrczpd", { XM, EXxmm }, 0 }, |
10253 | { "vfrczpd", { XM, EXymmq }, 0 }, | |
5dd85c99 | 10254 | }, |
331d2d0d L |
10255 | }; |
10256 | ||
9e30b8e0 | 10257 | static const struct dis386 vex_w_table[][2] = { |
b844680a | 10258 | { |
592a252b | 10259 | /* VEX_W_0F10_P_0 */ |
bf890a93 | 10260 | { "vmovups", { XM, EXx }, 0 }, |
d8faab4e L |
10261 | }, |
10262 | { | |
592a252b | 10263 | /* VEX_W_0F10_P_1 */ |
bf890a93 | 10264 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, |
d8faab4e L |
10265 | }, |
10266 | { | |
592a252b | 10267 | /* VEX_W_0F10_P_2 */ |
bf890a93 | 10268 | { "vmovupd", { XM, EXx }, 0 }, |
d8faab4e L |
10269 | }, |
10270 | { | |
592a252b | 10271 | /* VEX_W_0F10_P_3 */ |
bf890a93 | 10272 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, |
d8faab4e L |
10273 | }, |
10274 | { | |
592a252b | 10275 | /* VEX_W_0F11_P_0 */ |
bf890a93 | 10276 | { "vmovups", { EXxS, XM }, 0 }, |
d8faab4e L |
10277 | }, |
10278 | { | |
592a252b | 10279 | /* VEX_W_0F11_P_1 */ |
bf890a93 | 10280 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, |
b844680a L |
10281 | }, |
10282 | { | |
592a252b | 10283 | /* VEX_W_0F11_P_2 */ |
bf890a93 | 10284 | { "vmovupd", { EXxS, XM }, 0 }, |
b844680a L |
10285 | }, |
10286 | { | |
592a252b | 10287 | /* VEX_W_0F11_P_3 */ |
bf890a93 | 10288 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, |
d8faab4e L |
10289 | }, |
10290 | { | |
592a252b | 10291 | /* VEX_W_0F12_P_0_M_0 */ |
bf890a93 | 10292 | { "vmovlps", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10293 | }, |
10294 | { | |
592a252b | 10295 | /* VEX_W_0F12_P_0_M_1 */ |
bf890a93 | 10296 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10297 | }, |
10298 | { | |
592a252b | 10299 | /* VEX_W_0F12_P_1 */ |
bf890a93 | 10300 | { "vmovsldup", { XM, EXx }, 0 }, |
b844680a L |
10301 | }, |
10302 | { | |
592a252b | 10303 | /* VEX_W_0F12_P_2 */ |
bf890a93 | 10304 | { "vmovlpd", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10305 | }, |
10306 | { | |
592a252b | 10307 | /* VEX_W_0F12_P_3 */ |
bf890a93 | 10308 | { "vmovddup", { XM, EXymmq }, 0 }, |
b844680a L |
10309 | }, |
10310 | { | |
592a252b | 10311 | /* VEX_W_0F13_M_0 */ |
bf890a93 | 10312 | { "vmovlpX", { EXq, XM }, 0 }, |
b844680a L |
10313 | }, |
10314 | { | |
592a252b | 10315 | /* VEX_W_0F14 */ |
bf890a93 | 10316 | { "vunpcklpX", { XM, Vex, EXx }, 0 }, |
b844680a L |
10317 | }, |
10318 | { | |
592a252b | 10319 | /* VEX_W_0F15 */ |
bf890a93 | 10320 | { "vunpckhpX", { XM, Vex, EXx }, 0 }, |
b844680a L |
10321 | }, |
10322 | { | |
592a252b | 10323 | /* VEX_W_0F16_P_0_M_0 */ |
bf890a93 | 10324 | { "vmovhps", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10325 | }, |
10326 | { | |
592a252b | 10327 | /* VEX_W_0F16_P_0_M_1 */ |
bf890a93 | 10328 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10329 | }, |
10330 | { | |
592a252b | 10331 | /* VEX_W_0F16_P_1 */ |
bf890a93 | 10332 | { "vmovshdup", { XM, EXx }, 0 }, |
9e30b8e0 L |
10333 | }, |
10334 | { | |
592a252b | 10335 | /* VEX_W_0F16_P_2 */ |
bf890a93 | 10336 | { "vmovhpd", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10337 | }, |
10338 | { | |
592a252b | 10339 | /* VEX_W_0F17_M_0 */ |
bf890a93 | 10340 | { "vmovhpX", { EXq, XM }, 0 }, |
9e30b8e0 L |
10341 | }, |
10342 | { | |
592a252b | 10343 | /* VEX_W_0F28 */ |
bf890a93 | 10344 | { "vmovapX", { XM, EXx }, 0 }, |
9e30b8e0 L |
10345 | }, |
10346 | { | |
592a252b | 10347 | /* VEX_W_0F29 */ |
bf890a93 | 10348 | { "vmovapX", { EXxS, XM }, 0 }, |
9e30b8e0 L |
10349 | }, |
10350 | { | |
592a252b | 10351 | /* VEX_W_0F2B_M_0 */ |
bf890a93 | 10352 | { "vmovntpX", { Mx, XM }, 0 }, |
9e30b8e0 L |
10353 | }, |
10354 | { | |
592a252b | 10355 | /* VEX_W_0F2E_P_0 */ |
bf890a93 | 10356 | { "vucomiss", { XMScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10357 | }, |
10358 | { | |
592a252b | 10359 | /* VEX_W_0F2E_P_2 */ |
bf890a93 | 10360 | { "vucomisd", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10361 | }, |
10362 | { | |
592a252b | 10363 | /* VEX_W_0F2F_P_0 */ |
bf890a93 | 10364 | { "vcomiss", { XMScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10365 | }, |
10366 | { | |
592a252b | 10367 | /* VEX_W_0F2F_P_2 */ |
bf890a93 | 10368 | { "vcomisd", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 | 10369 | }, |
43234a1e L |
10370 | { |
10371 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10372 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
10373 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
10374 | }, |
10375 | { | |
10376 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10377 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
10378 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
10379 | }, |
10380 | { | |
10381 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10382 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
10383 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
10384 | }, |
10385 | { | |
10386 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10387 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
10388 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
10389 | }, |
10390 | { | |
10391 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10392 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
10393 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
10394 | }, |
10395 | { | |
10396 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10397 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
10398 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
10399 | }, |
10400 | { | |
10401 | /* VEX_W_0F45_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10402 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, |
10403 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
1ba585e8 IT |
10404 | }, |
10405 | { | |
10406 | /* VEX_W_0F45_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10407 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, |
10408 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
43234a1e L |
10409 | }, |
10410 | { | |
10411 | /* VEX_W_0F46_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10412 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, |
10413 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
1ba585e8 IT |
10414 | }, |
10415 | { | |
10416 | /* VEX_W_0F46_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10417 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, |
10418 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
43234a1e L |
10419 | }, |
10420 | { | |
10421 | /* VEX_W_0F47_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10422 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, |
10423 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
1ba585e8 IT |
10424 | }, |
10425 | { | |
10426 | /* VEX_W_0F47_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10427 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, |
10428 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
1ba585e8 IT |
10429 | }, |
10430 | { | |
10431 | /* VEX_W_0F4A_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10432 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, |
10433 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
1ba585e8 IT |
10434 | }, |
10435 | { | |
10436 | /* VEX_W_0F4A_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10437 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, |
10438 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
1ba585e8 IT |
10439 | }, |
10440 | { | |
10441 | /* VEX_W_0F4B_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10442 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, |
10443 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
43234a1e L |
10444 | }, |
10445 | { | |
10446 | /* VEX_W_0F4B_P_2_LEN_1 */ | |
ab4e4ed5 | 10447 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, |
43234a1e | 10448 | }, |
9e30b8e0 | 10449 | { |
592a252b | 10450 | /* VEX_W_0F50_M_0 */ |
bf890a93 | 10451 | { "vmovmskpX", { Gdq, XS }, 0 }, |
9e30b8e0 L |
10452 | }, |
10453 | { | |
592a252b | 10454 | /* VEX_W_0F51_P_0 */ |
bf890a93 | 10455 | { "vsqrtps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10456 | }, |
10457 | { | |
592a252b | 10458 | /* VEX_W_0F51_P_1 */ |
bf890a93 | 10459 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10460 | }, |
10461 | { | |
592a252b | 10462 | /* VEX_W_0F51_P_2 */ |
bf890a93 | 10463 | { "vsqrtpd", { XM, EXx }, 0 }, |
9e30b8e0 L |
10464 | }, |
10465 | { | |
592a252b | 10466 | /* VEX_W_0F51_P_3 */ |
bf890a93 | 10467 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10468 | }, |
10469 | { | |
592a252b | 10470 | /* VEX_W_0F52_P_0 */ |
bf890a93 | 10471 | { "vrsqrtps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10472 | }, |
10473 | { | |
592a252b | 10474 | /* VEX_W_0F52_P_1 */ |
bf890a93 | 10475 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10476 | }, |
10477 | { | |
592a252b | 10478 | /* VEX_W_0F53_P_0 */ |
bf890a93 | 10479 | { "vrcpps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10480 | }, |
10481 | { | |
592a252b | 10482 | /* VEX_W_0F53_P_1 */ |
bf890a93 | 10483 | { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10484 | }, |
10485 | { | |
592a252b | 10486 | /* VEX_W_0F58_P_0 */ |
bf890a93 | 10487 | { "vaddps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10488 | }, |
10489 | { | |
592a252b | 10490 | /* VEX_W_0F58_P_1 */ |
bf890a93 | 10491 | { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10492 | }, |
10493 | { | |
592a252b | 10494 | /* VEX_W_0F58_P_2 */ |
bf890a93 | 10495 | { "vaddpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10496 | }, |
10497 | { | |
592a252b | 10498 | /* VEX_W_0F58_P_3 */ |
bf890a93 | 10499 | { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10500 | }, |
10501 | { | |
592a252b | 10502 | /* VEX_W_0F59_P_0 */ |
bf890a93 | 10503 | { "vmulps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10504 | }, |
10505 | { | |
592a252b | 10506 | /* VEX_W_0F59_P_1 */ |
bf890a93 | 10507 | { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10508 | }, |
10509 | { | |
592a252b | 10510 | /* VEX_W_0F59_P_2 */ |
bf890a93 | 10511 | { "vmulpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10512 | }, |
10513 | { | |
592a252b | 10514 | /* VEX_W_0F59_P_3 */ |
bf890a93 | 10515 | { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10516 | }, |
10517 | { | |
592a252b | 10518 | /* VEX_W_0F5A_P_0 */ |
bf890a93 | 10519 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
10520 | }, |
10521 | { | |
592a252b | 10522 | /* VEX_W_0F5A_P_1 */ |
bf890a93 | 10523 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10524 | }, |
10525 | { | |
592a252b | 10526 | /* VEX_W_0F5A_P_3 */ |
bf890a93 | 10527 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10528 | }, |
10529 | { | |
592a252b | 10530 | /* VEX_W_0F5B_P_0 */ |
bf890a93 | 10531 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10532 | }, |
10533 | { | |
592a252b | 10534 | /* VEX_W_0F5B_P_1 */ |
bf890a93 | 10535 | { "vcvttps2dq", { XM, EXx }, 0 }, |
9e30b8e0 L |
10536 | }, |
10537 | { | |
592a252b | 10538 | /* VEX_W_0F5B_P_2 */ |
bf890a93 | 10539 | { "vcvtps2dq", { XM, EXx }, 0 }, |
9e30b8e0 L |
10540 | }, |
10541 | { | |
592a252b | 10542 | /* VEX_W_0F5C_P_0 */ |
bf890a93 | 10543 | { "vsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10544 | }, |
10545 | { | |
592a252b | 10546 | /* VEX_W_0F5C_P_1 */ |
bf890a93 | 10547 | { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10548 | }, |
10549 | { | |
592a252b | 10550 | /* VEX_W_0F5C_P_2 */ |
bf890a93 | 10551 | { "vsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10552 | }, |
10553 | { | |
592a252b | 10554 | /* VEX_W_0F5C_P_3 */ |
bf890a93 | 10555 | { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10556 | }, |
10557 | { | |
592a252b | 10558 | /* VEX_W_0F5D_P_0 */ |
bf890a93 | 10559 | { "vminps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10560 | }, |
10561 | { | |
592a252b | 10562 | /* VEX_W_0F5D_P_1 */ |
bf890a93 | 10563 | { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10564 | }, |
10565 | { | |
592a252b | 10566 | /* VEX_W_0F5D_P_2 */ |
bf890a93 | 10567 | { "vminpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10568 | }, |
10569 | { | |
592a252b | 10570 | /* VEX_W_0F5D_P_3 */ |
bf890a93 | 10571 | { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10572 | }, |
10573 | { | |
592a252b | 10574 | /* VEX_W_0F5E_P_0 */ |
bf890a93 | 10575 | { "vdivps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10576 | }, |
10577 | { | |
592a252b | 10578 | /* VEX_W_0F5E_P_1 */ |
bf890a93 | 10579 | { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10580 | }, |
10581 | { | |
592a252b | 10582 | /* VEX_W_0F5E_P_2 */ |
bf890a93 | 10583 | { "vdivpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10584 | }, |
10585 | { | |
592a252b | 10586 | /* VEX_W_0F5E_P_3 */ |
bf890a93 | 10587 | { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10588 | }, |
10589 | { | |
592a252b | 10590 | /* VEX_W_0F5F_P_0 */ |
bf890a93 | 10591 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10592 | }, |
10593 | { | |
592a252b | 10594 | /* VEX_W_0F5F_P_1 */ |
bf890a93 | 10595 | { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10596 | }, |
10597 | { | |
592a252b | 10598 | /* VEX_W_0F5F_P_2 */ |
bf890a93 | 10599 | { "vmaxpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10600 | }, |
10601 | { | |
592a252b | 10602 | /* VEX_W_0F5F_P_3 */ |
bf890a93 | 10603 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10604 | }, |
10605 | { | |
592a252b | 10606 | /* VEX_W_0F60_P_2 */ |
bf890a93 | 10607 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10608 | }, |
10609 | { | |
592a252b | 10610 | /* VEX_W_0F61_P_2 */ |
bf890a93 | 10611 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10612 | }, |
10613 | { | |
592a252b | 10614 | /* VEX_W_0F62_P_2 */ |
bf890a93 | 10615 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10616 | }, |
10617 | { | |
592a252b | 10618 | /* VEX_W_0F63_P_2 */ |
bf890a93 | 10619 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10620 | }, |
10621 | { | |
592a252b | 10622 | /* VEX_W_0F64_P_2 */ |
bf890a93 | 10623 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10624 | }, |
10625 | { | |
592a252b | 10626 | /* VEX_W_0F65_P_2 */ |
bf890a93 | 10627 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10628 | }, |
10629 | { | |
592a252b | 10630 | /* VEX_W_0F66_P_2 */ |
bf890a93 | 10631 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10632 | }, |
10633 | { | |
592a252b | 10634 | /* VEX_W_0F67_P_2 */ |
bf890a93 | 10635 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10636 | }, |
10637 | { | |
592a252b | 10638 | /* VEX_W_0F68_P_2 */ |
bf890a93 | 10639 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10640 | }, |
10641 | { | |
592a252b | 10642 | /* VEX_W_0F69_P_2 */ |
bf890a93 | 10643 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10644 | }, |
10645 | { | |
592a252b | 10646 | /* VEX_W_0F6A_P_2 */ |
bf890a93 | 10647 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10648 | }, |
10649 | { | |
592a252b | 10650 | /* VEX_W_0F6B_P_2 */ |
bf890a93 | 10651 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10652 | }, |
10653 | { | |
592a252b | 10654 | /* VEX_W_0F6C_P_2 */ |
bf890a93 | 10655 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10656 | }, |
10657 | { | |
592a252b | 10658 | /* VEX_W_0F6D_P_2 */ |
bf890a93 | 10659 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10660 | }, |
10661 | { | |
592a252b | 10662 | /* VEX_W_0F6F_P_1 */ |
bf890a93 | 10663 | { "vmovdqu", { XM, EXx }, 0 }, |
9e30b8e0 L |
10664 | }, |
10665 | { | |
592a252b | 10666 | /* VEX_W_0F6F_P_2 */ |
bf890a93 | 10667 | { "vmovdqa", { XM, EXx }, 0 }, |
9e30b8e0 L |
10668 | }, |
10669 | { | |
592a252b | 10670 | /* VEX_W_0F70_P_1 */ |
bf890a93 | 10671 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10672 | }, |
10673 | { | |
592a252b | 10674 | /* VEX_W_0F70_P_2 */ |
bf890a93 | 10675 | { "vpshufd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10676 | }, |
10677 | { | |
592a252b | 10678 | /* VEX_W_0F70_P_3 */ |
bf890a93 | 10679 | { "vpshuflw", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10680 | }, |
10681 | { | |
592a252b | 10682 | /* VEX_W_0F71_R_2_P_2 */ |
bf890a93 | 10683 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10684 | }, |
10685 | { | |
592a252b | 10686 | /* VEX_W_0F71_R_4_P_2 */ |
bf890a93 | 10687 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10688 | }, |
10689 | { | |
592a252b | 10690 | /* VEX_W_0F71_R_6_P_2 */ |
bf890a93 | 10691 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10692 | }, |
10693 | { | |
592a252b | 10694 | /* VEX_W_0F72_R_2_P_2 */ |
bf890a93 | 10695 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10696 | }, |
10697 | { | |
592a252b | 10698 | /* VEX_W_0F72_R_4_P_2 */ |
bf890a93 | 10699 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10700 | }, |
10701 | { | |
592a252b | 10702 | /* VEX_W_0F72_R_6_P_2 */ |
bf890a93 | 10703 | { "vpslld", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10704 | }, |
10705 | { | |
592a252b | 10706 | /* VEX_W_0F73_R_2_P_2 */ |
bf890a93 | 10707 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10708 | }, |
10709 | { | |
592a252b | 10710 | /* VEX_W_0F73_R_3_P_2 */ |
bf890a93 | 10711 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10712 | }, |
10713 | { | |
592a252b | 10714 | /* VEX_W_0F73_R_6_P_2 */ |
bf890a93 | 10715 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10716 | }, |
10717 | { | |
592a252b | 10718 | /* VEX_W_0F73_R_7_P_2 */ |
bf890a93 | 10719 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10720 | }, |
10721 | { | |
592a252b | 10722 | /* VEX_W_0F74_P_2 */ |
bf890a93 | 10723 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10724 | }, |
10725 | { | |
592a252b | 10726 | /* VEX_W_0F75_P_2 */ |
bf890a93 | 10727 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10728 | }, |
10729 | { | |
592a252b | 10730 | /* VEX_W_0F76_P_2 */ |
bf890a93 | 10731 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10732 | }, |
10733 | { | |
592a252b | 10734 | /* VEX_W_0F77_P_0 */ |
bf890a93 | 10735 | { "", { VZERO }, 0 }, |
9e30b8e0 L |
10736 | }, |
10737 | { | |
592a252b | 10738 | /* VEX_W_0F7C_P_2 */ |
bf890a93 | 10739 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10740 | }, |
10741 | { | |
592a252b | 10742 | /* VEX_W_0F7C_P_3 */ |
bf890a93 | 10743 | { "vhaddps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10744 | }, |
10745 | { | |
592a252b | 10746 | /* VEX_W_0F7D_P_2 */ |
bf890a93 | 10747 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10748 | }, |
10749 | { | |
592a252b | 10750 | /* VEX_W_0F7D_P_3 */ |
bf890a93 | 10751 | { "vhsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10752 | }, |
10753 | { | |
592a252b | 10754 | /* VEX_W_0F7E_P_1 */ |
bf890a93 | 10755 | { "vmovq", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10756 | }, |
10757 | { | |
592a252b | 10758 | /* VEX_W_0F7F_P_1 */ |
bf890a93 | 10759 | { "vmovdqu", { EXxS, XM }, 0 }, |
9e30b8e0 L |
10760 | }, |
10761 | { | |
592a252b | 10762 | /* VEX_W_0F7F_P_2 */ |
bf890a93 | 10763 | { "vmovdqa", { EXxS, XM }, 0 }, |
9e30b8e0 | 10764 | }, |
43234a1e L |
10765 | { |
10766 | /* VEX_W_0F90_P_0_LEN_0 */ | |
bf890a93 IT |
10767 | { "kmovw", { MaskG, MaskE }, 0 }, |
10768 | { "kmovq", { MaskG, MaskE }, 0 }, | |
1ba585e8 IT |
10769 | }, |
10770 | { | |
10771 | /* VEX_W_0F90_P_2_LEN_0 */ | |
bf890a93 IT |
10772 | { "kmovb", { MaskG, MaskBDE }, 0 }, |
10773 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
43234a1e L |
10774 | }, |
10775 | { | |
10776 | /* VEX_W_0F91_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10777 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, |
10778 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
1ba585e8 IT |
10779 | }, |
10780 | { | |
10781 | /* VEX_W_0F91_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10782 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, |
10783 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
43234a1e L |
10784 | }, |
10785 | { | |
10786 | /* VEX_W_0F92_P_0_LEN_0 */ | |
ab4e4ed5 | 10787 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, |
43234a1e | 10788 | }, |
90a915bf IT |
10789 | { |
10790 | /* VEX_W_0F92_P_2_LEN_0 */ | |
ab4e4ed5 | 10791 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, |
90a915bf | 10792 | }, |
1ba585e8 IT |
10793 | { |
10794 | /* VEX_W_0F92_P_3_LEN_0 */ | |
ab4e4ed5 AF |
10795 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) }, |
10796 | { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) }, | |
1ba585e8 | 10797 | }, |
43234a1e L |
10798 | { |
10799 | /* VEX_W_0F93_P_0_LEN_0 */ | |
ab4e4ed5 | 10800 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, |
43234a1e | 10801 | }, |
90a915bf IT |
10802 | { |
10803 | /* VEX_W_0F93_P_2_LEN_0 */ | |
ab4e4ed5 | 10804 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, |
90a915bf | 10805 | }, |
1ba585e8 IT |
10806 | { |
10807 | /* VEX_W_0F93_P_3_LEN_0 */ | |
ab4e4ed5 AF |
10808 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) }, |
10809 | { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) }, | |
1ba585e8 | 10810 | }, |
43234a1e L |
10811 | { |
10812 | /* VEX_W_0F98_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10813 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, |
10814 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
1ba585e8 IT |
10815 | }, |
10816 | { | |
10817 | /* VEX_W_0F98_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10818 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, |
10819 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
1ba585e8 IT |
10820 | }, |
10821 | { | |
10822 | /* VEX_W_0F99_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10823 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, |
10824 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
1ba585e8 IT |
10825 | }, |
10826 | { | |
10827 | /* VEX_W_0F99_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10828 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, |
10829 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
43234a1e | 10830 | }, |
9e30b8e0 | 10831 | { |
592a252b | 10832 | /* VEX_W_0FAE_R_2_M_0 */ |
bf890a93 | 10833 | { "vldmxcsr", { Md }, 0 }, |
9e30b8e0 L |
10834 | }, |
10835 | { | |
592a252b | 10836 | /* VEX_W_0FAE_R_3_M_0 */ |
bf890a93 | 10837 | { "vstmxcsr", { Md }, 0 }, |
9e30b8e0 L |
10838 | }, |
10839 | { | |
592a252b | 10840 | /* VEX_W_0FC2_P_0 */ |
bf890a93 | 10841 | { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, |
9e30b8e0 L |
10842 | }, |
10843 | { | |
592a252b | 10844 | /* VEX_W_0FC2_P_1 */ |
bf890a93 | 10845 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, |
9e30b8e0 L |
10846 | }, |
10847 | { | |
592a252b | 10848 | /* VEX_W_0FC2_P_2 */ |
bf890a93 | 10849 | { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, |
9e30b8e0 L |
10850 | }, |
10851 | { | |
592a252b | 10852 | /* VEX_W_0FC2_P_3 */ |
bf890a93 | 10853 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, |
9e30b8e0 L |
10854 | }, |
10855 | { | |
592a252b | 10856 | /* VEX_W_0FC4_P_2 */ |
bf890a93 | 10857 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
9e30b8e0 L |
10858 | }, |
10859 | { | |
592a252b | 10860 | /* VEX_W_0FC5_P_2 */ |
bf890a93 | 10861 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
9e30b8e0 L |
10862 | }, |
10863 | { | |
592a252b | 10864 | /* VEX_W_0FD0_P_2 */ |
bf890a93 | 10865 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10866 | }, |
10867 | { | |
592a252b | 10868 | /* VEX_W_0FD0_P_3 */ |
bf890a93 | 10869 | { "vaddsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10870 | }, |
10871 | { | |
592a252b | 10872 | /* VEX_W_0FD1_P_2 */ |
bf890a93 | 10873 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10874 | }, |
10875 | { | |
592a252b | 10876 | /* VEX_W_0FD2_P_2 */ |
bf890a93 | 10877 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10878 | }, |
10879 | { | |
592a252b | 10880 | /* VEX_W_0FD3_P_2 */ |
bf890a93 | 10881 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10882 | }, |
10883 | { | |
592a252b | 10884 | /* VEX_W_0FD4_P_2 */ |
bf890a93 | 10885 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10886 | }, |
10887 | { | |
592a252b | 10888 | /* VEX_W_0FD5_P_2 */ |
bf890a93 | 10889 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10890 | }, |
10891 | { | |
592a252b | 10892 | /* VEX_W_0FD6_P_2 */ |
bf890a93 | 10893 | { "vmovq", { EXqScalarS, XMScalar }, 0 }, |
9e30b8e0 L |
10894 | }, |
10895 | { | |
592a252b | 10896 | /* VEX_W_0FD7_P_2_M_1 */ |
bf890a93 | 10897 | { "vpmovmskb", { Gdq, XS }, 0 }, |
9e30b8e0 L |
10898 | }, |
10899 | { | |
592a252b | 10900 | /* VEX_W_0FD8_P_2 */ |
bf890a93 | 10901 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10902 | }, |
10903 | { | |
592a252b | 10904 | /* VEX_W_0FD9_P_2 */ |
bf890a93 | 10905 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10906 | }, |
10907 | { | |
592a252b | 10908 | /* VEX_W_0FDA_P_2 */ |
bf890a93 | 10909 | { "vpminub", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10910 | }, |
10911 | { | |
592a252b | 10912 | /* VEX_W_0FDB_P_2 */ |
bf890a93 | 10913 | { "vpand", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10914 | }, |
10915 | { | |
592a252b | 10916 | /* VEX_W_0FDC_P_2 */ |
bf890a93 | 10917 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10918 | }, |
10919 | { | |
592a252b | 10920 | /* VEX_W_0FDD_P_2 */ |
bf890a93 | 10921 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10922 | }, |
10923 | { | |
592a252b | 10924 | /* VEX_W_0FDE_P_2 */ |
bf890a93 | 10925 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10926 | }, |
10927 | { | |
592a252b | 10928 | /* VEX_W_0FDF_P_2 */ |
bf890a93 | 10929 | { "vpandn", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10930 | }, |
10931 | { | |
592a252b | 10932 | /* VEX_W_0FE0_P_2 */ |
bf890a93 | 10933 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10934 | }, |
10935 | { | |
592a252b | 10936 | /* VEX_W_0FE1_P_2 */ |
bf890a93 | 10937 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10938 | }, |
10939 | { | |
592a252b | 10940 | /* VEX_W_0FE2_P_2 */ |
bf890a93 | 10941 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10942 | }, |
10943 | { | |
592a252b | 10944 | /* VEX_W_0FE3_P_2 */ |
bf890a93 | 10945 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10946 | }, |
10947 | { | |
592a252b | 10948 | /* VEX_W_0FE4_P_2 */ |
bf890a93 | 10949 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10950 | }, |
10951 | { | |
592a252b | 10952 | /* VEX_W_0FE5_P_2 */ |
bf890a93 | 10953 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10954 | }, |
10955 | { | |
592a252b | 10956 | /* VEX_W_0FE6_P_1 */ |
bf890a93 | 10957 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
10958 | }, |
10959 | { | |
592a252b | 10960 | /* VEX_W_0FE6_P_2 */ |
bf890a93 | 10961 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, |
9e30b8e0 L |
10962 | }, |
10963 | { | |
592a252b | 10964 | /* VEX_W_0FE6_P_3 */ |
bf890a93 | 10965 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, |
9e30b8e0 L |
10966 | }, |
10967 | { | |
592a252b | 10968 | /* VEX_W_0FE7_P_2_M_0 */ |
bf890a93 | 10969 | { "vmovntdq", { Mx, XM }, 0 }, |
9e30b8e0 L |
10970 | }, |
10971 | { | |
592a252b | 10972 | /* VEX_W_0FE8_P_2 */ |
bf890a93 | 10973 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10974 | }, |
10975 | { | |
592a252b | 10976 | /* VEX_W_0FE9_P_2 */ |
bf890a93 | 10977 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10978 | }, |
10979 | { | |
592a252b | 10980 | /* VEX_W_0FEA_P_2 */ |
bf890a93 | 10981 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10982 | }, |
10983 | { | |
592a252b | 10984 | /* VEX_W_0FEB_P_2 */ |
bf890a93 | 10985 | { "vpor", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10986 | }, |
10987 | { | |
592a252b | 10988 | /* VEX_W_0FEC_P_2 */ |
bf890a93 | 10989 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10990 | }, |
10991 | { | |
592a252b | 10992 | /* VEX_W_0FED_P_2 */ |
bf890a93 | 10993 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10994 | }, |
10995 | { | |
592a252b | 10996 | /* VEX_W_0FEE_P_2 */ |
bf890a93 | 10997 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10998 | }, |
10999 | { | |
592a252b | 11000 | /* VEX_W_0FEF_P_2 */ |
bf890a93 | 11001 | { "vpxor", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11002 | }, |
11003 | { | |
592a252b | 11004 | /* VEX_W_0FF0_P_3_M_0 */ |
bf890a93 | 11005 | { "vlddqu", { XM, M }, 0 }, |
9e30b8e0 L |
11006 | }, |
11007 | { | |
592a252b | 11008 | /* VEX_W_0FF1_P_2 */ |
bf890a93 | 11009 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11010 | }, |
11011 | { | |
592a252b | 11012 | /* VEX_W_0FF2_P_2 */ |
bf890a93 | 11013 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11014 | }, |
11015 | { | |
592a252b | 11016 | /* VEX_W_0FF3_P_2 */ |
bf890a93 | 11017 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11018 | }, |
11019 | { | |
592a252b | 11020 | /* VEX_W_0FF4_P_2 */ |
bf890a93 | 11021 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11022 | }, |
11023 | { | |
592a252b | 11024 | /* VEX_W_0FF5_P_2 */ |
bf890a93 | 11025 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11026 | }, |
11027 | { | |
592a252b | 11028 | /* VEX_W_0FF6_P_2 */ |
bf890a93 | 11029 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11030 | }, |
11031 | { | |
592a252b | 11032 | /* VEX_W_0FF7_P_2 */ |
bf890a93 | 11033 | { "vmaskmovdqu", { XM, XS }, 0 }, |
9e30b8e0 L |
11034 | }, |
11035 | { | |
592a252b | 11036 | /* VEX_W_0FF8_P_2 */ |
bf890a93 | 11037 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11038 | }, |
11039 | { | |
592a252b | 11040 | /* VEX_W_0FF9_P_2 */ |
bf890a93 | 11041 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11042 | }, |
11043 | { | |
592a252b | 11044 | /* VEX_W_0FFA_P_2 */ |
bf890a93 | 11045 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11046 | }, |
11047 | { | |
592a252b | 11048 | /* VEX_W_0FFB_P_2 */ |
bf890a93 | 11049 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11050 | }, |
11051 | { | |
592a252b | 11052 | /* VEX_W_0FFC_P_2 */ |
bf890a93 | 11053 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11054 | }, |
11055 | { | |
592a252b | 11056 | /* VEX_W_0FFD_P_2 */ |
bf890a93 | 11057 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11058 | }, |
11059 | { | |
592a252b | 11060 | /* VEX_W_0FFE_P_2 */ |
bf890a93 | 11061 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11062 | }, |
11063 | { | |
592a252b | 11064 | /* VEX_W_0F3800_P_2 */ |
bf890a93 | 11065 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11066 | }, |
11067 | { | |
592a252b | 11068 | /* VEX_W_0F3801_P_2 */ |
bf890a93 | 11069 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11070 | }, |
11071 | { | |
592a252b | 11072 | /* VEX_W_0F3802_P_2 */ |
bf890a93 | 11073 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11074 | }, |
11075 | { | |
592a252b | 11076 | /* VEX_W_0F3803_P_2 */ |
bf890a93 | 11077 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11078 | }, |
11079 | { | |
592a252b | 11080 | /* VEX_W_0F3804_P_2 */ |
bf890a93 | 11081 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11082 | }, |
11083 | { | |
592a252b | 11084 | /* VEX_W_0F3805_P_2 */ |
bf890a93 | 11085 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11086 | }, |
11087 | { | |
592a252b | 11088 | /* VEX_W_0F3806_P_2 */ |
bf890a93 | 11089 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11090 | }, |
11091 | { | |
592a252b | 11092 | /* VEX_W_0F3807_P_2 */ |
bf890a93 | 11093 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11094 | }, |
11095 | { | |
592a252b | 11096 | /* VEX_W_0F3808_P_2 */ |
bf890a93 | 11097 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11098 | }, |
11099 | { | |
592a252b | 11100 | /* VEX_W_0F3809_P_2 */ |
bf890a93 | 11101 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11102 | }, |
11103 | { | |
592a252b | 11104 | /* VEX_W_0F380A_P_2 */ |
bf890a93 | 11105 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11106 | }, |
11107 | { | |
592a252b | 11108 | /* VEX_W_0F380B_P_2 */ |
bf890a93 | 11109 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11110 | }, |
11111 | { | |
592a252b | 11112 | /* VEX_W_0F380C_P_2 */ |
bf890a93 | 11113 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11114 | }, |
11115 | { | |
592a252b | 11116 | /* VEX_W_0F380D_P_2 */ |
bf890a93 | 11117 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11118 | }, |
11119 | { | |
592a252b | 11120 | /* VEX_W_0F380E_P_2 */ |
bf890a93 | 11121 | { "vtestps", { XM, EXx }, 0 }, |
9e30b8e0 L |
11122 | }, |
11123 | { | |
592a252b | 11124 | /* VEX_W_0F380F_P_2 */ |
bf890a93 | 11125 | { "vtestpd", { XM, EXx }, 0 }, |
9e30b8e0 | 11126 | }, |
6c30d220 L |
11127 | { |
11128 | /* VEX_W_0F3816_P_2 */ | |
bf890a93 | 11129 | { "vpermps", { XM, Vex, EXx }, 0 }, |
6c30d220 | 11130 | }, |
9e30b8e0 | 11131 | { |
592a252b | 11132 | /* VEX_W_0F3817_P_2 */ |
bf890a93 | 11133 | { "vptest", { XM, EXx }, 0 }, |
9e30b8e0 | 11134 | }, |
bcf2684f | 11135 | { |
6c30d220 | 11136 | /* VEX_W_0F3818_P_2 */ |
bf890a93 | 11137 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
bcf2684f | 11138 | }, |
9e30b8e0 | 11139 | { |
6c30d220 | 11140 | /* VEX_W_0F3819_P_2 */ |
bf890a93 | 11141 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
9e30b8e0 L |
11142 | }, |
11143 | { | |
592a252b | 11144 | /* VEX_W_0F381A_P_2_M_0 */ |
bf890a93 | 11145 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
9e30b8e0 L |
11146 | }, |
11147 | { | |
592a252b | 11148 | /* VEX_W_0F381C_P_2 */ |
bf890a93 | 11149 | { "vpabsb", { XM, EXx }, 0 }, |
9e30b8e0 L |
11150 | }, |
11151 | { | |
592a252b | 11152 | /* VEX_W_0F381D_P_2 */ |
bf890a93 | 11153 | { "vpabsw", { XM, EXx }, 0 }, |
9e30b8e0 L |
11154 | }, |
11155 | { | |
592a252b | 11156 | /* VEX_W_0F381E_P_2 */ |
bf890a93 | 11157 | { "vpabsd", { XM, EXx }, 0 }, |
9e30b8e0 L |
11158 | }, |
11159 | { | |
592a252b | 11160 | /* VEX_W_0F3820_P_2 */ |
bf890a93 | 11161 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11162 | }, |
11163 | { | |
592a252b | 11164 | /* VEX_W_0F3821_P_2 */ |
bf890a93 | 11165 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11166 | }, |
11167 | { | |
592a252b | 11168 | /* VEX_W_0F3822_P_2 */ |
bf890a93 | 11169 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
9e30b8e0 L |
11170 | }, |
11171 | { | |
592a252b | 11172 | /* VEX_W_0F3823_P_2 */ |
bf890a93 | 11173 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11174 | }, |
11175 | { | |
592a252b | 11176 | /* VEX_W_0F3824_P_2 */ |
bf890a93 | 11177 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11178 | }, |
11179 | { | |
592a252b | 11180 | /* VEX_W_0F3825_P_2 */ |
bf890a93 | 11181 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11182 | }, |
11183 | { | |
592a252b | 11184 | /* VEX_W_0F3828_P_2 */ |
bf890a93 | 11185 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11186 | }, |
11187 | { | |
592a252b | 11188 | /* VEX_W_0F3829_P_2 */ |
bf890a93 | 11189 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11190 | }, |
11191 | { | |
592a252b | 11192 | /* VEX_W_0F382A_P_2_M_0 */ |
bf890a93 | 11193 | { "vmovntdqa", { XM, Mx }, 0 }, |
9e30b8e0 L |
11194 | }, |
11195 | { | |
592a252b | 11196 | /* VEX_W_0F382B_P_2 */ |
bf890a93 | 11197 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 | 11198 | }, |
53aa04a0 | 11199 | { |
592a252b | 11200 | /* VEX_W_0F382C_P_2_M_0 */ |
bf890a93 | 11201 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
11202 | }, |
11203 | { | |
592a252b | 11204 | /* VEX_W_0F382D_P_2_M_0 */ |
bf890a93 | 11205 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
11206 | }, |
11207 | { | |
592a252b | 11208 | /* VEX_W_0F382E_P_2_M_0 */ |
bf890a93 | 11209 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
53aa04a0 L |
11210 | }, |
11211 | { | |
592a252b | 11212 | /* VEX_W_0F382F_P_2_M_0 */ |
bf890a93 | 11213 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
53aa04a0 | 11214 | }, |
9e30b8e0 | 11215 | { |
592a252b | 11216 | /* VEX_W_0F3830_P_2 */ |
bf890a93 | 11217 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11218 | }, |
11219 | { | |
592a252b | 11220 | /* VEX_W_0F3831_P_2 */ |
bf890a93 | 11221 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11222 | }, |
11223 | { | |
592a252b | 11224 | /* VEX_W_0F3832_P_2 */ |
bf890a93 | 11225 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
9e30b8e0 L |
11226 | }, |
11227 | { | |
592a252b | 11228 | /* VEX_W_0F3833_P_2 */ |
bf890a93 | 11229 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11230 | }, |
11231 | { | |
592a252b | 11232 | /* VEX_W_0F3834_P_2 */ |
bf890a93 | 11233 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11234 | }, |
11235 | { | |
592a252b | 11236 | /* VEX_W_0F3835_P_2 */ |
bf890a93 | 11237 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
6c30d220 L |
11238 | }, |
11239 | { | |
11240 | /* VEX_W_0F3836_P_2 */ | |
bf890a93 | 11241 | { "vpermd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11242 | }, |
11243 | { | |
592a252b | 11244 | /* VEX_W_0F3837_P_2 */ |
bf890a93 | 11245 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11246 | }, |
11247 | { | |
592a252b | 11248 | /* VEX_W_0F3838_P_2 */ |
bf890a93 | 11249 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11250 | }, |
11251 | { | |
592a252b | 11252 | /* VEX_W_0F3839_P_2 */ |
bf890a93 | 11253 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11254 | }, |
11255 | { | |
592a252b | 11256 | /* VEX_W_0F383A_P_2 */ |
bf890a93 | 11257 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11258 | }, |
11259 | { | |
592a252b | 11260 | /* VEX_W_0F383B_P_2 */ |
bf890a93 | 11261 | { "vpminud", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11262 | }, |
11263 | { | |
592a252b | 11264 | /* VEX_W_0F383C_P_2 */ |
bf890a93 | 11265 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11266 | }, |
11267 | { | |
592a252b | 11268 | /* VEX_W_0F383D_P_2 */ |
bf890a93 | 11269 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11270 | }, |
11271 | { | |
592a252b | 11272 | /* VEX_W_0F383E_P_2 */ |
bf890a93 | 11273 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11274 | }, |
11275 | { | |
592a252b | 11276 | /* VEX_W_0F383F_P_2 */ |
bf890a93 | 11277 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11278 | }, |
11279 | { | |
592a252b | 11280 | /* VEX_W_0F3840_P_2 */ |
bf890a93 | 11281 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11282 | }, |
11283 | { | |
592a252b | 11284 | /* VEX_W_0F3841_P_2 */ |
bf890a93 | 11285 | { "vphminposuw", { XM, EXx }, 0 }, |
9e30b8e0 | 11286 | }, |
6c30d220 L |
11287 | { |
11288 | /* VEX_W_0F3846_P_2 */ | |
bf890a93 | 11289 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
11290 | }, |
11291 | { | |
11292 | /* VEX_W_0F3858_P_2 */ | |
bf890a93 | 11293 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
6c30d220 L |
11294 | }, |
11295 | { | |
11296 | /* VEX_W_0F3859_P_2 */ | |
bf890a93 | 11297 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
6c30d220 L |
11298 | }, |
11299 | { | |
11300 | /* VEX_W_0F385A_P_2_M_0 */ | |
bf890a93 | 11301 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
6c30d220 L |
11302 | }, |
11303 | { | |
11304 | /* VEX_W_0F3878_P_2 */ | |
bf890a93 | 11305 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
6c30d220 L |
11306 | }, |
11307 | { | |
11308 | /* VEX_W_0F3879_P_2 */ | |
bf890a93 | 11309 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
6c30d220 | 11310 | }, |
48521003 IT |
11311 | { |
11312 | /* VEX_W_0F38CF_P_2 */ | |
11313 | { "vgf2p8mulb", { XM, Vex, EXx }, 0 }, | |
11314 | }, | |
9e30b8e0 | 11315 | { |
592a252b | 11316 | /* VEX_W_0F38DB_P_2 */ |
bf890a93 | 11317 | { "vaesimc", { XM, EXx }, 0 }, |
9e30b8e0 | 11318 | }, |
6c30d220 L |
11319 | { |
11320 | /* VEX_W_0F3A00_P_2 */ | |
11321 | { Bad_Opcode }, | |
bf890a93 | 11322 | { "vpermq", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
11323 | }, |
11324 | { | |
11325 | /* VEX_W_0F3A01_P_2 */ | |
11326 | { Bad_Opcode }, | |
bf890a93 | 11327 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
11328 | }, |
11329 | { | |
11330 | /* VEX_W_0F3A02_P_2 */ | |
bf890a93 | 11331 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
6c30d220 | 11332 | }, |
9e30b8e0 | 11333 | { |
592a252b | 11334 | /* VEX_W_0F3A04_P_2 */ |
bf890a93 | 11335 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11336 | }, |
11337 | { | |
592a252b | 11338 | /* VEX_W_0F3A05_P_2 */ |
bf890a93 | 11339 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11340 | }, |
11341 | { | |
592a252b | 11342 | /* VEX_W_0F3A06_P_2 */ |
bf890a93 | 11343 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
9e30b8e0 L |
11344 | }, |
11345 | { | |
592a252b | 11346 | /* VEX_W_0F3A08_P_2 */ |
bf890a93 | 11347 | { "vroundps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11348 | }, |
11349 | { | |
592a252b | 11350 | /* VEX_W_0F3A09_P_2 */ |
bf890a93 | 11351 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11352 | }, |
11353 | { | |
592a252b | 11354 | /* VEX_W_0F3A0A_P_2 */ |
bf890a93 | 11355 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, |
9e30b8e0 L |
11356 | }, |
11357 | { | |
592a252b | 11358 | /* VEX_W_0F3A0B_P_2 */ |
bf890a93 | 11359 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, |
9e30b8e0 L |
11360 | }, |
11361 | { | |
592a252b | 11362 | /* VEX_W_0F3A0C_P_2 */ |
bf890a93 | 11363 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11364 | }, |
11365 | { | |
592a252b | 11366 | /* VEX_W_0F3A0D_P_2 */ |
bf890a93 | 11367 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11368 | }, |
11369 | { | |
592a252b | 11370 | /* VEX_W_0F3A0E_P_2 */ |
bf890a93 | 11371 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11372 | }, |
11373 | { | |
592a252b | 11374 | /* VEX_W_0F3A0F_P_2 */ |
bf890a93 | 11375 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11376 | }, |
11377 | { | |
592a252b | 11378 | /* VEX_W_0F3A14_P_2 */ |
bf890a93 | 11379 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
9e30b8e0 L |
11380 | }, |
11381 | { | |
592a252b | 11382 | /* VEX_W_0F3A15_P_2 */ |
bf890a93 | 11383 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
9e30b8e0 L |
11384 | }, |
11385 | { | |
592a252b | 11386 | /* VEX_W_0F3A18_P_2 */ |
bf890a93 | 11387 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
9e30b8e0 L |
11388 | }, |
11389 | { | |
592a252b | 11390 | /* VEX_W_0F3A19_P_2 */ |
bf890a93 | 11391 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
9e30b8e0 L |
11392 | }, |
11393 | { | |
592a252b | 11394 | /* VEX_W_0F3A20_P_2 */ |
bf890a93 | 11395 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
9e30b8e0 L |
11396 | }, |
11397 | { | |
592a252b | 11398 | /* VEX_W_0F3A21_P_2 */ |
bf890a93 | 11399 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
9e30b8e0 | 11400 | }, |
43234a1e | 11401 | { |
1ba585e8 | 11402 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
ab4e4ed5 AF |
11403 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
11404 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, | |
43234a1e L |
11405 | }, |
11406 | { | |
1ba585e8 | 11407 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
ab4e4ed5 AF |
11408 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
11409 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, | |
1ba585e8 IT |
11410 | }, |
11411 | { | |
11412 | /* VEX_W_0F3A32_P_2_LEN_0 */ | |
ab4e4ed5 AF |
11413 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
11414 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, | |
43234a1e | 11415 | }, |
1ba585e8 IT |
11416 | { |
11417 | /* VEX_W_0F3A33_P_2_LEN_0 */ | |
ab4e4ed5 AF |
11418 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
11419 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, | |
1ba585e8 | 11420 | }, |
6c30d220 L |
11421 | { |
11422 | /* VEX_W_0F3A38_P_2 */ | |
bf890a93 | 11423 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
6c30d220 L |
11424 | }, |
11425 | { | |
11426 | /* VEX_W_0F3A39_P_2 */ | |
bf890a93 | 11427 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
6c30d220 | 11428 | }, |
9e30b8e0 | 11429 | { |
592a252b | 11430 | /* VEX_W_0F3A40_P_2 */ |
bf890a93 | 11431 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11432 | }, |
11433 | { | |
592a252b | 11434 | /* VEX_W_0F3A41_P_2 */ |
bf890a93 | 11435 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
9e30b8e0 L |
11436 | }, |
11437 | { | |
592a252b | 11438 | /* VEX_W_0F3A42_P_2 */ |
bf890a93 | 11439 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 | 11440 | }, |
6c30d220 L |
11441 | { |
11442 | /* VEX_W_0F3A46_P_2 */ | |
bf890a93 | 11443 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
6c30d220 | 11444 | }, |
a683cc34 | 11445 | { |
592a252b | 11446 | /* VEX_W_0F3A48_P_2 */ |
bf890a93 IT |
11447 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
11448 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 SP |
11449 | }, |
11450 | { | |
592a252b | 11451 | /* VEX_W_0F3A49_P_2 */ |
bf890a93 IT |
11452 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
11453 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 | 11454 | }, |
9e30b8e0 | 11455 | { |
592a252b | 11456 | /* VEX_W_0F3A4A_P_2 */ |
bf890a93 | 11457 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
11458 | }, |
11459 | { | |
592a252b | 11460 | /* VEX_W_0F3A4B_P_2 */ |
bf890a93 | 11461 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
11462 | }, |
11463 | { | |
592a252b | 11464 | /* VEX_W_0F3A4C_P_2 */ |
bf890a93 | 11465 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 | 11466 | }, |
9e30b8e0 | 11467 | { |
592a252b | 11468 | /* VEX_W_0F3A62_P_2 */ |
bf890a93 | 11469 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11470 | }, |
11471 | { | |
592a252b | 11472 | /* VEX_W_0F3A63_P_2 */ |
bf890a93 | 11473 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
9e30b8e0 | 11474 | }, |
48521003 IT |
11475 | { |
11476 | /* VEX_W_0F3ACE_P_2 */ | |
11477 | { Bad_Opcode }, | |
11478 | { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 }, | |
11479 | }, | |
11480 | { | |
11481 | /* VEX_W_0F3ACF_P_2 */ | |
11482 | { Bad_Opcode }, | |
11483 | { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 }, | |
11484 | }, | |
9e30b8e0 | 11485 | { |
592a252b | 11486 | /* VEX_W_0F3ADF_P_2 */ |
bf890a93 | 11487 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
9e30b8e0 | 11488 | }, |
43234a1e L |
11489 | #define NEED_VEX_W_TABLE |
11490 | #include "i386-dis-evex.h" | |
11491 | #undef NEED_VEX_W_TABLE | |
9e30b8e0 L |
11492 | }; |
11493 | ||
11494 | static const struct dis386 mod_table[][2] = { | |
11495 | { | |
11496 | /* MOD_8D */ | |
bf890a93 | 11497 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 11498 | }, |
42164a71 L |
11499 | { |
11500 | /* MOD_C6_REG_7 */ | |
11501 | { Bad_Opcode }, | |
11502 | { RM_TABLE (RM_C6_REG_7) }, | |
11503 | }, | |
11504 | { | |
11505 | /* MOD_C7_REG_7 */ | |
11506 | { Bad_Opcode }, | |
11507 | { RM_TABLE (RM_C7_REG_7) }, | |
11508 | }, | |
4a357820 MZ |
11509 | { |
11510 | /* MOD_FF_REG_3 */ | |
a72d2af2 | 11511 | { "Jcall^", { indirEp }, 0 }, |
4a357820 MZ |
11512 | }, |
11513 | { | |
11514 | /* MOD_FF_REG_5 */ | |
a72d2af2 | 11515 | { "Jjmp^", { indirEp }, 0 }, |
4a357820 | 11516 | }, |
9e30b8e0 L |
11517 | { |
11518 | /* MOD_0F01_REG_0 */ | |
11519 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
11520 | { RM_TABLE (RM_0F01_REG_0) }, | |
11521 | }, | |
11522 | { | |
11523 | /* MOD_0F01_REG_1 */ | |
11524 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
11525 | { RM_TABLE (RM_0F01_REG_1) }, | |
11526 | }, | |
11527 | { | |
11528 | /* MOD_0F01_REG_2 */ | |
11529 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
11530 | { RM_TABLE (RM_0F01_REG_2) }, | |
11531 | }, | |
11532 | { | |
11533 | /* MOD_0F01_REG_3 */ | |
11534 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
11535 | { RM_TABLE (RM_0F01_REG_3) }, | |
11536 | }, | |
8eab4136 L |
11537 | { |
11538 | /* MOD_0F01_REG_5 */ | |
603555e5 | 11539 | { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) }, |
8eab4136 L |
11540 | { RM_TABLE (RM_0F01_REG_5) }, |
11541 | }, | |
9e30b8e0 L |
11542 | { |
11543 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 11544 | { "invlpg", { Mb }, 0 }, |
9e30b8e0 L |
11545 | { RM_TABLE (RM_0F01_REG_7) }, |
11546 | }, | |
11547 | { | |
11548 | /* MOD_0F12_PREFIX_0 */ | |
507bd325 L |
11549 | { "movlps", { XM, EXq }, PREFIX_OPCODE }, |
11550 | { "movhlps", { XM, EXq }, PREFIX_OPCODE }, | |
9e30b8e0 L |
11551 | }, |
11552 | { | |
11553 | /* MOD_0F13 */ | |
507bd325 | 11554 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
11555 | }, |
11556 | { | |
11557 | /* MOD_0F16_PREFIX_0 */ | |
bf890a93 IT |
11558 | { "movhps", { XM, EXq }, 0 }, |
11559 | { "movlhps", { XM, EXq }, 0 }, | |
9e30b8e0 L |
11560 | }, |
11561 | { | |
11562 | /* MOD_0F17 */ | |
507bd325 | 11563 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
11564 | }, |
11565 | { | |
11566 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 11567 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
11568 | }, |
11569 | { | |
11570 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 11571 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
11572 | }, |
11573 | { | |
11574 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 11575 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
11576 | }, |
11577 | { | |
11578 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 11579 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 11580 | }, |
d7189fa5 RM |
11581 | { |
11582 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 11583 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11584 | }, |
11585 | { | |
11586 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 11587 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11588 | }, |
11589 | { | |
11590 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 11591 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11592 | }, |
11593 | { | |
11594 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 11595 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 11596 | }, |
7e8b059b L |
11597 | { |
11598 | /* MOD_0F1A_PREFIX_0 */ | |
bf890a93 IT |
11599 | { "bndldx", { Gbnd, Ev_bnd }, 0 }, |
11600 | { "nopQ", { Ev }, 0 }, | |
7e8b059b L |
11601 | }, |
11602 | { | |
11603 | /* MOD_0F1B_PREFIX_0 */ | |
bf890a93 IT |
11604 | { "bndstx", { Ev_bnd, Gbnd }, 0 }, |
11605 | { "nopQ", { Ev }, 0 }, | |
7e8b059b L |
11606 | }, |
11607 | { | |
11608 | /* MOD_0F1B_PREFIX_1 */ | |
bf890a93 IT |
11609 | { "bndmk", { Gbnd, Ev_bnd }, 0 }, |
11610 | { "nopQ", { Ev }, 0 }, | |
7e8b059b | 11611 | }, |
603555e5 L |
11612 | { |
11613 | /* MOD_0F1E_PREFIX_1 */ | |
11614 | { "nopQ", { Ev }, 0 }, | |
11615 | { REG_TABLE (REG_0F1E_MOD_3) }, | |
11616 | }, | |
b844680a | 11617 | { |
92fddf8e | 11618 | /* MOD_0F24 */ |
7bb15c6f | 11619 | { Bad_Opcode }, |
bf890a93 | 11620 | { "movL", { Rd, Td }, 0 }, |
b844680a L |
11621 | }, |
11622 | { | |
92fddf8e | 11623 | /* MOD_0F26 */ |
592d1631 | 11624 | { Bad_Opcode }, |
bf890a93 | 11625 | { "movL", { Td, Rd }, 0 }, |
b844680a | 11626 | }, |
75c135a8 L |
11627 | { |
11628 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 11629 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11630 | }, |
11631 | { | |
11632 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 11633 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11634 | }, |
11635 | { | |
11636 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 11637 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11638 | }, |
11639 | { | |
11640 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 11641 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11642 | }, |
11643 | { | |
11644 | /* MOD_0F51 */ | |
592d1631 | 11645 | { Bad_Opcode }, |
507bd325 | 11646 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 11647 | }, |
b844680a | 11648 | { |
1ceb70f8 | 11649 | /* MOD_0F71_REG_2 */ |
592d1631 | 11650 | { Bad_Opcode }, |
bf890a93 | 11651 | { "psrlw", { MS, Ib }, 0 }, |
b844680a L |
11652 | }, |
11653 | { | |
1ceb70f8 | 11654 | /* MOD_0F71_REG_4 */ |
592d1631 | 11655 | { Bad_Opcode }, |
bf890a93 | 11656 | { "psraw", { MS, Ib }, 0 }, |
b844680a L |
11657 | }, |
11658 | { | |
1ceb70f8 | 11659 | /* MOD_0F71_REG_6 */ |
592d1631 | 11660 | { Bad_Opcode }, |
bf890a93 | 11661 | { "psllw", { MS, Ib }, 0 }, |
b844680a L |
11662 | }, |
11663 | { | |
1ceb70f8 | 11664 | /* MOD_0F72_REG_2 */ |
592d1631 | 11665 | { Bad_Opcode }, |
bf890a93 | 11666 | { "psrld", { MS, Ib }, 0 }, |
b844680a L |
11667 | }, |
11668 | { | |
1ceb70f8 | 11669 | /* MOD_0F72_REG_4 */ |
592d1631 | 11670 | { Bad_Opcode }, |
bf890a93 | 11671 | { "psrad", { MS, Ib }, 0 }, |
b844680a L |
11672 | }, |
11673 | { | |
1ceb70f8 | 11674 | /* MOD_0F72_REG_6 */ |
592d1631 | 11675 | { Bad_Opcode }, |
bf890a93 | 11676 | { "pslld", { MS, Ib }, 0 }, |
b844680a L |
11677 | }, |
11678 | { | |
1ceb70f8 | 11679 | /* MOD_0F73_REG_2 */ |
592d1631 | 11680 | { Bad_Opcode }, |
bf890a93 | 11681 | { "psrlq", { MS, Ib }, 0 }, |
b844680a L |
11682 | }, |
11683 | { | |
1ceb70f8 | 11684 | /* MOD_0F73_REG_3 */ |
592d1631 | 11685 | { Bad_Opcode }, |
c0f3af97 L |
11686 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
11687 | }, | |
11688 | { | |
11689 | /* MOD_0F73_REG_6 */ | |
592d1631 | 11690 | { Bad_Opcode }, |
bf890a93 | 11691 | { "psllq", { MS, Ib }, 0 }, |
c0f3af97 L |
11692 | }, |
11693 | { | |
11694 | /* MOD_0F73_REG_7 */ | |
592d1631 | 11695 | { Bad_Opcode }, |
c0f3af97 L |
11696 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
11697 | }, | |
11698 | { | |
11699 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 11700 | { "fxsave", { FXSAVE }, 0 }, |
c7b8aa3a | 11701 | { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, |
c0f3af97 L |
11702 | }, |
11703 | { | |
11704 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 11705 | { "fxrstor", { FXSAVE }, 0 }, |
c7b8aa3a | 11706 | { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, |
c0f3af97 L |
11707 | }, |
11708 | { | |
11709 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 11710 | { "ldmxcsr", { Md }, 0 }, |
c7b8aa3a | 11711 | { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, |
c0f3af97 L |
11712 | }, |
11713 | { | |
11714 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 11715 | { "stmxcsr", { Md }, 0 }, |
c7b8aa3a | 11716 | { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, |
c0f3af97 L |
11717 | }, |
11718 | { | |
11719 | /* MOD_0FAE_REG_4 */ | |
6b40c462 L |
11720 | { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) }, |
11721 | { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) }, | |
c0f3af97 L |
11722 | }, |
11723 | { | |
11724 | /* MOD_0FAE_REG_5 */ | |
603555e5 | 11725 | { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) }, |
2234eee6 | 11726 | { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) }, |
c0f3af97 L |
11727 | }, |
11728 | { | |
11729 | /* MOD_0FAE_REG_6 */ | |
c5e7287a | 11730 | { PREFIX_TABLE (PREFIX_0FAE_REG_6) }, |
c0f3af97 L |
11731 | { RM_TABLE (RM_0FAE_REG_6) }, |
11732 | }, | |
11733 | { | |
11734 | /* MOD_0FAE_REG_7 */ | |
963f3586 | 11735 | { PREFIX_TABLE (PREFIX_0FAE_REG_7) }, |
c0f3af97 L |
11736 | { RM_TABLE (RM_0FAE_REG_7) }, |
11737 | }, | |
11738 | { | |
11739 | /* MOD_0FB2 */ | |
bf890a93 | 11740 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11741 | }, |
11742 | { | |
11743 | /* MOD_0FB4 */ | |
bf890a93 | 11744 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11745 | }, |
11746 | { | |
11747 | /* MOD_0FB5 */ | |
bf890a93 | 11748 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 11749 | }, |
a8484f96 L |
11750 | { |
11751 | /* MOD_0FC3 */ | |
11752 | { PREFIX_TABLE (PREFIX_MOD_0_0FC3) }, | |
11753 | }, | |
963f3586 IT |
11754 | { |
11755 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 11756 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
11757 | }, |
11758 | { | |
11759 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 11760 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
11761 | }, |
11762 | { | |
11763 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 11764 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 11765 | }, |
c0f3af97 L |
11766 | { |
11767 | /* MOD_0FC7_REG_6 */ | |
f24bcbaa L |
11768 | { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) }, |
11769 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) } | |
c0f3af97 L |
11770 | }, |
11771 | { | |
11772 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 11773 | { "vmptrst", { Mq }, 0 }, |
f24bcbaa | 11774 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) } |
c0f3af97 L |
11775 | }, |
11776 | { | |
11777 | /* MOD_0FD7 */ | |
592d1631 | 11778 | { Bad_Opcode }, |
bf890a93 | 11779 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
11780 | }, |
11781 | { | |
11782 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 11783 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
11784 | }, |
11785 | { | |
11786 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 11787 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
11788 | }, |
11789 | { | |
11790 | /* MOD_0F382A_PREFIX_2 */ | |
bf890a93 | 11791 | { "movntdqa", { XM, Mx }, 0 }, |
c0f3af97 | 11792 | }, |
603555e5 L |
11793 | { |
11794 | /* MOD_0F38F5_PREFIX_2 */ | |
11795 | { "wrussK", { M, Gdq }, PREFIX_OPCODE }, | |
11796 | }, | |
11797 | { | |
11798 | /* MOD_0F38F6_PREFIX_0 */ | |
11799 | { "wrssK", { M, Gdq }, PREFIX_OPCODE }, | |
11800 | }, | |
c0f3af97 L |
11801 | { |
11802 | /* MOD_62_32BIT */ | |
bf890a93 | 11803 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 11804 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
11805 | }, |
11806 | { | |
11807 | /* MOD_C4_32BIT */ | |
bf890a93 | 11808 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11809 | { VEX_C4_TABLE (VEX_0F) }, |
11810 | }, | |
11811 | { | |
11812 | /* MOD_C5_32BIT */ | |
bf890a93 | 11813 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11814 | { VEX_C5_TABLE (VEX_0F) }, |
11815 | }, | |
11816 | { | |
592a252b L |
11817 | /* MOD_VEX_0F12_PREFIX_0 */ |
11818 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
11819 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 L |
11820 | }, |
11821 | { | |
592a252b L |
11822 | /* MOD_VEX_0F13 */ |
11823 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
11824 | }, |
11825 | { | |
592a252b L |
11826 | /* MOD_VEX_0F16_PREFIX_0 */ |
11827 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
11828 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 L |
11829 | }, |
11830 | { | |
592a252b L |
11831 | /* MOD_VEX_0F17 */ |
11832 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
11833 | }, |
11834 | { | |
592a252b L |
11835 | /* MOD_VEX_0F2B */ |
11836 | { VEX_W_TABLE (VEX_W_0F2B_M_0) }, | |
c0f3af97 | 11837 | }, |
ab4e4ed5 AF |
11838 | { |
11839 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
11840 | { Bad_Opcode }, | |
11841 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, | |
11842 | }, | |
11843 | { | |
11844 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
11845 | { Bad_Opcode }, | |
11846 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, | |
11847 | }, | |
11848 | { | |
11849 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
11850 | { Bad_Opcode }, | |
11851 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, | |
11852 | }, | |
11853 | { | |
11854 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
11855 | { Bad_Opcode }, | |
11856 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, | |
11857 | }, | |
11858 | { | |
11859 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
11860 | { Bad_Opcode }, | |
11861 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, | |
11862 | }, | |
11863 | { | |
11864 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
11865 | { Bad_Opcode }, | |
11866 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, | |
11867 | }, | |
11868 | { | |
11869 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
11870 | { Bad_Opcode }, | |
11871 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, | |
11872 | }, | |
11873 | { | |
11874 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
11875 | { Bad_Opcode }, | |
11876 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, | |
11877 | }, | |
11878 | { | |
11879 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
11880 | { Bad_Opcode }, | |
11881 | { "knotw", { MaskG, MaskR }, 0 }, | |
11882 | }, | |
11883 | { | |
11884 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
11885 | { Bad_Opcode }, | |
11886 | { "knotq", { MaskG, MaskR }, 0 }, | |
11887 | }, | |
11888 | { | |
11889 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
11890 | { Bad_Opcode }, | |
11891 | { "knotb", { MaskG, MaskR }, 0 }, | |
11892 | }, | |
11893 | { | |
11894 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
11895 | { Bad_Opcode }, | |
11896 | { "knotd", { MaskG, MaskR }, 0 }, | |
11897 | }, | |
11898 | { | |
11899 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
11900 | { Bad_Opcode }, | |
11901 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, | |
11902 | }, | |
11903 | { | |
11904 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
11905 | { Bad_Opcode }, | |
11906 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, | |
11907 | }, | |
11908 | { | |
11909 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
11910 | { Bad_Opcode }, | |
11911 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, | |
11912 | }, | |
11913 | { | |
11914 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
11915 | { Bad_Opcode }, | |
11916 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, | |
11917 | }, | |
11918 | { | |
11919 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
11920 | { Bad_Opcode }, | |
11921 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, | |
11922 | }, | |
11923 | { | |
11924 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
11925 | { Bad_Opcode }, | |
11926 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, | |
11927 | }, | |
11928 | { | |
11929 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
11930 | { Bad_Opcode }, | |
11931 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, | |
11932 | }, | |
11933 | { | |
11934 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
11935 | { Bad_Opcode }, | |
11936 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, | |
11937 | }, | |
11938 | { | |
11939 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
11940 | { Bad_Opcode }, | |
11941 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, | |
11942 | }, | |
11943 | { | |
11944 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
11945 | { Bad_Opcode }, | |
11946 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, | |
11947 | }, | |
11948 | { | |
11949 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
11950 | { Bad_Opcode }, | |
11951 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, | |
11952 | }, | |
11953 | { | |
11954 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
11955 | { Bad_Opcode }, | |
11956 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, | |
11957 | }, | |
11958 | { | |
11959 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
11960 | { Bad_Opcode }, | |
11961 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, | |
11962 | }, | |
11963 | { | |
11964 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
11965 | { Bad_Opcode }, | |
11966 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, | |
11967 | }, | |
11968 | { | |
11969 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
11970 | { Bad_Opcode }, | |
11971 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, | |
11972 | }, | |
11973 | { | |
11974 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
11975 | { Bad_Opcode }, | |
11976 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, | |
11977 | }, | |
11978 | { | |
11979 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
11980 | { Bad_Opcode }, | |
11981 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, | |
11982 | }, | |
11983 | { | |
11984 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
11985 | { Bad_Opcode }, | |
11986 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, | |
11987 | }, | |
11988 | { | |
11989 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
11990 | { Bad_Opcode }, | |
11991 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, | |
11992 | }, | |
c0f3af97 | 11993 | { |
592a252b | 11994 | /* MOD_VEX_0F50 */ |
592d1631 | 11995 | { Bad_Opcode }, |
592a252b | 11996 | { VEX_W_TABLE (VEX_W_0F50_M_0) }, |
c0f3af97 L |
11997 | }, |
11998 | { | |
592a252b | 11999 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 12000 | { Bad_Opcode }, |
592a252b | 12001 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
12002 | }, |
12003 | { | |
592a252b | 12004 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 12005 | { Bad_Opcode }, |
592a252b | 12006 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
12007 | }, |
12008 | { | |
592a252b | 12009 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 12010 | { Bad_Opcode }, |
592a252b | 12011 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
12012 | }, |
12013 | { | |
592a252b | 12014 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 12015 | { Bad_Opcode }, |
592a252b | 12016 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 12017 | }, |
d8faab4e | 12018 | { |
592a252b | 12019 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 12020 | { Bad_Opcode }, |
592a252b | 12021 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
12022 | }, |
12023 | { | |
592a252b | 12024 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 12025 | { Bad_Opcode }, |
592a252b | 12026 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 12027 | }, |
876d4bfa | 12028 | { |
592a252b | 12029 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 12030 | { Bad_Opcode }, |
592a252b | 12031 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
12032 | }, |
12033 | { | |
592a252b | 12034 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 12035 | { Bad_Opcode }, |
592a252b | 12036 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
12037 | }, |
12038 | { | |
592a252b | 12039 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 12040 | { Bad_Opcode }, |
592a252b | 12041 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
12042 | }, |
12043 | { | |
592a252b | 12044 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 12045 | { Bad_Opcode }, |
592a252b | 12046 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa | 12047 | }, |
ab4e4ed5 AF |
12048 | { |
12049 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
12050 | { "kmovw", { Ew, MaskG }, 0 }, | |
12051 | { Bad_Opcode }, | |
12052 | }, | |
12053 | { | |
12054 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
12055 | { "kmovq", { Eq, MaskG }, 0 }, | |
12056 | { Bad_Opcode }, | |
12057 | }, | |
12058 | { | |
12059 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
12060 | { "kmovb", { Eb, MaskG }, 0 }, | |
12061 | { Bad_Opcode }, | |
12062 | }, | |
12063 | { | |
12064 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
12065 | { "kmovd", { Ed, MaskG }, 0 }, | |
12066 | { Bad_Opcode }, | |
12067 | }, | |
12068 | { | |
12069 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
12070 | { Bad_Opcode }, | |
12071 | { "kmovw", { MaskG, Rdq }, 0 }, | |
12072 | }, | |
12073 | { | |
12074 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
12075 | { Bad_Opcode }, | |
12076 | { "kmovb", { MaskG, Rdq }, 0 }, | |
12077 | }, | |
12078 | { | |
12079 | /* MOD_VEX_W_0_0F92_P_3_LEN_0 */ | |
12080 | { Bad_Opcode }, | |
12081 | { "kmovd", { MaskG, Rdq }, 0 }, | |
12082 | }, | |
12083 | { | |
12084 | /* MOD_VEX_W_1_0F92_P_3_LEN_0 */ | |
12085 | { Bad_Opcode }, | |
12086 | { "kmovq", { MaskG, Rdq }, 0 }, | |
12087 | }, | |
12088 | { | |
12089 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
12090 | { Bad_Opcode }, | |
12091 | { "kmovw", { Gdq, MaskR }, 0 }, | |
12092 | }, | |
12093 | { | |
12094 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
12095 | { Bad_Opcode }, | |
12096 | { "kmovb", { Gdq, MaskR }, 0 }, | |
12097 | }, | |
12098 | { | |
12099 | /* MOD_VEX_W_0_0F93_P_3_LEN_0 */ | |
12100 | { Bad_Opcode }, | |
12101 | { "kmovd", { Gdq, MaskR }, 0 }, | |
12102 | }, | |
12103 | { | |
12104 | /* MOD_VEX_W_1_0F93_P_3_LEN_0 */ | |
12105 | { Bad_Opcode }, | |
12106 | { "kmovq", { Gdq, MaskR }, 0 }, | |
12107 | }, | |
12108 | { | |
12109 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
12110 | { Bad_Opcode }, | |
12111 | { "kortestw", { MaskG, MaskR }, 0 }, | |
12112 | }, | |
12113 | { | |
12114 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
12115 | { Bad_Opcode }, | |
12116 | { "kortestq", { MaskG, MaskR }, 0 }, | |
12117 | }, | |
12118 | { | |
12119 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
12120 | { Bad_Opcode }, | |
12121 | { "kortestb", { MaskG, MaskR }, 0 }, | |
12122 | }, | |
12123 | { | |
12124 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
12125 | { Bad_Opcode }, | |
12126 | { "kortestd", { MaskG, MaskR }, 0 }, | |
12127 | }, | |
12128 | { | |
12129 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
12130 | { Bad_Opcode }, | |
12131 | { "ktestw", { MaskG, MaskR }, 0 }, | |
12132 | }, | |
12133 | { | |
12134 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
12135 | { Bad_Opcode }, | |
12136 | { "ktestq", { MaskG, MaskR }, 0 }, | |
12137 | }, | |
12138 | { | |
12139 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
12140 | { Bad_Opcode }, | |
12141 | { "ktestb", { MaskG, MaskR }, 0 }, | |
12142 | }, | |
12143 | { | |
12144 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
12145 | { Bad_Opcode }, | |
12146 | { "ktestd", { MaskG, MaskR }, 0 }, | |
12147 | }, | |
876d4bfa | 12148 | { |
592a252b L |
12149 | /* MOD_VEX_0FAE_REG_2 */ |
12150 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 12151 | }, |
bbedc832 | 12152 | { |
592a252b L |
12153 | /* MOD_VEX_0FAE_REG_3 */ |
12154 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 12155 | }, |
144c41d9 | 12156 | { |
592a252b | 12157 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 12158 | { Bad_Opcode }, |
6c30d220 | 12159 | { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, |
144c41d9 | 12160 | }, |
1afd85e3 | 12161 | { |
592a252b L |
12162 | /* MOD_VEX_0FE7_PREFIX_2 */ |
12163 | { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, | |
1afd85e3 L |
12164 | }, |
12165 | { | |
592a252b L |
12166 | /* MOD_VEX_0FF0_PREFIX_3 */ |
12167 | { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, | |
92fddf8e | 12168 | }, |
75c135a8 | 12169 | { |
592a252b L |
12170 | /* MOD_VEX_0F381A_PREFIX_2 */ |
12171 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 12172 | }, |
1afd85e3 | 12173 | { |
592a252b | 12174 | /* MOD_VEX_0F382A_PREFIX_2 */ |
6c30d220 | 12175 | { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, |
1afd85e3 | 12176 | }, |
75c135a8 | 12177 | { |
592a252b L |
12178 | /* MOD_VEX_0F382C_PREFIX_2 */ |
12179 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 12180 | }, |
1afd85e3 | 12181 | { |
592a252b L |
12182 | /* MOD_VEX_0F382D_PREFIX_2 */ |
12183 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
12184 | }, |
12185 | { | |
592a252b L |
12186 | /* MOD_VEX_0F382E_PREFIX_2 */ |
12187 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
12188 | }, |
12189 | { | |
592a252b L |
12190 | /* MOD_VEX_0F382F_PREFIX_2 */ |
12191 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 12192 | }, |
6c30d220 L |
12193 | { |
12194 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
12195 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
12196 | }, | |
12197 | { | |
12198 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
bf890a93 | 12199 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
6c30d220 L |
12200 | }, |
12201 | { | |
12202 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
bf890a93 | 12203 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
6c30d220 | 12204 | }, |
ab4e4ed5 AF |
12205 | { |
12206 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ | |
12207 | { Bad_Opcode }, | |
12208 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, | |
12209 | }, | |
12210 | { | |
12211 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ | |
12212 | { Bad_Opcode }, | |
12213 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, | |
12214 | }, | |
12215 | { | |
12216 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ | |
12217 | { Bad_Opcode }, | |
12218 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, | |
12219 | }, | |
12220 | { | |
12221 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ | |
12222 | { Bad_Opcode }, | |
12223 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, | |
12224 | }, | |
12225 | { | |
12226 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ | |
12227 | { Bad_Opcode }, | |
12228 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, | |
12229 | }, | |
12230 | { | |
12231 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ | |
12232 | { Bad_Opcode }, | |
12233 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, | |
12234 | }, | |
12235 | { | |
12236 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ | |
12237 | { Bad_Opcode }, | |
12238 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, | |
12239 | }, | |
12240 | { | |
12241 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ | |
12242 | { Bad_Opcode }, | |
12243 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, | |
12244 | }, | |
43234a1e L |
12245 | #define NEED_MOD_TABLE |
12246 | #include "i386-dis-evex.h" | |
12247 | #undef NEED_MOD_TABLE | |
b844680a L |
12248 | }; |
12249 | ||
1ceb70f8 | 12250 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
12251 | { |
12252 | /* RM_C6_REG_7 */ | |
bf890a93 | 12253 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
12254 | }, |
12255 | { | |
12256 | /* RM_C7_REG_7 */ | |
bf890a93 | 12257 | { "xbeginT", { Skip_MODRM, Jv }, 0 }, |
42164a71 | 12258 | }, |
b844680a | 12259 | { |
1ceb70f8 | 12260 | /* RM_0F01_REG_0 */ |
592d1631 | 12261 | { Bad_Opcode }, |
bf890a93 IT |
12262 | { "vmcall", { Skip_MODRM }, 0 }, |
12263 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
12264 | { "vmresume", { Skip_MODRM }, 0 }, | |
12265 | { "vmxoff", { Skip_MODRM }, 0 }, | |
be3a8dca | 12266 | { "pconfig", { Skip_MODRM }, 0 }, |
b844680a L |
12267 | }, |
12268 | { | |
1ceb70f8 | 12269 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
12270 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
12271 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
12272 | { "clac", { Skip_MODRM }, 0 }, | |
12273 | { "stac", { Skip_MODRM }, 0 }, | |
2cf200a4 IT |
12274 | { Bad_Opcode }, |
12275 | { Bad_Opcode }, | |
12276 | { Bad_Opcode }, | |
bf890a93 | 12277 | { "encls", { Skip_MODRM }, 0 }, |
b844680a | 12278 | }, |
475a2301 L |
12279 | { |
12280 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
12281 | { "xgetbv", { Skip_MODRM }, 0 }, |
12282 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
12283 | { Bad_Opcode }, |
12284 | { Bad_Opcode }, | |
bf890a93 IT |
12285 | { "vmfunc", { Skip_MODRM }, 0 }, |
12286 | { "xend", { Skip_MODRM }, 0 }, | |
12287 | { "xtest", { Skip_MODRM }, 0 }, | |
12288 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 12289 | }, |
b844680a | 12290 | { |
1ceb70f8 | 12291 | /* RM_0F01_REG_3 */ |
bf890a93 IT |
12292 | { "vmrun", { Skip_MODRM }, 0 }, |
12293 | { "vmmcall", { Skip_MODRM }, 0 }, | |
12294 | { "vmload", { Skip_MODRM }, 0 }, | |
12295 | { "vmsave", { Skip_MODRM }, 0 }, | |
12296 | { "stgi", { Skip_MODRM }, 0 }, | |
12297 | { "clgi", { Skip_MODRM }, 0 }, | |
12298 | { "skinit", { Skip_MODRM }, 0 }, | |
12299 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 12300 | }, |
8eab4136 L |
12301 | { |
12302 | /* RM_0F01_REG_5 */ | |
2234eee6 | 12303 | { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) }, |
8eab4136 | 12304 | { Bad_Opcode }, |
603555e5 | 12305 | { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) }, |
8eab4136 L |
12306 | { Bad_Opcode }, |
12307 | { Bad_Opcode }, | |
12308 | { Bad_Opcode }, | |
12309 | { "rdpkru", { Skip_MODRM }, 0 }, | |
12310 | { "wrpkru", { Skip_MODRM }, 0 }, | |
12311 | }, | |
4e7d34a6 | 12312 | { |
1ceb70f8 | 12313 | /* RM_0F01_REG_7 */ |
bf890a93 IT |
12314 | { "swapgs", { Skip_MODRM }, 0 }, |
12315 | { "rdtscp", { Skip_MODRM }, 0 }, | |
9916071f AP |
12316 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, |
12317 | { "mwaitx", { { OP_Mwaitx, 0 } }, 0 }, | |
bf890a93 | 12318 | { "clzero", { Skip_MODRM }, 0 }, |
b844680a | 12319 | }, |
603555e5 L |
12320 | { |
12321 | /* RM_0F1E_MOD_3_REG_7 */ | |
12322 | { "nopQ", { Ev }, 0 }, | |
12323 | { "nopQ", { Ev }, 0 }, | |
12324 | { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, | |
12325 | { "endbr32", { Skip_MODRM }, PREFIX_OPCODE }, | |
12326 | { "nopQ", { Ev }, 0 }, | |
12327 | { "nopQ", { Ev }, 0 }, | |
12328 | { "nopQ", { Ev }, 0 }, | |
12329 | { "nopQ", { Ev }, 0 }, | |
12330 | }, | |
b844680a | 12331 | { |
1ceb70f8 | 12332 | /* RM_0FAE_REG_6 */ |
bf890a93 | 12333 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 12334 | }, |
bbedc832 | 12335 | { |
1ceb70f8 | 12336 | /* RM_0FAE_REG_7 */ |
b5cefcca L |
12337 | { "sfence", { Skip_MODRM }, 0 }, |
12338 | ||
144c41d9 | 12339 | }, |
b844680a L |
12340 | }; |
12341 | ||
c608c12e AM |
12342 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
12343 | ||
f16cd0d5 L |
12344 | /* We use the high bit to indicate different name for the same |
12345 | prefix. */ | |
f16cd0d5 | 12346 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
12347 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
12348 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 12349 | #define BND_PREFIX (0xf2 | 0x400) |
04ef582a | 12350 | #define NOTRACK_PREFIX (0x3e | 0x100) |
f16cd0d5 L |
12351 | |
12352 | static int | |
26ca5450 | 12353 | ckprefix (void) |
252b5132 | 12354 | { |
f16cd0d5 | 12355 | int newrex, i, length; |
52b15da3 | 12356 | rex = 0; |
c0f3af97 | 12357 | rex_ignored = 0; |
252b5132 | 12358 | prefixes = 0; |
7d421014 | 12359 | used_prefixes = 0; |
52b15da3 | 12360 | rex_used = 0; |
f16cd0d5 L |
12361 | last_lock_prefix = -1; |
12362 | last_repz_prefix = -1; | |
12363 | last_repnz_prefix = -1; | |
12364 | last_data_prefix = -1; | |
12365 | last_addr_prefix = -1; | |
12366 | last_rex_prefix = -1; | |
12367 | last_seg_prefix = -1; | |
d9949a36 | 12368 | fwait_prefix = -1; |
285ca992 | 12369 | active_seg_prefix = 0; |
f310f33d L |
12370 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
12371 | all_prefixes[i] = 0; | |
12372 | i = 0; | |
f16cd0d5 L |
12373 | length = 0; |
12374 | /* The maximum instruction length is 15bytes. */ | |
12375 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
12376 | { |
12377 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 12378 | newrex = 0; |
252b5132 RH |
12379 | switch (*codep) |
12380 | { | |
52b15da3 JH |
12381 | /* REX prefixes family. */ |
12382 | case 0x40: | |
12383 | case 0x41: | |
12384 | case 0x42: | |
12385 | case 0x43: | |
12386 | case 0x44: | |
12387 | case 0x45: | |
12388 | case 0x46: | |
12389 | case 0x47: | |
12390 | case 0x48: | |
12391 | case 0x49: | |
12392 | case 0x4a: | |
12393 | case 0x4b: | |
12394 | case 0x4c: | |
12395 | case 0x4d: | |
12396 | case 0x4e: | |
12397 | case 0x4f: | |
f16cd0d5 L |
12398 | if (address_mode == mode_64bit) |
12399 | newrex = *codep; | |
12400 | else | |
12401 | return 1; | |
12402 | last_rex_prefix = i; | |
52b15da3 | 12403 | break; |
252b5132 RH |
12404 | case 0xf3: |
12405 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 12406 | last_repz_prefix = i; |
252b5132 RH |
12407 | break; |
12408 | case 0xf2: | |
12409 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 12410 | last_repnz_prefix = i; |
252b5132 RH |
12411 | break; |
12412 | case 0xf0: | |
12413 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 12414 | last_lock_prefix = i; |
252b5132 RH |
12415 | break; |
12416 | case 0x2e: | |
12417 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 12418 | last_seg_prefix = i; |
285ca992 | 12419 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
12420 | break; |
12421 | case 0x36: | |
12422 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 12423 | last_seg_prefix = i; |
285ca992 | 12424 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
12425 | break; |
12426 | case 0x3e: | |
12427 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 12428 | last_seg_prefix = i; |
285ca992 | 12429 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
12430 | break; |
12431 | case 0x26: | |
12432 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 12433 | last_seg_prefix = i; |
285ca992 | 12434 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
12435 | break; |
12436 | case 0x64: | |
12437 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 12438 | last_seg_prefix = i; |
285ca992 | 12439 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
12440 | break; |
12441 | case 0x65: | |
12442 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 12443 | last_seg_prefix = i; |
285ca992 | 12444 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
12445 | break; |
12446 | case 0x66: | |
12447 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 12448 | last_data_prefix = i; |
252b5132 RH |
12449 | break; |
12450 | case 0x67: | |
12451 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 12452 | last_addr_prefix = i; |
252b5132 | 12453 | break; |
5076851f | 12454 | case FWAIT_OPCODE: |
252b5132 RH |
12455 | /* fwait is really an instruction. If there are prefixes |
12456 | before the fwait, they belong to the fwait, *not* to the | |
12457 | following instruction. */ | |
d9949a36 | 12458 | fwait_prefix = i; |
3e7d61b2 | 12459 | if (prefixes || rex) |
252b5132 RH |
12460 | { |
12461 | prefixes |= PREFIX_FWAIT; | |
12462 | codep++; | |
6c067bbb RM |
12463 | /* This ensures that the previous REX prefixes are noticed |
12464 | as unused prefixes, as in the return case below. */ | |
12465 | rex_used = rex; | |
f16cd0d5 | 12466 | return 1; |
252b5132 RH |
12467 | } |
12468 | prefixes = PREFIX_FWAIT; | |
12469 | break; | |
12470 | default: | |
f16cd0d5 | 12471 | return 1; |
252b5132 | 12472 | } |
52b15da3 JH |
12473 | /* Rex is ignored when followed by another prefix. */ |
12474 | if (rex) | |
12475 | { | |
3e7d61b2 | 12476 | rex_used = rex; |
f16cd0d5 | 12477 | return 1; |
52b15da3 | 12478 | } |
f16cd0d5 | 12479 | if (*codep != FWAIT_OPCODE) |
4e9ac44a | 12480 | all_prefixes[i++] = *codep; |
52b15da3 | 12481 | rex = newrex; |
252b5132 | 12482 | codep++; |
f16cd0d5 L |
12483 | length++; |
12484 | } | |
12485 | return 0; | |
12486 | } | |
12487 | ||
7d421014 ILT |
12488 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
12489 | prefix byte. */ | |
12490 | ||
12491 | static const char * | |
26ca5450 | 12492 | prefix_name (int pref, int sizeflag) |
7d421014 | 12493 | { |
0003779b L |
12494 | static const char *rexes [16] = |
12495 | { | |
12496 | "rex", /* 0x40 */ | |
12497 | "rex.B", /* 0x41 */ | |
12498 | "rex.X", /* 0x42 */ | |
12499 | "rex.XB", /* 0x43 */ | |
12500 | "rex.R", /* 0x44 */ | |
12501 | "rex.RB", /* 0x45 */ | |
12502 | "rex.RX", /* 0x46 */ | |
12503 | "rex.RXB", /* 0x47 */ | |
12504 | "rex.W", /* 0x48 */ | |
12505 | "rex.WB", /* 0x49 */ | |
12506 | "rex.WX", /* 0x4a */ | |
12507 | "rex.WXB", /* 0x4b */ | |
12508 | "rex.WR", /* 0x4c */ | |
12509 | "rex.WRB", /* 0x4d */ | |
12510 | "rex.WRX", /* 0x4e */ | |
12511 | "rex.WRXB", /* 0x4f */ | |
12512 | }; | |
12513 | ||
7d421014 ILT |
12514 | switch (pref) |
12515 | { | |
52b15da3 JH |
12516 | /* REX prefixes family. */ |
12517 | case 0x40: | |
52b15da3 | 12518 | case 0x41: |
52b15da3 | 12519 | case 0x42: |
52b15da3 | 12520 | case 0x43: |
52b15da3 | 12521 | case 0x44: |
52b15da3 | 12522 | case 0x45: |
52b15da3 | 12523 | case 0x46: |
52b15da3 | 12524 | case 0x47: |
52b15da3 | 12525 | case 0x48: |
52b15da3 | 12526 | case 0x49: |
52b15da3 | 12527 | case 0x4a: |
52b15da3 | 12528 | case 0x4b: |
52b15da3 | 12529 | case 0x4c: |
52b15da3 | 12530 | case 0x4d: |
52b15da3 | 12531 | case 0x4e: |
52b15da3 | 12532 | case 0x4f: |
0003779b | 12533 | return rexes [pref - 0x40]; |
7d421014 ILT |
12534 | case 0xf3: |
12535 | return "repz"; | |
12536 | case 0xf2: | |
12537 | return "repnz"; | |
12538 | case 0xf0: | |
12539 | return "lock"; | |
12540 | case 0x2e: | |
12541 | return "cs"; | |
12542 | case 0x36: | |
12543 | return "ss"; | |
12544 | case 0x3e: | |
12545 | return "ds"; | |
12546 | case 0x26: | |
12547 | return "es"; | |
12548 | case 0x64: | |
12549 | return "fs"; | |
12550 | case 0x65: | |
12551 | return "gs"; | |
12552 | case 0x66: | |
12553 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
12554 | case 0x67: | |
cb712a9e | 12555 | if (address_mode == mode_64bit) |
db6eb5be | 12556 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 12557 | else |
2888cb7a | 12558 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
12559 | case FWAIT_OPCODE: |
12560 | return "fwait"; | |
f16cd0d5 L |
12561 | case REP_PREFIX: |
12562 | return "rep"; | |
42164a71 L |
12563 | case XACQUIRE_PREFIX: |
12564 | return "xacquire"; | |
12565 | case XRELEASE_PREFIX: | |
12566 | return "xrelease"; | |
7e8b059b L |
12567 | case BND_PREFIX: |
12568 | return "bnd"; | |
04ef582a L |
12569 | case NOTRACK_PREFIX: |
12570 | return "notrack"; | |
7d421014 ILT |
12571 | default: |
12572 | return NULL; | |
12573 | } | |
12574 | } | |
12575 | ||
ce518a5f L |
12576 | static char op_out[MAX_OPERANDS][100]; |
12577 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 12578 | static int two_source_ops; |
ce518a5f L |
12579 | static bfd_vma op_address[MAX_OPERANDS]; |
12580 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 12581 | static bfd_vma start_pc; |
ce518a5f | 12582 | |
252b5132 RH |
12583 | /* |
12584 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
12585 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
12586 | * section of the "Virtual 8086 Mode" chapter.) | |
12587 | * 'pc' should be the address of this instruction, it will | |
12588 | * be used to print the target address if this is a relative jump or call | |
12589 | * The function returns the length of this instruction in bytes. | |
12590 | */ | |
12591 | ||
252b5132 | 12592 | static char intel_syntax; |
9d141669 | 12593 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
12594 | static char open_char; |
12595 | static char close_char; | |
12596 | static char separator_char; | |
12597 | static char scale_char; | |
12598 | ||
5db04b09 L |
12599 | enum x86_64_isa |
12600 | { | |
12601 | amd64 = 0, | |
12602 | intel64 | |
12603 | }; | |
12604 | ||
12605 | static enum x86_64_isa isa64; | |
12606 | ||
e396998b AM |
12607 | /* Here for backwards compatibility. When gdb stops using |
12608 | print_insn_i386_att and print_insn_i386_intel these functions can | |
12609 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 12610 | int |
26ca5450 | 12611 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
12612 | { |
12613 | intel_syntax = 0; | |
e396998b AM |
12614 | |
12615 | return print_insn (pc, info); | |
252b5132 RH |
12616 | } |
12617 | ||
12618 | int | |
26ca5450 | 12619 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
12620 | { |
12621 | intel_syntax = 1; | |
e396998b AM |
12622 | |
12623 | return print_insn (pc, info); | |
252b5132 RH |
12624 | } |
12625 | ||
e396998b | 12626 | int |
26ca5450 | 12627 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
12628 | { |
12629 | intel_syntax = -1; | |
12630 | ||
12631 | return print_insn (pc, info); | |
12632 | } | |
12633 | ||
f59a29b9 L |
12634 | void |
12635 | print_i386_disassembler_options (FILE *stream) | |
12636 | { | |
12637 | fprintf (stream, _("\n\ | |
12638 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
12639 | with the -M switch (multiple options should be separated by commas):\n")); | |
12640 | ||
12641 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
12642 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
12643 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
12644 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
12645 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
12646 | fprintf (stream, _(" att-mnemonic\n" |
12647 | " Display instruction in AT&T mnemonic\n")); | |
12648 | fprintf (stream, _(" intel-mnemonic\n" | |
12649 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
12650 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
12651 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
12652 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
12653 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
12654 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
12655 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
12656 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
12657 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
12658 | } |
12659 | ||
592d1631 | 12660 | /* Bad opcode. */ |
bf890a93 | 12661 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 12662 | |
b844680a L |
12663 | /* Get a pointer to struct dis386 with a valid name. */ |
12664 | ||
12665 | static const struct dis386 * | |
8bb15339 | 12666 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 12667 | { |
91d6fa6a | 12668 | int vindex, vex_table_index; |
b844680a L |
12669 | |
12670 | if (dp->name != NULL) | |
12671 | return dp; | |
12672 | ||
12673 | switch (dp->op[0].bytemode) | |
12674 | { | |
1ceb70f8 L |
12675 | case USE_REG_TABLE: |
12676 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
12677 | break; | |
12678 | ||
12679 | case USE_MOD_TABLE: | |
91d6fa6a NC |
12680 | vindex = modrm.mod == 0x3 ? 1 : 0; |
12681 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
12682 | break; |
12683 | ||
12684 | case USE_RM_TABLE: | |
12685 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
12686 | break; |
12687 | ||
4e7d34a6 | 12688 | case USE_PREFIX_TABLE: |
c0f3af97 | 12689 | if (need_vex) |
b844680a | 12690 | { |
c0f3af97 L |
12691 | /* The prefix in VEX is implicit. */ |
12692 | switch (vex.prefix) | |
12693 | { | |
12694 | case 0: | |
91d6fa6a | 12695 | vindex = 0; |
c0f3af97 L |
12696 | break; |
12697 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 12698 | vindex = 1; |
c0f3af97 L |
12699 | break; |
12700 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 12701 | vindex = 2; |
c0f3af97 L |
12702 | break; |
12703 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 12704 | vindex = 3; |
c0f3af97 L |
12705 | break; |
12706 | default: | |
12707 | abort (); | |
12708 | break; | |
12709 | } | |
b844680a | 12710 | } |
7bb15c6f | 12711 | else |
b844680a | 12712 | { |
285ca992 L |
12713 | int last_prefix = -1; |
12714 | int prefix = 0; | |
91d6fa6a | 12715 | vindex = 0; |
285ca992 L |
12716 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
12717 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
12718 | last one wins. */ | |
12719 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 12720 | { |
285ca992 | 12721 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 12722 | { |
285ca992 L |
12723 | vindex = 1; |
12724 | prefix = PREFIX_REPZ; | |
12725 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
12726 | } |
12727 | else | |
b844680a | 12728 | { |
285ca992 L |
12729 | vindex = 3; |
12730 | prefix = PREFIX_REPNZ; | |
12731 | last_prefix = last_repnz_prefix; | |
b844680a | 12732 | } |
285ca992 | 12733 | |
507bd325 L |
12734 | /* Check if prefix should be ignored. */ |
12735 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
12736 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
12737 | & prefix) != 0) | |
285ca992 L |
12738 | vindex = 0; |
12739 | } | |
12740 | ||
12741 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
12742 | { | |
12743 | vindex = 2; | |
12744 | prefix = PREFIX_DATA; | |
12745 | last_prefix = last_data_prefix; | |
12746 | } | |
12747 | ||
12748 | if (vindex != 0) | |
12749 | { | |
12750 | used_prefixes |= prefix; | |
12751 | all_prefixes[last_prefix] = 0; | |
b844680a L |
12752 | } |
12753 | } | |
91d6fa6a | 12754 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
12755 | break; |
12756 | ||
4e7d34a6 | 12757 | case USE_X86_64_TABLE: |
91d6fa6a NC |
12758 | vindex = address_mode == mode_64bit ? 1 : 0; |
12759 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
12760 | break; |
12761 | ||
4e7d34a6 | 12762 | case USE_3BYTE_TABLE: |
8bb15339 | 12763 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
12764 | vindex = *codep++; |
12765 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 12766 | end_codep = codep; |
8bb15339 L |
12767 | modrm.mod = (*codep >> 6) & 3; |
12768 | modrm.reg = (*codep >> 3) & 7; | |
12769 | modrm.rm = *codep & 7; | |
12770 | break; | |
12771 | ||
c0f3af97 L |
12772 | case USE_VEX_LEN_TABLE: |
12773 | if (!need_vex) | |
12774 | abort (); | |
12775 | ||
12776 | switch (vex.length) | |
12777 | { | |
12778 | case 128: | |
91d6fa6a | 12779 | vindex = 0; |
c0f3af97 L |
12780 | break; |
12781 | case 256: | |
91d6fa6a | 12782 | vindex = 1; |
c0f3af97 L |
12783 | break; |
12784 | default: | |
12785 | abort (); | |
12786 | break; | |
12787 | } | |
12788 | ||
91d6fa6a | 12789 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
12790 | break; |
12791 | ||
f88c9eb0 SP |
12792 | case USE_XOP_8F_TABLE: |
12793 | FETCH_DATA (info, codep + 3); | |
12794 | /* All bits in the REX prefix are ignored. */ | |
12795 | rex_ignored = rex; | |
12796 | rex = ~(*codep >> 5) & 0x7; | |
12797 | ||
12798 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
12799 | switch ((*codep & 0x1f)) | |
12800 | { | |
12801 | default: | |
f07af43e L |
12802 | dp = &bad_opcode; |
12803 | return dp; | |
5dd85c99 SP |
12804 | case 0x8: |
12805 | vex_table_index = XOP_08; | |
12806 | break; | |
f88c9eb0 SP |
12807 | case 0x9: |
12808 | vex_table_index = XOP_09; | |
12809 | break; | |
12810 | case 0xa: | |
12811 | vex_table_index = XOP_0A; | |
12812 | break; | |
12813 | } | |
12814 | codep++; | |
12815 | vex.w = *codep & 0x80; | |
12816 | if (vex.w && address_mode == mode_64bit) | |
12817 | rex |= REX_W; | |
12818 | ||
12819 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
abfcb414 | 12820 | if (address_mode != mode_64bit) |
f07af43e | 12821 | { |
abfcb414 AP |
12822 | /* In 16/32-bit mode REX_B is silently ignored. */ |
12823 | rex &= ~REX_B; | |
f07af43e | 12824 | } |
f88c9eb0 SP |
12825 | |
12826 | vex.length = (*codep & 0x4) ? 256 : 128; | |
12827 | switch ((*codep & 0x3)) | |
12828 | { | |
12829 | case 0: | |
12830 | vex.prefix = 0; | |
12831 | break; | |
12832 | case 1: | |
12833 | vex.prefix = DATA_PREFIX_OPCODE; | |
12834 | break; | |
12835 | case 2: | |
12836 | vex.prefix = REPE_PREFIX_OPCODE; | |
12837 | break; | |
12838 | case 3: | |
12839 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12840 | break; | |
12841 | } | |
12842 | need_vex = 1; | |
12843 | need_vex_reg = 1; | |
12844 | codep++; | |
91d6fa6a NC |
12845 | vindex = *codep++; |
12846 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 12847 | |
285ca992 | 12848 | end_codep = codep; |
c48244a5 SP |
12849 | FETCH_DATA (info, codep + 1); |
12850 | modrm.mod = (*codep >> 6) & 3; | |
12851 | modrm.reg = (*codep >> 3) & 7; | |
12852 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
12853 | break; |
12854 | ||
c0f3af97 | 12855 | case USE_VEX_C4_TABLE: |
43234a1e | 12856 | /* VEX prefix. */ |
c0f3af97 L |
12857 | FETCH_DATA (info, codep + 3); |
12858 | /* All bits in the REX prefix are ignored. */ | |
12859 | rex_ignored = rex; | |
12860 | rex = ~(*codep >> 5) & 0x7; | |
12861 | switch ((*codep & 0x1f)) | |
12862 | { | |
12863 | default: | |
f07af43e L |
12864 | dp = &bad_opcode; |
12865 | return dp; | |
c0f3af97 | 12866 | case 0x1: |
f88c9eb0 | 12867 | vex_table_index = VEX_0F; |
c0f3af97 L |
12868 | break; |
12869 | case 0x2: | |
f88c9eb0 | 12870 | vex_table_index = VEX_0F38; |
c0f3af97 L |
12871 | break; |
12872 | case 0x3: | |
f88c9eb0 | 12873 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
12874 | break; |
12875 | } | |
12876 | codep++; | |
12877 | vex.w = *codep & 0x80; | |
9889cbb1 | 12878 | if (address_mode == mode_64bit) |
f07af43e | 12879 | { |
9889cbb1 L |
12880 | if (vex.w) |
12881 | rex |= REX_W; | |
9889cbb1 L |
12882 | } |
12883 | else | |
12884 | { | |
12885 | /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit | |
12886 | is ignored, other REX bits are 0 and the highest bit in | |
5f847646 | 12887 | VEX.vvvv is also ignored (but we mustn't clear it here). */ |
9889cbb1 | 12888 | rex = 0; |
f07af43e | 12889 | } |
5f847646 | 12890 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
12891 | vex.length = (*codep & 0x4) ? 256 : 128; |
12892 | switch ((*codep & 0x3)) | |
12893 | { | |
12894 | case 0: | |
12895 | vex.prefix = 0; | |
12896 | break; | |
12897 | case 1: | |
12898 | vex.prefix = DATA_PREFIX_OPCODE; | |
12899 | break; | |
12900 | case 2: | |
12901 | vex.prefix = REPE_PREFIX_OPCODE; | |
12902 | break; | |
12903 | case 3: | |
12904 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12905 | break; | |
12906 | } | |
12907 | need_vex = 1; | |
12908 | need_vex_reg = 1; | |
12909 | codep++; | |
91d6fa6a NC |
12910 | vindex = *codep++; |
12911 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 12912 | end_codep = codep; |
53c4d625 JB |
12913 | /* There is no MODRM byte for VEX0F 77. */ |
12914 | if (vex_table_index != VEX_0F || vindex != 0x77) | |
c0f3af97 L |
12915 | { |
12916 | FETCH_DATA (info, codep + 1); | |
12917 | modrm.mod = (*codep >> 6) & 3; | |
12918 | modrm.reg = (*codep >> 3) & 7; | |
12919 | modrm.rm = *codep & 7; | |
12920 | } | |
12921 | break; | |
12922 | ||
12923 | case USE_VEX_C5_TABLE: | |
43234a1e | 12924 | /* VEX prefix. */ |
c0f3af97 L |
12925 | FETCH_DATA (info, codep + 2); |
12926 | /* All bits in the REX prefix are ignored. */ | |
12927 | rex_ignored = rex; | |
12928 | rex = (*codep & 0x80) ? 0 : REX_R; | |
12929 | ||
9889cbb1 L |
12930 | /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in |
12931 | VEX.vvvv is 1. */ | |
c0f3af97 | 12932 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
759a05ce | 12933 | vex.w = 0; |
c0f3af97 L |
12934 | vex.length = (*codep & 0x4) ? 256 : 128; |
12935 | switch ((*codep & 0x3)) | |
12936 | { | |
12937 | case 0: | |
12938 | vex.prefix = 0; | |
12939 | break; | |
12940 | case 1: | |
12941 | vex.prefix = DATA_PREFIX_OPCODE; | |
12942 | break; | |
12943 | case 2: | |
12944 | vex.prefix = REPE_PREFIX_OPCODE; | |
12945 | break; | |
12946 | case 3: | |
12947 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12948 | break; | |
12949 | } | |
12950 | need_vex = 1; | |
12951 | need_vex_reg = 1; | |
12952 | codep++; | |
91d6fa6a NC |
12953 | vindex = *codep++; |
12954 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 12955 | end_codep = codep; |
53c4d625 JB |
12956 | /* There is no MODRM byte for VEX 77. */ |
12957 | if (vindex != 0x77) | |
c0f3af97 L |
12958 | { |
12959 | FETCH_DATA (info, codep + 1); | |
12960 | modrm.mod = (*codep >> 6) & 3; | |
12961 | modrm.reg = (*codep >> 3) & 7; | |
12962 | modrm.rm = *codep & 7; | |
12963 | } | |
12964 | break; | |
12965 | ||
9e30b8e0 L |
12966 | case USE_VEX_W_TABLE: |
12967 | if (!need_vex) | |
12968 | abort (); | |
12969 | ||
12970 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
12971 | break; | |
12972 | ||
43234a1e L |
12973 | case USE_EVEX_TABLE: |
12974 | two_source_ops = 0; | |
12975 | /* EVEX prefix. */ | |
12976 | vex.evex = 1; | |
12977 | FETCH_DATA (info, codep + 4); | |
12978 | /* All bits in the REX prefix are ignored. */ | |
12979 | rex_ignored = rex; | |
12980 | /* The first byte after 0x62. */ | |
12981 | rex = ~(*codep >> 5) & 0x7; | |
12982 | vex.r = *codep & 0x10; | |
12983 | switch ((*codep & 0xf)) | |
12984 | { | |
12985 | default: | |
12986 | return &bad_opcode; | |
12987 | case 0x1: | |
12988 | vex_table_index = EVEX_0F; | |
12989 | break; | |
12990 | case 0x2: | |
12991 | vex_table_index = EVEX_0F38; | |
12992 | break; | |
12993 | case 0x3: | |
12994 | vex_table_index = EVEX_0F3A; | |
12995 | break; | |
12996 | } | |
12997 | ||
12998 | /* The second byte after 0x62. */ | |
12999 | codep++; | |
13000 | vex.w = *codep & 0x80; | |
13001 | if (vex.w && address_mode == mode_64bit) | |
13002 | rex |= REX_W; | |
13003 | ||
13004 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
43234a1e L |
13005 | |
13006 | /* The U bit. */ | |
13007 | if (!(*codep & 0x4)) | |
13008 | return &bad_opcode; | |
13009 | ||
13010 | switch ((*codep & 0x3)) | |
13011 | { | |
13012 | case 0: | |
13013 | vex.prefix = 0; | |
13014 | break; | |
13015 | case 1: | |
13016 | vex.prefix = DATA_PREFIX_OPCODE; | |
13017 | break; | |
13018 | case 2: | |
13019 | vex.prefix = REPE_PREFIX_OPCODE; | |
13020 | break; | |
13021 | case 3: | |
13022 | vex.prefix = REPNE_PREFIX_OPCODE; | |
13023 | break; | |
13024 | } | |
13025 | ||
13026 | /* The third byte after 0x62. */ | |
13027 | codep++; | |
13028 | ||
13029 | /* Remember the static rounding bits. */ | |
13030 | vex.ll = (*codep >> 5) & 3; | |
13031 | vex.b = (*codep & 0x10) != 0; | |
13032 | ||
13033 | vex.v = *codep & 0x8; | |
13034 | vex.mask_register_specifier = *codep & 0x7; | |
13035 | vex.zeroing = *codep & 0x80; | |
13036 | ||
5f847646 JB |
13037 | if (address_mode != mode_64bit) |
13038 | { | |
13039 | /* In 16/32-bit mode silently ignore following bits. */ | |
13040 | rex &= ~REX_B; | |
13041 | vex.r = 1; | |
13042 | vex.v = 1; | |
13043 | } | |
13044 | ||
43234a1e L |
13045 | need_vex = 1; |
13046 | need_vex_reg = 1; | |
13047 | codep++; | |
13048 | vindex = *codep++; | |
13049 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 13050 | end_codep = codep; |
43234a1e L |
13051 | FETCH_DATA (info, codep + 1); |
13052 | modrm.mod = (*codep >> 6) & 3; | |
13053 | modrm.reg = (*codep >> 3) & 7; | |
13054 | modrm.rm = *codep & 7; | |
13055 | ||
13056 | /* Set vector length. */ | |
13057 | if (modrm.mod == 3 && vex.b) | |
13058 | vex.length = 512; | |
13059 | else | |
13060 | { | |
13061 | switch (vex.ll) | |
13062 | { | |
13063 | case 0x0: | |
13064 | vex.length = 128; | |
13065 | break; | |
13066 | case 0x1: | |
13067 | vex.length = 256; | |
13068 | break; | |
13069 | case 0x2: | |
13070 | vex.length = 512; | |
13071 | break; | |
13072 | default: | |
13073 | return &bad_opcode; | |
13074 | } | |
13075 | } | |
13076 | break; | |
13077 | ||
592d1631 L |
13078 | case 0: |
13079 | dp = &bad_opcode; | |
13080 | break; | |
13081 | ||
b844680a | 13082 | default: |
d34b5006 | 13083 | abort (); |
b844680a L |
13084 | } |
13085 | ||
13086 | if (dp->name != NULL) | |
13087 | return dp; | |
13088 | else | |
8bb15339 | 13089 | return get_valid_dis386 (dp, info); |
b844680a L |
13090 | } |
13091 | ||
dfc8cf43 | 13092 | static void |
55cf16e1 | 13093 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
13094 | { |
13095 | /* If modrm.mod == 3, operand must be register. */ | |
13096 | if (need_modrm | |
55cf16e1 | 13097 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
13098 | && modrm.mod != 3 |
13099 | && modrm.rm == 4) | |
13100 | { | |
13101 | FETCH_DATA (info, codep + 2); | |
13102 | sib.index = (codep [1] >> 3) & 7; | |
13103 | sib.scale = (codep [1] >> 6) & 3; | |
13104 | sib.base = codep [1] & 7; | |
13105 | } | |
13106 | } | |
13107 | ||
e396998b | 13108 | static int |
26ca5450 | 13109 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 13110 | { |
2da11e11 | 13111 | const struct dis386 *dp; |
252b5132 | 13112 | int i; |
ce518a5f | 13113 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 13114 | int needcomma; |
df18fdba | 13115 | int sizeflag, orig_sizeflag; |
e396998b | 13116 | const char *p; |
252b5132 | 13117 | struct dis_private priv; |
f16cd0d5 | 13118 | int prefix_length; |
252b5132 | 13119 | |
d7921315 L |
13120 | priv.orig_sizeflag = AFLAG | DFLAG; |
13121 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 13122 | address_mode = mode_32bit; |
2da11e11 | 13123 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
13124 | { |
13125 | address_mode = mode_16bit; | |
13126 | priv.orig_sizeflag = 0; | |
13127 | } | |
2da11e11 | 13128 | else |
d7921315 L |
13129 | address_mode = mode_64bit; |
13130 | ||
13131 | if (intel_syntax == (char) -1) | |
13132 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
13133 | |
13134 | for (p = info->disassembler_options; p != NULL; ) | |
13135 | { | |
5db04b09 L |
13136 | if (CONST_STRNEQ (p, "amd64")) |
13137 | isa64 = amd64; | |
13138 | else if (CONST_STRNEQ (p, "intel64")) | |
13139 | isa64 = intel64; | |
13140 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 13141 | { |
cb712a9e | 13142 | address_mode = mode_64bit; |
e396998b AM |
13143 | priv.orig_sizeflag = AFLAG | DFLAG; |
13144 | } | |
0112cd26 | 13145 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 13146 | { |
cb712a9e | 13147 | address_mode = mode_32bit; |
e396998b AM |
13148 | priv.orig_sizeflag = AFLAG | DFLAG; |
13149 | } | |
0112cd26 | 13150 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 13151 | { |
cb712a9e | 13152 | address_mode = mode_16bit; |
e396998b AM |
13153 | priv.orig_sizeflag = 0; |
13154 | } | |
0112cd26 | 13155 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
13156 | { |
13157 | intel_syntax = 1; | |
9d141669 L |
13158 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
13159 | intel_mnemonic = 1; | |
e396998b | 13160 | } |
0112cd26 | 13161 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
13162 | { |
13163 | intel_syntax = 0; | |
9d141669 L |
13164 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
13165 | intel_mnemonic = 0; | |
e396998b | 13166 | } |
0112cd26 | 13167 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 13168 | { |
f59a29b9 L |
13169 | if (address_mode == mode_64bit) |
13170 | { | |
13171 | if (p[4] == '3' && p[5] == '2') | |
13172 | priv.orig_sizeflag &= ~AFLAG; | |
13173 | else if (p[4] == '6' && p[5] == '4') | |
13174 | priv.orig_sizeflag |= AFLAG; | |
13175 | } | |
13176 | else | |
13177 | { | |
13178 | if (p[4] == '1' && p[5] == '6') | |
13179 | priv.orig_sizeflag &= ~AFLAG; | |
13180 | else if (p[4] == '3' && p[5] == '2') | |
13181 | priv.orig_sizeflag |= AFLAG; | |
13182 | } | |
e396998b | 13183 | } |
0112cd26 | 13184 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
13185 | { |
13186 | if (p[4] == '1' && p[5] == '6') | |
13187 | priv.orig_sizeflag &= ~DFLAG; | |
13188 | else if (p[4] == '3' && p[5] == '2') | |
13189 | priv.orig_sizeflag |= DFLAG; | |
13190 | } | |
0112cd26 | 13191 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
13192 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
13193 | ||
13194 | p = strchr (p, ','); | |
13195 | if (p != NULL) | |
13196 | p++; | |
13197 | } | |
13198 | ||
c0f92bf9 L |
13199 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
13200 | { | |
13201 | (*info->fprintf_func) (info->stream, | |
13202 | _("64-bit address is disabled")); | |
13203 | return -1; | |
13204 | } | |
13205 | ||
e396998b AM |
13206 | if (intel_syntax) |
13207 | { | |
13208 | names64 = intel_names64; | |
13209 | names32 = intel_names32; | |
13210 | names16 = intel_names16; | |
13211 | names8 = intel_names8; | |
13212 | names8rex = intel_names8rex; | |
13213 | names_seg = intel_names_seg; | |
b9733481 | 13214 | names_mm = intel_names_mm; |
7e8b059b | 13215 | names_bnd = intel_names_bnd; |
b9733481 L |
13216 | names_xmm = intel_names_xmm; |
13217 | names_ymm = intel_names_ymm; | |
43234a1e | 13218 | names_zmm = intel_names_zmm; |
db51cc60 L |
13219 | index64 = intel_index64; |
13220 | index32 = intel_index32; | |
43234a1e | 13221 | names_mask = intel_names_mask; |
e396998b AM |
13222 | index16 = intel_index16; |
13223 | open_char = '['; | |
13224 | close_char = ']'; | |
13225 | separator_char = '+'; | |
13226 | scale_char = '*'; | |
13227 | } | |
13228 | else | |
13229 | { | |
13230 | names64 = att_names64; | |
13231 | names32 = att_names32; | |
13232 | names16 = att_names16; | |
13233 | names8 = att_names8; | |
13234 | names8rex = att_names8rex; | |
13235 | names_seg = att_names_seg; | |
b9733481 | 13236 | names_mm = att_names_mm; |
7e8b059b | 13237 | names_bnd = att_names_bnd; |
b9733481 L |
13238 | names_xmm = att_names_xmm; |
13239 | names_ymm = att_names_ymm; | |
43234a1e | 13240 | names_zmm = att_names_zmm; |
db51cc60 L |
13241 | index64 = att_index64; |
13242 | index32 = att_index32; | |
43234a1e | 13243 | names_mask = att_names_mask; |
e396998b AM |
13244 | index16 = att_index16; |
13245 | open_char = '('; | |
13246 | close_char = ')'; | |
13247 | separator_char = ','; | |
13248 | scale_char = ','; | |
13249 | } | |
2da11e11 | 13250 | |
4fe53c98 | 13251 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
13252 | puts most long word instructions on a single line. Use 8 bytes |
13253 | for Intel L1OM. */ | |
d7921315 | 13254 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
13255 | info->bytes_per_line = 8; |
13256 | else | |
13257 | info->bytes_per_line = 7; | |
252b5132 | 13258 | |
26ca5450 | 13259 | info->private_data = &priv; |
252b5132 RH |
13260 | priv.max_fetched = priv.the_buffer; |
13261 | priv.insn_start = pc; | |
252b5132 RH |
13262 | |
13263 | obuf[0] = 0; | |
ce518a5f L |
13264 | for (i = 0; i < MAX_OPERANDS; ++i) |
13265 | { | |
13266 | op_out[i][0] = 0; | |
13267 | op_index[i] = -1; | |
13268 | } | |
252b5132 RH |
13269 | |
13270 | the_info = info; | |
13271 | start_pc = pc; | |
e396998b AM |
13272 | start_codep = priv.the_buffer; |
13273 | codep = priv.the_buffer; | |
252b5132 | 13274 | |
8df14d78 | 13275 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 13276 | { |
7d421014 ILT |
13277 | const char *name; |
13278 | ||
5076851f | 13279 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
13280 | means we have an incomplete instruction of some sort. Just |
13281 | print the first byte as a prefix or a .byte pseudo-op. */ | |
13282 | if (codep > priv.the_buffer) | |
5076851f | 13283 | { |
e396998b | 13284 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
13285 | if (name != NULL) |
13286 | (*info->fprintf_func) (info->stream, "%s", name); | |
13287 | else | |
5076851f | 13288 | { |
7d421014 ILT |
13289 | /* Just print the first byte as a .byte instruction. */ |
13290 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 13291 | (unsigned int) priv.the_buffer[0]); |
5076851f | 13292 | } |
5076851f | 13293 | |
7d421014 | 13294 | return 1; |
5076851f ILT |
13295 | } |
13296 | ||
13297 | return -1; | |
13298 | } | |
13299 | ||
52b15da3 | 13300 | obufp = obuf; |
f16cd0d5 L |
13301 | sizeflag = priv.orig_sizeflag; |
13302 | ||
13303 | if (!ckprefix () || rex_used) | |
13304 | { | |
13305 | /* Too many prefixes or unused REX prefixes. */ | |
13306 | for (i = 0; | |
f6dd4781 | 13307 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 13308 | i++) |
de882298 | 13309 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 13310 | i == 0 ? "" : " ", |
f16cd0d5 | 13311 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 13312 | return i; |
f16cd0d5 | 13313 | } |
252b5132 RH |
13314 | |
13315 | insn_codep = codep; | |
13316 | ||
13317 | FETCH_DATA (info, codep + 1); | |
13318 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
13319 | ||
3e7d61b2 | 13320 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 13321 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 13322 | { |
86a80a50 | 13323 | /* Handle prefixes before fwait. */ |
d9949a36 | 13324 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
13325 | i++) |
13326 | (*info->fprintf_func) (info->stream, "%s ", | |
13327 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 13328 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 13329 | return i + 1; |
252b5132 RH |
13330 | } |
13331 | ||
252b5132 RH |
13332 | if (*codep == 0x0f) |
13333 | { | |
eec0f4ca | 13334 | unsigned char threebyte; |
5f40e14d JS |
13335 | |
13336 | codep++; | |
13337 | FETCH_DATA (info, codep + 1); | |
13338 | threebyte = *codep; | |
eec0f4ca | 13339 | dp = &dis386_twobyte[threebyte]; |
252b5132 | 13340 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 13341 | codep++; |
252b5132 RH |
13342 | } |
13343 | else | |
13344 | { | |
6439fc28 | 13345 | dp = &dis386[*codep]; |
252b5132 | 13346 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 13347 | codep++; |
252b5132 | 13348 | } |
246c51aa | 13349 | |
df18fdba L |
13350 | /* Save sizeflag for printing the extra prefixes later before updating |
13351 | it for mnemonic and operand processing. The prefix names depend | |
13352 | only on the address mode. */ | |
13353 | orig_sizeflag = sizeflag; | |
c608c12e | 13354 | if (prefixes & PREFIX_ADDR) |
df18fdba | 13355 | sizeflag ^= AFLAG; |
b844680a | 13356 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 13357 | sizeflag ^= DFLAG; |
3ffd33cf | 13358 | |
285ca992 | 13359 | end_codep = codep; |
8bb15339 | 13360 | if (need_modrm) |
252b5132 RH |
13361 | { |
13362 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
13363 | modrm.mod = (*codep >> 6) & 3; |
13364 | modrm.reg = (*codep >> 3) & 7; | |
13365 | modrm.rm = *codep & 7; | |
252b5132 RH |
13366 | } |
13367 | ||
42d5f9c6 MS |
13368 | need_vex = 0; |
13369 | need_vex_reg = 0; | |
13370 | vex_w_done = 0; | |
43234a1e | 13371 | vex.evex = 0; |
55b126d4 | 13372 | |
ce518a5f | 13373 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 13374 | { |
55cf16e1 | 13375 | get_sib (info, sizeflag); |
252b5132 RH |
13376 | dofloat (sizeflag); |
13377 | } | |
13378 | else | |
13379 | { | |
8bb15339 | 13380 | dp = get_valid_dis386 (dp, info); |
b844680a | 13381 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 13382 | { |
55cf16e1 | 13383 | get_sib (info, sizeflag); |
ce518a5f L |
13384 | for (i = 0; i < MAX_OPERANDS; ++i) |
13385 | { | |
246c51aa | 13386 | obufp = op_out[i]; |
ce518a5f L |
13387 | op_ad = MAX_OPERANDS - 1 - i; |
13388 | if (dp->op[i].rtn) | |
13389 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
13390 | /* For EVEX instruction after the last operand masking |
13391 | should be printed. */ | |
13392 | if (i == 0 && vex.evex) | |
13393 | { | |
13394 | /* Don't print {%k0}. */ | |
13395 | if (vex.mask_register_specifier) | |
13396 | { | |
13397 | oappend ("{"); | |
13398 | oappend (names_mask[vex.mask_register_specifier]); | |
13399 | oappend ("}"); | |
13400 | } | |
13401 | if (vex.zeroing) | |
13402 | oappend ("{z}"); | |
13403 | } | |
ce518a5f | 13404 | } |
6439fc28 | 13405 | } |
252b5132 RH |
13406 | } |
13407 | ||
d869730d | 13408 | /* Check if the REX prefix is used. */ |
e2e6193d | 13409 | if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) |
f16cd0d5 L |
13410 | all_prefixes[last_rex_prefix] = 0; |
13411 | ||
5e6718e4 | 13412 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
13413 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
13414 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 13415 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
13416 | all_prefixes[last_seg_prefix] = 0; |
13417 | ||
5e6718e4 | 13418 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
13419 | if ((prefixes & PREFIX_ADDR) != 0 |
13420 | && (used_prefixes & PREFIX_ADDR) != 0) | |
13421 | all_prefixes[last_addr_prefix] = 0; | |
13422 | ||
df18fdba L |
13423 | /* Check if the DATA prefix is used. */ |
13424 | if ((prefixes & PREFIX_DATA) != 0 | |
13425 | && (used_prefixes & PREFIX_DATA) != 0) | |
13426 | all_prefixes[last_data_prefix] = 0; | |
f16cd0d5 | 13427 | |
df18fdba | 13428 | /* Print the extra prefixes. */ |
f16cd0d5 | 13429 | prefix_length = 0; |
f310f33d | 13430 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
13431 | if (all_prefixes[i]) |
13432 | { | |
13433 | const char *name; | |
df18fdba | 13434 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
13435 | if (name == NULL) |
13436 | abort (); | |
13437 | prefix_length += strlen (name) + 1; | |
13438 | (*info->fprintf_func) (info->stream, "%s ", name); | |
13439 | } | |
b844680a | 13440 | |
285ca992 L |
13441 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
13442 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
13443 | used by putop and MMX/SSE operand and may be overriden by the | |
13444 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
13445 | separately. */ | |
3888916d | 13446 | if (dp->prefix_requirement == PREFIX_OPCODE |
285ca992 L |
13447 | && dp != &bad_opcode |
13448 | && (((prefixes | |
13449 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0 | |
13450 | && (used_prefixes | |
13451 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
13452 | || ((((prefixes | |
13453 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
13454 | == PREFIX_DATA) | |
13455 | && (used_prefixes & PREFIX_DATA) == 0)))) | |
13456 | { | |
13457 | (*info->fprintf_func) (info->stream, "(bad)"); | |
13458 | return end_codep - priv.the_buffer; | |
13459 | } | |
13460 | ||
f16cd0d5 L |
13461 | /* Check maximum code length. */ |
13462 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
13463 | { | |
13464 | (*info->fprintf_func) (info->stream, "(bad)"); | |
13465 | return MAX_CODE_LENGTH; | |
13466 | } | |
b844680a | 13467 | |
ea397f5b | 13468 | obufp = mnemonicendp; |
f16cd0d5 | 13469 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
13470 | oappend (" "); |
13471 | oappend (" "); | |
13472 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
13473 | ||
13474 | /* The enter and bound instructions are printed with operands in the same | |
13475 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 13476 | if (intel_syntax || two_source_ops) |
252b5132 | 13477 | { |
185b1163 L |
13478 | bfd_vma riprel; |
13479 | ||
ce518a5f | 13480 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 13481 | op_txt[i] = op_out[i]; |
246c51aa | 13482 | |
3a8547d2 JB |
13483 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
13484 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
13485 | { | |
13486 | op_txt[2] = op_out[3]; | |
13487 | op_txt[3] = op_out[2]; | |
13488 | } | |
13489 | ||
ce518a5f L |
13490 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
13491 | { | |
6c067bbb RM |
13492 | op_ad = op_index[i]; |
13493 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
13494 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
13495 | riprel = op_riprel[i]; |
13496 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
13497 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 13498 | } |
252b5132 RH |
13499 | } |
13500 | else | |
13501 | { | |
ce518a5f | 13502 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 13503 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
13504 | } |
13505 | ||
ce518a5f L |
13506 | needcomma = 0; |
13507 | for (i = 0; i < MAX_OPERANDS; ++i) | |
13508 | if (*op_txt[i]) | |
13509 | { | |
13510 | if (needcomma) | |
13511 | (*info->fprintf_func) (info->stream, ","); | |
13512 | if (op_index[i] != -1 && !op_riprel[i]) | |
13513 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); | |
13514 | else | |
13515 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
13516 | needcomma = 1; | |
13517 | } | |
050dfa73 | 13518 | |
ce518a5f | 13519 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
13520 | if (op_index[i] != -1 && op_riprel[i]) |
13521 | { | |
13522 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 13523 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 13524 | + op_address[op_index[i]]), info); |
185b1163 | 13525 | break; |
52b15da3 | 13526 | } |
e396998b | 13527 | return codep - priv.the_buffer; |
252b5132 RH |
13528 | } |
13529 | ||
6439fc28 | 13530 | static const char *float_mem[] = { |
252b5132 | 13531 | /* d8 */ |
7c52e0e8 L |
13532 | "fadd{s|}", |
13533 | "fmul{s|}", | |
13534 | "fcom{s|}", | |
13535 | "fcomp{s|}", | |
13536 | "fsub{s|}", | |
13537 | "fsubr{s|}", | |
13538 | "fdiv{s|}", | |
13539 | "fdivr{s|}", | |
db6eb5be | 13540 | /* d9 */ |
7c52e0e8 | 13541 | "fld{s|}", |
252b5132 | 13542 | "(bad)", |
7c52e0e8 L |
13543 | "fst{s|}", |
13544 | "fstp{s|}", | |
9306ca4a | 13545 | "fldenvIC", |
252b5132 | 13546 | "fldcw", |
9306ca4a | 13547 | "fNstenvIC", |
252b5132 RH |
13548 | "fNstcw", |
13549 | /* da */ | |
7c52e0e8 L |
13550 | "fiadd{l|}", |
13551 | "fimul{l|}", | |
13552 | "ficom{l|}", | |
13553 | "ficomp{l|}", | |
13554 | "fisub{l|}", | |
13555 | "fisubr{l|}", | |
13556 | "fidiv{l|}", | |
13557 | "fidivr{l|}", | |
252b5132 | 13558 | /* db */ |
7c52e0e8 L |
13559 | "fild{l|}", |
13560 | "fisttp{l|}", | |
13561 | "fist{l|}", | |
13562 | "fistp{l|}", | |
252b5132 | 13563 | "(bad)", |
6439fc28 | 13564 | "fld{t||t|}", |
252b5132 | 13565 | "(bad)", |
6439fc28 | 13566 | "fstp{t||t|}", |
252b5132 | 13567 | /* dc */ |
7c52e0e8 L |
13568 | "fadd{l|}", |
13569 | "fmul{l|}", | |
13570 | "fcom{l|}", | |
13571 | "fcomp{l|}", | |
13572 | "fsub{l|}", | |
13573 | "fsubr{l|}", | |
13574 | "fdiv{l|}", | |
13575 | "fdivr{l|}", | |
252b5132 | 13576 | /* dd */ |
7c52e0e8 L |
13577 | "fld{l|}", |
13578 | "fisttp{ll|}", | |
13579 | "fst{l||}", | |
13580 | "fstp{l|}", | |
9306ca4a | 13581 | "frstorIC", |
252b5132 | 13582 | "(bad)", |
9306ca4a | 13583 | "fNsaveIC", |
252b5132 RH |
13584 | "fNstsw", |
13585 | /* de */ | |
ac465521 JB |
13586 | "fiadd{s|}", |
13587 | "fimul{s|}", | |
13588 | "ficom{s|}", | |
13589 | "ficomp{s|}", | |
13590 | "fisub{s|}", | |
13591 | "fisubr{s|}", | |
13592 | "fidiv{s|}", | |
13593 | "fidivr{s|}", | |
252b5132 | 13594 | /* df */ |
ac465521 JB |
13595 | "fild{s|}", |
13596 | "fisttp{s|}", | |
13597 | "fist{s|}", | |
13598 | "fistp{s|}", | |
252b5132 | 13599 | "fbld", |
7c52e0e8 | 13600 | "fild{ll|}", |
252b5132 | 13601 | "fbstp", |
7c52e0e8 | 13602 | "fistp{ll|}", |
1d9f512f AM |
13603 | }; |
13604 | ||
13605 | static const unsigned char float_mem_mode[] = { | |
13606 | /* d8 */ | |
13607 | d_mode, | |
13608 | d_mode, | |
13609 | d_mode, | |
13610 | d_mode, | |
13611 | d_mode, | |
13612 | d_mode, | |
13613 | d_mode, | |
13614 | d_mode, | |
13615 | /* d9 */ | |
13616 | d_mode, | |
13617 | 0, | |
13618 | d_mode, | |
13619 | d_mode, | |
13620 | 0, | |
13621 | w_mode, | |
13622 | 0, | |
13623 | w_mode, | |
13624 | /* da */ | |
13625 | d_mode, | |
13626 | d_mode, | |
13627 | d_mode, | |
13628 | d_mode, | |
13629 | d_mode, | |
13630 | d_mode, | |
13631 | d_mode, | |
13632 | d_mode, | |
13633 | /* db */ | |
13634 | d_mode, | |
13635 | d_mode, | |
13636 | d_mode, | |
13637 | d_mode, | |
13638 | 0, | |
9306ca4a | 13639 | t_mode, |
1d9f512f | 13640 | 0, |
9306ca4a | 13641 | t_mode, |
1d9f512f AM |
13642 | /* dc */ |
13643 | q_mode, | |
13644 | q_mode, | |
13645 | q_mode, | |
13646 | q_mode, | |
13647 | q_mode, | |
13648 | q_mode, | |
13649 | q_mode, | |
13650 | q_mode, | |
13651 | /* dd */ | |
13652 | q_mode, | |
13653 | q_mode, | |
13654 | q_mode, | |
13655 | q_mode, | |
13656 | 0, | |
13657 | 0, | |
13658 | 0, | |
13659 | w_mode, | |
13660 | /* de */ | |
13661 | w_mode, | |
13662 | w_mode, | |
13663 | w_mode, | |
13664 | w_mode, | |
13665 | w_mode, | |
13666 | w_mode, | |
13667 | w_mode, | |
13668 | w_mode, | |
13669 | /* df */ | |
13670 | w_mode, | |
13671 | w_mode, | |
13672 | w_mode, | |
13673 | w_mode, | |
9306ca4a | 13674 | t_mode, |
1d9f512f | 13675 | q_mode, |
9306ca4a | 13676 | t_mode, |
1d9f512f | 13677 | q_mode |
252b5132 RH |
13678 | }; |
13679 | ||
ce518a5f L |
13680 | #define ST { OP_ST, 0 } |
13681 | #define STi { OP_STi, 0 } | |
252b5132 | 13682 | |
48c97fa1 L |
13683 | #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 |
13684 | #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 | |
13685 | #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 | |
13686 | #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 | |
13687 | #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 | |
13688 | #define FGRPda_5 NULL, { { NULL, 6 } }, 0 | |
13689 | #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 | |
13690 | #define FGRPde_3 NULL, { { NULL, 8 } }, 0 | |
13691 | #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 | |
252b5132 | 13692 | |
2da11e11 | 13693 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
13694 | /* d8 */ |
13695 | { | |
bf890a93 IT |
13696 | { "fadd", { ST, STi }, 0 }, |
13697 | { "fmul", { ST, STi }, 0 }, | |
13698 | { "fcom", { STi }, 0 }, | |
13699 | { "fcomp", { STi }, 0 }, | |
13700 | { "fsub", { ST, STi }, 0 }, | |
13701 | { "fsubr", { ST, STi }, 0 }, | |
13702 | { "fdiv", { ST, STi }, 0 }, | |
13703 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
13704 | }, |
13705 | /* d9 */ | |
13706 | { | |
bf890a93 IT |
13707 | { "fld", { STi }, 0 }, |
13708 | { "fxch", { STi }, 0 }, | |
252b5132 | 13709 | { FGRPd9_2 }, |
592d1631 | 13710 | { Bad_Opcode }, |
252b5132 RH |
13711 | { FGRPd9_4 }, |
13712 | { FGRPd9_5 }, | |
13713 | { FGRPd9_6 }, | |
13714 | { FGRPd9_7 }, | |
13715 | }, | |
13716 | /* da */ | |
13717 | { | |
bf890a93 IT |
13718 | { "fcmovb", { ST, STi }, 0 }, |
13719 | { "fcmove", { ST, STi }, 0 }, | |
13720 | { "fcmovbe",{ ST, STi }, 0 }, | |
13721 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 13722 | { Bad_Opcode }, |
252b5132 | 13723 | { FGRPda_5 }, |
592d1631 L |
13724 | { Bad_Opcode }, |
13725 | { Bad_Opcode }, | |
252b5132 RH |
13726 | }, |
13727 | /* db */ | |
13728 | { | |
bf890a93 IT |
13729 | { "fcmovnb",{ ST, STi }, 0 }, |
13730 | { "fcmovne",{ ST, STi }, 0 }, | |
13731 | { "fcmovnbe",{ ST, STi }, 0 }, | |
13732 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 13733 | { FGRPdb_4 }, |
bf890a93 IT |
13734 | { "fucomi", { ST, STi }, 0 }, |
13735 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 13736 | { Bad_Opcode }, |
252b5132 RH |
13737 | }, |
13738 | /* dc */ | |
13739 | { | |
bf890a93 IT |
13740 | { "fadd", { STi, ST }, 0 }, |
13741 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
13742 | { Bad_Opcode }, |
13743 | { Bad_Opcode }, | |
d53e6b98 JB |
13744 | { "fsub{!M|r}", { STi, ST }, 0 }, |
13745 | { "fsub{M|}", { STi, ST }, 0 }, | |
13746 | { "fdiv{!M|r}", { STi, ST }, 0 }, | |
13747 | { "fdiv{M|}", { STi, ST }, 0 }, | |
252b5132 RH |
13748 | }, |
13749 | /* dd */ | |
13750 | { | |
bf890a93 | 13751 | { "ffree", { STi }, 0 }, |
592d1631 | 13752 | { Bad_Opcode }, |
bf890a93 IT |
13753 | { "fst", { STi }, 0 }, |
13754 | { "fstp", { STi }, 0 }, | |
13755 | { "fucom", { STi }, 0 }, | |
13756 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
13757 | { Bad_Opcode }, |
13758 | { Bad_Opcode }, | |
252b5132 RH |
13759 | }, |
13760 | /* de */ | |
13761 | { | |
bf890a93 IT |
13762 | { "faddp", { STi, ST }, 0 }, |
13763 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 13764 | { Bad_Opcode }, |
252b5132 | 13765 | { FGRPde_3 }, |
d53e6b98 JB |
13766 | { "fsub{!M|r}p", { STi, ST }, 0 }, |
13767 | { "fsub{M|}p", { STi, ST }, 0 }, | |
13768 | { "fdiv{!M|r}p", { STi, ST }, 0 }, | |
13769 | { "fdiv{M|}p", { STi, ST }, 0 }, | |
252b5132 RH |
13770 | }, |
13771 | /* df */ | |
13772 | { | |
bf890a93 | 13773 | { "ffreep", { STi }, 0 }, |
592d1631 L |
13774 | { Bad_Opcode }, |
13775 | { Bad_Opcode }, | |
13776 | { Bad_Opcode }, | |
252b5132 | 13777 | { FGRPdf_4 }, |
bf890a93 IT |
13778 | { "fucomip", { ST, STi }, 0 }, |
13779 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 13780 | { Bad_Opcode }, |
252b5132 RH |
13781 | }, |
13782 | }; | |
13783 | ||
252b5132 | 13784 | static char *fgrps[][8] = { |
48c97fa1 L |
13785 | /* Bad opcode 0 */ |
13786 | { | |
13787 | "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13788 | }, | |
13789 | ||
13790 | /* d9_2 1 */ | |
252b5132 RH |
13791 | { |
13792 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13793 | }, | |
13794 | ||
48c97fa1 | 13795 | /* d9_4 2 */ |
252b5132 RH |
13796 | { |
13797 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
13798 | }, | |
13799 | ||
48c97fa1 | 13800 | /* d9_5 3 */ |
252b5132 RH |
13801 | { |
13802 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
13803 | }, | |
13804 | ||
48c97fa1 | 13805 | /* d9_6 4 */ |
252b5132 RH |
13806 | { |
13807 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
13808 | }, | |
13809 | ||
48c97fa1 | 13810 | /* d9_7 5 */ |
252b5132 RH |
13811 | { |
13812 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
13813 | }, | |
13814 | ||
48c97fa1 | 13815 | /* da_5 6 */ |
252b5132 RH |
13816 | { |
13817 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13818 | }, | |
13819 | ||
48c97fa1 | 13820 | /* db_4 7 */ |
252b5132 | 13821 | { |
309d3373 JB |
13822 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
13823 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
13824 | }, |
13825 | ||
48c97fa1 | 13826 | /* de_3 8 */ |
252b5132 RH |
13827 | { |
13828 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13829 | }, | |
13830 | ||
48c97fa1 | 13831 | /* df_4 9 */ |
252b5132 RH |
13832 | { |
13833 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13834 | }, | |
13835 | }; | |
13836 | ||
b6169b20 L |
13837 | static void |
13838 | swap_operand (void) | |
13839 | { | |
13840 | mnemonicendp[0] = '.'; | |
13841 | mnemonicendp[1] = 's'; | |
13842 | mnemonicendp += 2; | |
13843 | } | |
13844 | ||
b844680a L |
13845 | static void |
13846 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
13847 | int sizeflag ATTRIBUTE_UNUSED) | |
13848 | { | |
13849 | /* Skip mod/rm byte. */ | |
13850 | MODRM_CHECK; | |
13851 | codep++; | |
13852 | } | |
13853 | ||
252b5132 | 13854 | static void |
26ca5450 | 13855 | dofloat (int sizeflag) |
252b5132 | 13856 | { |
2da11e11 | 13857 | const struct dis386 *dp; |
252b5132 RH |
13858 | unsigned char floatop; |
13859 | ||
13860 | floatop = codep[-1]; | |
13861 | ||
7967e09e | 13862 | if (modrm.mod != 3) |
252b5132 | 13863 | { |
7967e09e | 13864 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
13865 | |
13866 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 13867 | obufp = op_out[0]; |
6e50d963 | 13868 | op_ad = 2; |
1d9f512f | 13869 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
13870 | return; |
13871 | } | |
6608db57 | 13872 | /* Skip mod/rm byte. */ |
4bba6815 | 13873 | MODRM_CHECK; |
252b5132 RH |
13874 | codep++; |
13875 | ||
7967e09e | 13876 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
13877 | if (dp->name == NULL) |
13878 | { | |
7967e09e | 13879 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 13880 | |
6608db57 | 13881 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 13882 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 13883 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
13884 | } |
13885 | else | |
13886 | { | |
13887 | putop (dp->name, sizeflag); | |
13888 | ||
ce518a5f | 13889 | obufp = op_out[0]; |
6e50d963 | 13890 | op_ad = 2; |
ce518a5f L |
13891 | if (dp->op[0].rtn) |
13892 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 13893 | |
ce518a5f | 13894 | obufp = op_out[1]; |
6e50d963 | 13895 | op_ad = 1; |
ce518a5f L |
13896 | if (dp->op[1].rtn) |
13897 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
13898 | } |
13899 | } | |
13900 | ||
9ce09ba2 RM |
13901 | /* Like oappend (below), but S is a string starting with '%'. |
13902 | In Intel syntax, the '%' is elided. */ | |
13903 | static void | |
13904 | oappend_maybe_intel (const char *s) | |
13905 | { | |
13906 | oappend (s + intel_syntax); | |
13907 | } | |
13908 | ||
252b5132 | 13909 | static void |
26ca5450 | 13910 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13911 | { |
9ce09ba2 | 13912 | oappend_maybe_intel ("%st"); |
252b5132 RH |
13913 | } |
13914 | ||
252b5132 | 13915 | static void |
26ca5450 | 13916 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13917 | { |
7967e09e | 13918 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 13919 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
13920 | } |
13921 | ||
6608db57 | 13922 | /* Capital letters in template are macros. */ |
6439fc28 | 13923 | static int |
d3ce72d0 | 13924 | putop (const char *in_template, int sizeflag) |
252b5132 | 13925 | { |
2da11e11 | 13926 | const char *p; |
9306ca4a | 13927 | int alt = 0; |
9d141669 | 13928 | int cond = 1; |
98b528ac L |
13929 | unsigned int l = 0, len = 1; |
13930 | char last[4]; | |
13931 | ||
13932 | #define SAVE_LAST(c) \ | |
13933 | if (l < len && l < sizeof (last)) \ | |
13934 | last[l++] = c; \ | |
13935 | else \ | |
13936 | abort (); | |
252b5132 | 13937 | |
d3ce72d0 | 13938 | for (p = in_template; *p; p++) |
252b5132 RH |
13939 | { |
13940 | switch (*p) | |
13941 | { | |
13942 | default: | |
13943 | *obufp++ = *p; | |
13944 | break; | |
98b528ac L |
13945 | case '%': |
13946 | len++; | |
13947 | break; | |
9d141669 L |
13948 | case '!': |
13949 | cond = 0; | |
13950 | break; | |
6439fc28 | 13951 | case '{': |
6439fc28 | 13952 | if (intel_syntax) |
6439fc28 AM |
13953 | { |
13954 | while (*++p != '|') | |
7c52e0e8 L |
13955 | if (*p == '}' || *p == '\0') |
13956 | abort (); | |
6439fc28 | 13957 | } |
9306ca4a JB |
13958 | /* Fall through. */ |
13959 | case 'I': | |
13960 | alt = 1; | |
13961 | continue; | |
6439fc28 AM |
13962 | case '|': |
13963 | while (*++p != '}') | |
13964 | { | |
13965 | if (*p == '\0') | |
13966 | abort (); | |
13967 | } | |
13968 | break; | |
13969 | case '}': | |
13970 | break; | |
252b5132 | 13971 | case 'A': |
db6eb5be AM |
13972 | if (intel_syntax) |
13973 | break; | |
7967e09e | 13974 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
13975 | *obufp++ = 'b'; |
13976 | break; | |
13977 | case 'B': | |
4b06377f L |
13978 | if (l == 0 && len == 1) |
13979 | { | |
13980 | case_B: | |
13981 | if (intel_syntax) | |
13982 | break; | |
13983 | if (sizeflag & SUFFIX_ALWAYS) | |
13984 | *obufp++ = 'b'; | |
13985 | } | |
13986 | else | |
13987 | { | |
13988 | if (l != 1 | |
13989 | || len != 2 | |
13990 | || last[0] != 'L') | |
13991 | { | |
13992 | SAVE_LAST (*p); | |
13993 | break; | |
13994 | } | |
13995 | ||
13996 | if (address_mode == mode_64bit | |
13997 | && !(prefixes & PREFIX_ADDR)) | |
13998 | { | |
13999 | *obufp++ = 'a'; | |
14000 | *obufp++ = 'b'; | |
14001 | *obufp++ = 's'; | |
14002 | } | |
14003 | ||
14004 | goto case_B; | |
14005 | } | |
252b5132 | 14006 | break; |
9306ca4a JB |
14007 | case 'C': |
14008 | if (intel_syntax && !alt) | |
14009 | break; | |
14010 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
14011 | { | |
14012 | if (sizeflag & DFLAG) | |
14013 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14014 | else | |
14015 | *obufp++ = intel_syntax ? 'w' : 's'; | |
14016 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14017 | } | |
14018 | break; | |
ed7841b3 JB |
14019 | case 'D': |
14020 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
14021 | break; | |
161a04f6 | 14022 | USED_REX (REX_W); |
7967e09e | 14023 | if (modrm.mod == 3) |
ed7841b3 | 14024 | { |
161a04f6 | 14025 | if (rex & REX_W) |
ed7841b3 | 14026 | *obufp++ = 'q'; |
ed7841b3 | 14027 | else |
f16cd0d5 L |
14028 | { |
14029 | if (sizeflag & DFLAG) | |
14030 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14031 | else | |
14032 | *obufp++ = 'w'; | |
14033 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14034 | } | |
ed7841b3 JB |
14035 | } |
14036 | else | |
14037 | *obufp++ = 'w'; | |
14038 | break; | |
252b5132 | 14039 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 14040 | if (address_mode == mode_64bit) |
c1a64871 JH |
14041 | { |
14042 | if (sizeflag & AFLAG) | |
14043 | *obufp++ = 'r'; | |
14044 | else | |
14045 | *obufp++ = 'e'; | |
14046 | } | |
14047 | else | |
14048 | if (sizeflag & AFLAG) | |
14049 | *obufp++ = 'e'; | |
3ffd33cf AM |
14050 | used_prefixes |= (prefixes & PREFIX_ADDR); |
14051 | break; | |
14052 | case 'F': | |
db6eb5be AM |
14053 | if (intel_syntax) |
14054 | break; | |
e396998b | 14055 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
14056 | { |
14057 | if (sizeflag & AFLAG) | |
cb712a9e | 14058 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 14059 | else |
cb712a9e | 14060 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
14061 | used_prefixes |= (prefixes & PREFIX_ADDR); |
14062 | } | |
252b5132 | 14063 | break; |
52fd6d94 JB |
14064 | case 'G': |
14065 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
14066 | break; | |
161a04f6 | 14067 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14068 | *obufp++ = 'l'; |
14069 | else | |
14070 | *obufp++ = 'w'; | |
161a04f6 | 14071 | if (!(rex & REX_W)) |
52fd6d94 JB |
14072 | used_prefixes |= (prefixes & PREFIX_DATA); |
14073 | break; | |
5dd0794d | 14074 | case 'H': |
db6eb5be AM |
14075 | if (intel_syntax) |
14076 | break; | |
5dd0794d AM |
14077 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
14078 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
14079 | { | |
14080 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
14081 | *obufp++ = ','; | |
14082 | *obufp++ = 'p'; | |
14083 | if (prefixes & PREFIX_DS) | |
14084 | *obufp++ = 't'; | |
14085 | else | |
14086 | *obufp++ = 'n'; | |
14087 | } | |
14088 | break; | |
9306ca4a JB |
14089 | case 'J': |
14090 | if (intel_syntax) | |
14091 | break; | |
14092 | *obufp++ = 'l'; | |
14093 | break; | |
42903f7f L |
14094 | case 'K': |
14095 | USED_REX (REX_W); | |
14096 | if (rex & REX_W) | |
14097 | *obufp++ = 'q'; | |
14098 | else | |
14099 | *obufp++ = 'd'; | |
14100 | break; | |
6dd5059a | 14101 | case 'Z': |
04d824a4 JB |
14102 | if (l != 0 || len != 1) |
14103 | { | |
14104 | if (l != 1 || len != 2 || last[0] != 'X') | |
14105 | { | |
14106 | SAVE_LAST (*p); | |
14107 | break; | |
14108 | } | |
14109 | if (!need_vex || !vex.evex) | |
14110 | abort (); | |
14111 | if (intel_syntax | |
14112 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
14113 | break; | |
14114 | switch (vex.length) | |
14115 | { | |
14116 | case 128: | |
14117 | *obufp++ = 'x'; | |
14118 | break; | |
14119 | case 256: | |
14120 | *obufp++ = 'y'; | |
14121 | break; | |
14122 | case 512: | |
14123 | *obufp++ = 'z'; | |
14124 | break; | |
14125 | default: | |
14126 | abort (); | |
14127 | } | |
14128 | break; | |
14129 | } | |
6dd5059a L |
14130 | if (intel_syntax) |
14131 | break; | |
14132 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
14133 | { | |
14134 | *obufp++ = 'q'; | |
14135 | break; | |
14136 | } | |
14137 | /* Fall through. */ | |
98b528ac | 14138 | goto case_L; |
252b5132 | 14139 | case 'L': |
98b528ac L |
14140 | if (l != 0 || len != 1) |
14141 | { | |
14142 | SAVE_LAST (*p); | |
14143 | break; | |
14144 | } | |
14145 | case_L: | |
db6eb5be AM |
14146 | if (intel_syntax) |
14147 | break; | |
252b5132 RH |
14148 | if (sizeflag & SUFFIX_ALWAYS) |
14149 | *obufp++ = 'l'; | |
252b5132 | 14150 | break; |
9d141669 L |
14151 | case 'M': |
14152 | if (intel_mnemonic != cond) | |
14153 | *obufp++ = 'r'; | |
14154 | break; | |
252b5132 RH |
14155 | case 'N': |
14156 | if ((prefixes & PREFIX_FWAIT) == 0) | |
14157 | *obufp++ = 'n'; | |
7d421014 ILT |
14158 | else |
14159 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 14160 | break; |
52b15da3 | 14161 | case 'O': |
161a04f6 L |
14162 | USED_REX (REX_W); |
14163 | if (rex & REX_W) | |
6439fc28 | 14164 | *obufp++ = 'o'; |
a35ca55a JB |
14165 | else if (intel_syntax && (sizeflag & DFLAG)) |
14166 | *obufp++ = 'q'; | |
52b15da3 JH |
14167 | else |
14168 | *obufp++ = 'd'; | |
161a04f6 | 14169 | if (!(rex & REX_W)) |
a35ca55a | 14170 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 14171 | break; |
07f5af7d L |
14172 | case '&': |
14173 | if (!intel_syntax | |
14174 | && address_mode == mode_64bit | |
14175 | && isa64 == intel64) | |
14176 | { | |
14177 | *obufp++ = 'q'; | |
14178 | break; | |
14179 | } | |
14180 | /* Fall through. */ | |
6439fc28 | 14181 | case 'T': |
d9e3625e L |
14182 | if (!intel_syntax |
14183 | && address_mode == mode_64bit | |
7bb15c6f | 14184 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
14185 | { |
14186 | *obufp++ = 'q'; | |
14187 | break; | |
14188 | } | |
6608db57 | 14189 | /* Fall through. */ |
4b4c407a | 14190 | goto case_P; |
252b5132 | 14191 | case 'P': |
4b4c407a | 14192 | if (l == 0 && len == 1) |
d9e3625e | 14193 | { |
4b4c407a L |
14194 | case_P: |
14195 | if (intel_syntax) | |
d9e3625e | 14196 | { |
4b4c407a L |
14197 | if ((rex & REX_W) == 0 |
14198 | && (prefixes & PREFIX_DATA)) | |
14199 | { | |
14200 | if ((sizeflag & DFLAG) == 0) | |
14201 | *obufp++ = 'w'; | |
14202 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14203 | } | |
14204 | break; | |
14205 | } | |
14206 | if ((prefixes & PREFIX_DATA) | |
14207 | || (rex & REX_W) | |
14208 | || (sizeflag & SUFFIX_ALWAYS)) | |
14209 | { | |
14210 | USED_REX (REX_W); | |
14211 | if (rex & REX_W) | |
14212 | *obufp++ = 'q'; | |
14213 | else | |
14214 | { | |
14215 | if (sizeflag & DFLAG) | |
14216 | *obufp++ = 'l'; | |
14217 | else | |
14218 | *obufp++ = 'w'; | |
14219 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14220 | } | |
d9e3625e | 14221 | } |
d9e3625e | 14222 | } |
4b4c407a | 14223 | else |
252b5132 | 14224 | { |
4b4c407a L |
14225 | if (l != 1 || len != 2 || last[0] != 'L') |
14226 | { | |
14227 | SAVE_LAST (*p); | |
14228 | break; | |
14229 | } | |
14230 | ||
14231 | if ((prefixes & PREFIX_DATA) | |
14232 | || (rex & REX_W) | |
14233 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 14234 | { |
4b4c407a L |
14235 | USED_REX (REX_W); |
14236 | if (rex & REX_W) | |
14237 | *obufp++ = 'q'; | |
14238 | else | |
14239 | { | |
14240 | if (sizeflag & DFLAG) | |
14241 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14242 | else | |
14243 | *obufp++ = 'w'; | |
14244 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14245 | } | |
52b15da3 | 14246 | } |
252b5132 RH |
14247 | } |
14248 | break; | |
6439fc28 | 14249 | case 'U': |
db6eb5be AM |
14250 | if (intel_syntax) |
14251 | break; | |
7bb15c6f | 14252 | if (address_mode == mode_64bit |
6c067bbb | 14253 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 14254 | { |
7967e09e | 14255 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 14256 | *obufp++ = 'q'; |
6439fc28 AM |
14257 | break; |
14258 | } | |
6608db57 | 14259 | /* Fall through. */ |
98b528ac | 14260 | goto case_Q; |
252b5132 | 14261 | case 'Q': |
98b528ac | 14262 | if (l == 0 && len == 1) |
252b5132 | 14263 | { |
98b528ac L |
14264 | case_Q: |
14265 | if (intel_syntax && !alt) | |
14266 | break; | |
14267 | USED_REX (REX_W); | |
14268 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 14269 | { |
98b528ac L |
14270 | if (rex & REX_W) |
14271 | *obufp++ = 'q'; | |
52b15da3 | 14272 | else |
98b528ac L |
14273 | { |
14274 | if (sizeflag & DFLAG) | |
14275 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14276 | else | |
14277 | *obufp++ = 'w'; | |
f16cd0d5 | 14278 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 14279 | } |
52b15da3 | 14280 | } |
98b528ac L |
14281 | } |
14282 | else | |
14283 | { | |
14284 | if (l != 1 || len != 2 || last[0] != 'L') | |
14285 | { | |
14286 | SAVE_LAST (*p); | |
14287 | break; | |
14288 | } | |
14289 | if (intel_syntax | |
14290 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
14291 | break; | |
14292 | if ((rex & REX_W)) | |
14293 | { | |
14294 | USED_REX (REX_W); | |
14295 | *obufp++ = 'q'; | |
14296 | } | |
14297 | else | |
14298 | *obufp++ = 'l'; | |
252b5132 RH |
14299 | } |
14300 | break; | |
14301 | case 'R': | |
161a04f6 L |
14302 | USED_REX (REX_W); |
14303 | if (rex & REX_W) | |
a35ca55a JB |
14304 | *obufp++ = 'q'; |
14305 | else if (sizeflag & DFLAG) | |
c608c12e | 14306 | { |
a35ca55a | 14307 | if (intel_syntax) |
c608c12e | 14308 | *obufp++ = 'd'; |
c608c12e | 14309 | else |
a35ca55a | 14310 | *obufp++ = 'l'; |
c608c12e | 14311 | } |
252b5132 | 14312 | else |
a35ca55a JB |
14313 | *obufp++ = 'w'; |
14314 | if (intel_syntax && !p[1] | |
161a04f6 | 14315 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 14316 | *obufp++ = 'e'; |
161a04f6 | 14317 | if (!(rex & REX_W)) |
52b15da3 | 14318 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 14319 | break; |
1a114b12 | 14320 | case 'V': |
4b06377f | 14321 | if (l == 0 && len == 1) |
1a114b12 | 14322 | { |
4b06377f L |
14323 | if (intel_syntax) |
14324 | break; | |
7bb15c6f | 14325 | if (address_mode == mode_64bit |
6c067bbb | 14326 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
14327 | { |
14328 | if (sizeflag & SUFFIX_ALWAYS) | |
14329 | *obufp++ = 'q'; | |
14330 | break; | |
14331 | } | |
14332 | } | |
14333 | else | |
14334 | { | |
14335 | if (l != 1 | |
14336 | || len != 2 | |
14337 | || last[0] != 'L') | |
14338 | { | |
14339 | SAVE_LAST (*p); | |
14340 | break; | |
14341 | } | |
14342 | ||
14343 | if (rex & REX_W) | |
14344 | { | |
14345 | *obufp++ = 'a'; | |
14346 | *obufp++ = 'b'; | |
14347 | *obufp++ = 's'; | |
14348 | } | |
1a114b12 JB |
14349 | } |
14350 | /* Fall through. */ | |
4b06377f | 14351 | goto case_S; |
252b5132 | 14352 | case 'S': |
4b06377f | 14353 | if (l == 0 && len == 1) |
252b5132 | 14354 | { |
4b06377f L |
14355 | case_S: |
14356 | if (intel_syntax) | |
14357 | break; | |
14358 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 14359 | { |
4b06377f L |
14360 | if (rex & REX_W) |
14361 | *obufp++ = 'q'; | |
52b15da3 | 14362 | else |
4b06377f L |
14363 | { |
14364 | if (sizeflag & DFLAG) | |
14365 | *obufp++ = 'l'; | |
14366 | else | |
14367 | *obufp++ = 'w'; | |
14368 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14369 | } | |
14370 | } | |
14371 | } | |
14372 | else | |
14373 | { | |
14374 | if (l != 1 | |
14375 | || len != 2 | |
14376 | || last[0] != 'L') | |
14377 | { | |
14378 | SAVE_LAST (*p); | |
14379 | break; | |
52b15da3 | 14380 | } |
4b06377f L |
14381 | |
14382 | if (address_mode == mode_64bit | |
14383 | && !(prefixes & PREFIX_ADDR)) | |
14384 | { | |
14385 | *obufp++ = 'a'; | |
14386 | *obufp++ = 'b'; | |
14387 | *obufp++ = 's'; | |
14388 | } | |
14389 | ||
14390 | goto case_S; | |
252b5132 | 14391 | } |
252b5132 | 14392 | break; |
041bd2e0 | 14393 | case 'X': |
c0f3af97 L |
14394 | if (l != 0 || len != 1) |
14395 | { | |
14396 | SAVE_LAST (*p); | |
14397 | break; | |
14398 | } | |
14399 | if (need_vex && vex.prefix) | |
14400 | { | |
14401 | if (vex.prefix == DATA_PREFIX_OPCODE) | |
14402 | *obufp++ = 'd'; | |
14403 | else | |
14404 | *obufp++ = 's'; | |
14405 | } | |
041bd2e0 | 14406 | else |
f16cd0d5 L |
14407 | { |
14408 | if (prefixes & PREFIX_DATA) | |
14409 | *obufp++ = 'd'; | |
14410 | else | |
14411 | *obufp++ = 's'; | |
14412 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14413 | } | |
041bd2e0 | 14414 | break; |
76f227a5 | 14415 | case 'Y': |
c0f3af97 | 14416 | if (l == 0 && len == 1) |
76f227a5 | 14417 | { |
c0f3af97 L |
14418 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
14419 | break; | |
14420 | if (rex & REX_W) | |
14421 | { | |
14422 | USED_REX (REX_W); | |
14423 | *obufp++ = 'q'; | |
14424 | } | |
14425 | break; | |
14426 | } | |
14427 | else | |
14428 | { | |
14429 | if (l != 1 || len != 2 || last[0] != 'X') | |
14430 | { | |
14431 | SAVE_LAST (*p); | |
14432 | break; | |
14433 | } | |
14434 | if (!need_vex) | |
14435 | abort (); | |
14436 | if (intel_syntax | |
04d824a4 | 14437 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
14438 | break; |
14439 | switch (vex.length) | |
14440 | { | |
14441 | case 128: | |
14442 | *obufp++ = 'x'; | |
14443 | break; | |
14444 | case 256: | |
14445 | *obufp++ = 'y'; | |
14446 | break; | |
04d824a4 JB |
14447 | case 512: |
14448 | if (!vex.evex) | |
c0f3af97 | 14449 | default: |
04d824a4 | 14450 | abort (); |
c0f3af97 | 14451 | } |
76f227a5 JH |
14452 | } |
14453 | break; | |
252b5132 | 14454 | case 'W': |
0bfee649 | 14455 | if (l == 0 && len == 1) |
a35ca55a | 14456 | { |
0bfee649 L |
14457 | /* operand size flag for cwtl, cbtw */ |
14458 | USED_REX (REX_W); | |
14459 | if (rex & REX_W) | |
14460 | { | |
14461 | if (intel_syntax) | |
14462 | *obufp++ = 'd'; | |
14463 | else | |
14464 | *obufp++ = 'l'; | |
14465 | } | |
14466 | else if (sizeflag & DFLAG) | |
14467 | *obufp++ = 'w'; | |
a35ca55a | 14468 | else |
0bfee649 L |
14469 | *obufp++ = 'b'; |
14470 | if (!(rex & REX_W)) | |
14471 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 14472 | } |
252b5132 | 14473 | else |
0bfee649 | 14474 | { |
6c30d220 L |
14475 | if (l != 1 |
14476 | || len != 2 | |
14477 | || (last[0] != 'X' | |
14478 | && last[0] != 'L')) | |
0bfee649 L |
14479 | { |
14480 | SAVE_LAST (*p); | |
14481 | break; | |
14482 | } | |
14483 | if (!need_vex) | |
14484 | abort (); | |
6c30d220 L |
14485 | if (last[0] == 'X') |
14486 | *obufp++ = vex.w ? 'd': 's'; | |
14487 | else | |
14488 | *obufp++ = vex.w ? 'q': 'd'; | |
0bfee649 | 14489 | } |
252b5132 | 14490 | break; |
a72d2af2 L |
14491 | case '^': |
14492 | if (intel_syntax) | |
14493 | break; | |
14494 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
14495 | { | |
14496 | if (sizeflag & DFLAG) | |
14497 | *obufp++ = 'l'; | |
14498 | else | |
14499 | *obufp++ = 'w'; | |
14500 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14501 | } | |
14502 | break; | |
5db04b09 L |
14503 | case '@': |
14504 | if (intel_syntax) | |
14505 | break; | |
14506 | if (address_mode == mode_64bit | |
14507 | && (isa64 == intel64 | |
14508 | || ((sizeflag & DFLAG) || (rex & REX_W)))) | |
14509 | *obufp++ = 'q'; | |
14510 | else if ((prefixes & PREFIX_DATA)) | |
14511 | { | |
14512 | if (!(sizeflag & DFLAG)) | |
14513 | *obufp++ = 'w'; | |
14514 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14515 | } | |
14516 | break; | |
252b5132 | 14517 | } |
9306ca4a | 14518 | alt = 0; |
252b5132 RH |
14519 | } |
14520 | *obufp = 0; | |
ea397f5b | 14521 | mnemonicendp = obufp; |
6439fc28 | 14522 | return 0; |
252b5132 RH |
14523 | } |
14524 | ||
14525 | static void | |
26ca5450 | 14526 | oappend (const char *s) |
252b5132 | 14527 | { |
ea397f5b | 14528 | obufp = stpcpy (obufp, s); |
252b5132 RH |
14529 | } |
14530 | ||
14531 | static void | |
26ca5450 | 14532 | append_seg (void) |
252b5132 | 14533 | { |
285ca992 L |
14534 | /* Only print the active segment register. */ |
14535 | if (!active_seg_prefix) | |
14536 | return; | |
14537 | ||
14538 | used_prefixes |= active_seg_prefix; | |
14539 | switch (active_seg_prefix) | |
7d421014 | 14540 | { |
285ca992 | 14541 | case PREFIX_CS: |
9ce09ba2 | 14542 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
14543 | break; |
14544 | case PREFIX_DS: | |
9ce09ba2 | 14545 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
14546 | break; |
14547 | case PREFIX_SS: | |
9ce09ba2 | 14548 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
14549 | break; |
14550 | case PREFIX_ES: | |
9ce09ba2 | 14551 | oappend_maybe_intel ("%es:"); |
285ca992 L |
14552 | break; |
14553 | case PREFIX_FS: | |
9ce09ba2 | 14554 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
14555 | break; |
14556 | case PREFIX_GS: | |
9ce09ba2 | 14557 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
14558 | break; |
14559 | default: | |
14560 | break; | |
7d421014 | 14561 | } |
252b5132 RH |
14562 | } |
14563 | ||
14564 | static void | |
26ca5450 | 14565 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
14566 | { |
14567 | if (!intel_syntax) | |
14568 | oappend ("*"); | |
14569 | OP_E (bytemode, sizeflag); | |
14570 | } | |
14571 | ||
52b15da3 | 14572 | static void |
26ca5450 | 14573 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 14574 | { |
cb712a9e | 14575 | if (address_mode == mode_64bit) |
52b15da3 JH |
14576 | { |
14577 | if (hex) | |
14578 | { | |
14579 | char tmp[30]; | |
14580 | int i; | |
14581 | buf[0] = '0'; | |
14582 | buf[1] = 'x'; | |
14583 | sprintf_vma (tmp, disp); | |
6608db57 | 14584 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
14585 | strcpy (buf + 2, tmp + i); |
14586 | } | |
14587 | else | |
14588 | { | |
14589 | bfd_signed_vma v = disp; | |
14590 | char tmp[30]; | |
14591 | int i; | |
14592 | if (v < 0) | |
14593 | { | |
14594 | *(buf++) = '-'; | |
14595 | v = -disp; | |
6608db57 | 14596 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
14597 | if (v < 0) |
14598 | { | |
14599 | strcpy (buf, "9223372036854775808"); | |
14600 | return; | |
14601 | } | |
14602 | } | |
14603 | if (!v) | |
14604 | { | |
14605 | strcpy (buf, "0"); | |
14606 | return; | |
14607 | } | |
14608 | ||
14609 | i = 0; | |
14610 | tmp[29] = 0; | |
14611 | while (v) | |
14612 | { | |
6608db57 | 14613 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
14614 | v /= 10; |
14615 | i++; | |
14616 | } | |
14617 | strcpy (buf, tmp + 29 - i); | |
14618 | } | |
14619 | } | |
14620 | else | |
14621 | { | |
14622 | if (hex) | |
14623 | sprintf (buf, "0x%x", (unsigned int) disp); | |
14624 | else | |
14625 | sprintf (buf, "%d", (int) disp); | |
14626 | } | |
14627 | } | |
14628 | ||
5d669648 L |
14629 | /* Put DISP in BUF as signed hex number. */ |
14630 | ||
14631 | static void | |
14632 | print_displacement (char *buf, bfd_vma disp) | |
14633 | { | |
14634 | bfd_signed_vma val = disp; | |
14635 | char tmp[30]; | |
14636 | int i, j = 0; | |
14637 | ||
14638 | if (val < 0) | |
14639 | { | |
14640 | buf[j++] = '-'; | |
14641 | val = -disp; | |
14642 | ||
14643 | /* Check for possible overflow. */ | |
14644 | if (val < 0) | |
14645 | { | |
14646 | switch (address_mode) | |
14647 | { | |
14648 | case mode_64bit: | |
14649 | strcpy (buf + j, "0x8000000000000000"); | |
14650 | break; | |
14651 | case mode_32bit: | |
14652 | strcpy (buf + j, "0x80000000"); | |
14653 | break; | |
14654 | case mode_16bit: | |
14655 | strcpy (buf + j, "0x8000"); | |
14656 | break; | |
14657 | } | |
14658 | return; | |
14659 | } | |
14660 | } | |
14661 | ||
14662 | buf[j++] = '0'; | |
14663 | buf[j++] = 'x'; | |
14664 | ||
0af1713e | 14665 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
14666 | for (i = 0; tmp[i] == '0'; i++) |
14667 | continue; | |
14668 | if (tmp[i] == '\0') | |
14669 | i--; | |
14670 | strcpy (buf + j, tmp + i); | |
14671 | } | |
14672 | ||
3f31e633 JB |
14673 | static void |
14674 | intel_operand_size (int bytemode, int sizeflag) | |
14675 | { | |
43234a1e L |
14676 | if (vex.evex |
14677 | && vex.b | |
14678 | && (bytemode == x_mode | |
14679 | || bytemode == evex_half_bcst_xmmq_mode)) | |
14680 | { | |
14681 | if (vex.w) | |
14682 | oappend ("QWORD PTR "); | |
14683 | else | |
14684 | oappend ("DWORD PTR "); | |
14685 | return; | |
14686 | } | |
3f31e633 JB |
14687 | switch (bytemode) |
14688 | { | |
14689 | case b_mode: | |
b6169b20 | 14690 | case b_swap_mode: |
42903f7f | 14691 | case dqb_mode: |
1ba585e8 | 14692 | case db_mode: |
3f31e633 JB |
14693 | oappend ("BYTE PTR "); |
14694 | break; | |
14695 | case w_mode: | |
1ba585e8 | 14696 | case dw_mode: |
3f31e633 JB |
14697 | case dqw_mode: |
14698 | oappend ("WORD PTR "); | |
14699 | break; | |
07f5af7d L |
14700 | case indir_v_mode: |
14701 | if (address_mode == mode_64bit && isa64 == intel64) | |
14702 | { | |
14703 | oappend ("QWORD PTR "); | |
14704 | break; | |
14705 | } | |
1a0670f3 | 14706 | /* Fall through. */ |
1a114b12 | 14707 | case stack_v_mode: |
7bb15c6f | 14708 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
14709 | { |
14710 | oappend ("QWORD PTR "); | |
3f31e633 JB |
14711 | break; |
14712 | } | |
1a0670f3 | 14713 | /* Fall through. */ |
3f31e633 | 14714 | case v_mode: |
b6169b20 | 14715 | case v_swap_mode: |
3f31e633 | 14716 | case dq_mode: |
161a04f6 L |
14717 | USED_REX (REX_W); |
14718 | if (rex & REX_W) | |
3f31e633 | 14719 | oappend ("QWORD PTR "); |
3f31e633 | 14720 | else |
f16cd0d5 L |
14721 | { |
14722 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
14723 | oappend ("DWORD PTR "); | |
14724 | else | |
14725 | oappend ("WORD PTR "); | |
14726 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14727 | } | |
3f31e633 | 14728 | break; |
52fd6d94 | 14729 | case z_mode: |
161a04f6 | 14730 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14731 | *obufp++ = 'D'; |
14732 | oappend ("WORD PTR "); | |
161a04f6 | 14733 | if (!(rex & REX_W)) |
52fd6d94 JB |
14734 | used_prefixes |= (prefixes & PREFIX_DATA); |
14735 | break; | |
34b772a6 JB |
14736 | case a_mode: |
14737 | if (sizeflag & DFLAG) | |
14738 | oappend ("QWORD PTR "); | |
14739 | else | |
14740 | oappend ("DWORD PTR "); | |
14741 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14742 | break; | |
3f31e633 | 14743 | case d_mode: |
539f890d L |
14744 | case d_scalar_mode: |
14745 | case d_scalar_swap_mode: | |
fa99fab2 | 14746 | case d_swap_mode: |
42903f7f | 14747 | case dqd_mode: |
3f31e633 JB |
14748 | oappend ("DWORD PTR "); |
14749 | break; | |
14750 | case q_mode: | |
539f890d L |
14751 | case q_scalar_mode: |
14752 | case q_scalar_swap_mode: | |
b6169b20 | 14753 | case q_swap_mode: |
3f31e633 JB |
14754 | oappend ("QWORD PTR "); |
14755 | break; | |
14756 | case m_mode: | |
cb712a9e | 14757 | if (address_mode == mode_64bit) |
3f31e633 JB |
14758 | oappend ("QWORD PTR "); |
14759 | else | |
14760 | oappend ("DWORD PTR "); | |
14761 | break; | |
14762 | case f_mode: | |
14763 | if (sizeflag & DFLAG) | |
14764 | oappend ("FWORD PTR "); | |
14765 | else | |
14766 | oappend ("DWORD PTR "); | |
14767 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14768 | break; | |
14769 | case t_mode: | |
14770 | oappend ("TBYTE PTR "); | |
14771 | break; | |
14772 | case x_mode: | |
b6169b20 | 14773 | case x_swap_mode: |
43234a1e L |
14774 | case evex_x_gscat_mode: |
14775 | case evex_x_nobcst_mode: | |
53467f57 IT |
14776 | case b_scalar_mode: |
14777 | case w_scalar_mode: | |
c0f3af97 L |
14778 | if (need_vex) |
14779 | { | |
14780 | switch (vex.length) | |
14781 | { | |
14782 | case 128: | |
14783 | oappend ("XMMWORD PTR "); | |
14784 | break; | |
14785 | case 256: | |
14786 | oappend ("YMMWORD PTR "); | |
14787 | break; | |
43234a1e L |
14788 | case 512: |
14789 | oappend ("ZMMWORD PTR "); | |
14790 | break; | |
c0f3af97 L |
14791 | default: |
14792 | abort (); | |
14793 | } | |
14794 | } | |
14795 | else | |
14796 | oappend ("XMMWORD PTR "); | |
14797 | break; | |
14798 | case xmm_mode: | |
3f31e633 JB |
14799 | oappend ("XMMWORD PTR "); |
14800 | break; | |
43234a1e L |
14801 | case ymm_mode: |
14802 | oappend ("YMMWORD PTR "); | |
14803 | break; | |
c0f3af97 | 14804 | case xmmq_mode: |
43234a1e | 14805 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
14806 | if (!need_vex) |
14807 | abort (); | |
14808 | ||
14809 | switch (vex.length) | |
14810 | { | |
14811 | case 128: | |
14812 | oappend ("QWORD PTR "); | |
14813 | break; | |
14814 | case 256: | |
14815 | oappend ("XMMWORD PTR "); | |
14816 | break; | |
43234a1e L |
14817 | case 512: |
14818 | oappend ("YMMWORD PTR "); | |
14819 | break; | |
c0f3af97 L |
14820 | default: |
14821 | abort (); | |
14822 | } | |
14823 | break; | |
6c30d220 L |
14824 | case xmm_mb_mode: |
14825 | if (!need_vex) | |
14826 | abort (); | |
14827 | ||
14828 | switch (vex.length) | |
14829 | { | |
14830 | case 128: | |
14831 | case 256: | |
43234a1e | 14832 | case 512: |
6c30d220 L |
14833 | oappend ("BYTE PTR "); |
14834 | break; | |
14835 | default: | |
14836 | abort (); | |
14837 | } | |
14838 | break; | |
14839 | case xmm_mw_mode: | |
14840 | if (!need_vex) | |
14841 | abort (); | |
14842 | ||
14843 | switch (vex.length) | |
14844 | { | |
14845 | case 128: | |
14846 | case 256: | |
43234a1e | 14847 | case 512: |
6c30d220 L |
14848 | oappend ("WORD PTR "); |
14849 | break; | |
14850 | default: | |
14851 | abort (); | |
14852 | } | |
14853 | break; | |
14854 | case xmm_md_mode: | |
14855 | if (!need_vex) | |
14856 | abort (); | |
14857 | ||
14858 | switch (vex.length) | |
14859 | { | |
14860 | case 128: | |
14861 | case 256: | |
43234a1e | 14862 | case 512: |
6c30d220 L |
14863 | oappend ("DWORD PTR "); |
14864 | break; | |
14865 | default: | |
14866 | abort (); | |
14867 | } | |
14868 | break; | |
14869 | case xmm_mq_mode: | |
14870 | if (!need_vex) | |
14871 | abort (); | |
14872 | ||
14873 | switch (vex.length) | |
14874 | { | |
14875 | case 128: | |
14876 | case 256: | |
43234a1e | 14877 | case 512: |
6c30d220 L |
14878 | oappend ("QWORD PTR "); |
14879 | break; | |
14880 | default: | |
14881 | abort (); | |
14882 | } | |
14883 | break; | |
14884 | case xmmdw_mode: | |
14885 | if (!need_vex) | |
14886 | abort (); | |
14887 | ||
14888 | switch (vex.length) | |
14889 | { | |
14890 | case 128: | |
14891 | oappend ("WORD PTR "); | |
14892 | break; | |
14893 | case 256: | |
14894 | oappend ("DWORD PTR "); | |
14895 | break; | |
43234a1e L |
14896 | case 512: |
14897 | oappend ("QWORD PTR "); | |
14898 | break; | |
6c30d220 L |
14899 | default: |
14900 | abort (); | |
14901 | } | |
14902 | break; | |
14903 | case xmmqd_mode: | |
14904 | if (!need_vex) | |
14905 | abort (); | |
14906 | ||
14907 | switch (vex.length) | |
14908 | { | |
14909 | case 128: | |
14910 | oappend ("DWORD PTR "); | |
14911 | break; | |
14912 | case 256: | |
14913 | oappend ("QWORD PTR "); | |
14914 | break; | |
43234a1e L |
14915 | case 512: |
14916 | oappend ("XMMWORD PTR "); | |
14917 | break; | |
6c30d220 L |
14918 | default: |
14919 | abort (); | |
14920 | } | |
14921 | break; | |
c0f3af97 L |
14922 | case ymmq_mode: |
14923 | if (!need_vex) | |
14924 | abort (); | |
14925 | ||
14926 | switch (vex.length) | |
14927 | { | |
14928 | case 128: | |
14929 | oappend ("QWORD PTR "); | |
14930 | break; | |
14931 | case 256: | |
14932 | oappend ("YMMWORD PTR "); | |
14933 | break; | |
43234a1e L |
14934 | case 512: |
14935 | oappend ("ZMMWORD PTR "); | |
14936 | break; | |
c0f3af97 L |
14937 | default: |
14938 | abort (); | |
14939 | } | |
14940 | break; | |
6c30d220 L |
14941 | case ymmxmm_mode: |
14942 | if (!need_vex) | |
14943 | abort (); | |
14944 | ||
14945 | switch (vex.length) | |
14946 | { | |
14947 | case 128: | |
14948 | case 256: | |
14949 | oappend ("XMMWORD PTR "); | |
14950 | break; | |
14951 | default: | |
14952 | abort (); | |
14953 | } | |
14954 | break; | |
fb9c77c7 L |
14955 | case o_mode: |
14956 | oappend ("OWORD PTR "); | |
14957 | break; | |
43234a1e | 14958 | case xmm_mdq_mode: |
0bfee649 | 14959 | case vex_w_dq_mode: |
1c480963 | 14960 | case vex_scalar_w_dq_mode: |
0bfee649 L |
14961 | if (!need_vex) |
14962 | abort (); | |
14963 | ||
14964 | if (vex.w) | |
14965 | oappend ("QWORD PTR "); | |
14966 | else | |
14967 | oappend ("DWORD PTR "); | |
14968 | break; | |
43234a1e L |
14969 | case vex_vsib_d_w_dq_mode: |
14970 | case vex_vsib_q_w_dq_mode: | |
14971 | if (!need_vex) | |
14972 | abort (); | |
14973 | ||
14974 | if (!vex.evex) | |
14975 | { | |
14976 | if (vex.w) | |
14977 | oappend ("QWORD PTR "); | |
14978 | else | |
14979 | oappend ("DWORD PTR "); | |
14980 | } | |
14981 | else | |
14982 | { | |
b28d1bda IT |
14983 | switch (vex.length) |
14984 | { | |
14985 | case 128: | |
14986 | oappend ("XMMWORD PTR "); | |
14987 | break; | |
14988 | case 256: | |
14989 | oappend ("YMMWORD PTR "); | |
14990 | break; | |
14991 | case 512: | |
14992 | oappend ("ZMMWORD PTR "); | |
14993 | break; | |
14994 | default: | |
14995 | abort (); | |
14996 | } | |
43234a1e L |
14997 | } |
14998 | break; | |
5fc35d96 IT |
14999 | case vex_vsib_q_w_d_mode: |
15000 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 15001 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
15002 | abort (); |
15003 | ||
b28d1bda IT |
15004 | switch (vex.length) |
15005 | { | |
15006 | case 128: | |
15007 | oappend ("QWORD PTR "); | |
15008 | break; | |
15009 | case 256: | |
15010 | oappend ("XMMWORD PTR "); | |
15011 | break; | |
15012 | case 512: | |
15013 | oappend ("YMMWORD PTR "); | |
15014 | break; | |
15015 | default: | |
15016 | abort (); | |
15017 | } | |
5fc35d96 IT |
15018 | |
15019 | break; | |
1ba585e8 IT |
15020 | case mask_bd_mode: |
15021 | if (!need_vex || vex.length != 128) | |
15022 | abort (); | |
15023 | if (vex.w) | |
15024 | oappend ("DWORD PTR "); | |
15025 | else | |
15026 | oappend ("BYTE PTR "); | |
15027 | break; | |
43234a1e L |
15028 | case mask_mode: |
15029 | if (!need_vex) | |
15030 | abort (); | |
1ba585e8 IT |
15031 | if (vex.w) |
15032 | oappend ("QWORD PTR "); | |
15033 | else | |
15034 | oappend ("WORD PTR "); | |
43234a1e | 15035 | break; |
6c75cc62 | 15036 | case v_bnd_mode: |
3f31e633 JB |
15037 | default: |
15038 | break; | |
15039 | } | |
15040 | } | |
15041 | ||
252b5132 | 15042 | static void |
c0f3af97 | 15043 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 15044 | { |
c0f3af97 L |
15045 | int reg = modrm.rm; |
15046 | const char **names; | |
252b5132 | 15047 | |
c0f3af97 L |
15048 | USED_REX (REX_B); |
15049 | if ((rex & REX_B)) | |
15050 | reg += 8; | |
252b5132 | 15051 | |
b6169b20 | 15052 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 | 15053 | && (bytemode == b_swap_mode |
9f79e886 | 15054 | || bytemode == bnd_swap_mode |
60227d64 | 15055 | || bytemode == v_swap_mode)) |
b6169b20 L |
15056 | swap_operand (); |
15057 | ||
c0f3af97 | 15058 | switch (bytemode) |
252b5132 | 15059 | { |
c0f3af97 | 15060 | case b_mode: |
b6169b20 | 15061 | case b_swap_mode: |
c0f3af97 L |
15062 | USED_REX (0); |
15063 | if (rex) | |
15064 | names = names8rex; | |
15065 | else | |
15066 | names = names8; | |
15067 | break; | |
15068 | case w_mode: | |
15069 | names = names16; | |
15070 | break; | |
15071 | case d_mode: | |
1ba585e8 IT |
15072 | case dw_mode: |
15073 | case db_mode: | |
c0f3af97 L |
15074 | names = names32; |
15075 | break; | |
15076 | case q_mode: | |
15077 | names = names64; | |
15078 | break; | |
15079 | case m_mode: | |
6c75cc62 | 15080 | case v_bnd_mode: |
c0f3af97 L |
15081 | names = address_mode == mode_64bit ? names64 : names32; |
15082 | break; | |
7e8b059b | 15083 | case bnd_mode: |
9f79e886 | 15084 | case bnd_swap_mode: |
0d96e4df L |
15085 | if (reg > 0x3) |
15086 | { | |
15087 | oappend ("(bad)"); | |
15088 | return; | |
15089 | } | |
7e8b059b L |
15090 | names = names_bnd; |
15091 | break; | |
07f5af7d L |
15092 | case indir_v_mode: |
15093 | if (address_mode == mode_64bit && isa64 == intel64) | |
15094 | { | |
15095 | names = names64; | |
15096 | break; | |
15097 | } | |
1a0670f3 | 15098 | /* Fall through. */ |
c0f3af97 | 15099 | case stack_v_mode: |
7bb15c6f | 15100 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 15101 | { |
c0f3af97 | 15102 | names = names64; |
252b5132 | 15103 | break; |
252b5132 | 15104 | } |
c0f3af97 | 15105 | bytemode = v_mode; |
1a0670f3 | 15106 | /* Fall through. */ |
c0f3af97 | 15107 | case v_mode: |
b6169b20 | 15108 | case v_swap_mode: |
c0f3af97 L |
15109 | case dq_mode: |
15110 | case dqb_mode: | |
15111 | case dqd_mode: | |
15112 | case dqw_mode: | |
15113 | USED_REX (REX_W); | |
15114 | if (rex & REX_W) | |
15115 | names = names64; | |
c0f3af97 | 15116 | else |
f16cd0d5 | 15117 | { |
7bb15c6f | 15118 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
15119 | || (bytemode != v_mode |
15120 | && bytemode != v_swap_mode)) | |
15121 | names = names32; | |
15122 | else | |
15123 | names = names16; | |
15124 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15125 | } | |
c0f3af97 | 15126 | break; |
1ba585e8 | 15127 | case mask_bd_mode: |
43234a1e | 15128 | case mask_mode: |
9889cbb1 L |
15129 | if (reg > 0x7) |
15130 | { | |
15131 | oappend ("(bad)"); | |
15132 | return; | |
15133 | } | |
43234a1e L |
15134 | names = names_mask; |
15135 | break; | |
c0f3af97 L |
15136 | case 0: |
15137 | return; | |
15138 | default: | |
15139 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
15140 | return; |
15141 | } | |
c0f3af97 L |
15142 | oappend (names[reg]); |
15143 | } | |
15144 | ||
15145 | static void | |
c1e679ec | 15146 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
15147 | { |
15148 | bfd_vma disp = 0; | |
15149 | int add = (rex & REX_B) ? 8 : 0; | |
15150 | int riprel = 0; | |
43234a1e L |
15151 | int shift; |
15152 | ||
15153 | if (vex.evex) | |
15154 | { | |
15155 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
15156 | if (vex.b | |
15157 | && bytemode != x_mode | |
90a915bf | 15158 | && bytemode != xmmq_mode |
43234a1e L |
15159 | && bytemode != evex_half_bcst_xmmq_mode) |
15160 | { | |
15161 | BadOp (); | |
15162 | return; | |
15163 | } | |
15164 | switch (bytemode) | |
15165 | { | |
1ba585e8 IT |
15166 | case dqw_mode: |
15167 | case dw_mode: | |
1ba585e8 IT |
15168 | shift = 1; |
15169 | break; | |
15170 | case dqb_mode: | |
15171 | case db_mode: | |
15172 | shift = 0; | |
15173 | break; | |
43234a1e | 15174 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 15175 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 15176 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15177 | case vex_vsib_q_w_d_mode: |
43234a1e L |
15178 | case evex_x_gscat_mode: |
15179 | case xmm_mdq_mode: | |
15180 | shift = vex.w ? 3 : 2; | |
15181 | break; | |
43234a1e L |
15182 | case x_mode: |
15183 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 15184 | case xmmq_mode: |
43234a1e L |
15185 | if (vex.b) |
15186 | { | |
15187 | shift = vex.w ? 3 : 2; | |
15188 | break; | |
15189 | } | |
1a0670f3 | 15190 | /* Fall through. */ |
43234a1e L |
15191 | case xmmqd_mode: |
15192 | case xmmdw_mode: | |
43234a1e L |
15193 | case ymmq_mode: |
15194 | case evex_x_nobcst_mode: | |
15195 | case x_swap_mode: | |
15196 | switch (vex.length) | |
15197 | { | |
15198 | case 128: | |
15199 | shift = 4; | |
15200 | break; | |
15201 | case 256: | |
15202 | shift = 5; | |
15203 | break; | |
15204 | case 512: | |
15205 | shift = 6; | |
15206 | break; | |
15207 | default: | |
15208 | abort (); | |
15209 | } | |
15210 | break; | |
15211 | case ymm_mode: | |
15212 | shift = 5; | |
15213 | break; | |
15214 | case xmm_mode: | |
15215 | shift = 4; | |
15216 | break; | |
15217 | case xmm_mq_mode: | |
15218 | case q_mode: | |
15219 | case q_scalar_mode: | |
15220 | case q_swap_mode: | |
15221 | case q_scalar_swap_mode: | |
15222 | shift = 3; | |
15223 | break; | |
15224 | case dqd_mode: | |
15225 | case xmm_md_mode: | |
15226 | case d_mode: | |
15227 | case d_scalar_mode: | |
15228 | case d_swap_mode: | |
15229 | case d_scalar_swap_mode: | |
15230 | shift = 2; | |
15231 | break; | |
53467f57 | 15232 | case w_scalar_mode: |
43234a1e L |
15233 | case xmm_mw_mode: |
15234 | shift = 1; | |
15235 | break; | |
53467f57 | 15236 | case b_scalar_mode: |
43234a1e L |
15237 | case xmm_mb_mode: |
15238 | shift = 0; | |
15239 | break; | |
15240 | default: | |
15241 | abort (); | |
15242 | } | |
15243 | /* Make necessary corrections to shift for modes that need it. | |
15244 | For these modes we currently have shift 4, 5 or 6 depending on | |
15245 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
15246 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
15247 | xmmq_mode). In case of broadcast enabled the corrections | |
15248 | aren't needed, as element size is always 32 or 64 bits. */ | |
90a915bf IT |
15249 | if (!vex.b |
15250 | && (bytemode == xmmq_mode | |
15251 | || bytemode == evex_half_bcst_xmmq_mode)) | |
43234a1e L |
15252 | shift -= 1; |
15253 | else if (bytemode == xmmqd_mode) | |
15254 | shift -= 2; | |
15255 | else if (bytemode == xmmdw_mode) | |
15256 | shift -= 3; | |
b28d1bda IT |
15257 | else if (bytemode == ymmq_mode && vex.length == 128) |
15258 | shift -= 1; | |
43234a1e L |
15259 | } |
15260 | else | |
15261 | shift = 0; | |
252b5132 | 15262 | |
c0f3af97 | 15263 | USED_REX (REX_B); |
3f31e633 JB |
15264 | if (intel_syntax) |
15265 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
15266 | append_seg (); |
15267 | ||
5d669648 | 15268 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 15269 | { |
5d669648 L |
15270 | /* 32/64 bit address mode */ |
15271 | int havedisp; | |
252b5132 RH |
15272 | int havesib; |
15273 | int havebase; | |
0f7da397 | 15274 | int haveindex; |
20afcfb7 | 15275 | int needindex; |
82c18208 | 15276 | int base, rbase; |
91d6fa6a | 15277 | int vindex = 0; |
252b5132 | 15278 | int scale = 0; |
7e8b059b L |
15279 | int addr32flag = !((sizeflag & AFLAG) |
15280 | || bytemode == v_bnd_mode | |
9f79e886 JB |
15281 | || bytemode == bnd_mode |
15282 | || bytemode == bnd_swap_mode); | |
6c30d220 L |
15283 | const char **indexes64 = names64; |
15284 | const char **indexes32 = names32; | |
252b5132 RH |
15285 | |
15286 | havesib = 0; | |
15287 | havebase = 1; | |
0f7da397 | 15288 | haveindex = 0; |
7967e09e | 15289 | base = modrm.rm; |
252b5132 RH |
15290 | |
15291 | if (base == 4) | |
15292 | { | |
15293 | havesib = 1; | |
dfc8cf43 | 15294 | vindex = sib.index; |
161a04f6 L |
15295 | USED_REX (REX_X); |
15296 | if (rex & REX_X) | |
91d6fa6a | 15297 | vindex += 8; |
6c30d220 L |
15298 | switch (bytemode) |
15299 | { | |
15300 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 15301 | case vex_vsib_d_w_d_mode: |
6c30d220 | 15302 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15303 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
15304 | if (!need_vex) |
15305 | abort (); | |
43234a1e L |
15306 | if (vex.evex) |
15307 | { | |
15308 | if (!vex.v) | |
15309 | vindex += 16; | |
15310 | } | |
6c30d220 L |
15311 | |
15312 | haveindex = 1; | |
15313 | switch (vex.length) | |
15314 | { | |
15315 | case 128: | |
7bb15c6f | 15316 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
15317 | break; |
15318 | case 256: | |
5fc35d96 IT |
15319 | if (!vex.w |
15320 | || bytemode == vex_vsib_q_w_dq_mode | |
15321 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 15322 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 15323 | else |
7bb15c6f | 15324 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 15325 | break; |
43234a1e | 15326 | case 512: |
5fc35d96 IT |
15327 | if (!vex.w |
15328 | || bytemode == vex_vsib_q_w_dq_mode | |
15329 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
15330 | indexes64 = indexes32 = names_zmm; |
15331 | else | |
15332 | indexes64 = indexes32 = names_ymm; | |
15333 | break; | |
6c30d220 L |
15334 | default: |
15335 | abort (); | |
15336 | } | |
15337 | break; | |
15338 | default: | |
15339 | haveindex = vindex != 4; | |
15340 | break; | |
15341 | } | |
15342 | scale = sib.scale; | |
15343 | base = sib.base; | |
252b5132 RH |
15344 | codep++; |
15345 | } | |
82c18208 | 15346 | rbase = base + add; |
252b5132 | 15347 | |
7967e09e | 15348 | switch (modrm.mod) |
252b5132 RH |
15349 | { |
15350 | case 0: | |
82c18208 | 15351 | if (base == 5) |
252b5132 RH |
15352 | { |
15353 | havebase = 0; | |
cb712a9e | 15354 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
15355 | riprel = 1; |
15356 | disp = get32s (); | |
252b5132 RH |
15357 | } |
15358 | break; | |
15359 | case 1: | |
15360 | FETCH_DATA (the_info, codep + 1); | |
15361 | disp = *codep++; | |
15362 | if ((disp & 0x80) != 0) | |
15363 | disp -= 0x100; | |
43234a1e L |
15364 | if (vex.evex && shift > 0) |
15365 | disp <<= shift; | |
252b5132 RH |
15366 | break; |
15367 | case 2: | |
52b15da3 | 15368 | disp = get32s (); |
252b5132 RH |
15369 | break; |
15370 | } | |
15371 | ||
20afcfb7 L |
15372 | /* In 32bit mode, we need index register to tell [offset] from |
15373 | [eiz*1 + offset]. */ | |
15374 | needindex = (havesib | |
15375 | && !havebase | |
15376 | && !haveindex | |
15377 | && address_mode == mode_32bit); | |
15378 | havedisp = (havebase | |
15379 | || needindex | |
15380 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 15381 | |
252b5132 | 15382 | if (!intel_syntax) |
82c18208 | 15383 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 15384 | { |
5d669648 L |
15385 | if (havedisp || riprel) |
15386 | print_displacement (scratchbuf, disp); | |
15387 | else | |
15388 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 15389 | oappend (scratchbuf); |
52b15da3 JH |
15390 | if (riprel) |
15391 | { | |
15392 | set_op (disp, 1); | |
28596323 | 15393 | oappend (!addr32flag ? "(%rip)" : "(%eip)"); |
52b15da3 | 15394 | } |
db6eb5be | 15395 | } |
2da11e11 | 15396 | |
7e8b059b L |
15397 | if ((havebase || haveindex || riprel) |
15398 | && (bytemode != v_bnd_mode) | |
9f79e886 JB |
15399 | && (bytemode != bnd_mode) |
15400 | && (bytemode != bnd_swap_mode)) | |
87767711 JB |
15401 | used_prefixes |= PREFIX_ADDR; |
15402 | ||
5d669648 | 15403 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 15404 | { |
252b5132 | 15405 | *obufp++ = open_char; |
52b15da3 | 15406 | if (intel_syntax && riprel) |
185b1163 L |
15407 | { |
15408 | set_op (disp, 1); | |
28596323 | 15409 | oappend (!addr32flag ? "rip" : "eip"); |
185b1163 | 15410 | } |
db6eb5be | 15411 | *obufp = '\0'; |
252b5132 | 15412 | if (havebase) |
7e8b059b | 15413 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 15414 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
15415 | if (havesib) |
15416 | { | |
db51cc60 L |
15417 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
15418 | print index to tell base + index from base. */ | |
15419 | if (scale != 0 | |
20afcfb7 | 15420 | || needindex |
db51cc60 L |
15421 | || haveindex |
15422 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 15423 | { |
9306ca4a | 15424 | if (!intel_syntax || havebase) |
db6eb5be | 15425 | { |
9306ca4a JB |
15426 | *obufp++ = separator_char; |
15427 | *obufp = '\0'; | |
db6eb5be | 15428 | } |
db51cc60 | 15429 | if (haveindex) |
7e8b059b | 15430 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 15431 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 15432 | else |
7e8b059b | 15433 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
15434 | ? index64 : index32); |
15435 | ||
db6eb5be AM |
15436 | *obufp++ = scale_char; |
15437 | *obufp = '\0'; | |
15438 | sprintf (scratchbuf, "%d", 1 << scale); | |
15439 | oappend (scratchbuf); | |
15440 | } | |
252b5132 | 15441 | } |
185b1163 | 15442 | if (intel_syntax |
82c18208 | 15443 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 15444 | { |
db51cc60 | 15445 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
15446 | { |
15447 | *obufp++ = '+'; | |
15448 | *obufp = '\0'; | |
15449 | } | |
05203043 | 15450 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
15451 | { |
15452 | *obufp++ = '-'; | |
15453 | *obufp = '\0'; | |
15454 | disp = - (bfd_signed_vma) disp; | |
15455 | } | |
15456 | ||
db51cc60 L |
15457 | if (havedisp) |
15458 | print_displacement (scratchbuf, disp); | |
15459 | else | |
15460 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
15461 | oappend (scratchbuf); |
15462 | } | |
252b5132 RH |
15463 | |
15464 | *obufp++ = close_char; | |
db6eb5be | 15465 | *obufp = '\0'; |
252b5132 RH |
15466 | } |
15467 | else if (intel_syntax) | |
db6eb5be | 15468 | { |
82c18208 | 15469 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 15470 | { |
285ca992 | 15471 | if (!active_seg_prefix) |
252b5132 | 15472 | { |
d708bcba | 15473 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
15474 | oappend (":"); |
15475 | } | |
52b15da3 | 15476 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
15477 | oappend (scratchbuf); |
15478 | } | |
15479 | } | |
252b5132 RH |
15480 | } |
15481 | else | |
f16cd0d5 L |
15482 | { |
15483 | /* 16 bit address mode */ | |
15484 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 15485 | switch (modrm.mod) |
252b5132 RH |
15486 | { |
15487 | case 0: | |
7967e09e | 15488 | if (modrm.rm == 6) |
252b5132 RH |
15489 | { |
15490 | disp = get16 (); | |
15491 | if ((disp & 0x8000) != 0) | |
15492 | disp -= 0x10000; | |
15493 | } | |
15494 | break; | |
15495 | case 1: | |
15496 | FETCH_DATA (the_info, codep + 1); | |
15497 | disp = *codep++; | |
15498 | if ((disp & 0x80) != 0) | |
15499 | disp -= 0x100; | |
65f3ed04 JB |
15500 | if (vex.evex && shift > 0) |
15501 | disp <<= shift; | |
252b5132 RH |
15502 | break; |
15503 | case 2: | |
15504 | disp = get16 (); | |
15505 | if ((disp & 0x8000) != 0) | |
15506 | disp -= 0x10000; | |
15507 | break; | |
15508 | } | |
15509 | ||
15510 | if (!intel_syntax) | |
7967e09e | 15511 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 15512 | { |
5d669648 | 15513 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
15514 | oappend (scratchbuf); |
15515 | } | |
252b5132 | 15516 | |
7967e09e | 15517 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
15518 | { |
15519 | *obufp++ = open_char; | |
db6eb5be | 15520 | *obufp = '\0'; |
7967e09e | 15521 | oappend (index16[modrm.rm]); |
5d669648 L |
15522 | if (intel_syntax |
15523 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 15524 | { |
5d669648 | 15525 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
15526 | { |
15527 | *obufp++ = '+'; | |
15528 | *obufp = '\0'; | |
15529 | } | |
7967e09e | 15530 | else if (modrm.mod != 1) |
3d456fa1 JB |
15531 | { |
15532 | *obufp++ = '-'; | |
15533 | *obufp = '\0'; | |
15534 | disp = - (bfd_signed_vma) disp; | |
15535 | } | |
15536 | ||
5d669648 | 15537 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
15538 | oappend (scratchbuf); |
15539 | } | |
15540 | ||
db6eb5be AM |
15541 | *obufp++ = close_char; |
15542 | *obufp = '\0'; | |
252b5132 | 15543 | } |
3d456fa1 JB |
15544 | else if (intel_syntax) |
15545 | { | |
285ca992 | 15546 | if (!active_seg_prefix) |
3d456fa1 JB |
15547 | { |
15548 | oappend (names_seg[ds_reg - es_reg]); | |
15549 | oappend (":"); | |
15550 | } | |
15551 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
15552 | oappend (scratchbuf); | |
15553 | } | |
252b5132 | 15554 | } |
43234a1e L |
15555 | if (vex.evex && vex.b |
15556 | && (bytemode == x_mode | |
90a915bf | 15557 | || bytemode == xmmq_mode |
43234a1e L |
15558 | || bytemode == evex_half_bcst_xmmq_mode)) |
15559 | { | |
90a915bf IT |
15560 | if (vex.w |
15561 | || bytemode == xmmq_mode | |
15562 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
15563 | { |
15564 | switch (vex.length) | |
15565 | { | |
15566 | case 128: | |
15567 | oappend ("{1to2}"); | |
15568 | break; | |
15569 | case 256: | |
15570 | oappend ("{1to4}"); | |
15571 | break; | |
15572 | case 512: | |
15573 | oappend ("{1to8}"); | |
15574 | break; | |
15575 | default: | |
15576 | abort (); | |
15577 | } | |
15578 | } | |
43234a1e | 15579 | else |
b28d1bda IT |
15580 | { |
15581 | switch (vex.length) | |
15582 | { | |
15583 | case 128: | |
15584 | oappend ("{1to4}"); | |
15585 | break; | |
15586 | case 256: | |
15587 | oappend ("{1to8}"); | |
15588 | break; | |
15589 | case 512: | |
15590 | oappend ("{1to16}"); | |
15591 | break; | |
15592 | default: | |
15593 | abort (); | |
15594 | } | |
15595 | } | |
43234a1e | 15596 | } |
252b5132 RH |
15597 | } |
15598 | ||
c0f3af97 | 15599 | static void |
8b3f93e7 | 15600 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
15601 | { |
15602 | /* Skip mod/rm byte. */ | |
15603 | MODRM_CHECK; | |
15604 | codep++; | |
15605 | ||
15606 | if (modrm.mod == 3) | |
15607 | OP_E_register (bytemode, sizeflag); | |
15608 | else | |
c1e679ec | 15609 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
15610 | } |
15611 | ||
252b5132 | 15612 | static void |
26ca5450 | 15613 | OP_G (int bytemode, int sizeflag) |
252b5132 | 15614 | { |
52b15da3 | 15615 | int add = 0; |
161a04f6 L |
15616 | USED_REX (REX_R); |
15617 | if (rex & REX_R) | |
52b15da3 | 15618 | add += 8; |
252b5132 RH |
15619 | switch (bytemode) |
15620 | { | |
15621 | case b_mode: | |
52b15da3 JH |
15622 | USED_REX (0); |
15623 | if (rex) | |
7967e09e | 15624 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 15625 | else |
7967e09e | 15626 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
15627 | break; |
15628 | case w_mode: | |
7967e09e | 15629 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
15630 | break; |
15631 | case d_mode: | |
1ba585e8 IT |
15632 | case db_mode: |
15633 | case dw_mode: | |
7967e09e | 15634 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
15635 | break; |
15636 | case q_mode: | |
7967e09e | 15637 | oappend (names64[modrm.reg + add]); |
252b5132 | 15638 | break; |
7e8b059b | 15639 | case bnd_mode: |
0d96e4df L |
15640 | if (modrm.reg > 0x3) |
15641 | { | |
15642 | oappend ("(bad)"); | |
15643 | return; | |
15644 | } | |
7e8b059b L |
15645 | oappend (names_bnd[modrm.reg]); |
15646 | break; | |
252b5132 | 15647 | case v_mode: |
9306ca4a | 15648 | case dq_mode: |
42903f7f L |
15649 | case dqb_mode: |
15650 | case dqd_mode: | |
9306ca4a | 15651 | case dqw_mode: |
161a04f6 L |
15652 | USED_REX (REX_W); |
15653 | if (rex & REX_W) | |
7967e09e | 15654 | oappend (names64[modrm.reg + add]); |
252b5132 | 15655 | else |
f16cd0d5 L |
15656 | { |
15657 | if ((sizeflag & DFLAG) || bytemode != v_mode) | |
15658 | oappend (names32[modrm.reg + add]); | |
15659 | else | |
15660 | oappend (names16[modrm.reg + add]); | |
15661 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15662 | } | |
252b5132 | 15663 | break; |
90700ea2 | 15664 | case m_mode: |
cb712a9e | 15665 | if (address_mode == mode_64bit) |
7967e09e | 15666 | oappend (names64[modrm.reg + add]); |
90700ea2 | 15667 | else |
7967e09e | 15668 | oappend (names32[modrm.reg + add]); |
90700ea2 | 15669 | break; |
1ba585e8 | 15670 | case mask_bd_mode: |
43234a1e | 15671 | case mask_mode: |
9889cbb1 L |
15672 | if ((modrm.reg + add) > 0x7) |
15673 | { | |
15674 | oappend ("(bad)"); | |
15675 | return; | |
15676 | } | |
43234a1e L |
15677 | oappend (names_mask[modrm.reg + add]); |
15678 | break; | |
252b5132 RH |
15679 | default: |
15680 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15681 | break; | |
15682 | } | |
15683 | } | |
15684 | ||
52b15da3 | 15685 | static bfd_vma |
26ca5450 | 15686 | get64 (void) |
52b15da3 | 15687 | { |
5dd0794d | 15688 | bfd_vma x; |
52b15da3 | 15689 | #ifdef BFD64 |
5dd0794d AM |
15690 | unsigned int a; |
15691 | unsigned int b; | |
15692 | ||
52b15da3 JH |
15693 | FETCH_DATA (the_info, codep + 8); |
15694 | a = *codep++ & 0xff; | |
15695 | a |= (*codep++ & 0xff) << 8; | |
15696 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 15697 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 15698 | b = *codep++ & 0xff; |
52b15da3 JH |
15699 | b |= (*codep++ & 0xff) << 8; |
15700 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 15701 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
15702 | x = a + ((bfd_vma) b << 32); |
15703 | #else | |
6608db57 | 15704 | abort (); |
5dd0794d | 15705 | x = 0; |
52b15da3 JH |
15706 | #endif |
15707 | return x; | |
15708 | } | |
15709 | ||
15710 | static bfd_signed_vma | |
26ca5450 | 15711 | get32 (void) |
252b5132 | 15712 | { |
52b15da3 | 15713 | bfd_signed_vma x = 0; |
252b5132 RH |
15714 | |
15715 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
15716 | x = *codep++ & (bfd_signed_vma) 0xff; |
15717 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15718 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15719 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15720 | return x; | |
15721 | } | |
15722 | ||
15723 | static bfd_signed_vma | |
26ca5450 | 15724 | get32s (void) |
52b15da3 JH |
15725 | { |
15726 | bfd_signed_vma x = 0; | |
15727 | ||
15728 | FETCH_DATA (the_info, codep + 4); | |
15729 | x = *codep++ & (bfd_signed_vma) 0xff; | |
15730 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15731 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15732 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15733 | ||
15734 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
15735 | ||
252b5132 RH |
15736 | return x; |
15737 | } | |
15738 | ||
15739 | static int | |
26ca5450 | 15740 | get16 (void) |
252b5132 RH |
15741 | { |
15742 | int x = 0; | |
15743 | ||
15744 | FETCH_DATA (the_info, codep + 2); | |
15745 | x = *codep++ & 0xff; | |
15746 | x |= (*codep++ & 0xff) << 8; | |
15747 | return x; | |
15748 | } | |
15749 | ||
15750 | static void | |
26ca5450 | 15751 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
15752 | { |
15753 | op_index[op_ad] = op_ad; | |
cb712a9e | 15754 | if (address_mode == mode_64bit) |
7081ff04 AJ |
15755 | { |
15756 | op_address[op_ad] = op; | |
15757 | op_riprel[op_ad] = riprel; | |
15758 | } | |
15759 | else | |
15760 | { | |
15761 | /* Mask to get a 32-bit address. */ | |
15762 | op_address[op_ad] = op & 0xffffffff; | |
15763 | op_riprel[op_ad] = riprel & 0xffffffff; | |
15764 | } | |
252b5132 RH |
15765 | } |
15766 | ||
15767 | static void | |
26ca5450 | 15768 | OP_REG (int code, int sizeflag) |
252b5132 | 15769 | { |
2da11e11 | 15770 | const char *s; |
9b60702d | 15771 | int add; |
de882298 RM |
15772 | |
15773 | switch (code) | |
15774 | { | |
15775 | case es_reg: case ss_reg: case cs_reg: | |
15776 | case ds_reg: case fs_reg: case gs_reg: | |
15777 | oappend (names_seg[code - es_reg]); | |
15778 | return; | |
15779 | } | |
15780 | ||
161a04f6 L |
15781 | USED_REX (REX_B); |
15782 | if (rex & REX_B) | |
52b15da3 | 15783 | add = 8; |
9b60702d L |
15784 | else |
15785 | add = 0; | |
52b15da3 JH |
15786 | |
15787 | switch (code) | |
15788 | { | |
52b15da3 JH |
15789 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
15790 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15791 | s = names16[code - ax_reg + add]; | |
15792 | break; | |
52b15da3 JH |
15793 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
15794 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
15795 | USED_REX (0); | |
15796 | if (rex) | |
15797 | s = names8rex[code - al_reg + add]; | |
15798 | else | |
15799 | s = names8[code - al_reg]; | |
15800 | break; | |
6439fc28 AM |
15801 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
15802 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 15803 | if (address_mode == mode_64bit |
6c067bbb | 15804 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
15805 | { |
15806 | s = names64[code - rAX_reg + add]; | |
15807 | break; | |
15808 | } | |
15809 | code += eAX_reg - rAX_reg; | |
6608db57 | 15810 | /* Fall through. */ |
52b15da3 JH |
15811 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
15812 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15813 | USED_REX (REX_W); |
15814 | if (rex & REX_W) | |
52b15da3 | 15815 | s = names64[code - eAX_reg + add]; |
52b15da3 | 15816 | else |
f16cd0d5 L |
15817 | { |
15818 | if (sizeflag & DFLAG) | |
15819 | s = names32[code - eAX_reg + add]; | |
15820 | else | |
15821 | s = names16[code - eAX_reg + add]; | |
15822 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15823 | } | |
52b15da3 | 15824 | break; |
52b15da3 JH |
15825 | default: |
15826 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15827 | break; | |
15828 | } | |
15829 | oappend (s); | |
15830 | } | |
15831 | ||
15832 | static void | |
26ca5450 | 15833 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
15834 | { |
15835 | const char *s; | |
252b5132 RH |
15836 | |
15837 | switch (code) | |
15838 | { | |
15839 | case indir_dx_reg: | |
d708bcba | 15840 | if (intel_syntax) |
52fd6d94 | 15841 | s = "dx"; |
d708bcba | 15842 | else |
db6eb5be | 15843 | s = "(%dx)"; |
252b5132 RH |
15844 | break; |
15845 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
15846 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15847 | s = names16[code - ax_reg]; | |
15848 | break; | |
15849 | case es_reg: case ss_reg: case cs_reg: | |
15850 | case ds_reg: case fs_reg: case gs_reg: | |
15851 | s = names_seg[code - es_reg]; | |
15852 | break; | |
15853 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
15854 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
15855 | USED_REX (0); |
15856 | if (rex) | |
15857 | s = names8rex[code - al_reg]; | |
15858 | else | |
15859 | s = names8[code - al_reg]; | |
252b5132 RH |
15860 | break; |
15861 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
15862 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15863 | USED_REX (REX_W); |
15864 | if (rex & REX_W) | |
52b15da3 | 15865 | s = names64[code - eAX_reg]; |
252b5132 | 15866 | else |
f16cd0d5 L |
15867 | { |
15868 | if (sizeflag & DFLAG) | |
15869 | s = names32[code - eAX_reg]; | |
15870 | else | |
15871 | s = names16[code - eAX_reg]; | |
15872 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15873 | } | |
252b5132 | 15874 | break; |
52fd6d94 | 15875 | case z_mode_ax_reg: |
161a04f6 | 15876 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
15877 | s = *names32; |
15878 | else | |
15879 | s = *names16; | |
161a04f6 | 15880 | if (!(rex & REX_W)) |
52fd6d94 JB |
15881 | used_prefixes |= (prefixes & PREFIX_DATA); |
15882 | break; | |
252b5132 RH |
15883 | default: |
15884 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15885 | break; | |
15886 | } | |
15887 | oappend (s); | |
15888 | } | |
15889 | ||
15890 | static void | |
26ca5450 | 15891 | OP_I (int bytemode, int sizeflag) |
252b5132 | 15892 | { |
52b15da3 JH |
15893 | bfd_signed_vma op; |
15894 | bfd_signed_vma mask = -1; | |
252b5132 RH |
15895 | |
15896 | switch (bytemode) | |
15897 | { | |
15898 | case b_mode: | |
15899 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
15900 | op = *codep++; |
15901 | mask = 0xff; | |
15902 | break; | |
15903 | case q_mode: | |
cb712a9e | 15904 | if (address_mode == mode_64bit) |
6439fc28 AM |
15905 | { |
15906 | op = get32s (); | |
15907 | break; | |
15908 | } | |
6608db57 | 15909 | /* Fall through. */ |
252b5132 | 15910 | case v_mode: |
161a04f6 L |
15911 | USED_REX (REX_W); |
15912 | if (rex & REX_W) | |
52b15da3 | 15913 | op = get32s (); |
252b5132 | 15914 | else |
52b15da3 | 15915 | { |
f16cd0d5 L |
15916 | if (sizeflag & DFLAG) |
15917 | { | |
15918 | op = get32 (); | |
15919 | mask = 0xffffffff; | |
15920 | } | |
15921 | else | |
15922 | { | |
15923 | op = get16 (); | |
15924 | mask = 0xfffff; | |
15925 | } | |
15926 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 15927 | } |
252b5132 RH |
15928 | break; |
15929 | case w_mode: | |
52b15da3 | 15930 | mask = 0xfffff; |
252b5132 RH |
15931 | op = get16 (); |
15932 | break; | |
9306ca4a JB |
15933 | case const_1_mode: |
15934 | if (intel_syntax) | |
6c067bbb | 15935 | oappend ("1"); |
9306ca4a | 15936 | return; |
252b5132 RH |
15937 | default: |
15938 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15939 | return; | |
15940 | } | |
15941 | ||
52b15da3 JH |
15942 | op &= mask; |
15943 | scratchbuf[0] = '$'; | |
d708bcba | 15944 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 15945 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
15946 | scratchbuf[0] = '\0'; |
15947 | } | |
15948 | ||
15949 | static void | |
26ca5450 | 15950 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 JH |
15951 | { |
15952 | bfd_signed_vma op; | |
15953 | bfd_signed_vma mask = -1; | |
15954 | ||
cb712a9e | 15955 | if (address_mode != mode_64bit) |
6439fc28 AM |
15956 | { |
15957 | OP_I (bytemode, sizeflag); | |
15958 | return; | |
15959 | } | |
15960 | ||
52b15da3 JH |
15961 | switch (bytemode) |
15962 | { | |
15963 | case b_mode: | |
15964 | FETCH_DATA (the_info, codep + 1); | |
15965 | op = *codep++; | |
15966 | mask = 0xff; | |
15967 | break; | |
15968 | case v_mode: | |
161a04f6 L |
15969 | USED_REX (REX_W); |
15970 | if (rex & REX_W) | |
52b15da3 | 15971 | op = get64 (); |
52b15da3 JH |
15972 | else |
15973 | { | |
f16cd0d5 L |
15974 | if (sizeflag & DFLAG) |
15975 | { | |
15976 | op = get32 (); | |
15977 | mask = 0xffffffff; | |
15978 | } | |
15979 | else | |
15980 | { | |
15981 | op = get16 (); | |
15982 | mask = 0xfffff; | |
15983 | } | |
15984 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 15985 | } |
52b15da3 JH |
15986 | break; |
15987 | case w_mode: | |
15988 | mask = 0xfffff; | |
15989 | op = get16 (); | |
15990 | break; | |
15991 | default: | |
15992 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15993 | return; | |
15994 | } | |
15995 | ||
15996 | op &= mask; | |
15997 | scratchbuf[0] = '$'; | |
d708bcba | 15998 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 15999 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16000 | scratchbuf[0] = '\0'; |
16001 | } | |
16002 | ||
16003 | static void | |
26ca5450 | 16004 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 16005 | { |
52b15da3 | 16006 | bfd_signed_vma op; |
252b5132 RH |
16007 | |
16008 | switch (bytemode) | |
16009 | { | |
16010 | case b_mode: | |
e3949f17 | 16011 | case b_T_mode: |
252b5132 RH |
16012 | FETCH_DATA (the_info, codep + 1); |
16013 | op = *codep++; | |
16014 | if ((op & 0x80) != 0) | |
16015 | op -= 0x100; | |
e3949f17 L |
16016 | if (bytemode == b_T_mode) |
16017 | { | |
16018 | if (address_mode != mode_64bit | |
7bb15c6f | 16019 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 16020 | { |
6c067bbb RM |
16021 | /* The operand-size prefix is overridden by a REX prefix. */ |
16022 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
16023 | op &= 0xffffffff; |
16024 | else | |
16025 | op &= 0xffff; | |
16026 | } | |
16027 | } | |
16028 | else | |
16029 | { | |
16030 | if (!(rex & REX_W)) | |
16031 | { | |
16032 | if (sizeflag & DFLAG) | |
16033 | op &= 0xffffffff; | |
16034 | else | |
16035 | op &= 0xffff; | |
16036 | } | |
16037 | } | |
252b5132 RH |
16038 | break; |
16039 | case v_mode: | |
7bb15c6f RM |
16040 | /* The operand-size prefix is overridden by a REX prefix. */ |
16041 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 16042 | op = get32s (); |
252b5132 | 16043 | else |
d9e3625e | 16044 | op = get16 (); |
252b5132 RH |
16045 | break; |
16046 | default: | |
16047 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16048 | return; | |
16049 | } | |
52b15da3 JH |
16050 | |
16051 | scratchbuf[0] = '$'; | |
16052 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 16053 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16054 | } |
16055 | ||
16056 | static void | |
26ca5450 | 16057 | OP_J (int bytemode, int sizeflag) |
252b5132 | 16058 | { |
52b15da3 | 16059 | bfd_vma disp; |
7081ff04 | 16060 | bfd_vma mask = -1; |
65ca155d | 16061 | bfd_vma segment = 0; |
252b5132 RH |
16062 | |
16063 | switch (bytemode) | |
16064 | { | |
16065 | case b_mode: | |
16066 | FETCH_DATA (the_info, codep + 1); | |
16067 | disp = *codep++; | |
16068 | if ((disp & 0x80) != 0) | |
16069 | disp -= 0x100; | |
16070 | break; | |
16071 | case v_mode: | |
5db04b09 L |
16072 | if (isa64 == amd64) |
16073 | USED_REX (REX_W); | |
16074 | if ((sizeflag & DFLAG) | |
16075 | || (address_mode == mode_64bit | |
16076 | && (isa64 != amd64 || (rex & REX_W)))) | |
52b15da3 | 16077 | disp = get32s (); |
252b5132 RH |
16078 | else |
16079 | { | |
16080 | disp = get16 (); | |
206717e8 L |
16081 | if ((disp & 0x8000) != 0) |
16082 | disp -= 0x10000; | |
65ca155d L |
16083 | /* In 16bit mode, address is wrapped around at 64k within |
16084 | the same segment. Otherwise, a data16 prefix on a jump | |
16085 | instruction means that the pc is masked to 16 bits after | |
16086 | the displacement is added! */ | |
16087 | mask = 0xffff; | |
16088 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 16089 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 16090 | & ~((bfd_vma) 0xffff)); |
252b5132 | 16091 | } |
5db04b09 L |
16092 | if (address_mode != mode_64bit |
16093 | || (isa64 == amd64 && !(rex & REX_W))) | |
f16cd0d5 | 16094 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
16095 | break; |
16096 | default: | |
16097 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16098 | return; | |
16099 | } | |
42d5f9c6 | 16100 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
16101 | set_op (disp, 0); |
16102 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
16103 | oappend (scratchbuf); |
16104 | } | |
16105 | ||
252b5132 | 16106 | static void |
ed7841b3 | 16107 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 16108 | { |
ed7841b3 | 16109 | if (bytemode == w_mode) |
7967e09e | 16110 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 16111 | else |
7967e09e | 16112 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
16113 | } |
16114 | ||
16115 | static void | |
26ca5450 | 16116 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
16117 | { |
16118 | int seg, offset; | |
16119 | ||
c608c12e | 16120 | if (sizeflag & DFLAG) |
252b5132 | 16121 | { |
c608c12e AM |
16122 | offset = get32 (); |
16123 | seg = get16 (); | |
252b5132 | 16124 | } |
c608c12e AM |
16125 | else |
16126 | { | |
16127 | offset = get16 (); | |
16128 | seg = get16 (); | |
16129 | } | |
7d421014 | 16130 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 16131 | if (intel_syntax) |
3f31e633 | 16132 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
16133 | else |
16134 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 16135 | oappend (scratchbuf); |
252b5132 RH |
16136 | } |
16137 | ||
252b5132 | 16138 | static void |
3f31e633 | 16139 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 16140 | { |
52b15da3 | 16141 | bfd_vma off; |
252b5132 | 16142 | |
3f31e633 JB |
16143 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
16144 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
16145 | append_seg (); |
16146 | ||
cb712a9e | 16147 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
16148 | off = get32 (); |
16149 | else | |
16150 | off = get16 (); | |
16151 | ||
16152 | if (intel_syntax) | |
16153 | { | |
285ca992 | 16154 | if (!active_seg_prefix) |
252b5132 | 16155 | { |
d708bcba | 16156 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
16157 | oappend (":"); |
16158 | } | |
16159 | } | |
52b15da3 JH |
16160 | print_operand_value (scratchbuf, 1, off); |
16161 | oappend (scratchbuf); | |
16162 | } | |
6439fc28 | 16163 | |
52b15da3 | 16164 | static void |
3f31e633 | 16165 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
16166 | { |
16167 | bfd_vma off; | |
16168 | ||
539e75ad L |
16169 | if (address_mode != mode_64bit |
16170 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
16171 | { |
16172 | OP_OFF (bytemode, sizeflag); | |
16173 | return; | |
16174 | } | |
16175 | ||
3f31e633 JB |
16176 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
16177 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
16178 | append_seg (); |
16179 | ||
6608db57 | 16180 | off = get64 (); |
52b15da3 JH |
16181 | |
16182 | if (intel_syntax) | |
16183 | { | |
285ca992 | 16184 | if (!active_seg_prefix) |
52b15da3 | 16185 | { |
d708bcba | 16186 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
16187 | oappend (":"); |
16188 | } | |
16189 | } | |
16190 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
16191 | oappend (scratchbuf); |
16192 | } | |
16193 | ||
16194 | static void | |
26ca5450 | 16195 | ptr_reg (int code, int sizeflag) |
252b5132 | 16196 | { |
2da11e11 | 16197 | const char *s; |
d708bcba | 16198 | |
1d9f512f | 16199 | *obufp++ = open_char; |
20f0a1fc | 16200 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 16201 | if (address_mode == mode_64bit) |
c1a64871 JH |
16202 | { |
16203 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 16204 | s = names32[code - eAX_reg]; |
c1a64871 | 16205 | else |
db6eb5be | 16206 | s = names64[code - eAX_reg]; |
c1a64871 | 16207 | } |
52b15da3 | 16208 | else if (sizeflag & AFLAG) |
252b5132 RH |
16209 | s = names32[code - eAX_reg]; |
16210 | else | |
16211 | s = names16[code - eAX_reg]; | |
16212 | oappend (s); | |
1d9f512f AM |
16213 | *obufp++ = close_char; |
16214 | *obufp = 0; | |
252b5132 RH |
16215 | } |
16216 | ||
16217 | static void | |
26ca5450 | 16218 | OP_ESreg (int code, int sizeflag) |
252b5132 | 16219 | { |
9306ca4a | 16220 | if (intel_syntax) |
52fd6d94 JB |
16221 | { |
16222 | switch (codep[-1]) | |
16223 | { | |
16224 | case 0x6d: /* insw/insl */ | |
16225 | intel_operand_size (z_mode, sizeflag); | |
16226 | break; | |
16227 | case 0xa5: /* movsw/movsl/movsq */ | |
16228 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
16229 | case 0xab: /* stosw/stosl */ | |
16230 | case 0xaf: /* scasw/scasl */ | |
16231 | intel_operand_size (v_mode, sizeflag); | |
16232 | break; | |
16233 | default: | |
16234 | intel_operand_size (b_mode, sizeflag); | |
16235 | } | |
16236 | } | |
9ce09ba2 | 16237 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
16238 | ptr_reg (code, sizeflag); |
16239 | } | |
16240 | ||
16241 | static void | |
26ca5450 | 16242 | OP_DSreg (int code, int sizeflag) |
252b5132 | 16243 | { |
9306ca4a | 16244 | if (intel_syntax) |
52fd6d94 JB |
16245 | { |
16246 | switch (codep[-1]) | |
16247 | { | |
16248 | case 0x6f: /* outsw/outsl */ | |
16249 | intel_operand_size (z_mode, sizeflag); | |
16250 | break; | |
16251 | case 0xa5: /* movsw/movsl/movsq */ | |
16252 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
16253 | case 0xad: /* lodsw/lodsl/lodsq */ | |
16254 | intel_operand_size (v_mode, sizeflag); | |
16255 | break; | |
16256 | default: | |
16257 | intel_operand_size (b_mode, sizeflag); | |
16258 | } | |
16259 | } | |
285ca992 L |
16260 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
16261 | default segment register DS is printed. */ | |
16262 | if (!active_seg_prefix) | |
16263 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 16264 | append_seg (); |
252b5132 RH |
16265 | ptr_reg (code, sizeflag); |
16266 | } | |
16267 | ||
252b5132 | 16268 | static void |
26ca5450 | 16269 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16270 | { |
9b60702d | 16271 | int add; |
161a04f6 | 16272 | if (rex & REX_R) |
c4a530c5 | 16273 | { |
161a04f6 | 16274 | USED_REX (REX_R); |
c4a530c5 JB |
16275 | add = 8; |
16276 | } | |
cb712a9e | 16277 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 16278 | { |
f16cd0d5 | 16279 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
16280 | used_prefixes |= PREFIX_LOCK; |
16281 | add = 8; | |
16282 | } | |
9b60702d L |
16283 | else |
16284 | add = 0; | |
7967e09e | 16285 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 16286 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16287 | } |
16288 | ||
252b5132 | 16289 | static void |
26ca5450 | 16290 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16291 | { |
9b60702d | 16292 | int add; |
161a04f6 L |
16293 | USED_REX (REX_R); |
16294 | if (rex & REX_R) | |
52b15da3 | 16295 | add = 8; |
9b60702d L |
16296 | else |
16297 | add = 0; | |
d708bcba | 16298 | if (intel_syntax) |
7967e09e | 16299 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 16300 | else |
7967e09e | 16301 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
16302 | oappend (scratchbuf); |
16303 | } | |
16304 | ||
252b5132 | 16305 | static void |
26ca5450 | 16306 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16307 | { |
7967e09e | 16308 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 16309 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16310 | } |
16311 | ||
16312 | static void | |
6f74c397 | 16313 | OP_R (int bytemode, int sizeflag) |
252b5132 | 16314 | { |
68f34464 L |
16315 | /* Skip mod/rm byte. */ |
16316 | MODRM_CHECK; | |
16317 | codep++; | |
16318 | OP_E_register (bytemode, sizeflag); | |
252b5132 RH |
16319 | } |
16320 | ||
16321 | static void | |
26ca5450 | 16322 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16323 | { |
b9733481 L |
16324 | int reg = modrm.reg; |
16325 | const char **names; | |
16326 | ||
041bd2e0 JH |
16327 | used_prefixes |= (prefixes & PREFIX_DATA); |
16328 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 16329 | { |
b9733481 | 16330 | names = names_xmm; |
161a04f6 L |
16331 | USED_REX (REX_R); |
16332 | if (rex & REX_R) | |
b9733481 | 16333 | reg += 8; |
20f0a1fc | 16334 | } |
041bd2e0 | 16335 | else |
b9733481 L |
16336 | names = names_mm; |
16337 | oappend (names[reg]); | |
252b5132 RH |
16338 | } |
16339 | ||
c608c12e | 16340 | static void |
c0f3af97 | 16341 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 16342 | { |
b9733481 L |
16343 | int reg = modrm.reg; |
16344 | const char **names; | |
16345 | ||
161a04f6 L |
16346 | USED_REX (REX_R); |
16347 | if (rex & REX_R) | |
b9733481 | 16348 | reg += 8; |
43234a1e L |
16349 | if (vex.evex) |
16350 | { | |
16351 | if (!vex.r) | |
16352 | reg += 16; | |
16353 | } | |
16354 | ||
539f890d L |
16355 | if (need_vex |
16356 | && bytemode != xmm_mode | |
43234a1e L |
16357 | && bytemode != xmmq_mode |
16358 | && bytemode != evex_half_bcst_xmmq_mode | |
16359 | && bytemode != ymm_mode | |
539f890d | 16360 | && bytemode != scalar_mode) |
c0f3af97 L |
16361 | { |
16362 | switch (vex.length) | |
16363 | { | |
16364 | case 128: | |
b9733481 | 16365 | names = names_xmm; |
c0f3af97 L |
16366 | break; |
16367 | case 256: | |
5fc35d96 IT |
16368 | if (vex.w |
16369 | || (bytemode != vex_vsib_q_w_dq_mode | |
16370 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
16371 | names = names_ymm; |
16372 | else | |
16373 | names = names_xmm; | |
c0f3af97 | 16374 | break; |
43234a1e L |
16375 | case 512: |
16376 | names = names_zmm; | |
16377 | break; | |
c0f3af97 L |
16378 | default: |
16379 | abort (); | |
16380 | } | |
16381 | } | |
43234a1e L |
16382 | else if (bytemode == xmmq_mode |
16383 | || bytemode == evex_half_bcst_xmmq_mode) | |
16384 | { | |
16385 | switch (vex.length) | |
16386 | { | |
16387 | case 128: | |
16388 | case 256: | |
16389 | names = names_xmm; | |
16390 | break; | |
16391 | case 512: | |
16392 | names = names_ymm; | |
16393 | break; | |
16394 | default: | |
16395 | abort (); | |
16396 | } | |
16397 | } | |
16398 | else if (bytemode == ymm_mode) | |
16399 | names = names_ymm; | |
c0f3af97 | 16400 | else |
b9733481 L |
16401 | names = names_xmm; |
16402 | oappend (names[reg]); | |
c608c12e AM |
16403 | } |
16404 | ||
252b5132 | 16405 | static void |
26ca5450 | 16406 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 16407 | { |
b9733481 L |
16408 | int reg; |
16409 | const char **names; | |
16410 | ||
7967e09e | 16411 | if (modrm.mod != 3) |
252b5132 | 16412 | { |
b6169b20 L |
16413 | if (intel_syntax |
16414 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
16415 | { |
16416 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16417 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 16418 | } |
252b5132 RH |
16419 | OP_E (bytemode, sizeflag); |
16420 | return; | |
16421 | } | |
16422 | ||
b6169b20 L |
16423 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
16424 | swap_operand (); | |
16425 | ||
6608db57 | 16426 | /* Skip mod/rm byte. */ |
4bba6815 | 16427 | MODRM_CHECK; |
252b5132 | 16428 | codep++; |
041bd2e0 | 16429 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 16430 | reg = modrm.rm; |
041bd2e0 | 16431 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 16432 | { |
b9733481 | 16433 | names = names_xmm; |
161a04f6 L |
16434 | USED_REX (REX_B); |
16435 | if (rex & REX_B) | |
b9733481 | 16436 | reg += 8; |
20f0a1fc | 16437 | } |
041bd2e0 | 16438 | else |
b9733481 L |
16439 | names = names_mm; |
16440 | oappend (names[reg]); | |
252b5132 RH |
16441 | } |
16442 | ||
246c51aa L |
16443 | /* cvt* are the only instructions in sse2 which have |
16444 | both SSE and MMX operands and also have 0x66 prefix | |
16445 | in their opcode. 0x66 was originally used to differentiate | |
16446 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
16447 | cvt* separately using OP_EMC and OP_MXC */ |
16448 | static void | |
16449 | OP_EMC (int bytemode, int sizeflag) | |
16450 | { | |
7967e09e | 16451 | if (modrm.mod != 3) |
4d9567e0 MM |
16452 | { |
16453 | if (intel_syntax && bytemode == v_mode) | |
16454 | { | |
16455 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16456 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 16457 | } |
4d9567e0 MM |
16458 | OP_E (bytemode, sizeflag); |
16459 | return; | |
16460 | } | |
246c51aa | 16461 | |
4d9567e0 MM |
16462 | /* Skip mod/rm byte. */ |
16463 | MODRM_CHECK; | |
16464 | codep++; | |
16465 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 16466 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
16467 | } |
16468 | ||
16469 | static void | |
16470 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16471 | { | |
16472 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 16473 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
16474 | } |
16475 | ||
c608c12e | 16476 | static void |
26ca5450 | 16477 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 16478 | { |
b9733481 L |
16479 | int reg; |
16480 | const char **names; | |
d6f574e0 L |
16481 | |
16482 | /* Skip mod/rm byte. */ | |
16483 | MODRM_CHECK; | |
16484 | codep++; | |
16485 | ||
7967e09e | 16486 | if (modrm.mod != 3) |
c608c12e | 16487 | { |
c1e679ec | 16488 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
16489 | return; |
16490 | } | |
d6f574e0 | 16491 | |
b9733481 | 16492 | reg = modrm.rm; |
161a04f6 L |
16493 | USED_REX (REX_B); |
16494 | if (rex & REX_B) | |
b9733481 | 16495 | reg += 8; |
43234a1e L |
16496 | if (vex.evex) |
16497 | { | |
16498 | USED_REX (REX_X); | |
16499 | if ((rex & REX_X)) | |
16500 | reg += 16; | |
16501 | } | |
c608c12e | 16502 | |
b6169b20 | 16503 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
16504 | && (bytemode == x_swap_mode |
16505 | || bytemode == d_swap_mode | |
7bb15c6f | 16506 | || bytemode == d_scalar_swap_mode |
539f890d L |
16507 | || bytemode == q_swap_mode |
16508 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
16509 | swap_operand (); |
16510 | ||
c0f3af97 L |
16511 | if (need_vex |
16512 | && bytemode != xmm_mode | |
6c30d220 L |
16513 | && bytemode != xmmdw_mode |
16514 | && bytemode != xmmqd_mode | |
16515 | && bytemode != xmm_mb_mode | |
16516 | && bytemode != xmm_mw_mode | |
16517 | && bytemode != xmm_md_mode | |
16518 | && bytemode != xmm_mq_mode | |
43234a1e | 16519 | && bytemode != xmm_mdq_mode |
539f890d | 16520 | && bytemode != xmmq_mode |
43234a1e L |
16521 | && bytemode != evex_half_bcst_xmmq_mode |
16522 | && bytemode != ymm_mode | |
539f890d | 16523 | && bytemode != d_scalar_mode |
7bb15c6f | 16524 | && bytemode != d_scalar_swap_mode |
539f890d | 16525 | && bytemode != q_scalar_mode |
1c480963 L |
16526 | && bytemode != q_scalar_swap_mode |
16527 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
16528 | { |
16529 | switch (vex.length) | |
16530 | { | |
16531 | case 128: | |
b9733481 | 16532 | names = names_xmm; |
c0f3af97 L |
16533 | break; |
16534 | case 256: | |
b9733481 | 16535 | names = names_ymm; |
c0f3af97 | 16536 | break; |
43234a1e L |
16537 | case 512: |
16538 | names = names_zmm; | |
16539 | break; | |
c0f3af97 L |
16540 | default: |
16541 | abort (); | |
16542 | } | |
16543 | } | |
43234a1e L |
16544 | else if (bytemode == xmmq_mode |
16545 | || bytemode == evex_half_bcst_xmmq_mode) | |
16546 | { | |
16547 | switch (vex.length) | |
16548 | { | |
16549 | case 128: | |
16550 | case 256: | |
16551 | names = names_xmm; | |
16552 | break; | |
16553 | case 512: | |
16554 | names = names_ymm; | |
16555 | break; | |
16556 | default: | |
16557 | abort (); | |
16558 | } | |
16559 | } | |
16560 | else if (bytemode == ymm_mode) | |
16561 | names = names_ymm; | |
c0f3af97 | 16562 | else |
b9733481 L |
16563 | names = names_xmm; |
16564 | oappend (names[reg]); | |
c608c12e AM |
16565 | } |
16566 | ||
252b5132 | 16567 | static void |
26ca5450 | 16568 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 16569 | { |
7967e09e | 16570 | if (modrm.mod == 3) |
2da11e11 AM |
16571 | OP_EM (bytemode, sizeflag); |
16572 | else | |
6608db57 | 16573 | BadOp (); |
252b5132 RH |
16574 | } |
16575 | ||
992aaec9 | 16576 | static void |
26ca5450 | 16577 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 16578 | { |
7967e09e | 16579 | if (modrm.mod == 3) |
992aaec9 AM |
16580 | OP_EX (bytemode, sizeflag); |
16581 | else | |
6608db57 | 16582 | BadOp (); |
992aaec9 AM |
16583 | } |
16584 | ||
cc0ec051 AM |
16585 | static void |
16586 | OP_M (int bytemode, int sizeflag) | |
16587 | { | |
7967e09e | 16588 | if (modrm.mod == 3) |
75413a22 L |
16589 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
16590 | BadOp (); | |
cc0ec051 AM |
16591 | else |
16592 | OP_E (bytemode, sizeflag); | |
16593 | } | |
16594 | ||
16595 | static void | |
16596 | OP_0f07 (int bytemode, int sizeflag) | |
16597 | { | |
7967e09e | 16598 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
16599 | BadOp (); |
16600 | else | |
16601 | OP_E (bytemode, sizeflag); | |
16602 | } | |
16603 | ||
46e883c5 | 16604 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 16605 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 16606 | |
cc0ec051 | 16607 | static void |
46e883c5 | 16608 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 16609 | { |
8b38ad71 L |
16610 | if ((prefixes & PREFIX_DATA) != 0 |
16611 | || (rex != 0 | |
16612 | && rex != 0x48 | |
16613 | && address_mode == mode_64bit)) | |
46e883c5 L |
16614 | OP_REG (bytemode, sizeflag); |
16615 | else | |
16616 | strcpy (obuf, "nop"); | |
16617 | } | |
16618 | ||
16619 | static void | |
16620 | NOP_Fixup2 (int bytemode, int sizeflag) | |
16621 | { | |
8b38ad71 L |
16622 | if ((prefixes & PREFIX_DATA) != 0 |
16623 | || (rex != 0 | |
16624 | && rex != 0x48 | |
16625 | && address_mode == mode_64bit)) | |
46e883c5 | 16626 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
16627 | } |
16628 | ||
84037f8c | 16629 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
16630 | /* 00 */ NULL, NULL, NULL, NULL, |
16631 | /* 04 */ NULL, NULL, NULL, NULL, | |
16632 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16633 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
16634 | /* 10 */ NULL, NULL, NULL, NULL, |
16635 | /* 14 */ NULL, NULL, NULL, NULL, | |
16636 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16637 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
16638 | /* 20 */ NULL, NULL, NULL, NULL, |
16639 | /* 24 */ NULL, NULL, NULL, NULL, | |
16640 | /* 28 */ NULL, NULL, NULL, NULL, | |
16641 | /* 2C */ NULL, NULL, NULL, NULL, | |
16642 | /* 30 */ NULL, NULL, NULL, NULL, | |
16643 | /* 34 */ NULL, NULL, NULL, NULL, | |
16644 | /* 38 */ NULL, NULL, NULL, NULL, | |
16645 | /* 3C */ NULL, NULL, NULL, NULL, | |
16646 | /* 40 */ NULL, NULL, NULL, NULL, | |
16647 | /* 44 */ NULL, NULL, NULL, NULL, | |
16648 | /* 48 */ NULL, NULL, NULL, NULL, | |
16649 | /* 4C */ NULL, NULL, NULL, NULL, | |
16650 | /* 50 */ NULL, NULL, NULL, NULL, | |
16651 | /* 54 */ NULL, NULL, NULL, NULL, | |
16652 | /* 58 */ NULL, NULL, NULL, NULL, | |
16653 | /* 5C */ NULL, NULL, NULL, NULL, | |
16654 | /* 60 */ NULL, NULL, NULL, NULL, | |
16655 | /* 64 */ NULL, NULL, NULL, NULL, | |
16656 | /* 68 */ NULL, NULL, NULL, NULL, | |
16657 | /* 6C */ NULL, NULL, NULL, NULL, | |
16658 | /* 70 */ NULL, NULL, NULL, NULL, | |
16659 | /* 74 */ NULL, NULL, NULL, NULL, | |
16660 | /* 78 */ NULL, NULL, NULL, NULL, | |
16661 | /* 7C */ NULL, NULL, NULL, NULL, | |
16662 | /* 80 */ NULL, NULL, NULL, NULL, | |
16663 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
16664 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
16665 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
16666 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
16667 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
16668 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
16669 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
16670 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
16671 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
16672 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
16673 | /* AC */ NULL, NULL, "pfacc", NULL, | |
16674 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 16675 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 16676 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
16677 | /* BC */ NULL, NULL, NULL, "pavgusb", |
16678 | /* C0 */ NULL, NULL, NULL, NULL, | |
16679 | /* C4 */ NULL, NULL, NULL, NULL, | |
16680 | /* C8 */ NULL, NULL, NULL, NULL, | |
16681 | /* CC */ NULL, NULL, NULL, NULL, | |
16682 | /* D0 */ NULL, NULL, NULL, NULL, | |
16683 | /* D4 */ NULL, NULL, NULL, NULL, | |
16684 | /* D8 */ NULL, NULL, NULL, NULL, | |
16685 | /* DC */ NULL, NULL, NULL, NULL, | |
16686 | /* E0 */ NULL, NULL, NULL, NULL, | |
16687 | /* E4 */ NULL, NULL, NULL, NULL, | |
16688 | /* E8 */ NULL, NULL, NULL, NULL, | |
16689 | /* EC */ NULL, NULL, NULL, NULL, | |
16690 | /* F0 */ NULL, NULL, NULL, NULL, | |
16691 | /* F4 */ NULL, NULL, NULL, NULL, | |
16692 | /* F8 */ NULL, NULL, NULL, NULL, | |
16693 | /* FC */ NULL, NULL, NULL, NULL, | |
16694 | }; | |
16695 | ||
16696 | static void | |
26ca5450 | 16697 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
16698 | { |
16699 | const char *mnemonic; | |
16700 | ||
16701 | FETCH_DATA (the_info, codep + 1); | |
16702 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
16703 | place where an 8-bit immediate would normally go. ie. the last | |
16704 | byte of the instruction. */ | |
ea397f5b | 16705 | obufp = mnemonicendp; |
c608c12e | 16706 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 16707 | if (mnemonic) |
2da11e11 | 16708 | oappend (mnemonic); |
252b5132 RH |
16709 | else |
16710 | { | |
16711 | /* Since a variable sized modrm/sib chunk is between the start | |
16712 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
16713 | all the modrm processing first, and don't know until now that | |
16714 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
16715 | op_out[0][0] = '\0'; |
16716 | op_out[1][0] = '\0'; | |
6608db57 | 16717 | BadOp (); |
252b5132 | 16718 | } |
ea397f5b | 16719 | mnemonicendp = obufp; |
252b5132 | 16720 | } |
c608c12e | 16721 | |
ea397f5b L |
16722 | static struct op simd_cmp_op[] = |
16723 | { | |
16724 | { STRING_COMMA_LEN ("eq") }, | |
16725 | { STRING_COMMA_LEN ("lt") }, | |
16726 | { STRING_COMMA_LEN ("le") }, | |
16727 | { STRING_COMMA_LEN ("unord") }, | |
16728 | { STRING_COMMA_LEN ("neq") }, | |
16729 | { STRING_COMMA_LEN ("nlt") }, | |
16730 | { STRING_COMMA_LEN ("nle") }, | |
16731 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
16732 | }; |
16733 | ||
16734 | static void | |
ad19981d | 16735 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
16736 | { |
16737 | unsigned int cmp_type; | |
16738 | ||
16739 | FETCH_DATA (the_info, codep + 1); | |
16740 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 16741 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 16742 | { |
ad19981d | 16743 | char suffix [3]; |
ea397f5b | 16744 | char *p = mnemonicendp - 2; |
ad19981d L |
16745 | suffix[0] = p[0]; |
16746 | suffix[1] = p[1]; | |
16747 | suffix[2] = '\0'; | |
ea397f5b L |
16748 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
16749 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
16750 | } |
16751 | else | |
16752 | { | |
ad19981d L |
16753 | /* We have a reserved extension byte. Output it directly. */ |
16754 | scratchbuf[0] = '$'; | |
16755 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16756 | oappend_maybe_intel (scratchbuf); |
ad19981d | 16757 | scratchbuf[0] = '\0'; |
c608c12e AM |
16758 | } |
16759 | } | |
16760 | ||
9916071f AP |
16761 | static void |
16762 | OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED, | |
16763 | int sizeflag ATTRIBUTE_UNUSED) | |
16764 | { | |
16765 | /* mwaitx %eax,%ecx,%ebx */ | |
16766 | if (!intel_syntax) | |
16767 | { | |
16768 | const char **names = (address_mode == mode_64bit | |
16769 | ? names64 : names32); | |
16770 | strcpy (op_out[0], names[0]); | |
16771 | strcpy (op_out[1], names[1]); | |
16772 | strcpy (op_out[2], names[3]); | |
16773 | two_source_ops = 1; | |
16774 | } | |
16775 | /* Skip mod/rm byte. */ | |
16776 | MODRM_CHECK; | |
16777 | codep++; | |
16778 | } | |
16779 | ||
ca164297 | 16780 | static void |
b844680a L |
16781 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
16782 | int sizeflag ATTRIBUTE_UNUSED) | |
16783 | { | |
16784 | /* mwait %eax,%ecx */ | |
16785 | if (!intel_syntax) | |
16786 | { | |
16787 | const char **names = (address_mode == mode_64bit | |
16788 | ? names64 : names32); | |
16789 | strcpy (op_out[0], names[0]); | |
16790 | strcpy (op_out[1], names[1]); | |
16791 | two_source_ops = 1; | |
16792 | } | |
16793 | /* Skip mod/rm byte. */ | |
16794 | MODRM_CHECK; | |
16795 | codep++; | |
16796 | } | |
16797 | ||
16798 | static void | |
16799 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
16800 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 16801 | { |
b844680a L |
16802 | /* monitor %eax,%ecx,%edx" */ |
16803 | if (!intel_syntax) | |
ca164297 | 16804 | { |
b844680a | 16805 | const char **op1_names; |
cb712a9e L |
16806 | const char **names = (address_mode == mode_64bit |
16807 | ? names64 : names32); | |
1d9f512f | 16808 | |
b844680a L |
16809 | if (!(prefixes & PREFIX_ADDR)) |
16810 | op1_names = (address_mode == mode_16bit | |
16811 | ? names16 : names); | |
ca164297 L |
16812 | else |
16813 | { | |
b844680a | 16814 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 16815 | all_prefixes[last_addr_prefix] = 0; |
b844680a L |
16816 | op1_names = (address_mode != mode_32bit |
16817 | ? names32 : names16); | |
16818 | used_prefixes |= PREFIX_ADDR; | |
ca164297 | 16819 | } |
b844680a L |
16820 | strcpy (op_out[0], op1_names[0]); |
16821 | strcpy (op_out[1], names[1]); | |
16822 | strcpy (op_out[2], names[2]); | |
16823 | two_source_ops = 1; | |
ca164297 | 16824 | } |
b844680a L |
16825 | /* Skip mod/rm byte. */ |
16826 | MODRM_CHECK; | |
16827 | codep++; | |
30123838 JB |
16828 | } |
16829 | ||
6608db57 KH |
16830 | static void |
16831 | BadOp (void) | |
2da11e11 | 16832 | { |
6608db57 KH |
16833 | /* Throw away prefixes and 1st. opcode byte. */ |
16834 | codep = insn_codep + 1; | |
2da11e11 AM |
16835 | oappend ("(bad)"); |
16836 | } | |
4cc91dba | 16837 | |
35c52694 L |
16838 | static void |
16839 | REP_Fixup (int bytemode, int sizeflag) | |
16840 | { | |
16841 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
16842 | lods and stos. */ | |
35c52694 | 16843 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 16844 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
16845 | |
16846 | switch (bytemode) | |
16847 | { | |
16848 | case al_reg: | |
16849 | case eAX_reg: | |
16850 | case indir_dx_reg: | |
16851 | OP_IMREG (bytemode, sizeflag); | |
16852 | break; | |
16853 | case eDI_reg: | |
16854 | OP_ESreg (bytemode, sizeflag); | |
16855 | break; | |
16856 | case eSI_reg: | |
16857 | OP_DSreg (bytemode, sizeflag); | |
16858 | break; | |
16859 | default: | |
16860 | abort (); | |
16861 | break; | |
16862 | } | |
16863 | } | |
f5804c90 | 16864 | |
7e8b059b L |
16865 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
16866 | "bnd". */ | |
16867 | ||
16868 | static void | |
16869 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16870 | { | |
16871 | if (prefixes & PREFIX_REPNZ) | |
16872 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
16873 | } | |
16874 | ||
04ef582a L |
16875 | /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as |
16876 | "notrack". */ | |
16877 | ||
16878 | static void | |
16879 | NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16880 | int sizeflag ATTRIBUTE_UNUSED) | |
16881 | { | |
9fef80d6 | 16882 | if (active_seg_prefix == PREFIX_DS |
04ef582a L |
16883 | && (address_mode != mode_64bit || last_data_prefix < 0)) |
16884 | { | |
4e9ac44a | 16885 | /* NOTRACK prefix is only valid on indirect branch instructions. |
9fef80d6 | 16886 | NB: DATA prefix is unsupported for Intel64. */ |
04ef582a L |
16887 | active_seg_prefix = 0; |
16888 | all_prefixes[last_seg_prefix] = NOTRACK_PREFIX; | |
16889 | } | |
16890 | } | |
16891 | ||
42164a71 L |
16892 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
16893 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
16894 | */ | |
16895 | ||
16896 | static void | |
16897 | HLE_Fixup1 (int bytemode, int sizeflag) | |
16898 | { | |
16899 | if (modrm.mod != 3 | |
16900 | && (prefixes & PREFIX_LOCK) != 0) | |
16901 | { | |
16902 | if (prefixes & PREFIX_REPZ) | |
16903 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16904 | if (prefixes & PREFIX_REPNZ) | |
16905 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16906 | } | |
16907 | ||
16908 | OP_E (bytemode, sizeflag); | |
16909 | } | |
16910 | ||
16911 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
16912 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
16913 | */ | |
16914 | ||
16915 | static void | |
16916 | HLE_Fixup2 (int bytemode, int sizeflag) | |
16917 | { | |
16918 | if (modrm.mod != 3) | |
16919 | { | |
16920 | if (prefixes & PREFIX_REPZ) | |
16921 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16922 | if (prefixes & PREFIX_REPNZ) | |
16923 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16924 | } | |
16925 | ||
16926 | OP_E (bytemode, sizeflag); | |
16927 | } | |
16928 | ||
16929 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
16930 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
16931 | ||
16932 | static void | |
16933 | HLE_Fixup3 (int bytemode, int sizeflag) | |
16934 | { | |
16935 | if (modrm.mod != 3 | |
16936 | && last_repz_prefix > last_repnz_prefix | |
16937 | && (prefixes & PREFIX_REPZ) != 0) | |
16938 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16939 | ||
16940 | OP_E (bytemode, sizeflag); | |
16941 | } | |
16942 | ||
f5804c90 L |
16943 | static void |
16944 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
16945 | { | |
161a04f6 L |
16946 | USED_REX (REX_W); |
16947 | if (rex & REX_W) | |
f5804c90 L |
16948 | { |
16949 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
16950 | char *p = mnemonicendp - 2; |
16951 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 16952 | bytemode = o_mode; |
f5804c90 | 16953 | } |
42164a71 L |
16954 | else if ((prefixes & PREFIX_LOCK) != 0) |
16955 | { | |
16956 | if (prefixes & PREFIX_REPZ) | |
16957 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16958 | if (prefixes & PREFIX_REPNZ) | |
16959 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16960 | } | |
16961 | ||
f5804c90 L |
16962 | OP_M (bytemode, sizeflag); |
16963 | } | |
42903f7f L |
16964 | |
16965 | static void | |
16966 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
16967 | { | |
b9733481 L |
16968 | const char **names; |
16969 | ||
c0f3af97 L |
16970 | if (need_vex) |
16971 | { | |
16972 | switch (vex.length) | |
16973 | { | |
16974 | case 128: | |
b9733481 | 16975 | names = names_xmm; |
c0f3af97 L |
16976 | break; |
16977 | case 256: | |
b9733481 | 16978 | names = names_ymm; |
c0f3af97 L |
16979 | break; |
16980 | default: | |
16981 | abort (); | |
16982 | } | |
16983 | } | |
16984 | else | |
b9733481 L |
16985 | names = names_xmm; |
16986 | oappend (names[reg]); | |
42903f7f | 16987 | } |
381d071f L |
16988 | |
16989 | static void | |
16990 | CRC32_Fixup (int bytemode, int sizeflag) | |
16991 | { | |
16992 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 16993 | char *p = mnemonicendp; |
381d071f L |
16994 | |
16995 | switch (bytemode) | |
16996 | { | |
16997 | case b_mode: | |
20592a94 | 16998 | if (intel_syntax) |
ea397f5b | 16999 | goto skip; |
20592a94 | 17000 | |
381d071f L |
17001 | *p++ = 'b'; |
17002 | break; | |
17003 | case v_mode: | |
20592a94 | 17004 | if (intel_syntax) |
ea397f5b | 17005 | goto skip; |
20592a94 | 17006 | |
381d071f L |
17007 | USED_REX (REX_W); |
17008 | if (rex & REX_W) | |
17009 | *p++ = 'q'; | |
7bb15c6f | 17010 | else |
f16cd0d5 L |
17011 | { |
17012 | if (sizeflag & DFLAG) | |
17013 | *p++ = 'l'; | |
17014 | else | |
17015 | *p++ = 'w'; | |
17016 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17017 | } | |
381d071f L |
17018 | break; |
17019 | default: | |
17020 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
17021 | break; | |
17022 | } | |
ea397f5b | 17023 | mnemonicendp = p; |
381d071f L |
17024 | *p = '\0'; |
17025 | ||
ea397f5b | 17026 | skip: |
381d071f L |
17027 | if (modrm.mod == 3) |
17028 | { | |
17029 | int add; | |
17030 | ||
17031 | /* Skip mod/rm byte. */ | |
17032 | MODRM_CHECK; | |
17033 | codep++; | |
17034 | ||
17035 | USED_REX (REX_B); | |
17036 | add = (rex & REX_B) ? 8 : 0; | |
17037 | if (bytemode == b_mode) | |
17038 | { | |
17039 | USED_REX (0); | |
17040 | if (rex) | |
17041 | oappend (names8rex[modrm.rm + add]); | |
17042 | else | |
17043 | oappend (names8[modrm.rm + add]); | |
17044 | } | |
17045 | else | |
17046 | { | |
17047 | USED_REX (REX_W); | |
17048 | if (rex & REX_W) | |
17049 | oappend (names64[modrm.rm + add]); | |
17050 | else if ((prefixes & PREFIX_DATA)) | |
17051 | oappend (names16[modrm.rm + add]); | |
17052 | else | |
17053 | oappend (names32[modrm.rm + add]); | |
17054 | } | |
17055 | } | |
17056 | else | |
9344ff29 | 17057 | OP_E (bytemode, sizeflag); |
381d071f | 17058 | } |
85f10a01 | 17059 | |
eacc9c89 L |
17060 | static void |
17061 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
17062 | { | |
17063 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
17064 | USED_REX (REX_W); | |
17065 | if (rex & REX_W) | |
17066 | { | |
17067 | char *p = mnemonicendp; | |
17068 | *p++ = '6'; | |
17069 | *p++ = '4'; | |
17070 | *p = '\0'; | |
17071 | mnemonicendp = p; | |
17072 | } | |
17073 | OP_M (bytemode, sizeflag); | |
17074 | } | |
17075 | ||
15c7c1d8 JB |
17076 | static void |
17077 | PCMPESTR_Fixup (int bytemode, int sizeflag) | |
17078 | { | |
17079 | /* Add proper suffix to "{,v}pcmpestr{i,m}". */ | |
17080 | if (!intel_syntax) | |
17081 | { | |
17082 | char *p = mnemonicendp; | |
17083 | ||
17084 | USED_REX (REX_W); | |
17085 | if (rex & REX_W) | |
17086 | *p++ = 'q'; | |
17087 | else if (sizeflag & SUFFIX_ALWAYS) | |
17088 | *p++ = 'l'; | |
17089 | ||
17090 | *p = '\0'; | |
17091 | mnemonicendp = p; | |
17092 | } | |
17093 | ||
17094 | OP_EX (bytemode, sizeflag); | |
17095 | } | |
17096 | ||
c0f3af97 L |
17097 | /* Display the destination register operand for instructions with |
17098 | VEX. */ | |
17099 | ||
17100 | static void | |
17101 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17102 | { | |
539f890d | 17103 | int reg; |
b9733481 L |
17104 | const char **names; |
17105 | ||
c0f3af97 L |
17106 | if (!need_vex) |
17107 | abort (); | |
17108 | ||
17109 | if (!need_vex_reg) | |
17110 | return; | |
17111 | ||
539f890d | 17112 | reg = vex.register_specifier; |
5f847646 JB |
17113 | if (address_mode != mode_64bit) |
17114 | reg &= 7; | |
17115 | else if (vex.evex && !vex.v) | |
17116 | reg += 16; | |
43234a1e | 17117 | |
539f890d L |
17118 | if (bytemode == vex_scalar_mode) |
17119 | { | |
17120 | oappend (names_xmm[reg]); | |
17121 | return; | |
17122 | } | |
17123 | ||
c0f3af97 L |
17124 | switch (vex.length) |
17125 | { | |
17126 | case 128: | |
17127 | switch (bytemode) | |
17128 | { | |
17129 | case vex_mode: | |
17130 | case vex128_mode: | |
6c30d220 | 17131 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 17132 | case vex_vsib_q_w_d_mode: |
cb21baef L |
17133 | names = names_xmm; |
17134 | break; | |
17135 | case dq_mode: | |
390a6789 | 17136 | if (rex & REX_W) |
cb21baef L |
17137 | names = names64; |
17138 | else | |
17139 | names = names32; | |
c0f3af97 | 17140 | break; |
1ba585e8 | 17141 | case mask_bd_mode: |
43234a1e | 17142 | case mask_mode: |
9889cbb1 L |
17143 | if (reg > 0x7) |
17144 | { | |
17145 | oappend ("(bad)"); | |
17146 | return; | |
17147 | } | |
43234a1e L |
17148 | names = names_mask; |
17149 | break; | |
c0f3af97 L |
17150 | default: |
17151 | abort (); | |
17152 | return; | |
17153 | } | |
c0f3af97 L |
17154 | break; |
17155 | case 256: | |
17156 | switch (bytemode) | |
17157 | { | |
17158 | case vex_mode: | |
17159 | case vex256_mode: | |
6c30d220 L |
17160 | names = names_ymm; |
17161 | break; | |
17162 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 17163 | case vex_vsib_q_w_d_mode: |
6c30d220 | 17164 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 17165 | break; |
1ba585e8 | 17166 | case mask_bd_mode: |
43234a1e | 17167 | case mask_mode: |
9889cbb1 L |
17168 | if (reg > 0x7) |
17169 | { | |
17170 | oappend ("(bad)"); | |
17171 | return; | |
17172 | } | |
43234a1e L |
17173 | names = names_mask; |
17174 | break; | |
c0f3af97 | 17175 | default: |
a37a2806 NC |
17176 | /* See PR binutils/20893 for a reproducer. */ |
17177 | oappend ("(bad)"); | |
c0f3af97 L |
17178 | return; |
17179 | } | |
c0f3af97 | 17180 | break; |
43234a1e L |
17181 | case 512: |
17182 | names = names_zmm; | |
17183 | break; | |
c0f3af97 L |
17184 | default: |
17185 | abort (); | |
17186 | break; | |
17187 | } | |
539f890d | 17188 | oappend (names[reg]); |
c0f3af97 L |
17189 | } |
17190 | ||
922d8de8 DR |
17191 | /* Get the VEX immediate byte without moving codep. */ |
17192 | ||
17193 | static unsigned char | |
ccc5981b | 17194 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
17195 | { |
17196 | int bytes_before_imm = 0; | |
17197 | ||
922d8de8 DR |
17198 | if (modrm.mod != 3) |
17199 | { | |
17200 | /* There are SIB/displacement bytes. */ | |
17201 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
6c067bbb | 17202 | { |
922d8de8 | 17203 | /* 32/64 bit address mode */ |
6c067bbb | 17204 | int base = modrm.rm; |
922d8de8 DR |
17205 | |
17206 | /* Check SIB byte. */ | |
6c067bbb RM |
17207 | if (base == 4) |
17208 | { | |
17209 | FETCH_DATA (the_info, codep + 1); | |
17210 | base = *codep & 7; | |
17211 | /* When decoding the third source, don't increase | |
17212 | bytes_before_imm as this has already been incremented | |
17213 | by one in OP_E_memory while decoding the second | |
17214 | source operand. */ | |
17215 | if (opnum == 0) | |
17216 | bytes_before_imm++; | |
17217 | } | |
17218 | ||
17219 | /* Don't increase bytes_before_imm when decoding the third source, | |
17220 | it has already been incremented by OP_E_memory while decoding | |
17221 | the second source operand. */ | |
17222 | if (opnum == 0) | |
17223 | { | |
17224 | switch (modrm.mod) | |
17225 | { | |
17226 | case 0: | |
17227 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
17228 | SIB == 5, there is a 4 byte displacement. */ | |
17229 | if (base != 5) | |
17230 | /* No displacement. */ | |
17231 | break; | |
1a0670f3 | 17232 | /* Fall through. */ |
6c067bbb RM |
17233 | case 2: |
17234 | /* 4 byte displacement. */ | |
17235 | bytes_before_imm += 4; | |
17236 | break; | |
17237 | case 1: | |
17238 | /* 1 byte displacement. */ | |
17239 | bytes_before_imm++; | |
17240 | break; | |
17241 | } | |
17242 | } | |
17243 | } | |
922d8de8 | 17244 | else |
02e647f9 SP |
17245 | { |
17246 | /* 16 bit address mode */ | |
6c067bbb RM |
17247 | /* Don't increase bytes_before_imm when decoding the third source, |
17248 | it has already been incremented by OP_E_memory while decoding | |
17249 | the second source operand. */ | |
17250 | if (opnum == 0) | |
17251 | { | |
02e647f9 SP |
17252 | switch (modrm.mod) |
17253 | { | |
17254 | case 0: | |
17255 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
17256 | if (modrm.rm != 6) | |
17257 | /* No displacement. */ | |
17258 | break; | |
1a0670f3 | 17259 | /* Fall through. */ |
02e647f9 SP |
17260 | case 2: |
17261 | /* 2 byte displacement. */ | |
17262 | bytes_before_imm += 2; | |
17263 | break; | |
17264 | case 1: | |
17265 | /* 1 byte displacement: when decoding the third source, | |
17266 | don't increase bytes_before_imm as this has already | |
17267 | been incremented by one in OP_E_memory while decoding | |
17268 | the second source operand. */ | |
17269 | if (opnum == 0) | |
17270 | bytes_before_imm++; | |
ccc5981b | 17271 | |
02e647f9 SP |
17272 | break; |
17273 | } | |
922d8de8 DR |
17274 | } |
17275 | } | |
17276 | } | |
17277 | ||
17278 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
17279 | return codep [bytes_before_imm]; | |
17280 | } | |
17281 | ||
17282 | static void | |
17283 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
17284 | { | |
b9733481 L |
17285 | const char **names; |
17286 | ||
922d8de8 DR |
17287 | if (reg == -1 && modrm.mod != 3) |
17288 | { | |
17289 | OP_E_memory (bytemode, sizeflag); | |
17290 | return; | |
17291 | } | |
17292 | else | |
17293 | { | |
17294 | if (reg == -1) | |
17295 | { | |
17296 | reg = modrm.rm; | |
17297 | USED_REX (REX_B); | |
17298 | if (rex & REX_B) | |
17299 | reg += 8; | |
17300 | } | |
5f847646 JB |
17301 | if (address_mode != mode_64bit) |
17302 | reg &= 7; | |
922d8de8 DR |
17303 | } |
17304 | ||
17305 | switch (vex.length) | |
17306 | { | |
17307 | case 128: | |
b9733481 | 17308 | names = names_xmm; |
922d8de8 DR |
17309 | break; |
17310 | case 256: | |
b9733481 | 17311 | names = names_ymm; |
922d8de8 DR |
17312 | break; |
17313 | default: | |
17314 | abort (); | |
17315 | } | |
b9733481 | 17316 | oappend (names[reg]); |
922d8de8 DR |
17317 | } |
17318 | ||
a683cc34 SP |
17319 | static void |
17320 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
17321 | { | |
17322 | int reg = -1; | |
17323 | static unsigned char vex_imm8; | |
17324 | ||
17325 | if (vex_w_done == 0) | |
17326 | { | |
17327 | vex_w_done = 1; | |
17328 | ||
17329 | /* Skip mod/rm byte. */ | |
17330 | MODRM_CHECK; | |
17331 | codep++; | |
17332 | ||
17333 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
17334 | ||
17335 | if (vex.w) | |
17336 | reg = vex_imm8 >> 4; | |
17337 | ||
17338 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
17339 | } | |
17340 | else if (vex_w_done == 1) | |
17341 | { | |
17342 | vex_w_done = 2; | |
17343 | ||
17344 | if (!vex.w) | |
17345 | reg = vex_imm8 >> 4; | |
17346 | ||
17347 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
17348 | } | |
17349 | else | |
17350 | { | |
17351 | /* Output the imm8 directly. */ | |
17352 | scratchbuf[0] = '$'; | |
17353 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
9ce09ba2 | 17354 | oappend_maybe_intel (scratchbuf); |
a683cc34 SP |
17355 | scratchbuf[0] = '\0'; |
17356 | codep++; | |
17357 | } | |
17358 | } | |
17359 | ||
5dd85c99 SP |
17360 | static void |
17361 | OP_Vex_2src (int bytemode, int sizeflag) | |
17362 | { | |
17363 | if (modrm.mod == 3) | |
17364 | { | |
b9733481 | 17365 | int reg = modrm.rm; |
5dd85c99 | 17366 | USED_REX (REX_B); |
b9733481 L |
17367 | if (rex & REX_B) |
17368 | reg += 8; | |
17369 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
17370 | } |
17371 | else | |
17372 | { | |
17373 | if (intel_syntax | |
17374 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
17375 | { | |
17376 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
17377 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17378 | } | |
17379 | OP_E (bytemode, sizeflag); | |
17380 | } | |
17381 | } | |
17382 | ||
17383 | static void | |
17384 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
17385 | { | |
17386 | if (modrm.mod == 3) | |
17387 | { | |
17388 | /* Skip mod/rm byte. */ | |
17389 | MODRM_CHECK; | |
17390 | codep++; | |
17391 | } | |
17392 | ||
17393 | if (vex.w) | |
5f847646 JB |
17394 | { |
17395 | unsigned int reg = vex.register_specifier; | |
17396 | ||
17397 | if (address_mode != mode_64bit) | |
17398 | reg &= 7; | |
17399 | oappend (names_xmm[reg]); | |
17400 | } | |
5dd85c99 SP |
17401 | else |
17402 | OP_Vex_2src (bytemode, sizeflag); | |
17403 | } | |
17404 | ||
17405 | static void | |
17406 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
17407 | { | |
17408 | if (vex.w) | |
17409 | OP_Vex_2src (bytemode, sizeflag); | |
17410 | else | |
5f847646 JB |
17411 | { |
17412 | unsigned int reg = vex.register_specifier; | |
17413 | ||
17414 | if (address_mode != mode_64bit) | |
17415 | reg &= 7; | |
17416 | oappend (names_xmm[reg]); | |
17417 | } | |
5dd85c99 SP |
17418 | } |
17419 | ||
922d8de8 DR |
17420 | static void |
17421 | OP_EX_VexW (int bytemode, int sizeflag) | |
17422 | { | |
17423 | int reg = -1; | |
17424 | ||
17425 | if (!vex_w_done) | |
17426 | { | |
41effecb SP |
17427 | /* Skip mod/rm byte. */ |
17428 | MODRM_CHECK; | |
17429 | codep++; | |
17430 | ||
922d8de8 | 17431 | if (vex.w) |
ccc5981b | 17432 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
17433 | } |
17434 | else | |
17435 | { | |
17436 | if (!vex.w) | |
ccc5981b | 17437 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
17438 | } |
17439 | ||
17440 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
922d8de8 | 17441 | |
3a2430e0 JB |
17442 | if (vex_w_done) |
17443 | codep++; | |
17444 | vex_w_done = 1; | |
922d8de8 DR |
17445 | } |
17446 | ||
c0f3af97 L |
17447 | static void |
17448 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17449 | { | |
17450 | int reg; | |
b9733481 L |
17451 | const char **names; |
17452 | ||
c0f3af97 L |
17453 | FETCH_DATA (the_info, codep + 1); |
17454 | reg = *codep++; | |
17455 | ||
17456 | if (bytemode != x_mode) | |
17457 | abort (); | |
17458 | ||
c0f3af97 | 17459 | reg >>= 4; |
5f847646 JB |
17460 | if (address_mode != mode_64bit) |
17461 | reg &= 7; | |
dae39acc | 17462 | |
c0f3af97 L |
17463 | switch (vex.length) |
17464 | { | |
17465 | case 128: | |
b9733481 | 17466 | names = names_xmm; |
c0f3af97 L |
17467 | break; |
17468 | case 256: | |
b9733481 | 17469 | names = names_ymm; |
c0f3af97 L |
17470 | break; |
17471 | default: | |
17472 | abort (); | |
17473 | } | |
b9733481 | 17474 | oappend (names[reg]); |
c0f3af97 L |
17475 | } |
17476 | ||
922d8de8 DR |
17477 | static void |
17478 | OP_XMM_VexW (int bytemode, int sizeflag) | |
17479 | { | |
17480 | /* Turn off the REX.W bit since it is used for swapping operands | |
17481 | now. */ | |
17482 | rex &= ~REX_W; | |
17483 | OP_XMM (bytemode, sizeflag); | |
17484 | } | |
17485 | ||
c0f3af97 L |
17486 | static void |
17487 | OP_EX_Vex (int bytemode, int sizeflag) | |
17488 | { | |
17489 | if (modrm.mod != 3) | |
17490 | { | |
17491 | if (vex.register_specifier != 0) | |
17492 | BadOp (); | |
17493 | need_vex_reg = 0; | |
17494 | } | |
17495 | OP_EX (bytemode, sizeflag); | |
17496 | } | |
17497 | ||
17498 | static void | |
17499 | OP_XMM_Vex (int bytemode, int sizeflag) | |
17500 | { | |
17501 | if (modrm.mod != 3) | |
17502 | { | |
17503 | if (vex.register_specifier != 0) | |
17504 | BadOp (); | |
17505 | need_vex_reg = 0; | |
17506 | } | |
17507 | OP_XMM (bytemode, sizeflag); | |
17508 | } | |
17509 | ||
17510 | static void | |
17511 | VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17512 | { | |
17513 | switch (vex.length) | |
17514 | { | |
17515 | case 128: | |
ea397f5b | 17516 | mnemonicendp = stpcpy (obuf, "vzeroupper"); |
c0f3af97 L |
17517 | break; |
17518 | case 256: | |
ea397f5b | 17519 | mnemonicendp = stpcpy (obuf, "vzeroall"); |
c0f3af97 L |
17520 | break; |
17521 | default: | |
17522 | abort (); | |
17523 | } | |
17524 | } | |
17525 | ||
ea397f5b L |
17526 | static struct op vex_cmp_op[] = |
17527 | { | |
17528 | { STRING_COMMA_LEN ("eq") }, | |
17529 | { STRING_COMMA_LEN ("lt") }, | |
17530 | { STRING_COMMA_LEN ("le") }, | |
17531 | { STRING_COMMA_LEN ("unord") }, | |
17532 | { STRING_COMMA_LEN ("neq") }, | |
17533 | { STRING_COMMA_LEN ("nlt") }, | |
17534 | { STRING_COMMA_LEN ("nle") }, | |
17535 | { STRING_COMMA_LEN ("ord") }, | |
17536 | { STRING_COMMA_LEN ("eq_uq") }, | |
17537 | { STRING_COMMA_LEN ("nge") }, | |
17538 | { STRING_COMMA_LEN ("ngt") }, | |
17539 | { STRING_COMMA_LEN ("false") }, | |
17540 | { STRING_COMMA_LEN ("neq_oq") }, | |
17541 | { STRING_COMMA_LEN ("ge") }, | |
17542 | { STRING_COMMA_LEN ("gt") }, | |
17543 | { STRING_COMMA_LEN ("true") }, | |
17544 | { STRING_COMMA_LEN ("eq_os") }, | |
17545 | { STRING_COMMA_LEN ("lt_oq") }, | |
17546 | { STRING_COMMA_LEN ("le_oq") }, | |
17547 | { STRING_COMMA_LEN ("unord_s") }, | |
17548 | { STRING_COMMA_LEN ("neq_us") }, | |
17549 | { STRING_COMMA_LEN ("nlt_uq") }, | |
17550 | { STRING_COMMA_LEN ("nle_uq") }, | |
17551 | { STRING_COMMA_LEN ("ord_s") }, | |
17552 | { STRING_COMMA_LEN ("eq_us") }, | |
17553 | { STRING_COMMA_LEN ("nge_uq") }, | |
17554 | { STRING_COMMA_LEN ("ngt_uq") }, | |
17555 | { STRING_COMMA_LEN ("false_os") }, | |
17556 | { STRING_COMMA_LEN ("neq_os") }, | |
17557 | { STRING_COMMA_LEN ("ge_oq") }, | |
17558 | { STRING_COMMA_LEN ("gt_oq") }, | |
17559 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
17560 | }; |
17561 | ||
17562 | static void | |
17563 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17564 | { | |
17565 | unsigned int cmp_type; | |
17566 | ||
17567 | FETCH_DATA (the_info, codep + 1); | |
17568 | cmp_type = *codep++ & 0xff; | |
17569 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
17570 | { | |
17571 | char suffix [3]; | |
ea397f5b | 17572 | char *p = mnemonicendp - 2; |
c0f3af97 L |
17573 | suffix[0] = p[0]; |
17574 | suffix[1] = p[1]; | |
17575 | suffix[2] = '\0'; | |
ea397f5b L |
17576 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
17577 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
17578 | } |
17579 | else | |
17580 | { | |
17581 | /* We have a reserved extension byte. Output it directly. */ | |
17582 | scratchbuf[0] = '$'; | |
17583 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 17584 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
17585 | scratchbuf[0] = '\0'; |
17586 | } | |
17587 | } | |
17588 | ||
43234a1e L |
17589 | static void |
17590 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17591 | int sizeflag ATTRIBUTE_UNUSED) | |
17592 | { | |
17593 | unsigned int cmp_type; | |
17594 | ||
17595 | if (!vex.evex) | |
17596 | abort (); | |
17597 | ||
17598 | FETCH_DATA (the_info, codep + 1); | |
17599 | cmp_type = *codep++ & 0xff; | |
17600 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
17601 | If it's the case, print suffix, otherwise - print the immediate. */ | |
17602 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
17603 | && cmp_type != 3 | |
17604 | && cmp_type != 7) | |
17605 | { | |
17606 | char suffix [3]; | |
17607 | char *p = mnemonicendp - 2; | |
17608 | ||
17609 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
17610 | if (p[0] == 'p') | |
17611 | { | |
17612 | p++; | |
17613 | suffix[0] = p[0]; | |
17614 | suffix[1] = '\0'; | |
17615 | } | |
17616 | else | |
17617 | { | |
17618 | suffix[0] = p[0]; | |
17619 | suffix[1] = p[1]; | |
17620 | suffix[2] = '\0'; | |
17621 | } | |
17622 | ||
17623 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
17624 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
17625 | } | |
be92cb14 JB |
17626 | else |
17627 | { | |
17628 | /* We have a reserved extension byte. Output it directly. */ | |
17629 | scratchbuf[0] = '$'; | |
17630 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
17631 | oappend_maybe_intel (scratchbuf); | |
17632 | scratchbuf[0] = '\0'; | |
17633 | } | |
17634 | } | |
17635 | ||
17636 | static const struct op xop_cmp_op[] = | |
17637 | { | |
17638 | { STRING_COMMA_LEN ("lt") }, | |
17639 | { STRING_COMMA_LEN ("le") }, | |
17640 | { STRING_COMMA_LEN ("gt") }, | |
17641 | { STRING_COMMA_LEN ("ge") }, | |
17642 | { STRING_COMMA_LEN ("eq") }, | |
17643 | { STRING_COMMA_LEN ("neq") }, | |
17644 | { STRING_COMMA_LEN ("false") }, | |
17645 | { STRING_COMMA_LEN ("true") } | |
17646 | }; | |
17647 | ||
17648 | static void | |
17649 | VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17650 | int sizeflag ATTRIBUTE_UNUSED) | |
17651 | { | |
17652 | unsigned int cmp_type; | |
17653 | ||
17654 | FETCH_DATA (the_info, codep + 1); | |
17655 | cmp_type = *codep++ & 0xff; | |
17656 | if (cmp_type < ARRAY_SIZE (xop_cmp_op)) | |
17657 | { | |
17658 | char suffix[3]; | |
17659 | char *p = mnemonicendp - 2; | |
17660 | ||
17661 | /* vpcom* can have both one- and two-lettered suffix. */ | |
17662 | if (p[0] == 'm') | |
17663 | { | |
17664 | p++; | |
17665 | suffix[0] = p[0]; | |
17666 | suffix[1] = '\0'; | |
17667 | } | |
17668 | else | |
17669 | { | |
17670 | suffix[0] = p[0]; | |
17671 | suffix[1] = p[1]; | |
17672 | suffix[2] = '\0'; | |
17673 | } | |
17674 | ||
17675 | sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); | |
17676 | mnemonicendp += xop_cmp_op[cmp_type].len; | |
17677 | } | |
43234a1e L |
17678 | else |
17679 | { | |
17680 | /* We have a reserved extension byte. Output it directly. */ | |
17681 | scratchbuf[0] = '$'; | |
17682 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 17683 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
17684 | scratchbuf[0] = '\0'; |
17685 | } | |
17686 | } | |
17687 | ||
ea397f5b L |
17688 | static const struct op pclmul_op[] = |
17689 | { | |
17690 | { STRING_COMMA_LEN ("lql") }, | |
17691 | { STRING_COMMA_LEN ("hql") }, | |
17692 | { STRING_COMMA_LEN ("lqh") }, | |
17693 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
17694 | }; |
17695 | ||
17696 | static void | |
17697 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17698 | int sizeflag ATTRIBUTE_UNUSED) | |
17699 | { | |
17700 | unsigned int pclmul_type; | |
17701 | ||
17702 | FETCH_DATA (the_info, codep + 1); | |
17703 | pclmul_type = *codep++ & 0xff; | |
17704 | switch (pclmul_type) | |
17705 | { | |
17706 | case 0x10: | |
17707 | pclmul_type = 2; | |
17708 | break; | |
17709 | case 0x11: | |
17710 | pclmul_type = 3; | |
17711 | break; | |
17712 | default: | |
17713 | break; | |
7bb15c6f | 17714 | } |
c0f3af97 L |
17715 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
17716 | { | |
17717 | char suffix [4]; | |
ea397f5b | 17718 | char *p = mnemonicendp - 3; |
c0f3af97 L |
17719 | suffix[0] = p[0]; |
17720 | suffix[1] = p[1]; | |
17721 | suffix[2] = p[2]; | |
17722 | suffix[3] = '\0'; | |
ea397f5b L |
17723 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
17724 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
17725 | } |
17726 | else | |
17727 | { | |
17728 | /* We have a reserved extension byte. Output it directly. */ | |
17729 | scratchbuf[0] = '$'; | |
17730 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 17731 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
17732 | scratchbuf[0] = '\0'; |
17733 | } | |
17734 | } | |
17735 | ||
f1f8f695 L |
17736 | static void |
17737 | MOVBE_Fixup (int bytemode, int sizeflag) | |
17738 | { | |
17739 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 17740 | char *p = mnemonicendp; |
f1f8f695 L |
17741 | |
17742 | switch (bytemode) | |
17743 | { | |
17744 | case v_mode: | |
17745 | if (intel_syntax) | |
ea397f5b | 17746 | goto skip; |
f1f8f695 L |
17747 | |
17748 | USED_REX (REX_W); | |
17749 | if (sizeflag & SUFFIX_ALWAYS) | |
17750 | { | |
17751 | if (rex & REX_W) | |
17752 | *p++ = 'q'; | |
f1f8f695 | 17753 | else |
f16cd0d5 L |
17754 | { |
17755 | if (sizeflag & DFLAG) | |
17756 | *p++ = 'l'; | |
17757 | else | |
17758 | *p++ = 'w'; | |
17759 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17760 | } | |
f1f8f695 | 17761 | } |
f1f8f695 L |
17762 | break; |
17763 | default: | |
17764 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
17765 | break; | |
17766 | } | |
ea397f5b | 17767 | mnemonicendp = p; |
f1f8f695 L |
17768 | *p = '\0'; |
17769 | ||
ea397f5b | 17770 | skip: |
f1f8f695 L |
17771 | OP_M (bytemode, sizeflag); |
17772 | } | |
f88c9eb0 SP |
17773 | |
17774 | static void | |
17775 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17776 | { | |
17777 | int reg; | |
17778 | const char **names; | |
17779 | ||
17780 | /* Skip mod/rm byte. */ | |
17781 | MODRM_CHECK; | |
17782 | codep++; | |
17783 | ||
390a6789 | 17784 | if (rex & REX_W) |
f88c9eb0 | 17785 | names = names64; |
f88c9eb0 | 17786 | else |
ce7d077e | 17787 | names = names32; |
f88c9eb0 SP |
17788 | |
17789 | reg = modrm.rm; | |
17790 | USED_REX (REX_B); | |
17791 | if (rex & REX_B) | |
17792 | reg += 8; | |
17793 | ||
17794 | oappend (names[reg]); | |
17795 | } | |
17796 | ||
17797 | static void | |
17798 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17799 | { | |
17800 | const char **names; | |
5f847646 | 17801 | unsigned int reg = vex.register_specifier; |
f88c9eb0 | 17802 | |
390a6789 | 17803 | if (rex & REX_W) |
f88c9eb0 | 17804 | names = names64; |
f88c9eb0 | 17805 | else |
ce7d077e | 17806 | names = names32; |
f88c9eb0 | 17807 | |
5f847646 JB |
17808 | if (address_mode != mode_64bit) |
17809 | reg &= 7; | |
17810 | oappend (names[reg]); | |
f88c9eb0 | 17811 | } |
43234a1e L |
17812 | |
17813 | static void | |
17814 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17815 | { | |
17816 | if (!vex.evex | |
1ba585e8 | 17817 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
17818 | abort (); |
17819 | ||
17820 | USED_REX (REX_R); | |
17821 | if ((rex & REX_R) != 0 || !vex.r) | |
17822 | { | |
17823 | BadOp (); | |
17824 | return; | |
17825 | } | |
17826 | ||
17827 | oappend (names_mask [modrm.reg]); | |
17828 | } | |
17829 | ||
17830 | static void | |
17831 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17832 | { | |
17833 | if (!vex.evex | |
17834 | || (bytemode != evex_rounding_mode | |
17835 | && bytemode != evex_sae_mode)) | |
17836 | abort (); | |
17837 | if (modrm.mod == 3 && vex.b) | |
17838 | switch (bytemode) | |
17839 | { | |
17840 | case evex_rounding_mode: | |
17841 | oappend (names_rounding[vex.ll]); | |
17842 | break; | |
17843 | case evex_sae_mode: | |
17844 | oappend ("{sae}"); | |
17845 | break; | |
17846 | default: | |
17847 | break; | |
17848 | } | |
17849 | } |