Commit | Line | Data |
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0b1cf022 | 1 | /* Declarations for Intel 80386 opcode table |
4b95cf5c | 2 | Copyright (C) 2007-2014 Free Software Foundation, Inc. |
0b1cf022 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
0b1cf022 | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
0b1cf022 | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 | 8 | the Free Software Foundation; either version 3, or (at your option) |
0b1cf022 L |
9 | any later version. |
10 | ||
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
0b1cf022 L |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA | |
19 | 02110-1301, USA. */ | |
20 | ||
21 | #include "opcode/i386.h" | |
40fb9820 L |
22 | #ifdef HAVE_LIMITS_H |
23 | #include <limits.h> | |
24 | #endif | |
25 | ||
26 | #ifndef CHAR_BIT | |
27 | #define CHAR_BIT 8 | |
28 | #endif | |
29 | ||
30 | /* Position of cpu flags bitfiled. */ | |
31 | ||
52a6c1fe L |
32 | enum |
33 | { | |
34 | /* i186 or better required */ | |
35 | Cpu186 = 0, | |
36 | /* i286 or better required */ | |
37 | Cpu286, | |
38 | /* i386 or better required */ | |
39 | Cpu386, | |
40 | /* i486 or better required */ | |
41 | Cpu486, | |
42 | /* i585 or better required */ | |
43 | Cpu586, | |
44 | /* i686 or better required */ | |
45 | Cpu686, | |
b49dfb4a | 46 | /* CLFLUSH Instruction support required */ |
52a6c1fe | 47 | CpuClflush, |
22109423 L |
48 | /* NOP Instruction support required */ |
49 | CpuNop, | |
b49dfb4a | 50 | /* SYSCALL Instructions support required */ |
52a6c1fe L |
51 | CpuSYSCALL, |
52 | /* Floating point support required */ | |
53 | Cpu8087, | |
54 | /* i287 support required */ | |
55 | Cpu287, | |
56 | /* i387 support required */ | |
57 | Cpu387, | |
58 | /* i686 and floating point support required */ | |
59 | Cpu687, | |
60 | /* SSE3 and floating point support required */ | |
61 | CpuFISTTP, | |
62 | /* MMX support required */ | |
63 | CpuMMX, | |
64 | /* SSE support required */ | |
65 | CpuSSE, | |
66 | /* SSE2 support required */ | |
67 | CpuSSE2, | |
68 | /* 3dnow! support required */ | |
69 | Cpu3dnow, | |
70 | /* 3dnow! Extensions support required */ | |
71 | Cpu3dnowA, | |
72 | /* SSE3 support required */ | |
73 | CpuSSE3, | |
74 | /* VIA PadLock required */ | |
75 | CpuPadLock, | |
76 | /* AMD Secure Virtual Machine Ext-s required */ | |
77 | CpuSVME, | |
78 | /* VMX Instructions required */ | |
79 | CpuVMX, | |
80 | /* SMX Instructions required */ | |
81 | CpuSMX, | |
82 | /* SSSE3 support required */ | |
83 | CpuSSSE3, | |
84 | /* SSE4a support required */ | |
85 | CpuSSE4a, | |
86 | /* ABM New Instructions required */ | |
87 | CpuABM, | |
88 | /* SSE4.1 support required */ | |
89 | CpuSSE4_1, | |
90 | /* SSE4.2 support required */ | |
91 | CpuSSE4_2, | |
92 | /* AVX support required */ | |
93 | CpuAVX, | |
6c30d220 L |
94 | /* AVX2 support required */ |
95 | CpuAVX2, | |
43234a1e L |
96 | /* Intel AVX-512 Foundation Instructions support required */ |
97 | CpuAVX512F, | |
98 | /* Intel AVX-512 Conflict Detection Instructions support required */ | |
99 | CpuAVX512CD, | |
100 | /* Intel AVX-512 Exponential and Reciprocal Instructions support | |
101 | required */ | |
102 | CpuAVX512ER, | |
103 | /* Intel AVX-512 Prefetch Instructions support required */ | |
104 | CpuAVX512PF, | |
b28d1bda IT |
105 | /* Intel AVX-512 VL Instructions support required. */ |
106 | CpuAVX512VL, | |
1ba585e8 IT |
107 | /* Intel AVX-512 BW Instructions support required. */ |
108 | CpuAVX512BW, | |
52a6c1fe L |
109 | /* Intel L1OM support required */ |
110 | CpuL1OM, | |
7a9068fe L |
111 | /* Intel K1OM support required */ |
112 | CpuK1OM, | |
b49dfb4a | 113 | /* Xsave/xrstor New Instructions support required */ |
52a6c1fe | 114 | CpuXsave, |
b49dfb4a | 115 | /* Xsaveopt New Instructions support required */ |
c7b8aa3a | 116 | CpuXsaveopt, |
52a6c1fe L |
117 | /* AES support required */ |
118 | CpuAES, | |
119 | /* PCLMUL support required */ | |
120 | CpuPCLMUL, | |
121 | /* FMA support required */ | |
122 | CpuFMA, | |
123 | /* FMA4 support required */ | |
124 | CpuFMA4, | |
5dd85c99 SP |
125 | /* XOP support required */ |
126 | CpuXOP, | |
f88c9eb0 SP |
127 | /* LWP support required */ |
128 | CpuLWP, | |
f12dc422 L |
129 | /* BMI support required */ |
130 | CpuBMI, | |
2a2a0f38 QN |
131 | /* TBM support required */ |
132 | CpuTBM, | |
b49dfb4a | 133 | /* MOVBE Instruction support required */ |
52a6c1fe | 134 | CpuMovbe, |
60aa667e L |
135 | /* CMPXCHG16B instruction support required. */ |
136 | CpuCX16, | |
52a6c1fe L |
137 | /* EPT Instructions required */ |
138 | CpuEPT, | |
b49dfb4a | 139 | /* RDTSCP Instruction support required */ |
52a6c1fe | 140 | CpuRdtscp, |
77321f53 | 141 | /* FSGSBASE Instructions required */ |
c7b8aa3a L |
142 | CpuFSGSBase, |
143 | /* RDRND Instructions required */ | |
144 | CpuRdRnd, | |
145 | /* F16C Instructions required */ | |
146 | CpuF16C, | |
6c30d220 L |
147 | /* Intel BMI2 support required */ |
148 | CpuBMI2, | |
149 | /* LZCNT support required */ | |
150 | CpuLZCNT, | |
42164a71 L |
151 | /* HLE support required */ |
152 | CpuHLE, | |
153 | /* RTM support required */ | |
154 | CpuRTM, | |
6c30d220 L |
155 | /* INVPCID Instructions required */ |
156 | CpuINVPCID, | |
8729a6f6 L |
157 | /* VMFUNC Instruction required */ |
158 | CpuVMFUNC, | |
7e8b059b L |
159 | /* Intel MPX Instructions required */ |
160 | CpuMPX, | |
52a6c1fe L |
161 | /* 64bit support available, used by -march= in assembler. */ |
162 | CpuLM, | |
e2e1fcde L |
163 | /* RDRSEED instruction required. */ |
164 | CpuRDSEED, | |
165 | /* Multi-presisionn add-carry instructions are required. */ | |
166 | CpuADX, | |
7b458c12 | 167 | /* Supports prefetchw and prefetch instructions. */ |
e2e1fcde | 168 | CpuPRFCHW, |
5c111e37 L |
169 | /* SMAP instructions required. */ |
170 | CpuSMAP, | |
a0046408 L |
171 | /* SHA instructions required. */ |
172 | CpuSHA, | |
43234a1e L |
173 | /* VREX support required */ |
174 | CpuVREX, | |
963f3586 IT |
175 | /* CLFLUSHOPT instruction required */ |
176 | CpuClflushOpt, | |
177 | /* XSAVES/XRSTORS instruction required */ | |
178 | CpuXSAVES, | |
179 | /* XSAVEC instruction required */ | |
180 | CpuXSAVEC, | |
dcf893b5 IT |
181 | /* PREFETCHWT1 instruction required */ |
182 | CpuPREFETCHWT1, | |
2cf200a4 IT |
183 | /* SE1 instruction required */ |
184 | CpuSE1, | |
52a6c1fe L |
185 | /* 64bit support required */ |
186 | Cpu64, | |
187 | /* Not supported in the 64bit mode */ | |
188 | CpuNo64, | |
189 | /* The last bitfield in i386_cpu_flags. */ | |
190 | CpuMax = CpuNo64 | |
191 | }; | |
40fb9820 L |
192 | |
193 | #define CpuNumOfUints \ | |
194 | (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1) | |
195 | #define CpuNumOfBits \ | |
196 | (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT) | |
197 | ||
198 | /* If you get a compiler error for zero width of the unused field, | |
199 | comment it out. */ | |
a0046408 | 200 | #define CpuUnused (CpuMax + 1) |
40fb9820 L |
201 | |
202 | /* We can check if an instruction is available with array instead | |
203 | of bitfield. */ | |
204 | typedef union i386_cpu_flags | |
205 | { | |
206 | struct | |
207 | { | |
208 | unsigned int cpui186:1; | |
209 | unsigned int cpui286:1; | |
210 | unsigned int cpui386:1; | |
211 | unsigned int cpui486:1; | |
212 | unsigned int cpui586:1; | |
213 | unsigned int cpui686:1; | |
bd5295b2 | 214 | unsigned int cpuclflush:1; |
22109423 | 215 | unsigned int cpunop:1; |
bd5295b2 | 216 | unsigned int cpusyscall:1; |
309d3373 JB |
217 | unsigned int cpu8087:1; |
218 | unsigned int cpu287:1; | |
219 | unsigned int cpu387:1; | |
220 | unsigned int cpu687:1; | |
221 | unsigned int cpufisttp:1; | |
40fb9820 | 222 | unsigned int cpummx:1; |
40fb9820 L |
223 | unsigned int cpusse:1; |
224 | unsigned int cpusse2:1; | |
225 | unsigned int cpua3dnow:1; | |
226 | unsigned int cpua3dnowa:1; | |
227 | unsigned int cpusse3:1; | |
228 | unsigned int cpupadlock:1; | |
229 | unsigned int cpusvme:1; | |
230 | unsigned int cpuvmx:1; | |
47dd174c | 231 | unsigned int cpusmx:1; |
40fb9820 L |
232 | unsigned int cpussse3:1; |
233 | unsigned int cpusse4a:1; | |
234 | unsigned int cpuabm:1; | |
235 | unsigned int cpusse4_1:1; | |
236 | unsigned int cpusse4_2:1; | |
c0f3af97 | 237 | unsigned int cpuavx:1; |
6c30d220 | 238 | unsigned int cpuavx2:1; |
43234a1e L |
239 | unsigned int cpuavx512f:1; |
240 | unsigned int cpuavx512cd:1; | |
241 | unsigned int cpuavx512er:1; | |
242 | unsigned int cpuavx512pf:1; | |
b28d1bda | 243 | unsigned int cpuavx512vl:1; |
1ba585e8 | 244 | unsigned int cpuavx512bw:1; |
8a9036a4 | 245 | unsigned int cpul1om:1; |
7a9068fe | 246 | unsigned int cpuk1om:1; |
475a2301 | 247 | unsigned int cpuxsave:1; |
c7b8aa3a | 248 | unsigned int cpuxsaveopt:1; |
c0f3af97 | 249 | unsigned int cpuaes:1; |
594ab6a3 | 250 | unsigned int cpupclmul:1; |
c0f3af97 | 251 | unsigned int cpufma:1; |
922d8de8 | 252 | unsigned int cpufma4:1; |
5dd85c99 | 253 | unsigned int cpuxop:1; |
f88c9eb0 | 254 | unsigned int cpulwp:1; |
f12dc422 | 255 | unsigned int cpubmi:1; |
2a2a0f38 | 256 | unsigned int cputbm:1; |
f1f8f695 | 257 | unsigned int cpumovbe:1; |
60aa667e | 258 | unsigned int cpucx16:1; |
f1f8f695 | 259 | unsigned int cpuept:1; |
1b7f3fb0 | 260 | unsigned int cpurdtscp:1; |
c7b8aa3a L |
261 | unsigned int cpufsgsbase:1; |
262 | unsigned int cpurdrnd:1; | |
263 | unsigned int cpuf16c:1; | |
6c30d220 L |
264 | unsigned int cpubmi2:1; |
265 | unsigned int cpulzcnt:1; | |
42164a71 L |
266 | unsigned int cpuhle:1; |
267 | unsigned int cpurtm:1; | |
6c30d220 | 268 | unsigned int cpuinvpcid:1; |
8729a6f6 | 269 | unsigned int cpuvmfunc:1; |
7e8b059b | 270 | unsigned int cpumpx:1; |
40fb9820 | 271 | unsigned int cpulm:1; |
e2e1fcde L |
272 | unsigned int cpurdseed:1; |
273 | unsigned int cpuadx:1; | |
274 | unsigned int cpuprfchw:1; | |
5c111e37 | 275 | unsigned int cpusmap:1; |
a0046408 | 276 | unsigned int cpusha:1; |
43234a1e | 277 | unsigned int cpuvrex:1; |
963f3586 IT |
278 | unsigned int cpuclflushopt:1; |
279 | unsigned int cpuxsaves:1; | |
280 | unsigned int cpuxsavec:1; | |
dcf893b5 | 281 | unsigned int cpuprefetchwt1:1; |
2cf200a4 | 282 | unsigned int cpuse1:1; |
40fb9820 L |
283 | unsigned int cpu64:1; |
284 | unsigned int cpuno64:1; | |
285 | #ifdef CpuUnused | |
286 | unsigned int unused:(CpuNumOfBits - CpuUnused); | |
287 | #endif | |
288 | } bitfield; | |
289 | unsigned int array[CpuNumOfUints]; | |
290 | } i386_cpu_flags; | |
291 | ||
292 | /* Position of opcode_modifier bits. */ | |
293 | ||
52a6c1fe L |
294 | enum |
295 | { | |
296 | /* has direction bit. */ | |
297 | D = 0, | |
298 | /* set if operands can be words or dwords encoded the canonical way */ | |
299 | W, | |
300 | /* Skip the current insn and use the next insn in i386-opc.tbl to swap | |
301 | operand in encoding. */ | |
302 | S, | |
303 | /* insn has a modrm byte. */ | |
304 | Modrm, | |
305 | /* register is in low 3 bits of opcode */ | |
306 | ShortForm, | |
307 | /* special case for jump insns. */ | |
308 | Jump, | |
309 | /* call and jump */ | |
310 | JumpDword, | |
311 | /* loop and jecxz */ | |
312 | JumpByte, | |
313 | /* special case for intersegment leaps/calls */ | |
314 | JumpInterSegment, | |
315 | /* FP insn memory format bit, sized by 0x4 */ | |
316 | FloatMF, | |
317 | /* src/dest swap for floats. */ | |
318 | FloatR, | |
319 | /* has float insn direction bit. */ | |
320 | FloatD, | |
321 | /* needs size prefix if in 32-bit mode */ | |
322 | Size16, | |
323 | /* needs size prefix if in 16-bit mode */ | |
324 | Size32, | |
325 | /* needs size prefix if in 64-bit mode */ | |
326 | Size64, | |
56ffb741 L |
327 | /* check register size. */ |
328 | CheckRegSize, | |
52a6c1fe L |
329 | /* instruction ignores operand size prefix and in Intel mode ignores |
330 | mnemonic size suffix check. */ | |
331 | IgnoreSize, | |
332 | /* default insn size depends on mode */ | |
333 | DefaultSize, | |
334 | /* b suffix on instruction illegal */ | |
335 | No_bSuf, | |
336 | /* w suffix on instruction illegal */ | |
337 | No_wSuf, | |
338 | /* l suffix on instruction illegal */ | |
339 | No_lSuf, | |
340 | /* s suffix on instruction illegal */ | |
341 | No_sSuf, | |
342 | /* q suffix on instruction illegal */ | |
343 | No_qSuf, | |
344 | /* long double suffix on instruction illegal */ | |
345 | No_ldSuf, | |
346 | /* instruction needs FWAIT */ | |
347 | FWait, | |
348 | /* quick test for string instructions */ | |
349 | IsString, | |
7e8b059b L |
350 | /* quick test if branch instruction is MPX supported */ |
351 | BNDPrefixOk, | |
c32fa91d L |
352 | /* quick test for lockable instructions */ |
353 | IsLockable, | |
52a6c1fe L |
354 | /* fake an extra reg operand for clr, imul and special register |
355 | processing for some instructions. */ | |
356 | RegKludge, | |
357 | /* The first operand must be xmm0 */ | |
358 | FirstXmm0, | |
359 | /* An implicit xmm0 as the first operand */ | |
360 | Implicit1stXmm0, | |
42164a71 L |
361 | /* The HLE prefix is OK: |
362 | 1. With a LOCK prefix. | |
363 | 2. With or without a LOCK prefix. | |
364 | 3. With a RELEASE (0xf3) prefix. | |
365 | */ | |
82c2def5 L |
366 | #define HLEPrefixNone 0 |
367 | #define HLEPrefixLock 1 | |
368 | #define HLEPrefixAny 2 | |
369 | #define HLEPrefixRelease 3 | |
42164a71 | 370 | HLEPrefixOk, |
29c048b6 RM |
371 | /* An instruction on which a "rep" prefix is acceptable. */ |
372 | RepPrefixOk, | |
52a6c1fe L |
373 | /* Convert to DWORD */ |
374 | ToDword, | |
375 | /* Convert to QWORD */ | |
376 | ToQword, | |
377 | /* Address prefix changes operand 0 */ | |
378 | AddrPrefixOp0, | |
379 | /* opcode is a prefix */ | |
380 | IsPrefix, | |
381 | /* instruction has extension in 8 bit imm */ | |
382 | ImmExt, | |
383 | /* instruction don't need Rex64 prefix. */ | |
384 | NoRex64, | |
385 | /* instruction require Rex64 prefix. */ | |
386 | Rex64, | |
387 | /* deprecated fp insn, gets a warning */ | |
388 | Ugh, | |
389 | /* insn has VEX prefix: | |
2bf05e57 L |
390 | 1: 128bit VEX prefix. |
391 | 2: 256bit VEX prefix. | |
712366da | 392 | 3: Scalar VEX prefix. |
52a6c1fe | 393 | */ |
712366da L |
394 | #define VEX128 1 |
395 | #define VEX256 2 | |
396 | #define VEXScalar 3 | |
52a6c1fe | 397 | Vex, |
2426c15f L |
398 | /* How to encode VEX.vvvv: |
399 | 0: VEX.vvvv must be 1111b. | |
a2a7d12c | 400 | 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where |
2426c15f | 401 | the content of source registers will be preserved. |
29c048b6 | 402 | VEX.DDS. The second register operand is encoded in VEX.vvvv |
2426c15f L |
403 | where the content of first source register will be overwritten |
404 | by the result. | |
6c30d220 L |
405 | VEX.NDD2. The second destination register operand is encoded in |
406 | VEX.vvvv for instructions with 2 destination register operands. | |
407 | For assembler, there are no difference between VEX.NDS, VEX.DDS | |
408 | and VEX.NDD2. | |
409 | 2. VEX.NDD. Register destination is encoded in VEX.vvvv for | |
410 | instructions with 1 destination register operand. | |
2426c15f L |
411 | 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one |
412 | of the operands can access a memory location. | |
413 | */ | |
414 | #define VEXXDS 1 | |
415 | #define VEXNDD 2 | |
416 | #define VEXLWP 3 | |
417 | VexVVVV, | |
1ef99a7b L |
418 | /* How the VEX.W bit is used: |
419 | 0: Set by the REX.W bit. | |
420 | 1: VEX.W0. Should always be 0. | |
421 | 2: VEX.W1. Should always be 1. | |
422 | */ | |
423 | #define VEXW0 1 | |
424 | #define VEXW1 2 | |
425 | VexW, | |
7f399153 L |
426 | /* VEX opcode prefix: |
427 | 0: VEX 0x0F opcode prefix. | |
428 | 1: VEX 0x0F38 opcode prefix. | |
429 | 2: VEX 0x0F3A opcode prefix | |
430 | 3: XOP 0x08 opcode prefix. | |
431 | 4: XOP 0x09 opcode prefix | |
432 | 5: XOP 0x0A opcode prefix. | |
433 | */ | |
434 | #define VEX0F 0 | |
435 | #define VEX0F38 1 | |
436 | #define VEX0F3A 2 | |
437 | #define XOP08 3 | |
438 | #define XOP09 4 | |
439 | #define XOP0A 5 | |
440 | VexOpcode, | |
8cd7925b | 441 | /* number of VEX source operands: |
8c43a48b L |
442 | 0: <= 2 source operands. |
443 | 1: 2 XOP source operands. | |
8cd7925b L |
444 | 2: 3 source operands. |
445 | */ | |
8c43a48b | 446 | #define XOP2SOURCES 1 |
8cd7925b L |
447 | #define VEX3SOURCES 2 |
448 | VexSources, | |
52a6c1fe L |
449 | /* instruction has VEX 8 bit imm */ |
450 | VexImmExt, | |
6c30d220 L |
451 | /* Instruction with vector SIB byte: |
452 | 1: 128bit vector register. | |
453 | 2: 256bit vector register. | |
43234a1e | 454 | 3: 512bit vector register. |
6c30d220 L |
455 | */ |
456 | #define VecSIB128 1 | |
457 | #define VecSIB256 2 | |
43234a1e | 458 | #define VecSIB512 3 |
6c30d220 | 459 | VecSIB, |
52a6c1fe L |
460 | /* SSE to AVX support required */ |
461 | SSE2AVX, | |
462 | /* No AVX equivalent */ | |
463 | NoAVX, | |
43234a1e L |
464 | |
465 | /* insn has EVEX prefix: | |
466 | 1: 512bit EVEX prefix. | |
467 | 2: 128bit EVEX prefix. | |
468 | 3: 256bit EVEX prefix. | |
469 | 4: Length-ignored (LIG) EVEX prefix. | |
470 | */ | |
471 | #define EVEX512 1 | |
472 | #define EVEX128 2 | |
473 | #define EVEX256 3 | |
474 | #define EVEXLIG 4 | |
475 | EVex, | |
476 | ||
477 | /* AVX512 masking support: | |
478 | 1: Zeroing-masking. | |
479 | 2: Merging-masking. | |
480 | 3: Both zeroing and merging masking. | |
481 | */ | |
482 | #define ZEROING_MASKING 1 | |
483 | #define MERGING_MASKING 2 | |
484 | #define BOTH_MASKING 3 | |
485 | Masking, | |
486 | ||
487 | /* Input element size of vector insn: | |
488 | 0: 32bit. | |
489 | 1: 64bit. | |
490 | */ | |
491 | VecESize, | |
492 | ||
493 | /* Broadcast factor. | |
494 | 0: No broadcast. | |
495 | 1: 1to16 broadcast. | |
496 | 2: 1to8 broadcast. | |
497 | */ | |
498 | #define NO_BROADCAST 0 | |
499 | #define BROADCAST_1TO16 1 | |
500 | #define BROADCAST_1TO8 2 | |
b28d1bda IT |
501 | #define BROADCAST_1TO4 3 |
502 | #define BROADCAST_1TO2 4 | |
43234a1e L |
503 | Broadcast, |
504 | ||
505 | /* Static rounding control is supported. */ | |
506 | StaticRounding, | |
507 | ||
508 | /* Supress All Exceptions is supported. */ | |
509 | SAE, | |
510 | ||
511 | /* Copressed Disp8*N attribute. */ | |
512 | Disp8MemShift, | |
513 | ||
514 | /* Default mask isn't allowed. */ | |
515 | NoDefMask, | |
516 | ||
52a6c1fe L |
517 | /* Compatible with old (<= 2.8.1) versions of gcc */ |
518 | OldGcc, | |
519 | /* AT&T mnemonic. */ | |
520 | ATTMnemonic, | |
521 | /* AT&T syntax. */ | |
522 | ATTSyntax, | |
523 | /* Intel syntax. */ | |
524 | IntelSyntax, | |
525 | /* The last bitfield in i386_opcode_modifier. */ | |
526 | Opcode_Modifier_Max | |
527 | }; | |
40fb9820 L |
528 | |
529 | typedef struct i386_opcode_modifier | |
530 | { | |
531 | unsigned int d:1; | |
532 | unsigned int w:1; | |
b6169b20 | 533 | unsigned int s:1; |
40fb9820 L |
534 | unsigned int modrm:1; |
535 | unsigned int shortform:1; | |
536 | unsigned int jump:1; | |
537 | unsigned int jumpdword:1; | |
538 | unsigned int jumpbyte:1; | |
539 | unsigned int jumpintersegment:1; | |
540 | unsigned int floatmf:1; | |
541 | unsigned int floatr:1; | |
542 | unsigned int floatd:1; | |
543 | unsigned int size16:1; | |
544 | unsigned int size32:1; | |
545 | unsigned int size64:1; | |
56ffb741 | 546 | unsigned int checkregsize:1; |
40fb9820 L |
547 | unsigned int ignoresize:1; |
548 | unsigned int defaultsize:1; | |
549 | unsigned int no_bsuf:1; | |
550 | unsigned int no_wsuf:1; | |
551 | unsigned int no_lsuf:1; | |
552 | unsigned int no_ssuf:1; | |
553 | unsigned int no_qsuf:1; | |
7ce189b3 | 554 | unsigned int no_ldsuf:1; |
40fb9820 L |
555 | unsigned int fwait:1; |
556 | unsigned int isstring:1; | |
7e8b059b | 557 | unsigned int bndprefixok:1; |
c32fa91d | 558 | unsigned int islockable:1; |
40fb9820 | 559 | unsigned int regkludge:1; |
e2ec9d29 | 560 | unsigned int firstxmm0:1; |
c0f3af97 | 561 | unsigned int implicit1stxmm0:1; |
42164a71 | 562 | unsigned int hleprefixok:2; |
29c048b6 | 563 | unsigned int repprefixok:1; |
ca61edf2 L |
564 | unsigned int todword:1; |
565 | unsigned int toqword:1; | |
566 | unsigned int addrprefixop0:1; | |
40fb9820 L |
567 | unsigned int isprefix:1; |
568 | unsigned int immext:1; | |
569 | unsigned int norex64:1; | |
570 | unsigned int rex64:1; | |
571 | unsigned int ugh:1; | |
2bf05e57 | 572 | unsigned int vex:2; |
2426c15f | 573 | unsigned int vexvvvv:2; |
1ef99a7b | 574 | unsigned int vexw:2; |
7f399153 | 575 | unsigned int vexopcode:3; |
8cd7925b | 576 | unsigned int vexsources:2; |
c0f3af97 | 577 | unsigned int veximmext:1; |
6c30d220 | 578 | unsigned int vecsib:2; |
c0f3af97 | 579 | unsigned int sse2avx:1; |
81f8a913 | 580 | unsigned int noavx:1; |
43234a1e L |
581 | unsigned int evex:3; |
582 | unsigned int masking:2; | |
583 | unsigned int vecesize:1; | |
584 | unsigned int broadcast:3; | |
585 | unsigned int staticrounding:1; | |
586 | unsigned int sae:1; | |
587 | unsigned int disp8memshift:3; | |
588 | unsigned int nodefmask:1; | |
1efbbeb4 L |
589 | unsigned int oldgcc:1; |
590 | unsigned int attmnemonic:1; | |
e1d4d893 | 591 | unsigned int attsyntax:1; |
5c07affc | 592 | unsigned int intelsyntax:1; |
40fb9820 L |
593 | } i386_opcode_modifier; |
594 | ||
595 | /* Position of operand_type bits. */ | |
596 | ||
52a6c1fe L |
597 | enum |
598 | { | |
599 | /* 8bit register */ | |
600 | Reg8 = 0, | |
601 | /* 16bit register */ | |
602 | Reg16, | |
603 | /* 32bit register */ | |
604 | Reg32, | |
605 | /* 64bit register */ | |
606 | Reg64, | |
607 | /* Floating pointer stack register */ | |
608 | FloatReg, | |
609 | /* MMX register */ | |
610 | RegMMX, | |
611 | /* SSE register */ | |
612 | RegXMM, | |
613 | /* AVX registers */ | |
614 | RegYMM, | |
43234a1e L |
615 | /* AVX512 registers */ |
616 | RegZMM, | |
617 | /* Vector Mask registers */ | |
618 | RegMask, | |
52a6c1fe L |
619 | /* Control register */ |
620 | Control, | |
621 | /* Debug register */ | |
622 | Debug, | |
623 | /* Test register */ | |
624 | Test, | |
625 | /* 2 bit segment register */ | |
626 | SReg2, | |
627 | /* 3 bit segment register */ | |
628 | SReg3, | |
629 | /* 1 bit immediate */ | |
630 | Imm1, | |
631 | /* 8 bit immediate */ | |
632 | Imm8, | |
633 | /* 8 bit immediate sign extended */ | |
634 | Imm8S, | |
635 | /* 16 bit immediate */ | |
636 | Imm16, | |
637 | /* 32 bit immediate */ | |
638 | Imm32, | |
639 | /* 32 bit immediate sign extended */ | |
640 | Imm32S, | |
641 | /* 64 bit immediate */ | |
642 | Imm64, | |
643 | /* 8bit/16bit/32bit displacements are used in different ways, | |
644 | depending on the instruction. For jumps, they specify the | |
645 | size of the PC relative displacement, for instructions with | |
646 | memory operand, they specify the size of the offset relative | |
647 | to the base register, and for instructions with memory offset | |
648 | such as `mov 1234,%al' they specify the size of the offset | |
649 | relative to the segment base. */ | |
650 | /* 8 bit displacement */ | |
651 | Disp8, | |
652 | /* 16 bit displacement */ | |
653 | Disp16, | |
654 | /* 32 bit displacement */ | |
655 | Disp32, | |
656 | /* 32 bit signed displacement */ | |
657 | Disp32S, | |
658 | /* 64 bit displacement */ | |
659 | Disp64, | |
660 | /* Accumulator %al/%ax/%eax/%rax */ | |
661 | Acc, | |
662 | /* Floating pointer top stack register %st(0) */ | |
663 | FloatAcc, | |
664 | /* Register which can be used for base or index in memory operand. */ | |
665 | BaseIndex, | |
666 | /* Register to hold in/out port addr = dx */ | |
667 | InOutPortReg, | |
668 | /* Register to hold shift count = cl */ | |
669 | ShiftCount, | |
670 | /* Absolute address for jump. */ | |
671 | JumpAbsolute, | |
672 | /* String insn operand with fixed es segment */ | |
673 | EsSeg, | |
674 | /* RegMem is for instructions with a modrm byte where the register | |
675 | destination operand should be encoded in the mod and regmem fields. | |
676 | Normally, it will be encoded in the reg field. We add a RegMem | |
677 | flag to the destination register operand to indicate that it should | |
678 | be encoded in the regmem field. */ | |
679 | RegMem, | |
680 | /* Memory. */ | |
681 | Mem, | |
682 | /* BYTE memory. */ | |
683 | Byte, | |
684 | /* WORD memory. 2 byte */ | |
685 | Word, | |
686 | /* DWORD memory. 4 byte */ | |
687 | Dword, | |
688 | /* FWORD memory. 6 byte */ | |
689 | Fword, | |
690 | /* QWORD memory. 8 byte */ | |
691 | Qword, | |
692 | /* TBYTE memory. 10 byte */ | |
693 | Tbyte, | |
694 | /* XMMWORD memory. */ | |
695 | Xmmword, | |
696 | /* YMMWORD memory. */ | |
697 | Ymmword, | |
43234a1e L |
698 | /* ZMMWORD memory. */ |
699 | Zmmword, | |
52a6c1fe L |
700 | /* Unspecified memory size. */ |
701 | Unspecified, | |
702 | /* Any memory size. */ | |
703 | Anysize, | |
40fb9820 | 704 | |
a683cc34 SP |
705 | /* Vector 4 bit immediate. */ |
706 | Vec_Imm4, | |
707 | ||
7e8b059b L |
708 | /* Bound register. */ |
709 | RegBND, | |
710 | ||
43234a1e L |
711 | /* Vector 8bit displacement */ |
712 | Vec_Disp8, | |
713 | ||
52a6c1fe L |
714 | /* The last bitfield in i386_operand_type. */ |
715 | OTMax | |
716 | }; | |
40fb9820 L |
717 | |
718 | #define OTNumOfUints \ | |
719 | (OTMax / sizeof (unsigned int) / CHAR_BIT + 1) | |
720 | #define OTNumOfBits \ | |
721 | (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT) | |
722 | ||
723 | /* If you get a compiler error for zero width of the unused field, | |
724 | comment it out. */ | |
8c6c9809 | 725 | #define OTUnused (OTMax + 1) |
40fb9820 L |
726 | |
727 | typedef union i386_operand_type | |
728 | { | |
729 | struct | |
730 | { | |
731 | unsigned int reg8:1; | |
732 | unsigned int reg16:1; | |
733 | unsigned int reg32:1; | |
734 | unsigned int reg64:1; | |
7d5e4556 L |
735 | unsigned int floatreg:1; |
736 | unsigned int regmmx:1; | |
737 | unsigned int regxmm:1; | |
c0f3af97 | 738 | unsigned int regymm:1; |
43234a1e L |
739 | unsigned int regzmm:1; |
740 | unsigned int regmask:1; | |
7d5e4556 L |
741 | unsigned int control:1; |
742 | unsigned int debug:1; | |
743 | unsigned int test:1; | |
744 | unsigned int sreg2:1; | |
745 | unsigned int sreg3:1; | |
746 | unsigned int imm1:1; | |
40fb9820 L |
747 | unsigned int imm8:1; |
748 | unsigned int imm8s:1; | |
749 | unsigned int imm16:1; | |
750 | unsigned int imm32:1; | |
751 | unsigned int imm32s:1; | |
752 | unsigned int imm64:1; | |
40fb9820 L |
753 | unsigned int disp8:1; |
754 | unsigned int disp16:1; | |
755 | unsigned int disp32:1; | |
756 | unsigned int disp32s:1; | |
757 | unsigned int disp64:1; | |
7d5e4556 L |
758 | unsigned int acc:1; |
759 | unsigned int floatacc:1; | |
760 | unsigned int baseindex:1; | |
40fb9820 L |
761 | unsigned int inoutportreg:1; |
762 | unsigned int shiftcount:1; | |
40fb9820 | 763 | unsigned int jumpabsolute:1; |
40fb9820 L |
764 | unsigned int esseg:1; |
765 | unsigned int regmem:1; | |
5c07affc | 766 | unsigned int mem:1; |
7d5e4556 L |
767 | unsigned int byte:1; |
768 | unsigned int word:1; | |
769 | unsigned int dword:1; | |
770 | unsigned int fword:1; | |
771 | unsigned int qword:1; | |
772 | unsigned int tbyte:1; | |
773 | unsigned int xmmword:1; | |
c0f3af97 | 774 | unsigned int ymmword:1; |
43234a1e | 775 | unsigned int zmmword:1; |
7d5e4556 L |
776 | unsigned int unspecified:1; |
777 | unsigned int anysize:1; | |
a683cc34 | 778 | unsigned int vec_imm4:1; |
7e8b059b | 779 | unsigned int regbnd:1; |
43234a1e | 780 | unsigned int vec_disp8:1; |
40fb9820 L |
781 | #ifdef OTUnused |
782 | unsigned int unused:(OTNumOfBits - OTUnused); | |
783 | #endif | |
784 | } bitfield; | |
785 | unsigned int array[OTNumOfUints]; | |
786 | } i386_operand_type; | |
0b1cf022 | 787 | |
d3ce72d0 | 788 | typedef struct insn_template |
0b1cf022 L |
789 | { |
790 | /* instruction name sans width suffix ("mov" for movl insns) */ | |
791 | char *name; | |
792 | ||
793 | /* how many operands */ | |
794 | unsigned int operands; | |
795 | ||
796 | /* base_opcode is the fundamental opcode byte without optional | |
797 | prefix(es). */ | |
798 | unsigned int base_opcode; | |
799 | #define Opcode_D 0x2 /* Direction bit: | |
800 | set if Reg --> Regmem; | |
801 | unset if Regmem --> Reg. */ | |
802 | #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */ | |
803 | #define Opcode_FloatD 0x400 /* Direction bit for float insns. */ | |
804 | ||
805 | /* extension_opcode is the 3 bit extension for group <n> insns. | |
806 | This field is also used to store the 8-bit opcode suffix for the | |
807 | AMD 3DNow! instructions. | |
29c048b6 | 808 | If this template has no extension opcode (the usual case) use None |
c1e679ec | 809 | Instructions */ |
0b1cf022 L |
810 | unsigned int extension_opcode; |
811 | #define None 0xffff /* If no extension_opcode is possible. */ | |
812 | ||
4dffcebc L |
813 | /* Opcode length. */ |
814 | unsigned char opcode_length; | |
815 | ||
0b1cf022 | 816 | /* cpu feature flags */ |
40fb9820 | 817 | i386_cpu_flags cpu_flags; |
0b1cf022 L |
818 | |
819 | /* the bits in opcode_modifier are used to generate the final opcode from | |
820 | the base_opcode. These bits also are used to detect alternate forms of | |
821 | the same instruction */ | |
40fb9820 | 822 | i386_opcode_modifier opcode_modifier; |
0b1cf022 L |
823 | |
824 | /* operand_types[i] describes the type of operand i. This is made | |
825 | by OR'ing together all of the possible type masks. (e.g. | |
826 | 'operand_types[i] = Reg|Imm' specifies that operand i can be | |
827 | either a register or an immediate operand. */ | |
40fb9820 | 828 | i386_operand_type operand_types[MAX_OPERANDS]; |
0b1cf022 | 829 | } |
d3ce72d0 | 830 | insn_template; |
0b1cf022 | 831 | |
d3ce72d0 | 832 | extern const insn_template i386_optab[]; |
0b1cf022 L |
833 | |
834 | /* these are for register name --> number & type hash lookup */ | |
835 | typedef struct | |
836 | { | |
837 | char *reg_name; | |
40fb9820 | 838 | i386_operand_type reg_type; |
a60de03c | 839 | unsigned char reg_flags; |
0b1cf022 L |
840 | #define RegRex 0x1 /* Extended register. */ |
841 | #define RegRex64 0x2 /* Extended 8 bit register. */ | |
43234a1e | 842 | #define RegVRex 0x4 /* Extended vector register. */ |
a60de03c JB |
843 | unsigned char reg_num; |
844 | #define RegRip ((unsigned char ) ~0) | |
9a04903e | 845 | #define RegEip (RegRip - 1) |
db51cc60 | 846 | /* EIZ and RIZ are fake index registers. */ |
9a04903e | 847 | #define RegEiz (RegEip - 1) |
db51cc60 | 848 | #define RegRiz (RegEiz - 1) |
b7240065 JB |
849 | /* FLAT is a fake segment register (Intel mode). */ |
850 | #define RegFlat ((unsigned char) ~0) | |
a60de03c JB |
851 | signed char dw2_regnum[2]; |
852 | #define Dw2Inval (-1) | |
0b1cf022 L |
853 | } |
854 | reg_entry; | |
855 | ||
856 | /* Entries in i386_regtab. */ | |
857 | #define REGNAM_AL 1 | |
858 | #define REGNAM_AX 25 | |
859 | #define REGNAM_EAX 41 | |
860 | ||
861 | extern const reg_entry i386_regtab[]; | |
c3fe08fa | 862 | extern const unsigned int i386_regtab_size; |
0b1cf022 L |
863 | |
864 | typedef struct | |
865 | { | |
866 | char *seg_name; | |
867 | unsigned int seg_prefix; | |
868 | } | |
869 | seg_entry; | |
870 | ||
871 | extern const seg_entry cs; | |
872 | extern const seg_entry ds; | |
873 | extern const seg_entry ss; | |
874 | extern const seg_entry es; | |
875 | extern const seg_entry fs; | |
876 | extern const seg_entry gs; |