[deliverable/binutils-gdb.git] / opcodes / i386-opc.h

/* Declarations for Intel 80386 opcode table
   Copyright 2007, 2008
   Free Software Foundation, Inc.

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with GAS; see the file COPYING.  If not, write to the Free
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
   02110-1301, USA.  */

#include "opcode/i386.h"
#ifdef HAVE_LIMITS_H
#include <limits.h>
#endif

#ifndef CHAR_BIT
#define CHAR_BIT 8
#endif

/* Position of cpu flags bitfiled.  */

/* i186 or better required */
#define Cpu186		0
/* i286 or better required */
#define Cpu286		(Cpu186 + 1)
/* i386 or better required */
#define Cpu386		(Cpu286 + 1)
/* i486 or better required */
#define Cpu486		(Cpu386 + 1)
/* i585 or better required */
#define Cpu586		(Cpu486 + 1)
/* i686 or better required */
#define Cpu686		(Cpu586 + 1)
/* Pentium4 or better required */
#define CpuP4		(Cpu686 + 1)
/* AMD K6 or better required*/
#define CpuK6		(CpuP4 + 1)
/* AMD K8 or better required */
#define CpuK8		(CpuK6 + 1)
/* MMX support required */
#define CpuMMX		(CpuK8 + 1)
/* SSE support required */
#define CpuSSE		(CpuMMX + 1)
/* SSE2 support required */
#define CpuSSE2		(CpuSSE + 1)
/* 3dnow! support required */
#define Cpu3dnow	(CpuSSE2 + 1)
/* 3dnow! Extensions support required */
#define Cpu3dnowA	(Cpu3dnow + 1)
/* SSE3 support required */
#define CpuSSE3		(Cpu3dnowA + 1)
/* VIA PadLock required */
#define CpuPadLock	(CpuSSE3 + 1)
/* AMD Secure Virtual Machine Ext-s required */
#define CpuSVME		(CpuPadLock + 1)
/* VMX Instructions required */
#define CpuVMX		(CpuSVME + 1)
/* SMX Instructions required */
#define CpuSMX		(CpuVMX + 1)
/* SSSE3 support required */
#define CpuSSSE3	(CpuSMX + 1)
/* SSE4a support required */
#define CpuSSE4a	(CpuSSSE3 + 1)
/* ABM New Instructions required */
#define CpuABM		(CpuSSE4a + 1)
/* SSE4.1 support required */
#define CpuSSE4_1	(CpuABM + 1)
/* SSE4.2 support required */
#define CpuSSE4_2	(CpuSSE4_1 + 1)
/* SSE5 support required */
#define CpuSSE5		(CpuSSE4_2 + 1)
/* 64bit support available, used by -march= in assembler.  */
#define CpuLM		(CpuSSE5 + 1)
/* 64bit support required  */
#define Cpu64		(CpuLM + 1)
/* Not supported in the 64bit mode  */
#define CpuNo64		(Cpu64 + 1)
/* The last bitfield in i386_cpu_flags.  */
#define CpuMax		CpuNo64

#define CpuNumOfUints \
  (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
#define CpuNumOfBits \
  (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)

/* If you get a compiler error for zero width of the unused field,
   comment it out.  */
#define CpuUnused	(CpuMax + 1)

/* We can check if an instruction is available with array instead
   of bitfield. */
typedef union i386_cpu_flags
{
  struct
    {
      unsigned int cpui186:1;
      unsigned int cpui286:1;
      unsigned int cpui386:1;
      unsigned int cpui486:1;
      unsigned int cpui586:1;
      unsigned int cpui686:1;
      unsigned int cpup4:1;
      unsigned int cpuk6:1;
      unsigned int cpuk8:1;
      unsigned int cpummx:1;
      unsigned int cpusse:1;
      unsigned int cpusse2:1;
      unsigned int cpua3dnow:1;
      unsigned int cpua3dnowa:1;
      unsigned int cpusse3:1;
      unsigned int cpupadlock:1;
      unsigned int cpusvme:1;
      unsigned int cpuvmx:1;
      unsigned int cpusmx:1;
      unsigned int cpussse3:1;
      unsigned int cpusse4a:1;
      unsigned int cpuabm:1;
      unsigned int cpusse4_1:1;
      unsigned int cpusse4_2:1;
      unsigned int cpusse5:1;
      unsigned int cpulm:1;
      unsigned int cpu64:1;
      unsigned int cpuno64:1;
#ifdef CpuUnused
      unsigned int unused:(CpuNumOfBits - CpuUnused);
#endif
    } bitfield;
  unsigned int array[CpuNumOfUints];
} i386_cpu_flags;

/* Position of opcode_modifier bits.  */

/* has direction bit. */
#define D			0
/* set if operands can be words or dwords encoded the canonical way */
#define W			(D + 1)
/* insn has a modrm byte. */
#define Modrm			(W + 1)
/* register is in low 3 bits of opcode */
#define ShortForm		(Modrm + 1)
/* special case for jump insns.  */
#define Jump			(ShortForm + 1)
/* call and jump */
#define JumpDword		(Jump + 1)
/* loop and jecxz */
#define JumpByte		(JumpDword + 1)
/* special case for intersegment leaps/calls */
#define JumpInterSegment	(JumpByte + 1)
/* FP insn memory format bit, sized by 0x4 */
#define FloatMF			(JumpInterSegment + 1)
/* src/dest swap for floats. */
#define FloatR			(FloatMF + 1)
/* has float insn direction bit. */
#define FloatD			(FloatR + 1)
/* needs size prefix if in 32-bit mode */
#define Size16			(FloatD + 1)
/* needs size prefix if in 16-bit mode */
#define Size32			(Size16 + 1)
/* needs size prefix if in 64-bit mode */
#define Size64			(Size32 + 1)
/* instruction ignores operand size prefix and in Intel mode ignores
   mnemonic size suffix check.  */
#define IgnoreSize		(Size64 + 1)
/* default insn size depends on mode */
#define DefaultSize		(IgnoreSize + 1)
/* b suffix on instruction illegal */
#define No_bSuf			(DefaultSize + 1)
/* w suffix on instruction illegal */
#define No_wSuf			(No_bSuf + 1)
/* l suffix on instruction illegal */
#define No_lSuf			(No_wSuf + 1)
/* s suffix on instruction illegal */
#define No_sSuf			(No_lSuf + 1)
/* q suffix on instruction illegal */
#define No_qSuf			(No_sSuf + 1)
/* long double suffix on instruction illegal */
#define No_ldSuf		(No_qSuf + 1)
/* instruction needs FWAIT */
#define FWait			(No_ldSuf + 1)
/* quick test for string instructions */
#define IsString		(FWait + 1)
/* fake an extra reg operand for clr, imul and special register
   processing for some instructions.  */
#define RegKludge		(IsString + 1)
/* The first operand must be xmm0 */
#define FirstXmm0		(RegKludge + 1)
/* BYTE is OK in Intel syntax. */
#define ByteOkIntel		(FirstXmm0 + 1)
/* Convert to DWORD */
#define ToDword			(ByteOkIntel + 1)
/* Convert to QWORD */
#define ToQword			(ToDword + 1)
/* Address prefix changes operand 0 */
#define AddrPrefixOp0		(ToQword + 1)
/* opcode is a prefix */
#define IsPrefix		(AddrPrefixOp0 + 1)
/* instruction has extension in 8 bit imm */
#define ImmExt			(IsPrefix + 1)
/* instruction don't need Rex64 prefix.  */
#define NoRex64			(ImmExt + 1)
/* instruction require Rex64 prefix.  */
#define Rex64			(NoRex64 + 1)
/* deprecated fp insn, gets a warning */
#define Ugh			(Rex64 + 1)
#define Drex			(Ugh + 1)
/* instruction needs DREX with multiple encodings for memory ops */
#define Drexv			(Drex + 1)
/* special DREX for comparisons */
#define Drexc			(Drexv + 1)
/* Compatible with old (<= 2.8.1) versions of gcc  */
#define OldGcc			(Drexc + 1)
/* AT&T mnemonic.  */
#define ATTMnemonic		(OldGcc + 1)
/* AT&T syntax.  */
#define ATTSyntax		(ATTMnemonic + 1)
/* Intel syntax.  */
#define IntelSyntax		(ATTSyntax + 1)
/* The last bitfield in i386_opcode_modifier.  */
#define Opcode_Modifier_Max	IntelSyntax

typedef struct i386_opcode_modifier
{
  unsigned int d:1;
  unsigned int w:1;
  unsigned int modrm:1;
  unsigned int shortform:1;
  unsigned int jump:1;
  unsigned int jumpdword:1;
  unsigned int jumpbyte:1;
  unsigned int jumpintersegment:1;
  unsigned int floatmf:1;
  unsigned int floatr:1;
  unsigned int floatd:1;
  unsigned int size16:1;
  unsigned int size32:1;
  unsigned int size64:1;
  unsigned int ignoresize:1;
  unsigned int defaultsize:1;
  unsigned int no_bsuf:1;
  unsigned int no_wsuf:1;
  unsigned int no_lsuf:1;
  unsigned int no_ssuf:1;
  unsigned int no_qsuf:1;
  unsigned int no_ldsuf:1;
  unsigned int fwait:1;
  unsigned int isstring:1;
  unsigned int regkludge:1;
  unsigned int firstxmm0:1;
  unsigned int byteokintel:1;
  unsigned int todword:1;
  unsigned int toqword:1;
  unsigned int addrprefixop0:1;
  unsigned int isprefix:1;
  unsigned int immext:1;
  unsigned int norex64:1;
  unsigned int rex64:1;
  unsigned int ugh:1;
  unsigned int drex:1;
  unsigned int drexv:1;
  unsigned int drexc:1;
  unsigned int oldgcc:1;
  unsigned int attmnemonic:1;
  unsigned int attsyntax:1;
  unsigned int intelsyntax:1;
} i386_opcode_modifier;

/* Position of operand_type bits.  */

/* 8bit register */
#define Reg8			0
/* 16bit register */
#define Reg16			(Reg8 + 1)
/* 32bit register */
#define Reg32			(Reg16 + 1)
/* 64bit register */
#define Reg64			(Reg32 + 1)
/* Floating pointer stack register */
#define FloatReg		(Reg64 + 1)
/* MMX register */
#define RegMMX			(FloatReg + 1)
/* SSE register */
#define RegXMM			(RegMMX + 1)
/* Control register */
#define Control			(RegXMM + 1)
/* Debug register */
#define Debug			(Control + 1)
/* Test register */
#define Test			(Debug + 1)
/* 2 bit segment register */
#define SReg2			(Test + 1)
/* 3 bit segment register */
#define SReg3			(SReg2 + 1)
/* 1 bit immediate */
#define Imm1			(SReg3 + 1)
/* 8 bit immediate */
#define Imm8			(Imm1 + 1)
/* 8 bit immediate sign extended */
#define Imm8S			(Imm8 + 1)
/* 16 bit immediate */
#define Imm16			(Imm8S + 1)
/* 32 bit immediate */
#define Imm32			(Imm16 + 1)
/* 32 bit immediate sign extended */
#define Imm32S			(Imm32 + 1)
/* 64 bit immediate */
#define Imm64			(Imm32S + 1)
/* 8bit/16bit/32bit displacements are used in different ways,
   depending on the instruction.  For jumps, they specify the
   size of the PC relative displacement, for instructions with
   memory operand, they specify the size of the offset relative
   to the base register, and for instructions with memory offset
   such as `mov 1234,%al' they specify the size of the offset
   relative to the segment base.  */
/* 8 bit displacement */
#define Disp8			(Imm64 + 1)
/* 16 bit displacement */
#define Disp16			(Disp8 + 1)
/* 32 bit displacement */
#define Disp32			(Disp16 + 1)
/* 32 bit signed displacement */
#define Disp32S			(Disp32 + 1)
/* 64 bit displacement */
#define Disp64			(Disp32S + 1)
/* Accumulator %al/%ax/%eax/%rax */
#define Acc			(Disp64 + 1)
/* Floating pointer top stack register %st(0) */
#define FloatAcc		(Acc + 1)
/* Register which can be used for base or index in memory operand.  */
#define BaseIndex		(FloatAcc + 1)
/* Register to hold in/out port addr = dx */
#define InOutPortReg		(BaseIndex + 1)
/* Register to hold shift count = cl */
#define ShiftCount		(InOutPortReg + 1)
/* Absolute address for jump.  */
#define JumpAbsolute		(ShiftCount + 1)
/* String insn operand with fixed es segment */
#define EsSeg			(JumpAbsolute + 1)
/* RegMem is for instructions with a modrm byte where the register
   destination operand should be encoded in the mod and regmem fields.
   Normally, it will be encoded in the reg field. We add a RegMem
   flag to the destination register operand to indicate that it should
   be encoded in the regmem field.  */
#define RegMem			(EsSeg + 1)
/* Memory.  */
#define Mem			(RegMem + 1)
/* BYTE memory. */
#define Byte			(Mem + 1)
/* WORD memory. 2 byte */
#define Word			(Byte + 1)
/* DWORD memory. 4 byte */
#define Dword			(Word + 1)
/* FWORD memory. 6 byte */
#define Fword			(Dword + 1)
/* QWORD memory. 8 byte */
#define Qword			(Fword + 1)
/* TBYTE memory. 10 byte */
#define Tbyte			(Qword + 1)
/* XMMWORD memory. */
#define Xmmword			(Tbyte + 1)
/* Unspecified memory size.  */
#define Unspecified		(Xmmword + 1)
/* Any memory size.  */
#define Anysize			(Unspecified  + 1)

/* The last bitfield in i386_operand_type.  */
#define OTMax			Anysize

#define OTNumOfUints \
  (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
#define OTNumOfBits \
  (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)

/* If you get a compiler error for zero width of the unused field,
   comment it out.  */
#define OTUnused		(OTMax + 1)

typedef union i386_operand_type
{
  struct
    {
      unsigned int reg8:1;
      unsigned int reg16:1;
      unsigned int reg32:1;
      unsigned int reg64:1;
      unsigned int floatreg:1;
      unsigned int regmmx:1;
      unsigned int regxmm:1;
      unsigned int control:1;
      unsigned int debug:1;
      unsigned int test:1;
      unsigned int sreg2:1;
      unsigned int sreg3:1;
      unsigned int imm1:1;
      unsigned int imm8:1;
      unsigned int imm8s:1;
      unsigned int imm16:1;
      unsigned int imm32:1;
      unsigned int imm32s:1;
      unsigned int imm64:1;
      unsigned int disp8:1;
      unsigned int disp16:1;
      unsigned int disp32:1;
      unsigned int disp32s:1;
      unsigned int disp64:1;
      unsigned int acc:1;
      unsigned int floatacc:1;
      unsigned int baseindex:1;
      unsigned int inoutportreg:1;
      unsigned int shiftcount:1;
      unsigned int jumpabsolute:1;
      unsigned int esseg:1;
      unsigned int regmem:1;
      unsigned int mem:1;
      unsigned int byte:1;
      unsigned int word:1;
      unsigned int dword:1;
      unsigned int fword:1;
      unsigned int qword:1;
      unsigned int tbyte:1;
      unsigned int xmmword:1;
      unsigned int unspecified:1;
      unsigned int anysize:1;
#ifdef OTUnused
      unsigned int unused:(OTNumOfBits - OTUnused);
#endif
    } bitfield;
  unsigned int array[OTNumOfUints];
} i386_operand_type;

typedef struct template
{
  /* instruction name sans width suffix ("mov" for movl insns) */
  char *name;

  /* how many operands */
  unsigned int operands;

  /* base_opcode is the fundamental opcode byte without optional
     prefix(es).  */
  unsigned int base_opcode;
#define Opcode_D	0x2 /* Direction bit:
			       set if Reg --> Regmem;
			       unset if Regmem --> Reg. */
#define Opcode_FloatR	0x8 /* Bit to swap src/dest for float insns. */
#define Opcode_FloatD 0x400 /* Direction bit for float insns. */

  /* extension_opcode is the 3 bit extension for group <n> insns.
     This field is also used to store the 8-bit opcode suffix for the
     AMD 3DNow! instructions.
     If this template has no extension opcode (the usual case) use None 
     Instructions with Drex use this to specify 2 bits for OC */
  unsigned int extension_opcode;
#define None 0xffff		/* If no extension_opcode is possible.  */

  /* Opcode length.  */
  unsigned char opcode_length;

  /* cpu feature flags */
  i386_cpu_flags cpu_flags;

  /* the bits in opcode_modifier are used to generate the final opcode from
     the base_opcode.  These bits also are used to detect alternate forms of
     the same instruction */
  i386_opcode_modifier opcode_modifier;

  /* operand_types[i] describes the type of operand i.  This is made
     by OR'ing together all of the possible type masks.  (e.g.
     'operand_types[i] = Reg|Imm' specifies that operand i can be
     either a register or an immediate operand.  */
  i386_operand_type operand_types[MAX_OPERANDS];
}
template;

extern const template i386_optab[];

/* these are for register name --> number & type hash lookup */
typedef struct
{
  char *reg_name;
  i386_operand_type reg_type;
  unsigned int reg_flags;
#define RegRex	    0x1  /* Extended register.  */
#define RegRex64    0x2  /* Extended 8 bit register.  */
  unsigned int reg_num;
#define RegRip	((unsigned int ) ~0)
#define RegEip	(RegRip - 1)
/* EIZ and RIZ are fake index registers.  */
#define RegEiz	(RegEip - 1)
#define RegRiz	(RegEiz - 1)
}
reg_entry;

/* Entries in i386_regtab.  */
#define REGNAM_AL 1
#define REGNAM_AX 25
#define REGNAM_EAX 41

extern const reg_entry i386_regtab[];
extern const unsigned int i386_regtab_size;

typedef struct
{
  char *seg_name;
  unsigned int seg_prefix;
}
seg_entry;

extern const seg_entry cs;
extern const seg_entry ds;
extern const seg_entry ss;
extern const seg_entry es;
extern const seg_entry fs;
extern const seg_entry gs;
Commit	Line	Data
0b1cf022	1	/* Declarations for Intel 80386 opcode table
6f143e4d	2	Copyright 2007, 2008
0b1cf022 L	3	Free Software Foundation, Inc.
0b1cf022 L	4
9b201bb5	5	This file is part of the GNU opcodes library.
0b1cf022	6
9b201bb5	7	This library is free software; you can redistribute it and/or modify
0b1cf022	8	it under the terms of the GNU General Public License as published by
9b201bb5	9	the Free Software Foundation; either version 3, or (at your option)
0b1cf022 L	10	any later version.
0b1cf022 L	11
9b201bb5 NC	12	It is distributed in the hope that it will be useful, but WITHOUT
	13	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	14	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	License for more details.
0b1cf022 L	16
	17	You should have received a copy of the GNU General Public License
	18	along with GAS; see the file COPYING. If not, write to the Free
	19	Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
	20	02110-1301, USA. */
	21
	22	#include "opcode/i386.h"
40fb9820 L	23	#ifdef HAVE_LIMITS_H
	24	#include <limits.h>
	25	#endif
	26
	27	#ifndef CHAR_BIT
	28	#define CHAR_BIT 8
	29	#endif
	30
	31	/* Position of cpu flags bitfiled. */
	32
	33	/* i186 or better required */
	34	#define Cpu186 0
	35	/* i286 or better required */
	36	#define Cpu286 (Cpu186 + 1)
	37	/* i386 or better required */
	38	#define Cpu386 (Cpu286 + 1)
	39	/* i486 or better required */
	40	#define Cpu486 (Cpu386 + 1)
	41	/* i585 or better required */
	42	#define Cpu586 (Cpu486 + 1)
	43	/* i686 or better required */
	44	#define Cpu686 (Cpu586 + 1)
	45	/* Pentium4 or better required */
	46	#define CpuP4 (Cpu686 + 1)
	47	/* AMD K6 or better required*/
	48	#define CpuK6 (CpuP4 + 1)
	49	/* AMD K8 or better required */
	50	#define CpuK8 (CpuK6 + 1)
	51	/* MMX support required */
	52	#define CpuMMX (CpuK8 + 1)
40fb9820	53	/* SSE support required */
115c7c25	54	#define CpuSSE (CpuMMX + 1)
40fb9820 L	55	/* SSE2 support required */
	56	#define CpuSSE2 (CpuSSE + 1)
	57	/* 3dnow! support required */
	58	#define Cpu3dnow (CpuSSE2 + 1)
	59	/* 3dnow! Extensions support required */
	60	#define Cpu3dnowA (Cpu3dnow + 1)
	61	/* SSE3 support required */
	62	#define CpuSSE3 (Cpu3dnowA + 1)
	63	/* VIA PadLock required */
	64	#define CpuPadLock (CpuSSE3 + 1)
	65	/* AMD Secure Virtual Machine Ext-s required */
	66	#define CpuSVME (CpuPadLock + 1)
	67	/* VMX Instructions required */
	68	#define CpuVMX (CpuSVME + 1)
47dd174c L	69	/* SMX Instructions required */
47dd174c L	70	#define CpuSMX (CpuVMX + 1)
40fb9820	71	/* SSSE3 support required */
47dd174c	72	#define CpuSSSE3 (CpuSMX + 1)
40fb9820 L	73	/* SSE4a support required */
	74	#define CpuSSE4a (CpuSSSE3 + 1)
	75	/* ABM New Instructions required */
	76	#define CpuABM (CpuSSE4a + 1)
	77	/* SSE4.1 support required */
	78	#define CpuSSE4_1 (CpuABM + 1)
	79	/* SSE4.2 support required */
	80	#define CpuSSE4_2 (CpuSSE4_1 + 1)
85f10a01	81	/* SSE5 support required */
a967d2b7	82	#define CpuSSE5 (CpuSSE4_2 + 1)
40fb9820	83	/* 64bit support available, used by -march= in assembler. */
3629bb00	84	#define CpuLM (CpuSSE5 + 1)
40fb9820 L	85	/* 64bit support required */
	86	#define Cpu64 (CpuLM + 1)
	87	/* Not supported in the 64bit mode */
	88	#define CpuNo64 (Cpu64 + 1)
	89	/* The last bitfield in i386_cpu_flags. */
	90	#define CpuMax CpuNo64
	91
	92	#define CpuNumOfUints \
	93	(CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
	94	#define CpuNumOfBits \
	95	(CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
	96
	97	/* If you get a compiler error for zero width of the unused field,
	98	comment it out. */
8c6c9809	99	#define CpuUnused (CpuMax + 1)
40fb9820 L	100
	101	/* We can check if an instruction is available with array instead
	102	of bitfield. */
	103	typedef union i386_cpu_flags
	104	{
	105	struct
	106	{
	107	unsigned int cpui186:1;
	108	unsigned int cpui286:1;
	109	unsigned int cpui386:1;
	110	unsigned int cpui486:1;
	111	unsigned int cpui586:1;
	112	unsigned int cpui686:1;
	113	unsigned int cpup4:1;
	114	unsigned int cpuk6:1;
	115	unsigned int cpuk8:1;
	116	unsigned int cpummx:1;
40fb9820 L	117	unsigned int cpusse:1;
	118	unsigned int cpusse2:1;
	119	unsigned int cpua3dnow:1;
	120	unsigned int cpua3dnowa:1;
	121	unsigned int cpusse3:1;
	122	unsigned int cpupadlock:1;
	123	unsigned int cpusvme:1;
	124	unsigned int cpuvmx:1;
47dd174c	125	unsigned int cpusmx:1;
40fb9820 L	126	unsigned int cpussse3:1;
	127	unsigned int cpusse4a:1;
	128	unsigned int cpuabm:1;
	129	unsigned int cpusse4_1:1;
	130	unsigned int cpusse4_2:1;
85f10a01	131	unsigned int cpusse5:1;
40fb9820 L	132	unsigned int cpulm:1;
	133	unsigned int cpu64:1;
	134	unsigned int cpuno64:1;
	135	#ifdef CpuUnused
	136	unsigned int unused:(CpuNumOfBits - CpuUnused);
	137	#endif
	138	} bitfield;
	139	unsigned int array[CpuNumOfUints];
	140	} i386_cpu_flags;
	141
	142	/* Position of opcode_modifier bits. */
	143
	144	/* has direction bit. */
	145	#define D 0
	146	/* set if operands can be words or dwords encoded the canonical way */
	147	#define W (D + 1)
	148	/* insn has a modrm byte. */
	149	#define Modrm (W + 1)
	150	/* register is in low 3 bits of opcode */
	151	#define ShortForm (Modrm + 1)
	152	/* special case for jump insns. */
	153	#define Jump (ShortForm + 1)
	154	/* call and jump */
	155	#define JumpDword (Jump + 1)
	156	/* loop and jecxz */
	157	#define JumpByte (JumpDword + 1)
	158	/* special case for intersegment leaps/calls */
	159	#define JumpInterSegment (JumpByte + 1)
	160	/* FP insn memory format bit, sized by 0x4 */
	161	#define FloatMF (JumpInterSegment + 1)
	162	/* src/dest swap for floats. */
	163	#define FloatR (FloatMF + 1)
	164	/* has float insn direction bit. */
	165	#define FloatD (FloatR + 1)
	166	/* needs size prefix if in 32-bit mode */
	167	#define Size16 (FloatD + 1)
	168	/* needs size prefix if in 16-bit mode */
	169	#define Size32 (Size16 + 1)
	170	/* needs size prefix if in 64-bit mode */
	171	#define Size64 (Size32 + 1)
f2a9c676 L	172	/* instruction ignores operand size prefix and in Intel mode ignores
f2a9c676 L	173	mnemonic size suffix check. */
40fb9820 L	174	#define IgnoreSize (Size64 + 1)
	175	/* default insn size depends on mode */
	176	#define DefaultSize (IgnoreSize + 1)
	177	/* b suffix on instruction illegal */
	178	#define No_bSuf (DefaultSize + 1)
	179	/* w suffix on instruction illegal */
	180	#define No_wSuf (No_bSuf + 1)
	181	/* l suffix on instruction illegal */
	182	#define No_lSuf (No_wSuf + 1)
	183	/* s suffix on instruction illegal */
	184	#define No_sSuf (No_lSuf + 1)
	185	/* q suffix on instruction illegal */
	186	#define No_qSuf (No_sSuf + 1)
7ce189b3 L	187	/* long double suffix on instruction illegal */
7ce189b3 L	188	#define No_ldSuf (No_qSuf + 1)
40fb9820	189	/* instruction needs FWAIT */
7d5e4556	190	#define FWait (No_ldSuf + 1)
40fb9820 L	191	/* quick test for string instructions */
	192	#define IsString (FWait + 1)
	193	/* fake an extra reg operand for clr, imul and special register
	194	processing for some instructions. */
	195	#define RegKludge (IsString + 1)
e2ec9d29 L	196	/* The first operand must be xmm0 */
e2ec9d29 L	197	#define FirstXmm0 (RegKludge + 1)
ca61edf2 L	198	/* BYTE is OK in Intel syntax. */
	199	#define ByteOkIntel (FirstXmm0 + 1)
	200	/* Convert to DWORD */
	201	#define ToDword (ByteOkIntel + 1)
	202	/* Convert to QWORD */
	203	#define ToQword (ToDword + 1)
	204	/* Address prefix changes operand 0 */
	205	#define AddrPrefixOp0 (ToQword + 1)
40fb9820	206	/* opcode is a prefix */
ca61edf2	207	#define IsPrefix (AddrPrefixOp0 + 1)
40fb9820 L	208	/* instruction has extension in 8 bit imm */
	209	#define ImmExt (IsPrefix + 1)
	210	/* instruction don't need Rex64 prefix. */
	211	#define NoRex64 (ImmExt + 1)
	212	/* instruction require Rex64 prefix. */
	213	#define Rex64 (NoRex64 + 1)
	214	/* deprecated fp insn, gets a warning */
	215	#define Ugh (Rex64 + 1)
a967d2b7	216	#define Drex (Ugh + 1)
85f10a01	217	/* instruction needs DREX with multiple encodings for memory ops */
a967d2b7	218	#define Drexv (Drex + 1)
85f10a01	219	/* special DREX for comparisons */
a967d2b7	220	#define Drexc (Drexv + 1)
1efbbeb4 L	221	/* Compatible with old (<= 2.8.1) versions of gcc */
	222	#define OldGcc (Drexc + 1)
	223	/* AT&T mnemonic. */
	224	#define ATTMnemonic (OldGcc + 1)
e1d4d893 L	225	/* AT&T syntax. */
e1d4d893 L	226	#define ATTSyntax (ATTMnemonic + 1)
5c07affc L	227	/* Intel syntax. */
5c07affc L	228	#define IntelSyntax (ATTSyntax + 1)
40fb9820	229	/* The last bitfield in i386_opcode_modifier. */
5c07affc	230	#define Opcode_Modifier_Max IntelSyntax
40fb9820 L	231
	232	typedef struct i386_opcode_modifier
	233	{
	234	unsigned int d:1;
	235	unsigned int w:1;
	236	unsigned int modrm:1;
	237	unsigned int shortform:1;
	238	unsigned int jump:1;
	239	unsigned int jumpdword:1;
	240	unsigned int jumpbyte:1;
	241	unsigned int jumpintersegment:1;
	242	unsigned int floatmf:1;
	243	unsigned int floatr:1;
	244	unsigned int floatd:1;
	245	unsigned int size16:1;
	246	unsigned int size32:1;
	247	unsigned int size64:1;
	248	unsigned int ignoresize:1;
	249	unsigned int defaultsize:1;
	250	unsigned int no_bsuf:1;
	251	unsigned int no_wsuf:1;
	252	unsigned int no_lsuf:1;
	253	unsigned int no_ssuf:1;
	254	unsigned int no_qsuf:1;
7ce189b3	255	unsigned int no_ldsuf:1;
40fb9820 L	256	unsigned int fwait:1;
	257	unsigned int isstring:1;
	258	unsigned int regkludge:1;
e2ec9d29	259	unsigned int firstxmm0:1;
ca61edf2 L	260	unsigned int byteokintel:1;
	261	unsigned int todword:1;
	262	unsigned int toqword:1;
	263	unsigned int addrprefixop0:1;
40fb9820 L	264	unsigned int isprefix:1;
	265	unsigned int immext:1;
	266	unsigned int norex64:1;
	267	unsigned int rex64:1;
	268	unsigned int ugh:1;
85f10a01 MM	269	unsigned int drex:1;
	270	unsigned int drexv:1;
	271	unsigned int drexc:1;
1efbbeb4 L	272	unsigned int oldgcc:1;
1efbbeb4 L	273	unsigned int attmnemonic:1;
e1d4d893	274	unsigned int attsyntax:1;
5c07affc	275	unsigned int intelsyntax:1;
40fb9820 L	276	} i386_opcode_modifier;
	277
	278	/* Position of operand_type bits. */
	279
7d5e4556	280	/* 8bit register */
40fb9820	281	#define Reg8 0
7d5e4556	282	/* 16bit register */
40fb9820	283	#define Reg16 (Reg8 + 1)
7d5e4556	284	/* 32bit register */
40fb9820	285	#define Reg32 (Reg16 + 1)
7d5e4556	286	/* 64bit register */
40fb9820	287	#define Reg64 (Reg32 + 1)
7d5e4556 L	288	/* Floating pointer stack register */
	289	#define FloatReg (Reg64 + 1)
	290	/* MMX register */
	291	#define RegMMX (FloatReg + 1)
	292	/* SSE register */
	293	#define RegXMM (RegMMX + 1)
	294	/* Control register */
	295	#define Control (RegXMM + 1)
	296	/* Debug register */
	297	#define Debug (Control + 1)
	298	/* Test register */
	299	#define Test (Debug + 1)
	300	/* 2 bit segment register */
	301	#define SReg2 (Test + 1)
	302	/* 3 bit segment register */
	303	#define SReg3 (SReg2 + 1)
	304	/* 1 bit immediate */
	305	#define Imm1 (SReg3 + 1)
40fb9820	306	/* 8 bit immediate */
7d5e4556	307	#define Imm8 (Imm1 + 1)
40fb9820 L	308	/* 8 bit immediate sign extended */
	309	#define Imm8S (Imm8 + 1)
	310	/* 16 bit immediate */
	311	#define Imm16 (Imm8S + 1)
	312	/* 32 bit immediate */
	313	#define Imm32 (Imm16 + 1)
	314	/* 32 bit immediate sign extended */
	315	#define Imm32S (Imm32 + 1)
	316	/* 64 bit immediate */
	317	#define Imm64 (Imm32S + 1)
7d5e4556 L	318	/* 8bit/16bit/32bit displacements are used in different ways,
	319	depending on the instruction. For jumps, they specify the
	320	size of the PC relative displacement, for instructions with
	321	memory operand, they specify the size of the offset relative
	322	to the base register, and for instructions with memory offset
	323	such as `mov 1234,%al' they specify the size of the offset
	324	relative to the segment base. */
40fb9820	325	/* 8 bit displacement */
7d5e4556	326	#define Disp8 (Imm64 + 1)
40fb9820 L	327	/* 16 bit displacement */
	328	#define Disp16 (Disp8 + 1)
	329	/* 32 bit displacement */
	330	#define Disp32 (Disp16 + 1)
	331	/* 32 bit signed displacement */
	332	#define Disp32S (Disp32 + 1)
	333	/* 64 bit displacement */
	334	#define Disp64 (Disp32S + 1)
7d5e4556 L	335	/* Accumulator %al/%ax/%eax/%rax */
	336	#define Acc (Disp64 + 1)
	337	/* Floating pointer top stack register %st(0) */
	338	#define FloatAcc (Acc + 1)
	339	/* Register which can be used for base or index in memory operand. */
	340	#define BaseIndex (FloatAcc + 1)
	341	/* Register to hold in/out port addr = dx */
	342	#define InOutPortReg (BaseIndex + 1)
	343	/* Register to hold shift count = cl */
40fb9820	344	#define ShiftCount (InOutPortReg + 1)
7d5e4556 L	345	/* Absolute address for jump. */
7d5e4556 L	346	#define JumpAbsolute (ShiftCount + 1)
40fb9820	347	/* String insn operand with fixed es segment */
7d5e4556	348	#define EsSeg (JumpAbsolute + 1)
40fb9820 L	349	/* RegMem is for instructions with a modrm byte where the register
	350	destination operand should be encoded in the mod and regmem fields.
	351	Normally, it will be encoded in the reg field. We add a RegMem
	352	flag to the destination register operand to indicate that it should
	353	be encoded in the regmem field. */
	354	#define RegMem (EsSeg + 1)
5c07affc L	355	/* Memory. */
5c07affc L	356	#define Mem (RegMem + 1)
7d5e4556	357	/* BYTE memory. */
5c07affc	358	#define Byte (Mem + 1)
7d5e4556 L	359	/* WORD memory. 2 byte */
	360	#define Word (Byte + 1)
	361	/* DWORD memory. 4 byte */
	362	#define Dword (Word + 1)
	363	/* FWORD memory. 6 byte */
	364	#define Fword (Dword + 1)
	365	/* QWORD memory. 8 byte */
	366	#define Qword (Fword + 1)
	367	/* TBYTE memory. 10 byte */
	368	#define Tbyte (Qword + 1)
	369	/* XMMWORD memory. */
	370	#define Xmmword (Tbyte + 1)
	371	/* Unspecified memory size. */
	372	#define Unspecified (Xmmword + 1)
	373	/* Any memory size. */
	374	#define Anysize (Unspecified + 1)
40fb9820 L	375
40fb9820 L	376	/* The last bitfield in i386_operand_type. */
7d5e4556	377	#define OTMax Anysize
40fb9820 L	378
	379	#define OTNumOfUints \
	380	(OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
	381	#define OTNumOfBits \
	382	(OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
	383
	384	/* If you get a compiler error for zero width of the unused field,
	385	comment it out. */
8c6c9809	386	#define OTUnused (OTMax + 1)
40fb9820 L	387
	388	typedef union i386_operand_type
	389	{
	390	struct
	391	{
	392	unsigned int reg8:1;
	393	unsigned int reg16:1;
	394	unsigned int reg32:1;
	395	unsigned int reg64:1;
7d5e4556 L	396	unsigned int floatreg:1;
	397	unsigned int regmmx:1;
	398	unsigned int regxmm:1;
	399	unsigned int control:1;
	400	unsigned int debug:1;
	401	unsigned int test:1;
	402	unsigned int sreg2:1;
	403	unsigned int sreg3:1;
	404	unsigned int imm1:1;
40fb9820 L	405	unsigned int imm8:1;
	406	unsigned int imm8s:1;
	407	unsigned int imm16:1;
	408	unsigned int imm32:1;
	409	unsigned int imm32s:1;
	410	unsigned int imm64:1;
40fb9820 L	411	unsigned int disp8:1;
	412	unsigned int disp16:1;
	413	unsigned int disp32:1;
	414	unsigned int disp32s:1;
	415	unsigned int disp64:1;
7d5e4556 L	416	unsigned int acc:1;
	417	unsigned int floatacc:1;
	418	unsigned int baseindex:1;
40fb9820 L	419	unsigned int inoutportreg:1;
40fb9820 L	420	unsigned int shiftcount:1;
40fb9820	421	unsigned int jumpabsolute:1;
40fb9820 L	422	unsigned int esseg:1;
40fb9820 L	423	unsigned int regmem:1;
5c07affc	424	unsigned int mem:1;
7d5e4556 L	425	unsigned int byte:1;
	426	unsigned int word:1;
	427	unsigned int dword:1;
	428	unsigned int fword:1;
	429	unsigned int qword:1;
	430	unsigned int tbyte:1;
	431	unsigned int xmmword:1;
	432	unsigned int unspecified:1;
	433	unsigned int anysize:1;
40fb9820 L	434	#ifdef OTUnused
	435	unsigned int unused:(OTNumOfBits - OTUnused);
	436	#endif
	437	} bitfield;
	438	unsigned int array[OTNumOfUints];
	439	} i386_operand_type;
0b1cf022 L	440
	441	typedef struct template
	442	{
	443	/* instruction name sans width suffix ("mov" for movl insns) */
	444	char *name;
	445
	446	/* how many operands */
	447	unsigned int operands;
	448
	449	/* base_opcode is the fundamental opcode byte without optional
	450	prefix(es). */
	451	unsigned int base_opcode;
	452	#define Opcode_D 0x2 /* Direction bit:
	453	set if Reg --> Regmem;
	454	unset if Regmem --> Reg. */
	455	#define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
	456	#define Opcode_FloatD 0x400 /* Direction bit for float insns. */
	457
	458	/* extension_opcode is the 3 bit extension for group <n> insns.
	459	This field is also used to store the 8-bit opcode suffix for the
	460	AMD 3DNow! instructions.
85f10a01 MM	461	If this template has no extension opcode (the usual case) use None
85f10a01 MM	462	Instructions with Drex use this to specify 2 bits for OC */
0b1cf022 L	463	unsigned int extension_opcode;
	464	#define None 0xffff /* If no extension_opcode is possible. */
	465
4dffcebc L	466	/* Opcode length. */
	467	unsigned char opcode_length;
	468
0b1cf022	469	/* cpu feature flags */
40fb9820	470	i386_cpu_flags cpu_flags;
0b1cf022 L	471
	472	/* the bits in opcode_modifier are used to generate the final opcode from
	473	the base_opcode. These bits also are used to detect alternate forms of
	474	the same instruction */
40fb9820	475	i386_opcode_modifier opcode_modifier;
0b1cf022 L	476
	477	/* operand_types[i] describes the type of operand i. This is made
	478	by OR'ing together all of the possible type masks. (e.g.
	479	'operand_types[i] = Reg\|Imm' specifies that operand i can be
	480	either a register or an immediate operand. */
40fb9820	481	i386_operand_type operand_types[MAX_OPERANDS];
0b1cf022 L	482	}
	483	template;
	484
	485	extern const template i386_optab[];
	486
	487	/* these are for register name --> number & type hash lookup */
	488	typedef struct
	489	{
	490	char *reg_name;
40fb9820	491	i386_operand_type reg_type;
0b1cf022 L	492	unsigned int reg_flags;
	493	#define RegRex 0x1 /* Extended register. */
	494	#define RegRex64 0x2 /* Extended 8 bit register. */
	495	unsigned int reg_num;
20e192ab	496	#define RegRip ((unsigned int ) ~0)
9a04903e	497	#define RegEip (RegRip - 1)
db51cc60	498	/* EIZ and RIZ are fake index registers. */
9a04903e	499	#define RegEiz (RegEip - 1)
db51cc60	500	#define RegRiz (RegEiz - 1)
0b1cf022 L	501	}
	502	reg_entry;
	503
	504	/* Entries in i386_regtab. */
	505	#define REGNAM_AL 1
	506	#define REGNAM_AX 25
	507	#define REGNAM_EAX 41
	508
	509	extern const reg_entry i386_regtab[];
c3fe08fa	510	extern const unsigned int i386_regtab_size;
0b1cf022 L	511
	512	typedef struct
	513	{
	514	char *seg_name;
	515	unsigned int seg_prefix;
	516	}
	517	seg_entry;
	518
	519	extern const seg_entry cs;
	520	extern const seg_entry ds;
	521	extern const seg_entry ss;
	522	extern const seg_entry es;
	523	extern const seg_entry fs;
	524	extern const seg_entry gs;