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[deliverable/binutils-gdb.git] / opcodes / i386-reg.tbl
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40b8e679 1// i386 register table.
250d07de 2// Copyright (C) 2007-2021 Free Software Foundation, Inc.
9b201bb5
NC		 3//
4// This file is part of the GNU opcodes library.
5//
6// This library is free software; you can redistribute it and/or modify
7// it under the terms of the GNU General Public License as published by
8// the Free Software Foundation; either version 3, or (at your option)
9// any later version.
10//
11// It is distributed in the hope that it will be useful, but WITHOUT
12// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14// License for more details.
15//
16// You should have received a copy of the GNU General Public License
17// along with GAS; see the file COPYING. If not, write to the Free
18// Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19// 02110-1301, USA.
40b8e679 20
40b8e679 21// 8 bit regs
75e5731b
JB		 22al, Class=Reg|Instance=Accum|Byte, 0, 0, Dw2Inval, Dw2Inval
23cl, Class=Reg|Instance=RegC|Byte, 0, 1, Dw2Inval, Dw2Inval
bab6aec1
JB		 24dl, Class=Reg|Byte, 0, 2, Dw2Inval, Dw2Inval
25bl, Class=Reg|Byte, 0, 3, Dw2Inval, Dw2Inval
26ah, Class=Reg|Byte, 0, 4, Dw2Inval, Dw2Inval
27ch, Class=Reg|Byte, 0, 5, Dw2Inval, Dw2Inval
28dh, Class=Reg|Byte, 0, 6, Dw2Inval, Dw2Inval
29bh, Class=Reg|Byte, 0, 7, Dw2Inval, Dw2Inval
30axl, Class=Reg|Byte, RegRex64, 0, Dw2Inval, Dw2Inval
31cxl, Class=Reg|Byte, RegRex64, 1, Dw2Inval, Dw2Inval
32dxl, Class=Reg|Byte, RegRex64, 2, Dw2Inval, Dw2Inval
33bxl, Class=Reg|Byte, RegRex64, 3, Dw2Inval, Dw2Inval
34spl, Class=Reg|Byte, RegRex64, 4, Dw2Inval, Dw2Inval
35bpl, Class=Reg|Byte, RegRex64, 5, Dw2Inval, Dw2Inval
36sil, Class=Reg|Byte, RegRex64, 6, Dw2Inval, Dw2Inval
37dil, Class=Reg|Byte, RegRex64, 7, Dw2Inval, Dw2Inval
38r8b, Class=Reg|Byte, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval
39r9b, Class=Reg|Byte, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval
40r10b, Class=Reg|Byte, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval
41r11b, Class=Reg|Byte, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval
42r12b, Class=Reg|Byte, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval
43r13b, Class=Reg|Byte, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval
44r14b, Class=Reg|Byte, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
45r15b, Class=Reg|Byte, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
40b8e679 46// 16 bit regs
75e5731b 47ax, Class=Reg|Instance=Accum|Word, 0, 0, Dw2Inval, Dw2Inval
bab6aec1 48cx, Class=Reg|Word, 0, 1, Dw2Inval, Dw2Inval
75e5731b 49dx, Class=Reg|Instance=RegD|Word, 0, 2, Dw2Inval, Dw2Inval
bab6aec1
JB		 50bx, Class=Reg|Word|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
51sp, Class=Reg|Word, 0, 4, Dw2Inval, Dw2Inval
52bp, Class=Reg|Word|BaseIndex, 0, 5, Dw2Inval, Dw2Inval
53si, Class=Reg|Word|BaseIndex, 0, 6, Dw2Inval, Dw2Inval
54di, Class=Reg|Word|BaseIndex, 0, 7, Dw2Inval, Dw2Inval
55r8w, Class=Reg|Word, RegRex, 0, Dw2Inval, Dw2Inval
56r9w, Class=Reg|Word, RegRex, 1, Dw2Inval, Dw2Inval
57r10w, Class=Reg|Word, RegRex, 2, Dw2Inval, Dw2Inval
58r11w, Class=Reg|Word, RegRex, 3, Dw2Inval, Dw2Inval
59r12w, Class=Reg|Word, RegRex, 4, Dw2Inval, Dw2Inval
60r13w, Class=Reg|Word, RegRex, 5, Dw2Inval, Dw2Inval
61r14w, Class=Reg|Word, RegRex, 6, Dw2Inval, Dw2Inval
62r15w, Class=Reg|Word, RegRex, 7, Dw2Inval, Dw2Inval
40b8e679 63// 32 bit regs
75e5731b 64eax, Class=Reg|Instance=Accum|Dword|BaseIndex, 0, 0, 0, Dw2Inval
474da251
JB		 65ecx, Class=Reg|Instance=RegC|Dword|BaseIndex, 0, 1, 1, Dw2Inval
66edx, Class=Reg|Instance=RegD|Dword|BaseIndex, 0, 2, 2, Dw2Inval
67ebx, Class=Reg|Instance=RegB|Dword|BaseIndex, 0, 3, 3, Dw2Inval
bab6aec1
JB		 68esp, Class=Reg|Dword, 0, 4, 4, Dw2Inval
69ebp, Class=Reg|Dword|BaseIndex, 0, 5, 5, Dw2Inval
70esi, Class=Reg|Dword|BaseIndex, 0, 6, 6, Dw2Inval
71edi, Class=Reg|Dword|BaseIndex, 0, 7, 7, Dw2Inval
72r8d, Class=Reg|Dword|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval
73r9d, Class=Reg|Dword|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval
74r10d, Class=Reg|Dword|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval
75r11d, Class=Reg|Dword|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval
76r12d, Class=Reg|Dword|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval
77r13d, Class=Reg|Dword|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
78r14d, Class=Reg|Dword|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
79r15d, Class=Reg|Dword|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
75e5731b 80rax, Class=Reg|Instance=Accum|Qword|BaseIndex, 0, 0, Dw2Inval, 0
474da251
JB		 81rcx, Class=Reg|Instance=RegC|Qword|BaseIndex, 0, 1, Dw2Inval, 2
82rdx, Class=Reg|Instance=RegD|Qword|BaseIndex, 0, 2, Dw2Inval, 1
83rbx, Class=Reg|Instance=RegB|Qword|BaseIndex, 0, 3, Dw2Inval, 3
bab6aec1
JB		 84rsp, Class=Reg|Qword, 0, 4, Dw2Inval, 7
85rbp, Class=Reg|Qword|BaseIndex, 0, 5, Dw2Inval, 6
86rsi, Class=Reg|Qword|BaseIndex, 0, 6, Dw2Inval, 4
87rdi, Class=Reg|Qword|BaseIndex, 0, 7, Dw2Inval, 5
88r8, Class=Reg|Qword|BaseIndex, RegRex, 0, Dw2Inval, 8
89r9, Class=Reg|Qword|BaseIndex, RegRex, 1, Dw2Inval, 9
90r10, Class=Reg|Qword|BaseIndex, RegRex, 2, Dw2Inval, 10
91r11, Class=Reg|Qword|BaseIndex, RegRex, 3, Dw2Inval, 11
92r12, Class=Reg|Qword|BaseIndex, RegRex, 4, Dw2Inval, 12
93r13, Class=Reg|Qword|BaseIndex, RegRex, 5, Dw2Inval, 13
94r14, Class=Reg|Qword|BaseIndex, RegRex, 6, Dw2Inval, 14
95r15, Class=Reg|Qword|BaseIndex, RegRex, 7, Dw2Inval, 15
43234a1e 96// Vector mask registers.
f74a6307
JB		 97k0, Class=RegMask, 0, 0, 93, 118
98k1, Class=RegMask, 0, 1, 94, 119
99k2, Class=RegMask, 0, 2, 95, 120
100k3, Class=RegMask, 0, 3, 96, 121
101k4, Class=RegMask, 0, 4, 97, 122
102k5, Class=RegMask, 0, 5, 98, 123
103k6, Class=RegMask, 0, 6, 99, 124
104k7, Class=RegMask, 0, 7, 100, 125
f85fcb85 105// Segment registers.
00cee14f
JB		 106es, Class=SReg, 0, 0, 40, 50
107cs, Class=SReg, 0, 1, 41, 51
108ss, Class=SReg, 0, 2, 42, 52
109ds, Class=SReg, 0, 3, 43, 53
110fs, Class=SReg, 0, 4, 44, 54
111gs, Class=SReg, 0, 5, 45, 55
112flat, Class=SReg, 0, RegFlat, Dw2Inval, Dw2Inval
40b8e679 113// Control registers.
4a5c67ed
JB		 114cr0, Class=RegCR, 0, 0, Dw2Inval, Dw2Inval
115cr1, Class=RegCR, 0, 1, Dw2Inval, Dw2Inval
116cr2, Class=RegCR, 0, 2, Dw2Inval, Dw2Inval
117cr3, Class=RegCR, 0, 3, Dw2Inval, Dw2Inval
118cr4, Class=RegCR, 0, 4, Dw2Inval, Dw2Inval
119cr5, Class=RegCR, 0, 5, Dw2Inval, Dw2Inval
120cr6, Class=RegCR, 0, 6, Dw2Inval, Dw2Inval
121cr7, Class=RegCR, 0, 7, Dw2Inval, Dw2Inval
122cr8, Class=RegCR, RegRex, 0, Dw2Inval, Dw2Inval
123cr9, Class=RegCR, RegRex, 1, Dw2Inval, Dw2Inval
124cr10, Class=RegCR, RegRex, 2, Dw2Inval, Dw2Inval
125cr11, Class=RegCR, RegRex, 3, Dw2Inval, Dw2Inval
126cr12, Class=RegCR, RegRex, 4, Dw2Inval, Dw2Inval
127cr13, Class=RegCR, RegRex, 5, Dw2Inval, Dw2Inval
128cr14, Class=RegCR, RegRex, 6, Dw2Inval, Dw2Inval
129cr15, Class=RegCR, RegRex, 7, Dw2Inval, Dw2Inval
40b8e679 130// Debug registers.
4a5c67ed
JB		 131db0, Class=RegDR, 0, 0, Dw2Inval, Dw2Inval
132db1, Class=RegDR, 0, 1, Dw2Inval, Dw2Inval
133db2, Class=RegDR, 0, 2, Dw2Inval, Dw2Inval
134db3, Class=RegDR, 0, 3, Dw2Inval, Dw2Inval
135db4, Class=RegDR, 0, 4, Dw2Inval, Dw2Inval
136db5, Class=RegDR, 0, 5, Dw2Inval, Dw2Inval
137db6, Class=RegDR, 0, 6, Dw2Inval, Dw2Inval
138db7, Class=RegDR, 0, 7, Dw2Inval, Dw2Inval
139db8, Class=RegDR, RegRex, 0, Dw2Inval, Dw2Inval
140db9, Class=RegDR, RegRex, 1, Dw2Inval, Dw2Inval
141db10, Class=RegDR, RegRex, 2, Dw2Inval, Dw2Inval
142db11, Class=RegDR, RegRex, 3, Dw2Inval, Dw2Inval
143db12, Class=RegDR, RegRex, 4, Dw2Inval, Dw2Inval
144db13, Class=RegDR, RegRex, 5, Dw2Inval, Dw2Inval
145db14, Class=RegDR, RegRex, 6, Dw2Inval, Dw2Inval
146db15, Class=RegDR, RegRex, 7, Dw2Inval, Dw2Inval
147dr0, Class=RegDR, 0, 0, Dw2Inval, Dw2Inval
148dr1, Class=RegDR, 0, 1, Dw2Inval, Dw2Inval
149dr2, Class=RegDR, 0, 2, Dw2Inval, Dw2Inval
150dr3, Class=RegDR, 0, 3, Dw2Inval, Dw2Inval
151dr4, Class=RegDR, 0, 4, Dw2Inval, Dw2Inval
152dr5, Class=RegDR, 0, 5, Dw2Inval, Dw2Inval
153dr6, Class=RegDR, 0, 6, Dw2Inval, Dw2Inval
154dr7, Class=RegDR, 0, 7, Dw2Inval, Dw2Inval
155dr8, Class=RegDR, RegRex, 0, Dw2Inval, Dw2Inval
156dr9, Class=RegDR, RegRex, 1, Dw2Inval, Dw2Inval
157dr10, Class=RegDR, RegRex, 2, Dw2Inval, Dw2Inval
158dr11, Class=RegDR, RegRex, 3, Dw2Inval, Dw2Inval
159dr12, Class=RegDR, RegRex, 4, Dw2Inval, Dw2Inval
160dr13, Class=RegDR, RegRex, 5, Dw2Inval, Dw2Inval
161dr14, Class=RegDR, RegRex, 6, Dw2Inval, Dw2Inval
162dr15, Class=RegDR, RegRex, 7, Dw2Inval, Dw2Inval
40b8e679 163// Test registers.
4a5c67ed
JB		 164tr0, Class=RegTR, 0, 0, Dw2Inval, Dw2Inval
165tr1, Class=RegTR, 0, 1, Dw2Inval, Dw2Inval
166tr2, Class=RegTR, 0, 2, Dw2Inval, Dw2Inval
167tr3, Class=RegTR, 0, 3, Dw2Inval, Dw2Inval
168tr4, Class=RegTR, 0, 4, Dw2Inval, Dw2Inval
169tr5, Class=RegTR, 0, 5, Dw2Inval, Dw2Inval
170tr6, Class=RegTR, 0, 6, Dw2Inval, Dw2Inval
171tr7, Class=RegTR, 0, 7, Dw2Inval, Dw2Inval
40b8e679 172// MMX and simd registers.
3528c362
JB		 173mm0, Class=RegMMX, 0, 0, 29, 41
174mm1, Class=RegMMX, 0, 1, 30, 42
175mm2, Class=RegMMX, 0, 2, 31, 43
176mm3, Class=RegMMX, 0, 3, 32, 44
177mm4, Class=RegMMX, 0, 4, 33, 45
178mm5, Class=RegMMX, 0, 5, 34, 46
179mm6, Class=RegMMX, 0, 6, 35, 47
180mm7, Class=RegMMX, 0, 7, 36, 48
75e5731b 181xmm0, Class=RegSIMD|Instance=Accum|Xmmword, 0, 0, 21, 17
3528c362
JB		 182xmm1, Class=RegSIMD|Xmmword, 0, 1, 22, 18
183xmm2, Class=RegSIMD|Xmmword, 0, 2, 23, 19
184xmm3, Class=RegSIMD|Xmmword, 0, 3, 24, 20
185xmm4, Class=RegSIMD|Xmmword, 0, 4, 25, 21
186xmm5, Class=RegSIMD|Xmmword, 0, 5, 26, 22
187xmm6, Class=RegSIMD|Xmmword, 0, 6, 27, 23
188xmm7, Class=RegSIMD|Xmmword, 0, 7, 28, 24
189xmm8, Class=RegSIMD|Xmmword, RegRex, 0, Dw2Inval, 25
190xmm9, Class=RegSIMD|Xmmword, RegRex, 1, Dw2Inval, 26
191xmm10, Class=RegSIMD|Xmmword, RegRex, 2, Dw2Inval, 27
192xmm11, Class=RegSIMD|Xmmword, RegRex, 3, Dw2Inval, 28
193xmm12, Class=RegSIMD|Xmmword, RegRex, 4, Dw2Inval, 29
194xmm13, Class=RegSIMD|Xmmword, RegRex, 5, Dw2Inval, 30
195xmm14, Class=RegSIMD|Xmmword, RegRex, 6, Dw2Inval, 31
196xmm15, Class=RegSIMD|Xmmword, RegRex, 7, Dw2Inval, 32
197xmm16, Class=RegSIMD|Xmmword, RegVRex, 0, Dw2Inval, 67
198xmm17, Class=RegSIMD|Xmmword, RegVRex, 1, Dw2Inval, 68
199xmm18, Class=RegSIMD|Xmmword, RegVRex, 2, Dw2Inval, 69
200xmm19, Class=RegSIMD|Xmmword, RegVRex, 3, Dw2Inval, 70
201xmm20, Class=RegSIMD|Xmmword, RegVRex, 4, Dw2Inval, 71
202xmm21, Class=RegSIMD|Xmmword, RegVRex, 5, Dw2Inval, 72
203xmm22, Class=RegSIMD|Xmmword, RegVRex, 6, Dw2Inval, 73
204xmm23, Class=RegSIMD|Xmmword, RegVRex, 7, Dw2Inval, 74
205xmm24, Class=RegSIMD|Xmmword, RegVRex|RegRex, 0, Dw2Inval, 75
206xmm25, Class=RegSIMD|Xmmword, RegVRex|RegRex, 1, Dw2Inval, 76
207xmm26, Class=RegSIMD|Xmmword, RegVRex|RegRex, 2, Dw2Inval, 77
208xmm27, Class=RegSIMD|Xmmword, RegVRex|RegRex, 3, Dw2Inval, 78
209xmm28, Class=RegSIMD|Xmmword, RegVRex|RegRex, 4, Dw2Inval, 79
210xmm29, Class=RegSIMD|Xmmword, RegVRex|RegRex, 5, Dw2Inval, 80
211xmm30, Class=RegSIMD|Xmmword, RegVRex|RegRex, 6, Dw2Inval, 81
212xmm31, Class=RegSIMD|Xmmword, RegVRex|RegRex, 7, Dw2Inval, 82
c0f3af97 213// AVX registers.
3528c362
JB		 214ymm0, Class=RegSIMD|Ymmword, 0, 0, Dw2Inval, Dw2Inval
215ymm1, Class=RegSIMD|Ymmword, 0, 1, Dw2Inval, Dw2Inval
216ymm2, Class=RegSIMD|Ymmword, 0, 2, Dw2Inval, Dw2Inval
217ymm3, Class=RegSIMD|Ymmword, 0, 3, Dw2Inval, Dw2Inval
218ymm4, Class=RegSIMD|Ymmword, 0, 4, Dw2Inval, Dw2Inval
219ymm5, Class=RegSIMD|Ymmword, 0, 5, Dw2Inval, Dw2Inval
220ymm6, Class=RegSIMD|Ymmword, 0, 6, Dw2Inval, Dw2Inval
221ymm7, Class=RegSIMD|Ymmword, 0, 7, Dw2Inval, Dw2Inval
222ymm8, Class=RegSIMD|Ymmword, RegRex, 0, Dw2Inval, Dw2Inval
223ymm9, Class=RegSIMD|Ymmword, RegRex, 1, Dw2Inval, Dw2Inval
224ymm10, Class=RegSIMD|Ymmword, RegRex, 2, Dw2Inval, Dw2Inval
225ymm11, Class=RegSIMD|Ymmword, RegRex, 3, Dw2Inval, Dw2Inval
226ymm12, Class=RegSIMD|Ymmword, RegRex, 4, Dw2Inval, Dw2Inval
227ymm13, Class=RegSIMD|Ymmword, RegRex, 5, Dw2Inval, Dw2Inval
228ymm14, Class=RegSIMD|Ymmword, RegRex, 6, Dw2Inval, Dw2Inval
229ymm15, Class=RegSIMD|Ymmword, RegRex, 7, Dw2Inval, Dw2Inval
230ymm16, Class=RegSIMD|Ymmword, RegVRex, 0, Dw2Inval, Dw2Inval
231ymm17, Class=RegSIMD|Ymmword, RegVRex, 1, Dw2Inval, Dw2Inval
232ymm18, Class=RegSIMD|Ymmword, RegVRex, 2, Dw2Inval, Dw2Inval
233ymm19, Class=RegSIMD|Ymmword, RegVRex, 3, Dw2Inval, Dw2Inval
234ymm20, Class=RegSIMD|Ymmword, RegVRex, 4, Dw2Inval, Dw2Inval
235ymm21, Class=RegSIMD|Ymmword, RegVRex, 5, Dw2Inval, Dw2Inval
236ymm22, Class=RegSIMD|Ymmword, RegVRex, 6, Dw2Inval, Dw2Inval
237ymm23, Class=RegSIMD|Ymmword, RegVRex, 7, Dw2Inval, Dw2Inval
238ymm24, Class=RegSIMD|Ymmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
239ymm25, Class=RegSIMD|Ymmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
240ymm26, Class=RegSIMD|Ymmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
241ymm27, Class=RegSIMD|Ymmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
242ymm28, Class=RegSIMD|Ymmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
243ymm29, Class=RegSIMD|Ymmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
244ymm30, Class=RegSIMD|Ymmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
245ymm31, Class=RegSIMD|Ymmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
43234a1e 246// AVX512 registers.
3528c362
JB		 247zmm0, Class=RegSIMD|Zmmword, 0, 0, Dw2Inval, Dw2Inval
248zmm1, Class=RegSIMD|Zmmword, 0, 1, Dw2Inval, Dw2Inval
249zmm2, Class=RegSIMD|Zmmword, 0, 2, Dw2Inval, Dw2Inval
250zmm3, Class=RegSIMD|Zmmword, 0, 3, Dw2Inval, Dw2Inval
251zmm4, Class=RegSIMD|Zmmword, 0, 4, Dw2Inval, Dw2Inval
252zmm5, Class=RegSIMD|Zmmword, 0, 5, Dw2Inval, Dw2Inval
253zmm6, Class=RegSIMD|Zmmword, 0, 6, Dw2Inval, Dw2Inval
254zmm7, Class=RegSIMD|Zmmword, 0, 7, Dw2Inval, Dw2Inval
255zmm8, Class=RegSIMD|Zmmword, RegRex, 0, Dw2Inval, Dw2Inval
256zmm9, Class=RegSIMD|Zmmword, RegRex, 1, Dw2Inval, Dw2Inval
257zmm10, Class=RegSIMD|Zmmword, RegRex, 2, Dw2Inval, Dw2Inval
258zmm11, Class=RegSIMD|Zmmword, RegRex, 3, Dw2Inval, Dw2Inval
259zmm12, Class=RegSIMD|Zmmword, RegRex, 4, Dw2Inval, Dw2Inval
260zmm13, Class=RegSIMD|Zmmword, RegRex, 5, Dw2Inval, Dw2Inval
261zmm14, Class=RegSIMD|Zmmword, RegRex, 6, Dw2Inval, Dw2Inval
262zmm15, Class=RegSIMD|Zmmword, RegRex, 7, Dw2Inval, Dw2Inval
263zmm16, Class=RegSIMD|Zmmword, RegVRex, 0, Dw2Inval, Dw2Inval
264zmm17, Class=RegSIMD|Zmmword, RegVRex, 1, Dw2Inval, Dw2Inval
265zmm18, Class=RegSIMD|Zmmword, RegVRex, 2, Dw2Inval, Dw2Inval
266zmm19, Class=RegSIMD|Zmmword, RegVRex, 3, Dw2Inval, Dw2Inval
267zmm20, Class=RegSIMD|Zmmword, RegVRex, 4, Dw2Inval, Dw2Inval
268zmm21, Class=RegSIMD|Zmmword, RegVRex, 5, Dw2Inval, Dw2Inval
269zmm22, Class=RegSIMD|Zmmword, RegVRex, 6, Dw2Inval, Dw2Inval
270zmm23, Class=RegSIMD|Zmmword, RegVRex, 7, Dw2Inval, Dw2Inval
271zmm24, Class=RegSIMD|Zmmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
272zmm25, Class=RegSIMD|Zmmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
273zmm26, Class=RegSIMD|Zmmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
274zmm27, Class=RegSIMD|Zmmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
275zmm28, Class=RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
276zmm29, Class=RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
277zmm30, Class=RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
278zmm31, Class=RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
260cd341
LC		 279// TMM registers for AMX
280tmm0, Class=RegSIMD|Tmmword, 0, 0, Dw2Inval, Dw2Inval
281tmm1, Class=RegSIMD|Tmmword, 0, 1, Dw2Inval, Dw2Inval
282tmm2, Class=RegSIMD|Tmmword, 0, 2, Dw2Inval, Dw2Inval
283tmm3, Class=RegSIMD|Tmmword, 0, 3, Dw2Inval, Dw2Inval
284tmm4, Class=RegSIMD|Tmmword, 0, 4, Dw2Inval, Dw2Inval
285tmm5, Class=RegSIMD|Tmmword, 0, 5, Dw2Inval, Dw2Inval
286tmm6, Class=RegSIMD|Tmmword, 0, 6, Dw2Inval, Dw2Inval
287tmm7, Class=RegSIMD|Tmmword, 0, 7, Dw2Inval, Dw2Inval
7e8b059b 288// Bound registers for MPX
f74a6307
JB		 289bnd0, Class=RegBND, 0, 0, Dw2Inval, Dw2Inval
290bnd1, Class=RegBND, 0, 1, Dw2Inval, Dw2Inval
291bnd2, Class=RegBND, 0, 2, Dw2Inval, Dw2Inval
292bnd3, Class=RegBND, 0, 3, Dw2Inval, Dw2Inval
bab6aec1 293// No Class=Reg will make these registers rejected for all purposes except
9a04903e 294// for addressing. This saves creating one extra type for RIP/EIP.
e968fc9b
JB		 295rip, Qword, RegRex64, RegIP, Dw2Inval, 16
296eip, Dword, RegRex64, RegIP, 8, Dw2Inval
bab6aec1 297// No Class=Reg will make these registers rejected for all purposes except
db51cc60 298// for addressing.
e968fc9b
JB		 299riz, Qword|BaseIndex, RegRex64, RegIZ, Dw2Inval, Dw2Inval
300eiz, Dword|BaseIndex, 0, RegIZ, Dw2Inval, Dw2Inval
6288d05f
JB		 301// fp regs. No need for an explicit st(0) here.
302st, Class=Reg|Instance=Accum|Tbyte, 0, 0, 11, 33
bab6aec1
JB		 303st(1), Class=Reg|Tbyte, 0, 1, 12, 34
304st(2), Class=Reg|Tbyte, 0, 2, 13, 35
305st(3), Class=Reg|Tbyte, 0, 3, 14, 36
306st(4), Class=Reg|Tbyte, 0, 4, 15, 37
307st(5), Class=Reg|Tbyte, 0, 5, 16, 38
308st(6), Class=Reg|Tbyte, 0, 6, 17, 39
309st(7), Class=Reg|Tbyte, 0, 7, 18, 40
a60de03c
JB		 310// Pseudo-register names only used in .cfi_* directives
311eflags, 0, 0, 0, 9, 49
312rflags, 0, 0, 0, Dw2Inval, 49
313fs.base, 0, 0, 0, Dw2Inval, 58
314gs.base, 0, 0, 0, Dw2Inval, 59
315tr, 0, 0, 0, 48, 62
316ldtr, 0, 0, 0, 49, 63
317// st0...7 for backward compatibility
318st0, 0, 0, 0, 11, 33
319st1, 0, 0, 1, 12, 34
320st2, 0, 0, 2, 13, 35
321st3, 0, 0, 3, 14, 36
322st4, 0, 0, 4, 15, 37
323st5, 0, 0, 5, 16, 38
324st6, 0, 0, 6, 17, 39
325st7, 0, 0, 7, 18, 40
326fcw, 0, 0, 0, 37, 65
327fsw, 0, 0, 0, 38, 66
328mxcsr, 0, 0, 0, 39, 64
GDB Binutils - Deliverables
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