[deliverable/binutils-gdb.git] / opcodes / i860-dis.c

/* Disassembler for the i860.
   Copyright 2000 Free Software Foundation, Inc.

   Contributed by Jason Eckhardt <jle@cygnus.com>.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#include "dis-asm.h"
#include "opcode/i860.h"

/* Later we should probably choose the prefix based on which OS flavor.  */
#define I860_REG_PREFIX "%"

/* Integer register names (encoded as 0..31 in the instruction).  */
static const char *const grnames[] = 
 {"r0",  "r1",  "sp",  "fp",  "r4",  "r5",  "r6",  "r7",
  "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"};

/* FP register names (encoded as 0..31 in the instruction).  */
static const char *const frnames[] = 
 {"f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
  "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};

/* Control/status register names (encoded as 0..5 in the instruction).  */
static const char *const crnames[] = 
 {"fir", "psr", "dirbase", "db", "fsr", "epsr", "", ""};


/* Prototypes.  */
static int sign_ext		PARAMS((unsigned int, int)); 
static void print_br_address	PARAMS((disassemble_info *, bfd_vma, long));


/* True if opcode is xor, xorh, and, andh, or, orh, andnot, andnoth.  */
#define BITWISE_OP(op)  ((op) == 0x30 || (op) == 0x31		\
			 || (op) == 0x34 || (op) == 0x35	\
			 || (op) == 0x38 || (op) == 0x39	\
			 || (op) == 0x3c || (op) == 0x3d	\
			 || (op) == 0x33 || (op) == 0x37	\
			 || (op) == 0x3b || (op) == 0x3f)


/* Sign extend N-bit number.  */
static int
sign_ext (x, n)
     unsigned int x;
     int n;
{
  int t;
  t = x >> (n - 1);
  t = ((-t) << n) | x;
  return t;
}


/* Print a PC-relative branch offset.  VAL is the sign extended value
   from the branch instruction.  */
static void
print_br_address (info, memaddr, val)
     disassemble_info *info;
     bfd_vma memaddr;
     long val;
{

  long adj = (long)memaddr + 4 + (val << 2);

  (*info->fprintf_func) (info->stream, "0x%08x", adj);
	    
  /* Attempt to obtain a symbol for the target address.  */
	
  if (info->print_address_func && adj != 0)
    {
      (*info->fprintf_func) (info->stream, "\t// ");
      (*info->print_address_func) (adj, info);
    }
}


/* Print one instruction.  */
int
print_insn_i860 (memaddr, info)
     bfd_vma memaddr;
     disassemble_info *info;
{
  bfd_byte buff[4];
  unsigned int insn, i;
  int status;
  const struct i860_opcode *opcode = 0;

  status = (*info->read_memory_func) (memaddr, buff, sizeof (buff), info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, memaddr, info);
      return -1;
    }

  /* Note that i860 instructions are always accessed as little endian
     data, regardless of the endian mode of the i860.  */
  insn = bfd_getl32 (buff);

  status = 0;
  i = 0;
  while (i860_opcodes[i].name != NULL)
    {
      opcode = &i860_opcodes[i];
      if ((insn & opcode->match) == opcode->match
	  && (insn & opcode->lose) == 0)
	{
	  status = 1;
	  break;
	}
      ++i;
    }

  if (status == 0)
    {
      /* Instruction not in opcode table.  */
      (*info->fprintf_func) (info->stream, ".long %#08x", insn);
    }
  else
    {
      const char *s;
      int val;

      /* If this a flop (or a shrd) and its dual bit is set,
         prefix with 'd.'.  */ 	
      if (((insn & 0xfc000000) == 0x48000000
           || (insn & 0xfc000000) == 0xb0000000)
          && (insn & 0x200))
	(*info->fprintf_func) (info->stream, "d.%s\t", opcode->name);
      else
	(*info->fprintf_func) (info->stream, "%s\t", opcode->name);

      for (s = opcode->args; *s; s++)
	{
	  switch (*s)
	    {
	    /* Integer register (src1).  */
	    case '1':
	      (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
				     grnames[(insn >> 11) & 0x1f]);
	      break;

	    /* Integer register (src2).  */
	    case '2':
	      (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
				     grnames[(insn >> 21) & 0x1f]);
	      break;

	    /* Integer destination register.  */
	    case 'd':
	      (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
				     grnames[(insn >> 16) & 0x1f]);
	      break;

	    /* Floating-point register (src1).  */
	    case 'e':
	      (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
				     frnames[(insn >> 11) & 0x1f]);
	      break;

	    /* Floating-point register (src2).  */
	    case 'f':
	      (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
				     frnames[(insn >> 21) & 0x1f]);
	      break;

	    /* Floating-point destination register.  */
	    case 'g':
	      (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
				     frnames[(insn >> 16) & 0x1f]);
	      break;

	    /* Control register.  */
	    case 'c':
	      (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
				     crnames[(insn >> 21) & 0x7]);
	      break;

	    /* 16-bit immediate (sign extend, except for bitwise ops).  */
	    case 'i':
	      if (BITWISE_OP ((insn & 0xfc000000) >> 26))
		(*info->fprintf_func) (info->stream, "0x%04x",
				       (unsigned int) (insn & 0xffff));
	      else
		(*info->fprintf_func) (info->stream, "%d",
				       sign_ext ((insn & 0xffff), 16));
	      break;

	    /* 16-bit immediate, aligned (2^0, ld.b).  */
	    case 'I':
	      (*info->fprintf_func) (info->stream, "%d",
				     sign_ext ((insn & 0xffff), 16));
	      break;

	    /* 16-bit immediate, aligned (2^1, ld.s).  */
	    case 'J':
	      (*info->fprintf_func) (info->stream, "%d",
				     sign_ext ((insn & 0xfffe), 16));
	      break;

	    /* 16-bit immediate, aligned (2^2, ld.l, {p}fld.l, fst.l).  */
	    case 'K':
	      (*info->fprintf_func) (info->stream, "%d",
				     sign_ext ((insn & 0xfffc), 16));
	      break;

	    /* 16-bit immediate, aligned (2^3, {p}fld.d, fst.d).  */
	    case 'L':
	      (*info->fprintf_func) (info->stream, "%d",
				     sign_ext ((insn & 0xfff8), 16));
	      break;

	    /* 16-bit immediate, aligned (2^4, {p}fld.q, fst.q).  */
	    case 'M':
	      (*info->fprintf_func) (info->stream, "%d",
				     sign_ext ((insn & 0xfff0), 16));
	      break;

	    /* 5-bit immediate (zero extend).  */
	    case '5':
	      (*info->fprintf_func) (info->stream, "%d",
				     ((insn >> 11) & 0x1f));
	      break;

	    /* Split 16 bit immediate (20..16:10..0).  */
	    case 's':
	      val = ((insn >> 5) & 0xf800) | (insn & 0x07ff);
	      (*info->fprintf_func) (info->stream, "%d",
				     sign_ext (val, 16));
	      break;

	    /* Split 16 bit immediate, aligned. (2^0, st.b).  */
	    case 'S':
	      val = ((insn >> 5) & 0xf800) | (insn & 0x07ff);
	      (*info->fprintf_func) (info->stream, "%d",
				     sign_ext (val, 16));
	      break;

	    /* Split 16 bit immediate, aligned. (2^1, st.s).  */
	    case 'T':
	      val = ((insn >> 5) & 0xf800) | (insn & 0x07fe);
	      (*info->fprintf_func) (info->stream, "%d",
				     sign_ext (val, 16));
	      break;

	    /* Split 16 bit immediate, aligned. (2^2, st.l).  */
	    case 'U':
	      val = ((insn >> 5) & 0xf800) | (insn & 0x07fc);
	      (*info->fprintf_func) (info->stream, "%d",
				     sign_ext (val, 16));
	      break;

	    /* 26-bit PC relative immediate (lbroff).  */
	    case 'l':
	      val = sign_ext ((insn & 0x03ffffff), 26);
	      print_br_address (info, memaddr, val);
	      break;

	    /* 16-bit PC relative immediate (sbroff).  */
	    case 'r':
	      val = sign_ext ((((insn >> 5) & 0xf800) | (insn & 0x07ff)), 16);
	      print_br_address (info, memaddr, val);
	      break;

	    default:
	      (*info->fprintf_func) (info->stream, "%c", *s);
	      break;
	    }
	}
    }

  return sizeof (insn);
}
Commit	Line	Data
9d751335 JE	1	/* Disassembler for the i860.
	2	Copyright 2000 Free Software Foundation, Inc.
	3
	4	Contributed by Jason Eckhardt <jle@cygnus.com>.
	5
	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
	8	the Free Software Foundation; either version 2 of the License, or
	9	(at your option) any later version.
	10
	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
	17	along with this program; if not, write to the Free Software
	18	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	19
	20	#include "dis-asm.h"
	21	#include "opcode/i860.h"
	22
	23	/* Later we should probably choose the prefix based on which OS flavor. */
	24	#define I860_REG_PREFIX "%"
	25
	26	/* Integer register names (encoded as 0..31 in the instruction). */
	27	static const char *const grnames[] =
	28	{"r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7",
	29	"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
	30	"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
	31	"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"};
	32
	33	/* FP register names (encoded as 0..31 in the instruction). */
	34	static const char *const frnames[] =
	35	{"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
	36	"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
	37	"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
	38	"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};
	39
	40	/* Control/status register names (encoded as 0..5 in the instruction). */
	41	static const char *const crnames[] =
	42	{"fir", "psr", "dirbase", "db", "fsr", "epsr", "", ""};
	43
	44
	45	/* Prototypes. */
	46	static int sign_ext PARAMS((unsigned int, int));
305d537e	47	static void print_br_address PARAMS((disassemble_info *, bfd_vma, long));
9d751335 JE	48
	49
	50	/* True if opcode is xor, xorh, and, andh, or, orh, andnot, andnoth. */
	51	#define BITWISE_OP(op) ((op) == 0x30 \|\| (op) == 0x31 \
	52	\|\| (op) == 0x34 \|\| (op) == 0x35 \
	53	\|\| (op) == 0x38 \|\| (op) == 0x39 \
	54	\|\| (op) == 0x3c \|\| (op) == 0x3d \
	55	\|\| (op) == 0x33 \|\| (op) == 0x37 \
	56	\|\| (op) == 0x3b \|\| (op) == 0x3f)
	57
	58
	59	/* Sign extend N-bit number. */
	60	static int
	61	sign_ext (x, n)
	62	unsigned int x;
	63	int n;
	64	{
	65	int t;
	66	t = x >> (n - 1);
	67	t = ((-t) << n) \| x;
	68	return t;
	69	}
	70
	71
	72	/* Print a PC-relative branch offset. VAL is the sign extended value
	73	from the branch instruction. */
	74	static void
	75	print_br_address (info, memaddr, val)
	76	disassemble_info *info;
	77	bfd_vma memaddr;
305d537e	78	long val;
9d751335 JE	79	{
9d751335 JE	80
305d537e	81	long adj = (long)memaddr + 4 + (val << 2);
9d751335 JE	82
	83	(*info->fprintf_func) (info->stream, "0x%08x", adj);
	84
	85	/* Attempt to obtain a symbol for the target address. */
	86
	87	if (info->print_address_func && adj != 0)
	88	{
	89	(*info->fprintf_func) (info->stream, "\t// ");
	90	(*info->print_address_func) (adj, info);
	91	}
	92	}
	93
	94
	95	/* Print one instruction. */
	96	int
	97	print_insn_i860 (memaddr, info)
	98	bfd_vma memaddr;
	99	disassemble_info *info;
	100	{
	101	bfd_byte buff[4];
	102	unsigned int insn, i;
	103	int status;
	104	const struct i860_opcode *opcode = 0;
	105
	106	status = (*info->read_memory_func) (memaddr, buff, sizeof (buff), info);
	107	if (status != 0)
	108	{
	109	(*info->memory_error_func) (status, memaddr, info);
	110	return -1;
	111	}
	112
	113	/* Note that i860 instructions are always accessed as little endian
	114	data, regardless of the endian mode of the i860. */
	115	insn = bfd_getl32 (buff);
	116
	117	status = 0;
	118	i = 0;
	119	while (i860_opcodes[i].name != NULL)
	120	{
	121	opcode = &i860_opcodes[i];
	122	if ((insn & opcode->match) == opcode->match
	123	&& (insn & opcode->lose) == 0)
	124	{
	125	status = 1;
	126	break;
	127	}
	128	++i;
	129	}
	130
	131	if (status == 0)
	132	{
	133	/* Instruction not in opcode table. */
	134	(*info->fprintf_func) (info->stream, ".long %#08x", insn);
	135	}
	136	else
	137	{
	138	const char *s;
	139	int val;
	140
b645cb17 JE	141	/* If this a flop (or a shrd) and its dual bit is set,
	142	prefix with 'd.'. */
	143	if (((insn & 0xfc000000) == 0x48000000
	144	\|\| (insn & 0xfc000000) == 0xb0000000)
	145	&& (insn & 0x200))
9d751335 JE	146	(*info->fprintf_func) (info->stream, "d.%s\t", opcode->name);
	147	else
	148	(*info->fprintf_func) (info->stream, "%s\t", opcode->name);
	149
	150	for (s = opcode->args; *s; s++)
	151	{
	152	switch (*s)
	153	{
	154	/* Integer register (src1). */
	155	case '1':
	156	(*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
	157	grnames[(insn >> 11) & 0x1f]);
	158	break;
	159
	160	/* Integer register (src2). */
	161	case '2':
	162	(*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
	163	grnames[(insn >> 21) & 0x1f]);
	164	break;
	165
	166	/* Integer destination register. */
	167	case 'd':
	168	(*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
	169	grnames[(insn >> 16) & 0x1f]);
	170	break;
	171
	172	/* Floating-point register (src1). */
	173	case 'e':
	174	(*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
	175	frnames[(insn >> 11) & 0x1f]);
	176	break;
	177
	178	/* Floating-point register (src2). */
	179	case 'f':
	180	(*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
	181	frnames[(insn >> 21) & 0x1f]);
	182	break;
	183
	184	/* Floating-point destination register. */
	185	case 'g':
	186	(*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
	187	frnames[(insn >> 16) & 0x1f]);
	188	break;
	189
	190	/* Control register. */
	191	case 'c':
	192	(*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
	193	crnames[(insn >> 21) & 0x7]);
	194	break;
	195
	196	/* 16-bit immediate (sign extend, except for bitwise ops). */
	197	case 'i':
	198	if (BITWISE_OP ((insn & 0xfc000000) >> 26))
	199	(*info->fprintf_func) (info->stream, "0x%04x",
	200	(unsigned int) (insn & 0xffff));
	201	else
	202	(*info->fprintf_func) (info->stream, "%d",
	203	sign_ext ((insn & 0xffff), 16));
	204	break;
	205
	206	/* 16-bit immediate, aligned (2^0, ld.b). */
	207	case 'I':
	208	(*info->fprintf_func) (info->stream, "%d",
	209	sign_ext ((insn & 0xffff), 16));
210	break;
211
212	/* 16-bit immediate, aligned (2^1, ld.s). */
213	case 'J':
214	(*info->fprintf_func) (info->stream, "%d",
215	sign_ext ((insn & 0xfffe), 16));
216	break;
217
218	/* 16-bit immediate, aligned (2^2, ld.l, {p}fld.l, fst.l). */
219	case 'K':
220	(*info->fprintf_func) (info->stream, "%d",
221	sign_ext ((insn & 0xfffc), 16));
222	break;
223
224	/* 16-bit immediate, aligned (2^3, {p}fld.d, fst.d). */
225	case 'L':
226	(*info->fprintf_func) (info->stream, "%d",
227	sign_ext ((insn & 0xfff8), 16));
228	break;
229
230	/* 16-bit immediate, aligned (2^4, {p}fld.q, fst.q). */
231	case 'M':
232	(*info->fprintf_func) (info->stream, "%d",
233	sign_ext ((insn & 0xfff0), 16));
234	break;
235
236	/* 5-bit immediate (zero extend). */
237	case '5':
238	(*info->fprintf_func) (info->stream, "%d",
239	((insn >> 11) & 0x1f));
240	break;
241
242	/* Split 16 bit immediate (20..16:10..0). */
243	case 's':
244	val = ((insn >> 5) & 0xf800) \| (insn & 0x07ff);
245	(*info->fprintf_func) (info->stream, "%d",
246	sign_ext (val, 16));
247	break;
248
249	/* Split 16 bit immediate, aligned. (2^0, st.b). */
250	case 'S':
251	val = ((insn >> 5) & 0xf800) \| (insn & 0x07ff);
252	(*info->fprintf_func) (info->stream, "%d",
253	sign_ext (val, 16));
254	break;
255
256	/* Split 16 bit immediate, aligned. (2^1, st.s). */
257	case 'T':
258	val = ((insn >> 5) & 0xf800) \| (insn & 0x07fe);
259	(*info->fprintf_func) (info->stream, "%d",
260	sign_ext (val, 16));
261	break;
262
263	/* Split 16 bit immediate, aligned. (2^2, st.l). */
264	case 'U':
265	val = ((insn >> 5) & 0xf800) \| (insn & 0x07fc);
266	(*info->fprintf_func) (info->stream, "%d",
267	sign_ext (val, 16));
268	break;
269
270	/* 26-bit PC relative immediate (lbroff). */
271	case 'l':
272	val = sign_ext ((insn & 0x03ffffff), 26);
273	print_br_address (info, memaddr, val);
274	break;
275
276	/* 16-bit PC relative immediate (sbroff). */
277	case 'r':
278	val = sign_ext ((((insn >> 5) & 0xf800) \| (insn & 0x07ff)), 16);
279	print_br_address (info, memaddr, val);
280	break;
281
282	default:
283	(info->fprintf_func) (info->stream, "%c", s);
284	break;
285	}
286	}
287	}
288
289	return sizeof (insn);
290	}
291