Change source files over to GPLv3.

[deliverable/binutils-gdb.git] / opcodes / ia64-asmtab.c

/* This file is automatically generated by ia64-gen.  Do not edit!  */
/* Copyright 2007  Free Software Foundation, Inc.

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; see the file COPYING.  If not, write to the
   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
   02110-1301, USA.  */
static const char * const ia64_strings[] = {
  "", "0", "1", "a", "acq", "add", "addl", "addp4", "adds", "alloc", "and",
  "andcm", "b", "bias", "br", "break", "brl", "brp", "bsw", "c", "call",
  "cexit", "chk", "cloop", "clr", "clrrrb", "cmp", "cmp4", "cmp8xchg16",
  "cmpxchg1", "cmpxchg2", "cmpxchg4", "cmpxchg8", "cond", "cover", "ctop",
  "czx1", "czx2", "d", "dep", "dpnt", "dptk", "e", "epc", "eq", "excl",
  "exit", "exp", "extr", "f", "fabs", "fadd", "famax", "famin", "fand",
  "fandcm", "fault", "fc", "fchkf", "fclass", "fclrf", "fcmp", "fcvt",
  "fetchadd4", "fetchadd8", "few", "fill", "flushrs", "fma", "fmax",
  "fmerge", "fmin", "fmix", "fmpy", "fms", "fneg", "fnegabs", "fnma",
  "fnmpy", "fnorm", "for", "fpabs", "fpack", "fpamax", "fpamin", "fpcmp",
  "fpcvt", "fpma", "fpmax", "fpmerge", "fpmin", "fpmpy", "fpms", "fpneg",
  "fpnegabs", "fpnma", "fpnmpy", "fprcpa", "fprsqrta", "frcpa", "frsqrta",
  "fselect", "fsetc", "fsub", "fswap", "fsxt", "fwb", "fx", "fxor", "fxu",
  "g", "ga", "ge", "getf", "geu", "gt", "gtu", "h", "hint", "hu", "i", "ia",
  "imp", "invala", "itc", "itr", "l", "ld1", "ld16", "ld2", "ld4", "ld8",
  "ldf", "ldf8", "ldfd", "ldfe", "ldfp8", "ldfpd", "ldfps", "ldfs", "le",
  "leu", "lfetch", "loadrs", "loop", "lr", "lt", "ltu", "lu", "m", "many",
  "mf", "mix1", "mix2", "mix4", "mov", "movl", "mux1", "mux2", "nc", "ne",
  "neq", "nge", "ngt", "nl", "nle", "nlt", "nm", "nop", "nr", "ns", "nt1",
  "nt2", "nta", "nz", "or", "orcm", "ord", "pack2", "pack4", "padd1",
  "padd2", "padd4", "pavg1", "pavg2", "pavgsub1", "pavgsub2", "pcmp1",
  "pcmp2", "pcmp4", "pmax1", "pmax2", "pmin1", "pmin2", "pmpy2", "pmpyshr2",
  "popcnt", "pr", "probe", "psad1", "pshl2", "pshl4", "pshladd2", "pshr2",
  "pshr4", "pshradd2", "psub1", "psub2", "psub4", "ptc", "ptr", "r", "raz",
  "rel", "ret", "rfi", "rsm", "rum", "rw", "s", "s0", "s1", "s2", "s3",
  "sa", "se", "setf", "shl", "shladd", "shladdp4", "shr", "shrp", "sig",
  "spill", "spnt", "sptk", "srlz", "ssm", "sss", "st1", "st16", "st2",
  "st4", "st8", "stf", "stf8", "stfd", "stfe", "stfs", "sub", "sum", "sxt1",
  "sxt2", "sxt4", "sync", "tak", "tbit", "tf", "thash", "tnat", "tpa",
  "trunc", "ttag", "u", "unc", "unord", "unpack1", "unpack2", "unpack4",
  "uss", "uus", "uuu", "vmsw", "w", "wexit", "wtop", "x", "xchg1", "xchg2",
  "xchg4", "xchg8", "xf", "xma", "xmpy", "xor", "xuf", "z", "zxt1", "zxt2",
  "zxt4",
};

static const struct ia64_dependency
dependencies[] = {
  { "ALAT", 0, 0, 0, -1, NULL, },
  { "AR[BSP]", 26, 0, 2, 17, NULL, },
  { "AR[BSPSTORE]", 26, 0, 2, 18, NULL, },
  { "AR[CCV]", 26, 0, 2, 32, NULL, },
  { "AR[CFLG]", 26, 0, 2, 27, NULL, },
  { "AR[CSD]", 26, 0, 2, 25, NULL, },
  { "AR[EC]", 26, 0, 2, 66, NULL, },
  { "AR[EFLAG]", 26, 0, 2, 24, NULL, },
  { "AR[FCR]", 26, 0, 2, 21, NULL, },
  { "AR[FDR]", 26, 0, 2, 30, NULL, },
  { "AR[FIR]", 26, 0, 2, 29, NULL, },
  { "AR[FPSR].sf0.controls", 30, 0, 2, -1, NULL, },
  { "AR[FPSR].sf1.controls", 30, 0, 2, -1, NULL, },
  { "AR[FPSR].sf2.controls", 30, 0, 2, -1, NULL, },
  { "AR[FPSR].sf3.controls", 30, 0, 2, -1, NULL, },
  { "AR[FPSR].sf0.flags", 30, 0, 2, -1, NULL, },
  { "AR[FPSR].sf1.flags", 30, 0, 2, -1, NULL, },
  { "AR[FPSR].sf2.flags", 30, 0, 2, -1, NULL, },
  { "AR[FPSR].sf3.flags", 30, 0, 2, -1, NULL, },
  { "AR[FPSR].traps", 30, 0, 2, -1, NULL, },
  { "AR[FPSR].rv", 30, 0, 2, -1, NULL, },
  { "AR[FSR]", 26, 0, 2, 28, NULL, },
  { "AR[ITC]", 26, 0, 2, 44, NULL, },
  { "AR[K%], % in 0 - 7", 1, 0, 2, -1, NULL, },
  { "AR[LC]", 26, 0, 2, 65, NULL, },
  { "AR[PFS]", 26, 0, 2, 64, NULL, },
  { "AR[PFS]", 26, 0, 2, 64, NULL, },
  { "AR[PFS]", 26, 0, 0, 64, NULL, },
  { "AR[RNAT]", 26, 0, 2, 19, NULL, },
  { "AR[RSC]", 26, 0, 2, 16, NULL, },
  { "AR[SSD]", 26, 0, 2, 26, NULL, },
  { "AR[UNAT]{%}, % in 0 - 63", 2, 0, 2, -1, NULL, },
  { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 0, 0, -1, NULL, },
  { "AR%, % in 48-63, 112-127", 4, 0, 2, -1, NULL, },
  { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, },
  { "BR%, % in 0 - 7", 5, 0, 0, -1, NULL, },
  { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, },
  { "CFM", 6, 0, 2, -1, NULL, },
  { "CFM", 6, 0, 2, -1, NULL, },
  { "CFM", 6, 0, 2, -1, NULL, },
  { "CFM", 6, 0, 2, -1, NULL, },
  { "CFM", 6, 0, 0, -1, NULL, },
  { "CPUID#", 7, 0, 5, -1, NULL, },
  { "CR[CMCV]", 27, 0, 3, 74, NULL, },
  { "CR[DCR]", 27, 0, 3, 0, NULL, },