Commit | Line | Data |
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252b5132 RH |
1 | /* CPU data for m32r. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
060d22b0 | 5 | Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. |
252b5132 RH |
6 | |
7 | This file is part of the GNU Binutils and/or GDB, the GNU debugger. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License along | |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
22 | ||
23 | */ | |
24 | ||
25 | #include "sysdep.h" | |
252b5132 RH |
26 | #include <stdio.h> |
27 | #include <stdarg.h> | |
28 | #include "ansidecl.h" | |
29 | #include "bfd.h" | |
30 | #include "symcat.h" | |
31 | #include "m32r-desc.h" | |
32 | #include "m32r-opc.h" | |
33 | #include "opintl.h" | |
6bb95a0f | 34 | #include "libiberty.h" |
252b5132 | 35 | |
fc05c67f NC |
36 | static void init_tables PARAMS ((void)); |
37 | static const CGEN_MACH * lookup_mach_via_bfd_name PARAMS ((const CGEN_MACH *, const char *)); | |
38 | static void build_hw_table PARAMS ((CGEN_CPU_TABLE *)); | |
39 | static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *)); | |
40 | static void build_operand_table PARAMS ((CGEN_CPU_TABLE *)); | |
41 | static void build_insn_table PARAMS ((CGEN_CPU_TABLE *)); | |
42 | static void m32r_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *)); | |
252b5132 RH |
43 | /* Attributes. */ |
44 | ||
45 | static const CGEN_ATTR_ENTRY bool_attr[] = | |
46 | { | |
47 | { "#f", 0 }, | |
48 | { "#t", 1 }, | |
49 | { 0, 0 } | |
50 | }; | |
51 | ||
52 | static const CGEN_ATTR_ENTRY MACH_attr[] = | |
53 | { | |
54 | { "base", MACH_BASE }, | |
55 | { "m32r", MACH_M32R }, | |
1fa60b5d | 56 | { "m32rx", MACH_M32RX }, |
252b5132 RH |
57 | { "max", MACH_MAX }, |
58 | { 0, 0 } | |
59 | }; | |
60 | ||
61 | static const CGEN_ATTR_ENTRY ISA_attr[] = | |
62 | { | |
63 | { "m32r", ISA_M32R }, | |
64 | { "max", ISA_MAX }, | |
65 | { 0, 0 } | |
66 | }; | |
67 | ||
1fa60b5d DE |
68 | static const CGEN_ATTR_ENTRY PIPE_attr[] = |
69 | { | |
70 | { "NONE", PIPE_NONE }, | |
71 | { "O", PIPE_O }, | |
72 | { "S", PIPE_S }, | |
73 | { "OS", PIPE_OS }, | |
74 | { 0, 0 } | |
75 | }; | |
76 | ||
252b5132 RH |
77 | const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] = |
78 | { | |
6bb95a0f | 79 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, |
252b5132 RH |
80 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, |
81 | { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, | |
82 | { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, | |
83 | { "RESERVED", &bool_attr[0], &bool_attr[0] }, | |
84 | { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, | |
85 | { "SIGNED", &bool_attr[0], &bool_attr[0] }, | |
86 | { "RELOC", &bool_attr[0], &bool_attr[0] }, | |
87 | { 0, 0, 0 } | |
88 | }; | |
89 | ||
90 | const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] = | |
91 | { | |
6bb95a0f | 92 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, |
252b5132 RH |
93 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, |
94 | { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, | |
95 | { "PC", &bool_attr[0], &bool_attr[0] }, | |
96 | { "PROFILE", &bool_attr[0], &bool_attr[0] }, | |
97 | { 0, 0, 0 } | |
98 | }; | |
99 | ||
100 | const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] = | |
101 | { | |
6bb95a0f | 102 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, |
252b5132 RH |
103 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, |
104 | { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, | |
105 | { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, | |
106 | { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, | |
107 | { "SIGNED", &bool_attr[0], &bool_attr[0] }, | |
108 | { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, | |
109 | { "RELAX", &bool_attr[0], &bool_attr[0] }, | |
110 | { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, | |
111 | { "RELOC", &bool_attr[0], &bool_attr[0] }, | |
112 | { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] }, | |
113 | { 0, 0, 0 } | |
114 | }; | |
115 | ||
116 | const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] = | |
117 | { | |
6bb95a0f DB |
118 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, |
119 | { "PIPE", & PIPE_attr[0], & PIPE_attr[0] }, | |
252b5132 RH |
120 | { "ALIAS", &bool_attr[0], &bool_attr[0] }, |
121 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, | |
122 | { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, | |
123 | { "COND-CTI", &bool_attr[0], &bool_attr[0] }, | |
124 | { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, | |
125 | { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, | |
126 | { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, | |
127 | { "RELAX", &bool_attr[0], &bool_attr[0] }, | |
128 | { "NO-DIS", &bool_attr[0], &bool_attr[0] }, | |
129 | { "PBB", &bool_attr[0], &bool_attr[0] }, | |
130 | { "FILL-SLOT", &bool_attr[0], &bool_attr[0] }, | |
1fa60b5d | 131 | { "SPECIAL", &bool_attr[0], &bool_attr[0] }, |
252b5132 RH |
132 | { 0, 0, 0 } |
133 | }; | |
134 | ||
135 | /* Instruction set variants. */ | |
136 | ||
137 | static const CGEN_ISA m32r_cgen_isa_table[] = { | |
6bb95a0f DB |
138 | { "m32r", 32, 32, 16, 32 }, |
139 | { 0, 0, 0, 0, 0 } | |
252b5132 RH |
140 | }; |
141 | ||
142 | /* Machine variants. */ | |
143 | ||
144 | static const CGEN_MACH m32r_cgen_mach_table[] = { | |
fc7bc883 RH |
145 | { "m32r", "m32r", MACH_M32R, 0 }, |
146 | { "m32rx", "m32rx", MACH_M32RX, 0 }, | |
147 | { 0, 0, 0, 0 } | |
252b5132 RH |
148 | }; |
149 | ||
150 | static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] = | |
151 | { | |
6bb95a0f DB |
152 | { "fp", 13, {0, {0}}, 0, 0 }, |
153 | { "lr", 14, {0, {0}}, 0, 0 }, | |
154 | { "sp", 15, {0, {0}}, 0, 0 }, | |
155 | { "r0", 0, {0, {0}}, 0, 0 }, | |
156 | { "r1", 1, {0, {0}}, 0, 0 }, | |
157 | { "r2", 2, {0, {0}}, 0, 0 }, | |
158 | { "r3", 3, {0, {0}}, 0, 0 }, | |
159 | { "r4", 4, {0, {0}}, 0, 0 }, | |
160 | { "r5", 5, {0, {0}}, 0, 0 }, | |
161 | { "r6", 6, {0, {0}}, 0, 0 }, | |
162 | { "r7", 7, {0, {0}}, 0, 0 }, | |
163 | { "r8", 8, {0, {0}}, 0, 0 }, | |
164 | { "r9", 9, {0, {0}}, 0, 0 }, | |
165 | { "r10", 10, {0, {0}}, 0, 0 }, | |
166 | { "r11", 11, {0, {0}}, 0, 0 }, | |
167 | { "r12", 12, {0, {0}}, 0, 0 }, | |
168 | { "r13", 13, {0, {0}}, 0, 0 }, | |
169 | { "r14", 14, {0, {0}}, 0, 0 }, | |
170 | { "r15", 15, {0, {0}}, 0, 0 } | |
252b5132 RH |
171 | }; |
172 | ||
173 | CGEN_KEYWORD m32r_cgen_opval_gr_names = | |
174 | { | |
175 | & m32r_cgen_opval_gr_names_entries[0], | |
6bb95a0f | 176 | 19, |
fc7bc883 | 177 | 0, 0, 0, 0, "" |
252b5132 RH |
178 | }; |
179 | ||
180 | static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] = | |
181 | { | |
6bb95a0f DB |
182 | { "psw", 0, {0, {0}}, 0, 0 }, |
183 | { "cbr", 1, {0, {0}}, 0, 0 }, | |
184 | { "spi", 2, {0, {0}}, 0, 0 }, | |
185 | { "spu", 3, {0, {0}}, 0, 0 }, | |
186 | { "bpc", 6, {0, {0}}, 0, 0 }, | |
187 | { "bbpsw", 8, {0, {0}}, 0, 0 }, | |
188 | { "bbpc", 14, {0, {0}}, 0, 0 }, | |
189 | { "cr0", 0, {0, {0}}, 0, 0 }, | |
190 | { "cr1", 1, {0, {0}}, 0, 0 }, | |
191 | { "cr2", 2, {0, {0}}, 0, 0 }, | |
192 | { "cr3", 3, {0, {0}}, 0, 0 }, | |
193 | { "cr4", 4, {0, {0}}, 0, 0 }, | |
194 | { "cr5", 5, {0, {0}}, 0, 0 }, | |
195 | { "cr6", 6, {0, {0}}, 0, 0 }, | |
196 | { "cr7", 7, {0, {0}}, 0, 0 }, | |
197 | { "cr8", 8, {0, {0}}, 0, 0 }, | |
198 | { "cr9", 9, {0, {0}}, 0, 0 }, | |
199 | { "cr10", 10, {0, {0}}, 0, 0 }, | |
200 | { "cr11", 11, {0, {0}}, 0, 0 }, | |
201 | { "cr12", 12, {0, {0}}, 0, 0 }, | |
202 | { "cr13", 13, {0, {0}}, 0, 0 }, | |
203 | { "cr14", 14, {0, {0}}, 0, 0 }, | |
204 | { "cr15", 15, {0, {0}}, 0, 0 } | |
252b5132 RH |
205 | }; |
206 | ||
207 | CGEN_KEYWORD m32r_cgen_opval_cr_names = | |
208 | { | |
209 | & m32r_cgen_opval_cr_names_entries[0], | |
6bb95a0f | 210 | 23, |
fc7bc883 | 211 | 0, 0, 0, 0, "" |
252b5132 RH |
212 | }; |
213 | ||
1fa60b5d DE |
214 | static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] = |
215 | { | |
6bb95a0f DB |
216 | { "a0", 0, {0, {0}}, 0, 0 }, |
217 | { "a1", 1, {0, {0}}, 0, 0 } | |
1fa60b5d DE |
218 | }; |
219 | ||
220 | CGEN_KEYWORD m32r_cgen_opval_h_accums = | |
221 | { | |
222 | & m32r_cgen_opval_h_accums_entries[0], | |
6bb95a0f | 223 | 2, |
fc7bc883 | 224 | 0, 0, 0, 0, "" |
1fa60b5d DE |
225 | }; |
226 | ||
252b5132 | 227 | |
252b5132 RH |
228 | /* The hardware table. */ |
229 | ||
b3466c39 DB |
230 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) |
231 | #define A(a) (1 << CGEN_HW_##a) | |
232 | #else | |
233 | #define A(a) (1 << CGEN_HW_/**/a) | |
234 | #endif | |
252b5132 RH |
235 | |
236 | const CGEN_HW_ENTRY m32r_cgen_hw_table[] = | |
237 | { | |
238 | { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, | |
239 | { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, | |
240 | { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, | |
241 | { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, | |
242 | { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, | |
243 | { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } }, | |
244 | { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, | |
245 | { "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, | |
246 | { "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, | |
247 | { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } }, | |
248 | { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } }, | |
249 | { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, | |
1fa60b5d | 250 | { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX) } } }, |
252b5132 RH |
251 | { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, |
252 | { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, | |
253 | { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, | |
254 | { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, | |
255 | { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, | |
6bb95a0f | 256 | { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} } |
252b5132 RH |
257 | }; |
258 | ||
259 | #undef A | |
260 | ||
b3466c39 | 261 | |
252b5132 RH |
262 | /* The instruction field table. */ |
263 | ||
b3466c39 DB |
264 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) |
265 | #define A(a) (1 << CGEN_IFLD_##a) | |
266 | #else | |
267 | #define A(a) (1 << CGEN_IFLD_/**/a) | |
268 | #endif | |
252b5132 RH |
269 | |
270 | const CGEN_IFLD m32r_cgen_ifld_table[] = | |
271 | { | |
272 | { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, | |
cfcdbe97 | 273 | { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, |
252b5132 RH |
274 | { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } } }, |
275 | { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } }, | |
276 | { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } }, | |
277 | { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } }, | |
278 | { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } }, | |
279 | { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } }, | |
280 | { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } }, | |
281 | { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } } }, | |
282 | { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } }, | |
283 | { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { (1<<MACH_BASE) } } }, | |
284 | { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } }, | |
285 | { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } } }, | |
286 | { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } }, | |
287 | { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, | |
288 | { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, | |
289 | { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, | |
1fa60b5d DE |
290 | { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } } }, |
291 | { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { (1<<MACH_BASE) } } }, | |
292 | { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } } }, | |
293 | { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { (1<<MACH_BASE) } } }, | |
294 | { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { (1<<MACH_BASE) } } }, | |
295 | { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } } }, | |
296 | { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } } }, | |
297 | { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } }, | |
6bb95a0f | 298 | { 0, 0, 0, 0, 0, 0, {0, {0}} } |
252b5132 RH |
299 | }; |
300 | ||
301 | #undef A | |
302 | ||
b3466c39 | 303 | |
252b5132 RH |
304 | /* The operand table. */ |
305 | ||
b3466c39 DB |
306 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) |
307 | #define A(a) (1 << CGEN_OPERAND_##a) | |
308 | #else | |
309 | #define A(a) (1 << CGEN_OPERAND_/**/a) | |
310 | #endif | |
311 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) | |
312 | #define OPERAND(op) M32R_OPERAND_##op | |
313 | #else | |
314 | #define OPERAND(op) M32R_OPERAND_/**/op | |
315 | #endif | |
252b5132 RH |
316 | |
317 | const CGEN_OPERAND m32r_cgen_operand_table[] = | |
318 | { | |
319 | /* pc: program counter */ | |
320 | { "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0, | |
321 | { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, | |
322 | /* sr: source register */ | |
323 | { "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4, | |
324 | { 0, { (1<<MACH_BASE) } } }, | |
325 | /* dr: destination register */ | |
326 | { "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4, | |
327 | { 0, { (1<<MACH_BASE) } } }, | |
328 | /* src1: source register 1 */ | |
329 | { "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4, | |
330 | { 0, { (1<<MACH_BASE) } } }, | |
331 | /* src2: source register 2 */ | |
332 | { "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4, | |
333 | { 0, { (1<<MACH_BASE) } } }, | |
334 | /* scr: source control register */ | |
335 | { "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4, | |
336 | { 0, { (1<<MACH_BASE) } } }, | |
337 | /* dcr: destination control register */ | |
338 | { "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4, | |
339 | { 0, { (1<<MACH_BASE) } } }, | |
340 | /* simm8: 8 bit signed immediate */ | |
341 | { "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8, | |
342 | { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, | |
343 | /* simm16: 16 bit signed immediate */ | |
344 | { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16, | |
345 | { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, | |
346 | /* uimm4: 4 bit trap number */ | |
347 | { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4, | |
348 | { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, | |
349 | /* uimm5: 5 bit shift count */ | |
350 | { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5, | |
351 | { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, | |
352 | /* uimm16: 16 bit unsigned immediate */ | |
353 | { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16, | |
354 | { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, | |
1fa60b5d DE |
355 | /* imm1: 1 bit immediate */ |
356 | { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1, | |
357 | { 0|A(HASH_PREFIX), { (1<<MACH_M32RX) } } }, | |
358 | /* accd: accumulator destination register */ | |
359 | { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2, | |
360 | { 0, { (1<<MACH_M32RX) } } }, | |
361 | /* accs: accumulator source register */ | |
362 | { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2, | |
363 | { 0, { (1<<MACH_M32RX) } } }, | |
364 | /* acc: accumulator reg (d) */ | |
365 | { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1, | |
366 | { 0, { (1<<MACH_M32RX) } } }, | |
252b5132 RH |
367 | /* hash: # prefix */ |
368 | { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0, | |
369 | { 0, { (1<<MACH_BASE) } } }, | |
370 | /* hi16: high 16 bit immediate, sign optional */ | |
371 | { "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16, | |
372 | { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } }, | |
373 | /* slo16: 16 bit signed immediate, for low() */ | |
374 | { "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16, | |
375 | { 0, { (1<<MACH_BASE) } } }, | |
376 | /* ulo16: 16 bit unsigned immediate, for low() */ | |
377 | { "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16, | |
378 | { 0, { (1<<MACH_BASE) } } }, | |
379 | /* uimm24: 24 bit address */ | |
380 | { "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24, | |
381 | { 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } } }, | |
382 | /* disp8: 8 bit displacement */ | |
383 | { "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8, | |
384 | { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, | |
385 | /* disp16: 16 bit displacement */ | |
386 | { "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16, | |
387 | { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, | |
388 | /* disp24: 24 bit displacement */ | |
389 | { "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24, | |
390 | { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, | |
391 | /* condbit: condition bit */ | |
392 | { "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0, | |
393 | { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, | |
394 | /* accum: accumulator */ | |
395 | { "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0, | |
396 | { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, | |
6bb95a0f | 397 | { 0, 0, 0, 0, 0, {0, {0}} } |
252b5132 RH |
398 | }; |
399 | ||
400 | #undef A | |
401 | ||
252b5132 RH |
402 | |
403 | /* The instruction table. */ | |
404 | ||
b3466c39 DB |
405 | #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) |
406 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) | |
407 | #define A(a) (1 << CGEN_INSN_##a) | |
408 | #else | |
409 | #define A(a) (1 << CGEN_INSN_/**/a) | |
410 | #endif | |
411 | ||
252b5132 RH |
412 | static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] = |
413 | { | |
414 | /* Special null first entry. | |
415 | A `num' value of zero is thus invalid. | |
416 | Also, the special `invalid' insn resides here. */ | |
6bb95a0f | 417 | { 0, 0, 0, 0, {0, {0}} }, |
252b5132 RH |
418 | /* add $dr,$sr */ |
419 | { | |
420 | M32R_INSN_ADD, "add", "add", 16, | |
1fa60b5d | 421 | { 0, { (1<<MACH_BASE), PIPE_OS } } |
252b5132 RH |
422 | }, |
423 | /* add3 $dr,$sr,$hash$slo16 */ | |
424 | { | |
425 | M32R_INSN_ADD3, "add3", "add3", 32, | |
1fa60b5d | 426 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
427 | }, |
428 | /* and $dr,$sr */ | |
429 | { | |
430 | M32R_INSN_AND, "and", "and", 16, | |
1fa60b5d | 431 | { 0, { (1<<MACH_BASE), PIPE_OS } } |
252b5132 RH |
432 | }, |
433 | /* and3 $dr,$sr,$uimm16 */ | |
434 | { | |
435 | M32R_INSN_AND3, "and3", "and3", 32, | |
1fa60b5d | 436 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
437 | }, |
438 | /* or $dr,$sr */ | |
439 | { | |
440 | M32R_INSN_OR, "or", "or", 16, | |
1fa60b5d | 441 | { 0, { (1<<MACH_BASE), PIPE_OS } } |
252b5132 RH |
442 | }, |
443 | /* or3 $dr,$sr,$hash$ulo16 */ | |
444 | { | |
445 | M32R_INSN_OR3, "or3", "or3", 32, | |
1fa60b5d | 446 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
447 | }, |
448 | /* xor $dr,$sr */ | |
449 | { | |
450 | M32R_INSN_XOR, "xor", "xor", 16, | |
1fa60b5d | 451 | { 0, { (1<<MACH_BASE), PIPE_OS } } |
252b5132 RH |
452 | }, |
453 | /* xor3 $dr,$sr,$uimm16 */ | |
454 | { | |
455 | M32R_INSN_XOR3, "xor3", "xor3", 32, | |
1fa60b5d | 456 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
457 | }, |
458 | /* addi $dr,$simm8 */ | |
459 | { | |
460 | M32R_INSN_ADDI, "addi", "addi", 16, | |
1fa60b5d | 461 | { 0, { (1<<MACH_BASE), PIPE_OS } } |
252b5132 RH |
462 | }, |
463 | /* addv $dr,$sr */ | |
464 | { | |
465 | M32R_INSN_ADDV, "addv", "addv", 16, | |
1fa60b5d | 466 | { 0, { (1<<MACH_BASE), PIPE_OS } } |
252b5132 RH |
467 | }, |
468 | /* addv3 $dr,$sr,$simm16 */ | |
469 | { | |
470 | M32R_INSN_ADDV3, "addv3", "addv3", 32, | |
1fa60b5d | 471 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
472 | }, |
473 | /* addx $dr,$sr */ | |
474 | { | |
475 | M32R_INSN_ADDX, "addx", "addx", 16, | |
1fa60b5d | 476 | { 0, { (1<<MACH_BASE), PIPE_OS } } |
252b5132 RH |
477 | }, |
478 | /* bc.s $disp8 */ | |
479 | { | |
480 | M32R_INSN_BC8, "bc8", "bc.s", 16, | |
1fa60b5d | 481 | { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
482 | }, |
483 | /* bc.l $disp24 */ | |
484 | { | |
485 | M32R_INSN_BC24, "bc24", "bc.l", 32, | |
1fa60b5d | 486 | { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
487 | }, |
488 | /* beq $src1,$src2,$disp16 */ | |
489 | { | |
490 | M32R_INSN_BEQ, "beq", "beq", 32, | |
1fa60b5d | 491 | { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
492 | }, |
493 | /* beqz $src2,$disp16 */ | |
494 | { | |
495 | M32R_INSN_BEQZ, "beqz", "beqz", 32, | |
1fa60b5d | 496 | { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
497 | }, |
498 | /* bgez $src2,$disp16 */ | |
499 | { | |
500 | M32R_INSN_BGEZ, "bgez", "bgez", 32, | |
1fa60b5d | 501 | { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
502 | }, |
503 | /* bgtz $src2,$disp16 */ | |
504 | { | |
505 | M32R_INSN_BGTZ, "bgtz", "bgtz", 32, | |
1fa60b5d | 506 | { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
507 | }, |
508 | /* blez $src2,$disp16 */ | |
509 | { | |
510 | M32R_INSN_BLEZ, "blez", "blez", 32, | |
1fa60b5d | 511 | { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
512 | }, |
513 | /* bltz $src2,$disp16 */ | |
514 | { | |
515 | M32R_INSN_BLTZ, "bltz", "bltz", 32, | |
1fa60b5d | 516 | { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
517 | }, |
518 | /* bnez $src2,$disp16 */ | |
519 | { | |
520 | M32R_INSN_BNEZ, "bnez", "bnez", 32, | |
1fa60b5d | 521 | { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
522 | }, |
523 | /* bl.s $disp8 */ | |
524 | { | |
525 | M32R_INSN_BL8, "bl8", "bl.s", 16, | |
1fa60b5d | 526 | { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
527 | }, |
528 | /* bl.l $disp24 */ | |
529 | { | |
530 | M32R_INSN_BL24, "bl24", "bl.l", 32, | |
1fa60b5d DE |
531 | { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } } |
532 | }, | |
533 | /* bcl.s $disp8 */ | |
534 | { | |
535 | M32R_INSN_BCL8, "bcl8", "bcl.s", 16, | |
536 | { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } } | |
537 | }, | |
538 | /* bcl.l $disp24 */ | |
539 | { | |
540 | M32R_INSN_BCL24, "bcl24", "bcl.l", 32, | |
541 | { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } } | |
252b5132 RH |
542 | }, |
543 | /* bnc.s $disp8 */ | |
544 | { | |
545 | M32R_INSN_BNC8, "bnc8", "bnc.s", 16, | |
1fa60b5d | 546 | { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
547 | }, |
548 | /* bnc.l $disp24 */ | |
549 | { | |
550 | M32R_INSN_BNC24, "bnc24", "bnc.l", 32, | |
1fa60b5d | 551 | { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
552 | }, |
553 | /* bne $src1,$src2,$disp16 */ | |
554 | { | |
555 | M32R_INSN_BNE, "bne", "bne", 32, | |
1fa60b5d | 556 | { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
557 | }, |
558 | /* bra.s $disp8 */ | |
559 | { | |
560 | M32R_INSN_BRA8, "bra8", "bra.s", 16, | |
1fa60b5d | 561 | { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
562 | }, |
563 | /* bra.l $disp24 */ | |
564 | { | |
565 | M32R_INSN_BRA24, "bra24", "bra.l", 32, | |
1fa60b5d DE |
566 | { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } } |
567 | }, | |
568 | /* bncl.s $disp8 */ | |
569 | { | |
570 | M32R_INSN_BNCL8, "bncl8", "bncl.s", 16, | |
571 | { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } } | |
572 | }, | |
573 | /* bncl.l $disp24 */ | |
574 | { | |
575 | M32R_INSN_BNCL24, "bncl24", "bncl.l", 32, | |
576 | { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } } | |
252b5132 RH |
577 | }, |
578 | /* cmp $src1,$src2 */ | |
579 | { | |
580 | M32R_INSN_CMP, "cmp", "cmp", 16, | |
1fa60b5d | 581 | { 0, { (1<<MACH_BASE), PIPE_OS } } |
252b5132 RH |
582 | }, |
583 | /* cmpi $src2,$simm16 */ | |
584 | { | |
585 | M32R_INSN_CMPI, "cmpi", "cmpi", 32, | |
1fa60b5d | 586 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
587 | }, |
588 | /* cmpu $src1,$src2 */ | |
589 | { | |
590 | M32R_INSN_CMPU, "cmpu", "cmpu", 16, | |
1fa60b5d | 591 | { 0, { (1<<MACH_BASE), PIPE_OS } } |
252b5132 RH |
592 | }, |
593 | /* cmpui $src2,$simm16 */ | |
594 | { | |
595 | M32R_INSN_CMPUI, "cmpui", "cmpui", 32, | |
1fa60b5d DE |
596 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
597 | }, | |
598 | /* cmpeq $src1,$src2 */ | |
599 | { | |
600 | M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16, | |
601 | { 0, { (1<<MACH_M32RX), PIPE_OS } } | |
602 | }, | |
603 | /* cmpz $src2 */ | |
604 | { | |
605 | M32R_INSN_CMPZ, "cmpz", "cmpz", 16, | |
606 | { 0, { (1<<MACH_M32RX), PIPE_OS } } | |
252b5132 RH |
607 | }, |
608 | /* div $dr,$sr */ | |
609 | { | |
610 | M32R_INSN_DIV, "div", "div", 32, | |
1fa60b5d | 611 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
612 | }, |
613 | /* divu $dr,$sr */ | |
614 | { | |
615 | M32R_INSN_DIVU, "divu", "divu", 32, | |
1fa60b5d | 616 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
617 | }, |
618 | /* rem $dr,$sr */ | |
619 | { | |
620 | M32R_INSN_REM, "rem", "rem", 32, | |
1fa60b5d | 621 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
622 | }, |
623 | /* remu $dr,$sr */ | |
624 | { | |
625 | M32R_INSN_REMU, "remu", "remu", 32, | |
1fa60b5d DE |
626 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
627 | }, | |
628 | /* divh $dr,$sr */ | |
629 | { | |
630 | M32R_INSN_DIVH, "divh", "divh", 32, | |
631 | { 0, { (1<<MACH_M32RX), PIPE_NONE } } | |
632 | }, | |
633 | /* jc $sr */ | |
634 | { | |
635 | M32R_INSN_JC, "jc", "jc", 16, | |
636 | { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } } | |
637 | }, | |
638 | /* jnc $sr */ | |
639 | { | |
640 | M32R_INSN_JNC, "jnc", "jnc", 16, | |
641 | { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } } | |
252b5132 RH |
642 | }, |
643 | /* jl $sr */ | |
644 | { | |
645 | M32R_INSN_JL, "jl", "jl", 16, | |
1fa60b5d | 646 | { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
647 | }, |
648 | /* jmp $sr */ | |
649 | { | |
650 | M32R_INSN_JMP, "jmp", "jmp", 16, | |
1fa60b5d | 651 | { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
652 | }, |
653 | /* ld $dr,@$sr */ | |
654 | { | |
655 | M32R_INSN_LD, "ld", "ld", 16, | |
1fa60b5d | 656 | { 0, { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
657 | }, |
658 | /* ld $dr,@($slo16,$sr) */ | |
659 | { | |
660 | M32R_INSN_LD_D, "ld-d", "ld", 32, | |
1fa60b5d | 661 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
662 | }, |
663 | /* ldb $dr,@$sr */ | |
664 | { | |
665 | M32R_INSN_LDB, "ldb", "ldb", 16, | |
1fa60b5d | 666 | { 0, { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
667 | }, |
668 | /* ldb $dr,@($slo16,$sr) */ | |
669 | { | |
670 | M32R_INSN_LDB_D, "ldb-d", "ldb", 32, | |
1fa60b5d | 671 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
672 | }, |
673 | /* ldh $dr,@$sr */ | |
674 | { | |
675 | M32R_INSN_LDH, "ldh", "ldh", 16, | |
1fa60b5d | 676 | { 0, { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
677 | }, |
678 | /* ldh $dr,@($slo16,$sr) */ | |
679 | { | |
680 | M32R_INSN_LDH_D, "ldh-d", "ldh", 32, | |
1fa60b5d | 681 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
682 | }, |
683 | /* ldub $dr,@$sr */ | |
684 | { | |
685 | M32R_INSN_LDUB, "ldub", "ldub", 16, | |
1fa60b5d | 686 | { 0, { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
687 | }, |
688 | /* ldub $dr,@($slo16,$sr) */ | |
689 | { | |
690 | M32R_INSN_LDUB_D, "ldub-d", "ldub", 32, | |
1fa60b5d | 691 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
692 | }, |
693 | /* lduh $dr,@$sr */ | |
694 | { | |
695 | M32R_INSN_LDUH, "lduh", "lduh", 16, | |
1fa60b5d | 696 | { 0, { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
697 | }, |
698 | /* lduh $dr,@($slo16,$sr) */ | |
699 | { | |
700 | M32R_INSN_LDUH_D, "lduh-d", "lduh", 32, | |
1fa60b5d | 701 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
702 | }, |
703 | /* ld $dr,@$sr+ */ | |
704 | { | |
705 | M32R_INSN_LD_PLUS, "ld-plus", "ld", 16, | |
1fa60b5d | 706 | { 0, { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
707 | }, |
708 | /* ld24 $dr,$uimm24 */ | |
709 | { | |
710 | M32R_INSN_LD24, "ld24", "ld24", 32, | |
1fa60b5d | 711 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
712 | }, |
713 | /* ldi8 $dr,$simm8 */ | |
714 | { | |
715 | M32R_INSN_LDI8, "ldi8", "ldi8", 16, | |
1fa60b5d | 716 | { 0, { (1<<MACH_BASE), PIPE_OS } } |
252b5132 RH |
717 | }, |
718 | /* ldi16 $dr,$hash$slo16 */ | |
719 | { | |
720 | M32R_INSN_LDI16, "ldi16", "ldi16", 32, | |
1fa60b5d | 721 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
722 | }, |
723 | /* lock $dr,@$sr */ | |
724 | { | |
725 | M32R_INSN_LOCK, "lock", "lock", 16, | |
1fa60b5d | 726 | { 0, { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
727 | }, |
728 | /* machi $src1,$src2 */ | |
729 | { | |
730 | M32R_INSN_MACHI, "machi", "machi", 16, | |
1fa60b5d DE |
731 | { 0, { (1<<MACH_M32R), PIPE_S } } |
732 | }, | |
733 | /* machi $src1,$src2,$acc */ | |
734 | { | |
735 | M32R_INSN_MACHI_A, "machi-a", "machi", 16, | |
736 | { 0, { (1<<MACH_M32RX), PIPE_S } } | |
252b5132 RH |
737 | }, |
738 | /* maclo $src1,$src2 */ | |
739 | { | |
740 | M32R_INSN_MACLO, "maclo", "maclo", 16, | |
1fa60b5d DE |
741 | { 0, { (1<<MACH_M32R), PIPE_S } } |
742 | }, | |
743 | /* maclo $src1,$src2,$acc */ | |
744 | { | |
745 | M32R_INSN_MACLO_A, "maclo-a", "maclo", 16, | |
746 | { 0, { (1<<MACH_M32RX), PIPE_S } } | |
252b5132 RH |
747 | }, |
748 | /* macwhi $src1,$src2 */ | |
749 | { | |
750 | M32R_INSN_MACWHI, "macwhi", "macwhi", 16, | |
1fa60b5d DE |
751 | { 0, { (1<<MACH_M32R), PIPE_S } } |
752 | }, | |
753 | /* macwhi $src1,$src2,$acc */ | |
754 | { | |
755 | M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16, | |
756 | { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } } | |
252b5132 RH |
757 | }, |
758 | /* macwlo $src1,$src2 */ | |
759 | { | |
760 | M32R_INSN_MACWLO, "macwlo", "macwlo", 16, | |
1fa60b5d DE |
761 | { 0, { (1<<MACH_M32R), PIPE_S } } |
762 | }, | |
763 | /* macwlo $src1,$src2,$acc */ | |
764 | { | |
765 | M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16, | |
766 | { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } } | |
252b5132 RH |
767 | }, |
768 | /* mul $dr,$sr */ | |
769 | { | |
770 | M32R_INSN_MUL, "mul", "mul", 16, | |
1fa60b5d | 771 | { 0, { (1<<MACH_BASE), PIPE_S } } |
252b5132 RH |
772 | }, |
773 | /* mulhi $src1,$src2 */ | |
774 | { | |
775 | M32R_INSN_MULHI, "mulhi", "mulhi", 16, | |
1fa60b5d DE |
776 | { 0, { (1<<MACH_M32R), PIPE_S } } |
777 | }, | |
778 | /* mulhi $src1,$src2,$acc */ | |
779 | { | |
780 | M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16, | |
781 | { 0, { (1<<MACH_M32RX), PIPE_S } } | |
252b5132 RH |
782 | }, |
783 | /* mullo $src1,$src2 */ | |
784 | { | |
785 | M32R_INSN_MULLO, "mullo", "mullo", 16, | |
1fa60b5d DE |
786 | { 0, { (1<<MACH_M32R), PIPE_S } } |
787 | }, | |
788 | /* mullo $src1,$src2,$acc */ | |
789 | { | |
790 | M32R_INSN_MULLO_A, "mullo-a", "mullo", 16, | |
791 | { 0, { (1<<MACH_M32RX), PIPE_S } } | |
252b5132 RH |
792 | }, |
793 | /* mulwhi $src1,$src2 */ | |
794 | { | |
795 | M32R_INSN_MULWHI, "mulwhi", "mulwhi", 16, | |
1fa60b5d DE |
796 | { 0, { (1<<MACH_M32R), PIPE_S } } |
797 | }, | |
798 | /* mulwhi $src1,$src2,$acc */ | |
799 | { | |
800 | M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16, | |
801 | { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } } | |
252b5132 RH |
802 | }, |
803 | /* mulwlo $src1,$src2 */ | |
804 | { | |
805 | M32R_INSN_MULWLO, "mulwlo", "mulwlo", 16, | |
1fa60b5d DE |
806 | { 0, { (1<<MACH_M32R), PIPE_S } } |
807 | }, | |
808 | /* mulwlo $src1,$src2,$acc */ | |
809 | { | |
810 | M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16, | |
811 | { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } } | |
252b5132 RH |
812 | }, |
813 | /* mv $dr,$sr */ | |
814 | { | |
815 | M32R_INSN_MV, "mv", "mv", 16, | |
1fa60b5d | 816 | { 0, { (1<<MACH_BASE), PIPE_OS } } |
252b5132 RH |
817 | }, |
818 | /* mvfachi $dr */ | |
819 | { | |
820 | M32R_INSN_MVFACHI, "mvfachi", "mvfachi", 16, | |
1fa60b5d DE |
821 | { 0, { (1<<MACH_M32R), PIPE_S } } |
822 | }, | |
823 | /* mvfachi $dr,$accs */ | |
824 | { | |
825 | M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16, | |
826 | { 0, { (1<<MACH_M32RX), PIPE_S } } | |
252b5132 RH |
827 | }, |
828 | /* mvfaclo $dr */ | |
829 | { | |
830 | M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", 16, | |
1fa60b5d DE |
831 | { 0, { (1<<MACH_M32R), PIPE_S } } |
832 | }, | |
833 | /* mvfaclo $dr,$accs */ | |
834 | { | |
835 | M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16, | |
836 | { 0, { (1<<MACH_M32RX), PIPE_S } } | |
252b5132 RH |
837 | }, |
838 | /* mvfacmi $dr */ | |
839 | { | |
840 | M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", 16, | |
1fa60b5d DE |
841 | { 0, { (1<<MACH_M32R), PIPE_S } } |
842 | }, | |
843 | /* mvfacmi $dr,$accs */ | |
844 | { | |
845 | M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16, | |
846 | { 0, { (1<<MACH_M32RX), PIPE_S } } | |
252b5132 RH |
847 | }, |
848 | /* mvfc $dr,$scr */ | |
849 | { | |
850 | M32R_INSN_MVFC, "mvfc", "mvfc", 16, | |
1fa60b5d | 851 | { 0, { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
852 | }, |
853 | /* mvtachi $src1 */ | |
854 | { | |
855 | M32R_INSN_MVTACHI, "mvtachi", "mvtachi", 16, | |
1fa60b5d DE |
856 | { 0, { (1<<MACH_M32R), PIPE_S } } |
857 | }, | |
858 | /* mvtachi $src1,$accs */ | |
859 | { | |
860 | M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16, | |
861 | { 0, { (1<<MACH_M32RX), PIPE_S } } | |
252b5132 RH |
862 | }, |
863 | /* mvtaclo $src1 */ | |
864 | { | |
865 | M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", 16, | |
1fa60b5d DE |
866 | { 0, { (1<<MACH_M32R), PIPE_S } } |
867 | }, | |
868 | /* mvtaclo $src1,$accs */ | |
869 | { | |
870 | M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16, | |
871 | { 0, { (1<<MACH_M32RX), PIPE_S } } | |
252b5132 RH |
872 | }, |
873 | /* mvtc $sr,$dcr */ | |
874 | { | |
875 | M32R_INSN_MVTC, "mvtc", "mvtc", 16, | |
1fa60b5d | 876 | { 0, { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
877 | }, |
878 | /* neg $dr,$sr */ | |
879 | { | |
880 | M32R_INSN_NEG, "neg", "neg", 16, | |
1fa60b5d | 881 | { 0, { (1<<MACH_BASE), PIPE_OS } } |
252b5132 RH |
882 | }, |
883 | /* nop */ | |
884 | { | |
885 | M32R_INSN_NOP, "nop", "nop", 16, | |
1fa60b5d | 886 | { 0, { (1<<MACH_BASE), PIPE_OS } } |
252b5132 RH |
887 | }, |
888 | /* not $dr,$sr */ | |
889 | { | |
890 | M32R_INSN_NOT, "not", "not", 16, | |
1fa60b5d | 891 | { 0, { (1<<MACH_BASE), PIPE_OS } } |
252b5132 RH |
892 | }, |
893 | /* rac */ | |
894 | { | |
895 | M32R_INSN_RAC, "rac", "rac", 16, | |
1fa60b5d DE |
896 | { 0, { (1<<MACH_M32R), PIPE_S } } |
897 | }, | |
898 | /* rac $accd,$accs,$imm1 */ | |
899 | { | |
900 | M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16, | |
901 | { 0, { (1<<MACH_M32RX), PIPE_S } } | |
252b5132 RH |
902 | }, |
903 | /* rach */ | |
904 | { | |
905 | M32R_INSN_RACH, "rach", "rach", 16, | |
1fa60b5d DE |
906 | { 0, { (1<<MACH_M32R), PIPE_S } } |
907 | }, | |
908 | /* rach $accd,$accs,$imm1 */ | |
909 | { | |
910 | M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16, | |
911 | { 0, { (1<<MACH_M32RX), PIPE_S } } | |
252b5132 RH |
912 | }, |
913 | /* rte */ | |
914 | { | |
915 | M32R_INSN_RTE, "rte", "rte", 16, | |
1fa60b5d | 916 | { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
917 | }, |
918 | /* seth $dr,$hash$hi16 */ | |
919 | { | |
920 | M32R_INSN_SETH, "seth", "seth", 32, | |
1fa60b5d | 921 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
922 | }, |
923 | /* sll $dr,$sr */ | |
924 | { | |
925 | M32R_INSN_SLL, "sll", "sll", 16, | |
1fa60b5d | 926 | { 0, { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
927 | }, |
928 | /* sll3 $dr,$sr,$simm16 */ | |
929 | { | |
930 | M32R_INSN_SLL3, "sll3", "sll3", 32, | |
1fa60b5d | 931 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
932 | }, |
933 | /* slli $dr,$uimm5 */ | |
934 | { | |
935 | M32R_INSN_SLLI, "slli", "slli", 16, | |
1fa60b5d | 936 | { 0, { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
937 | }, |
938 | /* sra $dr,$sr */ | |
939 | { | |
940 | M32R_INSN_SRA, "sra", "sra", 16, | |
1fa60b5d | 941 | { 0, { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
942 | }, |
943 | /* sra3 $dr,$sr,$simm16 */ | |
944 | { | |
945 | M32R_INSN_SRA3, "sra3", "sra3", 32, | |
1fa60b5d | 946 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
947 | }, |
948 | /* srai $dr,$uimm5 */ | |
949 | { | |
950 | M32R_INSN_SRAI, "srai", "srai", 16, | |
1fa60b5d | 951 | { 0, { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
952 | }, |
953 | /* srl $dr,$sr */ | |
954 | { | |
955 | M32R_INSN_SRL, "srl", "srl", 16, | |
1fa60b5d | 956 | { 0, { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
957 | }, |
958 | /* srl3 $dr,$sr,$simm16 */ | |
959 | { | |
960 | M32R_INSN_SRL3, "srl3", "srl3", 32, | |
1fa60b5d | 961 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
962 | }, |
963 | /* srli $dr,$uimm5 */ | |
964 | { | |
965 | M32R_INSN_SRLI, "srli", "srli", 16, | |
1fa60b5d | 966 | { 0, { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
967 | }, |
968 | /* st $src1,@$src2 */ | |
969 | { | |
970 | M32R_INSN_ST, "st", "st", 16, | |
1fa60b5d | 971 | { 0, { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
972 | }, |
973 | /* st $src1,@($slo16,$src2) */ | |
974 | { | |
975 | M32R_INSN_ST_D, "st-d", "st", 32, | |
1fa60b5d | 976 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
977 | }, |
978 | /* stb $src1,@$src2 */ | |
979 | { | |
980 | M32R_INSN_STB, "stb", "stb", 16, | |
1fa60b5d | 981 | { 0, { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
982 | }, |
983 | /* stb $src1,@($slo16,$src2) */ | |
984 | { | |
985 | M32R_INSN_STB_D, "stb-d", "stb", 32, | |
1fa60b5d | 986 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
987 | }, |
988 | /* sth $src1,@$src2 */ | |
989 | { | |
990 | M32R_INSN_STH, "sth", "sth", 16, | |
1fa60b5d | 991 | { 0, { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
992 | }, |
993 | /* sth $src1,@($slo16,$src2) */ | |
994 | { | |
995 | M32R_INSN_STH_D, "sth-d", "sth", 32, | |
1fa60b5d | 996 | { 0, { (1<<MACH_BASE), PIPE_NONE } } |
252b5132 RH |
997 | }, |
998 | /* st $src1,@+$src2 */ | |
999 | { | |
1000 | M32R_INSN_ST_PLUS, "st-plus", "st", 16, | |
1fa60b5d | 1001 | { 0, { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
1002 | }, |
1003 | /* st $src1,@-$src2 */ | |
1004 | { | |
1005 | M32R_INSN_ST_MINUS, "st-minus", "st", 16, | |
1fa60b5d | 1006 | { 0, { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
1007 | }, |
1008 | /* sub $dr,$sr */ | |
1009 | { | |
1010 | M32R_INSN_SUB, "sub", "sub", 16, | |
1fa60b5d | 1011 | { 0, { (1<<MACH_BASE), PIPE_OS } } |
252b5132 RH |
1012 | }, |
1013 | /* subv $dr,$sr */ | |
1014 | { | |
1015 | M32R_INSN_SUBV, "subv", "subv", 16, | |
1fa60b5d | 1016 | { 0, { (1<<MACH_BASE), PIPE_OS } } |
252b5132 RH |
1017 | }, |
1018 | /* subx $dr,$sr */ | |
1019 | { | |
1020 | M32R_INSN_SUBX, "subx", "subx", 16, | |
1fa60b5d | 1021 | { 0, { (1<<MACH_BASE), PIPE_OS } } |
252b5132 RH |
1022 | }, |
1023 | /* trap $uimm4 */ | |
1024 | { | |
1025 | M32R_INSN_TRAP, "trap", "trap", 16, | |
1fa60b5d | 1026 | { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } |
252b5132 RH |
1027 | }, |
1028 | /* unlock $src1,@$src2 */ | |
1029 | { | |
1030 | M32R_INSN_UNLOCK, "unlock", "unlock", 16, | |
1fa60b5d DE |
1031 | { 0, { (1<<MACH_BASE), PIPE_O } } |
1032 | }, | |
1033 | /* satb $dr,$sr */ | |
1034 | { | |
1035 | M32R_INSN_SATB, "satb", "satb", 32, | |
1036 | { 0, { (1<<MACH_M32RX), PIPE_NONE } } | |
1037 | }, | |
1038 | /* sath $dr,$sr */ | |
1039 | { | |
1040 | M32R_INSN_SATH, "sath", "sath", 32, | |
1041 | { 0, { (1<<MACH_M32RX), PIPE_NONE } } | |
1042 | }, | |
1043 | /* sat $dr,$sr */ | |
1044 | { | |
1045 | M32R_INSN_SAT, "sat", "sat", 32, | |
1046 | { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } } | |
1047 | }, | |
1048 | /* pcmpbz $src2 */ | |
1049 | { | |
1050 | M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16, | |
cfcdbe97 | 1051 | { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_OS } } |
1fa60b5d DE |
1052 | }, |
1053 | /* sadd */ | |
1054 | { | |
1055 | M32R_INSN_SADD, "sadd", "sadd", 16, | |
1056 | { 0, { (1<<MACH_M32RX), PIPE_S } } | |
1057 | }, | |
1058 | /* macwu1 $src1,$src2 */ | |
1059 | { | |
1060 | M32R_INSN_MACWU1, "macwu1", "macwu1", 16, | |
1061 | { 0, { (1<<MACH_M32RX), PIPE_S } } | |
1062 | }, | |
1063 | /* msblo $src1,$src2 */ | |
1064 | { | |
1065 | M32R_INSN_MSBLO, "msblo", "msblo", 16, | |
1066 | { 0, { (1<<MACH_M32RX), PIPE_S } } | |
1067 | }, | |
1068 | /* mulwu1 $src1,$src2 */ | |
1069 | { | |
1070 | M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16, | |
1071 | { 0, { (1<<MACH_M32RX), PIPE_S } } | |
1072 | }, | |
1073 | /* maclh1 $src1,$src2 */ | |
1074 | { | |
1075 | M32R_INSN_MACLH1, "maclh1", "maclh1", 16, | |
1076 | { 0, { (1<<MACH_M32RX), PIPE_S } } | |
1077 | }, | |
1078 | /* sc */ | |
1079 | { | |
1080 | M32R_INSN_SC, "sc", "sc", 16, | |
1081 | { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } } | |
1082 | }, | |
1083 | /* snc */ | |
1084 | { | |
1085 | M32R_INSN_SNC, "snc", "snc", 16, | |
1086 | { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } } | |
252b5132 RH |
1087 | }, |
1088 | }; | |
1089 | ||
252b5132 | 1090 | #undef OP |
b3466c39 | 1091 | #undef A |
252b5132 RH |
1092 | |
1093 | /* Initialize anything needed to be done once, before any cpu_open call. */ | |
1094 | ||
1095 | static void | |
1096 | init_tables () | |
1097 | { | |
1098 | } | |
1099 | ||
1100 | /* Subroutine of m32r_cgen_cpu_open to look up a mach via its bfd name. */ | |
1101 | ||
1102 | static const CGEN_MACH * | |
1103 | lookup_mach_via_bfd_name (table, name) | |
1104 | const CGEN_MACH *table; | |
1105 | const char *name; | |
1106 | { | |
1107 | while (table->name) | |
1108 | { | |
1109 | if (strcmp (name, table->bfd_name) == 0) | |
1110 | return table; | |
1111 | ++table; | |
1112 | } | |
1113 | abort (); | |
1114 | } | |
1115 | ||
1116 | /* Subroutine of m32r_cgen_cpu_open to build the hardware table. */ | |
1117 | ||
1118 | static void | |
1119 | build_hw_table (cd) | |
1120 | CGEN_CPU_TABLE *cd; | |
1121 | { | |
1122 | int i; | |
1123 | int machs = cd->machs; | |
1124 | const CGEN_HW_ENTRY *init = & m32r_cgen_hw_table[0]; | |
1125 | /* MAX_HW is only an upper bound on the number of selected entries. | |
1126 | However each entry is indexed by it's enum so there can be holes in | |
1127 | the table. */ | |
1128 | const CGEN_HW_ENTRY **selected = | |
1129 | (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); | |
1130 | ||
1131 | cd->hw_table.init_entries = init; | |
1132 | cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); | |
1133 | memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); | |
1134 | /* ??? For now we just use machs to determine which ones we want. */ | |
1135 | for (i = 0; init[i].name != NULL; ++i) | |
1136 | if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) | |
1137 | & machs) | |
1138 | selected[init[i].type] = &init[i]; | |
1139 | cd->hw_table.entries = selected; | |
1140 | cd->hw_table.num_entries = MAX_HW; | |
1141 | } | |
1142 | ||
1143 | /* Subroutine of m32r_cgen_cpu_open to build the hardware table. */ | |
1144 | ||
1145 | static void | |
1146 | build_ifield_table (cd) | |
1147 | CGEN_CPU_TABLE *cd; | |
1148 | { | |
1149 | cd->ifld_table = & m32r_cgen_ifld_table[0]; | |
1150 | } | |
1151 | ||
1152 | /* Subroutine of m32r_cgen_cpu_open to build the hardware table. */ | |
1153 | ||
1154 | static void | |
1155 | build_operand_table (cd) | |
1156 | CGEN_CPU_TABLE *cd; | |
1157 | { | |
1158 | int i; | |
1159 | int machs = cd->machs; | |
1160 | const CGEN_OPERAND *init = & m32r_cgen_operand_table[0]; | |
1161 | /* MAX_OPERANDS is only an upper bound on the number of selected entries. | |
1162 | However each entry is indexed by it's enum so there can be holes in | |
1163 | the table. */ | |
1164 | const CGEN_OPERAND **selected = | |
1165 | (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); | |
1166 | ||
1167 | cd->operand_table.init_entries = init; | |
1168 | cd->operand_table.entry_size = sizeof (CGEN_OPERAND); | |
1169 | memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); | |
1170 | /* ??? For now we just use mach to determine which ones we want. */ | |
1171 | for (i = 0; init[i].name != NULL; ++i) | |
1172 | if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) | |
1173 | & machs) | |
1174 | selected[init[i].type] = &init[i]; | |
1175 | cd->operand_table.entries = selected; | |
1176 | cd->operand_table.num_entries = MAX_OPERANDS; | |
1177 | } | |
1178 | ||
1179 | /* Subroutine of m32r_cgen_cpu_open to build the hardware table. | |
1180 | ??? This could leave out insns not supported by the specified mach/isa, | |
1181 | but that would cause errors like "foo only supported by bar" to become | |
1182 | "unknown insn", so for now we include all insns and require the app to | |
1183 | do the checking later. | |
1184 | ??? On the other hand, parsing of such insns may require their hardware or | |
1185 | operand elements to be in the table [which they mightn't be]. */ | |
1186 | ||
1187 | static void | |
1188 | build_insn_table (cd) | |
1189 | CGEN_CPU_TABLE *cd; | |
1190 | { | |
1191 | int i; | |
1192 | const CGEN_IBASE *ib = & m32r_cgen_insn_table[0]; | |
1193 | CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); | |
1194 | ||
1195 | memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); | |
1196 | for (i = 0; i < MAX_INSNS; ++i) | |
1197 | insns[i].base = &ib[i]; | |
1198 | cd->insn_table.init_entries = insns; | |
1199 | cd->insn_table.entry_size = sizeof (CGEN_IBASE); | |
1200 | cd->insn_table.num_init_entries = MAX_INSNS; | |
1201 | } | |
1202 | ||
1203 | /* Subroutine of m32r_cgen_cpu_open to rebuild the tables. */ | |
1204 | ||
1205 | static void | |
1206 | m32r_cgen_rebuild_tables (cd) | |
1207 | CGEN_CPU_TABLE *cd; | |
1208 | { | |
fc7bc883 | 1209 | int i; |
252b5132 RH |
1210 | unsigned int isas = cd->isas; |
1211 | unsigned int machs = cd->machs; | |
1212 | ||
1213 | cd->int_insn_p = CGEN_INT_INSN_P; | |
1214 | ||
1215 | /* Data derived from the isa spec. */ | |
1216 | #define UNSET (CGEN_SIZE_UNKNOWN + 1) | |
1217 | cd->default_insn_bitsize = UNSET; | |
1218 | cd->base_insn_bitsize = UNSET; | |
1219 | cd->min_insn_bitsize = 65535; /* some ridiculously big number */ | |
1220 | cd->max_insn_bitsize = 0; | |
1221 | for (i = 0; i < MAX_ISAS; ++i) | |
1222 | if (((1 << i) & isas) != 0) | |
1223 | { | |
1224 | const CGEN_ISA *isa = & m32r_cgen_isa_table[i]; | |
1225 | ||
1226 | /* Default insn sizes of all selected isas must be equal or we set | |
1227 | the result to 0, meaning "unknown". */ | |
1228 | if (cd->default_insn_bitsize == UNSET) | |
1229 | cd->default_insn_bitsize = isa->default_insn_bitsize; | |
1230 | else if (isa->default_insn_bitsize == cd->default_insn_bitsize) | |
1231 | ; /* this is ok */ | |
1232 | else | |
1233 | cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; | |
1234 | ||
1235 | /* Base insn sizes of all selected isas must be equal or we set | |
1236 | the result to 0, meaning "unknown". */ | |
1237 | if (cd->base_insn_bitsize == UNSET) | |
1238 | cd->base_insn_bitsize = isa->base_insn_bitsize; | |
1239 | else if (isa->base_insn_bitsize == cd->base_insn_bitsize) | |
1240 | ; /* this is ok */ | |
1241 | else | |
1242 | cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; | |
1243 | ||
1244 | /* Set min,max insn sizes. */ | |
1245 | if (isa->min_insn_bitsize < cd->min_insn_bitsize) | |
1246 | cd->min_insn_bitsize = isa->min_insn_bitsize; | |
1247 | if (isa->max_insn_bitsize > cd->max_insn_bitsize) | |
1248 | cd->max_insn_bitsize = isa->max_insn_bitsize; | |
252b5132 RH |
1249 | } |
1250 | ||
1251 | /* Data derived from the mach spec. */ | |
1252 | for (i = 0; i < MAX_MACHS; ++i) | |
1253 | if (((1 << i) & machs) != 0) | |
1254 | { | |
1255 | const CGEN_MACH *mach = & m32r_cgen_mach_table[i]; | |
1256 | ||
fc7bc883 RH |
1257 | if (mach->insn_chunk_bitsize != 0) |
1258 | { | |
1259 | if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) | |
1260 | { | |
1261 | fprintf (stderr, "m32r_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", | |
1262 | cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); | |
1263 | abort (); | |
1264 | } | |
1265 | ||
1266 | cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; | |
1267 | } | |
252b5132 RH |
1268 | } |
1269 | ||
1270 | /* Determine which hw elements are used by MACH. */ | |
1271 | build_hw_table (cd); | |
1272 | ||
1273 | /* Build the ifield table. */ | |
1274 | build_ifield_table (cd); | |
1275 | ||
1276 | /* Determine which operands are used by MACH/ISA. */ | |
1277 | build_operand_table (cd); | |
1278 | ||
1279 | /* Build the instruction table. */ | |
1280 | build_insn_table (cd); | |
1281 | } | |
1282 | ||
1283 | /* Initialize a cpu table and return a descriptor. | |
1284 | It's much like opening a file, and must be the first function called. | |
1285 | The arguments are a set of (type/value) pairs, terminated with | |
1286 | CGEN_CPU_OPEN_END. | |
1287 | ||
1288 | Currently supported values: | |
1289 | CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr | |
1290 | CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr | |
1291 | CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name | |
1292 | CGEN_CPU_OPEN_ENDIAN: specify endian choice | |
1293 | CGEN_CPU_OPEN_END: terminates arguments | |
1294 | ||
1295 | ??? Simultaneous multiple isas might not make sense, but it's not (yet) | |
1296 | precluded. | |
1297 | ||
1298 | ??? We only support ISO C stdargs here, not K&R. | |
1299 | Laziness, plus experiment to see if anything requires K&R - eventually | |
1300 | K&R will no longer be supported - e.g. GDB is currently trying this. */ | |
1301 | ||
1302 | CGEN_CPU_DESC | |
1303 | m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) | |
1304 | { | |
1305 | CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); | |
1306 | static int init_p; | |
1307 | unsigned int isas = 0; /* 0 = "unspecified" */ | |
1308 | unsigned int machs = 0; /* 0 = "unspecified" */ | |
1309 | enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; | |
1310 | va_list ap; | |
1311 | ||
1312 | if (! init_p) | |
1313 | { | |
1314 | init_tables (); | |
1315 | init_p = 1; | |
1316 | } | |
1317 | ||
1318 | memset (cd, 0, sizeof (*cd)); | |
1319 | ||
1320 | va_start (ap, arg_type); | |
1321 | while (arg_type != CGEN_CPU_OPEN_END) | |
1322 | { | |
1323 | switch (arg_type) | |
1324 | { | |
1325 | case CGEN_CPU_OPEN_ISAS : | |
1326 | isas = va_arg (ap, unsigned int); | |
1327 | break; | |
1328 | case CGEN_CPU_OPEN_MACHS : | |
1329 | machs = va_arg (ap, unsigned int); | |
1330 | break; | |
1331 | case CGEN_CPU_OPEN_BFDMACH : | |
1332 | { | |
1333 | const char *name = va_arg (ap, const char *); | |
1334 | const CGEN_MACH *mach = | |
1335 | lookup_mach_via_bfd_name (m32r_cgen_mach_table, name); | |
1336 | ||
27fca2d8 | 1337 | machs |= 1 << mach->num; |
252b5132 RH |
1338 | break; |
1339 | } | |
1340 | case CGEN_CPU_OPEN_ENDIAN : | |
1341 | endian = va_arg (ap, enum cgen_endian); | |
1342 | break; | |
1343 | default : | |
1344 | fprintf (stderr, "m32r_cgen_cpu_open: unsupported argument `%d'\n", | |
1345 | arg_type); | |
1346 | abort (); /* ??? return NULL? */ | |
1347 | } | |
1348 | arg_type = va_arg (ap, enum cgen_cpu_open_arg); | |
1349 | } | |
1350 | va_end (ap); | |
1351 | ||
1352 | /* mach unspecified means "all" */ | |
1353 | if (machs == 0) | |
1354 | machs = (1 << MAX_MACHS) - 1; | |
1355 | /* base mach is always selected */ | |
1356 | machs |= 1; | |
1357 | /* isa unspecified means "all" */ | |
1358 | if (isas == 0) | |
1359 | isas = (1 << MAX_ISAS) - 1; | |
1360 | if (endian == CGEN_ENDIAN_UNKNOWN) | |
1361 | { | |
1362 | /* ??? If target has only one, could have a default. */ | |
1363 | fprintf (stderr, "m32r_cgen_cpu_open: no endianness specified\n"); | |
1364 | abort (); | |
1365 | } | |
1366 | ||
1367 | cd->isas = isas; | |
1368 | cd->machs = machs; | |
1369 | cd->endian = endian; | |
1370 | /* FIXME: for the sparc case we can determine insn-endianness statically. | |
1371 | The worry here is where both data and insn endian can be independently | |
1372 | chosen, in which case this function will need another argument. | |
1373 | Actually, will want to allow for more arguments in the future anyway. */ | |
1374 | cd->insn_endian = endian; | |
1375 | ||
1376 | /* Table (re)builder. */ | |
1377 | cd->rebuild_tables = m32r_cgen_rebuild_tables; | |
1378 | m32r_cgen_rebuild_tables (cd); | |
1379 | ||
6bb95a0f | 1380 | /* Default to not allowing signed overflow. */ |
77343c58 | 1381 | cd->signed_overflow_ok_p = 0; |
cfcdbe97 | 1382 | |
252b5132 RH |
1383 | return (CGEN_CPU_DESC) cd; |
1384 | } | |
1385 | ||
1386 | /* Cover fn to m32r_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. | |
1387 | MACH_NAME is the bfd name of the mach. */ | |
1388 | ||
1389 | CGEN_CPU_DESC | |
1390 | m32r_cgen_cpu_open_1 (mach_name, endian) | |
1391 | const char *mach_name; | |
1392 | enum cgen_endian endian; | |
1393 | { | |
1394 | return m32r_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, | |
1395 | CGEN_CPU_OPEN_ENDIAN, endian, | |
1396 | CGEN_CPU_OPEN_END); | |
1397 | } | |
1398 | ||
1399 | /* Close a cpu table. | |
1400 | ??? This can live in a machine independent file, but there's currently | |
1401 | no place to put this file (there's no libcgen). libopcodes is the wrong | |
1402 | place as some simulator ports use this but they don't use libopcodes. */ | |
1403 | ||
1404 | void | |
1405 | m32r_cgen_cpu_close (cd) | |
1406 | CGEN_CPU_DESC cd; | |
1407 | { | |
1408 | if (cd->insn_table.init_entries) | |
1409 | free ((CGEN_INSN *) cd->insn_table.init_entries); | |
1410 | if (cd->hw_table.entries) | |
1411 | free ((CGEN_HW_ENTRY *) cd->hw_table.entries); | |
1412 | free (cd); | |
1413 | } | |
1414 |