projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 252b5132 RH |
1 | /* Instruction opcode header for m32r. |
| 2 | ||
| 3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
| 4 | ||
| 5 | Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. | |
| 6 | ||
| 7 | This file is part of the GNU Binutils and/or GDB, the GNU debugger. | |
| 8 | ||
| 9 | This program is free software; you can redistribute it and/or modify | |
| 10 | it under the terms of the GNU General Public License as published by | |
| 11 | the Free Software Foundation; either version 2, or (at your option) | |
| 12 | any later version. | |
| 13 | ||
| 14 | This program is distributed in the hope that it will be useful, | |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | GNU General Public License for more details. | |
| 18 | ||
| 19 | You should have received a copy of the GNU General Public License along | |
| 20 | with this program; if not, write to the Free Software Foundation, Inc., | |
| 21 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
| 22 | ||
| 23 | */ | |
| 24 | ||
| 25 | #ifndef M32R_OPC_H | |
| 26 | #define M32R_OPC_H | |
| 27 | ||
| 28 | /* -- opc.h */ | |
| 29 | ||
| 30 | #undef CGEN_DIS_HASH_SIZE | |
| 31 | #define CGEN_DIS_HASH_SIZE 256 | |
| 32 | #undef CGEN_DIS_HASH | |
| 33 | #define X(b) (((unsigned char *) (b))[0] & 0xf0) | |
| 34 | #define CGEN_DIS_HASH(buffer, value) \ | |
| 35 | (X (buffer) | \ | |
| 36 | (X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \ | |
| 37 | : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \ | |
| 38 | : X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \ | |
| 39 | : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4))) | |
| 40 | ||
| 41 | /* -- */ | |
| 42 | /* Enum declaration for m32r instruction types. */ | |
| 43 | typedef enum cgen_insn_type { | |
| 44 | M32R_INSN_INVALID, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_AND | |
| 45 | , M32R_INSN_AND3, M32R_INSN_OR, M32R_INSN_OR3, M32R_INSN_XOR | |
| 46 | , M32R_INSN_XOR3, M32R_INSN_ADDI, M32R_INSN_ADDV, M32R_INSN_ADDV3 | |
| 47 | , M32R_INSN_ADDX, M32R_INSN_BC8, M32R_INSN_BC24, M32R_INSN_BEQ | |
| 48 | , M32R_INSN_BEQZ, M32R_INSN_BGEZ, M32R_INSN_BGTZ, M32R_INSN_BLEZ | |
| 49 | , M32R_INSN_BLTZ, M32R_INSN_BNEZ, M32R_INSN_BL8, M32R_INSN_BL24 | |
| 50 | , M32R_INSN_BNC8, M32R_INSN_BNC24, M32R_INSN_BNE, M32R_INSN_BRA8 | |
| 51 | , M32R_INSN_BRA24 | |
| 52 | , M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU, M32R_INSN_CMPUI | |
| 53 | , M32R_INSN_DIV, M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU | |
| 54 | , M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD, M32R_INSN_LD_D | |
| 55 | , M32R_INSN_LDB, M32R_INSN_LDB_D, M32R_INSN_LDH, M32R_INSN_LDH_D | |
| 56 | , M32R_INSN_LDUB, M32R_INSN_LDUB_D, M32R_INSN_LDUH, M32R_INSN_LDUH_D | |
| 57 | , M32R_INSN_LD_PLUS, M32R_INSN_LD24, M32R_INSN_LDI8, M32R_INSN_LDI16 | |
| 58 | , M32R_INSN_LOCK, M32R_INSN_MACHI | |
| 59 | , M32R_INSN_MACLO | |
| 60 | , M32R_INSN_MACWHI | |
| 61 | , M32R_INSN_MACWLO | |
| 62 | , M32R_INSN_MUL, M32R_INSN_MULHI | |
| 63 | , M32R_INSN_MULLO | |
| 64 | , M32R_INSN_MULWHI | |
| 65 | , M32R_INSN_MULWLO | |
| 66 | , M32R_INSN_MV, M32R_INSN_MVFACHI | |
| 67 | , M32R_INSN_MVFACLO | |
| 68 | , M32R_INSN_MVFACMI | |
| 69 | , M32R_INSN_MVFC, M32R_INSN_MVTACHI | |
| 70 | , M32R_INSN_MVTACLO | |
| 71 | , M32R_INSN_MVTC, M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT | |
| 72 | , M32R_INSN_RAC | |
| 73 | , M32R_INSN_RACH | |
| 74 | , M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3 | |
| 75 | , M32R_INSN_SLLI, M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI | |
| 76 | , M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST | |
| 77 | , M32R_INSN_ST_D, M32R_INSN_STB, M32R_INSN_STB_D, M32R_INSN_STH | |
| 78 | , M32R_INSN_STH_D, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS, M32R_INSN_SUB | |
| 79 | , M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP, M32R_INSN_UNLOCK | |
| 80 | , M32R_INSN_MAX | |
| 81 | } CGEN_INSN_TYPE; | |
| 82 | ||
| 83 | /* Index of `invalid' insn place holder. */ | |
| 84 | #define CGEN_INSN_INVALID M32R_INSN_INVALID | |
| 85 | ||
| 86 | /* Total number of insns in table. */ | |
| 87 | #define MAX_INSNS ((int) M32R_INSN_MAX) | |
| 88 | ||
| 89 | /* This struct records data prior to insertion or after extraction. */ | |
| 90 | struct cgen_fields | |
| 91 | { | |
| 92 | int length; | |
| 93 | long f_nil; | |
| 94 | long f_op1; | |
| 95 | long f_op2; | |
| 96 | long f_cond; | |
| 97 | long f_r1; | |
| 98 | long f_r2; | |
| 99 | long f_simm8; | |
| 100 | long f_simm16; | |
| 101 | long f_shift_op2; | |
| 102 | long f_uimm4; | |
| 103 | long f_uimm5; | |
| 104 | long f_uimm16; | |
| 105 | long f_uimm24; | |
| 106 | long f_hi16; | |
| 107 | long f_disp8; | |
| 108 | long f_disp16; | |
| 109 | long f_disp24; | |
| 110 | }; | |
| 111 | ||
| 112 | #define CGEN_INIT_PARSE(od) \ | |
| 113 | {\ | |
| 114 | } | |
| 115 | #define CGEN_INIT_INSERT(od) \ | |
| 116 | {\ | |
| 117 | } | |
| 118 | #define CGEN_INIT_EXTRACT(od) \ | |
| 119 | {\ | |
| 120 | } | |
| 121 | #define CGEN_INIT_PRINT(od) \ | |
| 122 | {\ | |
| 123 | } | |
| 124 | ||
| 125 | ||
| 126 | #endif /* M32R_OPC_H */ |