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[deliverable/binutils-gdb.git] / opcodes / mips-dis.c
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252b5132 1/* Print mips instructions for GDB, the GNU debugger, or for objdump.
060d22b0 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
794ac9d0 3 2000, 2001, 2002, 2003
73da6b6b 4 Free Software Foundation, Inc.
252b5132
RH		 5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
7This file is part of GDB, GAS, and the GNU binutils.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2 of the License, or
12(at your option) any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
20along with this program; if not, write to the Free Software
21Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22
252b5132
RH		 23#include "sysdep.h"
24#include "dis-asm.h"
640c0ccd 25#include "libiberty.h"
252b5132
RH		 26#include "opcode/mips.h"
27#include "opintl.h"
28
29/* FIXME: These are needed to figure out if the code is mips16 or
30 not. The low bit of the address is often a good indicator. No
31 symbol table is available when this code runs out in an embedded
7f6621cd 32 system as when it is used for disassembler support in a monitor. */
252b5132
RH		 33
34#if !defined(EMBEDDED_ENV)
35#define SYMTAB_AVAILABLE 1
36#include "elf-bfd.h"
37#include "elf/mips.h"
38#endif
39
aa5f19f2
NC		 40/* Mips instructions are at maximum this many bytes long. */
41#define INSNLEN 4
42
640c0ccd
CD		 43static void set_default_mips_dis_options
44 PARAMS ((struct disassemble_info *));
45static void parse_mips_dis_option
46 PARAMS ((const char *, unsigned int));
47static void parse_mips_dis_options
48 PARAMS ((const char *));
aa5f19f2
NC		 49static int _print_insn_mips
50 PARAMS ((bfd_vma, struct disassemble_info *, enum bfd_endian));
51static int print_insn_mips
52 PARAMS ((bfd_vma, unsigned long int, struct disassemble_info *));
794ac9d0 53static void print_insn_args
aa5f19f2
NC		 54 PARAMS ((const char *, unsigned long, bfd_vma, struct disassemble_info *));
55static int print_insn_mips16
56 PARAMS ((bfd_vma, struct disassemble_info *));
7fa108a4
AJ		 57static int is_newabi
58 PARAMS ((Elf_Internal_Ehdr *));
252b5132 59static void print_mips16_insn_arg
b34976b6 60 PARAMS ((int, const struct mips_opcode *, int, bfd_boolean, int, bfd_vma,
252b5132 61 struct disassemble_info *));
252b5132 62\f
aa5f19f2 63/* FIXME: These should be shared with gdb somehow. */
252b5132 64
bbcc0807
CD		 65struct mips_cp0sel_name {
66 unsigned int cp0reg;
67 unsigned int sel;
68 const char * const name;
69};
70
252b5132 71/* The mips16 register names. */
7f6621cd 72static const char * const mips16_reg_names[] = {
252b5132
RH		 73 "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
74};
fb48caed 75
640c0ccd
CD		 76static const char * const mips_gpr_names_numeric[32] = {
77 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
78 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
79 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
80 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
aa5f19f2
NC		 81};
82
640c0ccd
CD		 83static const char * const mips_gpr_names_oldabi[32] = {
84 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
85 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
86 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
87 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
aa5f19f2
NC		 88};
89
640c0ccd
CD		 90static const char * const mips_gpr_names_newabi[32] = {
91 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
92 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
93 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
94 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
95};
96
97static const char * const mips_fpr_names_numeric[32] = {
98 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
99 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
100 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
101 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
102};
103
104static const char * const mips_fpr_names_32[32] = {
105 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
106 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
107 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
108 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
109};
110
111static const char * const mips_fpr_names_n32[32] = {
112 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
113 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
114 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
115 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
116};
117
118static const char * const mips_fpr_names_64[32] = {
119 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
120 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
121 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
122 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
123};
124
125static const char * const mips_cp0_names_numeric[32] = {
126 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
127 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
128 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
129 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
130};
131
132static const char * const mips_cp0_names_mips3264[32] = {
133 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
134 "c0_context", "c0_pagemask", "c0_wired", "$7",
135 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
136 "c0_status", "c0_cause", "c0_epc", "c0_prid",
137 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
138 "c0_xcontext", "$21", "$22", "c0_debug",
139 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
140 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
141};
142
bbcc0807
CD		 143static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = {
144 { 16, 1, "c0_config1" },
145 { 16, 2, "c0_config2" },
146 { 16, 3, "c0_config3" },
147 { 18, 1, "c0_watchlo,1" },
148 { 18, 2, "c0_watchlo,2" },
149 { 18, 3, "c0_watchlo,3" },
150 { 18, 4, "c0_watchlo,4" },
151 { 18, 5, "c0_watchlo,5" },
152 { 18, 6, "c0_watchlo,6" },
153 { 18, 7, "c0_watchlo,7" },
154 { 19, 1, "c0_watchhi,1" },
155 { 19, 2, "c0_watchhi,2" },
156 { 19, 3, "c0_watchhi,3" },
157 { 19, 4, "c0_watchhi,4" },
158 { 19, 5, "c0_watchhi,5" },
159 { 19, 6, "c0_watchhi,6" },
160 { 19, 7, "c0_watchhi,7" },
161 { 25, 1, "c0_perfcnt,1" },
162 { 25, 2, "c0_perfcnt,2" },
163 { 25, 3, "c0_perfcnt,3" },
164 { 25, 4, "c0_perfcnt,4" },
165 { 25, 5, "c0_perfcnt,5" },
166 { 25, 6, "c0_perfcnt,6" },
167 { 25, 7, "c0_perfcnt,7" },
168 { 27, 1, "c0_cacheerr,1" },
169 { 27, 2, "c0_cacheerr,2" },
170 { 27, 3, "c0_cacheerr,3" },
171 { 28, 1, "c0_datalo" },
172 { 29, 1, "c0_datahi" }
173};
174
af7ee8bf
CD		 175static const char * const mips_cp0_names_mips3264r2[32] = {
176 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
177 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
178 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
179 "c0_status", "c0_cause", "c0_epc", "c0_prid",
180 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
181 "c0_xcontext", "$21", "$22", "c0_debug",
182 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
183 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
184};
185
bbcc0807
CD		 186static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = {
187 { 4, 1, "c0_contextconfig" },
188 { 5, 1, "c0_pagegrain" },
189 { 12, 1, "c0_intctl" },
190 { 12, 2, "c0_srsctl" },
191 { 12, 3, "c0_srsmap" },
192 { 15, 1, "c0_ebase" },
193 { 16, 1, "c0_config1" },
194 { 16, 2, "c0_config2" },
195 { 16, 3, "c0_config3" },
196 { 18, 1, "c0_watchlo,1" },
197 { 18, 2, "c0_watchlo,2" },
198 { 18, 3, "c0_watchlo,3" },
199 { 18, 4, "c0_watchlo,4" },
200 { 18, 5, "c0_watchlo,5" },
201 { 18, 6, "c0_watchlo,6" },
202 { 18, 7, "c0_watchlo,7" },
203 { 19, 1, "c0_watchhi,1" },
204 { 19, 2, "c0_watchhi,2" },
205 { 19, 3, "c0_watchhi,3" },
206 { 19, 4, "c0_watchhi,4" },
207 { 19, 5, "c0_watchhi,5" },
208 { 19, 6, "c0_watchhi,6" },
209 { 19, 7, "c0_watchhi,7" },
210 { 23, 1, "c0_tracecontrol" },
211 { 23, 2, "c0_tracecontrol2" },
212 { 23, 3, "c0_usertracedata" },
213 { 23, 4, "c0_tracebpc" },
214 { 25, 1, "c0_perfcnt,1" },
215 { 25, 2, "c0_perfcnt,2" },
216 { 25, 3, "c0_perfcnt,3" },
217 { 25, 4, "c0_perfcnt,4" },
218 { 25, 5, "c0_perfcnt,5" },
219 { 25, 6, "c0_perfcnt,6" },
220 { 25, 7, "c0_perfcnt,7" },
221 { 27, 1, "c0_cacheerr,1" },
222 { 27, 2, "c0_cacheerr,2" },
223 { 27, 3, "c0_cacheerr,3" },
224 { 28, 1, "c0_datalo" },
225 { 28, 2, "c0_taglo1" },
226 { 28, 3, "c0_datalo1" },
227 { 28, 4, "c0_taglo2" },
228 { 28, 5, "c0_datalo2" },
229 { 28, 6, "c0_taglo3" },
230 { 28, 7, "c0_datalo3" },
231 { 29, 1, "c0_datahi" },
232 { 29, 2, "c0_taghi1" },
233 { 29, 3, "c0_datahi1" },
234 { 29, 4, "c0_taghi2" },
235 { 29, 5, "c0_datahi2" },
236 { 29, 6, "c0_taghi3" },
237 { 29, 7, "c0_datahi3" },
238};
239
640c0ccd
CD		 240/* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
241static const char * const mips_cp0_names_sb1[32] = {
242 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
243 "c0_context", "c0_pagemask", "c0_wired", "$7",
244 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
245 "c0_status", "c0_cause", "c0_epc", "c0_prid",
246 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
247 "c0_xcontext", "$21", "$22", "c0_debug",
248 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
249 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
250};
251
bbcc0807
CD		 252static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = {
253 { 16, 1, "c0_config1" },
254 { 18, 1, "c0_watchlo,1" },
255 { 19, 1, "c0_watchhi,1" },
256 { 22, 0, "c0_perftrace" },
257 { 23, 3, "c0_edebug" },
258 { 25, 1, "c0_perfcnt,1" },
259 { 25, 2, "c0_perfcnt,2" },
260 { 25, 3, "c0_perfcnt,3" },
261 { 25, 4, "c0_perfcnt,4" },
262 { 25, 5, "c0_perfcnt,5" },
263 { 25, 6, "c0_perfcnt,6" },
264 { 25, 7, "c0_perfcnt,7" },
265 { 26, 1, "c0_buserr_pa" },
266 { 27, 1, "c0_cacheerr_d" },
267 { 27, 3, "c0_cacheerr_d_pa" },
268 { 28, 1, "c0_datalo_i" },
269 { 28, 2, "c0_taglo_d" },
270 { 28, 3, "c0_datalo_d" },
271 { 29, 1, "c0_datahi_i" },
272 { 29, 2, "c0_taghi_d" },
273 { 29, 3, "c0_datahi_d" },
274};
275
af7ee8bf
CD		 276static const char * const mips_hwr_names_numeric[32] = {
277 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
278 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
279 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
280 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
281};
282
283static const char * const mips_hwr_names_mips3264r2[32] = {
284 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
285 "$4", "$5", "$6", "$7",
286 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
287 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
288 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
289};
290
640c0ccd
CD		 291struct mips_abi_choice {
292 const char *name;
293 const char * const *gpr_names;
294 const char * const *fpr_names;
295};
296
297struct mips_abi_choice mips_abi_choices[] = {
298 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
299 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
300 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
301 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
302};
303
304struct mips_arch_choice {
305 const char *name;
306 int bfd_mach_valid;
307 unsigned long bfd_mach;
308 int processor;
309 int isa;
310 const char * const *cp0_names;
bbcc0807
CD		 311 const struct mips_cp0sel_name *cp0sel_names;
312 unsigned int cp0sel_names_len;
af7ee8bf 313 const char * const *hwr_names;
640c0ccd
CD		 314};
315
bbcc0807 316const struct mips_arch_choice mips_arch_choices[] = {
640c0ccd 317 { "numeric", 0, 0, 0, 0,
bbcc0807
CD		 318 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
319
640c0ccd 320 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
bbcc0807 321 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 322 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
bbcc0807 323 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 324 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
bbcc0807 325 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 326 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
bbcc0807 327 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 328 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
bbcc0807 329 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 330 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
bbcc0807 331 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 332 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
bbcc0807 333 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 334 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
bbcc0807 335 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 336 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
bbcc0807 337 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 338 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
bbcc0807 339 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 340 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
bbcc0807 341 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 342 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
bbcc0807 343 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 344 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
bbcc0807 345 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 346 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
bbcc0807 347 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 348 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
bbcc0807 349 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 350 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
bbcc0807 351 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 352 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
bbcc0807 353 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 354 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
bbcc0807 355 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 356 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
bbcc0807
CD		 357 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
358
640c0ccd
CD		 359 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
360 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
361 _MIPS32 Architecture For Programmers Volume I: Introduction to the
362 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
363 page 1. */
364 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
365 ISA_MIPS32 | INSN_MIPS16,
bbcc0807
CD		 366 mips_cp0_names_mips3264,
367 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
368 mips_hwr_names_numeric },
369
af7ee8bf
CD		 370 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
371 ISA_MIPS32R2 | INSN_MIPS16,
bbcc0807
CD		 372 mips_cp0_names_mips3264r2,
373 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
374 mips_hwr_names_mips3264r2 },
375
640c0ccd
CD		 376 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
377 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
378 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
bbcc0807
CD		 379 mips_cp0_names_mips3264,
380 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
381 mips_hwr_names_numeric },
382
640c0ccd
CD		 383 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
384 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
bbcc0807
CD		 385 mips_cp0_names_sb1,
386 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
387 mips_hwr_names_numeric },
640c0ccd
CD		 388
389 /* This entry, mips16, is here only for ISA/processor selection; do
390 not print its name. */
391 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
bbcc0807 392 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd
CD		 393};
394
395/* ISA and processor type to disassemble for, and register names to use.
396 set_default_mips_dis_options and parse_mips_dis_options fill in these
397 values. */
398static int mips_processor;
399static int mips_isa;
400static const char * const *mips_gpr_names;
401static const char * const *mips_fpr_names;
402static const char * const *mips_cp0_names;
bbcc0807
CD		 403static const struct mips_cp0sel_name *mips_cp0sel_names;
404static int mips_cp0sel_names_len;
af7ee8bf 405static const char * const *mips_hwr_names;
640c0ccd
CD		 406
407static const struct mips_abi_choice *choose_abi_by_name
408 PARAMS ((const char *, unsigned int));
409static const struct mips_arch_choice *choose_arch_by_name
410 PARAMS ((const char *, unsigned int));
411static const struct mips_arch_choice *choose_arch_by_number
412 PARAMS ((unsigned long));
bbcc0807
CD		 413static const struct mips_cp0sel_name *lookup_mips_cp0sel_name
414 PARAMS ((const struct mips_cp0sel_name *, unsigned int, unsigned int,
415 unsigned int));
640c0ccd
CD		 416\f
417static const struct mips_abi_choice *
418choose_abi_by_name (name, namelen)
419 const char *name;
420 unsigned int namelen;
421{
422 const struct mips_abi_choice *c;
423 unsigned int i;
424
425 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
426 {
427 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
428 && strlen (mips_abi_choices[i].name) == namelen)
429 c = &mips_abi_choices[i];
430 }
431 return c;
432}
433
434static const struct mips_arch_choice *
435choose_arch_by_name (name, namelen)
436 const char *name;
437 unsigned int namelen;
438{
439 const struct mips_arch_choice *c = NULL;
440 unsigned int i;
441
442 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
443 {
444 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
445 && strlen (mips_arch_choices[i].name) == namelen)
446 c = &mips_arch_choices[i];
447 }
448 return c;
449}
450
451static const struct mips_arch_choice *
452choose_arch_by_number (mach)
453 unsigned long mach;
454{
455 static unsigned long hint_bfd_mach;
456 static const struct mips_arch_choice *hint_arch_choice;
457 const struct mips_arch_choice *c;
458 unsigned int i;
459
460 /* We optimize this because even if the user specifies no
461 flags, this will be done for every instruction! */
462 if (hint_bfd_mach == mach
463 && hint_arch_choice != NULL
464 && hint_arch_choice->bfd_mach == hint_bfd_mach)
465 return hint_arch_choice;
466
467 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
468 {
469 if (mips_arch_choices[i].bfd_mach_valid
470 && mips_arch_choices[i].bfd_mach == mach)
471 {
472 c = &mips_arch_choices[i];
473 hint_bfd_mach = mach;
474 hint_arch_choice = c;
475 }
476 }
477 return c;
478}
479
480void
481set_default_mips_dis_options (info)
482 struct disassemble_info *info;
483{
484 const struct mips_arch_choice *chosen_arch;
485
486 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
af7ee8bf 487 and numeric FPR, CP0 register, and HWR names. */
640c0ccd
CD		 488 mips_isa = ISA_MIPS3;
489 mips_processor = CPU_R3000;
490 mips_gpr_names = mips_gpr_names_oldabi;
491 mips_fpr_names = mips_fpr_names_numeric;
492 mips_cp0_names = mips_cp0_names_numeric;
bbcc0807
CD		 493 mips_cp0sel_names = NULL;
494 mips_cp0sel_names_len = 0;
af7ee8bf 495 mips_hwr_names = mips_hwr_names_numeric;
640c0ccd
CD		 496
497 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
498 if (info->flavour == bfd_target_elf_flavour && info->symbols != NULL)
499 {
500 Elf_Internal_Ehdr *header;
501
502 header = elf_elfheader (bfd_asymbol_bfd (*(info->symbols)));
503 if (is_newabi (header))
504 mips_gpr_names = mips_gpr_names_newabi;
505 }
506
507 /* Set ISA, architecture, and cp0 register names as best we can. */
508#if ! SYMTAB_AVAILABLE
509 /* This is running out on a target machine, not in a host tool.
510 FIXME: Where does mips_target_info come from? */
511 target_processor = mips_target_info.processor;
512 mips_isa = mips_target_info.isa;
513#else
514 chosen_arch = choose_arch_by_number (info->mach);
515 if (chosen_arch != NULL)
516 {
517 mips_processor = chosen_arch->processor;
518 mips_isa = chosen_arch->isa;
bbcc0807
CD		 519 mips_cp0_names = chosen_arch->cp0_names;
520 mips_cp0sel_names = chosen_arch->cp0sel_names;
521 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
522 mips_hwr_names = chosen_arch->hwr_names;
640c0ccd
CD		 523 }
524#endif
525}
526
527void
528parse_mips_dis_option (option, len)
529 const char *option;
530 unsigned int len;
531{
532 unsigned int i, optionlen, vallen;
533 const char *val;
534 const struct mips_abi_choice *chosen_abi;
535 const struct mips_arch_choice *chosen_arch;
536
537 /* Look for the = that delimits the end of the option name. */
538 for (i = 0; i < len; i++)
539 {
540 if (option[i] == '=')
541 break;
542 }
543 if (i == 0) /* Invalid option: no name before '='. */
544 return;
545 if (i == len) /* Invalid option: no '='. */
546 return;
547 if (i == (len - 1)) /* Invalid option: no value after '='. */
548 return;
549
550 optionlen = i;
551 val = option + (optionlen + 1);
552 vallen = len - (optionlen + 1);
553
554 if (strncmp("gpr-names", option, optionlen) == 0
555 && strlen("gpr-names") == optionlen)
556 {
557 chosen_abi = choose_abi_by_name (val, vallen);
bbcc0807 558 if (chosen_abi != NULL)
640c0ccd
CD		 559 mips_gpr_names = chosen_abi->gpr_names;
560 return;
561 }
562
563 if (strncmp("fpr-names", option, optionlen) == 0
564 && strlen("fpr-names") == optionlen)
565 {
566 chosen_abi = choose_abi_by_name (val, vallen);
bbcc0807 567 if (chosen_abi != NULL)
640c0ccd
CD		 568 mips_fpr_names = chosen_abi->fpr_names;
569 return;
570 }
571
572 if (strncmp("cp0-names", option, optionlen) == 0
573 && strlen("cp0-names") == optionlen)
574 {
575 chosen_arch = choose_arch_by_name (val, vallen);
bbcc0807
CD		 576 if (chosen_arch != NULL)
577 {
578 mips_cp0_names = chosen_arch->cp0_names;
579 mips_cp0sel_names = chosen_arch->cp0sel_names;
580 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
581 }
640c0ccd
CD		 582 return;
583 }
584
af7ee8bf
CD		 585 if (strncmp("hwr-names", option, optionlen) == 0
586 && strlen("hwr-names") == optionlen)
587 {
588 chosen_arch = choose_arch_by_name (val, vallen);
bbcc0807 589 if (chosen_arch != NULL)
af7ee8bf
CD		 590 mips_hwr_names = chosen_arch->hwr_names;
591 return;
592 }
593
640c0ccd
CD		 594 if (strncmp("reg-names", option, optionlen) == 0
595 && strlen("reg-names") == optionlen)
596 {
597 /* We check both ABI and ARCH here unconditionally, so
598 that "numeric" will do the desirable thing: select
599 numeric register names for all registers. Other than
600 that, a given name probably won't match both. */
601 chosen_abi = choose_abi_by_name (val, vallen);
602 if (chosen_abi != NULL)
603 {
bbcc0807
CD		 604 mips_gpr_names = chosen_abi->gpr_names;
605 mips_fpr_names = chosen_abi->fpr_names;
640c0ccd
CD		 606 }
607 chosen_arch = choose_arch_by_name (val, vallen);
608 if (chosen_arch != NULL)
609 {
bbcc0807
CD		 610 mips_cp0_names = chosen_arch->cp0_names;
611 mips_cp0sel_names = chosen_arch->cp0sel_names;
612 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
613 mips_hwr_names = chosen_arch->hwr_names;
640c0ccd
CD		 614 }
615 return;
616 }
617
618 /* Invalid option. */
619}
620
621void
622parse_mips_dis_options (options)
623 const char *options;
624{
625 const char *option_end;
626
627 if (options == NULL)
628 return;
629
630 while (*options != '\0')
631 {
632 /* Skip empty options. */
633 if (*options == ',')
634 {
635 options++;
636 continue;
637 }
638
639 /* We know that *options is neither NUL or a comma. */
640 option_end = options + 1;
641 while (*option_end != ',' && *option_end != '\0')
642 option_end++;
643
644 parse_mips_dis_option (options, option_end - options);
645
646 /* Go on to the next one. If option_end points to a comma, it
647 will be skipped above. */
648 options = option_end;
649 }
650}
651
bbcc0807
CD		 652static const struct mips_cp0sel_name *
653lookup_mips_cp0sel_name(names, len, cp0reg, sel)
654 const struct mips_cp0sel_name *names;
655 unsigned int len, cp0reg, sel;
656{
657 unsigned int i;
658
659 for (i = 0; i < len; i++)
660 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
661 return &names[i];
662 return NULL;
663}
252b5132 664\f
7f6621cd 665/* Print insn arguments for 32/64-bit code. */
aa5f19f2 666
794ac9d0
CD		 667static void
668print_insn_args (d, l, pc, info)
252b5132
RH		 669 const char *d;
670 register unsigned long int l;
671 bfd_vma pc;
672 struct disassemble_info *info;
673{
794ac9d0 674 int op, delta;
252b5132 675
794ac9d0 676 for (; *d != '\0'; d++)
252b5132 677 {
af7ee8bf
CD		 678 switch (*d)
679 {
794ac9d0
CD		 680 case ',':
681 case '(':
682 case ')':
683 case '[':
684 case ']':
685 (*info->fprintf_func) (info->stream, "%c", *d);
686 break;
687
688 case '+':
689 /* Extension character; switch for second char. */
690 d++;
691 switch (*d)
692 {
693 case '\0':
694 /* xgettext:c-format */
695 (*info->fprintf_func) (info->stream,
696 _("# internal error, incomplete extension sequence (+)"));
697 return;
698
699 case 'A':
700 (*info->fprintf_func) (info->stream, "0x%x",
701 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
702 break;
703
704 case 'B':
705 (*info->fprintf_func) (info->stream, "0x%x",
706 (((l >> OP_SH_INSMSB) & OP_MASK_INSMSB)
707 - ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT)
708 + 1));
709 break;
710
711 case 'C':
712 (*info->fprintf_func) (info->stream, "0x%x",
713 (((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD)
714 + 1));
715 break;
716
717 case 'D':
718 {
719 const struct mips_cp0sel_name *n;
720 unsigned int cp0reg, sel;
721
722 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
723 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
724
725 /* CP0 register including 'sel' code for mtcN (et al.), to be
726 printed textually if known. If not known, print both
727 CP0 register name and sel numerically since CP0 register
728 with sel 0 may have a name unrelated to register being
729 printed. */
730 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
731 mips_cp0sel_names_len, cp0reg, sel);
732 if (n != NULL)
733 (*info->fprintf_func) (info->stream, "%s", n->name);
734 else
735 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
736 break;
737 }
738
739 default:
740 /* xgettext:c-format */
741 (*info->fprintf_func) (info->stream,
742 _("# internal error, undefined extension sequence (+%c)"),
743 *d);
744 return;
745 }
746 break;
747
748 case 's':
749 case 'b':
750 case 'r':
751 case 'v':
752 (*info->fprintf_func) (info->stream, "%s",
753 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
754 break;
755
756 case 't':
757 case 'w':
758 (*info->fprintf_func) (info->stream, "%s",
759 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
760 break;
761
762 case 'i':
763 case 'u':
764 (*info->fprintf_func) (info->stream, "0x%x",
765 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
766 break;
767
768 case 'j': /* Same as i, but sign-extended. */
769 case 'o':
770 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
771 if (delta & 0x8000)
772 delta |= ~0xffff;
773 (*info->fprintf_func) (info->stream, "%d",
774 delta);
775 break;
776
777 case 'h':
778 (*info->fprintf_func) (info->stream, "0x%x",
779 (unsigned int) ((l >> OP_SH_PREFX)
780 & OP_MASK_PREFX));
781 break;
782
783 case 'k':
784 (*info->fprintf_func) (info->stream, "0x%x",
785 (unsigned int) ((l >> OP_SH_CACHE)
786 & OP_MASK_CACHE));
787 break;
788
789 case 'a':
790 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
791 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
792 (*info->print_address_func) (info->target, info);
793 break;
794
795 case 'p':
796 /* Sign extend the displacement. */
797 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
798 if (delta & 0x8000)
799 delta |= ~0xffff;
800 info->target = (delta << 2) + pc + INSNLEN;
801 (*info->print_address_func) (info->target, info);
802 break;
803
804 case 'd':
805 (*info->fprintf_func) (info->stream, "%s",
806 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
807 break;
808
809 case 'U':
810 {
811 /* First check for both rd and rt being equal. */
812 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
813 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
814 (*info->fprintf_func) (info->stream, "%s",
815 mips_gpr_names[reg]);
816 else
817 {
818 /* If one is zero use the other. */
819 if (reg == 0)
820 (*info->fprintf_func) (info->stream, "%s",
821 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
822 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
823 (*info->fprintf_func) (info->stream, "%s",
824 mips_gpr_names[reg]);
825 else /* Bogus, result depends on processor. */
826 (*info->fprintf_func) (info->stream, "%s or %s",
827 mips_gpr_names[reg],
828 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
829 }
830 }
831 break;
832
833 case 'z':
834 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
835 break;
836
837 case '<':
af7ee8bf
CD		 838 (*info->fprintf_func) (info->stream, "0x%x",
839 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
840 break;
794ac9d0
CD		 841
842 case 'c':
af7ee8bf 843 (*info->fprintf_func) (info->stream, "0x%x",
794ac9d0
CD		 844 (l >> OP_SH_CODE) & OP_MASK_CODE);
845 break;
846
847 case 'q':
848 (*info->fprintf_func) (info->stream, "0x%x",
849 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
af7ee8bf
CD		 850 break;
851
852 case 'C':
853 (*info->fprintf_func) (info->stream, "0x%x",
794ac9d0
CD		 854 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
855 break;
856
857 case 'B':
858 (*info->fprintf_func) (info->stream, "0x%x",
859 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
860 break;
861
862 case 'J':
863 (*info->fprintf_func) (info->stream, "0x%x",
864 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
865 break;
866
867 case 'S':
868 case 'V':
869 (*info->fprintf_func) (info->stream, "%s",
870 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
871 break;
872
873 case 'T':
874 case 'W':
875 (*info->fprintf_func) (info->stream, "%s",
876 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
af7ee8bf
CD		 877 break;
878
bbcc0807 879 case 'D':
794ac9d0
CD		 880 (*info->fprintf_func) (info->stream, "%s",
881 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
882 break;
883
884 case 'R':
885 (*info->fprintf_func) (info->stream, "%s",
886 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
887 break;
888
889 case 'E':
890 /* Coprocessor register for lwcN instructions, et al.
891
892 Note that there is no load/store cp0 instructions, and
893 that FPU (cp1) instructions disassemble this field using
894 'T' format. Therefore, until we gain understanding of
895 cp2 register names, we can simply print the register
896 numbers. */
897 (*info->fprintf_func) (info->stream, "$%d",
898 (l >> OP_SH_RT) & OP_MASK_RT);
899 break;
900
901 case 'G':
902 /* Coprocessor register for mtcN instructions, et al. Note
903 that FPU (cp1) instructions disassemble this field using
904 'S' format. Therefore, we only need to worry about cp0,
905 cp2, and cp3. */
906 op = (l >> OP_SH_OP) & OP_MASK_OP;
907 if (op == OP_OP_COP0)
908 (*info->fprintf_func) (info->stream, "%s",
909 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
910 else
911 (*info->fprintf_func) (info->stream, "$%d",
912 (l >> OP_SH_RD) & OP_MASK_RD);
913 break;
914
915 case 'K':
916 (*info->fprintf_func) (info->stream, "%s",
917 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
918 break;
919
920 case 'N':
921 (*info->fprintf_func) (info->stream, "$fcc%d",
922 (l >> OP_SH_BCC) & OP_MASK_BCC);
923 break;
924
925 case 'M':
926 (*info->fprintf_func) (info->stream, "$fcc%d",
927 (l >> OP_SH_CCC) & OP_MASK_CCC);
928 break;
929
930 case 'P':
931 (*info->fprintf_func) (info->stream, "%d",
932 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
933 break;
934
935 case 'e':
936 (*info->fprintf_func) (info->stream, "%d",
937 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
938 break;
939
940 case '%':
941 (*info->fprintf_func) (info->stream, "%d",
942 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
943 break;
944
945 case 'H':
946 (*info->fprintf_func) (info->stream, "%d",
947 (l >> OP_SH_SEL) & OP_MASK_SEL);
948 break;
949
950 case 'O':
951 (*info->fprintf_func) (info->stream, "%d",
952 (l >> OP_SH_ALN) & OP_MASK_ALN);
953 break;
954
955 case 'Q':
bbcc0807 956 {
794ac9d0
CD		 957 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
958 if ((vsel & 0x10) == 0)
959 {
960 int fmt;
961 vsel &= 0x0f;
962 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
963 if ((vsel & 1) == 0)
964 break;
965 (*info->fprintf_func) (info->stream, "$v%d[%d]",
966 (l >> OP_SH_FT) & OP_MASK_FT,
967 vsel >> 1);
968 }
969 else if ((vsel & 0x08) == 0)
970 {
971 (*info->fprintf_func) (info->stream, "$v%d",
972 (l >> OP_SH_FT) & OP_MASK_FT);
973 }
bbcc0807 974 else
794ac9d0
CD		 975 {
976 (*info->fprintf_func) (info->stream, "0x%x",
977 (l >> OP_SH_FT) & OP_MASK_FT);
978 }
bbcc0807 979 }
794ac9d0
CD		 980 break;
981
982 case 'X':
983 (*info->fprintf_func) (info->stream, "$v%d",
984 (l >> OP_SH_FD) & OP_MASK_FD);
985 break;
986
987 case 'Y':
988 (*info->fprintf_func) (info->stream, "$v%d",
989 (l >> OP_SH_FS) & OP_MASK_FS);
990 break;
991
992 case 'Z':
993 (*info->fprintf_func) (info->stream, "$v%d",
994 (l >> OP_SH_FT) & OP_MASK_FT);
995 break;
bbcc0807 996
af7ee8bf
CD		 997 default:
998 /* xgettext:c-format */
999 (*info->fprintf_func) (info->stream,
794ac9d0 1000 _("# internal error, undefined modifier(%c)"),
af7ee8bf 1001 *d);
794ac9d0 1002 return;
af7ee8bf 1003 }
252b5132
RH		 1004 }
1005}
1006\f
21d34b1c 1007/* Check if the object uses NewABI conventions. */
aa5f19f2
NC		 1008
1009static int
7f6621cd 1010is_newabi (header)
21d34b1c 1011 Elf_Internal_Ehdr *header;
aa5f19f2 1012{
4c563ebf
CD		 1013 /* There are no old-style ABIs which use 64-bit ELF. */
1014 if (header->e_ident[EI_CLASS] == ELFCLASS64)
1015 return 1;
1016
563773fe
TS		 1017 /* If a 32-bit ELF file, n32 is a new-style ABI. */
1018 if ((header->e_flags & EF_MIPS_ABI2) != 0)
21d34b1c 1019 return 1;
252b5132 1020
21d34b1c 1021 return 0;
aa5f19f2
NC		 1022}
1023\f
252b5132
RH		 1024/* Print the mips instruction at address MEMADDR in debugged memory,
1025 on using INFO. Returns length of the instruction, in bytes, which is
aa5f19f2 1026 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
252b5132
RH		 1027 this is little-endian code. */
1028
1029static int
aa5f19f2 1030print_insn_mips (memaddr, word, info)
252b5132
RH		 1031 bfd_vma memaddr;
1032 unsigned long int word;
1033 struct disassemble_info *info;
1034{
1035 register const struct mips_opcode *op;
b34976b6 1036 static bfd_boolean init = 0;
252b5132
RH		 1037 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1038
1039 /* Build a hash table to shorten the search time. */
1040 if (! init)
1041 {
1042 unsigned int i;
1043
1044 for (i = 0; i <= OP_MASK_OP; i++)
1045 {
1046 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1047 {
1048 if (op->pinfo == INSN_MACRO)
1049 continue;
1050 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1051 {
1052 mips_hash[i] = op;
1053 break;
1054 }
1055 }
7f6621cd 1056 }
252b5132
RH		 1057
1058 init = 1;
1059 }
1060
aa5f19f2 1061 info->bytes_per_chunk = INSNLEN;
252b5132 1062 info->display_endian = info->endian;
9bb28706
CD		 1063 info->insn_info_valid = 1;
1064 info->branch_delay_insns = 0;
def7143b 1065 info->data_size = 0;
9bb28706
CD		 1066 info->insn_type = dis_nonbranch;
1067 info->target = 0;
1068 info->target2 = 0;
252b5132
RH		 1069
1070 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1071 if (op != NULL)
1072 {
1073 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1074 {
1075 if (op->pinfo != INSN_MACRO && (word & op->mask) == op->match)
1076 {
1077 register const char *d;
2bd7f1f3 1078
3396de36 1079 /* We always allow to disassemble the jalx instruction. */
640c0ccd 1080 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
3396de36 1081 && strcmp (op->name, "jalx"))
252b5132
RH		 1082 continue;
1083
9bb28706
CD		 1084 /* Figure out instruction type and branch delay information. */
1085 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1086 {
1087 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1088 info->insn_type = dis_jsr;
1089 else
1090 info->insn_type = dis_branch;
1091 info->branch_delay_insns = 1;
1092 }
1093 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1094 | INSN_COND_BRANCH_LIKELY)) != 0)
1095 {
1096 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1097 info->insn_type = dis_condjsr;
1098 else
1099 info->insn_type = dis_condbranch;
1100 info->branch_delay_insns = 1;
1101 }
1102 else if ((op->pinfo & (INSN_STORE_MEMORY
1103 | INSN_LOAD_MEMORY_DELAY)) != 0)
1104 info->insn_type = dis_dref;
1105
252b5132
RH		 1106 (*info->fprintf_func) (info->stream, "%s", op->name);
1107
1108 d = op->args;
1109 if (d != NULL && *d != '\0')
1110 {
7f6621cd 1111 (*info->fprintf_func) (info->stream, "\t");
794ac9d0 1112 print_insn_args (d, word, memaddr, info);
252b5132
RH		 1113 }
1114
aa5f19f2 1115 return INSNLEN;
252b5132
RH		 1116 }
1117 }
1118 }
1119
1120 /* Handle undefined instructions. */
9bb28706 1121 info->insn_type = dis_noninsn;
252b5132 1122 (*info->fprintf_func) (info->stream, "0x%x", word);
aa5f19f2 1123 return INSNLEN;
252b5132 1124}
aa5f19f2 1125\f
252b5132
RH		 1126/* In an environment where we do not know the symbol type of the
1127 instruction we are forced to assume that the low order bit of the
1128 instructions' address may mark it as a mips16 instruction. If we
1129 are single stepping, or the pc is within the disassembled function,
1130 this works. Otherwise, we need a clue. Sometimes. */
1131
aa5f19f2
NC		 1132static int
1133_print_insn_mips (memaddr, info, endianness)
252b5132
RH		 1134 bfd_vma memaddr;
1135 struct disassemble_info *info;
aa5f19f2 1136 enum bfd_endian endianness;
252b5132 1137{
aa5f19f2 1138 bfd_byte buffer[INSNLEN];
252b5132
RH		 1139 int status;
1140
640c0ccd
CD		 1141 set_default_mips_dis_options (info);
1142 parse_mips_dis_options (info->disassembler_options);
1143
252b5132
RH		 1144#if 1
1145 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
1146 /* Only a few tools will work this way. */
1147 if (memaddr & 0x01)
1148 return print_insn_mips16 (memaddr, info);
e93d7199 1149#endif
252b5132
RH		 1150
1151#if SYMTAB_AVAILABLE
53f32ea5 1152 if (info->mach == bfd_mach_mips16
252b5132
RH		 1153 || (info->flavour == bfd_target_elf_flavour
1154 && info->symbols != NULL
1155 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
1156 == STO_MIPS16)))
1157 return print_insn_mips16 (memaddr, info);
e93d7199 1158#endif
252b5132 1159
aa5f19f2 1160 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
252b5132 1161 if (status == 0)
aa5f19f2
NC		 1162 {
1163 unsigned long insn;
1164
1165 if (endianness == BFD_ENDIAN_BIG)
7f6621cd 1166 insn = (unsigned long) bfd_getb32 (buffer);
aa5f19f2
NC		 1167 else
1168 insn = (unsigned long) bfd_getl32 (buffer);
1169
1170 return print_insn_mips (memaddr, insn, info);
1171 }
252b5132
RH		 1172 else
1173 {
1174 (*info->memory_error_func) (status, memaddr, info);
1175 return -1;
1176 }
1177}
1178
1179int
aa5f19f2 1180print_insn_big_mips (memaddr, info)
252b5132
RH		 1181 bfd_vma memaddr;
1182 struct disassemble_info *info;
1183{
aa5f19f2
NC		 1184 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
1185}
252b5132 1186
aa5f19f2
NC		 1187int
1188print_insn_little_mips (memaddr, info)
1189 bfd_vma memaddr;
1190 struct disassemble_info *info;
1191{
1192 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
252b5132
RH		 1193}
1194\f
1195/* Disassemble mips16 instructions. */
1196
1197static int
1198print_insn_mips16 (memaddr, info)
1199 bfd_vma memaddr;
1200 struct disassemble_info *info;
1201{
1202 int status;
1203 bfd_byte buffer[2];
1204 int length;
1205 int insn;
b34976b6 1206 bfd_boolean use_extend;
252b5132
RH		 1207 int extend = 0;
1208 const struct mips_opcode *op, *opend;
1209
1210 info->bytes_per_chunk = 2;
1211 info->display_endian = info->endian;
252b5132
RH		 1212 info->insn_info_valid = 1;
1213 info->branch_delay_insns = 0;
1214 info->data_size = 0;
1215 info->insn_type = dis_nonbranch;
1216 info->target = 0;
1217 info->target2 = 0;
1218
1219 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1220 if (status != 0)
1221 {
1222 (*info->memory_error_func) (status, memaddr, info);
1223 return -1;
1224 }
1225
1226 length = 2;
1227
1228 if (info->endian == BFD_ENDIAN_BIG)
1229 insn = bfd_getb16 (buffer);
1230 else
1231 insn = bfd_getl16 (buffer);
1232
1233 /* Handle the extend opcode specially. */
b34976b6 1234 use_extend = FALSE;
252b5132
RH		 1235 if ((insn & 0xf800) == 0xf000)
1236 {
b34976b6 1237 use_extend = TRUE;
252b5132
RH		 1238 extend = insn & 0x7ff;
1239
1240 memaddr += 2;
1241
1242 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1243 if (status != 0)
1244 {
1245 (*info->fprintf_func) (info->stream, "extend 0x%x",
1246 (unsigned int) extend);
1247 (*info->memory_error_func) (status, memaddr, info);
1248 return -1;
1249 }
1250
1251 if (info->endian == BFD_ENDIAN_BIG)
1252 insn = bfd_getb16 (buffer);
1253 else
1254 insn = bfd_getl16 (buffer);
1255
1256 /* Check for an extend opcode followed by an extend opcode. */
1257 if ((insn & 0xf800) == 0xf000)
1258 {
1259 (*info->fprintf_func) (info->stream, "extend 0x%x",
1260 (unsigned int) extend);
1261 info->insn_type = dis_noninsn;
1262 return length;
1263 }
1264
1265 length += 2;
1266 }
1267
1268 /* FIXME: Should probably use a hash table on the major opcode here. */
1269
1270 opend = mips16_opcodes + bfd_mips16_num_opcodes;
1271 for (op = mips16_opcodes; op < opend; op++)
1272 {
1273 if (op->pinfo != INSN_MACRO && (insn & op->mask) == op->match)
1274 {
1275 const char *s;
1276
1277 if (strchr (op->args, 'a') != NULL)
1278 {
1279 if (use_extend)
1280 {
1281 (*info->fprintf_func) (info->stream, "extend 0x%x",
1282 (unsigned int) extend);
1283 info->insn_type = dis_noninsn;
1284 return length - 2;
1285 }
1286
b34976b6 1287 use_extend = FALSE;
252b5132
RH		 1288
1289 memaddr += 2;
1290
1291 status = (*info->read_memory_func) (memaddr, buffer, 2,
1292 info);
1293 if (status == 0)
1294 {
b34976b6 1295 use_extend = TRUE;
252b5132
RH		 1296 if (info->endian == BFD_ENDIAN_BIG)
1297 extend = bfd_getb16 (buffer);
1298 else
1299 extend = bfd_getl16 (buffer);
1300 length += 2;
1301 }
1302 }
1303
1304 (*info->fprintf_func) (info->stream, "%s", op->name);
1305 if (op->args[0] != '\0')
1306 (*info->fprintf_func) (info->stream, "\t");
1307
1308 for (s = op->args; *s != '\0'; s++)
1309 {
1310 if (*s == ','
1311 && s[1] == 'w'
1312 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
1313 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
1314 {
1315 /* Skip the register and the comma. */
1316 ++s;
1317 continue;
1318 }
1319 if (*s == ','
1320 && s[1] == 'v'
1321 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
1322 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
1323 {
1324 /* Skip the register and the comma. */
1325 ++s;
1326 continue;
1327 }
1328 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
1329 info);
1330 }
1331
1332 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1333 {
1334 info->branch_delay_insns = 1;
1335 if (info->insn_type != dis_jsr)
1336 info->insn_type = dis_branch;
1337 }
1338
1339 return length;
1340 }
1341 }
1342
1343 if (use_extend)
1344 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
1345 (*info->fprintf_func) (info->stream, "0x%x", insn);
1346 info->insn_type = dis_noninsn;
1347
1348 return length;
1349}
1350
1351/* Disassemble an operand for a mips16 instruction. */
1352
1353static void
1354print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info)
aa5f19f2 1355 char type;
252b5132
RH		 1356 const struct mips_opcode *op;
1357 int l;
b34976b6 1358 bfd_boolean use_extend;
252b5132
RH		 1359 int extend;
1360 bfd_vma memaddr;
1361 struct disassemble_info *info;
1362{
1363 switch (type)
1364 {
1365 case ',':
1366 case '(':
1367 case ')':
1368 (*info->fprintf_func) (info->stream, "%c", type);
1369 break;
1370
1371 case 'y':
1372 case 'w':
aa5f19f2 1373 (*info->fprintf_func) (info->stream, "%s",
252b5132
RH		 1374 mips16_reg_names[((l >> MIPS16OP_SH_RY)
1375 & MIPS16OP_MASK_RY)]);
1376 break;
1377
1378 case 'x':
1379 case 'v':
aa5f19f2 1380 (*info->fprintf_func) (info->stream, "%s",
252b5132
RH		 1381 mips16_reg_names[((l >> MIPS16OP_SH_RX)
1382 & MIPS16OP_MASK_RX)]);
1383 break;
1384
1385 case 'z':
aa5f19f2 1386 (*info->fprintf_func) (info->stream, "%s",
252b5132
RH		 1387 mips16_reg_names[((l >> MIPS16OP_SH_RZ)
1388 & MIPS16OP_MASK_RZ)]);
1389 break;
1390
1391 case 'Z':
aa5f19f2 1392 (*info->fprintf_func) (info->stream, "%s",
252b5132
RH		 1393 mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z)
1394 & MIPS16OP_MASK_MOVE32Z)]);
1395 break;
1396
1397 case '0':
640c0ccd 1398 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
252b5132
RH		 1399 break;
1400
1401 case 'S':
640c0ccd 1402 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
252b5132
RH		 1403 break;
1404
1405 case 'P':
1406 (*info->fprintf_func) (info->stream, "$pc");
1407 break;
1408
1409 case 'R':
640c0ccd 1410 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
252b5132
RH		 1411 break;
1412
1413 case 'X':
aa5f19f2 1414 (*info->fprintf_func) (info->stream, "%s",
640c0ccd
CD		 1415 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1416 & MIPS16OP_MASK_REGR32)]);
252b5132
RH		 1417 break;
1418
1419 case 'Y':
aa5f19f2 1420 (*info->fprintf_func) (info->stream, "%s",
640c0ccd 1421 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
252b5132
RH		 1422 break;
1423
1424 case '<':
1425 case '>':
1426 case '[':
1427 case ']':
1428 case '4':
1429 case '5':
1430 case 'H':
1431 case 'W':
1432 case 'D':
1433 case 'j':
1434 case '6':
1435 case '8':
1436 case 'V':
1437 case 'C':
1438 case 'U':
1439 case 'k':
1440 case 'K':
1441 case 'p':
1442 case 'q':
1443 case 'A':
1444 case 'B':
1445 case 'E':
1446 {
1447 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1448
1449 shift = 0;
1450 signedp = 0;
1451 extbits = 16;
1452 pcrel = 0;
1453 extu = 0;
1454 branch = 0;
1455 switch (type)
1456 {
1457 case '<':
1458 nbits = 3;
1459 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1460 extbits = 5;
1461 extu = 1;
1462 break;
1463 case '>':
1464 nbits = 3;
1465 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1466 extbits = 5;
1467 extu = 1;
1468 break;
1469 case '[':
1470 nbits = 3;
1471 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1472 extbits = 6;
1473 extu = 1;
1474 break;
1475 case ']':
1476 nbits = 3;
1477 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1478 extbits = 6;
1479 extu = 1;
1480 break;
1481 case '4':
1482 nbits = 4;
1483 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1484 signedp = 1;
1485 extbits = 15;
1486 break;
1487 case '5':
1488 nbits = 5;
1489 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1490 info->insn_type = dis_dref;
1491 info->data_size = 1;
1492 break;
1493 case 'H':
1494 nbits = 5;
1495 shift = 1;
1496 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1497 info->insn_type = dis_dref;
1498 info->data_size = 2;
1499 break;
1500 case 'W':
1501 nbits = 5;
1502 shift = 2;
1503 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1504 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1505 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1506 {
1507 info->insn_type = dis_dref;
1508 info->data_size = 4;
1509 }
1510 break;
1511 case 'D':
1512 nbits = 5;
1513 shift = 3;
1514 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1515 info->insn_type = dis_dref;
1516 info->data_size = 8;
1517 break;
1518 case 'j':
1519 nbits = 5;
1520 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1521 signedp = 1;
1522 break;
1523 case '6':
1524 nbits = 6;
1525 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1526 break;
1527 case '8':
1528 nbits = 8;
1529 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1530 break;
1531 case 'V':
1532 nbits = 8;
1533 shift = 2;
1534 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1535 /* FIXME: This might be lw, or it might be addiu to $sp or
1536 $pc. We assume it's load. */
1537 info->insn_type = dis_dref;
1538 info->data_size = 4;
1539 break;
1540 case 'C':
1541 nbits = 8;
1542 shift = 3;
1543 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1544 info->insn_type = dis_dref;
1545 info->data_size = 8;
1546 break;
1547 case 'U':
1548 nbits = 8;
1549 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1550 extu = 1;
1551 break;
1552 case 'k':
1553 nbits = 8;
1554 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1555 signedp = 1;
1556 break;
1557 case 'K':
1558 nbits = 8;
1559 shift = 3;
1560 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1561 signedp = 1;
1562 break;
1563 case 'p':
1564 nbits = 8;
1565 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1566 signedp = 1;
1567 pcrel = 1;
1568 branch = 1;
1569 info->insn_type = dis_condbranch;
1570 break;
1571 case 'q':
1572 nbits = 11;
1573 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1574 signedp = 1;
1575 pcrel = 1;
1576 branch = 1;
1577 info->insn_type = dis_branch;
1578 break;
1579 case 'A':
1580 nbits = 8;
1581 shift = 2;
1582 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1583 pcrel = 1;
1584 /* FIXME: This can be lw or la. We assume it is lw. */
1585 info->insn_type = dis_dref;
1586 info->data_size = 4;
1587 break;
1588 case 'B':
1589 nbits = 5;
1590 shift = 3;
1591 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1592 pcrel = 1;
1593 info->insn_type = dis_dref;
1594 info->data_size = 8;
1595 break;
1596 case 'E':
1597 nbits = 5;
1598 shift = 2;
1599 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1600 pcrel = 1;
1601 break;
1602 default:
1603 abort ();
1604 }
1605
1606 if (! use_extend)
1607 {
1608 if (signedp && immed >= (1 << (nbits - 1)))
1609 immed -= 1 << nbits;
1610 immed <<= shift;
1611 if ((type == '<' || type == '>' || type == '[' || type == ']')
1612 && immed == 0)
1613 immed = 8;
1614 }
1615 else
1616 {
1617 if (extbits == 16)
1618 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1619 else if (extbits == 15)
1620 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1621 else
1622 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1623 immed &= (1 << extbits) - 1;
1624 if (! extu && immed >= (1 << (extbits - 1)))
1625 immed -= 1 << extbits;
1626 }
1627
1628 if (! pcrel)
1629 (*info->fprintf_func) (info->stream, "%d", immed);
1630 else
1631 {
1632 bfd_vma baseaddr;
252b5132
RH		 1633
1634 if (branch)
1635 {
1636 immed *= 2;
1637 baseaddr = memaddr + 2;
1638 }
1639 else if (use_extend)
1640 baseaddr = memaddr - 2;
1641 else
1642 {
1643 int status;
1644 bfd_byte buffer[2];
1645
1646 baseaddr = memaddr;
1647
1648 /* If this instruction is in the delay slot of a jr
1649 instruction, the base address is the address of the
1650 jr instruction. If it is in the delay slot of jalr
1651 instruction, the base address is the address of the
1652 jalr instruction. This test is unreliable: we have
1653 no way of knowing whether the previous word is
1654 instruction or data. */
1655 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1656 info);
1657 if (status == 0
1658 && (((info->endian == BFD_ENDIAN_BIG
1659 ? bfd_getb16 (buffer)
1660 : bfd_getl16 (buffer))
1661 & 0xf800) == 0x1800))
1662 baseaddr = memaddr - 4;
1663 else
1664 {
1665 status = (*info->read_memory_func) (memaddr - 2, buffer,
1666 2, info);
1667 if (status == 0
1668 && (((info->endian == BFD_ENDIAN_BIG
1669 ? bfd_getb16 (buffer)
1670 : bfd_getl16 (buffer))
1671 & 0xf81f) == 0xe800))
1672 baseaddr = memaddr - 2;
1673 }
1674 }
9bb28706
CD		 1675 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1676 (*info->print_address_func) (info->target, info);
252b5132
RH		 1677 }
1678 }
1679 break;
1680
1681 case 'a':
1682 if (! use_extend)
1683 extend = 0;
1684 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
9bb28706
CD		 1685 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1686 (*info->print_address_func) (info->target, info);
252b5132 1687 info->insn_type = dis_jsr;
252b5132
RH		 1688 info->branch_delay_insns = 1;
1689 break;
1690
1691 case 'l':
1692 case 'L':
1693 {
1694 int need_comma, amask, smask;
1695
1696 need_comma = 0;
1697
1698 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1699
1700 amask = (l >> 3) & 7;
1701
1702 if (amask > 0 && amask < 5)
1703 {
640c0ccd 1704 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
252b5132 1705 if (amask > 1)
aa5f19f2 1706 (*info->fprintf_func) (info->stream, "-%s",
640c0ccd 1707 mips_gpr_names[amask + 3]);
252b5132
RH		 1708 need_comma = 1;
1709 }
1710
1711 smask = (l >> 1) & 3;
1712 if (smask == 3)
1713 {
1714 (*info->fprintf_func) (info->stream, "%s??",
1715 need_comma ? "," : "");
1716 need_comma = 1;
1717 }
1718 else if (smask > 0)
1719 {
aa5f19f2 1720 (*info->fprintf_func) (info->stream, "%s%s",
252b5132 1721 need_comma ? "," : "",
640c0ccd 1722 mips_gpr_names[16]);
252b5132 1723 if (smask > 1)
aa5f19f2 1724 (*info->fprintf_func) (info->stream, "-%s",
640c0ccd 1725 mips_gpr_names[smask + 15]);
252b5132
RH		 1726 need_comma = 1;
1727 }
1728
1729 if (l & 1)
1730 {
aa5f19f2 1731 (*info->fprintf_func) (info->stream, "%s%s",
252b5132 1732 need_comma ? "," : "",
640c0ccd 1733 mips_gpr_names[31]);
252b5132
RH		 1734 need_comma = 1;
1735 }
1736
1737 if (amask == 5 || amask == 6)
1738 {
1739 (*info->fprintf_func) (info->stream, "%s$f0",
1740 need_comma ? "," : "");
1741 if (amask == 6)
1742 (*info->fprintf_func) (info->stream, "-$f1");
1743 }
1744 }
1745 break;
1746
1747 default:
aa5f19f2
NC		 1748 /* xgettext:c-format */
1749 (*info->fprintf_func)
1750 (info->stream,
1751 _("# internal disassembler error, unrecognised modifier (%c)"),
1752 type);
252b5132
RH		 1753 abort ();
1754 }
1755}
640c0ccd
CD		 1756
1757void
1758print_mips_disassembler_options (stream)
1759 FILE *stream;
1760{
1761 int i;
1762
1763 fprintf (stream, _("\n\
1764The following MIPS specific disassembler options are supported for use\n\
1765with the -M switch (multiple options should be separated by commas):\n"));
1766
1767 fprintf (stream, _("\n\
1768 gpr-names=ABI Print GPR names according to specified ABI.\n\
1769 Default: based on binary being disassembled.\n"));
1770
1771 fprintf (stream, _("\n\
1772 fpr-names=ABI Print FPR names according to specified ABI.\n\
1773 Default: numeric.\n"));
1774
1775 fprintf (stream, _("\n\
1776 cp0-names=ARCH Print CP0 register names according to\n\
1777 specified architecture.\n\
1778 Default: based on binary being disassembled.\n"));
1779
af7ee8bf
CD		 1780 fprintf (stream, _("\n\
1781 hwr-names=ARCH Print HWR names according to specified \n\
1782 architecture.\n\
1783 Default: based on binary being disassembled.\n"));
1784
640c0ccd
CD		 1785 fprintf (stream, _("\n\
1786 reg-names=ABI Print GPR and FPR names according to\n\
1787 specified ABI.\n"));
1788
1789 fprintf (stream, _("\n\
af7ee8bf 1790 reg-names=ARCH Print CP0 register and HWR names according to\n\
640c0ccd
CD		 1791 specified architecture.\n"));
1792
1793 fprintf (stream, _("\n\
1794 For the options above, the following values are supported for \"ABI\":\n\
1795 "));
1796 for (i = 0; mips_abi_choices[i].name != NULL; i++)
1797 fprintf (stream, " %s", mips_abi_choices[i].name);
1798 fprintf (stream, _("\n"));
1799
1800 fprintf (stream, _("\n\
1801 For the options above, The following values are supported for \"ARCH\":\n\
1802 "));
1803 for (i = 0; mips_arch_choices[i].name != NULL; i++)
1804 if (*mips_arch_choices[i].name != '\0')
1805 fprintf (stream, " %s", mips_arch_choices[i].name);
1806 fprintf (stream, _("\n"));
1807
1808 fprintf (stream, _("\n"));
1809}
GDB Binutils - Deliverables
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