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Change source files over to GPLv3.
[deliverable/binutils-gdb.git] / opcodes / mips-dis.c
CommitLineData
252b5132 1/* Print mips instructions for GDB, the GNU debugger, or for objdump.
060d22b0 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
9b201bb5 3 2000, 2001, 2002, 2003, 2005, 2007
73da6b6b 4 Free Software Foundation, Inc.
252b5132
RH		 5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
9b201bb5 7 This file is part of the GNU opcodes library.
252b5132 8
9b201bb5 9 This library is free software; you can redistribute it and/or modify
47b0e7ad 10 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
252b5132 13
9b201bb5
NC		 14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
252b5132 18
47b0e7ad
NC		 19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
252b5132 23
252b5132
RH		 24#include "sysdep.h"
25#include "dis-asm.h"
640c0ccd 26#include "libiberty.h"
252b5132
RH		 27#include "opcode/mips.h"
28#include "opintl.h"
29
30/* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
7f6621cd 33 system as when it is used for disassembler support in a monitor. */
252b5132
RH		 34
35#if !defined(EMBEDDED_ENV)
36#define SYMTAB_AVAILABLE 1
37#include "elf-bfd.h"
38#include "elf/mips.h"
39#endif
40
aa5f19f2
NC		 41/* Mips instructions are at maximum this many bytes long. */
42#define INSNLEN 4
43
252b5132 44\f
aa5f19f2 45/* FIXME: These should be shared with gdb somehow. */
252b5132 46
47b0e7ad
NC		 47struct mips_cp0sel_name
48{
49 unsigned int cp0reg;
50 unsigned int sel;
51 const char * const name;
bbcc0807
CD		 52};
53
654c225a
TS		 54/* The mips16 registers. */
55static const unsigned int mips16_to_32_reg_map[] =
47b0e7ad 56{
654c225a 57 16, 17, 2, 3, 4, 5, 6, 7
252b5132 58};
fb48caed 59
654c225a
TS		 60#define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
61
62
47b0e7ad
NC		 63static const char * const mips_gpr_names_numeric[32] =
64{
640c0ccd
CD		 65 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
66 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
67 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
68 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
aa5f19f2
NC		 69};
70
47b0e7ad
NC		 71static const char * const mips_gpr_names_oldabi[32] =
72{
640c0ccd
CD		 73 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
74 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
75 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
76 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
aa5f19f2
NC		 77};
78
47b0e7ad
NC		 79static const char * const mips_gpr_names_newabi[32] =
80{
640c0ccd 81 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
0b14f26e 82 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
640c0ccd
CD		 83 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
84 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
85};
86
47b0e7ad
NC		 87static const char * const mips_fpr_names_numeric[32] =
88{
640c0ccd
CD		 89 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
90 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
91 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
92 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
93};
94
47b0e7ad
NC		 95static const char * const mips_fpr_names_32[32] =
96{
640c0ccd
CD		 97 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
98 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
99 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
100 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
101};
102
47b0e7ad
NC		 103static const char * const mips_fpr_names_n32[32] =
104{
640c0ccd
CD		 105 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
106 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
107 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
108 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
109};
110
47b0e7ad
NC		 111static const char * const mips_fpr_names_64[32] =
112{
640c0ccd
CD		 113 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
114 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
115 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
116 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
117};
118
47b0e7ad
NC		 119static const char * const mips_cp0_names_numeric[32] =
120{
640c0ccd
CD		 121 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
122 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
123 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
124 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
125};
126
47b0e7ad
NC		 127static const char * const mips_cp0_names_mips3264[32] =
128{
640c0ccd
CD		 129 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
130 "c0_context", "c0_pagemask", "c0_wired", "$7",
131 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
132 "c0_status", "c0_cause", "c0_epc", "c0_prid",
133 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
134 "c0_xcontext", "$21", "$22", "c0_debug",
135 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
136 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
137};
138
47b0e7ad
NC		 139static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
140{
bbcc0807
CD		 141 { 16, 1, "c0_config1" },
142 { 16, 2, "c0_config2" },
143 { 16, 3, "c0_config3" },
144 { 18, 1, "c0_watchlo,1" },
145 { 18, 2, "c0_watchlo,2" },
146 { 18, 3, "c0_watchlo,3" },
147 { 18, 4, "c0_watchlo,4" },
148 { 18, 5, "c0_watchlo,5" },
149 { 18, 6, "c0_watchlo,6" },
150 { 18, 7, "c0_watchlo,7" },
151 { 19, 1, "c0_watchhi,1" },
152 { 19, 2, "c0_watchhi,2" },
153 { 19, 3, "c0_watchhi,3" },
154 { 19, 4, "c0_watchhi,4" },
155 { 19, 5, "c0_watchhi,5" },
156 { 19, 6, "c0_watchhi,6" },
157 { 19, 7, "c0_watchhi,7" },
158 { 25, 1, "c0_perfcnt,1" },
159 { 25, 2, "c0_perfcnt,2" },
160 { 25, 3, "c0_perfcnt,3" },
161 { 25, 4, "c0_perfcnt,4" },
162 { 25, 5, "c0_perfcnt,5" },
163 { 25, 6, "c0_perfcnt,6" },
164 { 25, 7, "c0_perfcnt,7" },
165 { 27, 1, "c0_cacheerr,1" },
166 { 27, 2, "c0_cacheerr,2" },
167 { 27, 3, "c0_cacheerr,3" },
168 { 28, 1, "c0_datalo" },
169 { 29, 1, "c0_datahi" }
170};
171
47b0e7ad
NC		 172static const char * const mips_cp0_names_mips3264r2[32] =
173{
af7ee8bf
CD		 174 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
175 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
176 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
177 "c0_status", "c0_cause", "c0_epc", "c0_prid",
178 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
179 "c0_xcontext", "$21", "$22", "c0_debug",
180 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
181 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
182};
183
47b0e7ad
NC		 184static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
185{
bbcc0807 186 { 4, 1, "c0_contextconfig" },
59c455b3
TS		 187 { 0, 1, "c0_mvpcontrol" },
188 { 0, 2, "c0_mvpconf0" },
189 { 0, 3, "c0_mvpconf1" },
190 { 1, 1, "c0_vpecontrol" },
191 { 1, 2, "c0_vpeconf0" },
192 { 1, 3, "c0_vpeconf1" },
193 { 1, 4, "c0_yqmask" },
194 { 1, 5, "c0_vpeschedule" },
195 { 1, 6, "c0_vpeschefback" },
196 { 2, 1, "c0_tcstatus" },
197 { 2, 2, "c0_tcbind" },
198 { 2, 3, "c0_tcrestart" },
199 { 2, 4, "c0_tchalt" },
200 { 2, 5, "c0_tccontext" },
201 { 2, 6, "c0_tcschedule" },
202 { 2, 7, "c0_tcschefback" },
bbcc0807 203 { 5, 1, "c0_pagegrain" },
59c455b3
TS		 204 { 6, 1, "c0_srsconf0" },
205 { 6, 2, "c0_srsconf1" },
206 { 6, 3, "c0_srsconf2" },
207 { 6, 4, "c0_srsconf3" },
208 { 6, 5, "c0_srsconf4" },
bbcc0807
CD		 209 { 12, 1, "c0_intctl" },
210 { 12, 2, "c0_srsctl" },
211 { 12, 3, "c0_srsmap" },
212 { 15, 1, "c0_ebase" },
213 { 16, 1, "c0_config1" },
214 { 16, 2, "c0_config2" },
215 { 16, 3, "c0_config3" },
216 { 18, 1, "c0_watchlo,1" },
217 { 18, 2, "c0_watchlo,2" },
218 { 18, 3, "c0_watchlo,3" },
219 { 18, 4, "c0_watchlo,4" },
220 { 18, 5, "c0_watchlo,5" },
221 { 18, 6, "c0_watchlo,6" },
222 { 18, 7, "c0_watchlo,7" },
223 { 19, 1, "c0_watchhi,1" },
224 { 19, 2, "c0_watchhi,2" },
225 { 19, 3, "c0_watchhi,3" },
226 { 19, 4, "c0_watchhi,4" },
227 { 19, 5, "c0_watchhi,5" },
228 { 19, 6, "c0_watchhi,6" },
229 { 19, 7, "c0_watchhi,7" },
230 { 23, 1, "c0_tracecontrol" },
231 { 23, 2, "c0_tracecontrol2" },
232 { 23, 3, "c0_usertracedata" },
233 { 23, 4, "c0_tracebpc" },
234 { 25, 1, "c0_perfcnt,1" },
235 { 25, 2, "c0_perfcnt,2" },
236 { 25, 3, "c0_perfcnt,3" },
237 { 25, 4, "c0_perfcnt,4" },
238 { 25, 5, "c0_perfcnt,5" },
239 { 25, 6, "c0_perfcnt,6" },
240 { 25, 7, "c0_perfcnt,7" },
241 { 27, 1, "c0_cacheerr,1" },
242 { 27, 2, "c0_cacheerr,2" },
243 { 27, 3, "c0_cacheerr,3" },
244 { 28, 1, "c0_datalo" },
245 { 28, 2, "c0_taglo1" },
246 { 28, 3, "c0_datalo1" },
247 { 28, 4, "c0_taglo2" },
248 { 28, 5, "c0_datalo2" },
249 { 28, 6, "c0_taglo3" },
250 { 28, 7, "c0_datalo3" },
251 { 29, 1, "c0_datahi" },
252 { 29, 2, "c0_taghi1" },
253 { 29, 3, "c0_datahi1" },
254 { 29, 4, "c0_taghi2" },
255 { 29, 5, "c0_datahi2" },
256 { 29, 6, "c0_taghi3" },
257 { 29, 7, "c0_datahi3" },
258};
259
640c0ccd 260/* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
47b0e7ad
NC		 261static const char * const mips_cp0_names_sb1[32] =
262{
640c0ccd
CD		 263 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
264 "c0_context", "c0_pagemask", "c0_wired", "$7",
265 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
266 "c0_status", "c0_cause", "c0_epc", "c0_prid",
267 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
268 "c0_xcontext", "$21", "$22", "c0_debug",
269 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
270 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
271};
272
47b0e7ad
NC		 273static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
274{
bbcc0807
CD		 275 { 16, 1, "c0_config1" },
276 { 18, 1, "c0_watchlo,1" },
277 { 19, 1, "c0_watchhi,1" },
278 { 22, 0, "c0_perftrace" },
279 { 23, 3, "c0_edebug" },
280 { 25, 1, "c0_perfcnt,1" },
281 { 25, 2, "c0_perfcnt,2" },
282 { 25, 3, "c0_perfcnt,3" },
283 { 25, 4, "c0_perfcnt,4" },
284 { 25, 5, "c0_perfcnt,5" },
285 { 25, 6, "c0_perfcnt,6" },
286 { 25, 7, "c0_perfcnt,7" },
287 { 26, 1, "c0_buserr_pa" },
288 { 27, 1, "c0_cacheerr_d" },
289 { 27, 3, "c0_cacheerr_d_pa" },
290 { 28, 1, "c0_datalo_i" },
291 { 28, 2, "c0_taglo_d" },
292 { 28, 3, "c0_datalo_d" },
293 { 29, 1, "c0_datahi_i" },
294 { 29, 2, "c0_taghi_d" },
295 { 29, 3, "c0_datahi_d" },
296};
297
47b0e7ad
NC		 298static const char * const mips_hwr_names_numeric[32] =
299{
af7ee8bf
CD		 300 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
301 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
302 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
303 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
304};
305
47b0e7ad
NC		 306static const char * const mips_hwr_names_mips3264r2[32] =
307{
af7ee8bf
CD		 308 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
309 "$4", "$5", "$6", "$7",
310 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
311 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
312 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
313};
314
47b0e7ad
NC		 315struct mips_abi_choice
316{
317 const char * name;
640c0ccd
CD		 318 const char * const *gpr_names;
319 const char * const *fpr_names;
320};
321
47b0e7ad
NC		 322struct mips_abi_choice mips_abi_choices[] =
323{
640c0ccd
CD		 324 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
325 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
326 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
327 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
328};
329
47b0e7ad
NC		 330struct mips_arch_choice
331{
640c0ccd
CD		 332 const char *name;
333 int bfd_mach_valid;
334 unsigned long bfd_mach;
335 int processor;
336 int isa;
337 const char * const *cp0_names;
bbcc0807
CD		 338 const struct mips_cp0sel_name *cp0sel_names;
339 unsigned int cp0sel_names_len;
af7ee8bf 340 const char * const *hwr_names;
640c0ccd
CD		 341};
342
47b0e7ad
NC		 343const struct mips_arch_choice mips_arch_choices[] =
344{
640c0ccd 345 { "numeric", 0, 0, 0, 0,
bbcc0807
CD		 346 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
347
640c0ccd 348 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
bbcc0807 349 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 350 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
bbcc0807 351 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 352 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
bbcc0807 353 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 354 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
bbcc0807 355 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 356 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
bbcc0807 357 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 358 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
bbcc0807 359 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 360 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
bbcc0807 361 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 362 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
bbcc0807 363 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 364 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
bbcc0807 365 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 366 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
bbcc0807 367 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 368 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
bbcc0807 369 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 370 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
bbcc0807 371 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 372 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
bbcc0807 373 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 374 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
bbcc0807 375 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 376 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
bbcc0807 377 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
5a7ea749
RS		 378 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
379 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
380 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
381 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 382 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
bbcc0807 383 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 384 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
bbcc0807 385 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 386 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
bbcc0807 387 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 388 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
bbcc0807
CD		 389 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
390
640c0ccd
CD		 391 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
392 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
393 _MIPS32 Architecture For Programmers Volume I: Introduction to the
394 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
395 page 1. */
396 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
39a7806d 397 ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
bbcc0807
CD		 398 mips_cp0_names_mips3264,
399 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
400 mips_hwr_names_numeric },
401
af7ee8bf 402 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
8b082fb1
TS		 403 (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
404 | INSN_MIPS3D | INSN_MT),
bbcc0807
CD		 405 mips_cp0_names_mips3264r2,
406 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
407 mips_hwr_names_mips3264r2 },
408
640c0ccd
CD		 409 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
410 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
39a7806d 411 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
bbcc0807
CD		 412 mips_cp0_names_mips3264,
413 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
414 mips_hwr_names_numeric },
415
5f74bc13 416 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
8b082fb1
TS		 417 (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
418 | INSN_DSP64 | INSN_MT | INSN_MDMX),
5f74bc13
CD		 419 mips_cp0_names_mips3264r2,
420 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
421 mips_hwr_names_mips3264r2 },
422
640c0ccd
CD		 423 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
424 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
bbcc0807
CD		 425 mips_cp0_names_sb1,
426 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
427 mips_hwr_names_numeric },
640c0ccd
CD		 428
429 /* This entry, mips16, is here only for ISA/processor selection; do
430 not print its name. */
431 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
bbcc0807 432 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd
CD		 433};
434
435/* ISA and processor type to disassemble for, and register names to use.
436 set_default_mips_dis_options and parse_mips_dis_options fill in these
437 values. */
438static int mips_processor;
439static int mips_isa;
440static const char * const *mips_gpr_names;
441static const char * const *mips_fpr_names;
442static const char * const *mips_cp0_names;
bbcc0807
CD		 443static const struct mips_cp0sel_name *mips_cp0sel_names;
444static int mips_cp0sel_names_len;
af7ee8bf 445static const char * const *mips_hwr_names;
640c0ccd 446
986e18a5 447/* Other options */
47b0e7ad 448static int no_aliases; /* If set disassemble as most general inst. */
640c0ccd
CD		 449\f
450static const struct mips_abi_choice *
47b0e7ad 451choose_abi_by_name (const char *name, unsigned int namelen)
640c0ccd
CD		 452{
453 const struct mips_abi_choice *c;
454 unsigned int i;
455
456 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
47b0e7ad
NC		 457 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
458 && strlen (mips_abi_choices[i].name) == namelen)
459 c = &mips_abi_choices[i];
460
640c0ccd
CD		 461 return c;
462}
463
464static const struct mips_arch_choice *
47b0e7ad 465choose_arch_by_name (const char *name, unsigned int namelen)
640c0ccd
CD		 466{
467 const struct mips_arch_choice *c = NULL;
468 unsigned int i;
469
470 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
47b0e7ad
NC		 471 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
472 && strlen (mips_arch_choices[i].name) == namelen)
473 c = &mips_arch_choices[i];
474
640c0ccd
CD		 475 return c;
476}
477
478static const struct mips_arch_choice *
47b0e7ad 479choose_arch_by_number (unsigned long mach)
640c0ccd
CD		 480{
481 static unsigned long hint_bfd_mach;
482 static const struct mips_arch_choice *hint_arch_choice;
483 const struct mips_arch_choice *c;
484 unsigned int i;
485
486 /* We optimize this because even if the user specifies no
487 flags, this will be done for every instruction! */
488 if (hint_bfd_mach == mach
489 && hint_arch_choice != NULL
490 && hint_arch_choice->bfd_mach == hint_bfd_mach)
491 return hint_arch_choice;
492
493 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
494 {
495 if (mips_arch_choices[i].bfd_mach_valid
496 && mips_arch_choices[i].bfd_mach == mach)
497 {
498 c = &mips_arch_choices[i];
499 hint_bfd_mach = mach;
500 hint_arch_choice = c;
501 }
502 }
503 return c;
504}
505
47b0e7ad
NC		 506/* Check if the object uses NewABI conventions. */
507
508static int
509is_newabi (Elf_Internal_Ehdr *header)
510{
511 /* There are no old-style ABIs which use 64-bit ELF. */
512 if (header->e_ident[EI_CLASS] == ELFCLASS64)
513 return 1;
514
515 /* If a 32-bit ELF file, n32 is a new-style ABI. */
516 if ((header->e_flags & EF_MIPS_ABI2) != 0)
517 return 1;
518
519 return 0;
520}
521
522static void
523set_default_mips_dis_options (struct disassemble_info *info)
640c0ccd
CD		 524{
525 const struct mips_arch_choice *chosen_arch;
526
527 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
af7ee8bf 528 and numeric FPR, CP0 register, and HWR names. */
640c0ccd
CD		 529 mips_isa = ISA_MIPS3;
530 mips_processor = CPU_R3000;
531 mips_gpr_names = mips_gpr_names_oldabi;
532 mips_fpr_names = mips_fpr_names_numeric;
533 mips_cp0_names = mips_cp0_names_numeric;
bbcc0807
CD		 534 mips_cp0sel_names = NULL;
535 mips_cp0sel_names_len = 0;
af7ee8bf 536 mips_hwr_names = mips_hwr_names_numeric;
986e18a5 537 no_aliases = 0;
640c0ccd
CD		 538
539 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
fec06546 540 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
640c0ccd
CD		 541 {
542 Elf_Internal_Ehdr *header;
543
fec06546 544 header = elf_elfheader (info->section->owner);
640c0ccd
CD		 545 if (is_newabi (header))
546 mips_gpr_names = mips_gpr_names_newabi;
547 }
548
549 /* Set ISA, architecture, and cp0 register names as best we can. */
550#if ! SYMTAB_AVAILABLE
551 /* This is running out on a target machine, not in a host tool.
552 FIXME: Where does mips_target_info come from? */
553 target_processor = mips_target_info.processor;
554 mips_isa = mips_target_info.isa;
555#else
556 chosen_arch = choose_arch_by_number (info->mach);
557 if (chosen_arch != NULL)
558 {
559 mips_processor = chosen_arch->processor;
560 mips_isa = chosen_arch->isa;
bbcc0807
CD		 561 mips_cp0_names = chosen_arch->cp0_names;
562 mips_cp0sel_names = chosen_arch->cp0sel_names;
563 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
564 mips_hwr_names = chosen_arch->hwr_names;
640c0ccd
CD		 565 }
566#endif
567}
568
47b0e7ad
NC		 569static void
570parse_mips_dis_option (const char *option, unsigned int len)
640c0ccd
CD		 571{
572 unsigned int i, optionlen, vallen;
573 const char *val;
574 const struct mips_abi_choice *chosen_abi;
575 const struct mips_arch_choice *chosen_arch;
576
986e18a5 577 /* Try to match options that are simple flags */
0112cd26 578 if (CONST_STRNEQ (option, "no-aliases"))
986e18a5
FF		 579 {
580 no_aliases = 1;
581 return;
582 }
583
640c0ccd
CD		 584 /* Look for the = that delimits the end of the option name. */
585 for (i = 0; i < len; i++)
47b0e7ad
NC		 586 if (option[i] == '=')
587 break;
588
640c0ccd
CD		 589 if (i == 0) /* Invalid option: no name before '='. */
590 return;
591 if (i == len) /* Invalid option: no '='. */
592 return;
593 if (i == (len - 1)) /* Invalid option: no value after '='. */
594 return;
595
596 optionlen = i;
597 val = option + (optionlen + 1);
598 vallen = len - (optionlen + 1);
599
47b0e7ad
NC		 600 if (strncmp ("gpr-names", option, optionlen) == 0
601 && strlen ("gpr-names") == optionlen)
640c0ccd
CD		 602 {
603 chosen_abi = choose_abi_by_name (val, vallen);
bbcc0807 604 if (chosen_abi != NULL)
640c0ccd
CD		 605 mips_gpr_names = chosen_abi->gpr_names;
606 return;
607 }
608
47b0e7ad
NC		 609 if (strncmp ("fpr-names", option, optionlen) == 0
610 && strlen ("fpr-names") == optionlen)
640c0ccd
CD		 611 {
612 chosen_abi = choose_abi_by_name (val, vallen);
bbcc0807 613 if (chosen_abi != NULL)
640c0ccd
CD		 614 mips_fpr_names = chosen_abi->fpr_names;
615 return;
616 }
617
47b0e7ad
NC		 618 if (strncmp ("cp0-names", option, optionlen) == 0
619 && strlen ("cp0-names") == optionlen)
640c0ccd
CD		 620 {
621 chosen_arch = choose_arch_by_name (val, vallen);
bbcc0807
CD		 622 if (chosen_arch != NULL)
623 {
624 mips_cp0_names = chosen_arch->cp0_names;
625 mips_cp0sel_names = chosen_arch->cp0sel_names;
626 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
627 }
640c0ccd
CD		 628 return;
629 }
630
47b0e7ad
NC		 631 if (strncmp ("hwr-names", option, optionlen) == 0
632 && strlen ("hwr-names") == optionlen)
af7ee8bf
CD		 633 {
634 chosen_arch = choose_arch_by_name (val, vallen);
bbcc0807 635 if (chosen_arch != NULL)
af7ee8bf
CD		 636 mips_hwr_names = chosen_arch->hwr_names;
637 return;
638 }
639
47b0e7ad
NC		 640 if (strncmp ("reg-names", option, optionlen) == 0
641 && strlen ("reg-names") == optionlen)
640c0ccd
CD		 642 {
643 /* We check both ABI and ARCH here unconditionally, so
644 that "numeric" will do the desirable thing: select
645 numeric register names for all registers. Other than
646 that, a given name probably won't match both. */
647 chosen_abi = choose_abi_by_name (val, vallen);
648 if (chosen_abi != NULL)
649 {
bbcc0807
CD		 650 mips_gpr_names = chosen_abi->gpr_names;
651 mips_fpr_names = chosen_abi->fpr_names;
640c0ccd
CD		 652 }
653 chosen_arch = choose_arch_by_name (val, vallen);
654 if (chosen_arch != NULL)
655 {
bbcc0807
CD		 656 mips_cp0_names = chosen_arch->cp0_names;
657 mips_cp0sel_names = chosen_arch->cp0sel_names;
658 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
659 mips_hwr_names = chosen_arch->hwr_names;
640c0ccd
CD		 660 }
661 return;
662 }
663
664 /* Invalid option. */
665}
666
47b0e7ad
NC		 667static void
668parse_mips_dis_options (const char *options)
640c0ccd
CD		 669{
670 const char *option_end;
671
672 if (options == NULL)
673 return;
674
675 while (*options != '\0')
676 {
677 /* Skip empty options. */
678 if (*options == ',')
679 {
680 options++;
681 continue;
682 }
683
684 /* We know that *options is neither NUL or a comma. */
685 option_end = options + 1;
686 while (*option_end != ',' && *option_end != '\0')
687 option_end++;
688
689 parse_mips_dis_option (options, option_end - options);
690
691 /* Go on to the next one. If option_end points to a comma, it
692 will be skipped above. */
693 options = option_end;
694 }
695}
696
bbcc0807 697static const struct mips_cp0sel_name *
47b0e7ad
NC		 698lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
699 unsigned int len,
700 unsigned int cp0reg,
701 unsigned int sel)
bbcc0807
CD		 702{
703 unsigned int i;
704
705 for (i = 0; i < len; i++)
706 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
707 return &names[i];
708 return NULL;
709}
252b5132 710\f
7f6621cd 711/* Print insn arguments for 32/64-bit code. */
aa5f19f2 712
794ac9d0 713static void
47b0e7ad
NC		 714print_insn_args (const char *d,
715 register unsigned long int l,
716 bfd_vma pc,
cc0ca239
TS		 717 struct disassemble_info *info,
718 const struct mips_opcode *opp)
252b5132 719{
794ac9d0 720 int op, delta;
440cc0bc
CD		 721 unsigned int lsb, msb, msbd;
722
723 lsb = 0;
252b5132 724
794ac9d0 725 for (; *d != '\0'; d++)
252b5132 726 {
af7ee8bf
CD		 727 switch (*d)
728 {
794ac9d0
CD		 729 case ',':
730 case '(':
731 case ')':
732 case '[':
733 case ']':
734 (*info->fprintf_func) (info->stream, "%c", *d);
735 break;
736
737 case '+':
738 /* Extension character; switch for second char. */
739 d++;
740 switch (*d)
741 {
742 case '\0':
743 /* xgettext:c-format */
744 (*info->fprintf_func) (info->stream,
745 _("# internal error, incomplete extension sequence (+)"));
746 return;
747
748 case 'A':
440cc0bc
CD		 749 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
750 (*info->fprintf_func) (info->stream, "0x%x", lsb);
794ac9d0
CD		 751 break;
752
753 case 'B':
440cc0bc
CD		 754 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
755 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
794ac9d0
CD		 756 break;
757
9bcd4f99
TS		 758 case '1':
759 (*info->fprintf_func) (info->stream, "0x%lx",
760 (l >> OP_SH_UDI1) & OP_MASK_UDI1);
761 break;
762
763 case '2':
764 (*info->fprintf_func) (info->stream, "0x%lx",
765 (l >> OP_SH_UDI2) & OP_MASK_UDI2);
766 break;
767
768 case '3':
769 (*info->fprintf_func) (info->stream, "0x%lx",
770 (l >> OP_SH_UDI3) & OP_MASK_UDI3);
771 break;
772
773 case '4':
774 (*info->fprintf_func) (info->stream, "0x%lx",
775 (l >> OP_SH_UDI4) & OP_MASK_UDI4);
776 break;
777
794ac9d0 778 case 'C':
5f74bc13 779 case 'H':
440cc0bc
CD		 780 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
781 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
794ac9d0
CD		 782 break;
783
784 case 'D':
785 {
786 const struct mips_cp0sel_name *n;
787 unsigned int cp0reg, sel;
788
789 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
790 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
791
792 /* CP0 register including 'sel' code for mtcN (et al.), to be
793 printed textually if known. If not known, print both
794 CP0 register name and sel numerically since CP0 register
795 with sel 0 may have a name unrelated to register being
796 printed. */
797 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
798 mips_cp0sel_names_len, cp0reg, sel);
799 if (n != NULL)
800 (*info->fprintf_func) (info->stream, "%s", n->name);
801 else
802 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
803 break;
804 }
805
5f74bc13
CD		 806 case 'E':
807 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
808 (*info->fprintf_func) (info->stream, "0x%x", lsb);
809 break;
810
811 case 'F':
812 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
813 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
814 break;
815
816 case 'G':
817 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
818 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
819 break;
820
61cc0267
CF		 821 case 't': /* Coprocessor 0 reg name */
822 (*info->fprintf_func) (info->stream, "%s",
823 mips_cp0_names[(l >> OP_SH_RT) &
824 OP_MASK_RT]);
825 break;
826
827 case 'T': /* Coprocessor 0 reg name */
828 {
829 const struct mips_cp0sel_name *n;
830 unsigned int cp0reg, sel;
831
832 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
833 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
834
835 /* CP0 register including 'sel' code for mftc0, to be
836 printed textually if known. If not known, print both
837 CP0 register name and sel numerically since CP0 register
838 with sel 0 may have a name unrelated to register being
839 printed. */
840 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
841 mips_cp0sel_names_len, cp0reg, sel);
842 if (n != NULL)
843 (*info->fprintf_func) (info->stream, "%s", n->name);
844 else
845 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
846 break;
847 }
848
794ac9d0
CD		 849 default:
850 /* xgettext:c-format */
851 (*info->fprintf_func) (info->stream,
852 _("# internal error, undefined extension sequence (+%c)"),
853 *d);
854 return;
855 }
856 break;
857
8b082fb1
TS		 858 case '2':
859 (*info->fprintf_func) (info->stream, "0x%lx",
860 (l >> OP_SH_BP) & OP_MASK_BP);
861 break;
862
fd25c5a9
CF		 863 case '3':
864 (*info->fprintf_func) (info->stream, "0x%lx",
865 (l >> OP_SH_SA3) & OP_MASK_SA3);
866 break;
867
868 case '4':
869 (*info->fprintf_func) (info->stream, "0x%lx",
870 (l >> OP_SH_SA4) & OP_MASK_SA4);
871 break;
872
873 case '5':
874 (*info->fprintf_func) (info->stream, "0x%lx",
875 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
876 break;
877
878 case '6':
879 (*info->fprintf_func) (info->stream, "0x%lx",
880 (l >> OP_SH_RS) & OP_MASK_RS);
881 break;
882
883 case '7':
884 (*info->fprintf_func) (info->stream, "$ac%ld",
885 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
886 break;
887
888 case '8':
889 (*info->fprintf_func) (info->stream, "0x%lx",
890 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
891 break;
892
893 case '9':
894 (*info->fprintf_func) (info->stream, "$ac%ld",
895 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
896 break;
897
898 case '0': /* dsp 6-bit signed immediate in bit 20 */
899 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
900 if (delta & 0x20) /* test sign bit */
901 delta |= ~OP_MASK_DSPSFT;
902 (*info->fprintf_func) (info->stream, "%d", delta);
903 break;
904
905 case ':': /* dsp 7-bit signed immediate in bit 19 */
906 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
907 if (delta & 0x40) /* test sign bit */
908 delta |= ~OP_MASK_DSPSFT_7;
909 (*info->fprintf_func) (info->stream, "%d", delta);
910 break;
911
912 case '\'':
913 (*info->fprintf_func) (info->stream, "0x%lx",
914 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
915 break;
916
917 case '@': /* dsp 10-bit signed immediate in bit 16 */
918 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
919 if (delta & 0x200) /* test sign bit */
920 delta |= ~OP_MASK_IMM10;
921 (*info->fprintf_func) (info->stream, "%d", delta);
922 break;
923
61cc0267
CF		 924 case '!':
925 (*info->fprintf_func) (info->stream, "%ld",
926 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
927 break;
928
929 case '$':
930 (*info->fprintf_func) (info->stream, "%ld",
931 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
932 break;
933
934 case '*':
935 (*info->fprintf_func) (info->stream, "$ac%ld",
936 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
937 break;
938
939 case '&':
940 (*info->fprintf_func) (info->stream, "$ac%ld",
941 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
942 break;
943
944 case 'g':
945 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
946 (*info->fprintf_func) (info->stream, "$%ld",
947 (l >> OP_SH_RD) & OP_MASK_RD);
948 break;
949
794ac9d0
CD		 950 case 's':
951 case 'b':
952 case 'r':
953 case 'v':
954 (*info->fprintf_func) (info->stream, "%s",
955 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
956 break;
957
958 case 't':
959 case 'w':
960 (*info->fprintf_func) (info->stream, "%s",
961 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
962 break;
963
964 case 'i':
965 case 'u':
0fd3a477 966 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0
CD		 967 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
968 break;
969
970 case 'j': /* Same as i, but sign-extended. */
971 case 'o':
972 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
973 if (delta & 0x8000)
974 delta |= ~0xffff;
975 (*info->fprintf_func) (info->stream, "%d",
976 delta);
977 break;
978
979 case 'h':
980 (*info->fprintf_func) (info->stream, "0x%x",
981 (unsigned int) ((l >> OP_SH_PREFX)
982 & OP_MASK_PREFX));
983 break;
984
985 case 'k':
986 (*info->fprintf_func) (info->stream, "0x%x",
987 (unsigned int) ((l >> OP_SH_CACHE)
988 & OP_MASK_CACHE));
989 break;
990
991 case 'a':
992 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
993 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
022fac6d
TS		 994 /* For gdb disassembler, force odd address on jalx. */
995 if (info->flavour == bfd_target_unknown_flavour
996 && strcmp (opp->name, "jalx") == 0)
997 info->target |= 1;
794ac9d0
CD		 998 (*info->print_address_func) (info->target, info);
999 break;
1000
1001 case 'p':
1002 /* Sign extend the displacement. */
1003 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1004 if (delta & 0x8000)
1005 delta |= ~0xffff;
1006 info->target = (delta << 2) + pc + INSNLEN;
1007 (*info->print_address_func) (info->target, info);
1008 break;
1009
1010 case 'd':
1011 (*info->fprintf_func) (info->stream, "%s",
1012 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1013 break;
1014
1015 case 'U':
1016 {
1017 /* First check for both rd and rt being equal. */
1018 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
1019 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
1020 (*info->fprintf_func) (info->stream, "%s",
1021 mips_gpr_names[reg]);
1022 else
1023 {
1024 /* If one is zero use the other. */
1025 if (reg == 0)
1026 (*info->fprintf_func) (info->stream, "%s",
1027 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1028 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
1029 (*info->fprintf_func) (info->stream, "%s",
1030 mips_gpr_names[reg]);
1031 else /* Bogus, result depends on processor. */
1032 (*info->fprintf_func) (info->stream, "%s or %s",
1033 mips_gpr_names[reg],
1034 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1035 }
1036 }
1037 break;
1038
1039 case 'z':
1040 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1041 break;
1042
1043 case '<':
0fd3a477 1044 (*info->fprintf_func) (info->stream, "0x%lx",
af7ee8bf
CD		 1045 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
1046 break;
794ac9d0
CD		 1047
1048 case 'c':
0fd3a477 1049 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0
CD		 1050 (l >> OP_SH_CODE) & OP_MASK_CODE);
1051 break;
1052
1053 case 'q':
0fd3a477 1054 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0 1055 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
af7ee8bf
CD		 1056 break;
1057
1058 case 'C':
0fd3a477 1059 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0
CD		 1060 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
1061 break;
1062
1063 case 'B':
0fd3a477
JW		 1064 (*info->fprintf_func) (info->stream, "0x%lx",
1065
794ac9d0
CD		 1066 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
1067 break;
1068
1069 case 'J':
0fd3a477 1070 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0
CD		 1071 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
1072 break;
1073
1074 case 'S':
1075 case 'V':
1076 (*info->fprintf_func) (info->stream, "%s",
1077 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
1078 break;
1079
1080 case 'T':
1081 case 'W':
1082 (*info->fprintf_func) (info->stream, "%s",
1083 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
af7ee8bf
CD		 1084 break;
1085
bbcc0807 1086 case 'D':
794ac9d0
CD		 1087 (*info->fprintf_func) (info->stream, "%s",
1088 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
1089 break;
1090
1091 case 'R':
1092 (*info->fprintf_func) (info->stream, "%s",
1093 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
1094 break;
1095
1096 case 'E':
1097 /* Coprocessor register for lwcN instructions, et al.
1098
1099 Note that there is no load/store cp0 instructions, and
1100 that FPU (cp1) instructions disassemble this field using
1101 'T' format. Therefore, until we gain understanding of
1102 cp2 register names, we can simply print the register
1103 numbers. */
0fd3a477 1104 (*info->fprintf_func) (info->stream, "$%ld",
794ac9d0
CD		 1105 (l >> OP_SH_RT) & OP_MASK_RT);
1106 break;
1107
1108 case 'G':
1109 /* Coprocessor register for mtcN instructions, et al. Note
1110 that FPU (cp1) instructions disassemble this field using
1111 'S' format. Therefore, we only need to worry about cp0,
1112 cp2, and cp3. */
1113 op = (l >> OP_SH_OP) & OP_MASK_OP;
1114 if (op == OP_OP_COP0)
1115 (*info->fprintf_func) (info->stream, "%s",
1116 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1117 else
0fd3a477 1118 (*info->fprintf_func) (info->stream, "$%ld",
794ac9d0
CD		 1119 (l >> OP_SH_RD) & OP_MASK_RD);
1120 break;
1121
1122 case 'K':
1123 (*info->fprintf_func) (info->stream, "%s",
1124 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1125 break;
1126
1127 case 'N':
0d09bfe6
TS		 1128 (*info->fprintf_func) (info->stream,
1129 ((opp->pinfo & (FP_D | FP_S)) != 0
1130 ? "$fcc%ld" : "$cc%ld"),
794ac9d0
CD		 1131 (l >> OP_SH_BCC) & OP_MASK_BCC);
1132 break;
1133
1134 case 'M':
0fd3a477 1135 (*info->fprintf_func) (info->stream, "$fcc%ld",
794ac9d0
CD		 1136 (l >> OP_SH_CCC) & OP_MASK_CCC);
1137 break;
1138
1139 case 'P':
0fd3a477 1140 (*info->fprintf_func) (info->stream, "%ld",
794ac9d0
CD		 1141 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
1142 break;
1143
1144 case 'e':
0fd3a477 1145 (*info->fprintf_func) (info->stream, "%ld",
794ac9d0
CD		 1146 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
1147 break;
1148
1149 case '%':
0fd3a477 1150 (*info->fprintf_func) (info->stream, "%ld",
794ac9d0
CD		 1151 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
1152 break;
1153
1154 case 'H':
0fd3a477 1155 (*info->fprintf_func) (info->stream, "%ld",
794ac9d0
CD		 1156 (l >> OP_SH_SEL) & OP_MASK_SEL);
1157 break;
1158
1159 case 'O':
0fd3a477 1160 (*info->fprintf_func) (info->stream, "%ld",
794ac9d0
CD		 1161 (l >> OP_SH_ALN) & OP_MASK_ALN);
1162 break;
1163
1164 case 'Q':
bbcc0807 1165 {
794ac9d0 1166 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
47b0e7ad 1167
794ac9d0
CD		 1168 if ((vsel & 0x10) == 0)
1169 {
1170 int fmt;
47b0e7ad 1171
794ac9d0
CD		 1172 vsel &= 0x0f;
1173 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1174 if ((vsel & 1) == 0)
1175 break;
0fd3a477 1176 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
794ac9d0
CD		 1177 (l >> OP_SH_FT) & OP_MASK_FT,
1178 vsel >> 1);
1179 }
1180 else if ((vsel & 0x08) == 0)
1181 {
0fd3a477 1182 (*info->fprintf_func) (info->stream, "$v%ld",
794ac9d0
CD		 1183 (l >> OP_SH_FT) & OP_MASK_FT);
1184 }
bbcc0807 1185 else
794ac9d0 1186 {
0fd3a477 1187 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0
CD		 1188 (l >> OP_SH_FT) & OP_MASK_FT);
1189 }
bbcc0807 1190 }
794ac9d0
CD		 1191 break;
1192
1193 case 'X':
0fd3a477 1194 (*info->fprintf_func) (info->stream, "$v%ld",
794ac9d0
CD		 1195 (l >> OP_SH_FD) & OP_MASK_FD);
1196 break;
1197
1198 case 'Y':
0fd3a477 1199 (*info->fprintf_func) (info->stream, "$v%ld",
794ac9d0
CD		 1200 (l >> OP_SH_FS) & OP_MASK_FS);
1201 break;
1202
1203 case 'Z':
0fd3a477 1204 (*info->fprintf_func) (info->stream, "$v%ld",
794ac9d0
CD		 1205 (l >> OP_SH_FT) & OP_MASK_FT);
1206 break;
bbcc0807 1207
af7ee8bf
CD		 1208 default:
1209 /* xgettext:c-format */
1210 (*info->fprintf_func) (info->stream,
794ac9d0 1211 _("# internal error, undefined modifier(%c)"),
af7ee8bf 1212 *d);
794ac9d0 1213 return;
af7ee8bf 1214 }
252b5132
RH		 1215 }
1216}
1217\f
252b5132
RH		 1218/* Print the mips instruction at address MEMADDR in debugged memory,
1219 on using INFO. Returns length of the instruction, in bytes, which is
aa5f19f2 1220 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
252b5132
RH		 1221 this is little-endian code. */
1222
1223static int
47b0e7ad
NC		 1224print_insn_mips (bfd_vma memaddr,
1225 unsigned long int word,
1226 struct disassemble_info *info)
252b5132 1227{
47b0e7ad 1228 const struct mips_opcode *op;
b34976b6 1229 static bfd_boolean init = 0;
252b5132
RH		 1230 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1231
1232 /* Build a hash table to shorten the search time. */
1233 if (! init)
1234 {
1235 unsigned int i;
1236
1237 for (i = 0; i <= OP_MASK_OP; i++)
1238 {
1239 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1240 {
986e18a5 1241 if (op->pinfo == INSN_MACRO
9e836e3d 1242 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
252b5132
RH		 1243 continue;
1244 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1245 {
1246 mips_hash[i] = op;
1247 break;
1248 }
1249 }
7f6621cd 1250 }
252b5132
RH		 1251
1252 init = 1;
1253 }
1254
aa5f19f2 1255 info->bytes_per_chunk = INSNLEN;
252b5132 1256 info->display_endian = info->endian;
9bb28706
CD		 1257 info->insn_info_valid = 1;
1258 info->branch_delay_insns = 0;
def7143b 1259 info->data_size = 0;
9bb28706
CD		 1260 info->insn_type = dis_nonbranch;
1261 info->target = 0;
1262 info->target2 = 0;
252b5132
RH		 1263
1264 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1265 if (op != NULL)
1266 {
1267 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1268 {
986e18a5 1269 if (op->pinfo != INSN_MACRO
9e836e3d 1270 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
986e18a5 1271 && (word & op->mask) == op->match)
252b5132 1272 {
47b0e7ad 1273 const char *d;
2bd7f1f3 1274
3396de36 1275 /* We always allow to disassemble the jalx instruction. */
640c0ccd 1276 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
3396de36 1277 && strcmp (op->name, "jalx"))
252b5132
RH		 1278 continue;
1279
9bb28706
CD		 1280 /* Figure out instruction type and branch delay information. */
1281 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1282 {
1283 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1284 info->insn_type = dis_jsr;
1285 else
1286 info->insn_type = dis_branch;
1287 info->branch_delay_insns = 1;
1288 }
1289 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1290 | INSN_COND_BRANCH_LIKELY)) != 0)
1291 {
1292 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1293 info->insn_type = dis_condjsr;
1294 else
1295 info->insn_type = dis_condbranch;
1296 info->branch_delay_insns = 1;
1297 }
1298 else if ((op->pinfo & (INSN_STORE_MEMORY
1299 | INSN_LOAD_MEMORY_DELAY)) != 0)
1300 info->insn_type = dis_dref;
1301
252b5132
RH		 1302 (*info->fprintf_func) (info->stream, "%s", op->name);
1303
1304 d = op->args;
1305 if (d != NULL && *d != '\0')
1306 {
7f6621cd 1307 (*info->fprintf_func) (info->stream, "\t");
cc0ca239 1308 print_insn_args (d, word, memaddr, info, op);
252b5132
RH		 1309 }
1310
aa5f19f2 1311 return INSNLEN;
252b5132
RH		 1312 }
1313 }
1314 }
1315
1316 /* Handle undefined instructions. */
9bb28706 1317 info->insn_type = dis_noninsn;
0fd3a477 1318 (*info->fprintf_func) (info->stream, "0x%lx", word);
aa5f19f2 1319 return INSNLEN;
252b5132 1320}
aa5f19f2 1321\f
252b5132
RH		 1322/* Disassemble an operand for a mips16 instruction. */
1323
1324static void
47b0e7ad
NC		 1325print_mips16_insn_arg (char type,
1326 const struct mips_opcode *op,
1327 int l,
1328 bfd_boolean use_extend,
1329 int extend,
1330 bfd_vma memaddr,
1331 struct disassemble_info *info)
252b5132
RH		 1332{
1333 switch (type)
1334 {
1335 case ',':
1336 case '(':
1337 case ')':
1338 (*info->fprintf_func) (info->stream, "%c", type);
1339 break;
1340
1341 case 'y':
1342 case 'w':
aa5f19f2 1343 (*info->fprintf_func) (info->stream, "%s",
654c225a
TS		 1344 mips16_reg_names(((l >> MIPS16OP_SH_RY)
1345 & MIPS16OP_MASK_RY)));
252b5132
RH		 1346 break;
1347
1348 case 'x':
1349 case 'v':
aa5f19f2 1350 (*info->fprintf_func) (info->stream, "%s",
654c225a
TS		 1351 mips16_reg_names(((l >> MIPS16OP_SH_RX)
1352 & MIPS16OP_MASK_RX)));
252b5132
RH		 1353 break;
1354
1355 case 'z':
aa5f19f2 1356 (*info->fprintf_func) (info->stream, "%s",
654c225a
TS		 1357 mips16_reg_names(((l >> MIPS16OP_SH_RZ)
1358 & MIPS16OP_MASK_RZ)));
252b5132
RH		 1359 break;
1360
1361 case 'Z':
aa5f19f2 1362 (*info->fprintf_func) (info->stream, "%s",
654c225a
TS		 1363 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
1364 & MIPS16OP_MASK_MOVE32Z)));
252b5132
RH		 1365 break;
1366
1367 case '0':
640c0ccd 1368 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
252b5132
RH		 1369 break;
1370
1371 case 'S':
640c0ccd 1372 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
252b5132
RH		 1373 break;
1374
1375 case 'P':
1376 (*info->fprintf_func) (info->stream, "$pc");
1377 break;
1378
1379 case 'R':
640c0ccd 1380 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
252b5132
RH		 1381 break;
1382
1383 case 'X':
aa5f19f2 1384 (*info->fprintf_func) (info->stream, "%s",
640c0ccd
CD		 1385 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1386 & MIPS16OP_MASK_REGR32)]);
252b5132
RH		 1387 break;
1388
1389 case 'Y':
aa5f19f2 1390 (*info->fprintf_func) (info->stream, "%s",
640c0ccd 1391 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
252b5132
RH		 1392 break;
1393
1394 case '<':
1395 case '>':
1396 case '[':
1397 case ']':
1398 case '4':
1399 case '5':
1400 case 'H':
1401 case 'W':
1402 case 'D':
1403 case 'j':
1404 case '6':
1405 case '8':
1406 case 'V':
1407 case 'C':
1408 case 'U':
1409 case 'k':
1410 case 'K':
1411 case 'p':
1412 case 'q':
1413 case 'A':
1414 case 'B':
1415 case 'E':
1416 {
1417 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1418
1419 shift = 0;
1420 signedp = 0;
1421 extbits = 16;
1422 pcrel = 0;
1423 extu = 0;
1424 branch = 0;
1425 switch (type)
1426 {
1427 case '<':
1428 nbits = 3;
1429 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1430 extbits = 5;
1431 extu = 1;
1432 break;
1433 case '>':
1434 nbits = 3;
1435 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1436 extbits = 5;
1437 extu = 1;
1438 break;
1439 case '[':
1440 nbits = 3;
1441 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1442 extbits = 6;
1443 extu = 1;
1444 break;
1445 case ']':
1446 nbits = 3;
1447 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1448 extbits = 6;
1449 extu = 1;
1450 break;
1451 case '4':
1452 nbits = 4;
1453 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1454 signedp = 1;
1455 extbits = 15;
1456 break;
1457 case '5':
1458 nbits = 5;
1459 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1460 info->insn_type = dis_dref;
1461 info->data_size = 1;
1462 break;
1463 case 'H':
1464 nbits = 5;
1465 shift = 1;
1466 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1467 info->insn_type = dis_dref;
1468 info->data_size = 2;
1469 break;
1470 case 'W':
1471 nbits = 5;
1472 shift = 2;
1473 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1474 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1475 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1476 {
1477 info->insn_type = dis_dref;
1478 info->data_size = 4;
1479 }
1480 break;
1481 case 'D':
1482 nbits = 5;
1483 shift = 3;
1484 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1485 info->insn_type = dis_dref;
1486 info->data_size = 8;
1487 break;
1488 case 'j':
1489 nbits = 5;
1490 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1491 signedp = 1;
1492 break;
1493 case '6':
1494 nbits = 6;
1495 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1496 break;
1497 case '8':
1498 nbits = 8;
1499 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1500 break;
1501 case 'V':
1502 nbits = 8;
1503 shift = 2;
1504 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1505 /* FIXME: This might be lw, or it might be addiu to $sp or
1506 $pc. We assume it's load. */
1507 info->insn_type = dis_dref;
1508 info->data_size = 4;
1509 break;
1510 case 'C':
1511 nbits = 8;
1512 shift = 3;
1513 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1514 info->insn_type = dis_dref;
1515 info->data_size = 8;
1516 break;
1517 case 'U':
1518 nbits = 8;
1519 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1520 extu = 1;
1521 break;
1522 case 'k':
1523 nbits = 8;
1524 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1525 signedp = 1;
1526 break;
1527 case 'K':
1528 nbits = 8;
1529 shift = 3;
1530 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1531 signedp = 1;
1532 break;
1533 case 'p':
1534 nbits = 8;
1535 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1536 signedp = 1;
1537 pcrel = 1;
1538 branch = 1;
1539 info->insn_type = dis_condbranch;
1540 break;
1541 case 'q':
1542 nbits = 11;
1543 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1544 signedp = 1;
1545 pcrel = 1;
1546 branch = 1;
1547 info->insn_type = dis_branch;
1548 break;
1549 case 'A':
1550 nbits = 8;
1551 shift = 2;
1552 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1553 pcrel = 1;
1554 /* FIXME: This can be lw or la. We assume it is lw. */
1555 info->insn_type = dis_dref;
1556 info->data_size = 4;
1557 break;
1558 case 'B':
1559 nbits = 5;
1560 shift = 3;
1561 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1562 pcrel = 1;
1563 info->insn_type = dis_dref;
1564 info->data_size = 8;
1565 break;
1566 case 'E':
1567 nbits = 5;
1568 shift = 2;
1569 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1570 pcrel = 1;
1571 break;
1572 default:
1573 abort ();
1574 }
1575
1576 if (! use_extend)
1577 {
1578 if (signedp && immed >= (1 << (nbits - 1)))
1579 immed -= 1 << nbits;
1580 immed <<= shift;
1581 if ((type == '<' || type == '>' || type == '[' || type == ']')
1582 && immed == 0)
1583 immed = 8;
1584 }
1585 else
1586 {
1587 if (extbits == 16)
1588 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1589 else if (extbits == 15)
1590 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1591 else
1592 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1593 immed &= (1 << extbits) - 1;
1594 if (! extu && immed >= (1 << (extbits - 1)))
1595 immed -= 1 << extbits;
1596 }
1597
1598 if (! pcrel)
1599 (*info->fprintf_func) (info->stream, "%d", immed);
1600 else
1601 {
1602 bfd_vma baseaddr;
252b5132
RH		 1603
1604 if (branch)
1605 {
1606 immed *= 2;
1607 baseaddr = memaddr + 2;
1608 }
1609 else if (use_extend)
1610 baseaddr = memaddr - 2;
1611 else
1612 {
1613 int status;
1614 bfd_byte buffer[2];
1615
1616 baseaddr = memaddr;
1617
1618 /* If this instruction is in the delay slot of a jr
1619 instruction, the base address is the address of the
1620 jr instruction. If it is in the delay slot of jalr
1621 instruction, the base address is the address of the
1622 jalr instruction. This test is unreliable: we have
1623 no way of knowing whether the previous word is
1624 instruction or data. */
1625 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1626 info);
1627 if (status == 0
1628 && (((info->endian == BFD_ENDIAN_BIG
1629 ? bfd_getb16 (buffer)
1630 : bfd_getl16 (buffer))
1631 & 0xf800) == 0x1800))
1632 baseaddr = memaddr - 4;
1633 else
1634 {
1635 status = (*info->read_memory_func) (memaddr - 2, buffer,
1636 2, info);
1637 if (status == 0
1638 && (((info->endian == BFD_ENDIAN_BIG
1639 ? bfd_getb16 (buffer)
1640 : bfd_getl16 (buffer))
1641 & 0xf81f) == 0xe800))
1642 baseaddr = memaddr - 2;
1643 }
1644 }
9bb28706 1645 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
022fac6d
TS		 1646 if (pcrel && branch
1647 && info->flavour == bfd_target_unknown_flavour)
1648 /* For gdb disassembler, maintain odd address. */
1649 info->target |= 1;
9bb28706 1650 (*info->print_address_func) (info->target, info);
252b5132
RH		 1651 }
1652 }
1653 break;
1654
1655 case 'a':
022fac6d
TS		 1656 {
1657 int jalx = l & 0x400;
1658
1659 if (! use_extend)
1660 extend = 0;
1661 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1662 if (!jalx && info->flavour == bfd_target_unknown_flavour)
1663 /* For gdb disassembler, maintain odd address. */
1664 l |= 1;
1665 }
9bb28706
CD		 1666 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1667 (*info->print_address_func) (info->target, info);
252b5132 1668 info->insn_type = dis_jsr;
252b5132
RH		 1669 info->branch_delay_insns = 1;
1670 break;
1671
1672 case 'l':
1673 case 'L':
1674 {
1675 int need_comma, amask, smask;
1676
1677 need_comma = 0;
1678
1679 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1680
1681 amask = (l >> 3) & 7;
1682
1683 if (amask > 0 && amask < 5)
1684 {
640c0ccd 1685 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
252b5132 1686 if (amask > 1)
aa5f19f2 1687 (*info->fprintf_func) (info->stream, "-%s",
640c0ccd 1688 mips_gpr_names[amask + 3]);
252b5132
RH		 1689 need_comma = 1;
1690 }
1691
1692 smask = (l >> 1) & 3;
1693 if (smask == 3)
1694 {
1695 (*info->fprintf_func) (info->stream, "%s??",
1696 need_comma ? "," : "");
1697 need_comma = 1;
1698 }
1699 else if (smask > 0)
1700 {
aa5f19f2 1701 (*info->fprintf_func) (info->stream, "%s%s",
252b5132 1702 need_comma ? "," : "",
640c0ccd 1703 mips_gpr_names[16]);
252b5132 1704 if (smask > 1)
aa5f19f2 1705 (*info->fprintf_func) (info->stream, "-%s",
640c0ccd 1706 mips_gpr_names[smask + 15]);
252b5132
RH		 1707 need_comma = 1;
1708 }
1709
1710 if (l & 1)
1711 {
aa5f19f2 1712 (*info->fprintf_func) (info->stream, "%s%s",
252b5132 1713 need_comma ? "," : "",
640c0ccd 1714 mips_gpr_names[31]);
252b5132
RH		 1715 need_comma = 1;
1716 }
1717
1718 if (amask == 5 || amask == 6)
1719 {
1720 (*info->fprintf_func) (info->stream, "%s$f0",
1721 need_comma ? "," : "");
1722 if (amask == 6)
1723 (*info->fprintf_func) (info->stream, "-$f1");
1724 }
1725 }
1726 break;
1727
0499d65b
TS		 1728 case 'm':
1729 case 'M':
1730 /* MIPS16e save/restore. */
1731 {
1732 int need_comma = 0;
1733 int amask, args, statics;
1734 int nsreg, smask;
1735 int framesz;
1736 int i, j;
1737
1738 l = l & 0x7f;
1739 if (use_extend)
1740 l |= extend << 16;
1741
1742 amask = (l >> 16) & 0xf;
1743 if (amask == MIPS16_ALL_ARGS)
1744 {
1745 args = 4;
1746 statics = 0;
1747 }
1748 else if (amask == MIPS16_ALL_STATICS)
1749 {
1750 args = 0;
1751 statics = 4;
1752 }
1753 else
1754 {
1755 args = amask >> 2;
1756 statics = amask & 3;
1757 }
1758
1759 if (args > 0) {
1760 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1761 if (args > 1)
1762 (*info->fprintf_func) (info->stream, "-%s",
1763 mips_gpr_names[4 + args - 1]);
1764 need_comma = 1;
1765 }
1766
1767 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
1768 if (framesz == 0 && !use_extend)
1769 framesz = 128;
1770
1771 (*info->fprintf_func) (info->stream, "%s%d",
1772 need_comma ? "," : "",
1773 framesz);
1774
1775 if (l & 0x40) /* $ra */
1776 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
1777
1778 nsreg = (l >> 24) & 0x7;
1779 smask = 0;
1780 if (l & 0x20) /* $s0 */
1781 smask |= 1 << 0;
1782 if (l & 0x10) /* $s1 */
1783 smask |= 1 << 1;
1784 if (nsreg > 0) /* $s2-$s8 */
1785 smask |= ((1 << nsreg) - 1) << 2;
1786
1787 /* Find first set static reg bit. */
1788 for (i = 0; i < 9; i++)
1789 {
1790 if (smask & (1 << i))
1791 {
1792 (*info->fprintf_func) (info->stream, ",%s",
1793 mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1794 /* Skip over string of set bits. */
1795 for (j = i; smask & (2 << j); j++)
1796 continue;
1797 if (j > i)
1798 (*info->fprintf_func) (info->stream, "-%s",
1799 mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1800 i = j + 1;
1801 }
1802 }
1803
1804 /* Statics $ax - $a3. */
1805 if (statics == 1)
1806 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
1807 else if (statics > 0)
1808 (*info->fprintf_func) (info->stream, ",%s-%s",
1809 mips_gpr_names[7 - statics + 1],
1810 mips_gpr_names[7]);
1811 }
1812 break;
1813
252b5132 1814 default:
aa5f19f2
NC		 1815 /* xgettext:c-format */
1816 (*info->fprintf_func)
1817 (info->stream,
1818 _("# internal disassembler error, unrecognised modifier (%c)"),
1819 type);
252b5132
RH		 1820 abort ();
1821 }
1822}
640c0ccd 1823
47b0e7ad
NC		 1824/* Disassemble mips16 instructions. */
1825
1826static int
1827print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
1828{
1829 int status;
1830 bfd_byte buffer[2];
1831 int length;
1832 int insn;
1833 bfd_boolean use_extend;
1834 int extend = 0;
1835 const struct mips_opcode *op, *opend;
1836
1837 info->bytes_per_chunk = 2;
1838 info->display_endian = info->endian;
1839 info->insn_info_valid = 1;
1840 info->branch_delay_insns = 0;
1841 info->data_size = 0;
1842 info->insn_type = dis_nonbranch;
1843 info->target = 0;
1844 info->target2 = 0;
1845
1846 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1847 if (status != 0)
1848 {
1849 (*info->memory_error_func) (status, memaddr, info);
1850 return -1;
1851 }
1852
1853 length = 2;
1854
1855 if (info->endian == BFD_ENDIAN_BIG)
1856 insn = bfd_getb16 (buffer);
1857 else
1858 insn = bfd_getl16 (buffer);
1859
1860 /* Handle the extend opcode specially. */
1861 use_extend = FALSE;
1862 if ((insn & 0xf800) == 0xf000)
1863 {
1864 use_extend = TRUE;
1865 extend = insn & 0x7ff;
1866
1867 memaddr += 2;
1868
1869 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1870 if (status != 0)
1871 {
1872 (*info->fprintf_func) (info->stream, "extend 0x%x",
1873 (unsigned int) extend);
1874 (*info->memory_error_func) (status, memaddr, info);
1875 return -1;
1876 }
1877
1878 if (info->endian == BFD_ENDIAN_BIG)
1879 insn = bfd_getb16 (buffer);
1880 else
1881 insn = bfd_getl16 (buffer);
1882
1883 /* Check for an extend opcode followed by an extend opcode. */
1884 if ((insn & 0xf800) == 0xf000)
1885 {
1886 (*info->fprintf_func) (info->stream, "extend 0x%x",
1887 (unsigned int) extend);
1888 info->insn_type = dis_noninsn;
1889 return length;
1890 }
1891
1892 length += 2;
1893 }
1894
1895 /* FIXME: Should probably use a hash table on the major opcode here. */
1896
1897 opend = mips16_opcodes + bfd_mips16_num_opcodes;
1898 for (op = mips16_opcodes; op < opend; op++)
1899 {
1900 if (op->pinfo != INSN_MACRO
1901 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1902 && (insn & op->mask) == op->match)
1903 {
1904 const char *s;
1905
1906 if (strchr (op->args, 'a') != NULL)
1907 {
1908 if (use_extend)
1909 {
1910 (*info->fprintf_func) (info->stream, "extend 0x%x",
1911 (unsigned int) extend);
1912 info->insn_type = dis_noninsn;
1913 return length - 2;
1914 }
1915
1916 use_extend = FALSE;
1917
1918 memaddr += 2;
1919
1920 status = (*info->read_memory_func) (memaddr, buffer, 2,
1921 info);
1922 if (status == 0)
1923 {
1924 use_extend = TRUE;
1925 if (info->endian == BFD_ENDIAN_BIG)
1926 extend = bfd_getb16 (buffer);
1927 else
1928 extend = bfd_getl16 (buffer);
1929 length += 2;
1930 }
1931 }
1932
1933 (*info->fprintf_func) (info->stream, "%s", op->name);
1934 if (op->args[0] != '\0')
1935 (*info->fprintf_func) (info->stream, "\t");
1936
1937 for (s = op->args; *s != '\0'; s++)
1938 {
1939 if (*s == ','
1940 && s[1] == 'w'
1941 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
1942 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
1943 {
1944 /* Skip the register and the comma. */
1945 ++s;
1946 continue;
1947 }
1948 if (*s == ','
1949 && s[1] == 'v'
1950 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
1951 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
1952 {
1953 /* Skip the register and the comma. */
1954 ++s;
1955 continue;
1956 }
1957 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
1958 info);
1959 }
1960
1961 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1962 {
1963 info->branch_delay_insns = 1;
1964 if (info->insn_type != dis_jsr)
1965 info->insn_type = dis_branch;
1966 }
1967
1968 return length;
1969 }
1970 }
1971
1972 if (use_extend)
1973 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
1974 (*info->fprintf_func) (info->stream, "0x%x", insn);
1975 info->insn_type = dis_noninsn;
1976
1977 return length;
1978}
1979
1980/* In an environment where we do not know the symbol type of the
1981 instruction we are forced to assume that the low order bit of the
1982 instructions' address may mark it as a mips16 instruction. If we
1983 are single stepping, or the pc is within the disassembled function,
1984 this works. Otherwise, we need a clue. Sometimes. */
1985
1986static int
1987_print_insn_mips (bfd_vma memaddr,
1988 struct disassemble_info *info,
1989 enum bfd_endian endianness)
1990{
1991 bfd_byte buffer[INSNLEN];
1992 int status;
1993
1994 set_default_mips_dis_options (info);
1995 parse_mips_dis_options (info->disassembler_options);
1996
1997#if 1
1998 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
1999 /* Only a few tools will work this way. */
2000 if (memaddr & 0x01)
2001 return print_insn_mips16 (memaddr, info);
2002#endif
2003
2004#if SYMTAB_AVAILABLE
2005 if (info->mach == bfd_mach_mips16
2006 || (info->flavour == bfd_target_elf_flavour
2007 && info->symbols != NULL
2008 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
2009 == STO_MIPS16)))
2010 return print_insn_mips16 (memaddr, info);
2011#endif
2012
2013 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
2014 if (status == 0)
2015 {
2016 unsigned long insn;
2017
2018 if (endianness == BFD_ENDIAN_BIG)
2019 insn = (unsigned long) bfd_getb32 (buffer);
2020 else
2021 insn = (unsigned long) bfd_getl32 (buffer);
2022
2023 return print_insn_mips (memaddr, insn, info);
2024 }
2025 else
2026 {
2027 (*info->memory_error_func) (status, memaddr, info);
2028 return -1;
2029 }
2030}
2031
2032int
2033print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
2034{
2035 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
2036}
2037
2038int
2039print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
2040{
2041 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
2042}
2043\f
640c0ccd 2044void
47b0e7ad 2045print_mips_disassembler_options (FILE *stream)
640c0ccd 2046{
4a9a3c54 2047 unsigned int i;
640c0ccd
CD		 2048
2049 fprintf (stream, _("\n\
2050The following MIPS specific disassembler options are supported for use\n\
2051with the -M switch (multiple options should be separated by commas):\n"));
2052
2053 fprintf (stream, _("\n\
2054 gpr-names=ABI Print GPR names according to specified ABI.\n\
2055 Default: based on binary being disassembled.\n"));
2056
2057 fprintf (stream, _("\n\
2058 fpr-names=ABI Print FPR names according to specified ABI.\n\
2059 Default: numeric.\n"));
2060
2061 fprintf (stream, _("\n\
2062 cp0-names=ARCH Print CP0 register names according to\n\
2063 specified architecture.\n\
2064 Default: based on binary being disassembled.\n"));
2065
af7ee8bf
CD		 2066 fprintf (stream, _("\n\
2067 hwr-names=ARCH Print HWR names according to specified \n\
2068 architecture.\n\
2069 Default: based on binary being disassembled.\n"));
2070
640c0ccd
CD		 2071 fprintf (stream, _("\n\
2072 reg-names=ABI Print GPR and FPR names according to\n\
2073 specified ABI.\n"));
2074
2075 fprintf (stream, _("\n\
af7ee8bf 2076 reg-names=ARCH Print CP0 register and HWR names according to\n\
640c0ccd
CD		 2077 specified architecture.\n"));
2078
2079 fprintf (stream, _("\n\
2080 For the options above, the following values are supported for \"ABI\":\n\
2081 "));
4a9a3c54 2082 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
640c0ccd
CD		 2083 fprintf (stream, " %s", mips_abi_choices[i].name);
2084 fprintf (stream, _("\n"));
2085
2086 fprintf (stream, _("\n\
2087 For the options above, The following values are supported for \"ARCH\":\n\
2088 "));
4a9a3c54 2089 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
640c0ccd
CD		 2090 if (*mips_arch_choices[i].name != '\0')
2091 fprintf (stream, " %s", mips_arch_choices[i].name);
2092 fprintf (stream, _("\n"));
2093
2094 fprintf (stream, _("\n"));
2095}
GDB Binutils - Deliverables
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