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x86-64: Clear the R_X86_64_converted_reloc_bit bit
[deliverable/binutils-gdb.git] / opcodes / mips-dis.c
CommitLineData
252b5132 1/* Print mips instructions for GDB, the GNU debugger, or for objdump.
219d1afa 2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
4
9b201bb5 5 This file is part of the GNU opcodes library.
252b5132 6
9b201bb5 7 This library is free software; you can redistribute it and/or modify
47b0e7ad 8 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
252b5132 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
252b5132 16
47b0e7ad
NC		 17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
252b5132 21
252b5132 22#include "sysdep.h"
6394c606 23#include "disassemble.h"
640c0ccd 24#include "libiberty.h"
252b5132
RH		 25#include "opcode/mips.h"
26#include "opintl.h"
27
28/* FIXME: These are needed to figure out if the code is mips16 or
29 not. The low bit of the address is often a good indicator. No
30 symbol table is available when this code runs out in an embedded
7f6621cd 31 system as when it is used for disassembler support in a monitor. */
252b5132
RH		 32
33#if !defined(EMBEDDED_ENV)
34#define SYMTAB_AVAILABLE 1
35#include "elf-bfd.h"
36#include "elf/mips.h"
37#endif
38
aa5f19f2
NC		 39/* Mips instructions are at maximum this many bytes long. */
40#define INSNLEN 4
41
252b5132 42\f
aa5f19f2 43/* FIXME: These should be shared with gdb somehow. */
252b5132 44
47b0e7ad
NC		 45struct mips_cp0sel_name
46{
47 unsigned int cp0reg;
48 unsigned int sel;
49 const char * const name;
bbcc0807
CD		 50};
51
47b0e7ad
NC		 52static const char * const mips_gpr_names_numeric[32] =
53{
640c0ccd
CD		 54 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
55 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
56 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
57 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
aa5f19f2
NC		 58};
59
47b0e7ad
NC		 60static const char * const mips_gpr_names_oldabi[32] =
61{
640c0ccd
CD		 62 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
63 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
64 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
65 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
aa5f19f2
NC		 66};
67
47b0e7ad
NC		 68static const char * const mips_gpr_names_newabi[32] =
69{
640c0ccd 70 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
0b14f26e 71 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
640c0ccd
CD		 72 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
73 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
74};
75
47b0e7ad
NC		 76static const char * const mips_fpr_names_numeric[32] =
77{
640c0ccd
CD		 78 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
79 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
80 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
81 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
82};
83
47b0e7ad
NC		 84static const char * const mips_fpr_names_32[32] =
85{
640c0ccd
CD		 86 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
87 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
88 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
89 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
90};
91
47b0e7ad
NC		 92static const char * const mips_fpr_names_n32[32] =
93{
640c0ccd
CD		 94 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
95 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
96 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
97 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
98};
99
47b0e7ad
NC		 100static const char * const mips_fpr_names_64[32] =
101{
640c0ccd
CD		 102 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
103 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
104 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
105 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
106};
107
47b0e7ad
NC		 108static const char * const mips_cp0_names_numeric[32] =
109{
640c0ccd
CD		 110 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
111 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
112 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
113 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
114};
115
dc76d757
AB		 116static const char * const mips_cp1_names_numeric[32] =
117{
118 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
119 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
120 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
121 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
122};
123
f409fd1e
MR		 124static const char * const mips_cp0_names_r3000[32] =
125{
126 "c0_index", "c0_random", "c0_entrylo", "$3",
127 "c0_context", "$5", "$6", "$7",
128 "c0_badvaddr", "$9", "c0_entryhi", "$11",
129 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
130 "$16", "$17", "$18", "$19",
131 "$20", "$21", "$22", "$23",
132 "$24", "$25", "$26", "$27",
133 "$28", "$29", "$30", "$31",
134};
135
136static const char * const mips_cp0_names_r4000[32] =
137{
138 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
139 "c0_context", "c0_pagemask", "c0_wired", "$7",
140 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
141 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
142 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
143 "c0_xcontext", "$21", "$22", "$23",
144 "$24", "$25", "c0_ecc", "c0_cacheerr",
145 "c0_taglo", "c0_taghi", "c0_errorepc", "$31",
146};
147
e407c74b
NC		 148static const char * const mips_cp0_names_r5900[32] =
149{
150 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
151 "c0_context", "c0_pagemask", "c0_wired", "$7",
152 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
153 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
154 "c0_config", "$17", "$18", "$19",
155 "$20", "$21", "$22", "c0_badpaddr",
156 "c0_depc", "c0_perfcnt", "$26", "$27",
157 "c0_taglo", "c0_taghi", "c0_errorepc", "$31"
158};
159
47b0e7ad
NC		 160static const char * const mips_cp0_names_mips3264[32] =
161{
640c0ccd
CD		 162 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
163 "c0_context", "c0_pagemask", "c0_wired", "$7",
164 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
165 "c0_status", "c0_cause", "c0_epc", "c0_prid",
166 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
167 "c0_xcontext", "$21", "$22", "c0_debug",
168 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
169 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
170};
171
dc76d757
AB		 172static const char * const mips_cp1_names_mips3264[32] =
173{
174 "c1_fir", "c1_ufr", "$2", "$3",
175 "c1_unfr", "$5", "$6", "$7",
176 "$8", "$9", "$10", "$11",
177 "$12", "$13", "$14", "$15",
178 "$16", "$17", "$18", "$19",
179 "$20", "$21", "$22", "$23",
180 "$24", "c1_fccr", "c1_fexr", "$27",
181 "c1_fenr", "$29", "$30", "c1_fcsr"
182};
183
47b0e7ad
NC		 184static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
185{
bbcc0807
CD		 186 { 16, 1, "c0_config1" },
187 { 16, 2, "c0_config2" },
188 { 16, 3, "c0_config3" },
189 { 18, 1, "c0_watchlo,1" },
190 { 18, 2, "c0_watchlo,2" },
191 { 18, 3, "c0_watchlo,3" },
192 { 18, 4, "c0_watchlo,4" },
193 { 18, 5, "c0_watchlo,5" },
194 { 18, 6, "c0_watchlo,6" },
195 { 18, 7, "c0_watchlo,7" },
196 { 19, 1, "c0_watchhi,1" },
197 { 19, 2, "c0_watchhi,2" },
198 { 19, 3, "c0_watchhi,3" },
199 { 19, 4, "c0_watchhi,4" },
200 { 19, 5, "c0_watchhi,5" },
201 { 19, 6, "c0_watchhi,6" },
202 { 19, 7, "c0_watchhi,7" },
203 { 25, 1, "c0_perfcnt,1" },
204 { 25, 2, "c0_perfcnt,2" },
205 { 25, 3, "c0_perfcnt,3" },
206 { 25, 4, "c0_perfcnt,4" },
207 { 25, 5, "c0_perfcnt,5" },
208 { 25, 6, "c0_perfcnt,6" },
209 { 25, 7, "c0_perfcnt,7" },
210 { 27, 1, "c0_cacheerr,1" },
211 { 27, 2, "c0_cacheerr,2" },
212 { 27, 3, "c0_cacheerr,3" },
213 { 28, 1, "c0_datalo" },
214 { 29, 1, "c0_datahi" }
215};
216
47b0e7ad
NC		 217static const char * const mips_cp0_names_mips3264r2[32] =
218{
af7ee8bf
CD		 219 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
220 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
221 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
222 "c0_status", "c0_cause", "c0_epc", "c0_prid",
223 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
224 "c0_xcontext", "$21", "$22", "c0_debug",
225 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
226 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
227};
228
47b0e7ad
NC		 229static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
230{
bbcc0807 231 { 4, 1, "c0_contextconfig" },
59c455b3
TS		 232 { 0, 1, "c0_mvpcontrol" },
233 { 0, 2, "c0_mvpconf0" },
234 { 0, 3, "c0_mvpconf1" },
235 { 1, 1, "c0_vpecontrol" },
236 { 1, 2, "c0_vpeconf0" },
237 { 1, 3, "c0_vpeconf1" },
238 { 1, 4, "c0_yqmask" },
239 { 1, 5, "c0_vpeschedule" },
240 { 1, 6, "c0_vpeschefback" },
241 { 2, 1, "c0_tcstatus" },
242 { 2, 2, "c0_tcbind" },
243 { 2, 3, "c0_tcrestart" },
244 { 2, 4, "c0_tchalt" },
245 { 2, 5, "c0_tccontext" },
246 { 2, 6, "c0_tcschedule" },
247 { 2, 7, "c0_tcschefback" },
bbcc0807 248 { 5, 1, "c0_pagegrain" },
59c455b3
TS		 249 { 6, 1, "c0_srsconf0" },
250 { 6, 2, "c0_srsconf1" },
251 { 6, 3, "c0_srsconf2" },
252 { 6, 4, "c0_srsconf3" },
253 { 6, 5, "c0_srsconf4" },
bbcc0807
CD		 254 { 12, 1, "c0_intctl" },
255 { 12, 2, "c0_srsctl" },
256 { 12, 3, "c0_srsmap" },
257 { 15, 1, "c0_ebase" },
258 { 16, 1, "c0_config1" },
259 { 16, 2, "c0_config2" },
260 { 16, 3, "c0_config3" },
261 { 18, 1, "c0_watchlo,1" },
262 { 18, 2, "c0_watchlo,2" },
263 { 18, 3, "c0_watchlo,3" },
264 { 18, 4, "c0_watchlo,4" },
265 { 18, 5, "c0_watchlo,5" },
266 { 18, 6, "c0_watchlo,6" },
267 { 18, 7, "c0_watchlo,7" },
268 { 19, 1, "c0_watchhi,1" },
269 { 19, 2, "c0_watchhi,2" },
270 { 19, 3, "c0_watchhi,3" },
271 { 19, 4, "c0_watchhi,4" },
272 { 19, 5, "c0_watchhi,5" },
273 { 19, 6, "c0_watchhi,6" },
274 { 19, 7, "c0_watchhi,7" },
275 { 23, 1, "c0_tracecontrol" },
276 { 23, 2, "c0_tracecontrol2" },
277 { 23, 3, "c0_usertracedata" },
278 { 23, 4, "c0_tracebpc" },
279 { 25, 1, "c0_perfcnt,1" },
280 { 25, 2, "c0_perfcnt,2" },
281 { 25, 3, "c0_perfcnt,3" },
282 { 25, 4, "c0_perfcnt,4" },
283 { 25, 5, "c0_perfcnt,5" },
284 { 25, 6, "c0_perfcnt,6" },
285 { 25, 7, "c0_perfcnt,7" },
286 { 27, 1, "c0_cacheerr,1" },
287 { 27, 2, "c0_cacheerr,2" },
288 { 27, 3, "c0_cacheerr,3" },
289 { 28, 1, "c0_datalo" },
290 { 28, 2, "c0_taglo1" },
291 { 28, 3, "c0_datalo1" },
292 { 28, 4, "c0_taglo2" },
293 { 28, 5, "c0_datalo2" },
294 { 28, 6, "c0_taglo3" },
295 { 28, 7, "c0_datalo3" },
296 { 29, 1, "c0_datahi" },
297 { 29, 2, "c0_taghi1" },
298 { 29, 3, "c0_datahi1" },
299 { 29, 4, "c0_taghi2" },
300 { 29, 5, "c0_datahi2" },
301 { 29, 6, "c0_taghi3" },
302 { 29, 7, "c0_datahi3" },
303};
304
640c0ccd 305/* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
47b0e7ad
NC		 306static const char * const mips_cp0_names_sb1[32] =
307{
640c0ccd
CD		 308 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
309 "c0_context", "c0_pagemask", "c0_wired", "$7",
310 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
311 "c0_status", "c0_cause", "c0_epc", "c0_prid",
312 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
313 "c0_xcontext", "$21", "$22", "c0_debug",
314 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
315 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
316};
317
47b0e7ad
NC		 318static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
319{
bbcc0807
CD		 320 { 16, 1, "c0_config1" },
321 { 18, 1, "c0_watchlo,1" },
322 { 19, 1, "c0_watchhi,1" },
323 { 22, 0, "c0_perftrace" },
324 { 23, 3, "c0_edebug" },
325 { 25, 1, "c0_perfcnt,1" },
326 { 25, 2, "c0_perfcnt,2" },
327 { 25, 3, "c0_perfcnt,3" },
328 { 25, 4, "c0_perfcnt,4" },
329 { 25, 5, "c0_perfcnt,5" },
330 { 25, 6, "c0_perfcnt,6" },
331 { 25, 7, "c0_perfcnt,7" },
332 { 26, 1, "c0_buserr_pa" },
333 { 27, 1, "c0_cacheerr_d" },
334 { 27, 3, "c0_cacheerr_d_pa" },
335 { 28, 1, "c0_datalo_i" },
336 { 28, 2, "c0_taglo_d" },
337 { 28, 3, "c0_datalo_d" },
338 { 29, 1, "c0_datahi_i" },
339 { 29, 2, "c0_taghi_d" },
340 { 29, 3, "c0_datahi_d" },
341};
342
52b6b6b9
JM		 343/* Xlr cop0 register names. */
344static const char * const mips_cp0_names_xlr[32] = {
345 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
346 "c0_context", "c0_pagemask", "c0_wired", "$7",
347 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
348 "c0_status", "c0_cause", "c0_epc", "c0_prid",
349 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
350 "c0_xcontext", "$21", "$22", "c0_debug",
351 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
352 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
353};
354
355/* XLR's CP0 Select Registers. */
356
357static const struct mips_cp0sel_name mips_cp0sel_names_xlr[] = {
358 { 9, 6, "c0_extintreq" },
359 { 9, 7, "c0_extintmask" },
360 { 15, 1, "c0_ebase" },
361 { 16, 1, "c0_config1" },
362 { 16, 2, "c0_config2" },
363 { 16, 3, "c0_config3" },
364 { 16, 7, "c0_procid2" },
365 { 18, 1, "c0_watchlo,1" },
366 { 18, 2, "c0_watchlo,2" },
367 { 18, 3, "c0_watchlo,3" },
368 { 18, 4, "c0_watchlo,4" },
369 { 18, 5, "c0_watchlo,5" },
370 { 18, 6, "c0_watchlo,6" },
371 { 18, 7, "c0_watchlo,7" },
372 { 19, 1, "c0_watchhi,1" },
373 { 19, 2, "c0_watchhi,2" },
374 { 19, 3, "c0_watchhi,3" },
375 { 19, 4, "c0_watchhi,4" },
376 { 19, 5, "c0_watchhi,5" },
377 { 19, 6, "c0_watchhi,6" },
378 { 19, 7, "c0_watchhi,7" },
379 { 25, 1, "c0_perfcnt,1" },
380 { 25, 2, "c0_perfcnt,2" },
381 { 25, 3, "c0_perfcnt,3" },
382 { 25, 4, "c0_perfcnt,4" },
383 { 25, 5, "c0_perfcnt,5" },
384 { 25, 6, "c0_perfcnt,6" },
385 { 25, 7, "c0_perfcnt,7" },
386 { 27, 1, "c0_cacheerr,1" },
387 { 27, 2, "c0_cacheerr,2" },
388 { 27, 3, "c0_cacheerr,3" },
389 { 28, 1, "c0_datalo" },
390 { 29, 1, "c0_datahi" }
391};
392
47b0e7ad
NC		 393static const char * const mips_hwr_names_numeric[32] =
394{
af7ee8bf
CD		 395 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
396 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
397 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
398 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
399};
400
47b0e7ad
NC		 401static const char * const mips_hwr_names_mips3264r2[32] =
402{
af7ee8bf
CD		 403 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
404 "$4", "$5", "$6", "$7",
405 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
406 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
407 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
408};
409
4edbb8e3
CF		 410static const char * const msa_control_names[32] =
411{
412 "msa_ir", "msa_csr", "msa_access", "msa_save",
413 "msa_modify", "msa_request", "msa_map", "msa_unmap",
414 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
415 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
416 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
417};
418
47b0e7ad
NC		 419struct mips_abi_choice
420{
421 const char * name;
640c0ccd
CD		 422 const char * const *gpr_names;
423 const char * const *fpr_names;
424};
425
47b0e7ad
NC		 426struct mips_abi_choice mips_abi_choices[] =
427{
640c0ccd
CD		 428 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
429 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
430 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
431 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
432};
433
47b0e7ad
NC		 434struct mips_arch_choice
435{
640c0ccd
CD		 436 const char *name;
437 int bfd_mach_valid;
438 unsigned long bfd_mach;
439 int processor;
440 int isa;
d301a56b 441 int ase;
640c0ccd 442 const char * const *cp0_names;
bbcc0807
CD		 443 const struct mips_cp0sel_name *cp0sel_names;
444 unsigned int cp0sel_names_len;
dc76d757 445 const char * const *cp1_names;
af7ee8bf 446 const char * const *hwr_names;
640c0ccd
CD		 447};
448
47b0e7ad
NC		 449const struct mips_arch_choice mips_arch_choices[] =
450{
d301a56b 451 { "numeric", 0, 0, 0, 0, 0,
dc76d757
AB		 452 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
453 mips_hwr_names_numeric },
bbcc0807 454
d301a56b 455 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 0,
dc76d757
AB		 456 mips_cp0_names_r3000, NULL, 0, mips_cp1_names_numeric,
457 mips_hwr_names_numeric },
d301a56b 458 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 0,
dc76d757
AB		 459 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
460 mips_hwr_names_numeric },
d301a56b 461 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 0,
dc76d757
AB		 462 mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric,
463 mips_hwr_names_numeric },
d301a56b 464 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 0,
dc76d757
AB		 465 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
466 mips_hwr_names_numeric },
d301a56b 467 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 0,
dc76d757
AB		 468 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
469 mips_hwr_names_numeric },
d301a56b 470 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 0,
dc76d757
AB		 471 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
472 mips_hwr_names_numeric },
d301a56b 473 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 0,
dc76d757
AB		 474 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
475 mips_hwr_names_numeric },
d301a56b 476 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 0,
dc76d757
AB		 477 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
478 mips_hwr_names_numeric },
d301a56b 479 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 0,
dc76d757
AB		 480 mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric,
481 mips_hwr_names_numeric },
d301a56b 482 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 0,
dc76d757
AB		 483 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
484 mips_hwr_names_numeric },
d301a56b 485 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 0,
dc76d757
AB		 486 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
487 mips_hwr_names_numeric },
d301a56b 488 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 0,
dc76d757
AB		 489 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
490 mips_hwr_names_numeric },
d301a56b 491 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 0,
dc76d757
AB		 492 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
493 mips_hwr_names_numeric },
d301a56b 494 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 0,
dc76d757
AB		 495 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
496 mips_hwr_names_numeric },
d301a56b 497 { "r5900", 1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3, 0,
dc76d757
AB		 498 mips_cp0_names_r5900, NULL, 0, mips_cp1_names_numeric,
499 mips_hwr_names_numeric },
d301a56b 500 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 0,
dc76d757
AB		 501 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
502 mips_hwr_names_numeric },
d301a56b 503 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
dc76d757
AB		 504 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
505 mips_hwr_names_numeric },
d301a56b 506 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
dc76d757
AB		 507 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
508 mips_hwr_names_numeric },
d301a56b 509 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 0,
dc76d757
AB		 510 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
511 mips_hwr_names_numeric },
d301a56b 512 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 0,
dc76d757
AB		 513 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
514 mips_hwr_names_numeric },
d301a56b 515 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 0,
dc76d757
AB		 516 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
517 mips_hwr_names_numeric },
d301a56b 518 { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, 0,
dc76d757
AB		 519 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
520 mips_hwr_names_numeric },
d301a56b 521 { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, 0,
dc76d757
AB		 522 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
523 mips_hwr_names_numeric },
d301a56b 524 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 0,
dc76d757
AB		 525 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
526 mips_hwr_names_numeric },
bbcc0807 527
640c0ccd
CD		 528 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
529 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
530 _MIPS32 Architecture For Programmers Volume I: Introduction to the
531 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
532 page 1. */
533 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
d301a56b 534 ISA_MIPS32, ASE_SMARTMIPS,
bbcc0807
CD		 535 mips_cp0_names_mips3264,
536 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
dc76d757 537 mips_cp1_names_mips3264, mips_hwr_names_numeric },
bbcc0807 538
af7ee8bf 539 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
d301a56b 540 ISA_MIPS32R2,
7f3c4072 541 (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D
7d64c587 542 | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA),
bbcc0807
CD		 543 mips_cp0_names_mips3264r2,
544 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
dc76d757 545 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
bbcc0807 546
ae52f483
AB		 547 { "mips32r3", 1, bfd_mach_mipsisa32r3, CPU_MIPS32R3,
548 ISA_MIPS32R3,
549 (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D
550 | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA),
551 mips_cp0_names_mips3264r2,
552 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
553 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
554
555 { "mips32r5", 1, bfd_mach_mipsisa32r5, CPU_MIPS32R5,
556 ISA_MIPS32R5,
557 (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D
558 | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA),
559 mips_cp0_names_mips3264r2,
560 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
561 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
562
7361da2c
AB		 563 { "mips32r6", 1, bfd_mach_mipsisa32r6, CPU_MIPS32R6,
564 ISA_MIPS32R6,
565 (ASE_EVA | ASE_MSA | ASE_VIRT | ASE_XPA | ASE_MCU | ASE_MT | ASE_DSP
6f20c942 566 | ASE_DSPR2 | ASE_DSPR3 | ASE_CRC | ASE_GINV),
7361da2c
AB		 567 mips_cp0_names_mips3264r2,
568 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
569 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
570
640c0ccd
CD		 571 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
572 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
d301a56b 573 ISA_MIPS64, ASE_MIPS3D | ASE_MDMX,
bbcc0807
CD		 574 mips_cp0_names_mips3264,
575 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
dc76d757 576 mips_cp1_names_mips3264, mips_hwr_names_numeric },
bbcc0807 577
5f74bc13 578 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
d301a56b 579 ISA_MIPS64R2,
7f3c4072 580 (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT
7d64c587 581 | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA),
5f74bc13
CD		 582 mips_cp0_names_mips3264r2,
583 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
dc76d757 584 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
5f74bc13 585
ae52f483
AB		 586 { "mips64r3", 1, bfd_mach_mipsisa64r3, CPU_MIPS64R3,
587 ISA_MIPS64R3,
588 (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT
589 | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA),
590 mips_cp0_names_mips3264r2,
591 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
592 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
593
594 { "mips64r5", 1, bfd_mach_mipsisa64r5, CPU_MIPS64R5,
595 ISA_MIPS64R5,
596 (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT
597 | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA),
598 mips_cp0_names_mips3264r2,
599 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
600 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
601
7361da2c
AB		 602 { "mips64r6", 1, bfd_mach_mipsisa64r6, CPU_MIPS64R6,
603 ISA_MIPS64R6,
604 (ASE_EVA | ASE_MSA | ASE_MSA64 | ASE_XPA | ASE_VIRT | ASE_VIRT64
730c3174 605 | ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 | ASE_CRC
6f20c942 606 | ASE_CRC64 | ASE_GINV),
7361da2c
AB		 607 mips_cp0_names_mips3264r2,
608 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
609 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
610
38bf472a
MR		 611 { "interaptiv-mr2", 1, bfd_mach_mips_interaptiv_mr2, CPU_INTERAPTIV_MR2,
612 ISA_MIPS32R3,
613 ASE_MT | ASE_EVA | ASE_DSP | ASE_DSPR2 | ASE_MIPS16E2 | ASE_MIPS16E2_MT,
614 mips_cp0_names_mips3264r2,
615 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
616 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
617
640c0ccd 618 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
d301a56b 619 ISA_MIPS64 | INSN_SB1, ASE_MIPS3D,
bbcc0807
CD		 620 mips_cp0_names_sb1,
621 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
dc76d757 622 mips_cp1_names_mips3264, mips_hwr_names_numeric },
640c0ccd 623
350cc38d 624 { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
d301a56b 625 ISA_MIPS3 | INSN_LOONGSON_2E, 0, mips_cp0_names_numeric,
dc76d757 626 NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
350cc38d
MS		 627
628 { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
d301a56b 629 ISA_MIPS3 | INSN_LOONGSON_2F, 0, mips_cp0_names_numeric,
dc76d757 630 NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
350cc38d 631
fd503541 632 { "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
4ba154f5 633 ISA_MIPS64R2 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric,
dc76d757 634 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
fd503541 635
57b592a3 636 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
d301a56b 637 ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0,
dc76d757 638 mips_cp1_names_mips3264, mips_hwr_names_numeric },
57b592a3 639
dd6a37e7 640 { "octeon+", 1, bfd_mach_mips_octeonp, CPU_OCTEONP,
d301a56b 641 ISA_MIPS64R2 | INSN_OCTEONP, 0, mips_cp0_names_numeric,
dc76d757 642 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
432233b3
AP		 643
644 { "octeon2", 1, bfd_mach_mips_octeon2, CPU_OCTEON2,
d301a56b 645 ISA_MIPS64R2 | INSN_OCTEON2, 0, mips_cp0_names_numeric,
dc76d757 646 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
dd6a37e7 647
2c629856
N		 648 { "octeon3", 1, bfd_mach_mips_octeon3, CPU_OCTEON3,
649 ISA_MIPS64R5 | INSN_OCTEON3, ASE_VIRT | ASE_VIRT64,
650 mips_cp0_names_numeric,
651 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
652
52b6b6b9 653 { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
d301a56b 654 ISA_MIPS64 | INSN_XLR, 0,
52b6b6b9
JM		 655 mips_cp0_names_xlr,
656 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
dc76d757 657 mips_cp1_names_mips3264, mips_hwr_names_numeric },
52b6b6b9 658
55a36193
MK		 659 /* XLP is mostly like XLR, with the prominent exception it is being
660 MIPS64R2. */
661 { "xlp", 1, bfd_mach_mips_xlr, CPU_XLR,
d301a56b 662 ISA_MIPS64R2 | INSN_XLR, 0,
55a36193
MK		 663 mips_cp0_names_xlr,
664 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
dc76d757 665 mips_cp1_names_mips3264, mips_hwr_names_numeric },
55a36193 666
640c0ccd
CD		 667 /* This entry, mips16, is here only for ISA/processor selection; do
668 not print its name. */
25499ac7
MR		 669 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS64,
670 ASE_MIPS16E2 | ASE_MIPS16E2_MT,
dc76d757
AB		 671 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
672 mips_hwr_names_numeric },
640c0ccd
CD		 673};
674
675/* ISA and processor type to disassemble for, and register names to use.
676 set_default_mips_dis_options and parse_mips_dis_options fill in these
677 values. */
678static int mips_processor;
679static int mips_isa;
d301a56b 680static int mips_ase;
df58fc94 681static int micromips_ase;
640c0ccd
CD		 682static const char * const *mips_gpr_names;
683static const char * const *mips_fpr_names;
684static const char * const *mips_cp0_names;
bbcc0807
CD		 685static const struct mips_cp0sel_name *mips_cp0sel_names;
686static int mips_cp0sel_names_len;
dc76d757 687static const char * const *mips_cp1_names;
af7ee8bf 688static const char * const *mips_hwr_names;
640c0ccd 689
986e18a5 690/* Other options */
47b0e7ad 691static int no_aliases; /* If set disassemble as most general inst. */
640c0ccd
CD		 692\f
693static const struct mips_abi_choice *
47b0e7ad 694choose_abi_by_name (const char *name, unsigned int namelen)
640c0ccd
CD		 695{
696 const struct mips_abi_choice *c;
697 unsigned int i;
698
699 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
47b0e7ad
NC		 700 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
701 && strlen (mips_abi_choices[i].name) == namelen)
702 c = &mips_abi_choices[i];
703
640c0ccd
CD		 704 return c;
705}
706
707static const struct mips_arch_choice *
47b0e7ad 708choose_arch_by_name (const char *name, unsigned int namelen)
640c0ccd
CD		 709{
710 const struct mips_arch_choice *c = NULL;
711 unsigned int i;
712
713 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
47b0e7ad
NC		 714 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
715 && strlen (mips_arch_choices[i].name) == namelen)
716 c = &mips_arch_choices[i];
717
640c0ccd
CD		 718 return c;
719}
720
721static const struct mips_arch_choice *
47b0e7ad 722choose_arch_by_number (unsigned long mach)
640c0ccd
CD		 723{
724 static unsigned long hint_bfd_mach;
725 static const struct mips_arch_choice *hint_arch_choice;
726 const struct mips_arch_choice *c;
727 unsigned int i;
728
729 /* We optimize this because even if the user specifies no
730 flags, this will be done for every instruction! */
731 if (hint_bfd_mach == mach
732 && hint_arch_choice != NULL
733 && hint_arch_choice->bfd_mach == hint_bfd_mach)
734 return hint_arch_choice;
735
736 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
737 {
738 if (mips_arch_choices[i].bfd_mach_valid
739 && mips_arch_choices[i].bfd_mach == mach)
740 {
741 c = &mips_arch_choices[i];
742 hint_bfd_mach = mach;
743 hint_arch_choice = c;
744 }
745 }
746 return c;
747}
748
47b0e7ad
NC		 749/* Check if the object uses NewABI conventions. */
750
751static int
752is_newabi (Elf_Internal_Ehdr *header)
753{
754 /* There are no old-style ABIs which use 64-bit ELF. */
755 if (header->e_ident[EI_CLASS] == ELFCLASS64)
756 return 1;
757
758 /* If a 32-bit ELF file, n32 is a new-style ABI. */
759 if ((header->e_flags & EF_MIPS_ABI2) != 0)
760 return 1;
761
762 return 0;
763}
764
df58fc94
RS		 765/* Check if the object has microMIPS ASE code. */
766
767static int
768is_micromips (Elf_Internal_Ehdr *header)
769{
770 if ((header->e_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0)
771 return 1;
772
773 return 0;
774}
775
5e7fc731
MR		 776/* Convert ASE flags from .MIPS.abiflags to internal values. */
777
778static unsigned long
779mips_convert_abiflags_ases (unsigned long afl_ases)
780{
781 unsigned long opcode_ases = 0;
782
783 if (afl_ases & AFL_ASE_DSP)
784 opcode_ases |= ASE_DSP;
785 if (afl_ases & AFL_ASE_DSPR2)
786 opcode_ases |= ASE_DSPR2;
787 if (afl_ases & AFL_ASE_EVA)
788 opcode_ases |= ASE_EVA;
789 if (afl_ases & AFL_ASE_MCU)
790 opcode_ases |= ASE_MCU;
791 if (afl_ases & AFL_ASE_MDMX)
792 opcode_ases |= ASE_MDMX;
793 if (afl_ases & AFL_ASE_MIPS3D)
794 opcode_ases |= ASE_MIPS3D;
795 if (afl_ases & AFL_ASE_MT)
796 opcode_ases |= ASE_MT;
797 if (afl_ases & AFL_ASE_SMARTMIPS)
798 opcode_ases |= ASE_SMARTMIPS;
799 if (afl_ases & AFL_ASE_VIRT)
800 opcode_ases |= ASE_VIRT;
801 if (afl_ases & AFL_ASE_MSA)
802 opcode_ases |= ASE_MSA;
803 if (afl_ases & AFL_ASE_XPA)
804 opcode_ases |= ASE_XPA;
805 if (afl_ases & AFL_ASE_DSPR3)
806 opcode_ases |= ASE_DSPR3;
25499ac7
MR		 807 if (afl_ases & AFL_ASE_MIPS16E2)
808 opcode_ases |= ASE_MIPS16E2;
5e7fc731
MR		 809 return opcode_ases;
810}
811
60804c53
MR		 812/* Calculate combination ASE flags from regular ASE flags. */
813
814static unsigned long
815mips_calculate_combination_ases (unsigned long opcode_ases)
816{
817 unsigned long combination_ases = 0;
818
9785fc2a
MR		 819 if ((opcode_ases & (ASE_XPA | ASE_VIRT)) == (ASE_XPA | ASE_VIRT))
820 combination_ases |= ASE_XPA_VIRT;
60804c53
MR		 821 if ((opcode_ases & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT))
822 combination_ases |= ASE_MIPS16E2_MT;
823 return combination_ases;
824}
825
47b0e7ad
NC		 826static void
827set_default_mips_dis_options (struct disassemble_info *info)
640c0ccd
CD		 828{
829 const struct mips_arch_choice *chosen_arch;
830
df58fc94
RS		 831 /* Defaults: mipsIII/r3000 (?!), no microMIPS ASE (any compressed code
832 is MIPS16 ASE) (o)32-style ("oldabi") GPR names, and numeric FPR,
833 CP0 register, and HWR names. */
640c0ccd 834 mips_isa = ISA_MIPS3;
df58fc94
RS		 835 mips_processor = CPU_R3000;
836 micromips_ase = 0;
d301a56b 837 mips_ase = 0;
640c0ccd
CD		 838 mips_gpr_names = mips_gpr_names_oldabi;
839 mips_fpr_names = mips_fpr_names_numeric;
840 mips_cp0_names = mips_cp0_names_numeric;
bbcc0807
CD		 841 mips_cp0sel_names = NULL;
842 mips_cp0sel_names_len = 0;
dc76d757 843 mips_cp1_names = mips_cp1_names_numeric;
af7ee8bf 844 mips_hwr_names = mips_hwr_names_numeric;
986e18a5 845 no_aliases = 0;
640c0ccd 846
640c0ccd
CD		 847 /* Set ISA, architecture, and cp0 register names as best we can. */
848#if ! SYMTAB_AVAILABLE
849 /* This is running out on a target machine, not in a host tool.
850 FIXME: Where does mips_target_info come from? */
851 target_processor = mips_target_info.processor;
852 mips_isa = mips_target_info.isa;
d301a56b 853 mips_ase = mips_target_info.ase;
640c0ccd
CD		 854#else
855 chosen_arch = choose_arch_by_number (info->mach);
856 if (chosen_arch != NULL)
857 {
858 mips_processor = chosen_arch->processor;
859 mips_isa = chosen_arch->isa;
d301a56b 860 mips_ase = chosen_arch->ase;
bbcc0807
CD		 861 mips_cp0_names = chosen_arch->cp0_names;
862 mips_cp0sel_names = chosen_arch->cp0sel_names;
863 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
dc76d757 864 mips_cp1_names = chosen_arch->cp1_names;
bbcc0807 865 mips_hwr_names = chosen_arch->hwr_names;
640c0ccd 866 }
8184783a
MR		 867
868 /* Update settings according to the ELF file header flags. */
869 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
870 {
5e7fc731
MR		 871 struct bfd *abfd = info->section->owner;
872 Elf_Internal_Ehdr *header = elf_elfheader (abfd);
4df995c7
MR		 873 Elf_Internal_ABIFlags_v0 *abiflags = NULL;
874
9e76c212
MR		 875 /* We won't ever get here if !HAVE_BFD_MIPS_ELF_GET_ABIFLAGS,
876 because we won't then have a MIPS/ELF BFD, however we need
877 to guard against a link error in a `--enable-targets=...'
878 configuration with a 32-bit host where the MIPS target is
879 a secondary, or with MIPS/ECOFF configurations. */
880#ifdef HAVE_BFD_MIPS_ELF_GET_ABIFLAGS
4df995c7
MR		 881 abiflags = bfd_mips_elf_get_abiflags (abfd);
882#endif
8184783a
MR		 883 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
884 if (is_newabi (header))
885 mips_gpr_names = mips_gpr_names_newabi;
886 /* If a microMIPS binary, then don't use MIPS16 bindings. */
887 micromips_ase = is_micromips (header);
5e7fc731
MR		 888 /* OR in any extra ASE flags set in ELF file structures. */
889 if (abiflags)
890 mips_ase |= mips_convert_abiflags_ases (abiflags->ases);
891 else if (header->e_flags & EF_MIPS_ARCH_ASE_MDMX)
892 mips_ase |= ASE_MDMX;
8184783a 893 }
91068ec6 894#endif
60804c53 895 mips_ase |= mips_calculate_combination_ases (mips_ase);
640c0ccd
CD		 896}
897
9785fc2a
MR		 898/* Parse an ASE disassembler option and set the corresponding global
899 ASE flag(s). Return TRUE if successful, FALSE otherwise. */
b015e599 900
9785fc2a
MR		 901static bfd_boolean
902parse_mips_ase_option (const char *option)
903{
4edbb8e3
CF		 904 if (CONST_STRNEQ (option, "msa"))
905 {
906 mips_ase |= ASE_MSA;
ae52f483
AB		 907 if ((mips_isa & INSN_ISA_MASK) == ISA_MIPS64R2
908 || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R3
7361da2c
AB		 909 || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R5
910 || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R6)
4edbb8e3 911 mips_ase |= ASE_MSA64;
9785fc2a 912 return TRUE;
4edbb8e3
CF		 913 }
914
b015e599
AP		 915 if (CONST_STRNEQ (option, "virt"))
916 {
d301a56b 917 mips_ase |= ASE_VIRT;
ae52f483
AB		 918 if (mips_isa & ISA_MIPS64R2
919 || mips_isa & ISA_MIPS64R3
7361da2c
AB		 920 || mips_isa & ISA_MIPS64R5
921 || mips_isa & ISA_MIPS64R6)
d301a56b 922 mips_ase |= ASE_VIRT64;
9785fc2a 923 return TRUE;
b015e599 924 }
7d64c587
AB		 925
926 if (CONST_STRNEQ (option, "xpa"))
927 {
928 mips_ase |= ASE_XPA;
9785fc2a
MR		 929 return TRUE;
930 }
931
6f20c942
FS		 932 if (CONST_STRNEQ (option, "ginv"))
933 {
934 mips_ase |= ASE_GINV;
935 return TRUE;
936 }
937
9785fc2a
MR		 938 return FALSE;
939}
940
941static void
942parse_mips_dis_option (const char *option, unsigned int len)
943{
944 unsigned int i, optionlen, vallen;
945 const char *val;
946 const struct mips_abi_choice *chosen_abi;
947 const struct mips_arch_choice *chosen_arch;
948
949 /* Try to match options that are simple flags */
950 if (CONST_STRNEQ (option, "no-aliases"))
951 {
952 no_aliases = 1;
7d64c587
AB		 953 return;
954 }
43e65147 955
9785fc2a
MR		 956 if (parse_mips_ase_option (option))
957 {
958 mips_ase |= mips_calculate_combination_ases (mips_ase);
959 return;
960 }
43e65147 961
640c0ccd
CD		 962 /* Look for the = that delimits the end of the option name. */
963 for (i = 0; i < len; i++)
47b0e7ad
NC		 964 if (option[i] == '=')
965 break;
966
640c0ccd
CD		 967 if (i == 0) /* Invalid option: no name before '='. */
968 return;
969 if (i == len) /* Invalid option: no '='. */
970 return;
971 if (i == (len - 1)) /* Invalid option: no value after '='. */
972 return;
973
974 optionlen = i;
975 val = option + (optionlen + 1);
976 vallen = len - (optionlen + 1);
977
47b0e7ad
NC		 978 if (strncmp ("gpr-names", option, optionlen) == 0
979 && strlen ("gpr-names") == optionlen)
640c0ccd
CD		 980 {
981 chosen_abi = choose_abi_by_name (val, vallen);
bbcc0807 982 if (chosen_abi != NULL)
640c0ccd
CD		 983 mips_gpr_names = chosen_abi->gpr_names;
984 return;
985 }
986
47b0e7ad
NC		 987 if (strncmp ("fpr-names", option, optionlen) == 0
988 && strlen ("fpr-names") == optionlen)
640c0ccd
CD		 989 {
990 chosen_abi = choose_abi_by_name (val, vallen);
bbcc0807 991 if (chosen_abi != NULL)
640c0ccd
CD		 992 mips_fpr_names = chosen_abi->fpr_names;
993 return;
994 }
995
47b0e7ad
NC		 996 if (strncmp ("cp0-names", option, optionlen) == 0
997 && strlen ("cp0-names") == optionlen)
640c0ccd
CD		 998 {
999 chosen_arch = choose_arch_by_name (val, vallen);
bbcc0807
CD		 1000 if (chosen_arch != NULL)
1001 {
1002 mips_cp0_names = chosen_arch->cp0_names;
1003 mips_cp0sel_names = chosen_arch->cp0sel_names;
1004 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
1005 }
640c0ccd
CD		 1006 return;
1007 }
1008
dc76d757
AB		 1009 if (strncmp ("cp1-names", option, optionlen) == 0
1010 && strlen ("cp1-names") == optionlen)
1011 {
1012 chosen_arch = choose_arch_by_name (val, vallen);
1013 if (chosen_arch != NULL)
1014 mips_cp1_names = chosen_arch->cp1_names;
1015 return;
1016 }
1017
47b0e7ad
NC		 1018 if (strncmp ("hwr-names", option, optionlen) == 0
1019 && strlen ("hwr-names") == optionlen)
af7ee8bf
CD		 1020 {
1021 chosen_arch = choose_arch_by_name (val, vallen);
bbcc0807 1022 if (chosen_arch != NULL)
af7ee8bf
CD		 1023 mips_hwr_names = chosen_arch->hwr_names;
1024 return;
1025 }
1026
47b0e7ad
NC		 1027 if (strncmp ("reg-names", option, optionlen) == 0
1028 && strlen ("reg-names") == optionlen)
640c0ccd
CD		 1029 {
1030 /* We check both ABI and ARCH here unconditionally, so
1031 that "numeric" will do the desirable thing: select
1032 numeric register names for all registers. Other than
1033 that, a given name probably won't match both. */
1034 chosen_abi = choose_abi_by_name (val, vallen);
1035 if (chosen_abi != NULL)
1036 {
bbcc0807
CD		 1037 mips_gpr_names = chosen_abi->gpr_names;
1038 mips_fpr_names = chosen_abi->fpr_names;
640c0ccd
CD		 1039 }
1040 chosen_arch = choose_arch_by_name (val, vallen);
1041 if (chosen_arch != NULL)
1042 {
bbcc0807
CD		 1043 mips_cp0_names = chosen_arch->cp0_names;
1044 mips_cp0sel_names = chosen_arch->cp0sel_names;
1045 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
dc76d757 1046 mips_cp1_names = chosen_arch->cp1_names;
bbcc0807 1047 mips_hwr_names = chosen_arch->hwr_names;
640c0ccd
CD		 1048 }
1049 return;
1050 }
1051
1052 /* Invalid option. */
1053}
1054
47b0e7ad
NC		 1055static void
1056parse_mips_dis_options (const char *options)
640c0ccd
CD		 1057{
1058 const char *option_end;
1059
1060 if (options == NULL)
1061 return;
1062
1063 while (*options != '\0')
1064 {
1065 /* Skip empty options. */
1066 if (*options == ',')
1067 {
1068 options++;
1069 continue;
1070 }
1071
1072 /* We know that *options is neither NUL or a comma. */
1073 option_end = options + 1;
1074 while (*option_end != ',' && *option_end != '\0')
1075 option_end++;
1076
1077 parse_mips_dis_option (options, option_end - options);
1078
1079 /* Go on to the next one. If option_end points to a comma, it
1080 will be skipped above. */
1081 options = option_end;
1082 }
1083}
1084
bbcc0807 1085static const struct mips_cp0sel_name *
47b0e7ad
NC		 1086lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
1087 unsigned int len,
1088 unsigned int cp0reg,
1089 unsigned int sel)
bbcc0807
CD		 1090{
1091 unsigned int i;
1092
1093 for (i = 0; i < len; i++)
1094 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
1095 return &names[i];
1096 return NULL;
1097}
ab902481
RS		 1098
1099/* Print register REGNO, of type TYPE, for instruction OPCODE. */
aa5f19f2 1100
794ac9d0 1101static void
ab902481
RS		 1102print_reg (struct disassemble_info *info, const struct mips_opcode *opcode,
1103 enum mips_reg_operand_type type, int regno)
252b5132 1104{
ab902481
RS		 1105 switch (type)
1106 {
1107 case OP_REG_GP:
1108 info->fprintf_func (info->stream, "%s", mips_gpr_names[regno]);
1109 break;
440cc0bc 1110
ab902481
RS		 1111 case OP_REG_FP:
1112 info->fprintf_func (info->stream, "%s", mips_fpr_names[regno]);
1113 break;
252b5132 1114
ab902481
RS		 1115 case OP_REG_CCC:
1116 if (opcode->pinfo & (FP_D | FP_S))
1117 info->fprintf_func (info->stream, "$fcc%d", regno);
1118 else
1119 info->fprintf_func (info->stream, "$cc%d", regno);
1120 break;
794ac9d0 1121
ab902481
RS		 1122 case OP_REG_VEC:
1123 if (opcode->membership & INSN_5400)
1124 info->fprintf_func (info->stream, "$f%d", regno);
1125 else
1126 info->fprintf_func (info->stream, "$v%d", regno);
1127 break;
794ac9d0 1128
ab902481
RS		 1129 case OP_REG_ACC:
1130 info->fprintf_func (info->stream, "$ac%d", regno);
1131 break;
794ac9d0 1132
ab902481
RS		 1133 case OP_REG_COPRO:
1134 if (opcode->name[strlen (opcode->name) - 1] == '0')
1135 info->fprintf_func (info->stream, "%s", mips_cp0_names[regno]);
dc76d757
AB		 1136 else if (opcode->name[strlen (opcode->name) - 1] == '1')
1137 info->fprintf_func (info->stream, "%s", mips_cp1_names[regno]);
ab902481
RS		 1138 else
1139 info->fprintf_func (info->stream, "$%d", regno);
1140 break;
8b082fb1 1141
ab902481
RS		 1142 case OP_REG_HW:
1143 info->fprintf_func (info->stream, "%s", mips_hwr_names[regno]);
1144 break;
14daeee3
RS		 1145
1146 case OP_REG_VF:
1147 info->fprintf_func (info->stream, "$vf%d", regno);
1148 break;
1149
1150 case OP_REG_VI:
1151 info->fprintf_func (info->stream, "$vi%d", regno);
1152 break;
1153
1154 case OP_REG_R5900_I:
1155 info->fprintf_func (info->stream, "$I");
1156 break;
1157
1158 case OP_REG_R5900_Q:
1159 info->fprintf_func (info->stream, "$Q");
1160 break;
1161
1162 case OP_REG_R5900_R:
1163 info->fprintf_func (info->stream, "$R");
1164 break;
1165
1166 case OP_REG_R5900_ACC:
1167 info->fprintf_func (info->stream, "$ACC");
1168 break;
4edbb8e3
CF		 1169
1170 case OP_REG_MSA:
1171 info->fprintf_func (info->stream, "$w%d", regno);
1172 break;
1173
1174 case OP_REG_MSA_CTRL:
1175 info->fprintf_func (info->stream, "%s", msa_control_names[regno]);
1176 break;
1177
ab902481
RS		 1178 }
1179}
1180\f
1181/* Used to track the state carried over from previous operands in
1182 an instruction. */
1183struct mips_print_arg_state {
1184 /* The value of the last OP_INT seen. We only use this for OP_MSB,
1185 where the value is known to be unsigned and small. */
1186 unsigned int last_int;
1187
1188 /* The type and number of the last OP_REG seen. We only use this for
1189 OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG. */
1190 enum mips_reg_operand_type last_reg_type;
1191 unsigned int last_regno;
7361da2c
AB		 1192 unsigned int dest_regno;
1193 unsigned int seen_dest;
ab902481 1194};
fd25c5a9 1195
ab902481 1196/* Initialize STATE for the start of an instruction. */
fd25c5a9 1197
ab902481
RS		 1198static inline void
1199init_print_arg_state (struct mips_print_arg_state *state)
1200{
1201 memset (state, 0, sizeof (*state));
1202}
fd25c5a9 1203
14daeee3
RS		 1204/* Print OP_VU0_SUFFIX or OP_VU0_MATCH_SUFFIX operand OPERAND,
1205 whose value is given by UVAL. */
1206
1207static void
1208print_vu0_channel (struct disassemble_info *info,
1209 const struct mips_operand *operand, unsigned int uval)
1210{
1211 if (operand->size == 4)
1212 info->fprintf_func (info->stream, "%s%s%s%s",
1213 uval & 8 ? "x" : "",
1214 uval & 4 ? "y" : "",
1215 uval & 2 ? "z" : "",
1216 uval & 1 ? "w" : "");
1217 else if (operand->size == 2)
1218 info->fprintf_func (info->stream, "%c", "xyzw"[uval]);
1219 else
1220 abort ();
1221}
1222
7361da2c
AB		 1223/* Record information about a register operand. */
1224
1225static void
1226mips_seen_register (struct mips_print_arg_state *state,
1227 unsigned int regno,
1228 enum mips_reg_operand_type reg_type)
1229{
1230 state->last_reg_type = reg_type;
1231 state->last_regno = regno;
1232
1233 if (!state->seen_dest)
1234 {
1235 state->seen_dest = 1;
1236 state->dest_regno = regno;
1237 }
1238}
1239
38bf472a
MR		 1240/* Print SAVE/RESTORE instruction operands according to the argument
1241 register mask AMASK, the number of static registers saved NSREG,
1242 the $ra, $s0 and $s1 register specifiers RA, S0 and S1 respectively,
1243 and the frame size FRAME_SIZE. */
1244
1245static void
1246mips_print_save_restore (struct disassemble_info *info, unsigned int amask,
1247 unsigned int nsreg, unsigned int ra,
1248 unsigned int s0, unsigned int s1,
1249 unsigned int frame_size)
1250{
1251 const fprintf_ftype infprintf = info->fprintf_func;
1252 unsigned int nargs, nstatics, smask, i, j;
1253 void *is = info->stream;
1254 const char *sep;
1255
1256 if (amask == MIPS_SVRS_ALL_ARGS)
1257 {
1258 nargs = 4;
1259 nstatics = 0;
1260 }
1261 else if (amask == MIPS_SVRS_ALL_STATICS)
1262 {
1263 nargs = 0;
1264 nstatics = 4;
1265 }
1266 else
1267 {
1268 nargs = amask >> 2;
1269 nstatics = amask & 3;
1270 }
1271
1272 sep = "";
1273 if (nargs > 0)
1274 {
1275 infprintf (is, "%s", mips_gpr_names[4]);
1276 if (nargs > 1)
1277 infprintf (is, "-%s", mips_gpr_names[4 + nargs - 1]);
1278 sep = ",";
1279 }
1280
1281 infprintf (is, "%s%d", sep, frame_size);
1282
1283 if (ra) /* $ra */
1284 infprintf (is, ",%s", mips_gpr_names[31]);
1285
1286 smask = 0;
1287 if (s0) /* $s0 */
1288 smask |= 1 << 0;
1289 if (s1) /* $s1 */
1290 smask |= 1 << 1;
1291 if (nsreg > 0) /* $s2-$s8 */
1292 smask |= ((1 << nsreg) - 1) << 2;
1293
1294 for (i = 0; i < 9; i++)
1295 if (smask & (1 << i))
1296 {
1297 infprintf (is, ",%s", mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1298 /* Skip over string of set bits. */
1299 for (j = i; smask & (2 << j); j++)
1300 continue;
1301 if (j > i)
1302 infprintf (is, "-%s", mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1303 i = j + 1;
1304 }
1305 /* Statics $ax - $a3. */
1306 if (nstatics == 1)
1307 infprintf (is, ",%s", mips_gpr_names[7]);
1308 else if (nstatics > 0)
1309 infprintf (is, ",%s-%s",
1310 mips_gpr_names[7 - nstatics + 1],
1311 mips_gpr_names[7]);
1312}
1313
1314
ab902481
RS		 1315/* Print operand OPERAND of OPCODE, using STATE to track inter-operand state.
1316 UVAL is the encoding of the operand (shifted into bit 0) and BASE_PC is
1317 the base address for OP_PCREL operands. */
fd25c5a9 1318
ab902481
RS		 1319static void
1320print_insn_arg (struct disassemble_info *info,
1321 struct mips_print_arg_state *state,
1322 const struct mips_opcode *opcode,
1323 const struct mips_operand *operand,
1324 bfd_vma base_pc,
1325 unsigned int uval)
1326{
1327 const fprintf_ftype infprintf = info->fprintf_func;
1328 void *is = info->stream;
fd25c5a9 1329
ab902481
RS		 1330 switch (operand->type)
1331 {
1332 case OP_INT:
1333 {
1334 const struct mips_int_operand *int_op;
fd25c5a9 1335
ab902481
RS		 1336 int_op = (const struct mips_int_operand *) operand;
1337 uval = mips_decode_int_operand (int_op, uval);
1338 state->last_int = uval;
1339 if (int_op->print_hex)
1340 infprintf (is, "0x%x", uval);
1341 else
1342 infprintf (is, "%d", uval);
1343 }
1344 break;
fd25c5a9 1345
ab902481
RS		 1346 case OP_MAPPED_INT:
1347 {
1348 const struct mips_mapped_int_operand *mint_op;
fd25c5a9 1349
ab902481
RS		 1350 mint_op = (const struct mips_mapped_int_operand *) operand;
1351 uval = mint_op->int_map[uval];
1352 state->last_int = uval;
1353 if (mint_op->print_hex)
1354 infprintf (is, "0x%x", uval);
1355 else
1356 infprintf (is, "%d", uval);
1357 }
1358 break;
fd25c5a9 1359
ab902481
RS		 1360 case OP_MSB:
1361 {
1362 const struct mips_msb_operand *msb_op;
dec0624d 1363
ab902481
RS		 1364 msb_op = (const struct mips_msb_operand *) operand;
1365 uval += msb_op->bias;
1366 if (msb_op->add_lsb)
1367 uval -= state->last_int;
1368 infprintf (is, "0x%x", uval);
1369 }
1370 break;
dec0624d 1371
ab902481 1372 case OP_REG:
0f35dbc4 1373 case OP_OPTIONAL_REG:
ab902481
RS		 1374 {
1375 const struct mips_reg_operand *reg_op;
fd25c5a9 1376
ab902481 1377 reg_op = (const struct mips_reg_operand *) operand;
fc76e730 1378 uval = mips_decode_reg_operand (reg_op, uval);
ab902481 1379 print_reg (info, opcode, reg_op->reg_type, uval);
fd25c5a9 1380
7361da2c 1381 mips_seen_register (state, uval, reg_op->reg_type);
ab902481
RS		 1382 }
1383 break;
61cc0267 1384
ab902481
RS		 1385 case OP_REG_PAIR:
1386 {
1387 const struct mips_reg_pair_operand *pair_op;
1388
1389 pair_op = (const struct mips_reg_pair_operand *) operand;
1390 print_reg (info, opcode, pair_op->reg_type,
1391 pair_op->reg1_map[uval]);
1392 infprintf (is, ",");
1393 print_reg (info, opcode, pair_op->reg_type,
1394 pair_op->reg2_map[uval]);
1395 }
1396 break;
61cc0267 1397
ab902481
RS		 1398 case OP_PCREL:
1399 {
1400 const struct mips_pcrel_operand *pcrel_op;
61cc0267 1401
ab902481
RS		 1402 pcrel_op = (const struct mips_pcrel_operand *) operand;
1403 info->target = mips_decode_pcrel_operand (pcrel_op, base_pc, uval);
61cc0267 1404
a4ddc54e
MR		 1405 /* For jumps and branches clear the ISA bit except for
1406 the GDB disassembler. */
1407 if (pcrel_op->include_isa_bit
1408 && info->flavour != bfd_target_unknown_flavour)
ab902481 1409 info->target &= -2;
61cc0267 1410
ab902481
RS		 1411 (*info->print_address_func) (info->target, info);
1412 }
1413 break;
794ac9d0 1414
ab902481
RS		 1415 case OP_PERF_REG:
1416 infprintf (is, "%d", uval);
1417 break;
794ac9d0 1418
ab902481
RS		 1419 case OP_ADDIUSP_INT:
1420 {
1421 int sval;
794ac9d0 1422
ab902481
RS		 1423 sval = mips_signed_operand (operand, uval) * 4;
1424 if (sval >= -8 && sval < 8)
1425 sval ^= 0x400;
1426 infprintf (is, "%d", sval);
1427 break;
1428 }
794ac9d0 1429
ab902481
RS		 1430 case OP_CLO_CLZ_DEST:
1431 {
1432 unsigned int reg1, reg2;
1433
1434 reg1 = uval & 31;
1435 reg2 = uval >> 5;
1436 /* If one is zero use the other. */
1437 if (reg1 == reg2 || reg2 == 0)
1438 infprintf (is, "%s", mips_gpr_names[reg1]);
1439 else if (reg1 == 0)
1440 infprintf (is, "%s", mips_gpr_names[reg2]);
1441 else
1442 /* Bogus, result depends on processor. */
1443 infprintf (is, "%s or %s", mips_gpr_names[reg1],
1444 mips_gpr_names[reg2]);
1445 }
1446 break;
794ac9d0 1447
7361da2c
AB		 1448 case OP_SAME_RS_RT:
1449 case OP_CHECK_PREV:
1450 case OP_NON_ZERO_REG:
1451 {
1452 print_reg (info, opcode, OP_REG_GP, uval & 31);
1453 mips_seen_register (state, uval, OP_REG_GP);
1454 }
1455 break;
1456
ab902481
RS		 1457 case OP_LWM_SWM_LIST:
1458 if (operand->size == 2)
1459 {
1460 if (uval == 0)
1461 infprintf (is, "%s,%s",
1462 mips_gpr_names[16],
1463 mips_gpr_names[31]);
1464 else
1465 infprintf (is, "%s-%s,%s",
1466 mips_gpr_names[16],
1467 mips_gpr_names[16 + uval],
1468 mips_gpr_names[31]);
1469 }
1470 else
1471 {
1472 int s_reg_encode;
794ac9d0 1473
ab902481
RS		 1474 s_reg_encode = uval & 0xf;
1475 if (s_reg_encode != 0)
1476 {
1477 if (s_reg_encode == 1)
1478 infprintf (is, "%s", mips_gpr_names[16]);
1479 else if (s_reg_encode < 9)
1480 infprintf (is, "%s-%s",
1481 mips_gpr_names[16],
1482 mips_gpr_names[15 + s_reg_encode]);
1483 else if (s_reg_encode == 9)
1484 infprintf (is, "%s-%s,%s",
1485 mips_gpr_names[16],
1486 mips_gpr_names[23],
1487 mips_gpr_names[30]);
1488 else
1489 infprintf (is, "UNKNOWN");
1490 }
794ac9d0 1491
ab902481
RS		 1492 if (uval & 0x10) /* For ra. */
1493 {
1494 if (s_reg_encode == 0)
1495 infprintf (is, "%s", mips_gpr_names[31]);
1496 else
1497 infprintf (is, ",%s", mips_gpr_names[31]);
1498 }
1499 }
1500 break;
794ac9d0 1501
c3c07478
RS		 1502 case OP_ENTRY_EXIT_LIST:
1503 {
1504 const char *sep;
1505 unsigned int amask, smask;
1506
1507 sep = "";
1508 amask = (uval >> 3) & 7;
1509 if (amask > 0 && amask < 5)
1510 {
1511 infprintf (is, "%s", mips_gpr_names[4]);
1512 if (amask > 1)
1513 infprintf (is, "-%s", mips_gpr_names[amask + 3]);
1514 sep = ",";
1515 }
1516
1517 smask = (uval >> 1) & 3;
1518 if (smask == 3)
1519 {
1520 infprintf (is, "%s??", sep);
1521 sep = ",";
1522 }
1523 else if (smask > 0)
1524 {
1525 infprintf (is, "%s%s", sep, mips_gpr_names[16]);
1526 if (smask > 1)
1527 infprintf (is, "-%s", mips_gpr_names[smask + 15]);
1528 sep = ",";
1529 }
1530
1531 if (uval & 1)
1532 {
1533 infprintf (is, "%s%s", sep, mips_gpr_names[31]);
1534 sep = ",";
1535 }
1536
1537 if (amask == 5 || amask == 6)
1538 {
1539 infprintf (is, "%s%s", sep, mips_fpr_names[0]);
1540 if (amask == 6)
1541 infprintf (is, "-%s", mips_fpr_names[1]);
1542 }
1543 }
1544 break;
1545
1546 case OP_SAVE_RESTORE_LIST:
38bf472a 1547 /* Should be handled by the caller due to complex behavior. */
c3c07478
RS		 1548 abort ();
1549
ab902481
RS		 1550 case OP_MDMX_IMM_REG:
1551 {
1552 unsigned int vsel;
794ac9d0 1553
ab902481
RS		 1554 vsel = uval >> 5;
1555 uval &= 31;
1556 if ((vsel & 0x10) == 0)
794ac9d0 1557 {
ab902481
RS		 1558 int fmt;
1559
1560 vsel &= 0x0f;
1561 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1562 if ((vsel & 1) == 0)
1563 break;
1564 print_reg (info, opcode, OP_REG_VEC, uval);
1565 infprintf (is, "[%d]", vsel >> 1);
794ac9d0 1566 }
ab902481
RS		 1567 else if ((vsel & 0x08) == 0)
1568 print_reg (info, opcode, OP_REG_VEC, uval);
1569 else
1570 infprintf (is, "0x%x", uval);
1571 }
1572 break;
794ac9d0 1573
ab902481
RS		 1574 case OP_REPEAT_PREV_REG:
1575 print_reg (info, opcode, state->last_reg_type, state->last_regno);
1576 break;
794ac9d0 1577
ab902481 1578 case OP_REPEAT_DEST_REG:
7361da2c
AB		 1579 print_reg (info, opcode, state->last_reg_type, state->dest_regno);
1580 break;
794ac9d0 1581
ab902481
RS		 1582 case OP_PC:
1583 infprintf (is, "$pc");
1584 break;
14daeee3 1585
25499ac7
MR		 1586 case OP_REG28:
1587 print_reg (info, opcode, OP_REG_GP, 28);
1588 break;
1589
14daeee3
RS		 1590 case OP_VU0_SUFFIX:
1591 case OP_VU0_MATCH_SUFFIX:
1592 print_vu0_channel (info, operand, uval);
1593 break;
4edbb8e3
CF		 1594
1595 case OP_IMM_INDEX:
1596 infprintf (is, "[%d]", uval);
1597 break;
1598
1599 case OP_REG_INDEX:
1600 infprintf (is, "[");
1601 print_reg (info, opcode, OP_REG_GP, uval);
1602 infprintf (is, "]");
1603 break;
ab902481
RS		 1604 }
1605}
794ac9d0 1606
7361da2c
AB		 1607/* Validate the arguments for INSN, which is described by OPCODE.
1608 Use DECODE_OPERAND to get the encoding of each operand. */
1609
1610static bfd_boolean
1611validate_insn_args (const struct mips_opcode *opcode,
1612 const struct mips_operand *(*decode_operand) (const char *),
1613 unsigned int insn)
1614{
1615 struct mips_print_arg_state state;
1616 const struct mips_operand *operand;
1617 const char *s;
1618 unsigned int uval;
1619
1620 init_print_arg_state (&state);
1621 for (s = opcode->args; *s; ++s)
1622 {
1623 switch (*s)
1624 {
1625 case ',':
1626 case '(':
1627 case ')':
1628 break;
1629
1630 case '#':
1631 ++s;
1632 break;
1633
1634 default:
1635 operand = decode_operand (s);
1636
1637 if (operand)
1638 {
1639 uval = mips_extract_operand (operand, insn);
1640 switch (operand->type)
1641 {
1642 case OP_REG:
1643 case OP_OPTIONAL_REG:
1644 {
1645 const struct mips_reg_operand *reg_op;
1646
1647 reg_op = (const struct mips_reg_operand *) operand;
1648 uval = mips_decode_reg_operand (reg_op, uval);
1649 mips_seen_register (&state, uval, reg_op->reg_type);
1650 }
1651 break;
1652
1653 case OP_SAME_RS_RT:
1654 {
1655 unsigned int reg1, reg2;
1656
1657 reg1 = uval & 31;
1658 reg2 = uval >> 5;
1659
1660 if (reg1 != reg2 || reg1 == 0)
1661 return FALSE;
1662 }
1663 break;
1664
1665 case OP_CHECK_PREV:
1666 {
1667 const struct mips_check_prev_operand *prev_op;
1668
1669 prev_op = (const struct mips_check_prev_operand *) operand;
1670
1671 if (!prev_op->zero_ok && uval == 0)
1672 return FALSE;
1673
1674 if (((prev_op->less_than_ok && uval < state.last_regno)
1675 || (prev_op->greater_than_ok && uval > state.last_regno)
1676 || (prev_op->equal_ok && uval == state.last_regno)))
1677 break;
1678
1679 return FALSE;
1680 }
1681
1682 case OP_NON_ZERO_REG:
1683 {
1684 if (uval == 0)
1685 return FALSE;
1686 }
1687 break;
1688
1689 case OP_INT:
1690 case OP_MAPPED_INT:
1691 case OP_MSB:
1692 case OP_REG_PAIR:
1693 case OP_PCREL:
1694 case OP_PERF_REG:
1695 case OP_ADDIUSP_INT:
1696 case OP_CLO_CLZ_DEST:
1697 case OP_LWM_SWM_LIST:
1698 case OP_ENTRY_EXIT_LIST:
1699 case OP_MDMX_IMM_REG:
1700 case OP_REPEAT_PREV_REG:
1701 case OP_REPEAT_DEST_REG:
1702 case OP_PC:
25499ac7 1703 case OP_REG28:
7361da2c
AB		 1704 case OP_VU0_SUFFIX:
1705 case OP_VU0_MATCH_SUFFIX:
1706 case OP_IMM_INDEX:
1707 case OP_REG_INDEX:
7361da2c 1708 case OP_SAVE_RESTORE_LIST:
38bf472a 1709 break;
7361da2c
AB		 1710 }
1711 }
1712 if (*s == 'm' || *s == '+' || *s == '-')
1713 ++s;
1714 }
1715 }
1716 return TRUE;
1717}
1718
ab902481
RS		 1719/* Print the arguments for INSN, which is described by OPCODE.
1720 Use DECODE_OPERAND to get the encoding of each operand. Use BASE_PC
7361da2c
AB		 1721 as the base of OP_PCREL operands, adjusting by LENGTH if the OP_PCREL
1722 operand is for a branch or jump. */
af7ee8bf 1723
ab902481
RS		 1724static void
1725print_insn_args (struct disassemble_info *info,
1726 const struct mips_opcode *opcode,
1727 const struct mips_operand *(*decode_operand) (const char *),
7361da2c 1728 unsigned int insn, bfd_vma insn_pc, unsigned int length)
ab902481
RS		 1729{
1730 const fprintf_ftype infprintf = info->fprintf_func;
1731 void *is = info->stream;
1732 struct mips_print_arg_state state;
1733 const struct mips_operand *operand;
1734 const char *s;
794ac9d0 1735
ab902481
RS		 1736 init_print_arg_state (&state);
1737 for (s = opcode->args; *s; ++s)
1738 {
1739 switch (*s)
1740 {
1741 case ',':
1742 case '(':
1743 case ')':
1744 infprintf (is, "%c", *s);
794ac9d0
CD		 1745 break;
1746
14daeee3
RS		 1747 case '#':
1748 ++s;
1749 infprintf (is, "%c%c", *s, *s);
1750 break;
1751
ab902481
RS		 1752 default:
1753 operand = decode_operand (s);
1754 if (!operand)
fa7616a4 1755 {
ab902481
RS		 1756 /* xgettext:c-format */
1757 infprintf (is,
1758 _("# internal error, undefined operand in `%s %s'"),
1759 opcode->name, opcode->args);
1760 return;
1761 }
38bf472a
MR		 1762
1763 if (operand->type == OP_SAVE_RESTORE_LIST)
1764 {
1765 /* Handle this case here because of the complex behavior. */
1766 unsigned int amask = (insn >> 15) & 0xf;
1767 unsigned int nsreg = (insn >> 23) & 0x7;
1768 unsigned int ra = insn & 0x1000; /* $ra */
1769 unsigned int s0 = insn & 0x800; /* $s0 */
1770 unsigned int s1 = insn & 0x400; /* $s1 */
1771 unsigned int frame_size = (((insn >> 15) & 0xf0)
1772 | ((insn >> 6) & 0x0f)) * 8;
1773 mips_print_save_restore (info, amask, nsreg, ra, s0, s1,
1774 frame_size);
1775 }
1776 else if (operand->type == OP_REG
1777 && s[1] == ','
1778 && s[2] == 'H'
1779 && opcode->name[strlen (opcode->name) - 1] == '0')
ab902481 1780 {
fdfb4752 1781 /* Coprocessor register 0 with sel field. */
ab902481
RS		 1782 const struct mips_cp0sel_name *n;
1783 unsigned int reg, sel;
1784
1785 reg = mips_extract_operand (operand, insn);
1786 s += 2;
1787 operand = decode_operand (s);
1788 sel = mips_extract_operand (operand, insn);
1789
1790 /* CP0 register including 'sel' code for mftc0, to be
1791 printed textually if known. If not known, print both
1792 CP0 register name and sel numerically since CP0 register
1793 with sel 0 may have a name unrelated to register being
1794 printed. */
1795 n = lookup_mips_cp0sel_name (mips_cp0sel_names,
1796 mips_cp0sel_names_len,
1797 reg, sel);
1798 if (n != NULL)
1799 infprintf (is, "%s", n->name);
fa7616a4 1800 else
ab902481 1801 infprintf (is, "$%d,%d", reg, sel);
fa7616a4 1802 }
794ac9d0 1803 else
7361da2c
AB		 1804 {
1805 bfd_vma base_pc = insn_pc;
1806
1807 /* Adjust the PC relative base so that branch/jump insns use
1808 the following PC as the base but genuinely PC relative
1809 operands use the current PC. */
1810 if (operand->type == OP_PCREL)
1811 {
1812 const struct mips_pcrel_operand *pcrel_op;
1813
1814 pcrel_op = (const struct mips_pcrel_operand *) operand;
1815 /* The include_isa_bit flag is sufficient to distinguish
1816 branch/jump from other PC relative operands. */
1817 if (pcrel_op->include_isa_bit)
1818 base_pc += length;
1819 }
1820
1821 print_insn_arg (info, &state, opcode, operand, base_pc,
1822 mips_extract_operand (operand, insn));
1823 }
1824 if (*s == 'm' || *s == '+' || *s == '-')
ab902481 1825 ++s;
794ac9d0 1826 break;
af7ee8bf 1827 }
252b5132
RH		 1828 }
1829}
1830\f
252b5132
RH		 1831/* Print the mips instruction at address MEMADDR in debugged memory,
1832 on using INFO. Returns length of the instruction, in bytes, which is
aa5f19f2 1833 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
252b5132
RH		 1834 this is little-endian code. */
1835
1836static int
47b0e7ad 1837print_insn_mips (bfd_vma memaddr,
fc8c4fd1 1838 int word,
47b0e7ad 1839 struct disassemble_info *info)
252b5132 1840{
ab902481
RS		 1841#define GET_OP(insn, field) \
1842 (((insn) >> OP_SH_##field) & OP_MASK_##field)
fc8c4fd1
MR		 1843 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1844 const fprintf_ftype infprintf = info->fprintf_func;
47b0e7ad 1845 const struct mips_opcode *op;
b34976b6 1846 static bfd_boolean init = 0;
fc8c4fd1 1847 void *is = info->stream;
252b5132
RH		 1848
1849 /* Build a hash table to shorten the search time. */
1850 if (! init)
1851 {
1852 unsigned int i;
1853
1854 for (i = 0; i <= OP_MASK_OP; i++)
1855 {
1856 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1857 {
986e18a5 1858 if (op->pinfo == INSN_MACRO
9e836e3d 1859 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
252b5132 1860 continue;
fc8c4fd1 1861 if (i == GET_OP (op->match, OP))
252b5132
RH		 1862 {
1863 mips_hash[i] = op;
1864 break;
1865 }
1866 }
7f6621cd 1867 }
252b5132
RH		 1868
1869 init = 1;
1870 }
1871
aa5f19f2 1872 info->bytes_per_chunk = INSNLEN;
252b5132 1873 info->display_endian = info->endian;
9bb28706
CD		 1874 info->insn_info_valid = 1;
1875 info->branch_delay_insns = 0;
def7143b 1876 info->data_size = 0;
9bb28706
CD		 1877 info->insn_type = dis_nonbranch;
1878 info->target = 0;
1879 info->target2 = 0;
252b5132 1880
fc8c4fd1 1881 op = mips_hash[GET_OP (word, OP)];
252b5132
RH		 1882 if (op != NULL)
1883 {
1884 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1885 {
43e65147 1886 if (op->pinfo != INSN_MACRO
9e836e3d 1887 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
986e18a5 1888 && (word & op->mask) == op->match)
252b5132 1889 {
7361da2c 1890 /* We always disassemble the jalx instruction, except for MIPS r6. */
d301a56b 1891 if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor)
7361da2c
AB		 1892 && (strcmp (op->name, "jalx")
1893 || (mips_isa & INSN_ISA_MASK) == ISA_MIPS32R6
1894 || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R6))
252b5132
RH		 1895 continue;
1896
9bb28706
CD		 1897 /* Figure out instruction type and branch delay information. */
1898 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1899 {
fc76e730 1900 if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_1)) != 0)
9bb28706
CD		 1901 info->insn_type = dis_jsr;
1902 else
1903 info->insn_type = dis_branch;
1904 info->branch_delay_insns = 1;
1905 }
1906 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1907 | INSN_COND_BRANCH_LIKELY)) != 0)
1908 {
c680e7f6 1909 if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
9bb28706
CD		 1910 info->insn_type = dis_condjsr;
1911 else
1912 info->insn_type = dis_condbranch;
1913 info->branch_delay_insns = 1;
1914 }
1915 else if ((op->pinfo & (INSN_STORE_MEMORY
67dc82bc 1916 | INSN_LOAD_MEMORY)) != 0)
9bb28706
CD		 1917 info->insn_type = dis_dref;
1918
7361da2c
AB		 1919 if (!validate_insn_args (op, decode_mips_operand, word))
1920 continue;
1921
fc8c4fd1 1922 infprintf (is, "%s", op->name);
14daeee3
RS		 1923 if (op->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
1924 {
1925 unsigned int uval;
1926
1927 infprintf (is, ".");
1928 uval = mips_extract_operand (&mips_vu0_channel_mask, word);
1929 print_vu0_channel (info, &mips_vu0_channel_mask, uval);
1930 }
252b5132 1931
ab902481 1932 if (op->args[0])
252b5132 1933 {
fc8c4fd1 1934 infprintf (is, "\t");
ab902481 1935 print_insn_args (info, op, decode_mips_operand, word,
7361da2c 1936 memaddr, 4);
252b5132
RH		 1937 }
1938
aa5f19f2 1939 return INSNLEN;
252b5132
RH		 1940 }
1941 }
1942 }
fc8c4fd1 1943#undef GET_OP
252b5132
RH		 1944
1945 /* Handle undefined instructions. */
9bb28706 1946 info->insn_type = dis_noninsn;
fc8c4fd1 1947 infprintf (is, "0x%x", word);
aa5f19f2 1948 return INSNLEN;
252b5132 1949}
aa5f19f2 1950\f
252b5132
RH		 1951/* Disassemble an operand for a mips16 instruction. */
1952
1953static void
c3c07478
RS		 1954print_mips16_insn_arg (struct disassemble_info *info,
1955 struct mips_print_arg_state *state,
1956 const struct mips_opcode *opcode,
1957 char type, bfd_vma memaddr,
1958 unsigned insn, bfd_boolean use_extend,
1959 unsigned extend, bfd_boolean is_offset)
252b5132 1960{
fc8c4fd1
MR		 1961 const fprintf_ftype infprintf = info->fprintf_func;
1962 void *is = info->stream;
c3c07478 1963 const struct mips_operand *operand, *ext_operand;
bdd15286 1964 unsigned short ext_size;
c3c07478
RS		 1965 unsigned int uval;
1966 bfd_vma baseaddr;
1967
1968 if (!use_extend)
1969 extend = 0;
fc8c4fd1 1970
252b5132
RH		 1971 switch (type)
1972 {
1973 case ',':
1974 case '(':
1975 case ')':
fc8c4fd1 1976 infprintf (is, "%c", type);
252b5132
RH		 1977 break;
1978
c3c07478
RS		 1979 default:
1980 operand = decode_mips16_operand (type, FALSE);
1981 if (!operand)
1982 {
1983 /* xgettext:c-format */
1984 infprintf (is, _("# internal error, undefined operand in `%s %s'"),
1985 opcode->name, opcode->args);
1986 return;
1987 }
252b5132 1988
c3c07478
RS		 1989 if (operand->type == OP_SAVE_RESTORE_LIST)
1990 {
5f5c6e03 1991 /* Handle this case here because of the complex interaction
c3c07478 1992 with the EXTEND opcode. */
38bf472a
MR		 1993 unsigned int amask = extend & 0xf;
1994 unsigned int nsreg = (extend >> 8) & 0x7;
1995 unsigned int ra = insn & 0x40; /* $ra */
1996 unsigned int s0 = insn & 0x20; /* $s0 */
1997 unsigned int s1 = insn & 0x10; /* $s1 */
1998 unsigned int frame_size = ((extend & 0xf0) | (insn & 0x0f)) * 8;
c3c07478
RS		 1999 if (frame_size == 0 && !use_extend)
2000 frame_size = 128;
38bf472a 2001 mips_print_save_restore (info, amask, nsreg, ra, s0, s1, frame_size);
c3c07478
RS		 2002 break;
2003 }
252b5132 2004
c3c07478
RS		 2005 if (is_offset && operand->type == OP_INT)
2006 {
2007 const struct mips_int_operand *int_op;
252b5132 2008
c3c07478
RS		 2009 int_op = (const struct mips_int_operand *) operand;
2010 info->insn_type = dis_dref;
2011 info->data_size = 1 << int_op->shift;
2012 }
252b5132 2013
bdd15286
MR		 2014 ext_size = 0;
2015 if (use_extend)
c3c07478 2016 {
bdd15286 2017 ext_operand = decode_mips16_operand (type, TRUE);
25499ac7
MR		 2018 if (ext_operand != operand
2019 || (operand->type == OP_INT && operand->lsb == 0
2020 && mips_opcode_32bit_p (opcode)))
c3c07478 2021 {
bdd15286
MR		 2022 ext_size = ext_operand->size;
2023 operand = ext_operand;
c3c07478
RS		 2024 }
2025 }
bdd15286
MR		 2026 if (operand->size == 26)
2027 uval = ((extend & 0x1f) << 21) | ((extend & 0x3e0) << 11) | insn;
25499ac7 2028 else if (ext_size == 16 || ext_size == 9)
bdd15286
MR		 2029 uval = ((extend & 0x1f) << 11) | (extend & 0x7e0) | (insn & 0x1f);
2030 else if (ext_size == 15)
2031 uval = ((extend & 0xf) << 11) | (extend & 0x7f0) | (insn & 0xf);
2032 else if (ext_size == 6)
2033 uval = ((extend >> 6) & 0x1f) | (extend & 0x20);
2034 else
2035 uval = mips_extract_operand (operand, (extend << 16) | insn);
25499ac7
MR		 2036 if (ext_size == 9)
2037 uval &= (1U << ext_size) - 1;
c3c07478
RS		 2038
2039 baseaddr = memaddr + 2;
2040 if (operand->type == OP_PCREL)
2041 {
2042 const struct mips_pcrel_operand *pcrel_op;
2043
2044 pcrel_op = (const struct mips_pcrel_operand *) operand;
2045 if (!pcrel_op->include_isa_bit && use_extend)
2046 baseaddr = memaddr - 2;
2047 else if (!pcrel_op->include_isa_bit)
39f66f3a
MR		 2048 {
2049 bfd_byte buffer[2];
2050
2051 /* If this instruction is in the delay slot of a JAL/JALX
2052 instruction, the base address is the address of the
2053 JAL/JALX instruction. If it is in the delay slot of
2054 a JR/JALR instruction, the base address is the address
2055 of the JR/JALR instruction. This test is unreliable:
2056 we have no way of knowing whether the previous word is
2057 instruction or data. */
2058 if (info->read_memory_func (memaddr - 4, buffer, 2, info) == 0
2059 && (((info->endian == BFD_ENDIAN_BIG
2060 ? bfd_getb16 (buffer)
2061 : bfd_getl16 (buffer))
2062 & 0xf800) == 0x1800))
2063 baseaddr = memaddr - 4;
2064 else if (info->read_memory_func (memaddr - 2, buffer, 2,
2065 info) == 0
2066 && (((info->endian == BFD_ENDIAN_BIG
2067 ? bfd_getb16 (buffer)
2068 : bfd_getl16 (buffer))
2069 & 0xf89f) == 0xe800)
2070 && (((info->endian == BFD_ENDIAN_BIG
2071 ? bfd_getb16 (buffer)
2072 : bfd_getl16 (buffer))
2073 & 0x0060) != 0x0060))
2074 baseaddr = memaddr - 2;
2075 else
2076 baseaddr = memaddr;
2077 }
c3c07478 2078 }
0499d65b 2079
6d075bce 2080 print_insn_arg (info, state, opcode, operand, baseaddr + 1, uval);
0499d65b 2081 break;
252b5132
RH		 2082 }
2083}
640c0ccd 2084
1bbce132
MR		 2085
2086/* Check if the given address is the last word of a MIPS16 PLT entry.
2087 This word is data and depending on the value it may interfere with
2088 disassembly of further PLT entries. We make use of the fact PLT
2089 symbols are marked BSF_SYNTHETIC. */
2090static bfd_boolean
2091is_mips16_plt_tail (struct disassemble_info *info, bfd_vma addr)
2092{
2093 if (info->symbols
2094 && info->symbols[0]
2095 && (info->symbols[0]->flags & BSF_SYNTHETIC)
2096 && addr == bfd_asymbol_value (info->symbols[0]) + 12)
2097 return TRUE;
2098
2099 return FALSE;
2100}
2101
7fd53920
MR		 2102/* Whether none, a 32-bit or a 16-bit instruction match has been done. */
2103
2104enum match_kind
2105{
2106 MATCH_NONE,
2107 MATCH_FULL,
2108 MATCH_SHORT
2109};
2110
47b0e7ad
NC		 2111/* Disassemble mips16 instructions. */
2112
2113static int
2114print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
2115{
fc8c4fd1 2116 const fprintf_ftype infprintf = info->fprintf_func;
47b0e7ad 2117 int status;
1bbce132 2118 bfd_byte buffer[4];
47b0e7ad 2119 const struct mips_opcode *op, *opend;
c3c07478 2120 struct mips_print_arg_state state;
fc8c4fd1 2121 void *is = info->stream;
7fd53920 2122 bfd_boolean have_second;
25499ac7 2123 bfd_boolean extend_only;
7fd53920
MR		 2124 unsigned int second;
2125 unsigned int first;
2126 unsigned int full;
47b0e7ad
NC		 2127
2128 info->bytes_per_chunk = 2;
2129 info->display_endian = info->endian;
2130 info->insn_info_valid = 1;
2131 info->branch_delay_insns = 0;
2132 info->data_size = 0;
47b0e7ad
NC		 2133 info->target = 0;
2134 info->target2 = 0;
2135
c3c07478
RS		 2136#define GET_OP(insn, field) \
2137 (((insn) >> MIPS16OP_SH_##field) & MIPS16OP_MASK_##field)
1bbce132
MR		 2138 /* Decode PLT entry's GOT slot address word. */
2139 if (is_mips16_plt_tail (info, memaddr))
2140 {
2141 info->insn_type = dis_noninsn;
2142 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
2143 if (status == 0)
2144 {
2145 unsigned int gotslot;
2146
2147 if (info->endian == BFD_ENDIAN_BIG)
2148 gotslot = bfd_getb32 (buffer);
2149 else
2150 gotslot = bfd_getl32 (buffer);
2151 infprintf (is, ".word\t0x%x", gotslot);
2152
2153 return 4;
2154 }
2155 }
2156 else
2157 {
2158 info->insn_type = dis_nonbranch;
2159 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
2160 }
47b0e7ad
NC		 2161 if (status != 0)
2162 {
2163 (*info->memory_error_func) (status, memaddr, info);
2164 return -1;
2165 }
2166
25499ac7
MR		 2167 extend_only = FALSE;
2168
47b0e7ad 2169 if (info->endian == BFD_ENDIAN_BIG)
7fd53920 2170 first = bfd_getb16 (buffer);
47b0e7ad 2171 else
7fd53920 2172 first = bfd_getl16 (buffer);
47b0e7ad 2173
7fd53920
MR		 2174 status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
2175 if (status == 0)
47b0e7ad 2176 {
7fd53920 2177 have_second = TRUE;
47b0e7ad 2178 if (info->endian == BFD_ENDIAN_BIG)
7fd53920 2179 second = bfd_getb16 (buffer);
47b0e7ad 2180 else
7fd53920
MR		 2181 second = bfd_getl16 (buffer);
2182 full = (first << 16) | second;
2183 }
2184 else
2185 {
2186 have_second = FALSE;
2187 second = 0;
2188 full = first;
47b0e7ad
NC		 2189 }
2190
2191 /* FIXME: Should probably use a hash table on the major opcode here. */
2192
2193 opend = mips16_opcodes + bfd_mips16_num_opcodes;
2194 for (op = mips16_opcodes; op < opend; op++)
2195 {
7fd53920 2196 enum match_kind match;
47b0e7ad 2197
11dd08e9
MR		 2198 if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor))
2199 continue;
2200
7fd53920
MR		 2201 if (op->pinfo == INSN_MACRO
2202 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
2203 match = MATCH_NONE;
2204 else if (mips_opcode_32bit_p (op))
2205 {
2206 if (have_second
2207 && (full & op->mask) == op->match)
2208 match = MATCH_FULL;
2209 else
2210 match = MATCH_NONE;
2211 }
2212 else if ((first & op->mask) == op->match)
2213 {
2214 match = MATCH_SHORT;
2215 second = 0;
2216 full = first;
2217 }
2218 else if ((first & 0xf800) == 0xf000
2219 && have_second
25499ac7 2220 && !extend_only
7fd53920 2221 && (second & op->mask) == op->match)
25499ac7
MR		 2222 {
2223 if (op->pinfo2 & INSN2_SHORT_ONLY)
2224 {
2225 match = MATCH_NONE;
2226 extend_only = TRUE;
2227 }
2228 else
2229 match = MATCH_FULL;
2230 }
7fd53920
MR		 2231 else
2232 match = MATCH_NONE;
47b0e7ad 2233
7fd53920
MR		 2234 if (match != MATCH_NONE)
2235 {
2236 const char *s;
47b0e7ad 2237
fc8c4fd1 2238 infprintf (is, "%s", op->name);
47b0e7ad 2239 if (op->args[0] != '\0')
fc8c4fd1 2240 infprintf (is, "\t");
47b0e7ad 2241
c3c07478 2242 init_print_arg_state (&state);
47b0e7ad
NC		 2243 for (s = op->args; *s != '\0'; s++)
2244 {
2245 if (*s == ','
2246 && s[1] == 'w'
7fd53920 2247 && GET_OP (full, RX) == GET_OP (full, RY))
47b0e7ad
NC		 2248 {
2249 /* Skip the register and the comma. */
2250 ++s;
2251 continue;
2252 }
2253 if (*s == ','
2254 && s[1] == 'v'
7fd53920 2255 && GET_OP (full, RZ) == GET_OP (full, RX))
47b0e7ad
NC		 2256 {
2257 /* Skip the register and the comma. */
2258 ++s;
2259 continue;
2260 }
25499ac7
MR		 2261 if (s[0] == 'N'
2262 && s[1] == ','
2263 && s[2] == 'O'
2264 && op->name[strlen (op->name) - 1] == '0')
7fd53920 2265 {
25499ac7
MR		 2266 /* Coprocessor register 0 with sel field. */
2267 const struct mips_cp0sel_name *n;
2268 const struct mips_operand *operand;
2269 unsigned int reg, sel;
2270
2271 operand = decode_mips16_operand (*s, TRUE);
2272 reg = mips_extract_operand (operand, (first << 16) | second);
2273 s += 2;
2274 operand = decode_mips16_operand (*s, TRUE);
2275 sel = mips_extract_operand (operand, (first << 16) | second);
2276
2277 /* CP0 register including 'sel' code for mftc0, to be
2278 printed textually if known. If not known, print both
2279 CP0 register name and sel numerically since CP0 register
2280 with sel 0 may have a name unrelated to register being
2281 printed. */
2282 n = lookup_mips_cp0sel_name (mips_cp0sel_names,
2283 mips_cp0sel_names_len,
2284 reg, sel);
2285 if (n != NULL)
2286 infprintf (is, "%s", n->name);
2287 else
2288 infprintf (is, "$%d,%d", reg, sel);
7fd53920 2289 }
25499ac7
MR		 2290 else
2291 switch (match)
2292 {
2293 case MATCH_FULL:
2294 print_mips16_insn_arg (info, &state, op, *s, memaddr + 2,
2295 second, TRUE, first, s[1] == '(');
2296 break;
2297 case MATCH_SHORT:
2298 print_mips16_insn_arg (info, &state, op, *s, memaddr,
2299 first, FALSE, 0, s[1] == '(');
2300 break;
2301 case MATCH_NONE: /* Stop the compiler complaining. */
2302 break;
2303 }
47b0e7ad
NC		 2304 }
2305
9a2c7088 2306 /* Figure out branch instruction type and delay slot information. */
47b0e7ad 2307 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
9a2c7088 2308 info->branch_delay_insns = 1;
26545944
RS		 2309 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
2310 || (op->pinfo2 & INSN2_UNCOND_BRANCH) != 0)
47b0e7ad 2311 {
9a2c7088
MR		 2312 if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
2313 info->insn_type = dis_jsr;
2314 else
47b0e7ad
NC		 2315 info->insn_type = dis_branch;
2316 }
26545944 2317 else if ((op->pinfo2 & INSN2_COND_BRANCH) != 0)
9a2c7088 2318 info->insn_type = dis_condbranch;
47b0e7ad 2319
7fd53920 2320 return match == MATCH_FULL ? 4 : 2;
47b0e7ad
NC		 2321 }
2322 }
fc8c4fd1 2323#undef GET_OP
47b0e7ad 2324
7fd53920 2325 infprintf (is, "0x%x", first);
47b0e7ad
NC		 2326 info->insn_type = dis_noninsn;
2327
7fd53920 2328 return 2;
47b0e7ad
NC		 2329}
2330
df58fc94
RS		 2331/* Disassemble microMIPS instructions. */
2332
2333static int
2334print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
2335{
0c7533d3 2336 const fprintf_ftype infprintf = info->fprintf_func;
df58fc94 2337 const struct mips_opcode *op, *opend;
df58fc94 2338 void *is = info->stream;
df58fc94 2339 bfd_byte buffer[2];
ab902481
RS		 2340 unsigned int higher;
2341 unsigned int length;
df58fc94 2342 int status;
ab902481 2343 unsigned int insn;
df58fc94
RS		 2344
2345 info->bytes_per_chunk = 2;
2346 info->display_endian = info->endian;
2347 info->insn_info_valid = 1;
2348 info->branch_delay_insns = 0;
2349 info->data_size = 0;
2350 info->insn_type = dis_nonbranch;
2351 info->target = 0;
2352 info->target2 = 0;
2353
2354 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
2355 if (status != 0)
2356 {
2357 (*info->memory_error_func) (status, memaddr, info);
2358 return -1;
2359 }
2360
2361 length = 2;
2362
2363 if (info->endian == BFD_ENDIAN_BIG)
2364 insn = bfd_getb16 (buffer);
2365 else
2366 insn = bfd_getl16 (buffer);
2367
100b4f2e 2368 if ((insn & 0x1c00) == 0x0000 || (insn & 0x1000) == 0x1000)
df58fc94
RS		 2369 {
2370 /* This is a 32-bit microMIPS instruction. */
2371 higher = insn;
2372
2373 status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
2374 if (status != 0)
2375 {
0c7533d3 2376 infprintf (is, "micromips 0x%x", higher);
df58fc94
RS		 2377 (*info->memory_error_func) (status, memaddr + 2, info);
2378 return -1;
2379 }
2380
2381 if (info->endian == BFD_ENDIAN_BIG)
2382 insn = bfd_getb16 (buffer);
2383 else
2384 insn = bfd_getl16 (buffer);
2385
2386 insn = insn | (higher << 16);
2387
2388 length += 2;
2389 }
2390
2391 /* FIXME: Should probably use a hash table on the major opcode here. */
2392
df58fc94
RS		 2393 opend = micromips_opcodes + bfd_micromips_num_opcodes;
2394 for (op = micromips_opcodes; op < opend; op++)
2395 {
2396 if (op->pinfo != INSN_MACRO
2397 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
2398 && (insn & op->mask) == op->match
2399 && ((length == 2 && (op->mask & 0xffff0000) == 0)
2400 || (length == 4 && (op->mask & 0xffff0000) != 0)))
2401 {
7361da2c
AB		 2402 if (!validate_insn_args (op, decode_micromips_operand, insn))
2403 continue;
2404
0c7533d3 2405 infprintf (is, "%s", op->name);
df58fc94 2406
ab902481 2407 if (op->args[0])
df58fc94 2408 {
ab902481
RS		 2409 infprintf (is, "\t");
2410 print_insn_args (info, op, decode_micromips_operand, insn,
7361da2c 2411 memaddr + 1, length);
df58fc94
RS		 2412 }
2413
2414 /* Figure out instruction type and branch delay information. */
2415 if ((op->pinfo
2416 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY)) != 0)
2417 info->branch_delay_insns = 1;
2418 if (((op->pinfo & INSN_UNCOND_BRANCH_DELAY)
2419 | (op->pinfo2 & INSN2_UNCOND_BRANCH)) != 0)
2420 {
fc76e730 2421 if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_1)) != 0)
df58fc94
RS		 2422 info->insn_type = dis_jsr;
2423 else
2424 info->insn_type = dis_branch;
2425 }
2426 else if (((op->pinfo & INSN_COND_BRANCH_DELAY)
2427 | (op->pinfo2 & INSN2_COND_BRANCH)) != 0)
2428 {
2429 if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
2430 info->insn_type = dis_condjsr;
2431 else
2432 info->insn_type = dis_condbranch;
2433 }
2434 else if ((op->pinfo
67dc82bc 2435 & (INSN_STORE_MEMORY | INSN_LOAD_MEMORY)) != 0)
df58fc94
RS		 2436 info->insn_type = dis_dref;
2437
2438 return length;
2439 }
2440 }
df58fc94 2441
0c7533d3 2442 infprintf (is, "0x%x", insn);
df58fc94
RS		 2443 info->insn_type = dis_noninsn;
2444
2445 return length;
2446}
2447
2448/* Return 1 if a symbol associated with the location being disassembled
1401d2fe
MR		 2449 indicates a compressed mode, either MIPS16 or microMIPS, according to
2450 MICROMIPS_P. We iterate over all the symbols at the address being
2451 considered assuming if at least one of them indicates code compression,
2452 then such code has been genuinely produced here (other symbols could
2453 have been derived from function symbols defined elsewhere or could
2454 define data). Otherwise, return 0. */
df58fc94
RS		 2455
2456static bfd_boolean
1401d2fe 2457is_compressed_mode_p (struct disassemble_info *info, bfd_boolean micromips_p)
df58fc94 2458{
df58fc94 2459 int i;
1bbce132
MR		 2460 int l;
2461
2462 for (i = info->symtab_pos, l = i + info->num_symbols; i < l; i++)
2463 if (((info->symtab[i])->flags & BSF_SYNTHETIC) != 0
1401d2fe 2464 && ((!micromips_p
1bbce132 2465 && ELF_ST_IS_MIPS16 ((*info->symbols)->udata.i))
1401d2fe 2466 || (micromips_p
1bbce132
MR		 2467 && ELF_ST_IS_MICROMIPS ((*info->symbols)->udata.i))))
2468 return 1;
2469 else if (bfd_asymbol_flavour (info->symtab[i]) == bfd_target_elf_flavour
2470 && info->symtab[i]->section == info->section)
2471 {
2472 elf_symbol_type *symbol = (elf_symbol_type *) info->symtab[i];
1401d2fe 2473 if ((!micromips_p
1bbce132 2474 && ELF_ST_IS_MIPS16 (symbol->internal_elf_sym.st_other))
1401d2fe 2475 || (micromips_p
1bbce132
MR		 2476 && ELF_ST_IS_MICROMIPS (symbol->internal_elf_sym.st_other)))
2477 return 1;
2478 }
df58fc94
RS		 2479
2480 return 0;
2481}
2482
47b0e7ad
NC		 2483/* In an environment where we do not know the symbol type of the
2484 instruction we are forced to assume that the low order bit of the
2485 instructions' address may mark it as a mips16 instruction. If we
2486 are single stepping, or the pc is within the disassembled function,
2487 this works. Otherwise, we need a clue. Sometimes. */
2488
2489static int
2490_print_insn_mips (bfd_vma memaddr,
2491 struct disassemble_info *info,
2492 enum bfd_endian endianness)
2493{
2494 bfd_byte buffer[INSNLEN];
2495 int status;
2496
2497 set_default_mips_dis_options (info);
2498 parse_mips_dis_options (info->disassembler_options);
2499
df58fc94
RS		 2500 if (info->mach == bfd_mach_mips16)
2501 return print_insn_mips16 (memaddr, info);
2502 if (info->mach == bfd_mach_mips_micromips)
2503 return print_insn_micromips (memaddr, info);
2504
47b0e7ad 2505#if 1
df58fc94 2506 /* FIXME: If odd address, this is CLEARLY a compressed instruction. */
47b0e7ad
NC		 2507 /* Only a few tools will work this way. */
2508 if (memaddr & 0x01)
1401d2fe
MR		 2509 {
2510 if (micromips_ase)
2511 return print_insn_micromips (memaddr, info);
2512 else
2513 return print_insn_mips16 (memaddr, info);
2514 }
47b0e7ad
NC		 2515#endif
2516
2517#if SYMTAB_AVAILABLE
1401d2fe
MR		 2518 if (is_compressed_mode_p (info, TRUE))
2519 return print_insn_micromips (memaddr, info);
2520 if (is_compressed_mode_p (info, FALSE))
2521 return print_insn_mips16 (memaddr, info);
47b0e7ad
NC		 2522#endif
2523
2524 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
2525 if (status == 0)
2526 {
fc8c4fd1 2527 int insn;
47b0e7ad
NC		 2528
2529 if (endianness == BFD_ENDIAN_BIG)
fc8c4fd1 2530 insn = bfd_getb32 (buffer);
47b0e7ad 2531 else
fc8c4fd1 2532 insn = bfd_getl32 (buffer);
47b0e7ad
NC		 2533
2534 return print_insn_mips (memaddr, insn, info);
2535 }
2536 else
2537 {
2538 (*info->memory_error_func) (status, memaddr, info);
2539 return -1;
2540 }
2541}
2542
2543int
2544print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
2545{
2546 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
2547}
2548
2549int
2550print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
2551{
2552 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
2553}
2554\f
640c0ccd 2555void
47b0e7ad 2556print_mips_disassembler_options (FILE *stream)
640c0ccd 2557{
4a9a3c54 2558 unsigned int i;
640c0ccd
CD		 2559
2560 fprintf (stream, _("\n\
2561The following MIPS specific disassembler options are supported for use\n\
2562with the -M switch (multiple options should be separated by commas):\n"));
2563
0348fd79
MR		 2564 fprintf (stream, _("\n\
2565 no-aliases Use canonical instruction forms.\n"));
2566
4edbb8e3 2567 fprintf (stream, _("\n\
6725647c 2568 msa Recognize MSA instructions.\n"));
4edbb8e3 2569
b015e599 2570 fprintf (stream, _("\n\
6725647c 2571 virt Recognize the virtualization ASE instructions.\n"));
b015e599 2572
7d64c587 2573 fprintf (stream, _("\n\
6725647c
MR		 2574 xpa Recognize the eXtended Physical Address (XPA)\n\
2575 ASE instructions.\n"));
7d64c587 2576
6f20c942 2577 fprintf (stream, _("\n\
385e4d0f 2578 ginv Recognize the Global INValidate (GINV) ASE\n\
6f20c942
FS		 2579 instructions.\n"));
2580
640c0ccd 2581 fprintf (stream, _("\n\
6725647c 2582 gpr-names=ABI Print GPR names according to specified ABI.\n\
640c0ccd
CD		 2583 Default: based on binary being disassembled.\n"));
2584
2585 fprintf (stream, _("\n\
2586 fpr-names=ABI Print FPR names according to specified ABI.\n\
2587 Default: numeric.\n"));
2588
2589 fprintf (stream, _("\n\
2590 cp0-names=ARCH Print CP0 register names according to\n\
2591 specified architecture.\n\
2592 Default: based on binary being disassembled.\n"));
2593
af7ee8bf
CD		 2594 fprintf (stream, _("\n\
2595 hwr-names=ARCH Print HWR names according to specified \n\
6725647c 2596 architecture.\n\
af7ee8bf
CD		 2597 Default: based on binary being disassembled.\n"));
2598
640c0ccd
CD		 2599 fprintf (stream, _("\n\
2600 reg-names=ABI Print GPR and FPR names according to\n\
2601 specified ABI.\n"));
2602
2603 fprintf (stream, _("\n\
af7ee8bf 2604 reg-names=ARCH Print CP0 register and HWR names according to\n\
640c0ccd
CD		 2605 specified architecture.\n"));
2606
2607 fprintf (stream, _("\n\
2608 For the options above, the following values are supported for \"ABI\":\n\
2609 "));
4a9a3c54 2610 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
640c0ccd
CD		 2611 fprintf (stream, " %s", mips_abi_choices[i].name);
2612 fprintf (stream, _("\n"));
2613
2614 fprintf (stream, _("\n\
2615 For the options above, The following values are supported for \"ARCH\":\n\
2616 "));
4a9a3c54 2617 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
640c0ccd
CD		 2618 if (*mips_arch_choices[i].name != '\0')
2619 fprintf (stream, " %s", mips_arch_choices[i].name);
2620 fprintf (stream, _("\n"));
2621
2622 fprintf (stream, _("\n"));
2623}
GDB Binutils - Deliverables
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