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[deliverable/binutils-gdb.git] / opcodes / mips16-opc.c
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252b5132 1/* mips16-opc.c. Mips16 opcode table.
df7b86aa 2 Copyright 1996, 1997, 1998, 2000, 2005, 2006, 2007, 2012
aa820537 3 Free Software Foundation, Inc.
252b5132
RH		 4 Contributed by Ian Lance Taylor, Cygnus Support
5
9b201bb5 6 This file is part of the GNU opcodes library.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
9b201bb5
NC		 18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
0d8dfecf 23#include "sysdep.h"
df7b86aa 24#include <stdio.h>
252b5132 25#include "opcode/mips.h"
c3c07478
RS		 26#include "mips-formats.h"
27
28static unsigned char reg_0_map[] = { 0 };
29static unsigned char reg_29_map[] = { 29 };
30static unsigned char reg_31_map[] = { 31 };
31static unsigned char reg_m16_map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
32static unsigned char reg32r_map[] = {
33 0, 8, 16, 24,
34 1, 9, 17, 25,
35 2, 10, 18, 26,
36 3, 11, 19, 27,
37 4, 12, 20, 28,
38 5, 13, 21, 29,
39 6, 14, 22, 30,
40 7, 15, 23, 31
41};
42
43/* Return the meaning of operand character TYPE, or null if it isn't
44 recognized. If the operand is affected by the EXTEND instruction,
45 EXTENDED_P selects between the extended and unextended forms.
46 The extended forms all have an lsb of 0. */
47
48const struct mips_operand *
49decode_mips16_operand (char type, bfd_boolean extended_p)
50{
51 switch (type)
52 {
53 case '0': MAPPED_REG (0, 0, GP, reg_0_map);
54
55 case 'L': SPECIAL (6, 5, ENTRY_EXIT_LIST);
56 case 'M': SPECIAL (7, 0, SAVE_RESTORE_LIST);
57 case 'P': SPECIAL (0, 0, PC);
58 case 'R': MAPPED_REG (0, 0, GP, reg_31_map);
59 case 'S': MAPPED_REG (0, 0, GP, reg_29_map);
60 case 'X': REG (5, 0, GP);
61 case 'Y': MAPPED_REG (5, 3, GP, reg32r_map);
62 case 'Z': MAPPED_REG (3, 0, GP, reg_m16_map);
63
64 case 'a': JUMP (26, 0, 2);
65 case 'e': UINT (11, 0);
66 case 'i': JALX (26, 0, 2);
67 case 'l': SPECIAL (6, 5, ENTRY_EXIT_LIST);
68 case 'm': SPECIAL (7, 0, SAVE_RESTORE_LIST);
69 case 'v': MAPPED_REG (3, 8, GP, reg_m16_map);
70 case 'w': MAPPED_REG (3, 5, GP, reg_m16_map);
71 case 'x': MAPPED_REG (3, 8, GP, reg_m16_map);
72 case 'y': MAPPED_REG (3, 5, GP, reg_m16_map);
73 case 'z': MAPPED_REG (3, 2, GP, reg_m16_map);
74 }
75
76 if (extended_p)
77 switch (type)
78 {
79 case '<': UINT (5, 0);
80 case '>': UINT (5, 0);
81 case '[': UINT (6, 0);
82 case ']': UINT (6, 0);
83
84 case '4': SINT (15, 0);
85 case '5': SINT (16, 0);
86 case '6': SINT (16, 0);
87 case '8': SINT (16, 0);
88
3ccad066
RS		 89 case 'A': PCREL (16, 0, TRUE, 0, 2, FALSE, FALSE);
90 case 'B': PCREL (16, 0, TRUE, 0, 3, FALSE, FALSE);
c3c07478
RS		 91 case 'C': SINT (16, 0);
92 case 'D': SINT (16, 0);
3ccad066 93 case 'E': PCREL (16, 0, TRUE, 0, 2, FALSE, FALSE);
c3c07478
RS		 94 case 'H': SINT (16, 0);
95 case 'K': SINT (16, 0);
96 case 'U': UINT (16, 0);
97 case 'V': SINT (16, 0);
98 case 'W': SINT (16, 0);
99
100 case 'j': SINT (16, 0);
101 case 'k': SINT (16, 0);
102 case 'p': BRANCH (16, 0, 1);
103 case 'q': BRANCH (16, 0, 1);
104 }
105 else
106 switch (type)
107 {
108 case '<': INT_ADJ (3, 2, 8, 0, FALSE);
109 case '>': INT_ADJ (3, 8, 8, 0, FALSE);
110 case '[': INT_ADJ (3, 2, 8, 0, FALSE);
111 case ']': INT_ADJ (3, 8, 8, 0, FALSE);
112
113 case '4': SINT (4, 0);
114 case '5': UINT (5, 0);
115 case '6': UINT (6, 5);
116 case '8': UINT (8, 0);
117
3ccad066
RS		 118 case 'A': PCREL (8, 0, FALSE, 2, 2, FALSE, FALSE);
119 case 'B': PCREL (5, 0, FALSE, 3, 3, FALSE, FALSE);
c3c07478
RS		 120 case 'C': INT_ADJ (8, 0, 255, 3, FALSE); /* (0 .. 255) << 3 */
121 case 'D': INT_ADJ (5, 0, 31, 3, FALSE); /* (0 .. 31) << 3 */
3ccad066 122 case 'E': PCREL (5, 0, FALSE, 2, 2, FALSE, FALSE);
c3c07478
RS		 123 case 'H': INT_ADJ (5, 0, 31, 1, FALSE); /* (0 .. 31) << 1 */
124 case 'K': INT_ADJ (8, 0, 127, 3, FALSE); /* (-128 .. 127) << 3 */
125 case 'U': UINT (8, 0);
126 case 'V': INT_ADJ (8, 0, 255, 2, FALSE); /* (0 .. 255) << 2 */
127 case 'W': INT_ADJ (5, 0, 31, 2, FALSE); /* (0 .. 31) << 2 */
128
129 case 'j': SINT (5, 0);
130 case 'k': SINT (8, 0);
131 case 'p': BRANCH (8, 0, 1);
132 case 'q': BRANCH (11, 0, 1);
133 }
134 return 0;
135}
252b5132
RH		 136
137/* This is the opcodes table for the mips16 processor. The format of
138 this table is intentionally identical to the one in mips-opc.c.
139 However, the special letters that appear in the argument string are
140 different, and the table uses some different flags. */
141
142/* Use some short hand macros to keep down the length of the lines in
143 the opcodes table. */
144
145#define UBD INSN_UNCOND_BRANCH_DELAY
252b5132 146
fc76e730
RS		 147#define WR_1 INSN_WRITE_1
148#define WR_2 INSN_WRITE_2
149#define RD_1 INSN_READ_1
150#define RD_2 INSN_READ_2
151#define RD_3 INSN_READ_3
152#define RD_4 INSN_READ_4
153#define MOD_1 (WR_1|RD_1)
154#define MOD_2 (WR_2|RD_2)
252b5132 155
fc76e730
RS		 156#define RD_T INSN_READ_GPR_24
157#define WR_T INSN_WRITE_GPR_24
158#define WR_31 INSN_WRITE_GPR_31
252b5132
RH		 159
160#define WR_HI INSN_WRITE_HI
161#define WR_LO INSN_WRITE_LO
162#define RD_HI INSN_READ_HI
163#define RD_LO INSN_READ_LO
164
bcd530a7
RS		 165#define NODS INSN_NO_DELAY_SLOT
166#define TRAP INSN_NO_DELAY_SLOT
252b5132 167
fc76e730
RS		 168#define RD_16 INSN2_READ_GPR_16
169#define RD_SP INSN2_READ_SP
170#define WR_SP INSN2_WRITE_SP
171#define MOD_SP (RD_SP|WR_SP)
26545944
RS		 172#define RD_31 INSN2_READ_GPR_31
173#define RD_PC INSN2_READ_PC
174#define UBR INSN2_UNCOND_BRANCH
175#define CBR INSN2_COND_BRANCH
176
9b3f89ee 177#define I1 INSN_ISA1
252b5132 178#define I3 INSN_ISA3
9b3f89ee
TS		 179#define I32 INSN_ISA32
180#define I64 INSN_ISA64
181#define T3 INSN_3900
252b5132 182
b23da31b
NC		 183const struct mips_opcode mips16_opcodes[] =
184{
e7ae278d 185/* name, args, match, mask, pinfo, pinfo2, membership */
fc76e730
RS		 186{"nop", "", 0x6500, 0xffff, 0, RD_16, I1, 0, 0 }, /* move $0,$Z */
187{"la", "x,A", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
a8d92fc6 188{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 },
fc76e730
RS		 189{"addiu", "y,x,4", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
190{"addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 },
26545944
RS		 191{"addiu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
192{"addiu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
fc76e730
RS		 193{"addiu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
194{"addiu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
195{"addu", "z,v,y", 0xe001, 0xf803, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
196{"addu", "y,x,4", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
197{"addu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 },
26545944
RS		 198{"addu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
199{"addu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
fc76e730
RS		 200{"addu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
201{"addu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
202{"and", "x,y", 0xe80c, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
26545944 203{"b", "q", 0x1000, 0xf800, 0, UBR, I1, 0, 0 },
a8d92fc6
RS		 204{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, I1, 0, 0 },
205{"beq", "x,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 },
fc76e730 206{"beqz", "x,p", 0x2000, 0xf800, RD_1, CBR, I1, 0, 0 },
a8d92fc6
RS		 207{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 },
208{"bge", "x,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1, 0, 0 },
209{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1, 0, 0 },
210{"bgeu", "x,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1, 0, 0 },
211{"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0, I1, 0, 0 },
212{"bgt", "x,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1, 0, 0 },
213{"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1, 0, 0 },
214{"bgtu", "x,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1, 0, 0 },
215{"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0, I1, 0, 0 },
216{"ble", "x,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1, 0, 0 },
217{"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1, 0, 0 },
218{"bleu", "x,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1, 0, 0 },
219{"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0, I1, 0, 0 },
220{"blt", "x,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1, 0, 0 },
221{"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1, 0, 0 },
222{"bltu", "x,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1, 0, 0 },
223{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, I1, 0, 0 },
224{"bne", "x,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 },
fc76e730 225{"bnez", "x,p", 0x2800, 0xf800, RD_1, CBR, I1, 0, 0 },
a8d92fc6 226{"break", "6", 0xe805, 0xf81f, TRAP, 0, I1, 0, 0 },
26545944
RS		 227{"bteqz", "p", 0x6000, 0xff00, RD_T, CBR, I1, 0, 0 },
228{"btnez", "p", 0x6100, 0xff00, RD_T, CBR, I1, 0, 0 },
fc76e730
RS		 229{"cmpi", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
230{"cmp", "x,y", 0xe80a, 0xf81f, RD_1|RD_2|WR_T, 0, I1, 0, 0 },
231{"cmp", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
232{"dla", "y,E", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
233{"daddiu", "y,x,4", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
234{"daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
26545944
RS		 235{"daddiu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
236{"daddiu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
fc76e730
RS		 237{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
238{"daddiu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 },
239{"daddu", "z,v,y", 0xe000, 0xf803, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
240{"daddu", "y,x,4", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
241{"daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
26545944
RS		 242{"daddu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
243{"daddu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
fc76e730
RS		 244{"daddu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
245{"daddu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 },
246{"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I3, 0, 0 },
a8d92fc6 247{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I1, 0, 0 },
fc76e730 248{"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I3, 0, 0 },
a8d92fc6 249{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I1, 0, 0 },
fc76e730 250{"div", "0,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I1, 0, 0 },
a8d92fc6 251{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 },
fc76e730 252{"divu", "0,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I1, 0, 0 },
a8d92fc6
RS		 253{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, 0 },
254{"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, 0 },
fc76e730
RS		 255{"dmult", "x,y", 0xe81c, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, 0, I3, 0, 0 },
256{"dmultu", "x,y", 0xe81d, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, 0, I3, 0, 0 },
257{"drem", "0,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I3, 0, 0 },
a8d92fc6 258{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I1, 0, 0 },
fc76e730 259{"dremu", "0,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I3, 0, 0 },
a8d92fc6 260{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I1, 0, 0 },
fc76e730
RS		 261{"dsllv", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 },
262{"dsll", "x,w,[", 0x3001, 0xf803, WR_1|RD_2, 0, I3, 0, 0 },
263{"dsll", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 },
264{"dsrav", "y,x", 0xe817, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 },
265{"dsra", "y,]", 0xe813, 0xf81f, MOD_1, 0, I3, 0, 0 },
266{"dsra", "y,x", 0xe817, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 },
267{"dsrlv", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 },
268{"dsrl", "y,]", 0xe808, 0xf81f, MOD_1, 0, I3, 0, 0 },
269{"dsrl", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 },
270{"dsubu", "z,v,y", 0xe002, 0xf803, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
a8d92fc6
RS		 271{"dsubu", "y,x,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I1, 0, 0 },
272{"dsubu", "y,I", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I1, 0, 0 },
273{"exit", "L", 0xed09, 0xff1f, TRAP, 0, I1, 0, 0 },
274{"exit", "L", 0xee09, 0xff1f, TRAP, 0, I1, 0, 0 },
275{"exit", "", 0xef09, 0xffff, TRAP, 0, I1, 0, 0 },
276{"exit", "L", 0xef09, 0xff1f, TRAP, 0, I1, 0, 0 },
277{"entry", "", 0xe809, 0xffff, TRAP, 0, I1, 0, 0 },
278{"entry", "l", 0xe809, 0xf81f, TRAP, 0, I1, 0, 0 },
279{"extend", "e", 0xf000, 0xf800, 0, 0, I1, 0, 0 },
fc76e730
RS		 280{"jalr", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, 0, I1, 0, 0 },
281{"jalr", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, 0, I1, 0, 0 },
282{"jal", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, 0, I1, 0, 0 },
283{"jal", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, 0, I1, 0, 0 },
284{"jal", "a", 0x1800, 0xfc00, WR_31|UBD, 0, I1, 0, 0 },
285{"jalx", "i", 0x1c00, 0xfc00, WR_31|UBD, 0, I1, 0, 0 },
286{"jr", "x", 0xe800, 0xf8ff, RD_1|UBD, 0, I1, 0, 0 },
26545944 287{"jr", "R", 0xe820, 0xffff, UBD, RD_31, I1, 0, 0 },
fc76e730 288{"j", "x", 0xe800, 0xf8ff, RD_1|UBD, 0, I1, 0, 0 },
26545944 289{"j", "R", 0xe820, 0xffff, UBD, RD_31, I1, 0, 0 },
ceb94aa5
RS		 290/* MIPS16e compact branches. We keep them near the ordinary branches
291 so that we easily find them when converting a normal branch to a
292 compact one. */
fc76e730
RS		 293{"jalrc", "x", 0xe8c0, 0xf8ff, RD_1|WR_31|NODS, UBR, I32, 0, 0 },
294{"jalrc", "R,x", 0xe8c0, 0xf8ff, RD_2|WR_31|NODS, UBR, I32, 0, 0 },
295{"jrc", "x", 0xe880, 0xf8ff, RD_1|NODS, UBR, I32, 0, 0 },
296{"jrc", "R", 0xe8a0, 0xffff, NODS, RD_31|UBR, I32, 0, 0 },
297{"lb", "y,5(x)", 0x8000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
298{"lbu", "y,5(x)", 0xa000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
299{"ld", "y,D(x)", 0x3800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 },
300{"ld", "y,B", 0xfc00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
301{"ld", "y,D(P)", 0xfc00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
302{"ld", "y,D(S)", 0xf800, 0xff00, WR_1, RD_SP, I3, 0, 0 },
303{"lh", "y,H(x)", 0x8800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
304{"lhu", "y,H(x)", 0xa800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
305{"li", "x,U", 0x6800, 0xf800, WR_1, 0, I1, 0, 0 },
306{"lw", "y,W(x)", 0x9800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
307{"lw", "x,A", 0xb000, 0xf800, WR_1, RD_PC, I1, 0, 0 },
308{"lw", "x,V(P)", 0xb000, 0xf800, WR_1, RD_PC, I1, 0, 0 },
309{"lw", "x,V(S)", 0x9000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
310{"lwu", "y,W(x)", 0xb800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 },
311{"mfhi", "x", 0xe810, 0xf8ff, WR_1|RD_HI, 0, I1, 0, 0 },
312{"mflo", "x", 0xe812, 0xf8ff, WR_1|RD_LO, 0, I1, 0, 0 },
313{"move", "y,X", 0x6700, 0xff00, WR_1|RD_2, 0, I1, 0, 0 },
314{"move", "Y,Z", 0x6500, 0xff00, WR_1|RD_2, 0, I1, 0, 0 },
a8d92fc6 315{"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0, I1, 0, 0 },
fc76e730
RS		 316{"mult", "x,y", 0xe818, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, 0, I1, 0, 0 },
317{"multu", "x,y", 0xe819, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, 0, I1, 0, 0 },
318{"neg", "x,w", 0xe80b, 0xf81f, WR_1|RD_2, 0, I1, 0, 0 },
319{"not", "x,w", 0xe80f, 0xf81f, WR_1|RD_2, 0, I1, 0, 0 },
320{"or", "x,y", 0xe80d, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
321{"rem", "0,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I1, 0, 0 },
a8d92fc6 322{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, 0 },
fc76e730 323{"remu", "0,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I1, 0, 0 },
a8d92fc6 324{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 },
fc76e730
RS		 325{"sb", "y,5(x)", 0xc000, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
326{"sd", "y,D(x)", 0x7800, 0xf800, RD_1|RD_3, 0, I3, 0, 0 },
327{"sd", "y,D(S)", 0xf900, 0xff00, RD_1, RD_PC, I3, 0, 0 },
328{"sd", "R,C(S)", 0xfa00, 0xff00, 0, RD_31|RD_PC, I1, 0, 0 },
329{"sh", "y,H(x)", 0xc800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
330{"sllv", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
331{"sll", "x,w,<", 0x3000, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },
332{"sll", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
333{"slti", "x,8", 0x5000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
334{"slt", "x,y", 0xe802, 0xf81f, RD_1|RD_2|WR_T, 0, I1, 0, 0 },
335{"slt", "x,8", 0x5000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
336{"sltiu", "x,8", 0x5800, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
337{"sltu", "x,y", 0xe803, 0xf81f, RD_1|RD_2|WR_T, 0, I1, 0, 0 },
338{"sltu", "x,8", 0x5800, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
339{"srav", "y,x", 0xe807, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
340{"sra", "x,w,<", 0x3003, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },
341{"sra", "y,x", 0xe807, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
342{"srlv", "y,x", 0xe806, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
343{"srl", "x,w,<", 0x3002, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },
344{"srl", "y,x", 0xe806, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
345{"subu", "z,v,y", 0xe003, 0xf803, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
a8d92fc6
RS		 346{"subu", "y,x,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1, 0, 0 },
347{"subu", "x,I", 0, (int) M_SUBU_I_2, INSN_MACRO, 0, I1, 0, 0 },
fc76e730
RS		 348{"sw", "y,W(x)", 0xd800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
349{"sw", "x,V(S)", 0xd000, 0xf800, RD_1, RD_SP, I1, 0, 0 },
350{"sw", "R,V(S)", 0x6200, 0xff00, 0, RD_31|RD_SP, I1, 0, 0 },
351{"xor", "x,y", 0xe80e, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
4b185e97 352 /* MIPS16e additions */
26545944 353{"restore", "M", 0x6400, 0xff80, WR_31|NODS, MOD_SP, I32, 0, 0 },
fc76e730 354{"save", "m", 0x6480, 0xff80, NODS, RD_31|MOD_SP, I32, 0, 0 },
a8d92fc6 355{"sdbbp", "6", 0xe801, 0xf81f, TRAP, 0, I32, 0, 0 },
fc76e730
RS		 356{"seb", "x", 0xe891, 0xf8ff, MOD_1, 0, I32, 0, 0 },
357{"seh", "x", 0xe8b1, 0xf8ff, MOD_1, 0, I32, 0, 0 },
358{"sew", "x", 0xe8d1, 0xf8ff, MOD_1, 0, I64, 0, 0 },
359{"zeb", "x", 0xe811, 0xf8ff, MOD_1, 0, I32, 0, 0 },
360{"zeh", "x", 0xe831, 0xf8ff, MOD_1, 0, I32, 0, 0 },
361{"zew", "x", 0xe851, 0xf8ff, MOD_1, 0, I64, 0, 0 },
252b5132
RH		 362};
363
364const int bfd_mips16_num_opcodes =
365 ((sizeof mips16_opcodes) / (sizeof (mips16_opcodes[0])));
GDB Binutils - Deliverables
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