projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 252b5132 | 1 | /* mips16-opc.c. Mips16 opcode table. |
| df7b86aa | 2 | Copyright 1996, 1997, 1998, 2000, 2005, 2006, 2007, 2012 |
| aa820537 | 3 | Free Software Foundation, Inc. |
| 252b5132 RH |
4 | Contributed by Ian Lance Taylor, Cygnus Support |
| 5 | ||
| 9b201bb5 | 6 | This file is part of the GNU opcodes library. |
| 252b5132 | 7 | |
| 9b201bb5 NC |
8 | This library is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by | |
| 10 | the Free Software Foundation; either version 3, or (at your option) | |
| 11 | any later version. | |
| 252b5132 | 12 | |
| 9b201bb5 NC |
13 | It is distributed in the hope that it will be useful, but WITHOUT |
| 14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 16 | License for more details. | |
| 252b5132 | 17 | |
| 9b201bb5 NC |
18 | You should have received a copy of the GNU General Public License |
| 19 | along with this file; see the file COPYING. If not, write to the | |
| 20 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
| 21 | MA 02110-1301, USA. */ | |
| 252b5132 | 22 | |
| 0d8dfecf | 23 | #include "sysdep.h" |
| df7b86aa | 24 | #include <stdio.h> |
| 252b5132 | 25 | #include "opcode/mips.h" |
| c3c07478 RS |
26 | #include "mips-formats.h" |
| 27 | ||
| 28 | static unsigned char reg_0_map[] = { 0 }; | |
| 29 | static unsigned char reg_29_map[] = { 29 }; | |
| 30 | static unsigned char reg_31_map[] = { 31 }; | |
| 31 | static unsigned char reg_m16_map[] = { 16, 17, 2, 3, 4, 5, 6, 7 }; | |
| 32 | static unsigned char reg32r_map[] = { | |
| 33 | 0, 8, 16, 24, | |
| 34 | 1, 9, 17, 25, | |
| 35 | 2, 10, 18, 26, | |
| 36 | 3, 11, 19, 27, | |
| 37 | 4, 12, 20, 28, | |
| 38 | 5, 13, 21, 29, | |
| 39 | 6, 14, 22, 30, | |
| 40 | 7, 15, 23, 31 | |
| 41 | }; | |
| 42 | ||
| 43 | /* Return the meaning of operand character TYPE, or null if it isn't | |
| 44 | recognized. If the operand is affected by the EXTEND instruction, | |
| 45 | EXTENDED_P selects between the extended and unextended forms. | |
| 46 | The extended forms all have an lsb of 0. */ | |
| 47 | ||
| 48 | const struct mips_operand * | |
| 49 | decode_mips16_operand (char type, bfd_boolean extended_p) | |
| 50 | { | |
| 51 | switch (type) | |
| 52 | { | |
| 53 | case '0': MAPPED_REG (0, 0, GP, reg_0_map); | |
| 54 | ||
| 55 | case 'L': SPECIAL (6, 5, ENTRY_EXIT_LIST); | |
| 56 | case 'M': SPECIAL (7, 0, SAVE_RESTORE_LIST); | |
| 57 | case 'P': SPECIAL (0, 0, PC); | |
| 58 | case 'R': MAPPED_REG (0, 0, GP, reg_31_map); | |
| 59 | case 'S': MAPPED_REG (0, 0, GP, reg_29_map); | |
| 60 | case 'X': REG (5, 0, GP); | |
| 61 | case 'Y': MAPPED_REG (5, 3, GP, reg32r_map); | |
| 62 | case 'Z': MAPPED_REG (3, 0, GP, reg_m16_map); | |
| 63 | ||
| 64 | case 'a': JUMP (26, 0, 2); | |
| 65 | case 'e': UINT (11, 0); | |
| 66 | case 'i': JALX (26, 0, 2); | |
| 67 | case 'l': SPECIAL (6, 5, ENTRY_EXIT_LIST); | |
| 68 | case 'm': SPECIAL (7, 0, SAVE_RESTORE_LIST); | |
| 69 | case 'v': MAPPED_REG (3, 8, GP, reg_m16_map); | |
| 70 | case 'w': MAPPED_REG (3, 5, GP, reg_m16_map); | |
| 71 | case 'x': MAPPED_REG (3, 8, GP, reg_m16_map); | |
| 72 | case 'y': MAPPED_REG (3, 5, GP, reg_m16_map); | |
| 73 | case 'z': MAPPED_REG (3, 2, GP, reg_m16_map); | |
| 74 | } | |
| 75 | ||
| 76 | if (extended_p) | |
| 77 | switch (type) | |
| 78 | { | |
| 79 | case '<': UINT (5, 0); | |
| 80 | case '>': UINT (5, 0); | |
| 81 | case '[': UINT (6, 0); | |
| 82 | case ']': UINT (6, 0); | |
| 83 | ||
| 84 | case '4': SINT (15, 0); | |
| 85 | case '5': SINT (16, 0); | |
| 86 | case '6': SINT (16, 0); | |
| 87 | case '8': SINT (16, 0); | |
| 88 | ||
| 89 | case 'A': PCREL (16, 0, 2, 0, TRUE, FALSE, FALSE); | |
| 90 | case 'B': PCREL (16, 0, 3, 0, TRUE, FALSE, FALSE); | |
| 91 | case 'C': SINT (16, 0); | |
| 92 | case 'D': SINT (16, 0); | |
| 93 | case 'E': PCREL (16, 0, 2, 0, TRUE, FALSE, FALSE); | |
| 94 | case 'H': SINT (16, 0); | |
| 95 | case 'K': SINT (16, 0); | |
| 96 | case 'U': UINT (16, 0); | |
| 97 | case 'V': SINT (16, 0); | |
| 98 | case 'W': SINT (16, 0); | |
| 99 | ||
| 100 | case 'j': SINT (16, 0); | |
| 101 | case 'k': SINT (16, 0); | |
| 102 | case 'p': BRANCH (16, 0, 1); | |
| 103 | case 'q': BRANCH (16, 0, 1); | |
| 104 | } | |
| 105 | else | |
| 106 | switch (type) | |
| 107 | { | |
| 108 | case '<': INT_ADJ (3, 2, 8, 0, FALSE); | |
| 109 | case '>': INT_ADJ (3, 8, 8, 0, FALSE); | |
| 110 | case '[': INT_ADJ (3, 2, 8, 0, FALSE); | |
| 111 | case ']': INT_ADJ (3, 8, 8, 0, FALSE); | |
| 112 | ||
| 113 | case '4': SINT (4, 0); | |
| 114 | case '5': UINT (5, 0); | |
| 115 | case '6': UINT (6, 5); | |
| 116 | case '8': UINT (8, 0); | |
| 117 | ||
| 118 | case 'A': PCREL (8, 0, 2, 2, FALSE, FALSE, FALSE); | |
| 119 | case 'B': PCREL (5, 0, 3, 3, FALSE, FALSE, FALSE); | |
| 120 | case 'C': INT_ADJ (8, 0, 255, 3, FALSE); /* (0 .. 255) << 3 */ | |
| 121 | case 'D': INT_ADJ (5, 0, 31, 3, FALSE); /* (0 .. 31) << 3 */ | |
| 122 | case 'E': PCREL (5, 0, 2, 2, FALSE, FALSE, FALSE); | |
| 123 | case 'H': INT_ADJ (5, 0, 31, 1, FALSE); /* (0 .. 31) << 1 */ | |
| 124 | case 'K': INT_ADJ (8, 0, 127, 3, FALSE); /* (-128 .. 127) << 3 */ | |
| 125 | case 'U': UINT (8, 0); | |
| 126 | case 'V': INT_ADJ (8, 0, 255, 2, FALSE); /* (0 .. 255) << 2 */ | |
| 127 | case 'W': INT_ADJ (5, 0, 31, 2, FALSE); /* (0 .. 31) << 2 */ | |
| 128 | ||
| 129 | case 'j': SINT (5, 0); | |
| 130 | case 'k': SINT (8, 0); | |
| 131 | case 'p': BRANCH (8, 0, 1); | |
| 132 | case 'q': BRANCH (11, 0, 1); | |
| 133 | } | |
| 134 | return 0; | |
| 135 | } | |
| 252b5132 RH |
136 | |
| 137 | /* This is the opcodes table for the mips16 processor. The format of | |
| 138 | this table is intentionally identical to the one in mips-opc.c. | |
| 139 | However, the special letters that appear in the argument string are | |
| 140 | different, and the table uses some different flags. */ | |
| 141 | ||
| 142 | /* Use some short hand macros to keep down the length of the lines in | |
| 143 | the opcodes table. */ | |
| 144 | ||
| 145 | #define UBD INSN_UNCOND_BRANCH_DELAY | |
| 9a2c7088 MR |
146 | #define UBR MIPS16_INSN_UNCOND_BRANCH |
| 147 | #define CBR MIPS16_INSN_COND_BRANCH | |
| 252b5132 RH |
148 | |
| 149 | #define WR_x MIPS16_INSN_WRITE_X | |
| 150 | #define WR_y MIPS16_INSN_WRITE_Y | |
| 151 | #define WR_z MIPS16_INSN_WRITE_Z | |
| 152 | #define WR_T MIPS16_INSN_WRITE_T | |
| 153 | #define WR_SP MIPS16_INSN_WRITE_SP | |
| 154 | #define WR_31 MIPS16_INSN_WRITE_31 | |
| 155 | #define WR_Y MIPS16_INSN_WRITE_GPR_Y | |
| 156 | ||
| 157 | #define RD_x MIPS16_INSN_READ_X | |
| 158 | #define RD_y MIPS16_INSN_READ_Y | |
| 159 | #define RD_Z MIPS16_INSN_READ_Z | |
| 160 | #define RD_T MIPS16_INSN_READ_T | |
| 161 | #define RD_SP MIPS16_INSN_READ_SP | |
| 162 | #define RD_31 MIPS16_INSN_READ_31 | |
| 163 | #define RD_PC MIPS16_INSN_READ_PC | |
| 164 | #define RD_X MIPS16_INSN_READ_GPR_X | |
| 165 | ||
| 166 | #define WR_HI INSN_WRITE_HI | |
| 167 | #define WR_LO INSN_WRITE_LO | |
| 168 | #define RD_HI INSN_READ_HI | |
| 169 | #define RD_LO INSN_READ_LO | |
| 170 | ||
| bcd530a7 RS |
171 | #define NODS INSN_NO_DELAY_SLOT |
| 172 | #define TRAP INSN_NO_DELAY_SLOT | |
| 252b5132 | 173 | |
| 9b3f89ee | 174 | #define I1 INSN_ISA1 |
| 252b5132 | 175 | #define I3 INSN_ISA3 |
| 9b3f89ee TS |
176 | #define I32 INSN_ISA32 |
| 177 | #define I64 INSN_ISA64 | |
| 178 | #define T3 INSN_3900 | |
| 252b5132 | 179 | |
| b23da31b NC |
180 | const struct mips_opcode mips16_opcodes[] = |
| 181 | { | |
| e7ae278d | 182 | /* name, args, match, mask, pinfo, pinfo2, membership */ |
| a8d92fc6 RS |
183 | {"nop", "", 0x6500, 0xffff, RD_Z, 0, I1, 0, 0 }, /* move $0,$Z */ |
| 184 | {"la", "x,A", 0x0800, 0xf800, WR_x|RD_PC, 0, I1, 0, 0 }, | |
| 185 | {"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 }, | |
| 186 | {"addiu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0, I1, 0, 0 }, | |
| 187 | {"addiu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0, I1, 0, 0 }, | |
| 188 | {"addiu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1, 0, 0 }, | |
| 189 | {"addiu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1, 0, 0 }, | |
| 190 | {"addiu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0, I1, 0, 0 }, | |
| 191 | {"addiu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, I1, 0, 0 }, | |
| 192 | {"addu", "z,v,y", 0xe001, 0xf803, WR_z|RD_x|RD_y, 0, I1, 0, 0 }, | |
| 193 | {"addu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0, I1, 0, 0 }, | |
| 194 | {"addu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0, I1, 0, 0 }, | |
| 195 | {"addu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1, 0, 0 }, | |
| 196 | {"addu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1, 0, 0 }, | |
| 197 | {"addu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0, I1, 0, 0 }, | |
| 198 | {"addu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, I1, 0, 0 }, | |
| 199 | {"and", "x,y", 0xe80c, 0xf81f, WR_x|RD_x|RD_y, 0, I1, 0, 0 }, | |
| 200 | {"b", "q", 0x1000, 0xf800, UBR, 0, I1, 0, 0 }, | |
| 201 | {"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, I1, 0, 0 }, | |
| 202 | {"beq", "x,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| 203 | {"beqz", "x,p", 0x2000, 0xf800, CBR|RD_x, 0, I1, 0, 0 }, | |
| 204 | {"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 }, | |
| 205 | {"bge", "x,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| 206 | {"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1, 0, 0 }, | |
| 207 | {"bgeu", "x,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| 208 | {"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0, I1, 0, 0 }, | |
| 209 | {"bgt", "x,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| 210 | {"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1, 0, 0 }, | |
| 211 | {"bgtu", "x,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| 212 | {"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0, I1, 0, 0 }, | |
| 213 | {"ble", "x,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| 214 | {"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1, 0, 0 }, | |
| 215 | {"bleu", "x,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| 216 | {"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0, I1, 0, 0 }, | |
| 217 | {"blt", "x,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| 218 | {"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1, 0, 0 }, | |
| 219 | {"bltu", "x,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| 220 | {"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, I1, 0, 0 }, | |
| 221 | {"bne", "x,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| 222 | {"bnez", "x,p", 0x2800, 0xf800, CBR|RD_x, 0, I1, 0, 0 }, | |
| 223 | {"break", "6", 0xe805, 0xf81f, TRAP, 0, I1, 0, 0 }, | |
| 224 | {"bteqz", "p", 0x6000, 0xff00, CBR|RD_T, 0, I1, 0, 0 }, | |
| 225 | {"btnez", "p", 0x6100, 0xff00, CBR|RD_T, 0, I1, 0, 0 }, | |
| 226 | {"cmpi", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, I1, 0, 0 }, | |
| 227 | {"cmp", "x,y", 0xe80a, 0xf81f, WR_T|RD_x|RD_y, 0, I1, 0, 0 }, | |
| 228 | {"cmp", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, I1, 0, 0 }, | |
| 229 | {"dla", "y,E", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3, 0, 0 }, | |
| 230 | {"daddiu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, 0, I3, 0, 0 }, | |
| 231 | {"daddiu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, 0, I3, 0, 0 }, | |
| 232 | {"daddiu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3, 0, 0 }, | |
| 233 | {"daddiu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3, 0, 0 }, | |
| 234 | {"daddiu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3, 0, 0 }, | |
| 235 | {"daddiu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, 0, I3, 0, 0 }, | |
| 236 | {"daddu", "z,v,y", 0xe000, 0xf803, WR_z|RD_x|RD_y, 0, I3, 0, 0 }, | |
| 237 | {"daddu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, 0, I3, 0, 0 }, | |
| 238 | {"daddu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, 0, I3, 0, 0 }, | |
| 239 | {"daddu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3, 0, 0 }, | |
| 240 | {"daddu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3, 0, 0 }, | |
| 241 | {"daddu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3, 0, 0 }, | |
| 242 | {"daddu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, 0, I3, 0, 0 }, | |
| 243 | {"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3, 0, 0 }, | |
| 244 | {"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I1, 0, 0 }, | |
| 245 | {"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3, 0, 0 }, | |
| 246 | {"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I1, 0, 0 }, | |
| 247 | {"div", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1, 0, 0 }, | |
| 248 | {"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 }, | |
| 249 | {"divu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1, 0, 0 }, | |
| 250 | {"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, 0 }, | |
| 251 | {"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, 0 }, | |
| 252 | {"dmult", "x,y", 0xe81c, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3, 0, 0 }, | |
| 253 | {"dmultu", "x,y", 0xe81d, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3, 0, 0 }, | |
| 254 | {"drem", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3, 0, 0 }, | |
| 255 | {"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I1, 0, 0 }, | |
| 256 | {"dremu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3, 0, 0 }, | |
| 257 | {"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I1, 0, 0 }, | |
| 258 | {"dsllv", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, 0, I3, 0, 0 }, | |
| 259 | {"dsll", "x,w,[", 0x3001, 0xf803, WR_x|RD_y, 0, I3, 0, 0 }, | |
| 260 | {"dsll", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, 0, I3, 0, 0 }, | |
| 261 | {"dsrav", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, 0, I3, 0, 0 }, | |
| 262 | {"dsra", "y,]", 0xe813, 0xf81f, WR_y|RD_y, 0, I3, 0, 0 }, | |
| 263 | {"dsra", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, 0, I3, 0, 0 }, | |
| 264 | {"dsrlv", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, 0, I3, 0, 0 }, | |
| 265 | {"dsrl", "y,]", 0xe808, 0xf81f, WR_y|RD_y, 0, I3, 0, 0 }, | |
| 266 | {"dsrl", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, 0, I3, 0, 0 }, | |
| 267 | {"dsubu", "z,v,y", 0xe002, 0xf803, WR_z|RD_x|RD_y, 0, I3, 0, 0 }, | |
| 268 | {"dsubu", "y,x,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| 269 | {"dsubu", "y,I", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I1, 0, 0 }, | |
| 270 | {"exit", "L", 0xed09, 0xff1f, TRAP, 0, I1, 0, 0 }, | |
| 271 | {"exit", "L", 0xee09, 0xff1f, TRAP, 0, I1, 0, 0 }, | |
| 272 | {"exit", "", 0xef09, 0xffff, TRAP, 0, I1, 0, 0 }, | |
| 273 | {"exit", "L", 0xef09, 0xff1f, TRAP, 0, I1, 0, 0 }, | |
| 274 | {"entry", "", 0xe809, 0xffff, TRAP, 0, I1, 0, 0 }, | |
| 275 | {"entry", "l", 0xe809, 0xf81f, TRAP, 0, I1, 0, 0 }, | |
| 276 | {"extend", "e", 0xf000, 0xf800, 0, 0, I1, 0, 0 }, | |
| 277 | {"jalr", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1, 0, 0 }, | |
| 278 | {"jalr", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1, 0, 0 }, | |
| 279 | {"jal", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1, 0, 0 }, | |
| 280 | {"jal", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1, 0, 0 }, | |
| 281 | {"jal", "a", 0x1800, 0xfc00, UBD|WR_31, 0, I1, 0, 0 }, | |
| 282 | {"jalx", "i", 0x1c00, 0xfc00, UBD|WR_31, 0, I1, 0, 0 }, | |
| 283 | {"jr", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, I1, 0, 0 }, | |
| 284 | {"jr", "R", 0xe820, 0xffff, UBD|RD_31, 0, I1, 0, 0 }, | |
| 285 | {"j", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, I1, 0, 0 }, | |
| 286 | {"j", "R", 0xe820, 0xffff, UBD|RD_31, 0, I1, 0, 0 }, | |
| ceb94aa5 RS |
287 | /* MIPS16e compact branches. We keep them near the ordinary branches |
| 288 | so that we easily find them when converting a normal branch to a | |
| 289 | compact one. */ | |
| a8d92fc6 RS |
290 | {"jalrc", "x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|NODS, 0, I32, 0, 0 }, |
| 291 | {"jalrc", "R,x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|NODS, 0, I32, 0, 0 }, | |
| 292 | {"jrc", "x", 0xe880, 0xf8ff, UBR|RD_x|NODS, 0, I32, 0, 0 }, | |
| 293 | {"jrc", "R", 0xe8a0, 0xffff, UBR|RD_31|NODS, 0, I32, 0, 0 }, | |
| 294 | {"lb", "y,5(x)", 0x8000, 0xf800, WR_y|RD_x, 0, I1, 0, 0 }, | |
| 295 | {"lbu", "y,5(x)", 0xa000, 0xf800, WR_y|RD_x, 0, I1, 0, 0 }, | |
| 296 | {"ld", "y,D(x)", 0x3800, 0xf800, WR_y|RD_x, 0, I3, 0, 0 }, | |
| 297 | {"ld", "y,B", 0xfc00, 0xff00, WR_y|RD_PC, 0, I3, 0, 0 }, | |
| 298 | {"ld", "y,D(P)", 0xfc00, 0xff00, WR_y|RD_PC, 0, I3, 0, 0 }, | |
| 299 | {"ld", "y,D(S)", 0xf800, 0xff00, WR_y|RD_SP, 0, I3, 0, 0 }, | |
| 300 | {"lh", "y,H(x)", 0x8800, 0xf800, WR_y|RD_x, 0, I1, 0, 0 }, | |
| 301 | {"lhu", "y,H(x)", 0xa800, 0xf800, WR_y|RD_x, 0, I1, 0, 0 }, | |
| 302 | {"li", "x,U", 0x6800, 0xf800, WR_x, 0, I1, 0, 0 }, | |
| 303 | {"lw", "y,W(x)", 0x9800, 0xf800, WR_y|RD_x, 0, I1, 0, 0 }, | |
| 304 | {"lw", "x,A", 0xb000, 0xf800, WR_x|RD_PC, 0, I1, 0, 0 }, | |
| 305 | {"lw", "x,V(P)", 0xb000, 0xf800, WR_x|RD_PC, 0, I1, 0, 0 }, | |
| 306 | {"lw", "x,V(S)", 0x9000, 0xf800, WR_x|RD_SP, 0, I1, 0, 0 }, | |
| 307 | {"lwu", "y,W(x)", 0xb800, 0xf800, WR_y|RD_x, 0, I3, 0, 0 }, | |
| 308 | {"mfhi", "x", 0xe810, 0xf8ff, WR_x|RD_HI, 0, I1, 0, 0 }, | |
| 309 | {"mflo", "x", 0xe812, 0xf8ff, WR_x|RD_LO, 0, I1, 0, 0 }, | |
| 310 | {"move", "y,X", 0x6700, 0xff00, WR_y|RD_X, 0, I1, 0, 0 }, | |
| 311 | {"move", "Y,Z", 0x6500, 0xff00, WR_Y|RD_Z, 0, I1, 0, 0 }, | |
| 312 | {"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0, I1, 0, 0 }, | |
| 313 | {"mult", "x,y", 0xe818, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1, 0, 0 }, | |
| 314 | {"multu", "x,y", 0xe819, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1, 0, 0 }, | |
| 315 | {"neg", "x,w", 0xe80b, 0xf81f, WR_x|RD_y, 0, I1, 0, 0 }, | |
| 316 | {"not", "x,w", 0xe80f, 0xf81f, WR_x|RD_y, 0, I1, 0, 0 }, | |
| 317 | {"or", "x,y", 0xe80d, 0xf81f, WR_x|RD_x|RD_y, 0, I1, 0, 0 }, | |
| 318 | {"rem", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1, 0, 0 }, | |
| 319 | {"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, 0 }, | |
| 320 | {"remu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1, 0, 0 }, | |
| 321 | {"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 }, | |
| 322 | {"sb", "y,5(x)", 0xc000, 0xf800, RD_y|RD_x, 0, I1, 0, 0 }, | |
| 323 | {"sd", "y,D(x)", 0x7800, 0xf800, RD_y|RD_x, 0, I3, 0, 0 }, | |
| 324 | {"sd", "y,D(S)", 0xf900, 0xff00, RD_y|RD_PC, 0, I3, 0, 0 }, | |
| 325 | {"sd", "R,C(S)", 0xfa00, 0xff00, RD_31|RD_PC, 0, I1, 0, 0 }, | |
| 326 | {"sh", "y,H(x)", 0xc800, 0xf800, RD_y|RD_x, 0, I1, 0, 0 }, | |
| 327 | {"sllv", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0, I1, 0, 0 }, | |
| 328 | {"sll", "x,w,<", 0x3000, 0xf803, WR_x|RD_y, 0, I1, 0, 0 }, | |
| 329 | {"sll", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0, I1, 0, 0 }, | |
| 330 | {"slti", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0, I1, 0, 0 }, | |
| 331 | {"slt", "x,y", 0xe802, 0xf81f, WR_T|RD_x|RD_y, 0, I1, 0, 0 }, | |
| 332 | {"slt", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0, I1, 0, 0 }, | |
| 333 | {"sltiu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0, I1, 0, 0 }, | |
| 334 | {"sltu", "x,y", 0xe803, 0xf81f, WR_T|RD_x|RD_y, 0, I1, 0, 0 }, | |
| 335 | {"sltu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0, I1, 0, 0 }, | |
| 336 | {"srav", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0, I1, 0, 0 }, | |
| 337 | {"sra", "x,w,<", 0x3003, 0xf803, WR_x|RD_y, 0, I1, 0, 0 }, | |
| 338 | {"sra", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0, I1, 0, 0 }, | |
| 339 | {"srlv", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0, I1, 0, 0 }, | |
| 340 | {"srl", "x,w,<", 0x3002, 0xf803, WR_x|RD_y, 0, I1, 0, 0 }, | |
| 341 | {"srl", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0, I1, 0, 0 }, | |
| 342 | {"subu", "z,v,y", 0xe003, 0xf803, WR_z|RD_x|RD_y, 0, I1, 0, 0 }, | |
| 343 | {"subu", "y,x,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1, 0, 0 }, | |
| 344 | {"subu", "x,I", 0, (int) M_SUBU_I_2, INSN_MACRO, 0, I1, 0, 0 }, | |
| 345 | {"sw", "y,W(x)", 0xd800, 0xf800, RD_y|RD_x, 0, I1, 0, 0 }, | |
| 346 | {"sw", "x,V(S)", 0xd000, 0xf800, RD_x|RD_SP, 0, I1, 0, 0 }, | |
| 347 | {"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP, 0, I1, 0, 0 }, | |
| 348 | {"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0, I1, 0, 0 }, | |
| 4b185e97 | 349 | /* MIPS16e additions */ |
| a8d92fc6 RS |
350 | {"restore", "M", 0x6400, 0xff80, WR_31|RD_SP|WR_SP|NODS, 0, I32, 0, 0 }, |
| 351 | {"save", "m", 0x6480, 0xff80, RD_31|RD_SP|WR_SP|NODS, 0, I32, 0, 0 }, | |
| 352 | {"sdbbp", "6", 0xe801, 0xf81f, TRAP, 0, I32, 0, 0 }, | |
| 353 | {"seb", "x", 0xe891, 0xf8ff, WR_x|RD_x, 0, I32, 0, 0 }, | |
| 354 | {"seh", "x", 0xe8b1, 0xf8ff, WR_x|RD_x, 0, I32, 0, 0 }, | |
| 355 | {"sew", "x", 0xe8d1, 0xf8ff, WR_x|RD_x, 0, I64, 0, 0 }, | |
| 356 | {"zeb", "x", 0xe811, 0xf8ff, WR_x|RD_x, 0, I32, 0, 0 }, | |
| 357 | {"zeh", "x", 0xe831, 0xf8ff, WR_x|RD_x, 0, I32, 0, 0 }, | |
| 358 | {"zew", "x", 0xe851, 0xf8ff, WR_x|RD_x, 0, I64, 0, 0 }, | |
| 252b5132 RH |
359 | }; |
| 360 | ||
| 361 | const int bfd_mips16_num_opcodes = | |
| 362 | ((sizeof mips16_opcodes) / (sizeof (mips16_opcodes[0]))); |