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[deliverable/binutils-gdb.git] / opcodes / mips16-opc.c
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252b5132 1/* mips16-opc.c. Mips16 opcode table.
2571583a 2 Copyright (C) 1996-2017 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Ian Lance Taylor, Cygnus Support
4
9b201bb5 5 This file is part of the GNU opcodes library.
252b5132 6
9b201bb5
NC		 7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
252b5132 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
252b5132 16
9b201bb5
NC		 17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
252b5132 21
0d8dfecf 22#include "sysdep.h"
df7b86aa 23#include <stdio.h>
252b5132 24#include "opcode/mips.h"
c3c07478
RS		 25#include "mips-formats.h"
26
27static unsigned char reg_0_map[] = { 0 };
28static unsigned char reg_29_map[] = { 29 };
29static unsigned char reg_31_map[] = { 31 };
30static unsigned char reg_m16_map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
31static unsigned char reg32r_map[] = {
32 0, 8, 16, 24,
33 1, 9, 17, 25,
34 2, 10, 18, 26,
35 3, 11, 19, 27,
36 4, 12, 20, 28,
37 5, 13, 21, 29,
38 6, 14, 22, 30,
39 7, 15, 23, 31
40};
41
42/* Return the meaning of operand character TYPE, or null if it isn't
43 recognized. If the operand is affected by the EXTEND instruction,
44 EXTENDED_P selects between the extended and unextended forms.
45 The extended forms all have an lsb of 0. */
46
47const struct mips_operand *
48decode_mips16_operand (char type, bfd_boolean extended_p)
49{
50 switch (type)
51 {
d8722d76
MR		 52 case '.': MAPPED_REG (0, 0, GP, reg_0_map);
53
5284e471
MR		 54 case '0': HINT (5, 0);
55 case '1': HINT (3, 5);
56 case '2': HINT (3, 8);
57 case '3': HINT (5, 16);
58 case '4': HINT (3, 21);
b2805ed5 59 case '6': UINT (6, 5);
c3c07478
RS		 60
61 case 'L': SPECIAL (6, 5, ENTRY_EXIT_LIST);
62 case 'M': SPECIAL (7, 0, SAVE_RESTORE_LIST);
63 case 'P': SPECIAL (0, 0, PC);
64 case 'R': MAPPED_REG (0, 0, GP, reg_31_map);
65 case 'S': MAPPED_REG (0, 0, GP, reg_29_map);
66 case 'X': REG (5, 0, GP);
67 case 'Y': MAPPED_REG (5, 3, GP, reg32r_map);
68 case 'Z': MAPPED_REG (3, 0, GP, reg_m16_map);
69
70 case 'a': JUMP (26, 0, 2);
f17ecb4b 71 case 'e': HINT (11, 0);
c3c07478
RS		 72 case 'i': JALX (26, 0, 2);
73 case 'l': SPECIAL (6, 5, ENTRY_EXIT_LIST);
74 case 'm': SPECIAL (7, 0, SAVE_RESTORE_LIST);
5284e471 75 case 's': HINT (3, 24);
0f35dbc4
RS		 76 case 'v': OPTIONAL_MAPPED_REG (3, 8, GP, reg_m16_map);
77 case 'w': OPTIONAL_MAPPED_REG (3, 5, GP, reg_m16_map);
c3c07478
RS		 78 case 'x': MAPPED_REG (3, 8, GP, reg_m16_map);
79 case 'y': MAPPED_REG (3, 5, GP, reg_m16_map);
80 case 'z': MAPPED_REG (3, 2, GP, reg_m16_map);
81 }
82
83 if (extended_p)
84 switch (type)
85 {
bdd15286 86 case '<': UINT (5, 22);
c3c07478
RS		 87 case '[': UINT (6, 0);
88 case ']': UINT (6, 0);
89
c3c07478 90 case '5': SINT (16, 0);
c3c07478
RS		 91 case '8': SINT (16, 0);
92
3ccad066
RS		 93 case 'A': PCREL (16, 0, TRUE, 0, 2, FALSE, FALSE);
94 case 'B': PCREL (16, 0, TRUE, 0, 3, FALSE, FALSE);
c3c07478
RS		 95 case 'C': SINT (16, 0);
96 case 'D': SINT (16, 0);
3ccad066 97 case 'E': PCREL (16, 0, TRUE, 0, 2, FALSE, FALSE);
d8722d76 98 case 'F': SINT (15, 0);
c3c07478
RS		 99 case 'H': SINT (16, 0);
100 case 'K': SINT (16, 0);
101 case 'U': UINT (16, 0);
102 case 'V': SINT (16, 0);
103 case 'W': SINT (16, 0);
104
105 case 'j': SINT (16, 0);
106 case 'k': SINT (16, 0);
107 case 'p': BRANCH (16, 0, 1);
108 case 'q': BRANCH (16, 0, 1);
109 }
110 else
111 switch (type)
112 {
113 case '<': INT_ADJ (3, 2, 8, 0, FALSE);
c3c07478
RS		 114 case '[': INT_ADJ (3, 2, 8, 0, FALSE);
115 case ']': INT_ADJ (3, 8, 8, 0, FALSE);
116
c3c07478 117 case '5': UINT (5, 0);
c3c07478
RS		 118 case '8': UINT (8, 0);
119
3ccad066
RS		 120 case 'A': PCREL (8, 0, FALSE, 2, 2, FALSE, FALSE);
121 case 'B': PCREL (5, 0, FALSE, 3, 3, FALSE, FALSE);
c3c07478
RS		 122 case 'C': INT_ADJ (8, 0, 255, 3, FALSE); /* (0 .. 255) << 3 */
123 case 'D': INT_ADJ (5, 0, 31, 3, FALSE); /* (0 .. 31) << 3 */
3ccad066 124 case 'E': PCREL (5, 0, FALSE, 2, 2, FALSE, FALSE);
d8722d76 125 case 'F': SINT (4, 0);
c3c07478
RS		 126 case 'H': INT_ADJ (5, 0, 31, 1, FALSE); /* (0 .. 31) << 1 */
127 case 'K': INT_ADJ (8, 0, 127, 3, FALSE); /* (-128 .. 127) << 3 */
128 case 'U': UINT (8, 0);
129 case 'V': INT_ADJ (8, 0, 255, 2, FALSE); /* (0 .. 255) << 2 */
130 case 'W': INT_ADJ (5, 0, 31, 2, FALSE); /* (0 .. 31) << 2 */
131
132 case 'j': SINT (5, 0);
133 case 'k': SINT (8, 0);
134 case 'p': BRANCH (8, 0, 1);
135 case 'q': BRANCH (11, 0, 1);
136 }
137 return 0;
138}
252b5132
RH		 139
140/* This is the opcodes table for the mips16 processor. The format of
141 this table is intentionally identical to the one in mips-opc.c.
142 However, the special letters that appear in the argument string are
143 different, and the table uses some different flags. */
144
145/* Use some short hand macros to keep down the length of the lines in
146 the opcodes table. */
147
6e3d1f07
MR		 148#define AL INSN2_ALIAS
149
252b5132 150#define UBD INSN_UNCOND_BRANCH_DELAY
252b5132 151
fc76e730
RS		 152#define WR_1 INSN_WRITE_1
153#define WR_2 INSN_WRITE_2
154#define RD_1 INSN_READ_1
155#define RD_2 INSN_READ_2
156#define RD_3 INSN_READ_3
157#define RD_4 INSN_READ_4
158#define MOD_1 (WR_1|RD_1)
159#define MOD_2 (WR_2|RD_2)
252b5132 160
fc76e730
RS		 161#define RD_T INSN_READ_GPR_24
162#define WR_T INSN_WRITE_GPR_24
163#define WR_31 INSN_WRITE_GPR_31
252b5132
RH		 164
165#define WR_HI INSN_WRITE_HI
166#define WR_LO INSN_WRITE_LO
167#define RD_HI INSN_READ_HI
168#define RD_LO INSN_READ_LO
169
bcd530a7
RS		 170#define NODS INSN_NO_DELAY_SLOT
171#define TRAP INSN_NO_DELAY_SLOT
252b5132 172
fc76e730
RS		 173#define RD_16 INSN2_READ_GPR_16
174#define RD_SP INSN2_READ_SP
175#define WR_SP INSN2_WRITE_SP
176#define MOD_SP (RD_SP|WR_SP)
26545944
RS		 177#define RD_31 INSN2_READ_GPR_31
178#define RD_PC INSN2_READ_PC
179#define UBR INSN2_UNCOND_BRANCH
180#define CBR INSN2_COND_BRANCH
181
0674ee5d
MR		 182#define SH INSN2_SHORT_ONLY
183
9b3f89ee 184#define I1 INSN_ISA1
252b5132 185#define I3 INSN_ISA3
9b3f89ee
TS		 186#define I32 INSN_ISA32
187#define I64 INSN_ISA64
188#define T3 INSN_3900
252b5132 189
b23da31b
NC		 190const struct mips_opcode mips16_opcodes[] =
191{
343fa690 192/* name, args, match, mask, pinfo, pinfo2, membership, ase, exclusions */
6e3d1f07
MR		 193{"nop", "", 0x6500, 0xffff, 0, SH|RD_16|AL, I1, 0, 0 }, /* move $0,$Z */
194{"la", "x,A", 0x0800, 0xf800, WR_1, RD_PC|AL, I1, 0, 0 },
a8d92fc6 195{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 },
d8722d76 196{"addiu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
fc76e730 197{"addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 },
26545944
RS		 198{"addiu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
199{"addiu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
fc76e730
RS		 200{"addiu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
201{"addiu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
0674ee5d 202{"addu", "z,v,y", 0xe001, 0xf803, WR_1|RD_2|RD_3, SH, I1, 0, 0 },
d8722d76 203{"addu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
fc76e730 204{"addu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 },
26545944
RS		 205{"addu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
206{"addu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
fc76e730
RS		 207{"addu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
208{"addu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
0674ee5d 209{"and", "x,y", 0xe80c, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
26545944 210{"b", "q", 0x1000, 0xf800, 0, UBR, I1, 0, 0 },
a8d92fc6
RS		 211{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, I1, 0, 0 },
212{"beq", "x,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 },
fc76e730 213{"beqz", "x,p", 0x2000, 0xf800, RD_1, CBR, I1, 0, 0 },
a8d92fc6
RS		 214{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 },
215{"bge", "x,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1, 0, 0 },
216{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1, 0, 0 },
217{"bgeu", "x,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1, 0, 0 },
218{"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0, I1, 0, 0 },
219{"bgt", "x,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1, 0, 0 },
220{"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1, 0, 0 },
221{"bgtu", "x,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1, 0, 0 },
222{"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0, I1, 0, 0 },
223{"ble", "x,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1, 0, 0 },
224{"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1, 0, 0 },
225{"bleu", "x,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1, 0, 0 },
226{"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0, I1, 0, 0 },
227{"blt", "x,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1, 0, 0 },
228{"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1, 0, 0 },
229{"bltu", "x,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1, 0, 0 },
230{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, I1, 0, 0 },
231{"bne", "x,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 },
fc76e730 232{"bnez", "x,p", 0x2800, 0xf800, RD_1, CBR, I1, 0, 0 },
0674ee5d 233{"break", "6", 0xe805, 0xf81f, TRAP, SH, I1, 0, 0 },
26545944
RS		 234{"bteqz", "p", 0x6000, 0xff00, RD_T, CBR, I1, 0, 0 },
235{"btnez", "p", 0x6100, 0xff00, RD_T, CBR, I1, 0, 0 },
fc76e730 236{"cmpi", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
0674ee5d 237{"cmp", "x,y", 0xe80a, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 },
fc76e730 238{"cmp", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
6e3d1f07 239{"dla", "y,E", 0xfe00, 0xff00, WR_1, RD_PC|AL, I3, 0, 0 },
d8722d76 240{"daddiu", "y,x,F", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
fc76e730 241{"daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
26545944
RS		 242{"daddiu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
243{"daddiu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
fc76e730
RS		 244{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
245{"daddiu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 },
0674ee5d 246{"daddu", "z,v,y", 0xe000, 0xf803, WR_1|RD_2|RD_3, SH, I3, 0, 0 },
d8722d76 247{"daddu", "y,x,F", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
fc76e730 248{"daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
26545944
RS		 249{"daddu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
250{"daddu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
fc76e730
RS		 251{"daddu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
252{"daddu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 },
d8722d76 253{"ddiv", ".,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
4ebce1a0 254{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, 0 },
d8722d76 255{"ddivu", ".,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
4ebce1a0 256{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, 0 },
d8722d76 257{"div", ".,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
a8d92fc6 258{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 },
d8722d76 259{"divu", ".,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
a8d92fc6
RS		 260{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, 0 },
261{"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, 0 },
0674ee5d
MR		 262{"dmult", "x,y", 0xe81c, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I3, 0, 0 },
263{"dmultu", "x,y", 0xe81d, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I3, 0, 0 },
d8722d76 264{"drem", ".,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
4ebce1a0 265{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, 0 },
d8722d76 266{"dremu", ".,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
4ebce1a0 267{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, 0 },
0674ee5d 268{"dsllv", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
fc76e730 269{"dsll", "x,w,[", 0x3001, 0xf803, WR_1|RD_2, 0, I3, 0, 0 },
0674ee5d
MR		 270{"dsll", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
271{"dsrav", "y,x", 0xe817, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
fc76e730 272{"dsra", "y,]", 0xe813, 0xf81f, MOD_1, 0, I3, 0, 0 },
0674ee5d
MR		 273{"dsra", "y,x", 0xe817, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
274{"dsrlv", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
fc76e730 275{"dsrl", "y,]", 0xe808, 0xf81f, MOD_1, 0, I3, 0, 0 },
0674ee5d
MR		 276{"dsrl", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
277{"dsubu", "z,v,y", 0xe002, 0xf803, WR_1|RD_2|RD_3, SH, I3, 0, 0 },
4ebce1a0
MR		 278{"dsubu", "y,x,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 },
279{"dsubu", "y,I", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I3, 0, 0 },
0674ee5d
MR		 280{"exit", "L", 0xed09, 0xff1f, TRAP, SH, I1, 0, 0 },
281{"exit", "L", 0xee09, 0xff1f, TRAP, SH, I1, 0, 0 },
282{"exit", "", 0xef09, 0xffff, TRAP, SH, I1, 0, 0 },
283{"exit", "L", 0xef09, 0xff1f, TRAP, SH, I1, 0, 0 },
284{"entry", "", 0xe809, 0xffff, TRAP, SH, I1, 0, 0 },
285{"entry", "l", 0xe809, 0xf81f, TRAP, SH, I1, 0, 0 },
286{"jalr", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 },
287{"jalr", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 },
288{"jal", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 },
289{"jal", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 },
7fd53920
MR		 290{"jal", "a", 0x18000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 },
291{"jalx", "i", 0x1c000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 },
0674ee5d
MR		 292{"jr", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 },
293{"jr", "R", 0xe820, 0xffff, UBD, SH|RD_31, I1, 0, 0 },
294{"j", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 },
295{"j", "R", 0xe820, 0xffff, UBD, SH|RD_31, I1, 0, 0 },
63e014fc
MR		 296/* MIPS16e compact jumps. We keep them near the ordinary jumps
297 so that we easily find them when converting a normal jump
298 to a compact one. */
0674ee5d
MR		 299{"jalrc", "x", 0xe8c0, 0xf8ff, RD_1|WR_31|NODS, SH|UBR, I32, 0, 0 },
300{"jalrc", "R,x", 0xe8c0, 0xf8ff, RD_2|WR_31|NODS, SH|UBR, I32, 0, 0 },
301{"jrc", "x", 0xe880, 0xf8ff, RD_1|NODS, SH|UBR, I32, 0, 0 },
302{"jrc", "R", 0xe8a0, 0xffff, NODS, SH|RD_31|UBR, I32, 0, 0 },
fc76e730
RS		 303{"lb", "y,5(x)", 0x8000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
304{"lbu", "y,5(x)", 0xa000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
305{"ld", "y,D(x)", 0x3800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 },
6e3d1f07 306{"ld", "y,B", 0xfc00, 0xff00, WR_1, RD_PC|AL, I3, 0, 0 },
fc76e730
RS		 307{"ld", "y,D(P)", 0xfc00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
308{"ld", "y,D(S)", 0xf800, 0xff00, WR_1, RD_SP, I3, 0, 0 },
309{"lh", "y,H(x)", 0x8800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
310{"lhu", "y,H(x)", 0xa800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
311{"li", "x,U", 0x6800, 0xf800, WR_1, 0, I1, 0, 0 },
312{"lw", "y,W(x)", 0x9800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
6e3d1f07 313{"lw", "x,A", 0xb000, 0xf800, WR_1, RD_PC|AL, I1, 0, 0 },
fc76e730
RS		 314{"lw", "x,V(P)", 0xb000, 0xf800, WR_1, RD_PC, I1, 0, 0 },
315{"lw", "x,V(S)", 0x9000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
316{"lwu", "y,W(x)", 0xb800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 },
0674ee5d
MR		 317{"mfhi", "x", 0xe810, 0xf8ff, WR_1|RD_HI, SH, I1, 0, 0 },
318{"mflo", "x", 0xe812, 0xf8ff, WR_1|RD_LO, SH, I1, 0, 0 },
319{"move", "y,X", 0x6700, 0xff00, WR_1|RD_2, SH, I1, 0, 0 },
320{"move", "Y,Z", 0x6500, 0xff00, WR_1|RD_2, SH, I1, 0, 0 },
a8d92fc6 321{"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0, I1, 0, 0 },
0674ee5d
MR		 322{"mult", "x,y", 0xe818, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I1, 0, 0 },
323{"multu", "x,y", 0xe819, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I1, 0, 0 },
324{"neg", "x,w", 0xe80b, 0xf81f, WR_1|RD_2, SH, I1, 0, 0 },
325{"not", "x,w", 0xe80f, 0xf81f, WR_1|RD_2, SH, I1, 0, 0 },
326{"or", "x,y", 0xe80d, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
d8722d76 327{"rem", ".,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
a8d92fc6 328{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, 0 },
d8722d76 329{"remu", ".,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
a8d92fc6 330{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 },
fc76e730
RS		 331{"sb", "y,5(x)", 0xc000, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
332{"sd", "y,D(x)", 0x7800, 0xf800, RD_1|RD_3, 0, I3, 0, 0 },
353abf7c 333{"sd", "y,D(S)", 0xf900, 0xff00, RD_1, RD_SP, I3, 0, 0 },
c97dda72 334{"sd", "R,C(S)", 0xfa00, 0xff00, 0, RD_31|RD_SP, I3, 0, 0 },
fc76e730 335{"sh", "y,H(x)", 0xc800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
0674ee5d 336{"sllv", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
fc76e730 337{"sll", "x,w,<", 0x3000, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },
0674ee5d 338{"sll", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
fc76e730 339{"slti", "x,8", 0x5000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
0674ee5d 340{"slt", "x,y", 0xe802, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 },
fc76e730
RS		 341{"slt", "x,8", 0x5000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
342{"sltiu", "x,8", 0x5800, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
0674ee5d 343{"sltu", "x,y", 0xe803, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 },
fc76e730 344{"sltu", "x,8", 0x5800, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
0674ee5d 345{"srav", "y,x", 0xe807, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
fc76e730 346{"sra", "x,w,<", 0x3003, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },
0674ee5d
MR		 347{"sra", "y,x", 0xe807, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
348{"srlv", "y,x", 0xe806, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
fc76e730 349{"srl", "x,w,<", 0x3002, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },
0674ee5d
MR		 350{"srl", "y,x", 0xe806, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
351{"subu", "z,v,y", 0xe003, 0xf803, WR_1|RD_2|RD_3, SH, I1, 0, 0 },
a8d92fc6
RS		 352{"subu", "y,x,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1, 0, 0 },
353{"subu", "x,I", 0, (int) M_SUBU_I_2, INSN_MACRO, 0, I1, 0, 0 },
fc76e730
RS		 354{"sw", "y,W(x)", 0xd800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
355{"sw", "x,V(S)", 0xd000, 0xf800, RD_1, RD_SP, I1, 0, 0 },
356{"sw", "R,V(S)", 0x6200, 0xff00, 0, RD_31|RD_SP, I1, 0, 0 },
0674ee5d 357{"xor", "x,y", 0xe80e, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
63e014fc 358 /* MIPS16e additions; see above for compact jumps. */
26545944 359{"restore", "M", 0x6400, 0xff80, WR_31|NODS, MOD_SP, I32, 0, 0 },
fc76e730 360{"save", "m", 0x6480, 0xff80, NODS, RD_31|MOD_SP, I32, 0, 0 },
0674ee5d
MR		 361{"sdbbp", "6", 0xe801, 0xf81f, TRAP, SH, I32, 0, 0 },
362{"seb", "x", 0xe891, 0xf8ff, MOD_1, SH, I32, 0, 0 },
363{"seh", "x", 0xe8b1, 0xf8ff, MOD_1, SH, I32, 0, 0 },
364{"sew", "x", 0xe8d1, 0xf8ff, MOD_1, SH, I64, 0, 0 },
365{"zeb", "x", 0xe811, 0xf8ff, MOD_1, SH, I32, 0, 0 },
366{"zeh", "x", 0xe831, 0xf8ff, MOD_1, SH, I32, 0, 0 },
367{"zew", "x", 0xe851, 0xf8ff, MOD_1, SH, I64, 0, 0 },
5284e471
MR		 368 /* Place asmacro at the bottom so that it catches any implementation
369 specific macros that didn't match anything. */
370{"asmacro", "s,0,1,2,3,4", 0xf000e000, 0xf800f800, 0, 0, I32, 0, 0 },
7fd53920
MR		 371 /* Place EXTEND last so that it catches any prefix that didn't match
372 anything. */
0674ee5d 373{"extend", "e", 0xf000, 0xf800, NODS, SH, I1, 0, 0 },
252b5132
RH		 374};
375
376const int bfd_mips16_num_opcodes =
377 ((sizeof mips16_opcodes) / (sizeof (mips16_opcodes[0])));
GDB Binutils - Deliverables
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