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2005-10-28 Dave Brolley <brolley@redhat.com>
[deliverable/binutils-gdb.git] / opcodes / ms1-desc.h
CommitLineData
ac188222
DB		 1/* CPU data header for ms1.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5Copyright 1996-2005 Free Software Foundation, Inc.
6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2151 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22
23*/
24
25#ifndef MS1_CPU_H
26#define MS1_CPU_H
27
28#define CGEN_ARCH ms1
29
30/* Given symbol S, return ms1_cgen_<S>. */
31#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
32#define CGEN_SYM(s) ms1##_cgen_##s
33#else
34#define CGEN_SYM(s) ms1/**/_cgen_/**/s
35#endif
36
37
38/* Selected cpu families. */
39#define HAVE_CPU_MS1BF
40#define HAVE_CPU_MS1_003BF
41
42#define CGEN_INSN_LSB0_P 1
43
44/* Minimum size of any insn (in bytes). */
45#define CGEN_MIN_INSN_SIZE 4
46
47/* Maximum size of any insn (in bytes). */
48#define CGEN_MAX_INSN_SIZE 4
49
50#define CGEN_INT_INSN_P 1
51
52/* Maximum number of syntax elements in an instruction. */
53#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 40
54
55/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
56 e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
57 we can't hash on everything up to the space. */
58#define CGEN_MNEMONIC_OPERANDS
59
60/* Maximum number of fields in an instruction. */
61#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 14
62
63/* Enums. */
64
65/* Enum declaration for msys enums. */
66typedef enum insn_msys {
67 MSYS_NO, MSYS_YES
68} INSN_MSYS;
69
70/* Enum declaration for opc enums. */
71typedef enum insn_opc {
72 OPC_ADD = 0, OPC_ADDU = 1, OPC_SUB = 2, OPC_SUBU = 3
73 , OPC_MUL = 4, OPC_AND = 8, OPC_OR = 9, OPC_XOR = 10
74 , OPC_NAND = 11, OPC_NOR = 12, OPC_XNOR = 13, OPC_LDUI = 14
75 , OPC_LSL = 16, OPC_LSR = 17, OPC_ASR = 18, OPC_BRLT = 24
76 , OPC_BRLE = 25, OPC_BREQ = 26, OPC_JMP = 27, OPC_JAL = 28
77 , OPC_BRNEQ = 29, OPC_DBNZ = 30, OPC_LDW = 32, OPC_STW = 33
78 , OPC_EI = 48, OPC_DI = 49, OPC_SI = 50, OPC_RETI = 51
79 , OPC_BREAK = 52, OPC_IFLUSH = 53
80} INSN_OPC;
81
82/* Enum declaration for msopc enums. */
83typedef enum insn_msopc {
84 MSOPC_LDCTXT, MSOPC_LDFB, MSOPC_STFB, MSOPC_FBCB
85 , MSOPC_MFBCB, MSOPC_FBCCI, MSOPC_FBRCI, MSOPC_FBCRI
86 , MSOPC_FBRRI, MSOPC_MFBCCI, MSOPC_MFBRCI, MSOPC_MFBCRI
87 , MSOPC_MFBRRI, MSOPC_FBCBDR, MSOPC_RCFBCB, MSOPC_MRCFBCB
88 , MSOPC_CBCAST, MSOPC_DUPCBCAST, MSOPC_WFBI, MSOPC_WFB
89 , MSOPC_RCRISC, MSOPC_FBCBINC, MSOPC_RCXMODE, MSOPC_INTLVR
90 , MSOPC_WFBINC, MSOPC_MWFBINC, MSOPC_WFBINCR, MSOPC_MWFBINCR
91 , MSOPC_FBCBINCS, MSOPC_MFBCBINCS, MSOPC_FBCBINCRS, MSOPC_MFBCBINCRS
92} INSN_MSOPC;
93
94/* Enum declaration for imm enums. */
95typedef enum insn_imm {
96 IMM_NO, IMM_YES
97} INSN_IMM;
98
99/* Enum declaration for . */
100typedef enum msys_syms {
101 H_NIL_DUP = 1, H_NIL_XX = 0
102} MSYS_SYMS;
103
104/* Attributes. */
105
106/* Enum declaration for machine type selection. */
107typedef enum mach_attr {
108 MACH_BASE, MACH_MS1, MACH_MS1_003, MACH_MAX
109} MACH_ATTR;
110
111/* Enum declaration for instruction set selection. */
112typedef enum isa_attr {
113 ISA_MS1, ISA_MAX
114} ISA_ATTR;
115
116/* Number of architecture variants. */
117#define MAX_ISAS 1
118#define MAX_MACHS ((int) MACH_MAX)
119
120/* Ifield support. */
121
122/* Ifield attribute indices. */
123
124/* Enum declaration for cgen_ifld attrs. */
125typedef enum cgen_ifld_attr {
126 CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
127 , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
128 , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
129} CGEN_IFLD_ATTR;
130
131/* Number of non-boolean elements in cgen_ifld_attr. */
132#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
133
134/* Enum declaration for ms1 ifield types. */
135typedef enum ifield_type {
136 MS1_F_NIL, MS1_F_ANYOF, MS1_F_MSYS, MS1_F_OPC
137 , MS1_F_IMM, MS1_F_UU24, MS1_F_SR1, MS1_F_SR2
138 , MS1_F_DR, MS1_F_DRRR, MS1_F_IMM16U, MS1_F_IMM16S
139 , MS1_F_IMM16A, MS1_F_UU4A, MS1_F_UU4B, MS1_F_UU12
140 , MS1_F_UU16, MS1_F_MSOPC, MS1_F_UU_26_25, MS1_F_MASK
141 , MS1_F_BANKADDR, MS1_F_RDA, MS1_F_UU_2_25, MS1_F_RBBC
142 , MS1_F_PERM, MS1_F_MODE, MS1_F_UU_1_24, MS1_F_WR
143 , MS1_F_FBINCR, MS1_F_UU_2_23, MS1_F_XMODE, MS1_F_A23
144 , MS1_F_MASK1, MS1_F_CR, MS1_F_TYPE, MS1_F_INCAMT
145 , MS1_F_CBS, MS1_F_UU_1_19, MS1_F_BALL, MS1_F_COLNUM
146 , MS1_F_BRC, MS1_F_INCR, MS1_F_FBDISP, MS1_F_UU_4_15
147 , MS1_F_LENGTH, MS1_F_UU_1_15, MS1_F_RC, MS1_F_RCNUM
148 , MS1_F_ROWNUM, MS1_F_CBX, MS1_F_ID, MS1_F_SIZE
149 , MS1_F_ROWNUM1, MS1_F_UU_3_11, MS1_F_RC1, MS1_F_CCB
150 , MS1_F_CBRB, MS1_F_CDB, MS1_F_ROWNUM2, MS1_F_CELL
151 , MS1_F_UU_3_9, MS1_F_CONTNUM, MS1_F_UU_1_6, MS1_F_DUP
152 , MS1_F_RC2, MS1_F_CTXDISP, MS1_F_MSYSFRSR2, MS1_F_BRC2
153 , MS1_F_BALL2, MS1_F_MAX
154} IFIELD_TYPE;
155
156#define MAX_IFLD ((int) MS1_F_MAX)
157
158/* Hardware attribute indices. */
159
160/* Enum declaration for cgen_hw attrs. */
161typedef enum cgen_hw_attr {
162 CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
163 , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
164} CGEN_HW_ATTR;
165
166/* Number of non-boolean elements in cgen_hw_attr. */
167#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
168
169/* Enum declaration for ms1 hardware types. */
170typedef enum cgen_hw_type {
171 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
172 , HW_H_IADDR, HW_H_SPR, HW_H_PC, HW_MAX
173} CGEN_HW_TYPE;
174
175#define MAX_HW ((int) HW_MAX)
176
177/* Operand attribute indices. */
178
179/* Enum declaration for cgen_operand attrs. */
180typedef enum cgen_operand_attr {
181 CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
182 , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
183 , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
184} CGEN_OPERAND_ATTR;
185
186/* Number of non-boolean elements in cgen_operand_attr. */
187#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
188
189/* Enum declaration for ms1 operand types. */
190typedef enum cgen_operand_type {
191 MS1_OPERAND_PC, MS1_OPERAND_FRSR1, MS1_OPERAND_FRSR2, MS1_OPERAND_FRDR
192 , MS1_OPERAND_FRDRRR, MS1_OPERAND_IMM16, MS1_OPERAND_IMM16Z, MS1_OPERAND_IMM16O
193 , MS1_OPERAND_RC, MS1_OPERAND_RCNUM, MS1_OPERAND_CONTNUM, MS1_OPERAND_RBBC
194 , MS1_OPERAND_COLNUM, MS1_OPERAND_ROWNUM, MS1_OPERAND_ROWNUM1, MS1_OPERAND_ROWNUM2
195 , MS1_OPERAND_RC1, MS1_OPERAND_RC2, MS1_OPERAND_CBRB, MS1_OPERAND_CELL
196 , MS1_OPERAND_DUP, MS1_OPERAND_CTXDISP, MS1_OPERAND_FBDISP, MS1_OPERAND_TYPE
197 , MS1_OPERAND_MASK, MS1_OPERAND_BANKADDR, MS1_OPERAND_INCAMT, MS1_OPERAND_XMODE
198 , MS1_OPERAND_MASK1, MS1_OPERAND_BALL, MS1_OPERAND_BRC, MS1_OPERAND_RDA
199 , MS1_OPERAND_WR, MS1_OPERAND_BALL2, MS1_OPERAND_BRC2, MS1_OPERAND_PERM
200 , MS1_OPERAND_A23, MS1_OPERAND_CR, MS1_OPERAND_CBS, MS1_OPERAND_INCR
201 , MS1_OPERAND_LENGTH, MS1_OPERAND_CBX, MS1_OPERAND_CCB, MS1_OPERAND_CDB
202 , MS1_OPERAND_MODE, MS1_OPERAND_ID, MS1_OPERAND_SIZE, MS1_OPERAND_FBINCR
203 , MS1_OPERAND_MAX
204} CGEN_OPERAND_TYPE;
205
206/* Number of operands types. */
207#define MAX_OPERANDS 48
208
209/* Maximum number of operands referenced by any insn. */
210#define MAX_OPERAND_INSTANCES 8
211
212/* Insn attribute indices. */
213
214/* Enum declaration for cgen_insn attrs. */
215typedef enum cgen_insn_attr {
216 CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
217 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
218 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_LOAD_DELAY, CGEN_INSN_MEMORY_ACCESS
219 , CGEN_INSN_AL_INSN, CGEN_INSN_IO_INSN, CGEN_INSN_BR_INSN, CGEN_INSN_USES_FRDR
220 , CGEN_INSN_USES_FRDRRR, CGEN_INSN_USES_FRSR1, CGEN_INSN_USES_FRSR2, CGEN_INSN_SKIPA
221 , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
222} CGEN_INSN_ATTR;
223
224/* Number of non-boolean elements in cgen_insn_attr. */
225#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
226
227/* cgen.h uses things we just defined. */
228#include "opcode/cgen.h"
229
230extern const struct cgen_ifld ms1_cgen_ifld_table[];
231
232/* Attributes. */
233extern const CGEN_ATTR_TABLE ms1_cgen_hardware_attr_table[];
234extern const CGEN_ATTR_TABLE ms1_cgen_ifield_attr_table[];
235extern const CGEN_ATTR_TABLE ms1_cgen_operand_attr_table[];
236extern const CGEN_ATTR_TABLE ms1_cgen_insn_attr_table[];
237
238/* Hardware decls. */
239
240extern CGEN_KEYWORD ms1_cgen_opval_h_spr;
241
242extern const CGEN_HW_ENTRY ms1_cgen_hw_table[];
243
244
245
246#endif /* MS1_CPU_H */
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