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2005-06-15 Dave Brolley <brolley@redhat.com>
[deliverable/binutils-gdb.git] / opcodes / ms1-opc.c
CommitLineData
ac188222
DB		 1/* Instruction opcode table for ms1.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5Copyright 1996-2005 Free Software Foundation, Inc.
6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2151 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22
23*/
24
25#include "sysdep.h"
26#include "ansidecl.h"
27#include "bfd.h"
28#include "symcat.h"
29#include "ms1-desc.h"
30#include "ms1-opc.h"
31#include "libiberty.h"
32
33/* -- opc.c */
34#include "safe-ctype.h"
35
36/* Special check to ensure that instruction exists for given machine. */
37
38int
39ms1_cgen_insn_supported (CGEN_CPU_DESC cd,
40 const CGEN_INSN *insn)
41{
42 int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
43
44 /* No mach attribute? Assume it's supported for all machs. */
45 if (machs == 0)
46 return 1;
47
48 return ((machs & cd->machs) != 0);
49}
50
51/* A better hash function for instruction mnemonics. */
52
53unsigned int
54ms1_asm_hash (const char* insn)
55{
56 unsigned int hash;
57 const char* m = insn;
58
59 for (hash = 0; *m && ! ISSPACE (*m); m++)
60 hash = (hash * 23) ^ (0x1F & TOLOWER (*m));
61
62 /* printf ("%s %d\n", insn, (hash % CGEN_ASM_HASH_SIZE)); */
63
64 return hash % CGEN_ASM_HASH_SIZE;
65}
66
67\f
68/* -- asm.c */
69/* The hash functions are recorded here to help keep assembler code out of
70 the disassembler and vice versa. */
71
72static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
73static unsigned int asm_hash_insn PARAMS ((const char *));
74static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
75static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
76
77/* Instruction formats. */
78
79#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
80#define F(f) & ms1_cgen_ifld_table[MS1_##f]
81#else
82#define F(f) & ms1_cgen_ifld_table[MS1_/**/f]
83#endif
84static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = {
85 0, 0, 0x0, { { 0 } }
86};
87
88static const CGEN_IFMT ifmt_add ATTRIBUTE_UNUSED = {
89 32, 32, 0xff000fff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_DRRR) }, { F (F_UU12) }, { 0 } }
90};
91
92static const CGEN_IFMT ifmt_addi ATTRIBUTE_UNUSED = {
93 32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_DR) }, { F (F_IMM16S) }, { 0 } }
94};
95
96static const CGEN_IFMT ifmt_addui ATTRIBUTE_UNUSED = {
97 32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_DR) }, { F (F_IMM16U) }, { 0 } }
98};
99
100static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = {
101 32, 32, 0xffffffff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU24) }, { 0 } }
102};
103
104static const CGEN_IFMT ifmt_ldui ATTRIBUTE_UNUSED = {
105 32, 32, 0xfff00000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU4B) }, { F (F_DR) }, { F (F_IMM16U) }, { 0 } }
106};
107
108static const CGEN_IFMT ifmt_brlt ATTRIBUTE_UNUSED = {
109 32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_IMM16S) }, { 0 } }
110};
111
112static const CGEN_IFMT ifmt_jmp ATTRIBUTE_UNUSED = {
113 32, 32, 0xffff0000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU4B) }, { F (F_UU4A) }, { F (F_IMM16S) }, { 0 } }
114};
115
116static const CGEN_IFMT ifmt_jal ATTRIBUTE_UNUSED = {
117 32, 32, 0xff0f0fff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_UU4A) }, { F (F_DRRR) }, { F (F_UU12) }, { 0 } }
118};
119
120static const CGEN_IFMT ifmt_dbnz ATTRIBUTE_UNUSED = {
121 32, 32, 0xff0f0000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_UU4A) }, { F (F_IMM16S) }, { 0 } }
122};
123
124static const CGEN_IFMT ifmt_ei ATTRIBUTE_UNUSED = {
125 32, 32, 0xffffffff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU4B) }, { F (F_UU4A) }, { F (F_UU16) }, { 0 } }
126};
127
128static const CGEN_IFMT ifmt_si ATTRIBUTE_UNUSED = {
129 32, 32, 0xffff0fff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU4B) }, { F (F_UU4A) }, { F (F_DRRR) }, { F (F_UU12) }, { 0 } }
130};
131
132static const CGEN_IFMT ifmt_reti ATTRIBUTE_UNUSED = {
133 32, 32, 0xff0fffff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_UU4A) }, { F (F_UU16) }, { 0 } }
134};
135
136static const CGEN_IFMT ifmt_stw ATTRIBUTE_UNUSED = {
137 32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_IMM16S) }, { 0 } }
138};
139
140static const CGEN_IFMT ifmt_ldctxt ATTRIBUTE_UNUSED = {
141 32, 32, 0xff000e00, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_UU_2_25) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_RC) }, { F (F_RCNUM) }, { F (F_UU_3_11) }, { F (F_CONTNUM) }, { 0 } }
142};
143
144static const CGEN_IFMT ifmt_ldfb ATTRIBUTE_UNUSED = {
145 32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_UU_2_25) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_IMM16U) }, { 0 } }
146};
147
148static const CGEN_IFMT ifmt_fbcb ATTRIBUTE_UNUSED = {
149 32, 32, 0xfc00f000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_BALL) }, { F (F_BRC) }, { F (F_UU_4_15) }, { F (F_RC) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
150};
151
152static const CGEN_IFMT ifmt_mfbcb ATTRIBUTE_UNUSED = {
153 32, 32, 0xfc00f000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_UU_4_15) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
154};
155
156static const CGEN_IFMT ifmt_fbcci ATTRIBUTE_UNUSED = {
157 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_BALL) }, { F (F_BRC) }, { F (F_FBDISP) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
158};
159
160static const CGEN_IFMT ifmt_mfbcci ATTRIBUTE_UNUSED = {
161 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_FBDISP) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
162};
163
164static const CGEN_IFMT ifmt_fbcbdr ATTRIBUTE_UNUSED = {
165 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_BALL2) }, { F (F_BRC2) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
166};
167
168static const CGEN_IFMT ifmt_rcfbcb ATTRIBUTE_UNUSED = {
169 32, 32, 0xfcc08000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_UU_2_23) }, { F (F_TYPE) }, { F (F_BALL) }, { F (F_BRC) }, { F (F_UU_1_15) }, { F (F_ROWNUM) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
170};
171
172static const CGEN_IFMT ifmt_mrcfbcb ATTRIBUTE_UNUSED = {
173 32, 32, 0xfcc08000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_UU_2_23) }, { F (F_TYPE) }, { F (F_SR2) }, { F (F_UU_1_15) }, { F (F_ROWNUM) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
174};
175
176static const CGEN_IFMT ifmt_cbcast ATTRIBUTE_UNUSED = {
177 32, 32, 0xfc000380, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_MASK) }, { F (F_UU_3_9) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } }
178};
179
180static const CGEN_IFMT ifmt_dupcbcast ATTRIBUTE_UNUSED = {
181 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_MASK) }, { F (F_CELL) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } }
182};
183
184static const CGEN_IFMT ifmt_wfbi ATTRIBUTE_UNUSED = {
185 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_BANKADDR) }, { F (F_ROWNUM1) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
186};
187
188static const CGEN_IFMT ifmt_wfb ATTRIBUTE_UNUSED = {
189 32, 32, 0xff000040, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_UU_2_25) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_FBDISP) }, { F (F_ROWNUM2) }, { F (F_UU_1_6) }, { F (F_CTXDISP) }, { 0 } }
190};
191
192static const CGEN_IFMT ifmt_rcrisc ATTRIBUTE_UNUSED = {
193 32, 32, 0xfc080000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_UU_1_19) }, { F (F_COLNUM) }, { F (F_DRRR) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
194};
195
196static const CGEN_IFMT ifmt_fbcbinc ATTRIBUTE_UNUSED = {
197 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_INCAMT) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
198};
199
200static const CGEN_IFMT ifmt_rcxmode ATTRIBUTE_UNUSED = {
201 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_XMODE) }, { F (F_MASK1) }, { F (F_SR2) }, { F (F_FBDISP) }, { F (F_ROWNUM2) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } }
202};
203
204static const CGEN_IFMT ifmt_interleaver ATTRIBUTE_UNUSED = {
205 32, 32, 0xfc008000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_MODE) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_UU_1_15) }, { F (F_ID) }, { F (F_SIZE) }, { 0 } }
206};
207
208static const CGEN_IFMT ifmt_wfbinc ATTRIBUTE_UNUSED = {
209 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_FBINCR) }, { F (F_BALL) }, { F (F_COLNUM) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
210};
211
212static const CGEN_IFMT ifmt_mwfbinc ATTRIBUTE_UNUSED = {
213 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_FBINCR) }, { F (F_SR2) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
214};
215
216static const CGEN_IFMT ifmt_wfbincr ATTRIBUTE_UNUSED = {
217 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_SR1) }, { F (F_BALL) }, { F (F_COLNUM) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
218};
219
220static const CGEN_IFMT ifmt_mwfbincr ATTRIBUTE_UNUSED = {
221 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
222};
223
224static const CGEN_IFMT ifmt_fbcbincs ATTRIBUTE_UNUSED = {
225 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_PERM) }, { F (F_A23) }, { F (F_CR) }, { F (F_CBS) }, { F (F_INCR) }, { F (F_CCB) }, { F (F_CDB) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
226};
227
228static const CGEN_IFMT ifmt_mfbcbincs ATTRIBUTE_UNUSED = {
229 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_PERM) }, { F (F_SR1) }, { F (F_CBS) }, { F (F_INCR) }, { F (F_CCB) }, { F (F_CDB) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
230};
231
232static const CGEN_IFMT ifmt_fbcbincrs ATTRIBUTE_UNUSED = {
233 32, 32, 0xfc008000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_PERM) }, { F (F_SR1) }, { F (F_BALL) }, { F (F_COLNUM) }, { F (F_UU_1_15) }, { F (F_CBX) }, { F (F_CCB) }, { F (F_CDB) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
234};
235
236static const CGEN_IFMT ifmt_mfbcbincrs ATTRIBUTE_UNUSED = {
237 32, 32, 0xfc008000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_PERM) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_UU_1_15) }, { F (F_CBX) }, { F (F_CCB) }, { F (F_CDB) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
238};
239
240#undef F
241
242#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
243#define A(a) (1 << CGEN_INSN_##a)
244#else
245#define A(a) (1 << CGEN_INSN_/**/a)
246#endif
247#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
248#define OPERAND(op) MS1_OPERAND_##op
249#else
250#define OPERAND(op) MS1_OPERAND_/**/op
251#endif
252#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
253#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
254
255/* The instruction table. */
256
257static const CGEN_OPCODE ms1_cgen_insn_opcode_table[MAX_INSNS] =
258{
259 /* Special null first entry.
260 A `num' value of zero is thus invalid.
261 Also, the special `invalid' insn resides here. */
262 { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
263/* add $frdrrr,$frsr1,$frsr2 */
264 {
265 { 0, 0, 0, 0 },
266 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
267 & ifmt_add, { 0x0 }
268 },
269/* addu $frdrrr,$frsr1,$frsr2 */
270 {
271 { 0, 0, 0, 0 },
272 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
273 & ifmt_add, { 0x2000000 }
274 },
275/* addi $frdr,$frsr1,#$imm16 */
276 {
277 { 0, 0, 0, 0 },
278 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } },
279 & ifmt_addi, { 0x1000000 }
280 },
281/* addui $frdr,$frsr1,#$imm16z */
282 {
283 { 0, 0, 0, 0 },
284 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } },
285 & ifmt_addui, { 0x3000000 }
286 },
287/* sub $frdrrr,$frsr1,$frsr2 */
288 {
289 { 0, 0, 0, 0 },
290 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
291 & ifmt_add, { 0x4000000 }
292 },
293/* subu $frdrrr,$frsr1,$frsr2 */
294 {
295 { 0, 0, 0, 0 },
296 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
297 & ifmt_add, { 0x6000000 }
298 },
299/* subi $frdr,$frsr1,#$imm16 */
300 {
301 { 0, 0, 0, 0 },
302 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } },
303 & ifmt_addi, { 0x5000000 }
304 },
305/* subui $frdr,$frsr1,#$imm16z */
306 {
307 { 0, 0, 0, 0 },
308 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } },
309 & ifmt_addui, { 0x7000000 }
310 },
311/* mul $frdrrr,$frsr1,$frsr2 */
312 {
313 { 0, 0, 0, 0 },
314 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
315 & ifmt_add, { 0x8000000 }
316 },
317/* muli $frdr,$frsr1,#$imm16 */
318 {
319 { 0, 0, 0, 0 },
320 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } },
321 & ifmt_addi, { 0x9000000 }
322 },
323/* and $frdrrr,$frsr1,$frsr2 */
324 {
325 { 0, 0, 0, 0 },
326 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
327 & ifmt_add, { 0x10000000 }
328 },
329/* andi $frdr,$frsr1,#$imm16z */
330 {
331 { 0, 0, 0, 0 },
332 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } },
333 & ifmt_addui, { 0x11000000 }
334 },
335/* or $frdrrr,$frsr1,$frsr2 */
336 {
337 { 0, 0, 0, 0 },
338 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
339 & ifmt_add, { 0x12000000 }
340 },
341/* nop */
342 {
343 { 0, 0, 0, 0 },
344 { { MNEM, 0 } },
345 & ifmt_nop, { 0x12000000 }
346 },
347/* ori $frdr,$frsr1,#$imm16z */
348 {
349 { 0, 0, 0, 0 },
350 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } },
351 & ifmt_addui, { 0x13000000 }
352 },
353/* xor $frdrrr,$frsr1,$frsr2 */
354 {
355 { 0, 0, 0, 0 },
356 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
357 & ifmt_add, { 0x14000000 }
358 },
359/* xori $frdr,$frsr1,#$imm16z */
360 {
361 { 0, 0, 0, 0 },
362 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } },
363 & ifmt_addui, { 0x15000000 }
364 },
365/* nand $frdrrr,$frsr1,$frsr2 */
366 {
367 { 0, 0, 0, 0 },
368 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
369 & ifmt_add, { 0x16000000 }
370 },
371/* nandi $frdr,$frsr1,#$imm16z */
372 {
373 { 0, 0, 0, 0 },
374 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } },
375 & ifmt_addui, { 0x17000000 }
376 },
377/* nor $frdrrr,$frsr1,$frsr2 */
378 {
379 { 0, 0, 0, 0 },
380 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
381 & ifmt_add, { 0x18000000 }
382 },
383/* nori $frdr,$frsr1,#$imm16z */
384 {
385 { 0, 0, 0, 0 },
386 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } },
387 & ifmt_addui, { 0x19000000 }
388 },
389/* xnor $frdrrr,$frsr1,$frsr2 */
390 {
391 { 0, 0, 0, 0 },
392 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
393 & ifmt_add, { 0x1a000000 }
394 },
395/* xnori $frdr,$frsr1,#$imm16z */
396 {
397 { 0, 0, 0, 0 },
398 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } },
399 & ifmt_addui, { 0x1b000000 }
400 },
401/* ldui $frdr,#$imm16z */
402 {
403 { 0, 0, 0, 0 },
404 { { MNEM, ' ', OP (FRDR), ',', '#', OP (IMM16Z), 0 } },
405 & ifmt_ldui, { 0x1d000000 }
406 },
407/* lsl $frdrrr,$frsr1,$frsr2 */
408 {
409 { 0, 0, 0, 0 },
410 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
411 & ifmt_add, { 0x20000000 }
412 },
413/* lsli $frdr,$frsr1,#$imm16 */
414 {
415 { 0, 0, 0, 0 },
416 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } },
417 & ifmt_addi, { 0x21000000 }
418 },
419/* lsr $frdrrr,$frsr1,$frsr2 */
420 {
421 { 0, 0, 0, 0 },
422 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
423 & ifmt_add, { 0x22000000 }
424 },
425/* lsri $frdr,$frsr1,#$imm16 */
426 {
427 { 0, 0, 0, 0 },
428 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } },
429 & ifmt_addi, { 0x23000000 }
430 },
431/* asr $frdrrr,$frsr1,$frsr2 */
432 {
433 { 0, 0, 0, 0 },
434 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
435 & ifmt_add, { 0x24000000 }
436 },
437/* asri $frdr,$frsr1,#$imm16 */
438 {
439 { 0, 0, 0, 0 },
440 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } },
441 & ifmt_addi, { 0x25000000 }
442 },
443/* brlt $frsr1,$frsr2,$imm16o */
444 {
445 { 0, 0, 0, 0 },
446 { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', OP (IMM16O), 0 } },
447 & ifmt_brlt, { 0x31000000 }
448 },
449/* brle $frsr1,$frsr2,$imm16o */
450 {
451 { 0, 0, 0, 0 },
452 { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', OP (IMM16O), 0 } },
453 & ifmt_brlt, { 0x33000000 }
454 },
455/* breq $frsr1,$frsr2,$imm16o */
456 {
457 { 0, 0, 0, 0 },
458 { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', OP (IMM16O), 0 } },
459 & ifmt_brlt, { 0x35000000 }
460 },
461/* brne $frsr1,$frsr2,$imm16o */
462 {
463 { 0, 0, 0, 0 },
464 { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', OP (IMM16O), 0 } },
465 & ifmt_brlt, { 0x3b000000 }
466 },
467/* jmp $imm16o */
468 {
469 { 0, 0, 0, 0 },
470 { { MNEM, ' ', OP (IMM16O), 0 } },
471 & ifmt_jmp, { 0x37000000 }
472 },
473/* jal $frdrrr,$frsr1 */
474 {
475 { 0, 0, 0, 0 },
476 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), 0 } },
477 & ifmt_jal, { 0x38000000 }
478 },
479/* dbnz $frsr1,$imm16o */
480 {
481 { 0, 0, 0, 0 },
482 { { MNEM, ' ', OP (FRSR1), ',', OP (IMM16O), 0 } },
483 & ifmt_dbnz, { 0x3d000000 }
484 },
485/* ei */
486 {
487 { 0, 0, 0, 0 },
488 { { MNEM, 0 } },
489 & ifmt_ei, { 0x60000000 }
490 },
491/* di */
492 {
493 { 0, 0, 0, 0 },
494 { { MNEM, 0 } },
495 & ifmt_ei, { 0x62000000 }
496 },
497/* si $frdrrr */
498 {
499 { 0, 0, 0, 0 },
500 { { MNEM, ' ', OP (FRDRRR), 0 } },
501 & ifmt_si, { 0x64000000 }
502 },
503/* reti $frsr1 */
504 {
505 { 0, 0, 0, 0 },
506 { { MNEM, ' ', OP (FRSR1), 0 } },
507 & ifmt_reti, { 0x66000000 }
508 },
509/* ldw $frdr,$frsr1,#$imm16 */
510 {
511 { 0, 0, 0, 0 },
512 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } },
513 & ifmt_addi, { 0x41000000 }
514 },
515/* stw $frsr2,$frsr1,#$imm16 */
516 {
517 { 0, 0, 0, 0 },
518 { { MNEM, ' ', OP (FRSR2), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } },
519 & ifmt_stw, { 0x43000000 }
520 },
521/* break */
522 {
523 { 0, 0, 0, 0 },
524 { { MNEM, 0 } },
525 & ifmt_nop, { 0x68000000 }
526 },
527/* iflush */
528 {
529 { 0, 0, 0, 0 },
530 { { MNEM, 0 } },
531 & ifmt_nop, { 0x6a000000 }
532 },
533/* ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum */
534 {
535 { 0, 0, 0, 0 },
536 { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (RC), ',', '#', OP (RCNUM), ',', '#', OP (CONTNUM), 0 } },
537 & ifmt_ldctxt, { 0x80000000 }
538 },
539/* ldfb $frsr1,$frsr2,#$imm16z */
540 {
541 { 0, 0, 0, 0 },
542 { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (IMM16Z), 0 } },
543 & ifmt_ldfb, { 0x84000000 }
544 },
545/* stfb $frsr1,$frsr2,#$imm16z */
546 {
547 { 0, 0, 0, 0 },
548 { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (IMM16Z), 0 } },
549 & ifmt_ldfb, { 0x88000000 }
550 },
551/* fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
552 {
553 { 0, 0, 0, 0 },
554 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
555 & ifmt_fbcb, { 0x8c000000 }
556 },
557/* mfbcb $frsr1,#$rbbc,$frsr2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
558 {
559 { 0, 0, 0, 0 },
560 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
561 & ifmt_mfbcb, { 0x90000000 }
562 },
563/* fbcci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
564 {
565 { 0, 0, 0, 0 },
566 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
567 & ifmt_fbcci, { 0x94000000 }
568 },
569/* fbrci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
570 {
571 { 0, 0, 0, 0 },
572 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
573 & ifmt_fbcci, { 0x98000000 }
574 },
575/* fbcri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
576 {
577 { 0, 0, 0, 0 },
578 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
579 & ifmt_fbcci, { 0x9c000000 }
580 },
581/* fbrri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
582 {
583 { 0, 0, 0, 0 },
584 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
585 & ifmt_fbcci, { 0xa0000000 }
586 },
587/* mfbcci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
588 {
589 { 0, 0, 0, 0 },
590 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
591 & ifmt_mfbcci, { 0xa4000000 }
592 },
593/* mfbrci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
594 {
595 { 0, 0, 0, 0 },
596 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
597 & ifmt_mfbcci, { 0xa8000000 }
598 },
599/* mfbcri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
600 {
601 { 0, 0, 0, 0 },
602 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
603 & ifmt_mfbcci, { 0xac000000 }
604 },
605/* mfbrri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
606 {
607 { 0, 0, 0, 0 },
608 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
609 & ifmt_mfbcci, { 0xb0000000 }
610 },
611/* fbcbdr $frsr1,#$rbbc,$frsr2,#$ball2,#$brc2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
612 {
613 { 0, 0, 0, 0 },
614 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (BALL2), ',', '#', OP (BRC2), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
615 & ifmt_fbcbdr, { 0xb4000000 }
616 },
617/* rcfbcb #$rbbc,#$type,#$ball,#$brc,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
618 {
619 { 0, 0, 0, 0 },
620 { { MNEM, ' ', '#', OP (RBBC), ',', '#', OP (TYPE), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (ROWNUM), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
621 & ifmt_rcfbcb, { 0xb8000000 }
622 },
623/* mrcfbcb $frsr2,#$rbbc,#$type,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
624 {
625 { 0, 0, 0, 0 },
626 { { MNEM, ' ', OP (FRSR2), ',', '#', OP (RBBC), ',', '#', OP (TYPE), ',', '#', OP (ROWNUM), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
627 & ifmt_mrcfbcb, { 0xbc000000 }
628 },
629/* cbcast #$mask,#$rc2,#$ctxdisp */
630 {
631 { 0, 0, 0, 0 },
632 { { MNEM, ' ', '#', OP (MASK), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } },
633 & ifmt_cbcast, { 0xc0000000 }
634 },
635/* dupcbcast #$mask,#$cell,#$rc2,#$ctxdisp */
636 {
637 { 0, 0, 0, 0 },
638 { { MNEM, ' ', '#', OP (MASK), ',', '#', OP (CELL), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } },
639 & ifmt_dupcbcast, { 0xc4000000 }
640 },
641/* wfbi #$bankaddr,#$rownum1,#$cell,#$dup,#$ctxdisp */
642 {
643 { 0, 0, 0, 0 },
644 { { MNEM, ' ', '#', OP (BANKADDR), ',', '#', OP (ROWNUM1), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
645 & ifmt_wfbi, { 0xc8000000 }
646 },
647/* wfb $frsr1,$frsr2,#$fbdisp,#$rownum2,#$ctxdisp */
648 {
649 { 0, 0, 0, 0 },
650 { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (ROWNUM2), ',', '#', OP (CTXDISP), 0 } },
651 & ifmt_wfb, { 0xcc000000 }
652 },
653/* rcrisc $frdrrr,#$rbbc,$frsr1,#$colnum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
654 {
655 { 0, 0, 0, 0 },
656 { { MNEM, ' ', OP (FRDRRR), ',', '#', OP (RBBC), ',', OP (FRSR1), ',', '#', OP (COLNUM), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
657 & ifmt_rcrisc, { 0xd0000000 }
658 },
659/* fbcbinc $frsr1,#$rbbc,#$incamt,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
660 {
661 { 0, 0, 0, 0 },
662 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (INCAMT), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
663 & ifmt_fbcbinc, { 0xd4000000 }
664 },
665/* rcxmode $frsr2,#$rda,#$wr,#$xmode,#$mask1,#$fbdisp,#$rownum2,#$rc2,#$ctxdisp */
666 {
667 { 0, 0, 0, 0 },
668 { { MNEM, ' ', OP (FRSR2), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (XMODE), ',', '#', OP (MASK1), ',', '#', OP (FBDISP), ',', '#', OP (ROWNUM2), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } },
669 & ifmt_rcxmode, { 0xd8000000 }
670 },
671/* intlvr $frsr1,#$mode,$frsr2,#$id,#$size */
672 {
673 { 0, 0, 0, 0 },
674 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (MODE), ',', OP (FRSR2), ',', '#', OP (ID), ',', '#', OP (SIZE), 0 } },
675 & ifmt_interleaver, { 0xdc000000 }
676 },
677/* wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
678 {
679 { 0, 0, 0, 0 },
680 { { MNEM, ' ', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (FBINCR), ',', '#', OP (BALL), ',', '#', OP (COLNUM), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
681 & ifmt_wfbinc, { 0xe0000000 }
682 },
683/* mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
684 {
685 { 0, 0, 0, 0 },
686 { { MNEM, ' ', OP (FRSR2), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (FBINCR), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
687 & ifmt_mwfbinc, { 0xe4000000 }
688 },
689/* wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
690 {
691 { 0, 0, 0, 0 },
692 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (BALL), ',', '#', OP (COLNUM), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
693 & ifmt_wfbincr, { 0xe8000000 }
694 },
695/* mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
696 {
697 { 0, 0, 0, 0 },
698 { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
699 & ifmt_mwfbincr, { 0xec000000 }
700 },
701/* fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
702 {
703 { 0, 0, 0, 0 },
704 { { MNEM, ' ', '#', OP (PERM), ',', '#', OP (A23), ',', '#', OP (CR), ',', '#', OP (CBS), ',', '#', OP (INCR), ',', '#', OP (CCB), ',', '#', OP (CDB), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
705 & ifmt_fbcbincs, { 0xf0000000 }
706 },
707/* mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
708 {
709 { 0, 0, 0, 0 },
710 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (PERM), ',', '#', OP (CBS), ',', '#', OP (INCR), ',', '#', OP (CCB), ',', '#', OP (CDB), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
711 & ifmt_mfbcbincs, { 0xf4000000 }
712 },
713/* fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
714 {
715 { 0, 0, 0, 0 },
716 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (PERM), ',', '#', OP (BALL), ',', '#', OP (COLNUM), ',', '#', OP (CBX), ',', '#', OP (CCB), ',', '#', OP (CDB), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
717 & ifmt_fbcbincrs, { 0xf8000000 }
718 },
719/* mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
720 {
721 { 0, 0, 0, 0 },
722 { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (PERM), ',', '#', OP (CBX), ',', '#', OP (CCB), ',', '#', OP (CDB), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
723 & ifmt_mfbcbincrs, { 0xfc000000 }
724 },
725};
726
727#undef A
728#undef OPERAND
729#undef MNEM
730#undef OP
731
732/* Formats for ALIAS macro-insns. */
733
734#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
735#define F(f) & ms1_cgen_ifld_table[MS1_##f]
736#else
737#define F(f) & ms1_cgen_ifld_table[MS1_/**/f]
738#endif
739#undef F
740
741/* Each non-simple macro entry points to an array of expansion possibilities. */
742
743#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
744#define A(a) (1 << CGEN_INSN_##a)
745#else
746#define A(a) (1 << CGEN_INSN_/**/a)
747#endif
748#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
749#define OPERAND(op) MS1_OPERAND_##op
750#else
751#define OPERAND(op) MS1_OPERAND_/**/op
752#endif
753#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
754#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
755
756/* The macro instruction table. */
757
758static const CGEN_IBASE ms1_cgen_macro_insn_table[] =
759{
760};
761
762/* The macro instruction opcode table. */
763
764static const CGEN_OPCODE ms1_cgen_macro_insn_opcode_table[] =
765{
766};
767
768#undef A
769#undef OPERAND
770#undef MNEM
771#undef OP
772
773#ifndef CGEN_ASM_HASH_P
774#define CGEN_ASM_HASH_P(insn) 1
775#endif
776
777#ifndef CGEN_DIS_HASH_P
778#define CGEN_DIS_HASH_P(insn) 1
779#endif
780
781/* Return non-zero if INSN is to be added to the hash table.
782 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
783
784static int
785asm_hash_insn_p (insn)
786 const CGEN_INSN *insn ATTRIBUTE_UNUSED;
787{
788 return CGEN_ASM_HASH_P (insn);
789}
790
791static int
792dis_hash_insn_p (insn)
793 const CGEN_INSN *insn;
794{
795 /* If building the hash table and the NO-DIS attribute is present,
796 ignore. */
797 if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
798 return 0;
799 return CGEN_DIS_HASH_P (insn);
800}
801
802#ifndef CGEN_ASM_HASH
803#define CGEN_ASM_HASH_SIZE 127
804#ifdef CGEN_MNEMONIC_OPERANDS
805#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
806#else
807#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
808#endif
809#endif
810
811/* It doesn't make much sense to provide a default here,
812 but while this is under development we do.
813 BUFFER is a pointer to the bytes of the insn, target order.
814 VALUE is the first base_insn_bitsize bits as an int in host order. */
815
816#ifndef CGEN_DIS_HASH
817#define CGEN_DIS_HASH_SIZE 256
818#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
819#endif
820
821/* The result is the hash value of the insn.
822 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
823
824static unsigned int
825asm_hash_insn (mnem)
826 const char * mnem;
827{
828 return CGEN_ASM_HASH (mnem);
829}
830
831/* BUF is a pointer to the bytes of the insn, target order.
832 VALUE is the first base_insn_bitsize bits as an int in host order. */
833
834static unsigned int
835dis_hash_insn (buf, value)
836 const char * buf ATTRIBUTE_UNUSED;
837 CGEN_INSN_INT value ATTRIBUTE_UNUSED;
838{
839 return CGEN_DIS_HASH (buf, value);
840}
841
842static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
843
844/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
845
846static void
847set_fields_bitsize (fields, size)
848 CGEN_FIELDS *fields;
849 int size;
850{
851 CGEN_FIELDS_BITSIZE (fields) = size;
852}
853
854/* Function to call before using the operand instance table.
855 This plugs the opcode entries and macro instructions into the cpu table. */
856
857void
858ms1_cgen_init_opcode_table (cd)
859 CGEN_CPU_DESC cd;
860{
861 int i;
862 int num_macros = (sizeof (ms1_cgen_macro_insn_table) /
863 sizeof (ms1_cgen_macro_insn_table[0]));
864 const CGEN_IBASE *ib = & ms1_cgen_macro_insn_table[0];
865 const CGEN_OPCODE *oc = & ms1_cgen_macro_insn_opcode_table[0];
866 CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
867 memset (insns, 0, num_macros * sizeof (CGEN_INSN));
868 for (i = 0; i < num_macros; ++i)
869 {
870 insns[i].base = &ib[i];
871 insns[i].opcode = &oc[i];
872 ms1_cgen_build_insn_regex (& insns[i]);
873 }
874 cd->macro_insn_table.init_entries = insns;
875 cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
876 cd->macro_insn_table.num_init_entries = num_macros;
877
878 oc = & ms1_cgen_insn_opcode_table[0];
879 insns = (CGEN_INSN *) cd->insn_table.init_entries;
880 for (i = 0; i < MAX_INSNS; ++i)
881 {
882 insns[i].opcode = &oc[i];
883 ms1_cgen_build_insn_regex (& insns[i]);
884 }
885
886 cd->sizeof_fields = sizeof (CGEN_FIELDS);
887 cd->set_fields_bitsize = set_fields_bitsize;
888
889 cd->asm_hash_p = asm_hash_insn_p;
890 cd->asm_hash = asm_hash_insn;
891 cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
892
893 cd->dis_hash_p = dis_hash_insn_p;
894 cd->dis_hash = dis_hash_insn;
895 cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
896}
GDB Binutils - Deliverables
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