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* gold-threads.h (class Once): Define.
[deliverable/binutils-gdb.git] / opcodes / mt-desc.c
CommitLineData
d031aafb 1/* CPU data for mt.
ac188222
DB		 2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
05994f45 5Copyright 1996-2010 Free Software Foundation, Inc.
ac188222
DB		 6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9b201bb5
NC		 9 This file is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
ac188222 13
9b201bb5
NC		 14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
ac188222 18
9b201bb5
NC		 19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
ac188222
DB		 22
23*/
24
25#include "sysdep.h"
26#include <stdio.h>
27#include <stdarg.h>
28#include "ansidecl.h"
29#include "bfd.h"
30#include "symcat.h"
d031aafb
NS		 31#include "mt-desc.h"
32#include "mt-opc.h"
ac188222
DB		 33#include "opintl.h"
34#include "libiberty.h"
35#include "xregex.h"
36
37/* Attributes. */
38
39static const CGEN_ATTR_ENTRY bool_attr[] =
40{
41 { "#f", 0 },
42 { "#t", 1 },
43 { 0, 0 }
44};
45
46static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
47{
48 { "base", MACH_BASE },
49 { "ms1", MACH_MS1 },
50 { "ms1_003", MACH_MS1_003 },
6f84a2a6 51 { "ms2", MACH_MS2 },
ac188222
DB		 52 { "max", MACH_MAX },
53 { 0, 0 }
54};
55
56static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
57{
d031aafb 58 { "mt", ISA_MT },
ac188222
DB		 59 { "max", ISA_MAX },
60 { 0, 0 }
61};
62
d031aafb 63const CGEN_ATTR_TABLE mt_cgen_ifield_attr_table[] =
ac188222
DB		 64{
65 { "MACH", & MACH_attr[0], & MACH_attr[0] },
66 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
67 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
68 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
69 { "RESERVED", &bool_attr[0], &bool_attr[0] },
70 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
71 { "SIGNED", &bool_attr[0], &bool_attr[0] },
72 { 0, 0, 0 }
73};
74
d031aafb 75const CGEN_ATTR_TABLE mt_cgen_hardware_attr_table[] =
ac188222
DB		 76{
77 { "MACH", & MACH_attr[0], & MACH_attr[0] },
78 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
79 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
80 { "PC", &bool_attr[0], &bool_attr[0] },
81 { "PROFILE", &bool_attr[0], &bool_attr[0] },
82 { 0, 0, 0 }
83};
84
d031aafb 85const CGEN_ATTR_TABLE mt_cgen_operand_attr_table[] =
ac188222
DB		 86{
87 { "MACH", & MACH_attr[0], & MACH_attr[0] },
88 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
89 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
90 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
91 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
92 { "SIGNED", &bool_attr[0], &bool_attr[0] },
93 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
94 { "RELAX", &bool_attr[0], &bool_attr[0] },
95 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
96 { 0, 0, 0 }
97};
98
d031aafb 99const CGEN_ATTR_TABLE mt_cgen_insn_attr_table[] =
ac188222
DB		 100{
101 { "MACH", & MACH_attr[0], & MACH_attr[0] },
102 { "ALIAS", &bool_attr[0], &bool_attr[0] },
103 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
104 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
105 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
106 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
107 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
108 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
109 { "RELAXED", &bool_attr[0], &bool_attr[0] },
110 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
111 { "PBB", &bool_attr[0], &bool_attr[0] },
112 { "LOAD-DELAY", &bool_attr[0], &bool_attr[0] },
113 { "MEMORY-ACCESS", &bool_attr[0], &bool_attr[0] },
114 { "AL-INSN", &bool_attr[0], &bool_attr[0] },
115 { "IO-INSN", &bool_attr[0], &bool_attr[0] },
116 { "BR-INSN", &bool_attr[0], &bool_attr[0] },
6f84a2a6 117 { "JAL-HAZARD", &bool_attr[0], &bool_attr[0] },
ac188222
DB		 118 { "USES-FRDR", &bool_attr[0], &bool_attr[0] },
119 { "USES-FRDRRR", &bool_attr[0], &bool_attr[0] },
120 { "USES-FRSR1", &bool_attr[0], &bool_attr[0] },
121 { "USES-FRSR2", &bool_attr[0], &bool_attr[0] },
122 { "SKIPA", &bool_attr[0], &bool_attr[0] },
123 { 0, 0, 0 }
124};
125
126/* Instruction set variants. */
127
d031aafb
NS		 128static const CGEN_ISA mt_cgen_isa_table[] = {
129 { "mt", 32, 32, 32, 32 },
ac188222
DB		 130 { 0, 0, 0, 0, 0 }
131};
132
133/* Machine variants. */
134
d031aafb 135static const CGEN_MACH mt_cgen_mach_table[] = {
ac188222
DB		 136 { "ms1", "ms1", MACH_MS1, 0 },
137 { "ms1-003", "ms1-003", MACH_MS1_003, 0 },
6f84a2a6 138 { "ms2", "ms2", MACH_MS2, 0 },
ac188222
DB		 139 { 0, 0, 0, 0 }
140};
141
d031aafb 142static CGEN_KEYWORD_ENTRY mt_cgen_opval_msys_syms_entries[] =
ac188222 143{
fb53f5a8
DB		 144 { "DUP", 1, {0, {{{0, 0}}}}, 0, 0 },
145 { "XX", 0, {0, {{{0, 0}}}}, 0, 0 }
ac188222
DB		 146};
147
d031aafb 148CGEN_KEYWORD mt_cgen_opval_msys_syms =
ac188222 149{
d031aafb 150 & mt_cgen_opval_msys_syms_entries[0],
ac188222
DB		 151 2,
152 0, 0, 0, 0, ""
153};
154
d031aafb 155static CGEN_KEYWORD_ENTRY mt_cgen_opval_h_spr_entries[] =
ac188222 156{
fb53f5a8
DB		 157 { "R0", 0, {0, {{{0, 0}}}}, 0, 0 },
158 { "R1", 1, {0, {{{0, 0}}}}, 0, 0 },
159 { "R2", 2, {0, {{{0, 0}}}}, 0, 0 },
160 { "R3", 3, {0, {{{0, 0}}}}, 0, 0 },
161 { "R4", 4, {0, {{{0, 0}}}}, 0, 0 },
162 { "R5", 5, {0, {{{0, 0}}}}, 0, 0 },
163 { "R6", 6, {0, {{{0, 0}}}}, 0, 0 },
164 { "R7", 7, {0, {{{0, 0}}}}, 0, 0 },
165 { "R8", 8, {0, {{{0, 0}}}}, 0, 0 },
166 { "R9", 9, {0, {{{0, 0}}}}, 0, 0 },
167 { "R10", 10, {0, {{{0, 0}}}}, 0, 0 },
168 { "R11", 11, {0, {{{0, 0}}}}, 0, 0 },
169 { "R12", 12, {0, {{{0, 0}}}}, 0, 0 },
170 { "fp", 12, {0, {{{0, 0}}}}, 0, 0 },
171 { "R13", 13, {0, {{{0, 0}}}}, 0, 0 },
172 { "sp", 13, {0, {{{0, 0}}}}, 0, 0 },
173 { "R14", 14, {0, {{{0, 0}}}}, 0, 0 },
174 { "ra", 14, {0, {{{0, 0}}}}, 0, 0 },
175 { "R15", 15, {0, {{{0, 0}}}}, 0, 0 },
176 { "ira", 15, {0, {{{0, 0}}}}, 0, 0 }
ac188222
DB		 177};
178
d031aafb 179CGEN_KEYWORD mt_cgen_opval_h_spr =
ac188222 180{
d031aafb 181 & mt_cgen_opval_h_spr_entries[0],
ac188222
DB		 182 20,
183 0, 0, 0, 0, ""
184};
185
186
187/* The hardware table. */
188
189#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
190#define A(a) (1 << CGEN_HW_##a)
191#else
192#define A(a) (1 << CGEN_HW_/**/a)
193#endif
194
d031aafb 195const CGEN_HW_ENTRY mt_cgen_hw_table[] =
ac188222 196{
fb53f5a8
DB		 197 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
198 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
199 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
200 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
201 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
d031aafb 202 { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & mt_cgen_opval_h_spr, { 0, { { { (1<<MACH_BASE), 0 } } } } },
fb53f5a8
DB		 203 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
204 { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
ac188222
DB		 205};
206
207#undef A
208
209
210/* The instruction field table. */
211
212#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
213#define A(a) (1 << CGEN_IFLD_##a)
214#else
215#define A(a) (1 << CGEN_IFLD_/**/a)
216#endif
217
d031aafb 218const CGEN_IFLD mt_cgen_ifld_table[] =
ac188222 219{
d031aafb
NS		 220 { MT_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
221 { MT_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
222 { MT_F_MSYS, "f-msys", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
223 { MT_F_OPC, "f-opc", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
224 { MT_F_IMM, "f-imm", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
225 { MT_F_UU24, "f-uu24", 0, 32, 23, 24, { 0, { { { (1<<MACH_BASE), 0 } } } } },
226 { MT_F_SR1, "f-sr1", 0, 32, 23, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
227 { MT_F_SR2, "f-sr2", 0, 32, 19, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
228 { MT_F_DR, "f-dr", 0, 32, 19, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
229 { MT_F_DRRR, "f-drrr", 0, 32, 15, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
230 { MT_F_IMM16U, "f-imm16u", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
231 { MT_F_IMM16S, "f-imm16s", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
232 { MT_F_IMM16A, "f-imm16a", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
233 { MT_F_UU4A, "f-uu4a", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
234 { MT_F_UU4B, "f-uu4b", 0, 32, 23, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
235 { MT_F_UU12, "f-uu12", 0, 32, 11, 12, { 0, { { { (1<<MACH_BASE), 0 } } } } },
236 { MT_F_UU8, "f-uu8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
237 { MT_F_UU16, "f-uu16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
238 { MT_F_UU1, "f-uu1", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
239 { MT_F_MSOPC, "f-msopc", 0, 32, 30, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
240 { MT_F_UU_26_25, "f-uu-26-25", 0, 32, 25, 26, { 0, { { { (1<<MACH_BASE), 0 } } } } },
241 { MT_F_MASK, "f-mask", 0, 32, 25, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
242 { MT_F_BANKADDR, "f-bankaddr", 0, 32, 25, 13, { 0, { { { (1<<MACH_BASE), 0 } } } } },
243 { MT_F_RDA, "f-rda", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
244 { MT_F_UU_2_25, "f-uu-2-25", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
245 { MT_F_RBBC, "f-rbbc", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
246 { MT_F_PERM, "f-perm", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
247 { MT_F_MODE, "f-mode", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
248 { MT_F_UU_1_24, "f-uu-1-24", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
249 { MT_F_WR, "f-wr", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
250 { MT_F_FBINCR, "f-fbincr", 0, 32, 23, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
251 { MT_F_UU_2_23, "f-uu-2-23", 0, 32, 23, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
252 { MT_F_XMODE, "f-xmode", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
253 { MT_F_A23, "f-a23", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
254 { MT_F_MASK1, "f-mask1", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
255 { MT_F_CR, "f-cr", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
256 { MT_F_TYPE, "f-type", 0, 32, 21, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
257 { MT_F_INCAMT, "f-incamt", 0, 32, 19, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
258 { MT_F_CBS, "f-cbs", 0, 32, 19, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
259 { MT_F_UU_1_19, "f-uu-1-19", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
260 { MT_F_BALL, "f-ball", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
261 { MT_F_COLNUM, "f-colnum", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
262 { MT_F_BRC, "f-brc", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
263 { MT_F_INCR, "f-incr", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
264 { MT_F_FBDISP, "f-fbdisp", 0, 32, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
265 { MT_F_UU_4_15, "f-uu-4-15", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
266 { MT_F_LENGTH, "f-length", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
267 { MT_F_UU_1_15, "f-uu-1-15", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
268 { MT_F_RC, "f-rc", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
269 { MT_F_RCNUM, "f-rcnum", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
270 { MT_F_ROWNUM, "f-rownum", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
271 { MT_F_CBX, "f-cbx", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
272 { MT_F_ID, "f-id", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
273 { MT_F_SIZE, "f-size", 0, 32, 13, 14, { 0, { { { (1<<MACH_BASE), 0 } } } } },
274 { MT_F_ROWNUM1, "f-rownum1", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
275 { MT_F_UU_3_11, "f-uu-3-11", 0, 32, 11, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
276 { MT_F_RC1, "f-rc1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
277 { MT_F_CCB, "f-ccb", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
278 { MT_F_CBRB, "f-cbrb", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
279 { MT_F_CDB, "f-cdb", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
280 { MT_F_ROWNUM2, "f-rownum2", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
281 { MT_F_CELL, "f-cell", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
282 { MT_F_UU_3_9, "f-uu-3-9", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
283 { MT_F_CONTNUM, "f-contnum", 0, 32, 8, 9, { 0, { { { (1<<MACH_BASE), 0 } } } } },
284 { MT_F_UU_1_6, "f-uu-1-6", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
285 { MT_F_DUP, "f-dup", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
286 { MT_F_RC2, "f-rc2", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
287 { MT_F_CTXDISP, "f-ctxdisp", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
288 { MT_F_IMM16L, "f-imm16l", 0, 32, 23, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
289 { MT_F_LOOPO, "f-loopo", 0, 32, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
290 { MT_F_CB1SEL, "f-cb1sel", 0, 32, 25, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
291 { MT_F_CB2SEL, "f-cb2sel", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
292 { MT_F_CB1INCR, "f-cb1incr", 0, 32, 19, 6, { 0|A(SIGNED), { { { (1<<MACH_BASE), 0 } } } } },
293 { MT_F_CB2INCR, "f-cb2incr", 0, 32, 13, 6, { 0|A(SIGNED), { { { (1<<MACH_BASE), 0 } } } } },
294 { MT_F_RC3, "f-rc3", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
295 { MT_F_MSYSFRSR2, "f-msysfrsr2", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
296 { MT_F_BRC2, "f-brc2", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
297 { MT_F_BALL2, "f-ball2", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
fb53f5a8 298 { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
ac188222
DB		 299};
300
301#undef A
302
303
304
305/* multi ifield declarations */
306
307
308
309/* multi ifield definitions */
310
311
312/* The operand table. */
313
314#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
315#define A(a) (1 << CGEN_OPERAND_##a)
316#else
317#define A(a) (1 << CGEN_OPERAND_/**/a)
318#endif
319#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
d031aafb 320#define OPERAND(op) MT_OPERAND_##op
ac188222 321#else
d031aafb 322#define OPERAND(op) MT_OPERAND_/**/op
ac188222
DB		 323#endif
324
d031aafb 325const CGEN_OPERAND mt_cgen_operand_table[] =
ac188222
DB		 326{
327/* pc: program counter */
d031aafb
NS		 328 { "pc", MT_OPERAND_PC, HW_H_PC, 0, 0,
329 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_NIL] } },
fb53f5a8 330 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
ac188222 331/* frsr1: register */
d031aafb
NS		 332 { "frsr1", MT_OPERAND_FRSR1, HW_H_SPR, 23, 4,
333 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR1] } },
fb53f5a8 334 { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
ac188222 335/* frsr2: register */
d031aafb
NS		 336 { "frsr2", MT_OPERAND_FRSR2, HW_H_SPR, 19, 4,
337 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR2] } },
fb53f5a8 338 { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
ac188222 339/* frdr: register */
d031aafb
NS		 340 { "frdr", MT_OPERAND_FRDR, HW_H_SPR, 19, 4,
341 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DR] } },
fb53f5a8 342 { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
ac188222 343/* frdrrr: register */
d031aafb
NS		 344 { "frdrrr", MT_OPERAND_FRDRRR, HW_H_SPR, 15, 4,
345 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DRRR] } },
fb53f5a8 346 { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
ac188222 347/* imm16: immediate value - sign extd */
d031aafb
NS		 348 { "imm16", MT_OPERAND_IMM16, HW_H_SINT, 15, 16,
349 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } },
fb53f5a8 350 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 351/* imm16z: immediate value - zero extd */
d031aafb
NS		 352 { "imm16z", MT_OPERAND_IMM16Z, HW_H_UINT, 15, 16,
353 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16U] } },
fb53f5a8 354 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 355/* imm16o: immediate value */
d031aafb
NS		 356 { "imm16o", MT_OPERAND_IMM16O, HW_H_UINT, 15, 16,
357 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } },
6f84a2a6 358 { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
ac188222 359/* rc: rc */
d031aafb
NS		 360 { "rc", MT_OPERAND_RC, HW_H_UINT, 15, 1,
361 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC] } },
fb53f5a8 362 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 363/* rcnum: rcnum */
d031aafb
NS		 364 { "rcnum", MT_OPERAND_RCNUM, HW_H_UINT, 14, 3,
365 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RCNUM] } },
fb53f5a8 366 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 367/* contnum: context number */
d031aafb
NS		 368 { "contnum", MT_OPERAND_CONTNUM, HW_H_UINT, 8, 9,
369 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CONTNUM] } },
fb53f5a8 370 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 371/* rbbc: omega network configuration */
d031aafb
NS		 372 { "rbbc", MT_OPERAND_RBBC, HW_H_UINT, 25, 2,
373 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RBBC] } },
fb53f5a8 374 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 375/* colnum: column number */
d031aafb
NS		 376 { "colnum", MT_OPERAND_COLNUM, HW_H_UINT, 18, 3,
377 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_COLNUM] } },
fb53f5a8 378 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 379/* rownum: row number */
d031aafb
NS		 380 { "rownum", MT_OPERAND_ROWNUM, HW_H_UINT, 14, 3,
381 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM] } },
fb53f5a8 382 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 383/* rownum1: row number */
d031aafb
NS		 384 { "rownum1", MT_OPERAND_ROWNUM1, HW_H_UINT, 12, 3,
385 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM1] } },
fb53f5a8 386 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 387/* rownum2: row number */
d031aafb
NS		 388 { "rownum2", MT_OPERAND_ROWNUM2, HW_H_UINT, 9, 3,
389 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM2] } },
fb53f5a8 390 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 391/* rc1: rc1 */
d031aafb
NS		 392 { "rc1", MT_OPERAND_RC1, HW_H_UINT, 11, 1,
393 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC1] } },
fb53f5a8 394 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 395/* rc2: rc2 */
d031aafb
NS		 396 { "rc2", MT_OPERAND_RC2, HW_H_UINT, 6, 1,
397 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC2] } },
fb53f5a8 398 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 399/* cbrb: data-bus orientation */
d031aafb
NS		 400 { "cbrb", MT_OPERAND_CBRB, HW_H_UINT, 10, 1,
401 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBRB] } },
fb53f5a8 402 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 403/* cell: cell */
d031aafb
NS		 404 { "cell", MT_OPERAND_CELL, HW_H_UINT, 9, 3,
405 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CELL] } },
fb53f5a8 406 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 407/* dup: dup */
d031aafb
NS		 408 { "dup", MT_OPERAND_DUP, HW_H_UINT, 6, 1,
409 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DUP] } },
fb53f5a8 410 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 411/* ctxdisp: context displacement */
d031aafb
NS		 412 { "ctxdisp", MT_OPERAND_CTXDISP, HW_H_UINT, 5, 6,
413 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CTXDISP] } },
fb53f5a8 414 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 415/* fbdisp: frame buffer displacement */
d031aafb
NS		 416 { "fbdisp", MT_OPERAND_FBDISP, HW_H_UINT, 15, 6,
417 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBDISP] } },
fb53f5a8 418 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 419/* type: type */
d031aafb
NS		 420 { "type", MT_OPERAND_TYPE, HW_H_UINT, 21, 2,
421 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_TYPE] } },
fb53f5a8 422 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 423/* mask: mask */
d031aafb
NS		 424 { "mask", MT_OPERAND_MASK, HW_H_UINT, 25, 16,
425 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK] } },
fb53f5a8 426 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 427/* bankaddr: bank address */
d031aafb
NS		 428 { "bankaddr", MT_OPERAND_BANKADDR, HW_H_UINT, 25, 13,
429 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BANKADDR] } },
fb53f5a8 430 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 431/* incamt: increment amount */
d031aafb
NS		 432 { "incamt", MT_OPERAND_INCAMT, HW_H_UINT, 19, 8,
433 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCAMT] } },
fb53f5a8 434 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 435/* xmode: xmode */
d031aafb
NS		 436 { "xmode", MT_OPERAND_XMODE, HW_H_UINT, 23, 1,
437 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_XMODE] } },
fb53f5a8 438 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 439/* mask1: mask1 */
d031aafb
NS		 440 { "mask1", MT_OPERAND_MASK1, HW_H_UINT, 22, 3,
441 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK1] } },
fb53f5a8 442 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 443/* ball: b_all */
d031aafb
NS		 444 { "ball", MT_OPERAND_BALL, HW_H_UINT, 19, 1,
445 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL] } },
fb53f5a8 446 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 447/* brc: b_r_c */
d031aafb
NS		 448 { "brc", MT_OPERAND_BRC, HW_H_UINT, 18, 3,
449 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC] } },
fb53f5a8 450 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 451/* rda: rd */
d031aafb
NS		 452 { "rda", MT_OPERAND_RDA, HW_H_UINT, 25, 1,
453 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RDA] } },
fb53f5a8 454 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 455/* wr: wr */
d031aafb
NS		 456 { "wr", MT_OPERAND_WR, HW_H_UINT, 24, 1,
457 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_WR] } },
fb53f5a8 458 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 459/* ball2: b_all2 */
d031aafb
NS		 460 { "ball2", MT_OPERAND_BALL2, HW_H_UINT, 15, 1,
461 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL2] } },
fb53f5a8 462 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 463/* brc2: b_r_c2 */
d031aafb
NS		 464 { "brc2", MT_OPERAND_BRC2, HW_H_UINT, 14, 3,
465 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC2] } },
fb53f5a8 466 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 467/* perm: perm */
d031aafb
NS		 468 { "perm", MT_OPERAND_PERM, HW_H_UINT, 25, 2,
469 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_PERM] } },
fb53f5a8 470 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 471/* a23: a23 */
d031aafb
NS		 472 { "a23", MT_OPERAND_A23, HW_H_UINT, 23, 1,
473 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_A23] } },
fb53f5a8 474 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 475/* cr: c-r */
d031aafb
NS		 476 { "cr", MT_OPERAND_CR, HW_H_UINT, 22, 3,
477 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CR] } },
fb53f5a8 478 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 479/* cbs: cbs */
d031aafb
NS		 480 { "cbs", MT_OPERAND_CBS, HW_H_UINT, 19, 2,
481 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBS] } },
fb53f5a8 482 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 483/* incr: incr */
d031aafb
NS		 484 { "incr", MT_OPERAND_INCR, HW_H_UINT, 17, 6,
485 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCR] } },
fb53f5a8 486 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 487/* length: length */
d031aafb
NS		 488 { "length", MT_OPERAND_LENGTH, HW_H_UINT, 15, 3,
489 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LENGTH] } },
fb53f5a8 490 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 491/* cbx: cbx */
d031aafb
NS		 492 { "cbx", MT_OPERAND_CBX, HW_H_UINT, 14, 3,
493 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBX] } },
fb53f5a8 494 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 495/* ccb: ccb */
d031aafb
NS		 496 { "ccb", MT_OPERAND_CCB, HW_H_UINT, 11, 1,
497 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CCB] } },
fb53f5a8 498 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 499/* cdb: cdb */
d031aafb
NS		 500 { "cdb", MT_OPERAND_CDB, HW_H_UINT, 10, 1,
501 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CDB] } },
fb53f5a8 502 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 503/* mode: mode */
d031aafb
NS		 504 { "mode", MT_OPERAND_MODE, HW_H_UINT, 25, 2,
505 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MODE] } },
fb53f5a8 506 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 507/* id: i/d */
d031aafb
NS		 508 { "id", MT_OPERAND_ID, HW_H_UINT, 14, 1,
509 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ID] } },
fb53f5a8 510 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 511/* size: size */
d031aafb
NS		 512 { "size", MT_OPERAND_SIZE, HW_H_UINT, 13, 14,
513 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SIZE] } },
fb53f5a8 514 { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222 515/* fbincr: fb incr */
d031aafb
NS		 516 { "fbincr", MT_OPERAND_FBINCR, HW_H_UINT, 23, 4,
517 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBINCR] } },
fb53f5a8 518 { 0, { { { (1<<MACH_BASE), 0 } } } } },
6f84a2a6 519/* loopsize: immediate value */
d031aafb
NS		 520 { "loopsize", MT_OPERAND_LOOPSIZE, HW_H_UINT, 7, 8,
521 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LOOPO] } },
6f84a2a6
NS		 522 { 0|A(PCREL_ADDR), { { { (1<<MACH_MS2), 0 } } } } },
523/* imm16l: immediate value */
d031aafb
NS		 524 { "imm16l", MT_OPERAND_IMM16L, HW_H_UINT, 23, 16,
525 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16L] } },
6f84a2a6
NS		 526 { 0, { { { (1<<MACH_MS2), 0 } } } } },
527/* rc3: rc3 */
d031aafb
NS		 528 { "rc3", MT_OPERAND_RC3, HW_H_UINT, 7, 1,
529 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC3] } },
6f84a2a6
NS		 530 { 0, { { { (1<<MACH_MS2), 0 } } } } },
531/* cb1sel: cb1sel */
d031aafb
NS		 532 { "cb1sel", MT_OPERAND_CB1SEL, HW_H_UINT, 25, 3,
533 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1SEL] } },
6f84a2a6
NS		 534 { 0, { { { (1<<MACH_MS2), 0 } } } } },
535/* cb2sel: cb2sel */
d031aafb
NS		 536 { "cb2sel", MT_OPERAND_CB2SEL, HW_H_UINT, 22, 3,
537 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2SEL] } },
6f84a2a6
NS		 538 { 0, { { { (1<<MACH_MS2), 0 } } } } },
539/* cb1incr: cb1incr */
d031aafb
NS		 540 { "cb1incr", MT_OPERAND_CB1INCR, HW_H_SINT, 19, 6,
541 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1INCR] } },
6f84a2a6
NS		 542 { 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } } },
543/* cb2incr: cb2incr */
d031aafb
NS		 544 { "cb2incr", MT_OPERAND_CB2INCR, HW_H_SINT, 13, 6,
545 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2INCR] } },
6f84a2a6 546 { 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } } },
ac188222
DB		 547/* sentinel */
548 { 0, 0, 0, 0, 0,
549 { 0, { (const PTR) 0 } },
fb53f5a8 550 { 0, { { { (1<<MACH_BASE), 0 } } } } }
ac188222
DB		 551};
552
553#undef A
554
555
556/* The instruction table. */
557
558#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
559#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
560#define A(a) (1 << CGEN_INSN_##a)
561#else
562#define A(a) (1 << CGEN_INSN_/**/a)
563#endif
564
d031aafb 565static const CGEN_IBASE mt_cgen_insn_table[MAX_INSNS] =
ac188222
DB		 566{
567 /* Special null first entry.
568 A `num' value of zero is thus invalid.
569 Also, the special `invalid' insn resides here. */
fb53f5a8 570 { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
ac188222
DB		 571/* add $frdrrr,$frsr1,$frsr2 */
572 {
d031aafb 573 MT_INSN_ADD, "add", "add", 32,
fb53f5a8 574 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 575 },
576/* addu $frdrrr,$frsr1,$frsr2 */
577 {
d031aafb 578 MT_INSN_ADDU, "addu", "addu", 32,
fb53f5a8 579 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 580 },
581/* addi $frdr,$frsr1,#$imm16 */
582 {
d031aafb 583 MT_INSN_ADDI, "addi", "addi", 32,
fb53f5a8 584 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 585 },
586/* addui $frdr,$frsr1,#$imm16z */
587 {
d031aafb 588 MT_INSN_ADDUI, "addui", "addui", 32,
fb53f5a8 589 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 590 },
591/* sub $frdrrr,$frsr1,$frsr2 */
592 {
d031aafb 593 MT_INSN_SUB, "sub", "sub", 32,
fb53f5a8 594 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 595 },
596/* subu $frdrrr,$frsr1,$frsr2 */
597 {
d031aafb 598 MT_INSN_SUBU, "subu", "subu", 32,
fb53f5a8 599 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 600 },
601/* subi $frdr,$frsr1,#$imm16 */
602 {
d031aafb 603 MT_INSN_SUBI, "subi", "subi", 32,
fb53f5a8 604 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 605 },
606/* subui $frdr,$frsr1,#$imm16z */
607 {
d031aafb 608 MT_INSN_SUBUI, "subui", "subui", 32,
fb53f5a8 609 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 610 },
611/* mul $frdrrr,$frsr1,$frsr2 */
612 {
d031aafb 613 MT_INSN_MUL, "mul", "mul", 32,
6f84a2a6 614 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
ac188222
DB		 615 },
616/* muli $frdr,$frsr1,#$imm16 */
617 {
d031aafb 618 MT_INSN_MULI, "muli", "muli", 32,
6f84a2a6 619 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
ac188222
DB		 620 },
621/* and $frdrrr,$frsr1,$frsr2 */
622 {
d031aafb 623 MT_INSN_AND, "and", "and", 32,
fb53f5a8 624 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 625 },
626/* andi $frdr,$frsr1,#$imm16z */
627 {
d031aafb 628 MT_INSN_ANDI, "andi", "andi", 32,
fb53f5a8 629 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 630 },
631/* or $frdrrr,$frsr1,$frsr2 */
632 {
d031aafb 633 MT_INSN_OR, "or", "or", 32,
fb53f5a8 634 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 635 },
636/* nop */
637 {
d031aafb 638 MT_INSN_NOP, "nop", "nop", 32,
fb53f5a8 639 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 640 },
641/* ori $frdr,$frsr1,#$imm16z */
642 {
d031aafb 643 MT_INSN_ORI, "ori", "ori", 32,
fb53f5a8 644 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 645 },
646/* xor $frdrrr,$frsr1,$frsr2 */
647 {
d031aafb 648 MT_INSN_XOR, "xor", "xor", 32,
fb53f5a8 649 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 650 },
651/* xori $frdr,$frsr1,#$imm16z */
652 {
d031aafb 653 MT_INSN_XORI, "xori", "xori", 32,
fb53f5a8 654 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 655 },
656/* nand $frdrrr,$frsr1,$frsr2 */
657 {
d031aafb 658 MT_INSN_NAND, "nand", "nand", 32,
fb53f5a8 659 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 660 },
661/* nandi $frdr,$frsr1,#$imm16z */
662 {
d031aafb 663 MT_INSN_NANDI, "nandi", "nandi", 32,
fb53f5a8 664 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 665 },
666/* nor $frdrrr,$frsr1,$frsr2 */
667 {
d031aafb 668 MT_INSN_NOR, "nor", "nor", 32,
fb53f5a8 669 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 670 },
671/* nori $frdr,$frsr1,#$imm16z */
672 {
d031aafb 673 MT_INSN_NORI, "nori", "nori", 32,
fb53f5a8 674 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 675 },
676/* xnor $frdrrr,$frsr1,$frsr2 */
677 {
d031aafb 678 MT_INSN_XNOR, "xnor", "xnor", 32,
fb53f5a8 679 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 680 },
681/* xnori $frdr,$frsr1,#$imm16z */
682 {
d031aafb 683 MT_INSN_XNORI, "xnori", "xnori", 32,
fb53f5a8 684 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 685 },
686/* ldui $frdr,#$imm16z */
687 {
d031aafb 688 MT_INSN_LDUI, "ldui", "ldui", 32,
fb53f5a8 689 { 0|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 690 },
691/* lsl $frdrrr,$frsr1,$frsr2 */
692 {
d031aafb 693 MT_INSN_LSL, "lsl", "lsl", 32,
fb53f5a8 694 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 695 },
696/* lsli $frdr,$frsr1,#$imm16 */
697 {
d031aafb 698 MT_INSN_LSLI, "lsli", "lsli", 32,
fb53f5a8 699 { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 700 },
701/* lsr $frdrrr,$frsr1,$frsr2 */
702 {
d031aafb 703 MT_INSN_LSR, "lsr", "lsr", 32,
fb53f5a8 704 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 705 },
706/* lsri $frdr,$frsr1,#$imm16 */
707 {
d031aafb 708 MT_INSN_LSRI, "lsri", "lsri", 32,
fb53f5a8 709 { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 710 },
711/* asr $frdrrr,$frsr1,$frsr2 */
712 {
d031aafb 713 MT_INSN_ASR, "asr", "asr", 32,
fb53f5a8 714 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 715 },
716/* asri $frdr,$frsr1,#$imm16 */
717 {
d031aafb 718 MT_INSN_ASRI, "asri", "asri", 32,
fb53f5a8 719 { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 720 },
721/* brlt $frsr1,$frsr2,$imm16o */
722 {
d031aafb 723 MT_INSN_BRLT, "brlt", "brlt", 32,
fb53f5a8 724 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 725 },
726/* brle $frsr1,$frsr2,$imm16o */
727 {
d031aafb 728 MT_INSN_BRLE, "brle", "brle", 32,
fb53f5a8 729 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 730 },
731/* breq $frsr1,$frsr2,$imm16o */
732 {
d031aafb 733 MT_INSN_BREQ, "breq", "breq", 32,
fb53f5a8 734 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 735 },
736/* brne $frsr1,$frsr2,$imm16o */
737 {
d031aafb 738 MT_INSN_BRNE, "brne", "brne", 32,
fb53f5a8 739 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 740 },
741/* jmp $imm16o */
742 {
d031aafb 743 MT_INSN_JMP, "jmp", "jmp", 32,
fb53f5a8 744 { 0|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 745 },
746/* jal $frdrrr,$frsr1 */
747 {
d031aafb 748 MT_INSN_JAL, "jal", "jal", 32,
6f84a2a6 749 { 0|A(JAL_HAZARD)|A(USES_FRSR1)|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 750 },
751/* dbnz $frsr1,$imm16o */
752 {
d031aafb 753 MT_INSN_DBNZ, "dbnz", "dbnz", 32,
6f84a2a6 754 { 0|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
ac188222
DB		 755 },
756/* ei */
757 {
d031aafb 758 MT_INSN_EI, "ei", "ei", 32,
fb53f5a8 759 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 760 },
761/* di */
762 {
d031aafb 763 MT_INSN_DI, "di", "di", 32,
fb53f5a8 764 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 765 },
766/* si $frdrrr */
767 {
d031aafb 768 MT_INSN_SI, "si", "si", 32,
fb53f5a8 769 { 0|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 770 },
771/* reti $frsr1 */
772 {
d031aafb 773 MT_INSN_RETI, "reti", "reti", 32,
6f84a2a6 774 { 0|A(JAL_HAZARD)|A(USES_FRSR1)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 775 },
776/* ldw $frdr,$frsr1,#$imm16 */
777 {
d031aafb 778 MT_INSN_LDW, "ldw", "ldw", 32,
fb53f5a8 779 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(MEMORY_ACCESS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 780 },
781/* stw $frsr2,$frsr1,#$imm16 */
782 {
d031aafb 783 MT_INSN_STW, "stw", "stw", 32,
fb53f5a8 784 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(MEMORY_ACCESS), { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 785 },
786/* break */
787 {
d031aafb 788 MT_INSN_BREAK, "break", "break", 32,
fb53f5a8 789 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 790 },
791/* iflush */
792 {
d031aafb 793 MT_INSN_IFLUSH, "iflush", "iflush", 32,
6f84a2a6 794 { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
ac188222
DB		 795 },
796/* ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum */
797 {
d031aafb 798 MT_INSN_LDCTXT, "ldctxt", "ldctxt", 32,
6f84a2a6 799 { 0, { { { (1<<MACH_MS1), 0 } } } }
ac188222
DB		 800 },
801/* ldfb $frsr1,$frsr2,#$imm16z */
802 {
d031aafb 803 MT_INSN_LDFB, "ldfb", "ldfb", 32,
6f84a2a6 804 { 0, { { { (1<<MACH_MS1), 0 } } } }
ac188222
DB		 805 },
806/* stfb $frsr1,$frsr2,#$imm16z */
807 {
d031aafb 808 MT_INSN_STFB, "stfb", "stfb", 32,
6f84a2a6 809 { 0, { { { (1<<MACH_MS1), 0 } } } }
ac188222
DB		 810 },
811/* fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
812 {
d031aafb 813 MT_INSN_FBCB, "fbcb", "fbcb", 32,
6f84a2a6 814 { 0, { { { (1<<MACH_MS1)|(1<<MACH_MS1_003), 0 } } } }
ac188222
DB		 815 },
816/* mfbcb $frsr1,#$rbbc,$frsr2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
817 {
d031aafb 818 MT_INSN_MFBCB, "mfbcb", "mfbcb", 32,
fb53f5a8 819 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 820 },
821/* fbcci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
822 {
d031aafb 823 MT_INSN_FBCCI, "fbcci", "fbcci", 32,
fb53f5a8 824 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 825 },
826/* fbrci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
827 {
d031aafb 828 MT_INSN_FBRCI, "fbrci", "fbrci", 32,
fb53f5a8 829 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 830 },
831/* fbcri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
832 {
d031aafb 833 MT_INSN_FBCRI, "fbcri", "fbcri", 32,
fb53f5a8 834 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 835 },
836/* fbrri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
837 {
d031aafb 838 MT_INSN_FBRRI, "fbrri", "fbrri", 32,
fb53f5a8 839 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 840 },
841/* mfbcci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
842 {
d031aafb 843 MT_INSN_MFBCCI, "mfbcci", "mfbcci", 32,
fb53f5a8 844 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 845 },
846/* mfbrci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
847 {
d031aafb 848 MT_INSN_MFBRCI, "mfbrci", "mfbrci", 32,
fb53f5a8 849 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 850 },
851/* mfbcri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
852 {
d031aafb 853 MT_INSN_MFBCRI, "mfbcri", "mfbcri", 32,
fb53f5a8 854 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 855 },
856/* mfbrri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
857 {
d031aafb 858 MT_INSN_MFBRRI, "mfbrri", "mfbrri", 32,
fb53f5a8 859 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 860 },
861/* fbcbdr $frsr1,#$rbbc,$frsr2,#$ball2,#$brc2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
862 {
d031aafb 863 MT_INSN_FBCBDR, "fbcbdr", "fbcbdr", 32,
fb53f5a8 864 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 865 },
866/* rcfbcb #$rbbc,#$type,#$ball,#$brc,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
867 {
d031aafb 868 MT_INSN_RCFBCB, "rcfbcb", "rcfbcb", 32,
fb53f5a8 869 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 870 },
871/* mrcfbcb $frsr2,#$rbbc,#$type,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
872 {
d031aafb 873 MT_INSN_MRCFBCB, "mrcfbcb", "mrcfbcb", 32,
fb53f5a8 874 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 875 },
876/* cbcast #$mask,#$rc2,#$ctxdisp */
877 {
d031aafb 878 MT_INSN_CBCAST, "cbcast", "cbcast", 32,
fb53f5a8 879 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 880 },
881/* dupcbcast #$mask,#$cell,#$rc2,#$ctxdisp */
882 {
d031aafb 883 MT_INSN_DUPCBCAST, "dupcbcast", "dupcbcast", 32,
fb53f5a8 884 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 885 },
886/* wfbi #$bankaddr,#$rownum1,#$cell,#$dup,#$ctxdisp */
887 {
d031aafb 888 MT_INSN_WFBI, "wfbi", "wfbi", 32,
fb53f5a8 889 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 890 },
891/* wfb $frsr1,$frsr2,#$fbdisp,#$rownum2,#$ctxdisp */
892 {
d031aafb 893 MT_INSN_WFB, "wfb", "wfb", 32,
fb53f5a8 894 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 895 },
896/* rcrisc $frdrrr,#$rbbc,$frsr1,#$colnum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
897 {
d031aafb 898 MT_INSN_RCRISC, "rcrisc", "rcrisc", 32,
fb53f5a8 899 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 900 },
901/* fbcbinc $frsr1,#$rbbc,#$incamt,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
902 {
d031aafb 903 MT_INSN_FBCBINC, "fbcbinc", "fbcbinc", 32,
fb53f5a8 904 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 905 },
906/* rcxmode $frsr2,#$rda,#$wr,#$xmode,#$mask1,#$fbdisp,#$rownum2,#$rc2,#$ctxdisp */
907 {
d031aafb 908 MT_INSN_RCXMODE, "rcxmode", "rcxmode", 32,
fb53f5a8 909 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 910 },
911/* intlvr $frsr1,#$mode,$frsr2,#$id,#$size */
912 {
d031aafb 913 MT_INSN_INTERLEAVER, "interleaver", "intlvr", 32,
fb53f5a8 914 { 0, { { { (1<<MACH_BASE), 0 } } } }
ac188222
DB		 915 },
916/* wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
917 {
d031aafb 918 MT_INSN_WFBINC, "wfbinc", "wfbinc", 32,
6f84a2a6 919 { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
ac188222
DB		 920 },
921/* mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
922 {
d031aafb 923 MT_INSN_MWFBINC, "mwfbinc", "mwfbinc", 32,
6f84a2a6 924 { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
ac188222
DB		 925 },
926/* wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
927 {
d031aafb 928 MT_INSN_WFBINCR, "wfbincr", "wfbincr", 32,
6f84a2a6 929 { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
ac188222
DB		 930 },
931/* mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
932 {
d031aafb 933 MT_INSN_MWFBINCR, "mwfbincr", "mwfbincr", 32,
6f84a2a6 934 { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
ac188222
DB		 935 },
936/* fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
937 {
d031aafb 938 MT_INSN_FBCBINCS, "fbcbincs", "fbcbincs", 32,
6f84a2a6 939 { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
ac188222
DB		 940 },
941/* mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
942 {
d031aafb 943 MT_INSN_MFBCBINCS, "mfbcbincs", "mfbcbincs", 32,
6f84a2a6 944 { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
ac188222
DB		 945 },
946/* fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
947 {
d031aafb 948 MT_INSN_FBCBINCRS, "fbcbincrs", "fbcbincrs", 32,
6f84a2a6 949 { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
ac188222
DB		 950 },
951/* mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
952 {
d031aafb 953 MT_INSN_MFBCBINCRS, "mfbcbincrs", "mfbcbincrs", 32,
6f84a2a6
NS		 954 { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
955 },
956/* loop $frsr1,$loopsize */
957 {
d031aafb 958 MT_INSN_LOOP, "loop", "loop", 32,
6f84a2a6
NS		 959 { 0|A(USES_FRSR1)|A(DELAY_SLOT), { { { (1<<MACH_MS2), 0 } } } }
960 },
961/* loopi #$imm16l,$loopsize */
962 {
d031aafb 963 MT_INSN_LOOPI, "loopi", "loopi", 32,
6f84a2a6
NS		 964 { 0|A(DELAY_SLOT), { { { (1<<MACH_MS2), 0 } } } }
965 },
966/* dfbc #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */
967 {
d031aafb 968 MT_INSN_DFBC, "dfbc", "dfbc", 32,
6f84a2a6
NS		 969 { 0, { { { (1<<MACH_MS2), 0 } } } }
970 },
971/* dwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc2,#$ctxdisp */
972 {
d031aafb 973 MT_INSN_DWFB, "dwfb", "dwfb", 32,
6f84a2a6
NS		 974 { 0, { { { (1<<MACH_MS2), 0 } } } }
975 },
976/* fbwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */
977 {
d031aafb 978 MT_INSN_FBWFB, "fbwfb", "fbwfb", 32,
6f84a2a6
NS		 979 { 0, { { { (1<<MACH_MS2), 0 } } } }
980 },
981/* dfbr #$cb1sel,#$cb2sel,$frsr2,#$length,#$rownum1,#$rownum2,#$rc2,#$ctxdisp */
982 {
d031aafb 983 MT_INSN_DFBR, "dfbr", "dfbr", 32,
6f84a2a6 984 { 0|A(USES_FRSR2), { { { (1<<MACH_MS2), 0 } } } }
ac188222
DB		 985 },
986};
987
988#undef OP
989#undef A
990
991/* Initialize anything needed to be done once, before any cpu_open call. */
ac188222
DB		 992
993static void
47b0e7ad 994init_tables (void)
ac188222
DB		 995{
996}
997
47b0e7ad
NC		 998static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
999static void build_hw_table (CGEN_CPU_TABLE *);
1000static void build_ifield_table (CGEN_CPU_TABLE *);
1001static void build_operand_table (CGEN_CPU_TABLE *);
1002static void build_insn_table (CGEN_CPU_TABLE *);
d031aafb 1003static void mt_cgen_rebuild_tables (CGEN_CPU_TABLE *);
ac188222 1004
d031aafb 1005/* Subroutine of mt_cgen_cpu_open to look up a mach via its bfd name. */
ac188222
DB		 1006
1007static const CGEN_MACH *
47b0e7ad 1008lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
ac188222
DB		 1009{
1010 while (table->name)
1011 {
1012 if (strcmp (name, table->bfd_name) == 0)
1013 return table;
1014 ++table;
1015 }
1016 abort ();
1017}
1018
d031aafb 1019/* Subroutine of mt_cgen_cpu_open to build the hardware table. */
ac188222
DB		 1020
1021static void
47b0e7ad 1022build_hw_table (CGEN_CPU_TABLE *cd)
ac188222
DB		 1023{
1024 int i;
1025 int machs = cd->machs;
d031aafb 1026 const CGEN_HW_ENTRY *init = & mt_cgen_hw_table[0];
ac188222
DB		 1027 /* MAX_HW is only an upper bound on the number of selected entries.
1028 However each entry is indexed by it's enum so there can be holes in
1029 the table. */
1030 const CGEN_HW_ENTRY **selected =
1031 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1032
1033 cd->hw_table.init_entries = init;
1034 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1035 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1036 /* ??? For now we just use machs to determine which ones we want. */
1037 for (i = 0; init[i].name != NULL; ++i)
1038 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1039 & machs)
1040 selected[init[i].type] = &init[i];
1041 cd->hw_table.entries = selected;
1042 cd->hw_table.num_entries = MAX_HW;
1043}
1044
d031aafb 1045/* Subroutine of mt_cgen_cpu_open to build the hardware table. */
ac188222
DB		 1046
1047static void
47b0e7ad 1048build_ifield_table (CGEN_CPU_TABLE *cd)
ac188222 1049{
d031aafb 1050 cd->ifld_table = & mt_cgen_ifld_table[0];
ac188222
DB		 1051}
1052
d031aafb 1053/* Subroutine of mt_cgen_cpu_open to build the hardware table. */
ac188222
DB		 1054
1055static void
47b0e7ad 1056build_operand_table (CGEN_CPU_TABLE *cd)
ac188222
DB		 1057{
1058 int i;
1059 int machs = cd->machs;
d031aafb 1060 const CGEN_OPERAND *init = & mt_cgen_operand_table[0];
ac188222
DB		 1061 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1062 However each entry is indexed by it's enum so there can be holes in
1063 the table. */
47b0e7ad 1064 const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
ac188222
DB		 1065
1066 cd->operand_table.init_entries = init;
1067 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1068 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1069 /* ??? For now we just use mach to determine which ones we want. */
1070 for (i = 0; init[i].name != NULL; ++i)
1071 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1072 & machs)
1073 selected[init[i].type] = &init[i];
1074 cd->operand_table.entries = selected;
1075 cd->operand_table.num_entries = MAX_OPERANDS;
1076}
1077
d031aafb 1078/* Subroutine of mt_cgen_cpu_open to build the hardware table.
ac188222
DB		 1079 ??? This could leave out insns not supported by the specified mach/isa,
1080 but that would cause errors like "foo only supported by bar" to become
1081 "unknown insn", so for now we include all insns and require the app to
1082 do the checking later.
1083 ??? On the other hand, parsing of such insns may require their hardware or
1084 operand elements to be in the table [which they mightn't be]. */
1085
1086static void
47b0e7ad 1087build_insn_table (CGEN_CPU_TABLE *cd)
ac188222
DB		 1088{
1089 int i;
d031aafb 1090 const CGEN_IBASE *ib = & mt_cgen_insn_table[0];
47b0e7ad 1091 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
ac188222
DB		 1092
1093 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1094 for (i = 0; i < MAX_INSNS; ++i)
1095 insns[i].base = &ib[i];
1096 cd->insn_table.init_entries = insns;
1097 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1098 cd->insn_table.num_init_entries = MAX_INSNS;
1099}
1100
d031aafb 1101/* Subroutine of mt_cgen_cpu_open to rebuild the tables. */
ac188222
DB		 1102
1103static void
d031aafb 1104mt_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
ac188222
DB		 1105{
1106 int i;
fb53f5a8 1107 CGEN_BITSET *isas = cd->isas;
ac188222
DB		 1108 unsigned int machs = cd->machs;
1109
1110 cd->int_insn_p = CGEN_INT_INSN_P;
1111
1112 /* Data derived from the isa spec. */
1113#define UNSET (CGEN_SIZE_UNKNOWN + 1)
1114 cd->default_insn_bitsize = UNSET;
1115 cd->base_insn_bitsize = UNSET;
47b0e7ad 1116 cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
ac188222
DB		 1117 cd->max_insn_bitsize = 0;
1118 for (i = 0; i < MAX_ISAS; ++i)
fb53f5a8 1119 if (cgen_bitset_contains (isas, i))
ac188222 1120 {
d031aafb 1121 const CGEN_ISA *isa = & mt_cgen_isa_table[i];
ac188222
DB		 1122
1123 /* Default insn sizes of all selected isas must be
1124 equal or we set the result to 0, meaning "unknown". */
1125 if (cd->default_insn_bitsize == UNSET)
1126 cd->default_insn_bitsize = isa->default_insn_bitsize;
1127 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
47b0e7ad 1128 ; /* This is ok. */
ac188222
DB		 1129 else
1130 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1131
1132 /* Base insn sizes of all selected isas must be equal
1133 or we set the result to 0, meaning "unknown". */
1134 if (cd->base_insn_bitsize == UNSET)
1135 cd->base_insn_bitsize = isa->base_insn_bitsize;
1136 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
47b0e7ad 1137 ; /* This is ok. */
ac188222
DB		 1138 else
1139 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1140
1141 /* Set min,max insn sizes. */
1142 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1143 cd->min_insn_bitsize = isa->min_insn_bitsize;
1144 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1145 cd->max_insn_bitsize = isa->max_insn_bitsize;
1146 }
1147
1148 /* Data derived from the mach spec. */
1149 for (i = 0; i < MAX_MACHS; ++i)
1150 if (((1 << i) & machs) != 0)
1151 {
d031aafb 1152 const CGEN_MACH *mach = & mt_cgen_mach_table[i];
ac188222
DB		 1153
1154 if (mach->insn_chunk_bitsize != 0)
1155 {
1156 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1157 {
d031aafb 1158 fprintf (stderr, "mt_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
ac188222
DB		 1159 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1160 abort ();
1161 }
1162
1163 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1164 }
1165 }
1166
1167 /* Determine which hw elements are used by MACH. */
1168 build_hw_table (cd);
1169
1170 /* Build the ifield table. */
1171 build_ifield_table (cd);
1172
1173 /* Determine which operands are used by MACH/ISA. */
1174 build_operand_table (cd);
1175
1176 /* Build the instruction table. */
1177 build_insn_table (cd);
1178}
1179
1180/* Initialize a cpu table and return a descriptor.
1181 It's much like opening a file, and must be the first function called.
1182 The arguments are a set of (type/value) pairs, terminated with
1183 CGEN_CPU_OPEN_END.
1184
1185 Currently supported values:
1186 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
1187 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
1188 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1189 CGEN_CPU_OPEN_ENDIAN: specify endian choice
1190 CGEN_CPU_OPEN_END: terminates arguments
1191
1192 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1193 precluded.
1194
1195 ??? We only support ISO C stdargs here, not K&R.
1196 Laziness, plus experiment to see if anything requires K&R - eventually
1197 K&R will no longer be supported - e.g. GDB is currently trying this. */
1198
1199CGEN_CPU_DESC
d031aafb 1200mt_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
ac188222
DB		 1201{
1202 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1203 static int init_p;
fb53f5a8 1204 CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
ac188222
DB		 1205 unsigned int machs = 0; /* 0 = "unspecified" */
1206 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1207 va_list ap;
1208
1209 if (! init_p)
1210 {
1211 init_tables ();
1212 init_p = 1;
1213 }
1214
1215 memset (cd, 0, sizeof (*cd));
1216
1217 va_start (ap, arg_type);
1218 while (arg_type != CGEN_CPU_OPEN_END)
1219 {
1220 switch (arg_type)
1221 {
1222 case CGEN_CPU_OPEN_ISAS :
fb53f5a8 1223 isas = va_arg (ap, CGEN_BITSET *);
ac188222
DB		 1224 break;
1225 case CGEN_CPU_OPEN_MACHS :
1226 machs = va_arg (ap, unsigned int);
1227 break;
1228 case CGEN_CPU_OPEN_BFDMACH :
1229 {
1230 const char *name = va_arg (ap, const char *);
1231 const CGEN_MACH *mach =
d031aafb 1232 lookup_mach_via_bfd_name (mt_cgen_mach_table, name);
ac188222
DB		 1233
1234 machs |= 1 << mach->num;
1235 break;
1236 }
1237 case CGEN_CPU_OPEN_ENDIAN :
1238 endian = va_arg (ap, enum cgen_endian);
1239 break;
1240 default :
d031aafb 1241 fprintf (stderr, "mt_cgen_cpu_open: unsupported argument `%d'\n",
ac188222
DB		 1242 arg_type);
1243 abort (); /* ??? return NULL? */
1244 }
1245 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1246 }
1247 va_end (ap);
1248
47b0e7ad 1249 /* Mach unspecified means "all". */
ac188222
DB		 1250 if (machs == 0)
1251 machs = (1 << MAX_MACHS) - 1;
47b0e7ad 1252 /* Base mach is always selected. */
ac188222 1253 machs |= 1;
ac188222
DB		 1254 if (endian == CGEN_ENDIAN_UNKNOWN)
1255 {
1256 /* ??? If target has only one, could have a default. */
d031aafb 1257 fprintf (stderr, "mt_cgen_cpu_open: no endianness specified\n");
ac188222
DB		 1258 abort ();
1259 }
1260
fb53f5a8 1261 cd->isas = cgen_bitset_copy (isas);
ac188222
DB		 1262 cd->machs = machs;
1263 cd->endian = endian;
1264 /* FIXME: for the sparc case we can determine insn-endianness statically.
1265 The worry here is where both data and insn endian can be independently
1266 chosen, in which case this function will need another argument.
1267 Actually, will want to allow for more arguments in the future anyway. */
1268 cd->insn_endian = endian;
1269
1270 /* Table (re)builder. */
d031aafb
NS		 1271 cd->rebuild_tables = mt_cgen_rebuild_tables;
1272 mt_cgen_rebuild_tables (cd);
ac188222
DB		 1273
1274 /* Default to not allowing signed overflow. */
1275 cd->signed_overflow_ok_p = 0;
1276
1277 return (CGEN_CPU_DESC) cd;
1278}
1279
d031aafb 1280/* Cover fn to mt_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
ac188222
DB		 1281 MACH_NAME is the bfd name of the mach. */
1282
1283CGEN_CPU_DESC
d031aafb 1284mt_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
ac188222 1285{
d031aafb 1286 return mt_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
ac188222
DB		 1287 CGEN_CPU_OPEN_ENDIAN, endian,
1288 CGEN_CPU_OPEN_END);
1289}
1290
1291/* Close a cpu table.
1292 ??? This can live in a machine independent file, but there's currently
1293 no place to put this file (there's no libcgen). libopcodes is the wrong
1294 place as some simulator ports use this but they don't use libopcodes. */
1295
1296void
d031aafb 1297mt_cgen_cpu_close (CGEN_CPU_DESC cd)
ac188222
DB		 1298{
1299 unsigned int i;
1300 const CGEN_INSN *insns;
1301
1302 if (cd->macro_insn_table.init_entries)
1303 {
1304 insns = cd->macro_insn_table.init_entries;
1305 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
47b0e7ad
NC		 1306 if (CGEN_INSN_RX ((insns)))
1307 regfree (CGEN_INSN_RX (insns));
ac188222
DB		 1308 }
1309
1310 if (cd->insn_table.init_entries)
1311 {
1312 insns = cd->insn_table.init_entries;
1313 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
47b0e7ad
NC		 1314 if (CGEN_INSN_RX (insns))
1315 regfree (CGEN_INSN_RX (insns));
1316 }
ac188222
DB		 1317
1318 if (cd->macro_insn_table.init_entries)
1319 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1320
1321 if (cd->insn_table.init_entries)
1322 free ((CGEN_INSN *) cd->insn_table.init_entries);
1323
1324 if (cd->hw_table.entries)
1325 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1326
1327 if (cd->operand_table.entries)
1328 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
1329
1330 free (cd);
1331}
1332
GDB Binutils - Deliverables
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