[deliverable/binutils-gdb.git] / opcodes / nds32-asm.h

/* NDS32-specific support for 32-bit ELF.
   Copyright (C) 2012-2020 Free Software Foundation, Inc.
   Contributed by Andes Technology Corporation.

   This file is part of BFD, the Binary File Descriptor library.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
   02110-1301, USA.  */


#ifndef NDS32_ASM_H
#define NDS32_ASM_H

#ifdef __cplusplus
extern "C" {
#endif

/* Constant values for assembler.  */
enum
{
  /* Error code for assembling an instruction.  */
  NASM_OK = 0,
  NASM_ERR_UNKNOWN_OP,
  NASM_ERR_SYNTAX,
  NASM_ERR_OPERAND,
  NASM_ERR_OUT_OF_RANGE,
  NASM_ERR_REG_REDUCED,
  NASM_ERR_JUNK_EOL,

  /* Results of parse_operand.  */
  NASM_R_CONST,
  NASM_R_SYMBOL,
  NASM_R_ILLEGAL,

  /* Flags for open description.  */
  NASM_OPEN_ARCH_V1		= 0x0,
  NASM_OPEN_ARCH_V2		= 0x1,
  NASM_OPEN_ARCH_V3		= 0x2,
  NASM_OPEN_ARCH_V3M		= 0x3,
  NASM_OPEN_ARCH_MASK		= 0xf,
  NASM_OPEN_REDUCED_REG		= 0x10,

  /* Common attributes.  */
  NASM_ATTR_ISA_V1		= 0x01,
  NASM_ATTR_ISA_V2		= 0x02,
  NASM_ATTR_ISA_V3		= 0x04,
  NASM_ATTR_ISA_V3M		= 0x08,
  NASM_ATTR_ISA_ALL		= 0x0f,

  /* Attributes for instructions.  */
  NASM_ATTR_MAC			= 0x0000100,
  NASM_ATTR_DIV			= 0x0000200,
  NASM_ATTR_FPU			= 0x0000400,
  NASM_ATTR_FPU_SP_EXT		= 0x0000800,
  NASM_ATTR_FPU_DP_EXT		= 0x0001000,
  NASM_ATTR_STR_EXT		= 0x0002000,
  NASM_ATTR_PERF_EXT		= 0x0004000,
  NASM_ATTR_PERF2_EXT		= 0x0008000,
  NASM_ATTR_AUDIO_ISAEXT	= 0x0010000,
  NASM_ATTR_IFC_EXT		= 0x0020000,
  NASM_ATTR_EX9_EXT		= 0x0040000,
  NASM_ATTR_FPU_FMA		= 0x0080000,
  NASM_ATTR_DXREG		= 0x0100000,
  NASM_ATTR_BRANCH		= 0x0200000,
  NASM_ATTR_SATURATION_EXT	= 0x0400000,
  NASM_ATTR_PCREL		= 0x0800000,
  NASM_ATTR_GPREL		= 0x1000000,
  NASM_ATTR_DSP_ISAEXT		= 0x2000000,
  NASM_ATTR_ZOL			= (1 << 26),

  /* Attributes for relocations.  */
  NASM_ATTR_HI20		= 0x10000000,
  NASM_ATTR_LO12		= 0x20000000,
  NASM_ATTR_LO20		= 0x40000000,

  /* Attributes for registers.  */
  NASM_ATTR_RDREG		= 0x000100
};

/* We only support one core for now.  */
#define NDS32_CORE_COUNT	1
#define NDS32_MAIN_CORE		0

enum
{
  /* This operand is used for input or output.  (define or use)  */
  SYN_INPUT = 0x10000,
  SYN_OUTPUT = 0x20000,
  SYN_LOPT = 0x40000,
  SYN_ROPT = 0x80000,

  /* Hardware resources:
     Current set up allows up to 256 resources for each class
     defined above.  */
  HW_GPR = NDS32_MAIN_CORE << 8,
  HW_USR,
  HW_DXR,
  HW_SR,
  HW_FSR,
  HW_FDR,
  HW_CP,	/* Co-processor ID.  */
  HW_CPR,	/* Co-processor registers.  */
  HW_ABDIM,	/* [ab][di]m? flag for LSMWA?.  */
  HW_ABM,	/* [ab]m? flag for LSMWZB.  */
  HW_DTITON,
  HW_DTITOFF,
  HW_DPREF_ST,
  HW_CCTL_ST0,
  HW_CCTL_ST1,
  HW_CCTL_ST2,
  HW_CCTL_ST3,
  HW_CCTL_ST4,
  HW_CCTL_ST5,
  HW_CCTL_LV,
  HW_TLBOP_ST,
  HW_STANDBY_ST,
  HW_MSYNC_ST,
  HW_AEXT_IM_I,
  HW_AEXT_IM_M,
  HW_AEXT_ACC,
  HW_AEXT_ARIDX,
  HW_AEXT_ARIDX2,
  HW_AEXT_ARIDXI,
  HW_AEXT_ARIDXI_MX,
  _HW_LAST,
  HW_INT = 0x1000,
  HW_UINT
};

/* for audio-extension.  */
enum
{
  N32_AEXT_AMADD = 0,
  N32_AEXT_AMSUB,
  N32_AEXT_AMULT,
  N32_AEXT_AMFAR,
  N32_AEXT_AMADDS,
  N32_AEXT_AMSUBS,
  N32_AEXT_AMULTS,
  N32_AEXT_AMNEGS,
  N32_AEXT_AADDL,
  N32_AEXT_AMTARI,
  N32_AEXT_AMAWBS = 0x0c,
  N32_AEXT_AMAWTS,
  N32_AEXT_AMWBS,
  N32_AEXT_AMWTS,
  N32_AEXT_AMABBS,
  N32_AEXT_AMABTS,
  N32_AEXT_AMATBS,
  N32_AEXT_AMATTS,
  N32_AEXT_AMBBS,
  N32_AEXT_AMBTS,
  N32_AEXT_AMTBS,
  N32_AEXT_AMTTS
};

/* Macro for instruction attribute.  */
#define ATTR(attr)		NASM_ATTR_ ## attr
#define ATTR_NONE		0
#define ATTR_PCREL		(ATTR (PCREL) | ATTR (BRANCH))

#define ATTR_ALL		(ATTR (ISA_ALL))
#define ATTR_V2UP		(ATTR_ALL & ~(ATTR (ISA_V1)))
#define ATTR_V3MUP		(ATTR (ISA_V3) | ATTR (ISA_V3M))
#define ATTR_V3			(ATTR (ISA_V3))
#define ATTR_V3MEX_V1		(ATTR_ALL & ~(ATTR (ISA_V3M)))
#define ATTR_V3MEX_V2		(ATTR_V2UP & ~(ATTR (ISA_V3M)))

/* Lexical element in parsed syntax.  */
typedef int lex_t;

/* Common header for hash entries.  */
struct nds32_hash_entry
{
  const char *name;
};

typedef struct nds32_keyword
{
  const char *name;
  int value;
  uint64_t attr;
} keyword_t;

typedef struct nds32_opcode
{
  /* Opcode for the instruction.  */
  const char *opcode;
  /* Human readable string of this instruction.  */
  const char *instruction;
  /* Base value of this instruction.  */
  uint32_t value;
  /* The byte-size of the instruction.  */
  int isize;
  /* Attributes of this instruction.  */
  uint64_t attr;
  /* Implicit define/use.  */
  uint64_t defuse;
  /* Parsed string for assembling.  */
  lex_t *syntax;
  /* Number of variant.  */
  int variant;
  /* Next form of the same mnemonic.  */
  struct nds32_opcode *next;

  /* TODO: Extra constrains and verification.
	   For example, `mov55 $sp, $sp' is not allowed in v3.  */
} opcode_t;

typedef struct nds32_asm_insn
{
  /* Assembled instruction bytes.  */
  uint32_t insn;
  /* The opcode structure for this instruction.  */
  struct nds32_opcode *opcode;
  /* The field need special fix-up, used for relocation.  */
  const struct nds32_field *field;
  /* Attributes for relocation.  */
  uint64_t attr;
  /* Application-dependent data, e.g., expression.  */
  void *info;
  /* Input/output registers.  */
  uint64_t defuse;
} nds32_asm_insn_t;

typedef struct nds32_asm_desc
{
  /* The callback provided by assembler user for parse an operand,
     e.g., parse integer.  */
  int (*parse_operand) (struct nds32_asm_desc *,
			struct nds32_asm_insn *,
			char **, int64_t *);

  /* Result of assembling.  */
  int result;

  /* The mach for this assembling.  */
  int mach;

  int flags;
} nds32_asm_desc_t;

/* The field information for an operand.  */
typedef struct nds32_field
{
  /* Name of the field.  */
  const char *name;

  int bitpos;
  int bitsize;
  int shift;
  int hw_res;

  int (*parse) (struct nds32_asm_desc *,
		struct nds32_asm_insn *,
		char **, int64_t *);
} field_t;

extern void nds32_assemble (nds32_asm_desc_t *, nds32_asm_insn_t *, char *);
extern void nds32_asm_init (nds32_asm_desc_t *, int);

#define OP6(op6)	(N32_OP6_ ## op6 << 25)

#define LSMW(sub)	(OP6 (LSMW) | N32_LSMW_ ## sub)
#define JREG(sub)	(OP6 (JREG) | N32_JREG_ ## sub)
#define JREG_RET	(1 << 5)
#define JREG_IFC	(1 << 6)
#define BR2(sub)	(OP6 (BR2) | (N32_BR2_ ## sub << 16))
#define SIMD(sub)	(OP6 (SIMD) | N32_SIMD_ ## sub)
#define ALU1(sub)	(OP6 (ALU1) | N32_ALU1_ ## sub)
#define ALU2(sub)	(OP6 (ALU2) | N32_ALU2_ ## sub)
#define ALU2_1(sub)	(OP6 (ALU2) | N32_BIT (6) | N32_ALU2_ ## sub)
#define ALU2_2(sub)	(OP6 (ALU2) | N32_BIT (7) | N32_ALU2_ ## sub)
#define ALU2_3(sub)	(OP6 (ALU2) | N32_BIT (6) | N32_BIT (7) | N32_ALU2_ ## sub)
#define MISC(sub)	(OP6 (MISC) | N32_MISC_ ## sub)
#define MEM(sub)	(OP6 (MEM) | N32_MEM_ ## sub)
#define FPU_RA_IMMBI(sub)	(OP6 (sub) | N32_BIT (12))
#define FS1(sub)	(OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_ ## sub << 6))
#define FS1_F2OP(sub)	(OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_F2OP << 6) \
			| (N32_FPU_FS1_F2OP_ ## sub << 10))
#define FS2(sub) 	(OP6 (COP) | N32_FPU_FS2 | (N32_FPU_FS2_ ## sub << 6))
#define FD1(sub)	(OP6 (COP) | N32_FPU_FD1 | (N32_FPU_FD1_ ## sub << 6))
#define FD1_F2OP(sub)	(OP6 (COP) | N32_FPU_FD1 | (N32_FPU_FD1_F2OP << 6) \
			| (N32_FPU_FD1_F2OP_ ## sub << 10))
#define FD2(sub)	(OP6 (COP) | N32_FPU_FD2 | (N32_FPU_FD2_ ## sub << 6))
#define MFCP(sub)	(OP6 (COP) | N32_FPU_MFCP | (N32_FPU_MFCP_ ## sub << 6))
#define MFCP_XR(sub)	(OP6 (COP) | N32_FPU_MFCP | (N32_FPU_MFCP_XR << 6) \
			| (N32_FPU_MFCP_XR_ ## sub << 10))
#define MTCP(sub)	(OP6 (COP) | N32_FPU_MTCP | (N32_FPU_MTCP_ ## sub << 6))
#define MTCP_XR(sub)	(OP6 (COP) | N32_FPU_MTCP | (N32_FPU_MTCP_XR << 6) \
			| (N32_FPU_MTCP_XR_ ## sub << 10))
#define FPU_MEM(sub)	(OP6 (COP) | N32_FPU_ ## sub)
#define FPU_MEMBI(sub)	(OP6 (COP) | N32_FPU_ ## sub | 0x1 << 7)
#define AUDIO(sub)	(OP6 (AEXT) | (N32_AEXT_ ## sub << 20))

#ifdef __cplusplus
}
#endif

#endif
Commit	Line	Data
35c08157	1	/* NDS32-specific support for 32-bit ELF.
b3adc24a	2	Copyright (C) 2012-2020 Free Software Foundation, Inc.
35c08157 KLC	3	Contributed by Andes Technology Corporation.
	4
	5	This file is part of BFD, the Binary File Descriptor library.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 3 of the License, or
	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this program; if not, write to the Free Software
	19	Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
40c7a7cb	20	02110-1301, USA. */
35c08157 KLC	21
	22
	23	#ifndef NDS32_ASM_H
	24	#define NDS32_ASM_H
	25
1fe0971e TS	26	#ifdef __cplusplus
	27	extern "C" {
	28	#endif
	29
35c08157 KLC	30	/* Constant values for assembler. */
	31	enum
	32	{
	33	/* Error code for assembling an instruction. */
	34	NASM_OK = 0,
	35	NASM_ERR_UNKNOWN_OP,
	36	NASM_ERR_SYNTAX,
	37	NASM_ERR_OPERAND,
	38	NASM_ERR_OUT_OF_RANGE,
	39	NASM_ERR_REG_REDUCED,
	40	NASM_ERR_JUNK_EOL,
	41
	42	/* Results of parse_operand. */
	43	NASM_R_CONST,
	44	NASM_R_SYMBOL,
	45	NASM_R_ILLEGAL,
	46
	47	/* Flags for open description. */
	48	NASM_OPEN_ARCH_V1 = 0x0,
	49	NASM_OPEN_ARCH_V2 = 0x1,
	50	NASM_OPEN_ARCH_V3 = 0x2,
	51	NASM_OPEN_ARCH_V3M = 0x3,
	52	NASM_OPEN_ARCH_MASK = 0xf,
	53	NASM_OPEN_REDUCED_REG = 0x10,
	54
	55	/* Common attributes. */
	56	NASM_ATTR_ISA_V1 = 0x01,
	57	NASM_ATTR_ISA_V2 = 0x02,
	58	NASM_ATTR_ISA_V3 = 0x04,
	59	NASM_ATTR_ISA_V3M = 0x08,
	60	NASM_ATTR_ISA_ALL = 0x0f,
	61
	62	/* Attributes for instructions. */
	63	NASM_ATTR_MAC = 0x0000100,
	64	NASM_ATTR_DIV = 0x0000200,
	65	NASM_ATTR_FPU = 0x0000400,
	66	NASM_ATTR_FPU_SP_EXT = 0x0000800,
	67	NASM_ATTR_FPU_DP_EXT = 0x0001000,
	68	NASM_ATTR_STR_EXT = 0x0002000,
	69	NASM_ATTR_PERF_EXT = 0x0004000,
	70	NASM_ATTR_PERF2_EXT = 0x0008000,
	71	NASM_ATTR_AUDIO_ISAEXT = 0x0010000,
	72	NASM_ATTR_IFC_EXT = 0x0020000,
	73	NASM_ATTR_EX9_EXT = 0x0040000,
	74	NASM_ATTR_FPU_FMA = 0x0080000,
	75	NASM_ATTR_DXREG = 0x0100000,
	76	NASM_ATTR_BRANCH = 0x0200000,
40c7a7cb	77	NASM_ATTR_SATURATION_EXT = 0x0400000,
35c08157 KLC	78	NASM_ATTR_PCREL = 0x0800000,
35c08157 KLC	79	NASM_ATTR_GPREL = 0x1000000,
fbaf61ad NC	80	NASM_ATTR_DSP_ISAEXT = 0x2000000,
fbaf61ad NC	81	NASM_ATTR_ZOL = (1 << 26),
35c08157 KLC	82
	83	/* Attributes for relocations. */
	84	NASM_ATTR_HI20 = 0x10000000,
	85	NASM_ATTR_LO12 = 0x20000000,
	86	NASM_ATTR_LO20 = 0x40000000,
	87
	88	/* Attributes for registers. */
	89	NASM_ATTR_RDREG = 0x000100
	90	};
	91
fbaf61ad NC	92	/* We only support one core for now. */
	93	#define NDS32_CORE_COUNT 1
	94	#define NDS32_MAIN_CORE 0
	95
40c7a7cb KLC	96	enum
40c7a7cb KLC	97	{
40c7a7cb	98	/* This operand is used for input or output. (define or use) */
fbaf61ad NC	99	SYN_INPUT = 0x10000,
	100	SYN_OUTPUT = 0x20000,
	101	SYN_LOPT = 0x40000,
	102	SYN_ROPT = 0x80000,
	103
	104	/* Hardware resources:
	105	Current set up allows up to 256 resources for each class
	106	defined above. */
	107	HW_GPR = NDS32_MAIN_CORE << 8,
40c7a7cb KLC	108	HW_USR,
	109	HW_DXR,
	110	HW_SR,
	111	HW_FSR,
	112	HW_FDR,
	113	HW_CP, /* Co-processor ID. */
	114	HW_CPR, /* Co-processor registers. */
	115	HW_ABDIM, /* [ab][di]m? flag for LSMWA?. */
	116	HW_ABM, /* [ab]m? flag for LSMWZB. */
	117	HW_DTITON,
	118	HW_DTITOFF,
	119	HW_DPREF_ST,
	120	HW_CCTL_ST0,
	121	HW_CCTL_ST1,
	122	HW_CCTL_ST2,
	123	HW_CCTL_ST3,
	124	HW_CCTL_ST4,
	125	HW_CCTL_ST5,
	126	HW_CCTL_LV,
	127	HW_TLBOP_ST,
	128	HW_STANDBY_ST,
	129	HW_MSYNC_ST,
	130	HW_AEXT_IM_I,
	131	HW_AEXT_IM_M,
	132	HW_AEXT_ACC,
	133	HW_AEXT_ARIDX,
	134	HW_AEXT_ARIDX2,
	135	HW_AEXT_ARIDXI,
fbaf61ad	136	HW_AEXT_ARIDXI_MX,
40c7a7cb	137	_HW_LAST,
fbaf61ad	138	HW_INT = 0x1000,
40c7a7cb KLC	139	HW_UINT
	140	};
	141
	142	/* for audio-extension. */
	143	enum
	144	{
	145	N32_AEXT_AMADD = 0,
	146	N32_AEXT_AMSUB,
	147	N32_AEXT_AMULT,
	148	N32_AEXT_AMFAR,
	149	N32_AEXT_AMADDS,
	150	N32_AEXT_AMSUBS,
	151	N32_AEXT_AMULTS,
	152	N32_AEXT_AMNEGS,
	153	N32_AEXT_AADDL,
	154	N32_AEXT_AMTARI,
	155	N32_AEXT_AMAWBS = 0x0c,
	156	N32_AEXT_AMAWTS,
	157	N32_AEXT_AMWBS,
	158	N32_AEXT_AMWTS,
	159	N32_AEXT_AMABBS,
	160	N32_AEXT_AMABTS,
	161	N32_AEXT_AMATBS,
	162	N32_AEXT_AMATTS,
	163	N32_AEXT_AMBBS,
	164	N32_AEXT_AMBTS,
	165	N32_AEXT_AMTBS,
	166	N32_AEXT_AMTTS
	167	};
	168
35c08157 KLC	169	/* Macro for instruction attribute. */
	170	#define ATTR(attr) NASM_ATTR_ ## attr
	171	#define ATTR_NONE 0
	172	#define ATTR_PCREL (ATTR (PCREL) \| ATTR (BRANCH))
	173
	174	#define ATTR_ALL (ATTR (ISA_ALL))
	175	#define ATTR_V2UP (ATTR_ALL & ~(ATTR (ISA_V1)))
	176	#define ATTR_V3MUP (ATTR (ISA_V3) \| ATTR (ISA_V3M))
	177	#define ATTR_V3 (ATTR (ISA_V3))
	178	#define ATTR_V3MEX_V1 (ATTR_ALL & ~(ATTR (ISA_V3M)))
	179	#define ATTR_V3MEX_V2 (ATTR_V2UP & ~(ATTR (ISA_V3M)))
	180
	181	/* Lexical element in parsed syntax. */
	182	typedef int lex_t;
	183
	184	/* Common header for hash entries. */
	185	struct nds32_hash_entry
	186	{
	187	const char *name;
	188	};
	189
	190	typedef struct nds32_keyword
	191	{
	192	const char *name;
	193	int value;
	194	uint64_t attr;
	195	} keyword_t;
	196
	197	typedef struct nds32_opcode
	198	{
	199	/* Opcode for the instruction. */
	200	const char *opcode;
	201	/* Human readable string of this instruction. */
	202	const char *instruction;
	203	/* Base value of this instruction. */
	204	uint32_t value;
	205	/* The byte-size of the instruction. */
	206	int isize;
	207	/* Attributes of this instruction. */
	208	uint64_t attr;
	209	/* Implicit define/use. */
	210	uint64_t defuse;
	211	/* Parsed string for assembling. */
	212	lex_t *syntax;
	213	/* Number of variant. */
	214	int variant;
	215	/* Next form of the same mnemonic. */
	216	struct nds32_opcode *next;
40c7a7cb	217
35c08157 KLC	218	/* TODO: Extra constrains and verification.
	219	For example, `mov55 $sp, $sp' is not allowed in v3. */
	220	} opcode_t;
	221
	222	typedef struct nds32_asm_insn
	223	{
	224	/* Assembled instruction bytes. */
	225	uint32_t insn;
	226	/* The opcode structure for this instruction. */
	227	struct nds32_opcode *opcode;
	228	/* The field need special fix-up, used for relocation. */
	229	const struct nds32_field *field;
	230	/* Attributes for relocation. */
	231	uint64_t attr;
	232	/* Application-dependent data, e.g., expression. */
	233	void *info;
	234	/* Input/output registers. */
	235	uint64_t defuse;
	236	} nds32_asm_insn_t;
	237
	238	typedef struct nds32_asm_desc
	239	{
	240	/* The callback provided by assembler user for parse an operand,
	241	e.g., parse integer. */
	242	int (parse_operand) (struct nds32_asm_desc ,
	243	struct nds32_asm_insn *,
	244	char *, int64_t );
	245
	246	/* Result of assembling. */
	247	int result;
	248
	249	/* The mach for this assembling. */
	250	int mach;
	251
	252	int flags;
	253	} nds32_asm_desc_t;
	254
	255	/* The field information for an operand. */
	256	typedef struct nds32_field
	257	{
	258	/* Name of the field. */
	259	const char *name;
	260
	261	int bitpos;
	262	int bitsize;
	263	int shift;
	264	int hw_res;
	265
	266	int (parse) (struct nds32_asm_desc ,
	267	struct nds32_asm_insn *,
	268	char *, int64_t );
	269	} field_t;
	270
	271	extern void nds32_assemble (nds32_asm_desc_t , nds32_asm_insn_t , char *);
	272	extern void nds32_asm_init (nds32_asm_desc_t *, int);
	273
40c7a7cb KLC	274	#define OP6(op6) (N32_OP6_ ## op6 << 25)
	275
	276	#define LSMW(sub) (OP6 (LSMW) \| N32_LSMW_ ## sub)
	277	#define JREG(sub) (OP6 (JREG) \| N32_JREG_ ## sub)
	278	#define JREG_RET (1 << 5)
	279	#define JREG_IFC (1 << 6)
	280	#define BR2(sub) (OP6 (BR2) \| (N32_BR2_ ## sub << 16))
	281	#define SIMD(sub) (OP6 (SIMD) \| N32_SIMD_ ## sub)
	282	#define ALU1(sub) (OP6 (ALU1) \| N32_ALU1_ ## sub)
	283	#define ALU2(sub) (OP6 (ALU2) \| N32_ALU2_ ## sub)
fbaf61ad NC	284	#define ALU2_1(sub) (OP6 (ALU2) \| N32_BIT (6) \| N32_ALU2_ ## sub)
	285	#define ALU2_2(sub) (OP6 (ALU2) \| N32_BIT (7) \| N32_ALU2_ ## sub)
	286	#define ALU2_3(sub) (OP6 (ALU2) \| N32_BIT (6) \| N32_BIT (7) \| N32_ALU2_ ## sub)
40c7a7cb KLC	287	#define MISC(sub) (OP6 (MISC) \| N32_MISC_ ## sub)
40c7a7cb KLC	288	#define MEM(sub) (OP6 (MEM) \| N32_MEM_ ## sub)
4ec521f2	289	#define FPU_RA_IMMBI(sub) (OP6 (sub) \| N32_BIT (12))
40c7a7cb KLC	290	#define FS1(sub) (OP6 (COP) \| N32_FPU_FS1 \| (N32_FPU_FS1_ ## sub << 6))
	291	#define FS1_F2OP(sub) (OP6 (COP) \| N32_FPU_FS1 \| (N32_FPU_FS1_F2OP << 6) \
	292	\| (N32_FPU_FS1_F2OP_ ## sub << 10))
	293	#define FS2(sub) (OP6 (COP) \| N32_FPU_FS2 \| (N32_FPU_FS2_ ## sub << 6))
	294	#define FD1(sub) (OP6 (COP) \| N32_FPU_FD1 \| (N32_FPU_FD1_ ## sub << 6))
	295	#define FD1_F2OP(sub) (OP6 (COP) \| N32_FPU_FD1 \| (N32_FPU_FD1_F2OP << 6) \
	296	\| (N32_FPU_FD1_F2OP_ ## sub << 10))
	297	#define FD2(sub) (OP6 (COP) \| N32_FPU_FD2 \| (N32_FPU_FD2_ ## sub << 6))
	298	#define MFCP(sub) (OP6 (COP) \| N32_FPU_MFCP \| (N32_FPU_MFCP_ ## sub << 6))
	299	#define MFCP_XR(sub) (OP6 (COP) \| N32_FPU_MFCP \| (N32_FPU_MFCP_XR << 6) \
	300	\| (N32_FPU_MFCP_XR_ ## sub << 10))
	301	#define MTCP(sub) (OP6 (COP) \| N32_FPU_MTCP \| (N32_FPU_MTCP_ ## sub << 6))
	302	#define MTCP_XR(sub) (OP6 (COP) \| N32_FPU_MTCP \| (N32_FPU_MTCP_XR << 6) \
	303	\| (N32_FPU_MTCP_XR_ ## sub << 10))
	304	#define FPU_MEM(sub) (OP6 (COP) \| N32_FPU_ ## sub)
	305	#define FPU_MEMBI(sub) (OP6 (COP) \| N32_FPU_ ## sub \| 0x1 << 7)
	306	#define AUDIO(sub) (OP6 (AEXT) \| (N32_AEXT_ ## sub << 20))
	307
1fe0971e TS	308	#ifdef __cplusplus
	309	}
	310	#endif
	311
35c08157	312	#endif