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Use disassemble.c:disassembler select rs6000 disassembler
[deliverable/binutils-gdb.git] / opcodes / nios2-dis.c
CommitLineData
36591ba1 1/* Altera Nios II disassemble routines
2571583a 2 Copyright (C) 2012-2017 Free Software Foundation, Inc.
36591ba1
SL		 3 Contributed by Nigel Gray (ngray@altera.com).
4 Contributed by Mentor Graphics, Inc.
5
6 This file is part of the GNU opcodes library.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23#include "sysdep.h"
24#include "dis-asm.h"
25#include "opcode/nios2.h"
26#include "libiberty.h"
27#include <string.h>
28#include <assert.h>
29
30/* No symbol table is available when this code runs out in an embedded
31 system as when it is used for disassembler support in a monitor. */
32#if !defined(EMBEDDED_ENV)
33#define SYMTAB_AVAILABLE 1
34#include "elf-bfd.h"
35#include "elf/nios2.h"
36#endif
37
96ba4233 38/* Default length of Nios II instruction in bytes. */
36591ba1
SL		 39#define INSNLEN 4
40
41/* Data structures used by the opcode hash table. */
42typedef struct _nios2_opcode_hash
43{
44 const struct nios2_opcode *opcode;
45 struct _nios2_opcode_hash *next;
46} nios2_opcode_hash;
47
96ba4233
SL		 48/* Hash table size. */
49#define OPCODE_HASH_SIZE (IW_R1_OP_UNSHIFTED_MASK + 1)
36591ba1 50
96ba4233
SL		 51/* Extract the opcode from an instruction word. */
52static unsigned int
53nios2_r1_extract_opcode (unsigned int x)
54{
55 return GET_IW_R1_OP (x);
56}
57
c8c8175b
SL		 58static unsigned int
59nios2_r2_extract_opcode (unsigned int x)
60{
61 return GET_IW_R2_OP (x);
62}
63
64/* We maintain separate hash tables for R1 and R2 opcodes, and pseudo-ops
65 are stored in a different table than regular instructions. */
96ba4233
SL		 66
67typedef struct _nios2_disassembler_state
68{
69 const struct nios2_opcode *opcodes;
70 const int *num_opcodes;
71 unsigned int (*extract_opcode) (unsigned int);
72 nios2_opcode_hash *hash[OPCODE_HASH_SIZE];
73 nios2_opcode_hash *ps_hash[OPCODE_HASH_SIZE];
74 const struct nios2_opcode *nop;
75 bfd_boolean init;
76} nios2_disassembler_state;
77
78static nios2_disassembler_state
79nios2_r1_disassembler_state = {
80 nios2_r1_opcodes,
81 &nios2_num_r1_opcodes,
82 nios2_r1_extract_opcode,
83 {},
84 {},
85 NULL,
86 0
87};
36591ba1 88
c8c8175b
SL		 89static nios2_disassembler_state
90nios2_r2_disassembler_state = {
91 nios2_r2_opcodes,
92 &nios2_num_r2_opcodes,
93 nios2_r2_extract_opcode,
94 {},
95 {},
96 NULL,
97 0
98};
43e65147 99
36591ba1
SL		 100/* Function to initialize the opcode hash table. */
101static void
96ba4233 102nios2_init_opcode_hash (nios2_disassembler_state *state)
36591ba1
SL		 103{
104 unsigned int i;
105 register const struct nios2_opcode *op;
106
96ba4233
SL		 107 for (i = 0; i < OPCODE_HASH_SIZE; i++)
108 for (op = state->opcodes; op < &state->opcodes[*(state->num_opcodes)]; op++)
36591ba1
SL		 109 {
110 nios2_opcode_hash *new_hash;
111 nios2_opcode_hash **bucket = NULL;
112
113 if ((op->pinfo & NIOS2_INSN_MACRO) == NIOS2_INSN_MACRO)
114 {
96ba4233 115 if (i == state->extract_opcode (op->match)
36591ba1
SL		 116 && (op->pinfo & (NIOS2_INSN_MACRO_MOV | NIOS2_INSN_MACRO_MOVI)
117 & 0x7fffffff))
96ba4233
SL		 118 {
119 bucket = &(state->ps_hash[i]);
120 if (strcmp (op->name, "nop") == 0)
121 state->nop = op;
122 }
36591ba1 123 }
96ba4233
SL		 124 else if (i == state->extract_opcode (op->match))
125 bucket = &(state->hash[i]);
36591ba1
SL		 126
127 if (bucket)
128 {
129 new_hash =
130 (nios2_opcode_hash *) malloc (sizeof (nios2_opcode_hash));
131 if (new_hash == NULL)
132 {
133 fprintf (stderr,
134 "error allocating memory...broken disassembler\n");
135 abort ();
136 }
137 new_hash->opcode = op;
138 new_hash->next = NULL;
139 while (*bucket)
140 bucket = &((*bucket)->next);
141 *bucket = new_hash;
142 }
143 }
96ba4233
SL		 144 state->init = 1;
145
36591ba1 146#ifdef DEBUG_HASHTABLE
96ba4233 147 for (i = 0; i < OPCODE_HASH_SIZE; ++i)
36591ba1 148 {
96ba4233 149 nios2_opcode_hash *tmp_hash = state->hash[i];
36591ba1
SL		 150 printf ("index: 0x%02X ops: ", i);
151 while (tmp_hash != NULL)
152 {
153 printf ("%s ", tmp_hash->opcode->name);
154 tmp_hash = tmp_hash->next;
155 }
156 printf ("\n");
157 }
158
96ba4233 159 for (i = 0; i < OPCODE_HASH_SIZE; ++i)
36591ba1 160 {
96ba4233 161 nios2_opcode_hash *tmp_hash = state->ps_hash[i];
36591ba1
SL		 162 printf ("index: 0x%02X ops: ", i);
163 while (tmp_hash != NULL)
164 {
165 printf ("%s ", tmp_hash->opcode->name);
166 tmp_hash = tmp_hash->next;
167 }
168 printf ("\n");
169 }
170#endif /* DEBUG_HASHTABLE */
171}
172
173/* Return a pointer to an nios2_opcode struct for a given instruction
b4714c7c 174 word OPCODE for bfd machine MACH, or NULL if there is an error. */
36591ba1 175const struct nios2_opcode *
c8c8175b 176nios2_find_opcode_hash (unsigned long opcode, unsigned long mach)
36591ba1
SL		 177{
178 nios2_opcode_hash *entry;
96ba4233
SL		 179 nios2_disassembler_state *state;
180
c8c8175b
SL		 181 /* Select the right instruction set, hash tables, and opcode accessor
182 for the mach variant. */
183 if (mach == bfd_mach_nios2r2)
184 state = &nios2_r2_disassembler_state;
185 else
186 state = &nios2_r1_disassembler_state;
36591ba1
SL		 187
188 /* Build a hash table to shorten the search time. */
96ba4233
SL		 189 if (!state->init)
190 nios2_init_opcode_hash (state);
191
192 /* Check for NOP first. Both NOP and MOV are macros that expand into
193 an ADD instruction, and we always want to give priority to NOP. */
194 if (state->nop->match == (opcode & state->nop->mask))
195 return state->nop;
36591ba1
SL		 196
197 /* First look in the pseudo-op hashtable. */
96ba4233 198 for (entry = state->ps_hash[state->extract_opcode (opcode)];
36591ba1
SL		 199 entry; entry = entry->next)
200 if (entry->opcode->match == (opcode & entry->opcode->mask))
201 return entry->opcode;
202
203 /* Otherwise look in the main hashtable. */
96ba4233 204 for (entry = state->hash[state->extract_opcode (opcode)];
36591ba1
SL		 205 entry; entry = entry->next)
206 if (entry->opcode->match == (opcode & entry->opcode->mask))
207 return entry->opcode;
208
209 return NULL;
210}
211
212/* There are 32 regular registers, 32 coprocessor registers,
213 and 32 control registers. */
214#define NUMREGNAMES 32
215
216/* Return a pointer to the base of the coprocessor register name array. */
217static struct nios2_reg *
218nios2_coprocessor_regs (void)
219{
220 static struct nios2_reg *cached = NULL;
43e65147 221
36591ba1
SL		 222 if (!cached)
223 {
224 int i;
225 for (i = NUMREGNAMES; i < nios2_num_regs; i++)
226 if (!strcmp (nios2_regs[i].name, "c0"))
227 {
228 cached = nios2_regs + i;
229 break;
230 }
231 assert (cached);
232 }
233 return cached;
234}
235
236/* Return a pointer to the base of the control register name array. */
237static struct nios2_reg *
238nios2_control_regs (void)
239{
240 static struct nios2_reg *cached = NULL;
43e65147 241
36591ba1
SL		 242 if (!cached)
243 {
244 int i;
245 for (i = NUMREGNAMES; i < nios2_num_regs; i++)
246 if (!strcmp (nios2_regs[i].name, "status"))
247 {
248 cached = nios2_regs + i;
249 break;
250 }
251 assert (cached);
252 }
253 return cached;
254}
255
96ba4233
SL		 256/* Helper routine to report internal errors. */
257static void
258bad_opcode (const struct nios2_opcode *op)
259{
260 fprintf (stderr, "Internal error: broken opcode descriptor for `%s %s'\n",
261 op->name, op->args);
262 abort ();
263}
264
36591ba1
SL		 265/* The function nios2_print_insn_arg uses the character pointed
266 to by ARGPTR to determine how it print the next token or separator
267 character in the arguments to an instruction. */
268static int
269nios2_print_insn_arg (const char *argptr,
270 unsigned long opcode, bfd_vma address,
96ba4233
SL		 271 disassemble_info *info,
272 const struct nios2_opcode *op)
36591ba1
SL		 273{
274 unsigned long i = 0;
275 struct nios2_reg *reg_base;
276
277 switch (*argptr)
278 {
279 case ',':
280 case '(':
281 case ')':
282 (*info->fprintf_func) (info->stream, "%c", *argptr);
283 break;
36591ba1 284
c8c8175b
SL		 285 case 'c':
286 /* Control register index. */
287 switch (op->format)
288 {
289 case iw_r_type:
290 i = GET_IW_R_IMM5 (opcode);
291 break;
292 case iw_F3X6L5_type:
293 i = GET_IW_F3X6L5_IMM5 (opcode);
294 break;
295 default:
296 bad_opcode (op);
297 }
298 reg_base = nios2_control_regs ();
299 (*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
300 break;
301
96ba4233 302 case 'd':
c8c8175b 303 reg_base = nios2_regs;
96ba4233
SL		 304 switch (op->format)
305 {
306 case iw_r_type:
307 i = GET_IW_R_C (opcode);
96ba4233
SL		 308 break;
309 case iw_custom_type:
310 i = GET_IW_CUSTOM_C (opcode);
311 if (GET_IW_CUSTOM_READC (opcode) == 0)
312 reg_base = nios2_coprocessor_regs ();
c8c8175b
SL		 313 break;
314 case iw_F3X6L5_type:
315 case iw_F3X6_type:
316 i = GET_IW_F3X6L5_C (opcode);
317 break;
318 case iw_F3X8_type:
319 i = GET_IW_F3X8_C (opcode);
320 if (GET_IW_F3X8_READC (opcode) == 0)
321 reg_base = nios2_coprocessor_regs ();
322 break;
323 case iw_F2_type:
324 i = GET_IW_F2_B (opcode);
96ba4233
SL		 325 break;
326 default:
327 bad_opcode (op);
328 }
36591ba1
SL		 329 if (i < NUMREGNAMES)
330 (*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
331 else
332 (*info->fprintf_func) (info->stream, "unknown");
333 break;
36591ba1 334
96ba4233 335 case 's':
c8c8175b 336 reg_base = nios2_regs;
96ba4233
SL		 337 switch (op->format)
338 {
339 case iw_r_type:
340 i = GET_IW_R_A (opcode);
96ba4233
SL		 341 break;
342 case iw_i_type:
343 i = GET_IW_I_A (opcode);
96ba4233
SL		 344 break;
345 case iw_custom_type:
346 i = GET_IW_CUSTOM_A (opcode);
347 if (GET_IW_CUSTOM_READA (opcode) == 0)
348 reg_base = nios2_coprocessor_regs ();
c8c8175b
SL		 349 break;
350 case iw_F2I16_type:
351 i = GET_IW_F2I16_A (opcode);
352 break;
353 case iw_F2X4I12_type:
354 i = GET_IW_F2X4I12_A (opcode);
355 break;
356 case iw_F1X4I12_type:
357 i = GET_IW_F1X4I12_A (opcode);
358 break;
359 case iw_F1X4L17_type:
360 i = GET_IW_F1X4L17_A (opcode);
361 break;
362 case iw_F3X6L5_type:
363 case iw_F3X6_type:
364 i = GET_IW_F3X6L5_A (opcode);
365 break;
366 case iw_F2X6L10_type:
367 i = GET_IW_F2X6L10_A (opcode);
368 break;
369 case iw_F3X8_type:
370 i = GET_IW_F3X8_A (opcode);
371 if (GET_IW_F3X8_READA (opcode) == 0)
372 reg_base = nios2_coprocessor_regs ();
373 break;
374 case iw_F1X1_type:
375 i = GET_IW_F1X1_A (opcode);
376 break;
377 case iw_F1I5_type:
378 i = 27; /* Implicit stack pointer reference. */
379 break;
380 case iw_F2_type:
381 i = GET_IW_F2_A (opcode);
96ba4233
SL		 382 break;
383 default:
384 bad_opcode (op);
385 }
36591ba1
SL		 386 if (i < NUMREGNAMES)
387 (*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
388 else
389 (*info->fprintf_func) (info->stream, "unknown");
390 break;
36591ba1 391
96ba4233 392 case 't':
c8c8175b 393 reg_base = nios2_regs;
96ba4233
SL		 394 switch (op->format)
395 {
396 case iw_r_type:
397 i = GET_IW_R_B (opcode);
96ba4233
SL		 398 break;
399 case iw_i_type:
400 i = GET_IW_I_B (opcode);
96ba4233
SL		 401 break;
402 case iw_custom_type:
403 i = GET_IW_CUSTOM_B (opcode);
404 if (GET_IW_CUSTOM_READB (opcode) == 0)
405 reg_base = nios2_coprocessor_regs ();
c8c8175b
SL		 406 break;
407 case iw_F2I16_type:
408 i = GET_IW_F2I16_B (opcode);
409 break;
410 case iw_F2X4I12_type:
411 i = GET_IW_F2X4I12_B (opcode);
412 break;
413 case iw_F3X6L5_type:
414 case iw_F3X6_type:
415 i = GET_IW_F3X6L5_B (opcode);
416 break;
417 case iw_F2X6L10_type:
418 i = GET_IW_F2X6L10_B (opcode);
419 break;
420 case iw_F3X8_type:
421 i = GET_IW_F3X8_B (opcode);
422 if (GET_IW_F3X8_READB (opcode) == 0)
423 reg_base = nios2_coprocessor_regs ();
424 break;
425 case iw_F1I5_type:
426 i = GET_IW_F1I5_B (opcode);
427 break;
428 case iw_F2_type:
429 i = GET_IW_F2_B (opcode);
430 break;
431 case iw_T1X1I6_type:
432 i = 0;
96ba4233
SL		 433 break;
434 default:
435 bad_opcode (op);
436 }
36591ba1
SL		 437 if (i < NUMREGNAMES)
438 (*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
439 else
440 (*info->fprintf_func) (info->stream, "unknown");
441 break;
96ba4233 442
c8c8175b
SL		 443 case 'D':
444 switch (op->format)
445 {
446 case iw_T1I7_type:
447 i = GET_IW_T1I7_A3 (opcode);
448 break;
449 case iw_T2X1L3_type:
450 i = GET_IW_T2X1L3_B3 (opcode);
451 break;
452 case iw_T2X1I3_type:
453 i = GET_IW_T2X1I3_B3 (opcode);
454 break;
455 case iw_T3X1_type:
456 i = GET_IW_T3X1_C3 (opcode);
457 break;
458 case iw_T2X3_type:
459 if (op->num_args == 3)
460 i = GET_IW_T2X3_A3 (opcode);
461 else
462 i = GET_IW_T2X3_B3 (opcode);
463 break;
464 default:
465 bad_opcode (op);
466 }
467 i = nios2_r2_reg3_mappings[i];
468 (*info->fprintf_func) (info->stream, "%s", nios2_regs[i].name);
469 break;
470
471 case 'M':
472 /* 6-bit unsigned immediate with no shift. */
473 switch (op->format)
474 {
475 case iw_T1X1I6_type:
476 i = GET_IW_T1X1I6_IMM6 (opcode);
477 break;
478 default:
479 bad_opcode (op);
480 }
481 (*info->fprintf_func) (info->stream, "%ld", i);
482 break;
483
484 case 'N':
485 /* 6-bit unsigned immediate with 2-bit shift. */
486 switch (op->format)
487 {
488 case iw_T1X1I6_type:
489 i = GET_IW_T1X1I6_IMM6 (opcode) << 2;
490 break;
491 default:
492 bad_opcode (op);
493 }
494 (*info->fprintf_func) (info->stream, "%ld", i);
495 break;
496
497 case 'S':
498 switch (op->format)
499 {
500 case iw_T1I7_type:
501 i = GET_IW_T1I7_A3 (opcode);
502 break;
503 case iw_T2I4_type:
504 i = GET_IW_T2I4_A3 (opcode);
505 break;
506 case iw_T2X1L3_type:
507 i = GET_IW_T2X1L3_A3 (opcode);
508 break;
509 case iw_T2X1I3_type:
510 i = GET_IW_T2X1I3_A3 (opcode);
511 break;
512 case iw_T3X1_type:
513 i = GET_IW_T3X1_A3 (opcode);
514 break;
515 case iw_T2X3_type:
516 i = GET_IW_T2X3_A3 (opcode);
517 break;
518 case iw_T1X1I6_type:
519 i = GET_IW_T1X1I6_A3 (opcode);
520 break;
521 default:
522 bad_opcode (op);
523 }
524 i = nios2_r2_reg3_mappings[i];
525 (*info->fprintf_func) (info->stream, "%s", nios2_regs[i].name);
526 break;
527
528 case 'T':
529 switch (op->format)
530 {
531 case iw_T2I4_type:
532 i = GET_IW_T2I4_B3 (opcode);
533 break;
534 case iw_T3X1_type:
535 i = GET_IW_T3X1_B3 (opcode);
536 break;
537 case iw_T2X3_type:
538 i = GET_IW_T2X3_B3 (opcode);
539 break;
540 default:
541 bad_opcode (op);
542 }
543 i = nios2_r2_reg3_mappings[i];
544 (*info->fprintf_func) (info->stream, "%s", nios2_regs[i].name);
545 break;
546
36591ba1
SL		 547 case 'i':
548 /* 16-bit signed immediate. */
96ba4233
SL		 549 switch (op->format)
550 {
551 case iw_i_type:
552 i = (signed) (GET_IW_I_IMM16 (opcode) << 16) >> 16;
553 break;
c8c8175b
SL		 554 case iw_F2I16_type:
555 i = (signed) (GET_IW_F2I16_IMM16 (opcode) << 16) >> 16;
556 break;
557 default:
558 bad_opcode (op);
559 }
560 (*info->fprintf_func) (info->stream, "%ld", i);
561 break;
562
563 case 'I':
564 /* 12-bit signed immediate. */
565 switch (op->format)
566 {
567 case iw_F2X4I12_type:
568 i = (signed) (GET_IW_F2X4I12_IMM12 (opcode) << 20) >> 20;
569 break;
570 case iw_F1X4I12_type:
571 i = (signed) (GET_IW_F1X4I12_IMM12 (opcode) << 20) >> 20;
572 break;
96ba4233
SL		 573 default:
574 bad_opcode (op);
575 }
36591ba1
SL		 576 (*info->fprintf_func) (info->stream, "%ld", i);
577 break;
96ba4233 578
36591ba1
SL		 579 case 'u':
580 /* 16-bit unsigned immediate. */
96ba4233
SL		 581 switch (op->format)
582 {
583 case iw_i_type:
584 i = GET_IW_I_IMM16 (opcode);
585 break;
c8c8175b
SL		 586 case iw_F2I16_type:
587 i = GET_IW_F2I16_IMM16 (opcode);
588 break;
589 default:
590 bad_opcode (op);
591 }
592 (*info->fprintf_func) (info->stream, "%ld", i);
593 break;
594
595 case 'U':
596 /* 7-bit unsigned immediate with 2-bit shift. */
597 switch (op->format)
598 {
599 case iw_T1I7_type:
600 i = GET_IW_T1I7_IMM7 (opcode) << 2;
601 break;
602 case iw_X1I7_type:
603 i = GET_IW_X1I7_IMM7 (opcode) << 2;
604 break;
605 default:
606 bad_opcode (op);
607 }
608 (*info->fprintf_func) (info->stream, "%ld", i);
609 break;
610
611 case 'V':
612 /* 5-bit unsigned immediate with 2-bit shift. */
613 switch (op->format)
614 {
615 case iw_F1I5_type:
616 i = GET_IW_F1I5_IMM5 (opcode) << 2;
617 break;
618 default:
619 bad_opcode (op);
620 }
621 (*info->fprintf_func) (info->stream, "%ld", i);
622 break;
623
624 case 'W':
625 /* 4-bit unsigned immediate with 2-bit shift. */
626 switch (op->format)
627 {
628 case iw_T2I4_type:
629 i = GET_IW_T2I4_IMM4 (opcode) << 2;
630 break;
631 case iw_L5I4X1_type:
632 i = GET_IW_L5I4X1_IMM4 (opcode) << 2;
633 break;
634 default:
635 bad_opcode (op);
636 }
637 (*info->fprintf_func) (info->stream, "%ld", i);
638 break;
639
640 case 'X':
641 /* 4-bit unsigned immediate with 1-bit shift. */
642 switch (op->format)
643 {
644 case iw_T2I4_type:
645 i = GET_IW_T2I4_IMM4 (opcode) << 1;
646 break;
647 default:
648 bad_opcode (op);
649 }
650 (*info->fprintf_func) (info->stream, "%ld", i);
651 break;
652
653 case 'Y':
654 /* 4-bit unsigned immediate without shift. */
655 switch (op->format)
656 {
657 case iw_T2I4_type:
658 i = GET_IW_T2I4_IMM4 (opcode);
659 break;
96ba4233
SL		 660 default:
661 bad_opcode (op);
662 }
36591ba1
SL		 663 (*info->fprintf_func) (info->stream, "%ld", i);
664 break;
96ba4233 665
36591ba1
SL		 666 case 'o':
667 /* 16-bit signed immediate address offset. */
96ba4233
SL		 668 switch (op->format)
669 {
670 case iw_i_type:
671 i = (signed) (GET_IW_I_IMM16 (opcode) << 16) >> 16;
672 break;
c8c8175b
SL		 673 case iw_F2I16_type:
674 i = (signed) (GET_IW_F2I16_IMM16 (opcode) << 16) >> 16;
675 break;
96ba4233
SL		 676 default:
677 bad_opcode (op);
678 }
36591ba1
SL		 679 address = address + 4 + i;
680 (*info->print_address_func) (address, info);
681 break;
96ba4233 682
c8c8175b
SL		 683 case 'O':
684 /* 10-bit signed address offset with 1-bit shift. */
685 switch (op->format)
686 {
687 case iw_I10_type:
688 i = (signed) (GET_IW_I10_IMM10 (opcode) << 22) >> 21;
689 break;
690 default:
691 bad_opcode (op);
692 }
693 address = address + 2 + i;
694 (*info->print_address_func) (address, info);
695 break;
696
697 case 'P':
698 /* 7-bit signed address offset with 1-bit shift. */
699 switch (op->format)
700 {
701 case iw_T1I7_type:
702 i = (signed) (GET_IW_T1I7_IMM7 (opcode) << 25) >> 24;
703 break;
704 default:
705 bad_opcode (op);
706 }
707 address = address + 2 + i;
708 (*info->print_address_func) (address, info);
709 break;
710
36591ba1
SL		 711 case 'j':
712 /* 5-bit unsigned immediate. */
96ba4233
SL		 713 switch (op->format)
714 {
715 case iw_r_type:
716 i = GET_IW_R_IMM5 (opcode);
717 break;
c8c8175b
SL		 718 case iw_F3X6L5_type:
719 i = GET_IW_F3X6L5_IMM5 (opcode);
720 break;
721 case iw_F2X6L10_type:
722 i = GET_IW_F2X6L10_MSB (opcode);
723 break;
724 case iw_X2L5_type:
725 i = GET_IW_X2L5_IMM5 (opcode);
726 break;
727 default:
728 bad_opcode (op);
729 }
730 (*info->fprintf_func) (info->stream, "%ld", i);
731 break;
732
733 case 'k':
734 /* Second 5-bit unsigned immediate field. */
735 switch (op->format)
736 {
737 case iw_F2X6L10_type:
738 i = GET_IW_F2X6L10_LSB (opcode);
739 break;
96ba4233
SL		 740 default:
741 bad_opcode (op);
742 }
36591ba1
SL		 743 (*info->fprintf_func) (info->stream, "%ld", i);
744 break;
96ba4233 745
36591ba1
SL		 746 case 'l':
747 /* 8-bit unsigned immediate. */
96ba4233
SL		 748 switch (op->format)
749 {
750 case iw_custom_type:
751 i = GET_IW_CUSTOM_N (opcode);
752 break;
c8c8175b
SL		 753 case iw_F3X8_type:
754 i = GET_IW_F3X8_N (opcode);
755 break;
96ba4233
SL		 756 default:
757 bad_opcode (op);
758 }
36591ba1
SL		 759 (*info->fprintf_func) (info->stream, "%lu", i);
760 break;
96ba4233 761
36591ba1
SL		 762 case 'm':
763 /* 26-bit unsigned immediate. */
96ba4233
SL		 764 switch (op->format)
765 {
766 case iw_j_type:
767 i = GET_IW_J_IMM26 (opcode);
768 break;
c8c8175b
SL		 769 case iw_L26_type:
770 i = GET_IW_L26_IMM26 (opcode);
771 break;
96ba4233
SL		 772 default:
773 bad_opcode (op);
774 }
36591ba1
SL		 775 /* This translates to an address because it's only used in call
776 instructions. */
777 address = (address & 0xf0000000) | (i << 2);
778 (*info->print_address_func) (address, info);
779 break;
96ba4233 780
c8c8175b
SL		 781 case 'e':
782 /* Encoded enumeration for addi.n/subi.n. */
96ba4233
SL		 783 switch (op->format)
784 {
c8c8175b
SL		 785 case iw_T2X1I3_type:
786 i = nios2_r2_asi_n_mappings[GET_IW_T2X1I3_IMM3 (opcode)];
787 break;
788 default:
789 bad_opcode (op);
790 }
791 (*info->fprintf_func) (info->stream, "%lu", i);
792 break;
793
794 case 'f':
795 /* Encoded enumeration for slli.n/srli.n. */
796 switch (op->format)
797 {
798 case iw_T2X1L3_type:
799 i = nios2_r2_shi_n_mappings[GET_IW_T2X1I3_IMM3 (opcode)];
800 break;
801 default:
802 bad_opcode (op);
803 }
804 (*info->fprintf_func) (info->stream, "%lu", i);
805 break;
806
807 case 'g':
808 /* Encoded enumeration for andi.n. */
809 switch (op->format)
810 {
811 case iw_T2I4_type:
812 i = nios2_r2_andi_n_mappings[GET_IW_T2I4_IMM4 (opcode)];
813 break;
814 default:
815 bad_opcode (op);
816 }
817 (*info->fprintf_func) (info->stream, "%lu", i);
818 break;
819
820 case 'h':
821 /* Encoded enumeration for movi.n. */
822 switch (op->format)
823 {
824 case iw_T1I7_type:
825 i = GET_IW_T1I7_IMM7 (opcode);
826 if (i == 125)
827 i = 0xff;
828 else if (i == 126)
829 i = -2;
830 else if (i == 127)
831 i = -1;
832 break;
833 default:
834 bad_opcode (op);
835 }
836 (*info->fprintf_func) (info->stream, "%ld", i);
837 break;
838
839 case 'R':
840 {
841 unsigned long reglist = 0;
842 int dir = 1;
843 int k, t;
844
845 switch (op->format)
846 {
847 case iw_F1X4L17_type:
848 /* Encoding for ldwm/stwm. */
849 i = GET_IW_F1X4L17_REGMASK (opcode);
850 if (GET_IW_F1X4L17_RS (opcode))
851 {
852 reglist = ((i << 14) & 0x00ffc000);
853 if (i & (1 << 10))
854 reglist |= (1 << 28);
855 if (i & (1 << 11))
856 reglist |= (1 << 31);
857 }
858 else
859 reglist = i << 2;
860 dir = GET_IW_F1X4L17_REGMASK (opcode) ? 1 : -1;
861 break;
43e65147 862
c8c8175b
SL		 863 case iw_L5I4X1_type:
864 /* Encoding for push.n/pop.n. */
865 reglist |= (1 << 31);
866 if (GET_IW_L5I4X1_FP (opcode))
867 reglist |= (1 << 28);
868 if (GET_IW_L5I4X1_CS (opcode))
869 {
870 int val = GET_IW_L5I4X1_REGRANGE (opcode);
871 reglist |= nios2_r2_reg_range_mappings[val];
872 }
873 dir = (op->match == MATCH_R2_POP_N ? 1 : -1);
874 break;
875
876 default:
877 bad_opcode (op);
878 }
879
880 t = 0;
881 (*info->fprintf_func) (info->stream, "{");
882 for (k = (dir == 1 ? 0 : 31);
883 (dir == 1 && k < 32) || (dir == -1 && k >= 0);
884 k += dir)
885 if (reglist & (1 << k))
886 {
887 if (t)
888 (*info->fprintf_func) (info->stream, ",");
889 else
890 t++;
891 (*info->fprintf_func) (info->stream, "%s", nios2_regs[k].name);
892 }
893 (*info->fprintf_func) (info->stream, "}");
894 break;
895 }
896
897 case 'B':
898 /* Base register and options for ldwm/stwm. */
899 switch (op->format)
900 {
901 case iw_F1X4L17_type:
902 if (GET_IW_F1X4L17_ID (opcode) == 0)
903 (*info->fprintf_func) (info->stream, "--");
904
905 i = GET_IW_F1X4I12_A (opcode);
43e65147 906 (*info->fprintf_func) (info->stream, "(%s)",
c8c8175b
SL		 907 nios2_builtin_regs[i].name);
908
909 if (GET_IW_F1X4L17_ID (opcode))
910 (*info->fprintf_func) (info->stream, "++");
911 if (GET_IW_F1X4L17_WB (opcode))
912 (*info->fprintf_func) (info->stream, ",writeback");
913 if (GET_IW_F1X4L17_PC (opcode))
914 (*info->fprintf_func) (info->stream, ",ret");
96ba4233
SL		 915 break;
916 default:
917 bad_opcode (op);
918 }
36591ba1 919 break;
96ba4233 920
36591ba1
SL		 921 default:
922 (*info->fprintf_func) (info->stream, "unknown");
923 break;
924 }
925 return 0;
926}
927
928/* nios2_disassemble does all the work of disassembling a Nios II
929 instruction opcode. */
930static int
931nios2_disassemble (bfd_vma address, unsigned long opcode,
932 disassemble_info *info)
933{
934 const struct nios2_opcode *op;
935
936 info->bytes_per_line = INSNLEN;
937 info->bytes_per_chunk = INSNLEN;
938 info->display_endian = info->endian;
939 info->insn_info_valid = 1;
940 info->branch_delay_insns = 0;
941 info->data_size = 0;
942 info->insn_type = dis_nonbranch;
943 info->target = 0;
944 info->target2 = 0;
945
946 /* Find the major opcode and use this to disassemble
947 the instruction and its arguments. */
b4714c7c 948 op = nios2_find_opcode_hash (opcode, info->mach);
36591ba1
SL		 949
950 if (op != NULL)
951 {
96ba4233
SL		 952 const char *argstr = op->args;
953 (*info->fprintf_func) (info->stream, "%s", op->name);
954 if (argstr != NULL && *argstr != '\0')
36591ba1 955 {
96ba4233
SL		 956 (*info->fprintf_func) (info->stream, "\t");
957 while (*argstr != '\0')
36591ba1 958 {
96ba4233
SL		 959 nios2_print_insn_arg (argstr, opcode, address, info, op);
960 ++argstr;
36591ba1
SL		 961 }
962 }
96ba4233
SL		 963 /* Tell the caller how far to advance the program counter. */
964 info->bytes_per_chunk = op->size;
965 return op->size;
36591ba1
SL		 966 }
967 else
968 {
969 /* Handle undefined instructions. */
970 info->insn_type = dis_noninsn;
971 (*info->fprintf_func) (info->stream, "0x%lx", opcode);
96ba4233 972 return INSNLEN;
36591ba1 973 }
36591ba1
SL		 974}
975
976
977/* print_insn_nios2 is the main disassemble function for Nios II.
978 The function diassembler(abfd) (source in disassemble.c) returns a
979 pointer to this either print_insn_big_nios2 or
980 print_insn_little_nios2, which in turn call this function when the
981 bfd machine type is Nios II. print_insn_nios2 reads the
982 instruction word at the address given, and prints the disassembled
983 instruction on the stream info->stream using info->fprintf_func. */
984
985static int
986print_insn_nios2 (bfd_vma address, disassemble_info *info,
987 enum bfd_endian endianness)
988{
989 bfd_byte buffer[INSNLEN];
990 int status;
991
992 status = (*info->read_memory_func) (address, buffer, INSNLEN, info);
993 if (status == 0)
994 {
995 unsigned long insn;
996 if (endianness == BFD_ENDIAN_BIG)
997 insn = (unsigned long) bfd_getb32 (buffer);
998 else
999 insn = (unsigned long) bfd_getl32 (buffer);
c8c8175b 1000 return nios2_disassemble (address, insn, info);
36591ba1 1001 }
c8c8175b
SL		 1002
1003 /* We might have a 16-bit R2 instruction at the end of memory. Try that. */
1004 if (info->mach == bfd_mach_nios2r2)
36591ba1 1005 {
c8c8175b
SL		 1006 status = (*info->read_memory_func) (address, buffer, 2, info);
1007 if (status == 0)
1008 {
1009 unsigned long insn;
1010 if (endianness == BFD_ENDIAN_BIG)
1011 insn = (unsigned long) bfd_getb16 (buffer);
1012 else
1013 insn = (unsigned long) bfd_getl16 (buffer);
1014 return nios2_disassemble (address, insn, info);
1015 }
36591ba1 1016 }
c8c8175b
SL		 1017
1018 /* If we got here, we couldn't read anything. */
1019 (*info->memory_error_func) (status, address, info);
1020 return -1;
36591ba1
SL		 1021}
1022
1023/* These two functions are the main entry points, accessed from
1024 disassemble.c. */
1025int
1026print_insn_big_nios2 (bfd_vma address, disassemble_info *info)
1027{
1028 return print_insn_nios2 (address, info, BFD_ENDIAN_BIG);
1029}
1030
1031int
1032print_insn_little_nios2 (bfd_vma address, disassemble_info *info)
1033{
1034 return print_insn_nios2 (address, info, BFD_ENDIAN_LITTLE);
1035}
GDB Binutils - Deliverables
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