[deliverable/binutils-gdb.git] / opcodes / openrisc-dis.c

/* Disassembler interface for targets using CGEN. -*- C -*-
   CGEN: Cpu tools GENerator

THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't

Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.

This file is part of the GNU Binutils and GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

/* ??? Eventually more and more of this stuff can go to cpu-independent files.
   Keep that in mind.  */

#include "sysdep.h"
#include <stdio.h>
#include "ansidecl.h"
#include "dis-asm.h"
#include "bfd.h"
#include "symcat.h"
#include "openrisc-desc.h"
#include "openrisc-opc.h"
#include "opintl.h"

/* Default text to print if an instruction isn't recognized.  */
#define UNKNOWN_INSN_MSG _("*unknown*")

static void print_normal
     PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
static void print_address
     PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
static void print_keyword
     PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
static void print_insn_normal
     PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
	      bfd_vma, int));
static int print_insn
     PARAMS ((CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned));
static int default_print_insn
     PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
static int read_insn
     PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
	      CGEN_EXTRACT_INFO *, unsigned long *));
\f
/* -- disassembler routines inserted here */


void openrisc_cgen_print_operand
  PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
           void const *, bfd_vma, int));

/* Main entry point for printing operands.
   XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
   of dis-asm.h on cgen.h.

   This function is basically just a big switch statement.  Earlier versions
   used tables to look up the function to use, but
   - if the table contains both assembler and disassembler functions then
     the disassembler contains much of the assembler and vice-versa,
   - there's a lot of inlining possibilities as things grow,
   - using a switch statement avoids the function call overhead.

   This function could be moved into `print_insn_normal', but keeping it
   separate makes clear the interface between `print_insn_normal' and each of
   the handlers.  */

void
openrisc_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
     CGEN_CPU_DESC cd;
     int opindex;
     PTR xinfo;
     CGEN_FIELDS *fields;
     void const *attrs ATTRIBUTE_UNUSED;
     bfd_vma pc;
     int length;
{
 disassemble_info *info = (disassemble_info *) xinfo;

  switch (opindex)
    {
    case OPENRISC_OPERAND_ABS_26 :
      print_address (cd, info, fields->f_abs26, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
      break;
    case OPENRISC_OPERAND_DISP_26 :
      print_address (cd, info, fields->f_disp26, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
      break;
    case OPENRISC_OPERAND_HI16 :
      print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
      break;
    case OPENRISC_OPERAND_LO16 :
      print_normal (cd, info, fields->f_lo16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
      break;
    case OPENRISC_OPERAND_OP_F_23 :
      print_normal (cd, info, fields->f_op4, 0, pc, length);
      break;
    case OPENRISC_OPERAND_OP_F_3 :
      print_normal (cd, info, fields->f_op5, 0, pc, length);
      break;
    case OPENRISC_OPERAND_RA :
      print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r2, 0);
      break;
    case OPENRISC_OPERAND_RB :
      print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r3, 0);
      break;
    case OPENRISC_OPERAND_RD :
      print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r1, 0);
      break;
    case OPENRISC_OPERAND_SIMM_16 :
      print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
      break;
    case OPENRISC_OPERAND_UI16NC :
      print_normal (cd, info, fields->f_i16nc, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
      break;
    case OPENRISC_OPERAND_UIMM_16 :
      print_normal (cd, info, fields->f_uimm16, 0, pc, length);
      break;
    case OPENRISC_OPERAND_UIMM_5 :
      print_normal (cd, info, fields->f_uimm5, 0, pc, length);
      break;

    default :
      /* xgettext:c-format */
      fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
	       opindex);
    abort ();
  }
}

cgen_print_fn * const openrisc_cgen_print_handlers[] = 
{
  print_insn_normal,
};


void
openrisc_cgen_init_dis (cd)
     CGEN_CPU_DESC cd;
{
  openrisc_cgen_init_opcode_table (cd);
  openrisc_cgen_init_ibld_table (cd);
  cd->print_handlers = & openrisc_cgen_print_handlers[0];
  cd->print_operand = openrisc_cgen_print_operand;
}

\f
/* Default print handler.  */

static void
print_normal (cd, dis_info, value, attrs, pc, length)
     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
     PTR dis_info;
     long value;
     unsigned int attrs;
     bfd_vma pc ATTRIBUTE_UNUSED;
     int length ATTRIBUTE_UNUSED;
{
  disassemble_info *info = (disassemble_info *) dis_info;

#ifdef CGEN_PRINT_NORMAL
  CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
#endif

  /* Print the operand as directed by the attributes.  */
  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
    ; /* nothing to do */
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
    (*info->fprintf_func) (info->stream, "%ld", value);
  else
    (*info->fprintf_func) (info->stream, "0x%lx", value);
}

/* Default address handler.  */

static void
print_address (cd, dis_info, value, attrs, pc, length)
     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
     PTR dis_info;
     bfd_vma value;
     unsigned int attrs;
     bfd_vma pc ATTRIBUTE_UNUSED;
     int length ATTRIBUTE_UNUSED;
{
  disassemble_info *info = (disassemble_info *) dis_info;

#ifdef CGEN_PRINT_ADDRESS
  CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
#endif

  /* Print the operand as directed by the attributes.  */
  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
    ; /* nothing to do */
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
    (*info->print_address_func) (value, info);
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
    (*info->print_address_func) (value, info);
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
    (*info->fprintf_func) (info->stream, "%ld", (long) value);
  else
    (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
}

/* Keyword print handler.  */

static void
print_keyword (cd, dis_info, keyword_table, value, attrs)
     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
     PTR dis_info;
     CGEN_KEYWORD *keyword_table;
     long value;
     unsigned int attrs ATTRIBUTE_UNUSED;
{
  disassemble_info *info = (disassemble_info *) dis_info;
  const CGEN_KEYWORD_ENTRY *ke;

  ke = cgen_keyword_lookup_value (keyword_table, value);
  if (ke != NULL)
    (*info->fprintf_func) (info->stream, "%s", ke->name);
  else
    (*info->fprintf_func) (info->stream, "???");
}
\f
/* Default insn printer.

   DIS_INFO is defined as `PTR' so the disassembler needn't know anything
   about disassemble_info.  */

static void
print_insn_normal (cd, dis_info, insn, fields, pc, length)
     CGEN_CPU_DESC cd;
     PTR dis_info;
     const CGEN_INSN *insn;
     CGEN_FIELDS *fields;
     bfd_vma pc;
     int length;
{
  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
  disassemble_info *info = (disassemble_info *) dis_info;
  const CGEN_SYNTAX_CHAR_TYPE *syn;

  CGEN_INIT_PRINT (cd);

  for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
    {
      if (CGEN_SYNTAX_MNEMONIC_P (*syn))
	{
	  (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
	  continue;
	}
      if (CGEN_SYNTAX_CHAR_P (*syn))
	{
	  (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
	  continue;
	}

      /* We have an operand.  */
      openrisc_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
				 fields, CGEN_INSN_ATTRS (insn), pc, length);
    }
}
\f
/* Subroutine of print_insn. Reads an insn into the given buffers and updates
   the extract info.
   Returns 0 if all is well, non-zero otherwise.  */

static int
read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
     bfd_vma pc;
     disassemble_info *info;
     char *buf;
     int buflen;
     CGEN_EXTRACT_INFO *ex_info;
     unsigned long *insn_value;
{
  int status = (*info->read_memory_func) (pc, buf, buflen, info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, pc, info);
      return -1;
    }

  ex_info->dis_info = info;
  ex_info->valid = (1 << buflen) - 1;
  ex_info->insn_bytes = buf;

  *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
  return 0;
}

/* Utility to print an insn.
   BUF is the base part of the insn, target byte order, BUFLEN bytes long.
   The result is the size of the insn in bytes or zero for an unknown insn
   or -1 if an error occurs fetching data (memory_error_func will have
   been called).  */

static int
print_insn (cd, pc, info, buf, buflen)
     CGEN_CPU_DESC cd;
     bfd_vma pc;
     disassemble_info *info;
     char *buf;
     unsigned int buflen;
{
  CGEN_INSN_INT insn_value;
  const CGEN_INSN_LIST *insn_list;
  CGEN_EXTRACT_INFO ex_info;
  int basesize;

  /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
  basesize = cd->base_insn_bitsize < buflen * 8 ?
                                     cd->base_insn_bitsize : buflen * 8;
  insn_value = cgen_get_insn_value (cd, buf, basesize);


  /* Fill in ex_info fields like read_insn would.  Don't actually call
     read_insn, since the incoming buffer is already read (and possibly
     modified a la m32r).  */
  ex_info.valid = (1 << buflen) - 1;
  ex_info.dis_info = info;
  ex_info.insn_bytes = buf;

  /* The instructions are stored in hash lists.
     Pick the first one and keep trying until we find the right one.  */

  insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
  while (insn_list != NULL)
    {
      const CGEN_INSN *insn = insn_list->insn;
      CGEN_FIELDS fields;
      int length;
      unsigned long insn_value_cropped;

#ifdef CGEN_VALIDATE_INSN_SUPPORTED 
      /* Not needed as insn shouldn't be in hash lists if not supported.  */
      /* Supported by this cpu?  */
      if (! openrisc_cgen_insn_supported (cd, insn))
        {
          insn_list = CGEN_DIS_NEXT_INSN (insn_list);
	  continue;
        }
#endif

      /* Basic bit mask must be correct.  */
      /* ??? May wish to allow target to defer this check until the extract
	 handler.  */

      /* Base size may exceed this instruction's size.  Extract the
         relevant part from the buffer. */
      if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
	  (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
	insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), 
					   info->endian == BFD_ENDIAN_BIG);
      else
	insn_value_cropped = insn_value;

      if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
	  == CGEN_INSN_BASE_VALUE (insn))
	{
	  /* Printing is handled in two passes.  The first pass parses the
	     machine insn and extracts the fields.  The second pass prints
	     them.  */

	  /* Make sure the entire insn is loaded into insn_value, if it
	     can fit.  */
	  if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
	      (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
	    {
	      unsigned long full_insn_value;
	      int rc = read_insn (cd, pc, info, buf,
				  CGEN_INSN_BITSIZE (insn) / 8,
				  & ex_info, & full_insn_value);
	      if (rc != 0)
		return rc;
	      length = CGEN_EXTRACT_FN (cd, insn)
		(cd, insn, &ex_info, full_insn_value, &fields, pc);
	    }
	  else
	    length = CGEN_EXTRACT_FN (cd, insn)
	      (cd, insn, &ex_info, insn_value_cropped, &fields, pc);

	  /* length < 0 -> error */
	  if (length < 0)
	    return length;
	  if (length > 0)
	    {
	      CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
	      /* length is in bits, result is in bytes */
	      return length / 8;
	    }
	}

      insn_list = CGEN_DIS_NEXT_INSN (insn_list);
    }

  return 0;
}

/* Default value for CGEN_PRINT_INSN.
   The result is the size of the insn in bytes or zero for an unknown insn
   or -1 if an error occured fetching bytes.  */

#ifndef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN default_print_insn
#endif

static int
default_print_insn (cd, pc, info)
     CGEN_CPU_DESC cd;
     bfd_vma pc;
     disassemble_info *info;
{
  char buf[CGEN_MAX_INSN_SIZE];
  int buflen;
  int status;

  /* Attempt to read the base part of the insn.  */
  buflen = cd->base_insn_bitsize / 8;
  status = (*info->read_memory_func) (pc, buf, buflen, info);

  /* Try again with the minimum part, if min < base.  */
  if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
    {
      buflen = cd->min_insn_bitsize / 8;
      status = (*info->read_memory_func) (pc, buf, buflen, info);
    }

  if (status != 0)
    {
      (*info->memory_error_func) (status, pc, info);
      return -1;
    }

  return print_insn (cd, pc, info, buf, buflen);
}

/* Main entry point.
   Print one instruction from PC on INFO->STREAM.
   Return the size of the instruction (in bytes).  */

typedef struct cpu_desc_list {
  struct cpu_desc_list *next;
  int isa;
  int mach;
  int endian;
  CGEN_CPU_DESC cd;
} cpu_desc_list;

int
print_insn_openrisc (pc, info)
     bfd_vma pc;
     disassemble_info *info;
{
  static cpu_desc_list *cd_list = 0;
  cpu_desc_list *cl = 0;
  static CGEN_CPU_DESC cd = 0;
  static int prev_isa;
  static int prev_mach;
  static int prev_endian;
  int length;
  int isa,mach;
  int endian = (info->endian == BFD_ENDIAN_BIG
		? CGEN_ENDIAN_BIG
		: CGEN_ENDIAN_LITTLE);
  enum bfd_architecture arch;

  /* ??? gdb will set mach but leave the architecture as "unknown" */
#ifndef CGEN_BFD_ARCH
#define CGEN_BFD_ARCH bfd_arch_openrisc
#endif
  arch = info->arch;
  if (arch == bfd_arch_unknown)
    arch = CGEN_BFD_ARCH;
   
  /* There's no standard way to compute the machine or isa number
     so we leave it to the target.  */
#ifdef CGEN_COMPUTE_MACH
  mach = CGEN_COMPUTE_MACH (info);
#else
  mach = info->mach;
#endif

#ifdef CGEN_COMPUTE_ISA
  isa = CGEN_COMPUTE_ISA (info);
#else
  isa = info->insn_sets;
#endif

  /* If we've switched cpu's, try to find a handle we've used before */
  if (cd
      && (isa != prev_isa
	  || mach != prev_mach
	  || endian != prev_endian))
    {
      cd = 0;
      for (cl = cd_list; cl; cl = cl->next)
	{
	  if (cl->isa == isa &&
	      cl->mach == mach &&
	      cl->endian == endian)
	    {
	      cd = cl->cd;
	      break;
	    }
	}
    } 

  /* If we haven't initialized yet, initialize the opcode table.  */
  if (! cd)
    {
      const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
      const char *mach_name;

      if (!arch_type)
	abort ();
      mach_name = arch_type->printable_name;

      prev_isa = isa;
      prev_mach = mach;
      prev_endian = endian;
      cd = openrisc_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
				 CGEN_CPU_OPEN_BFDMACH, mach_name,
				 CGEN_CPU_OPEN_ENDIAN, prev_endian,
				 CGEN_CPU_OPEN_END);
      if (!cd)
	abort ();

      /* save this away for future reference */
      cl = xmalloc (sizeof (struct cpu_desc_list));
      cl->cd = cd;
      cl->isa = isa;
      cl->mach = mach;
      cl->endian = endian;
      cl->next = cd_list;
      cd_list = cl;

      openrisc_cgen_init_dis (cd);
    }

  /* We try to have as much common code as possible.
     But at this point some targets need to take over.  */
  /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
     but if not possible try to move this hook elsewhere rather than
     have two hooks.  */
  length = CGEN_PRINT_INSN (cd, pc, info);
  if (length > 0)
    return length;
  if (length < 0)
    return -1;

  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
  return cd->default_insn_bitsize / 8;
}
Commit	Line	Data
87e6d782 NC	1	/* Disassembler interface for targets using CGEN. -- C --
	2	CGEN: Cpu tools GENerator
	3
	4	THIS FILE IS MACHINE GENERATED WITH CGEN.
	5	- the resultant file is machine generated, cgen-dis.in isn't
	6
	7	Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
	8
	9	This file is part of the GNU Binutils and GDB, the GNU debugger.
	10
	11	This program is free software; you can redistribute it and/or modify
	12	it under the terms of the GNU General Public License as published by
	13	the Free Software Foundation; either version 2, or (at your option)
	14	any later version.
	15
	16	This program is distributed in the hope that it will be useful,
	17	but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	GNU General Public License for more details.
	20
	21	You should have received a copy of the GNU General Public License
	22	along with this program; if not, write to the Free Software Foundation, Inc.,
	23	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	24
	25	/* ??? Eventually more and more of this stuff can go to cpu-independent files.
	26	Keep that in mind. */
	27
	28	#include "sysdep.h"
	29	#include <stdio.h>
	30	#include "ansidecl.h"
	31	#include "dis-asm.h"
	32	#include "bfd.h"
	33	#include "symcat.h"
	34	#include "openrisc-desc.h"
	35	#include "openrisc-opc.h"
	36	#include "opintl.h"
	37
	38	/* Default text to print if an instruction isn't recognized. */
	39	#define UNKNOWN_INSN_MSG _("unknown")
	40
	41	static void print_normal
	42	PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
	43	static void print_address
	44	PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
	45	static void print_keyword
	46	PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
	47	static void print_insn_normal
	48	PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN , CGEN_FIELDS ,
	49	bfd_vma, int));
0e2ee3ca NC	50	static int print_insn
0e2ee3ca NC	51	PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info , char , unsigned));
87e6d782 NC	52	static int default_print_insn
87e6d782 NC	53	PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
fc05c67f	54	static int read_insn
0e2ee3ca NC	55	PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info , char , int,
0e2ee3ca NC	56	CGEN_EXTRACT_INFO , unsigned long ));
87e6d782 NC	57	\f
	58	/* -- disassembler routines inserted here */
	59
	60
0e2ee3ca NC	61	void openrisc_cgen_print_operand
	62	PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
	63	void const *, bfd_vma, int));
	64
87e6d782 NC	65	/* Main entry point for printing operands.
	66	XINFO is a `void ' and not a `disassemble_info ' to not put a requirement
	67	of dis-asm.h on cgen.h.
	68
	69	This function is basically just a big switch statement. Earlier versions
	70	used tables to look up the function to use, but
	71	- if the table contains both assembler and disassembler functions then
	72	the disassembler contains much of the assembler and vice-versa,
	73	- there's a lot of inlining possibilities as things grow,
	74	- using a switch statement avoids the function call overhead.
	75
	76	This function could be moved into `print_insn_normal', but keeping it
	77	separate makes clear the interface between `print_insn_normal' and each of
9a2e995d	78	the handlers. */
87e6d782 NC	79
	80	void
	81	openrisc_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
	82	CGEN_CPU_DESC cd;
	83	int opindex;
	84	PTR xinfo;
	85	CGEN_FIELDS *fields;
fc05c67f	86	void const *attrs ATTRIBUTE_UNUSED;
87e6d782 NC	87	bfd_vma pc;
	88	int length;
	89	{
	90	disassemble_info info = (disassemble_info ) xinfo;
	91
	92	switch (opindex)
	93	{
	94	case OPENRISC_OPERAND_ABS_26 :
	95	print_address (cd, info, fields->f_abs26, 0\|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
	96	break;
	97	case OPENRISC_OPERAND_DISP_26 :
	98	print_address (cd, info, fields->f_disp26, 0\|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
	99	break;
	100	case OPENRISC_OPERAND_HI16 :
	101	print_normal (cd, info, fields->f_simm16, 0\|(1<<CGEN_OPERAND_SIGNED)\|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
	102	break;
	103	case OPENRISC_OPERAND_LO16 :
	104	print_normal (cd, info, fields->f_lo16, 0\|(1<<CGEN_OPERAND_SIGNED)\|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
	105	break;
	106	case OPENRISC_OPERAND_OP_F_23 :
	107	print_normal (cd, info, fields->f_op4, 0, pc, length);
	108	break;
	109	case OPENRISC_OPERAND_OP_F_3 :
	110	print_normal (cd, info, fields->f_op5, 0, pc, length);
	111	break;
	112	case OPENRISC_OPERAND_RA :
	113	print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r2, 0);
	114	break;
	115	case OPENRISC_OPERAND_RB :
	116	print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r3, 0);
	117	break;
	118	case OPENRISC_OPERAND_RD :
	119	print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r1, 0);
	120	break;
	121	case OPENRISC_OPERAND_SIMM_16 :
	122	print_normal (cd, info, fields->f_simm16, 0\|(1<<CGEN_OPERAND_SIGNED), pc, length);
	123	break;
	124	case OPENRISC_OPERAND_UI16NC :
	125	print_normal (cd, info, fields->f_i16nc, 0\|(1<<CGEN_OPERAND_SIGNED)\|(1<<CGEN_OPERAND_SIGN_OPT)\|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
	126	break;
	127	case OPENRISC_OPERAND_UIMM_16 :
	128	print_normal (cd, info, fields->f_uimm16, 0, pc, length);
	129	break;
	130	case OPENRISC_OPERAND_UIMM_5 :
	131	print_normal (cd, info, fields->f_uimm5, 0, pc, length);
	132	break;
	133
	134	default :
	135	/* xgettext:c-format */
	136	fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
	137	opindex);
	138	abort ();
	139	}
	140	}
	141
	142	cgen_print_fn * const openrisc_cgen_print_handlers[] =
	143	{
	144	print_insn_normal,
	145	};
	146
	147
	148	void
	149	openrisc_cgen_init_dis (cd)
	150	CGEN_CPU_DESC cd;
151	{
152	openrisc_cgen_init_opcode_table (cd);
153	openrisc_cgen_init_ibld_table (cd);
154	cd->print_handlers = & openrisc_cgen_print_handlers[0];
155	cd->print_operand = openrisc_cgen_print_operand;
156	}
157
158	\f
159	/* Default print handler. */
160
161	static void
162	print_normal (cd, dis_info, value, attrs, pc, length)
87e6d782	163	CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
87e6d782 NC	164	PTR dis_info;
	165	long value;
	166	unsigned int attrs;
87e6d782 NC	167	bfd_vma pc ATTRIBUTE_UNUSED;
87e6d782 NC	168	int length ATTRIBUTE_UNUSED;
87e6d782 NC	169	{
	170	disassemble_info info = (disassemble_info ) dis_info;
	171
	172	#ifdef CGEN_PRINT_NORMAL
	173	CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
	174	#endif
	175
	176	/* Print the operand as directed by the attributes. */
	177	if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
	178	; /* nothing to do */
	179	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
	180	(*info->fprintf_func) (info->stream, "%ld", value);
	181	else
	182	(*info->fprintf_func) (info->stream, "0x%lx", value);
	183	}
	184
	185	/* Default address handler. */
	186
	187	static void
	188	print_address (cd, dis_info, value, attrs, pc, length)
87e6d782	189	CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
87e6d782 NC	190	PTR dis_info;
	191	bfd_vma value;
	192	unsigned int attrs;
87e6d782 NC	193	bfd_vma pc ATTRIBUTE_UNUSED;
87e6d782 NC	194	int length ATTRIBUTE_UNUSED;
87e6d782 NC	195	{
	196	disassemble_info info = (disassemble_info ) dis_info;
	197
	198	#ifdef CGEN_PRINT_ADDRESS
	199	CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
	200	#endif
	201
	202	/* Print the operand as directed by the attributes. */
	203	if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
	204	; /* nothing to do */
	205	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
	206	(*info->print_address_func) (value, info);
	207	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
	208	(*info->print_address_func) (value, info);
	209	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
	210	(*info->fprintf_func) (info->stream, "%ld", (long) value);
	211	else
	212	(*info->fprintf_func) (info->stream, "0x%lx", (long) value);
	213	}
	214
	215	/* Keyword print handler. */
	216
	217	static void
	218	print_keyword (cd, dis_info, keyword_table, value, attrs)
	219	CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
	220	PTR dis_info;
	221	CGEN_KEYWORD *keyword_table;
	222	long value;
	223	unsigned int attrs ATTRIBUTE_UNUSED;
	224	{
	225	disassemble_info info = (disassemble_info ) dis_info;
	226	const CGEN_KEYWORD_ENTRY *ke;
	227
	228	ke = cgen_keyword_lookup_value (keyword_table, value);
	229	if (ke != NULL)
	230	(*info->fprintf_func) (info->stream, "%s", ke->name);
	231	else
	232	(*info->fprintf_func) (info->stream, "???");
	233	}
	234	\f
	235	/* Default insn printer.
	236
	237	DIS_INFO is defined as `PTR' so the disassembler needn't know anything
	238	about disassemble_info. */
	239
	240	static void
	241	print_insn_normal (cd, dis_info, insn, fields, pc, length)
	242	CGEN_CPU_DESC cd;
	243	PTR dis_info;
	244	const CGEN_INSN *insn;
	245	CGEN_FIELDS *fields;
	246	bfd_vma pc;
	247	int length;
	248	{
	249	const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
	250	disassemble_info info = (disassemble_info ) dis_info;
	251	const CGEN_SYNTAX_CHAR_TYPE *syn;
	252
	253	CGEN_INIT_PRINT (cd);
	254
	255	for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
	256	{
	257	if (CGEN_SYNTAX_MNEMONIC_P (*syn))
	258	{
259	(*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
260	continue;
261	}
262	if (CGEN_SYNTAX_CHAR_P (*syn))
263	{
264	(info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (syn));
265	continue;
266	}
267
268	/* We have an operand. */
269	openrisc_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
270	fields, CGEN_INSN_ATTRS (insn), pc, length);
271	}
272	}
273	\f
274	/* Subroutine of print_insn. Reads an insn into the given buffers and updates
275	the extract info.
276	Returns 0 if all is well, non-zero otherwise. */
0e2ee3ca	277
87e6d782 NC	278	static int
87e6d782 NC	279	read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
fc05c67f	280	CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
87e6d782 NC	281	bfd_vma pc;
	282	disassemble_info *info;
	283	char *buf;
	284	int buflen;
	285	CGEN_EXTRACT_INFO *ex_info;
	286	unsigned long *insn_value;
	287	{
	288	int status = (*info->read_memory_func) (pc, buf, buflen, info);
	289	if (status != 0)
	290	{
	291	(*info->memory_error_func) (status, pc, info);
	292	return -1;
	293	}
	294
	295	ex_info->dis_info = info;
	296	ex_info->valid = (1 << buflen) - 1;
	297	ex_info->insn_bytes = buf;
	298
	299	insn_value = bfd_get_bits (buf, buflen 8, info->endian == BFD_ENDIAN_BIG);
	300	return 0;
	301	}
	302
	303	/* Utility to print an insn.
	304	BUF is the base part of the insn, target byte order, BUFLEN bytes long.
	305	The result is the size of the insn in bytes or zero for an unknown insn
	306	or -1 if an error occurs fetching data (memory_error_func will have
	307	been called). */
	308
	309	static int
	310	print_insn (cd, pc, info, buf, buflen)
	311	CGEN_CPU_DESC cd;
	312	bfd_vma pc;
	313	disassemble_info *info;
	314	char *buf;
0e2ee3ca	315	unsigned int buflen;
87e6d782	316	{
fc7bc883	317	CGEN_INSN_INT insn_value;
87e6d782 NC	318	const CGEN_INSN_LIST *insn_list;
87e6d782 NC	319	CGEN_EXTRACT_INFO ex_info;
3c3bdf30	320	int basesize;
87e6d782	321
fc7bc883	322	/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
3c3bdf30 NC	323	basesize = cd->base_insn_bitsize < buflen * 8 ?
	324	cd->base_insn_bitsize : buflen * 8;
	325	insn_value = cgen_get_insn_value (cd, buf, basesize);
	326
fc7bc883 RH	327
	328	/* Fill in ex_info fields like read_insn would. Don't actually call
	329	read_insn, since the incoming buffer is already read (and possibly
	330	modified a la m32r). */
	331	ex_info.valid = (1 << buflen) - 1;
	332	ex_info.dis_info = info;
	333	ex_info.insn_bytes = buf;
87e6d782 NC	334
	335	/* The instructions are stored in hash lists.
	336	Pick the first one and keep trying until we find the right one. */
	337
	338	insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
	339	while (insn_list != NULL)
	340	{
	341	const CGEN_INSN *insn = insn_list->insn;
	342	CGEN_FIELDS fields;
	343	int length;
fc7bc883	344	unsigned long insn_value_cropped;
87e6d782 NC	345
87e6d782 NC	346	#ifdef CGEN_VALIDATE_INSN_SUPPORTED
0e2ee3ca	347	/* Not needed as insn shouldn't be in hash lists if not supported. */
87e6d782 NC	348	/* Supported by this cpu? */
	349	if (! openrisc_cgen_insn_supported (cd, insn))
	350	{
	351	insn_list = CGEN_DIS_NEXT_INSN (insn_list);
	352	continue;
	353	}
	354	#endif
	355
	356	/* Basic bit mask must be correct. */
	357	/* ??? May wish to allow target to defer this check until the extract
	358	handler. */
fc7bc883 RH	359
	360	/* Base size may exceed this instruction's size. Extract the
	361	relevant part from the buffer. */
0e2ee3ca NC	362	if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
0e2ee3ca NC	363	(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
fc7bc883 RH	364	insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
	365	info->endian == BFD_ENDIAN_BIG);
	366	else
	367	insn_value_cropped = insn_value;
	368
	369	if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
87e6d782 NC	370	== CGEN_INSN_BASE_VALUE (insn))
	371	{
	372	/* Printing is handled in two passes. The first pass parses the
	373	machine insn and extracts the fields. The second pass prints
	374	them. */
	375
	376	/* Make sure the entire insn is loaded into insn_value, if it
	377	can fit. */
0e2ee3ca NC	378	if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
0e2ee3ca NC	379	(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
87e6d782 NC	380	{
	381	unsigned long full_insn_value;
	382	int rc = read_insn (cd, pc, info, buf,
	383	CGEN_INSN_BITSIZE (insn) / 8,
	384	& ex_info, & full_insn_value);
	385	if (rc != 0)
	386	return rc;
	387	length = CGEN_EXTRACT_FN (cd, insn)
	388	(cd, insn, &ex_info, full_insn_value, &fields, pc);
	389	}
	390	else
	391	length = CGEN_EXTRACT_FN (cd, insn)
fc7bc883	392	(cd, insn, &ex_info, insn_value_cropped, &fields, pc);
87e6d782 NC	393
	394	/* length < 0 -> error */
	395	if (length < 0)
	396	return length;
	397	if (length > 0)
	398	{
	399	CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
	400	/* length is in bits, result is in bytes */
	401	return length / 8;
	402	}
	403	}
	404
	405	insn_list = CGEN_DIS_NEXT_INSN (insn_list);
	406	}
	407
	408	return 0;
	409	}
	410
	411	/* Default value for CGEN_PRINT_INSN.
	412	The result is the size of the insn in bytes or zero for an unknown insn
	413	or -1 if an error occured fetching bytes. */
	414
	415	#ifndef CGEN_PRINT_INSN
	416	#define CGEN_PRINT_INSN default_print_insn
	417	#endif
	418
	419	static int
	420	default_print_insn (cd, pc, info)
	421	CGEN_CPU_DESC cd;
	422	bfd_vma pc;
	423	disassemble_info *info;
	424	{
	425	char buf[CGEN_MAX_INSN_SIZE];
fc7bc883	426	int buflen;
87e6d782 NC	427	int status;
87e6d782 NC	428
fc7bc883 RH	429	/* Attempt to read the base part of the insn. */
	430	buflen = cd->base_insn_bitsize / 8;
	431	status = (*info->read_memory_func) (pc, buf, buflen, info);
	432
	433	/* Try again with the minimum part, if min < base. */
	434	if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
	435	{
	436	buflen = cd->min_insn_bitsize / 8;
	437	status = (*info->read_memory_func) (pc, buf, buflen, info);
	438	}
87e6d782	439
87e6d782 NC	440	if (status != 0)
	441	{
	442	(*info->memory_error_func) (status, pc, info);
	443	return -1;
	444	}
	445
fc7bc883	446	return print_insn (cd, pc, info, buf, buflen);
87e6d782 NC	447	}
	448
	449	/* Main entry point.
	450	Print one instruction from PC on INFO->STREAM.
	451	Return the size of the instruction (in bytes). */
	452
a978a3e5 NC	453	typedef struct cpu_desc_list {
	454	struct cpu_desc_list *next;
	455	int isa;
	456	int mach;
	457	int endian;
	458	CGEN_CPU_DESC cd;
	459	} cpu_desc_list;
	460
87e6d782 NC	461	int
	462	print_insn_openrisc (pc, info)
	463	bfd_vma pc;
	464	disassemble_info *info;
	465	{
a978a3e5 NC	466	static cpu_desc_list *cd_list = 0;
a978a3e5 NC	467	cpu_desc_list *cl = 0;
87e6d782 NC	468	static CGEN_CPU_DESC cd = 0;
	469	static int prev_isa;
	470	static int prev_mach;
	471	static int prev_endian;
	472	int length;
	473	int isa,mach;
	474	int endian = (info->endian == BFD_ENDIAN_BIG
	475	? CGEN_ENDIAN_BIG
	476	: CGEN_ENDIAN_LITTLE);
	477	enum bfd_architecture arch;
	478
	479	/* ??? gdb will set mach but leave the architecture as "unknown" */
	480	#ifndef CGEN_BFD_ARCH
	481	#define CGEN_BFD_ARCH bfd_arch_openrisc
	482	#endif
	483	arch = info->arch;
	484	if (arch == bfd_arch_unknown)
	485	arch = CGEN_BFD_ARCH;
	486
	487	/* There's no standard way to compute the machine or isa number
	488	so we leave it to the target. */
	489	#ifdef CGEN_COMPUTE_MACH
	490	mach = CGEN_COMPUTE_MACH (info);
	491	#else
	492	mach = info->mach;
	493	#endif
	494
	495	#ifdef CGEN_COMPUTE_ISA
	496	isa = CGEN_COMPUTE_ISA (info);
	497	#else
a978a3e5	498	isa = info->insn_sets;
87e6d782 NC	499	#endif
87e6d782 NC	500
a978a3e5	501	/* If we've switched cpu's, try to find a handle we've used before */
87e6d782 NC	502	if (cd
	503	&& (isa != prev_isa
	504	\|\| mach != prev_mach
	505	\|\| endian != prev_endian))
	506	{
87e6d782	507	cd = 0;
a978a3e5 NC	508	for (cl = cd_list; cl; cl = cl->next)
	509	{
	510	if (cl->isa == isa &&
	511	cl->mach == mach &&
	512	cl->endian == endian)
	513	{
	514	cd = cl->cd;
	515	break;
	516	}
	517	}
	518	}
87e6d782 NC	519
	520	/* If we haven't initialized yet, initialize the opcode table. */
	521	if (! cd)
	522	{
	523	const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
	524	const char *mach_name;
	525
	526	if (!arch_type)
	527	abort ();
	528	mach_name = arch_type->printable_name;
	529
	530	prev_isa = isa;
	531	prev_mach = mach;
	532	prev_endian = endian;
	533	cd = openrisc_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
	534	CGEN_CPU_OPEN_BFDMACH, mach_name,
	535	CGEN_CPU_OPEN_ENDIAN, prev_endian,
	536	CGEN_CPU_OPEN_END);
	537	if (!cd)
	538	abort ();
a978a3e5 NC	539
	540	/* save this away for future reference */
	541	cl = xmalloc (sizeof (struct cpu_desc_list));
	542	cl->cd = cd;
	543	cl->isa = isa;
	544	cl->mach = mach;
	545	cl->endian = endian;
	546	cl->next = cd_list;
	547	cd_list = cl;
	548
87e6d782 NC	549	openrisc_cgen_init_dis (cd);
	550	}
	551
	552	/* We try to have as much common code as possible.
	553	But at this point some targets need to take over. */
	554	/* ??? Some targets may need a hook elsewhere. Try to avoid this,
	555	but if not possible try to move this hook elsewhere rather than
	556	have two hooks. */
	557	length = CGEN_PRINT_INSN (cd, pc, info);
	558	if (length > 0)
	559	return length;
	560	if (length < 0)
	561	return -1;
	562
	563	(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
	564	return cd->default_insn_bitsize / 8;
	565	}