x86: use template for XOP integer comparison, shift, and rotate insns
[deliverable/binutils-gdb.git] / opcodes / or1k-ibld.c
CommitLineData
4162bb66 1/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
73589c9d 2/* Instruction building/extraction support for or1k. -*- C -*-
87e6d782 3
47b0e7ad
NC
4 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
5 - the resultant file is machine generated, cgen-ibld.in isn't
87e6d782 6
b3adc24a 7 Copyright (C) 1996-2020 Free Software Foundation, Inc.
87e6d782 8
9b201bb5 9 This file is part of libopcodes.
87e6d782 10
9b201bb5 11 This library is free software; you can redistribute it and/or modify
47b0e7ad 12 it under the terms of the GNU General Public License as published by
9b201bb5 13 the Free Software Foundation; either version 3, or (at your option)
47b0e7ad 14 any later version.
87e6d782 15
9b201bb5
NC
16 It is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
87e6d782 20
47b0e7ad
NC
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software Foundation, Inc.,
23 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
87e6d782
NC
24
25/* ??? Eventually more and more of this stuff can go to cpu-independent files.
26 Keep that in mind. */
27
28#include "sysdep.h"
87e6d782
NC
29#include <stdio.h>
30#include "ansidecl.h"
31#include "dis-asm.h"
32#include "bfd.h"
33#include "symcat.h"
73589c9d
CS
34#include "or1k-desc.h"
35#include "or1k-opc.h"
fe8afbc4 36#include "cgen/basic-modes.h"
87e6d782 37#include "opintl.h"
37111cc7 38#include "safe-ctype.h"
87e6d782 39
47b0e7ad 40#undef min
87e6d782 41#define min(a,b) ((a) < (b) ? (a) : (b))
47b0e7ad 42#undef max
87e6d782
NC
43#define max(a,b) ((a) > (b) ? (a) : (b))
44
45/* Used by the ifield rtx function. */
46#define FLD(f) (fields->f)
47
48static const char * insert_normal
ffead7ae
MM
49 (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
50 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
87e6d782 51static const char * insert_insn_normal
ffead7ae
MM
52 (CGEN_CPU_DESC, const CGEN_INSN *,
53 CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
87e6d782 54static int extract_normal
ffead7ae
MM
55 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
56 unsigned int, unsigned int, unsigned int, unsigned int,
57 unsigned int, unsigned int, bfd_vma, long *);
87e6d782 58static int extract_insn_normal
ffead7ae
MM
59 (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
60 CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
0e2ee3ca 61#if CGEN_INT_INSN_P
87e6d782 62static void put_insn_int_value
ffead7ae 63 (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
0e2ee3ca
NC
64#endif
65#if ! CGEN_INT_INSN_P
66static CGEN_INLINE void insert_1
ffead7ae 67 (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
0e2ee3ca 68static CGEN_INLINE int fill_cache
ffead7ae 69 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma);
0e2ee3ca 70static CGEN_INLINE long extract_1
ffead7ae 71 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
0e2ee3ca 72#endif
87e6d782
NC
73\f
74/* Operand insertion. */
75
76#if ! CGEN_INT_INSN_P
77
78/* Subroutine of insert_normal. */
79
80static CGEN_INLINE void
ffead7ae
MM
81insert_1 (CGEN_CPU_DESC cd,
82 unsigned long value,
83 int start,
84 int length,
85 int word_length,
86 unsigned char *bufp)
87e6d782
NC
87{
88 unsigned long x,mask;
89 int shift;
87e6d782 90
0e2ee3ca 91 x = cgen_get_insn_value (cd, bufp, word_length);
87e6d782
NC
92
93 /* Written this way to avoid undefined behaviour. */
94 mask = (((1L << (length - 1)) - 1) << 1) | 1;
95 if (CGEN_INSN_LSB0_P)
96 shift = (start + 1) - length;
97 else
98 shift = (word_length - (start + length));
99 x = (x & ~(mask << shift)) | ((value & mask) << shift);
100
0e2ee3ca 101 cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
87e6d782
NC
102}
103
104#endif /* ! CGEN_INT_INSN_P */
105
106/* Default insertion routine.
107
108 ATTRS is a mask of the boolean attributes.
109 WORD_OFFSET is the offset in bits from the start of the insn of the value.
110 WORD_LENGTH is the length of the word in bits in which the value resides.
111 START is the starting bit number in the word, architecture origin.
112 LENGTH is the length of VALUE in bits.
113 TOTAL_LENGTH is the total length of the insn in bits.
114
115 The result is an error message or NULL if success. */
116
117/* ??? This duplicates functionality with bfd's howto table and
118 bfd_install_relocation. */
119/* ??? This doesn't handle bfd_vma's. Create another function when
120 necessary. */
121
122static const char *
ffead7ae
MM
123insert_normal (CGEN_CPU_DESC cd,
124 long value,
125 unsigned int attrs,
126 unsigned int word_offset,
127 unsigned int start,
128 unsigned int length,
129 unsigned int word_length,
130 unsigned int total_length,
131 CGEN_INSN_BYTES_PTR buffer)
87e6d782
NC
132{
133 static char errbuf[100];
134 /* Written this way to avoid undefined behaviour. */
135 unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
136
137 /* If LENGTH is zero, this operand doesn't contribute to the value. */
138 if (length == 0)
139 return NULL;
140
b7cd1872 141 if (word_length > 8 * sizeof (CGEN_INSN_INT))
87e6d782
NC
142 abort ();
143
144 /* For architectures with insns smaller than the base-insn-bitsize,
145 word_length may be too big. */
146 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
147 {
148 if (word_offset == 0
149 && word_length > total_length)
150 word_length = total_length;
151 }
152
153 /* Ensure VALUE will fit. */
fc7bc883
RH
154 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
155 {
156 long minval = - (1L << (length - 1));
157 unsigned long maxval = mask;
43e65147 158
fc7bc883
RH
159 if ((value > 0 && (unsigned long) value > maxval)
160 || value < minval)
161 {
162 /* xgettext:c-format */
163 sprintf (errbuf,
164 _("operand out of range (%ld not between %ld and %lu)"),
165 value, minval, maxval);
166 return errbuf;
167 }
168 }
169 else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
87e6d782
NC
170 {
171 unsigned long maxval = mask;
ed963e2d
NC
172 unsigned long val = (unsigned long) value;
173
174 /* For hosts with a word size > 32 check to see if value has been sign
175 extended beyond 32 bits. If so then ignore these higher sign bits
176 as the user is attempting to store a 32-bit signed value into an
177 unsigned 32-bit field which is allowed. */
178 if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
179 val &= 0xFFFFFFFF;
180
181 if (val > maxval)
87e6d782
NC
182 {
183 /* xgettext:c-format */
184 sprintf (errbuf,
ed963e2d
NC
185 _("operand out of range (0x%lx not between 0 and 0x%lx)"),
186 val, maxval);
87e6d782
NC
187 return errbuf;
188 }
189 }
190 else
191 {
192 if (! cgen_signed_overflow_ok_p (cd))
193 {
194 long minval = - (1L << (length - 1));
195 long maxval = (1L << (length - 1)) - 1;
43e65147 196
87e6d782
NC
197 if (value < minval || value > maxval)
198 {
199 sprintf
200 /* xgettext:c-format */
201 (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
202 value, minval, maxval);
203 return errbuf;
204 }
205 }
206 }
207
208#if CGEN_INT_INSN_P
209
210 {
a143b004 211 int shift_within_word, shift_to_word, shift;
87e6d782 212
a143b004
AB
213 /* How to shift the value to BIT0 of the word. */
214 shift_to_word = total_length - (word_offset + word_length);
215
216 /* How to shift the value to the field within the word. */
87e6d782 217 if (CGEN_INSN_LSB0_P)
a143b004 218 shift_within_word = start + 1 - length;
87e6d782 219 else
a143b004
AB
220 shift_within_word = word_length - start - length;
221
222 /* The total SHIFT, then mask in the value. */
223 shift = shift_to_word + shift_within_word;
87e6d782
NC
224 *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
225 }
226
227#else /* ! CGEN_INT_INSN_P */
228
229 {
230 unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
231
232 insert_1 (cd, value, start, length, word_length, bufp);
233 }
234
235#endif /* ! CGEN_INT_INSN_P */
236
237 return NULL;
238}
239
240/* Default insn builder (insert handler).
241 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
242 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
243 recorded in host byte order, otherwise BUFFER is an array of bytes
244 and the value is recorded in target byte order).
245 The result is an error message or NULL if success. */
246
247static const char *
ffead7ae
MM
248insert_insn_normal (CGEN_CPU_DESC cd,
249 const CGEN_INSN * insn,
250 CGEN_FIELDS * fields,
251 CGEN_INSN_BYTES_PTR buffer,
252 bfd_vma pc)
87e6d782
NC
253{
254 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
255 unsigned long value;
256 const CGEN_SYNTAX_CHAR_TYPE * syn;
257
258 CGEN_INIT_INSERT (cd);
259 value = CGEN_INSN_BASE_VALUE (insn);
260
261 /* If we're recording insns as numbers (rather than a string of bytes),
262 target byte order handling is deferred until later. */
263
264#if CGEN_INT_INSN_P
265
266 put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
267 CGEN_FIELDS_BITSIZE (fields), value);
268
269#else
270
0e2ee3ca
NC
271 cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
272 (unsigned) CGEN_FIELDS_BITSIZE (fields)),
87e6d782
NC
273 value);
274
275#endif /* ! CGEN_INT_INSN_P */
276
277 /* ??? It would be better to scan the format's fields.
278 Still need to be able to insert a value based on the operand though;
279 e.g. storing a branch displacement that got resolved later.
280 Needs more thought first. */
281
282 for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
283 {
284 const char *errmsg;
285
286 if (CGEN_SYNTAX_CHAR_P (* syn))
287 continue;
288
289 errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
290 fields, buffer, pc);
291 if (errmsg)
292 return errmsg;
293 }
294
295 return NULL;
296}
297
0e2ee3ca 298#if CGEN_INT_INSN_P
87e6d782 299/* Cover function to store an insn value into an integral insn. Must go here
47b0e7ad 300 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
87e6d782
NC
301
302static void
ffead7ae
MM
303put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
304 CGEN_INSN_BYTES_PTR buf,
305 int length,
306 int insn_length,
307 CGEN_INSN_INT value)
87e6d782
NC
308{
309 /* For architectures with insns smaller than the base-insn-bitsize,
310 length may be too big. */
311 if (length > insn_length)
312 *buf = value;
313 else
314 {
315 int shift = insn_length - length;
316 /* Written this way to avoid undefined behaviour. */
317 CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
47b0e7ad 318
87e6d782
NC
319 *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
320 }
321}
0e2ee3ca 322#endif
87e6d782
NC
323\f
324/* Operand extraction. */
325
326#if ! CGEN_INT_INSN_P
327
328/* Subroutine of extract_normal.
329 Ensure sufficient bytes are cached in EX_INFO.
330 OFFSET is the offset in bytes from the start of the insn of the value.
331 BYTES is the length of the needed value.
332 Returns 1 for success, 0 for failure. */
333
334static CGEN_INLINE int
ffead7ae
MM
335fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
336 CGEN_EXTRACT_INFO *ex_info,
337 int offset,
338 int bytes,
339 bfd_vma pc)
87e6d782
NC
340{
341 /* It's doubtful that the middle part has already been fetched so
342 we don't optimize that case. kiss. */
0e2ee3ca 343 unsigned int mask;
87e6d782
NC
344 disassemble_info *info = (disassemble_info *) ex_info->dis_info;
345
346 /* First do a quick check. */
347 mask = (1 << bytes) - 1;
348 if (((ex_info->valid >> offset) & mask) == mask)
349 return 1;
350
351 /* Search for the first byte we need to read. */
352 for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
353 if (! (mask & ex_info->valid))
354 break;
355
356 if (bytes)
357 {
358 int status;
359
360 pc += offset;
361 status = (*info->read_memory_func)
362 (pc, ex_info->insn_bytes + offset, bytes, info);
363
364 if (status != 0)
365 {
366 (*info->memory_error_func) (status, pc, info);
367 return 0;
368 }
369
370 ex_info->valid |= ((1 << bytes) - 1) << offset;
371 }
372
373 return 1;
374}
375
376/* Subroutine of extract_normal. */
377
378static CGEN_INLINE long
ffead7ae
MM
379extract_1 (CGEN_CPU_DESC cd,
380 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
381 int start,
382 int length,
383 int word_length,
384 unsigned char *bufp,
385 bfd_vma pc ATTRIBUTE_UNUSED)
87e6d782
NC
386{
387 unsigned long x;
388 int shift;
47b0e7ad 389
e333d2c4
NC
390 x = cgen_get_insn_value (cd, bufp, word_length);
391
87e6d782
NC
392 if (CGEN_INSN_LSB0_P)
393 shift = (start + 1) - length;
394 else
395 shift = (word_length - (start + length));
396 return x >> shift;
397}
398
399#endif /* ! CGEN_INT_INSN_P */
400
401/* Default extraction routine.
402
403 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
404 or sometimes less for cases like the m32r where the base insn size is 32
405 but some insns are 16 bits.
406 ATTRS is a mask of the boolean attributes. We only need `SIGNED',
407 but for generality we take a bitmask of all of them.
408 WORD_OFFSET is the offset in bits from the start of the insn of the value.
409 WORD_LENGTH is the length of the word in bits in which the value resides.
410 START is the starting bit number in the word, architecture origin.
411 LENGTH is the length of VALUE in bits.
412 TOTAL_LENGTH is the total length of the insn in bits.
413
414 Returns 1 for success, 0 for failure. */
415
416/* ??? The return code isn't properly used. wip. */
417
418/* ??? This doesn't handle bfd_vma's. Create another function when
419 necessary. */
420
421static int
ffead7ae 422extract_normal (CGEN_CPU_DESC cd,
87e6d782 423#if ! CGEN_INT_INSN_P
ffead7ae 424 CGEN_EXTRACT_INFO *ex_info,
87e6d782 425#else
ffead7ae 426 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
87e6d782 427#endif
ffead7ae
MM
428 CGEN_INSN_INT insn_value,
429 unsigned int attrs,
430 unsigned int word_offset,
431 unsigned int start,
432 unsigned int length,
433 unsigned int word_length,
434 unsigned int total_length,
87e6d782 435#if ! CGEN_INT_INSN_P
ffead7ae 436 bfd_vma pc,
87e6d782 437#else
ffead7ae 438 bfd_vma pc ATTRIBUTE_UNUSED,
87e6d782 439#endif
ffead7ae 440 long *valuep)
87e6d782 441{
fc7bc883 442 long value, mask;
87e6d782
NC
443
444 /* If LENGTH is zero, this operand doesn't contribute to the value
445 so give it a standard value of zero. */
446 if (length == 0)
447 {
448 *valuep = 0;
449 return 1;
450 }
451
b7cd1872 452 if (word_length > 8 * sizeof (CGEN_INSN_INT))
87e6d782
NC
453 abort ();
454
455 /* For architectures with insns smaller than the insn-base-bitsize,
456 word_length may be too big. */
457 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
458 {
ed963e2d
NC
459 if (word_offset + word_length > total_length)
460 word_length = total_length - word_offset;
87e6d782
NC
461 }
462
fc7bc883 463 /* Does the value reside in INSN_VALUE, and at the right alignment? */
87e6d782 464
fc7bc883 465 if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
87e6d782
NC
466 {
467 if (CGEN_INSN_LSB0_P)
468 value = insn_value >> ((word_offset + start + 1) - length);
469 else
470 value = insn_value >> (total_length - ( word_offset + start + length));
471 }
472
473#if ! CGEN_INT_INSN_P
474
475 else
476 {
477 unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
478
b7cd1872 479 if (word_length > 8 * sizeof (CGEN_INSN_INT))
87e6d782
NC
480 abort ();
481
482 if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
2f5dd314
AM
483 {
484 *valuep = 0;
485 return 0;
486 }
87e6d782
NC
487
488 value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
489 }
490
491#endif /* ! CGEN_INT_INSN_P */
492
493 /* Written this way to avoid undefined behaviour. */
494 mask = (((1L << (length - 1)) - 1) << 1) | 1;
495
496 value &= mask;
497 /* sign extend? */
498 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
499 && (value & (1L << (length - 1))))
500 value |= ~mask;
501
502 *valuep = value;
503
504 return 1;
505}
506
507/* Default insn extractor.
508
509 INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
510 The extracted fields are stored in FIELDS.
511 EX_INFO is used to handle reading variable length insns.
512 Return the length of the insn in bits, or 0 if no match,
513 or -1 if an error occurs fetching data (memory_error_func will have
514 been called). */
515
516static int
ffead7ae
MM
517extract_insn_normal (CGEN_CPU_DESC cd,
518 const CGEN_INSN *insn,
519 CGEN_EXTRACT_INFO *ex_info,
520 CGEN_INSN_INT insn_value,
521 CGEN_FIELDS *fields,
522 bfd_vma pc)
87e6d782
NC
523{
524 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
525 const CGEN_SYNTAX_CHAR_TYPE *syn;
526
527 CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
528
529 CGEN_INIT_EXTRACT (cd);
530
531 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
532 {
533 int length;
534
535 if (CGEN_SYNTAX_CHAR_P (*syn))
536 continue;
537
538 length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
539 ex_info, insn_value, fields, pc);
540 if (length <= 0)
541 return length;
542 }
543
544 /* We recognized and successfully extracted this insn. */
545 return CGEN_INSN_BITSIZE (insn);
546}
547\f
47b0e7ad 548/* Machine generated code added here. */
87e6d782 549
73589c9d 550const char * or1k_cgen_insert_operand
47b0e7ad 551 (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
0e2ee3ca 552
87e6d782
NC
553/* Main entry point for operand insertion.
554
555 This function is basically just a big switch statement. Earlier versions
556 used tables to look up the function to use, but
557 - if the table contains both assembler and disassembler functions then
558 the disassembler contains much of the assembler and vice-versa,
559 - there's a lot of inlining possibilities as things grow,
560 - using a switch statement avoids the function call overhead.
561
562 This function could be moved into `parse_insn_normal', but keeping it
563 separate makes clear the interface between `parse_insn_normal' and each of
564 the handlers. It's also needed by GAS to insert operands that couldn't be
9a2e995d 565 resolved during parsing. */
87e6d782
NC
566
567const char *
73589c9d 568or1k_cgen_insert_operand (CGEN_CPU_DESC cd,
47b0e7ad
NC
569 int opindex,
570 CGEN_FIELDS * fields,
571 CGEN_INSN_BYTES_PTR buffer,
572 bfd_vma pc ATTRIBUTE_UNUSED)
87e6d782
NC
573{
574 const char * errmsg = NULL;
575 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
576
577 switch (opindex)
578 {
c8e98e36
SH
579 case OR1K_OPERAND_DISP21 :
580 {
581 long value = fields->f_disp21;
582 value = ((((DI) (value) >> (13))) - (((DI) (pc) >> (13))));
583 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_ABS_ADDR), 0, 20, 21, 32, total_length, buffer);
584 }
585 break;
73589c9d 586 case OR1K_OPERAND_DISP26 :
87e6d782
NC
587 {
588 long value = fields->f_disp26;
c8e98e36 589 value = ((DI) (((value) - (pc))) >> (2));
87e6d782
NC
590 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, buffer);
591 }
592 break;
73589c9d
CS
593 case OR1K_OPERAND_RA :
594 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
87e6d782 595 break;
e4c4ac46
SH
596 case OR1K_OPERAND_RAD32F :
597 {
598{
599 FLD (f_r2) = ((FLD (f_rad32)) & (31));
600 FLD (f_raoff_9_1) = ((((SI) (FLD (f_rad32)) >> (5))) & (1));
601}
602 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
603 if (errmsg)
604 break;
605 errmsg = insert_normal (cd, fields->f_raoff_9_1, 0, 0, 9, 1, 32, total_length, buffer);
606 if (errmsg)
607 break;
608 }
609 break;
73589c9d 610 case OR1K_OPERAND_RADF :
e4c4ac46
SH
611 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
612 break;
613 case OR1K_OPERAND_RADI :
614 {
615{
616 FLD (f_r2) = ((FLD (f_rad32)) & (31));
617 FLD (f_raoff_9_1) = ((((SI) (FLD (f_rad32)) >> (5))) & (1));
618}
619 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
620 if (errmsg)
621 break;
622 errmsg = insert_normal (cd, fields->f_raoff_9_1, 0, 0, 9, 1, 32, total_length, buffer);
623 if (errmsg)
624 break;
625 }
87e6d782 626 break;
73589c9d
CS
627 case OR1K_OPERAND_RASF :
628 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
87e6d782 629 break;
73589c9d
CS
630 case OR1K_OPERAND_RB :
631 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
87e6d782 632 break;
e4c4ac46
SH
633 case OR1K_OPERAND_RBD32F :
634 {
635{
636 FLD (f_r3) = ((FLD (f_rbd32)) & (31));
637 FLD (f_rboff_8_1) = ((((SI) (FLD (f_rbd32)) >> (5))) & (1));
638}
639 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
640 if (errmsg)
641 break;
642 errmsg = insert_normal (cd, fields->f_rboff_8_1, 0, 0, 8, 1, 32, total_length, buffer);
643 if (errmsg)
644 break;
645 }
646 break;
73589c9d 647 case OR1K_OPERAND_RBDF :
e4c4ac46
SH
648 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
649 break;
650 case OR1K_OPERAND_RBDI :
651 {
652{
653 FLD (f_r3) = ((FLD (f_rbd32)) & (31));
654 FLD (f_rboff_8_1) = ((((SI) (FLD (f_rbd32)) >> (5))) & (1));
655}
656 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
657 if (errmsg)
658 break;
659 errmsg = insert_normal (cd, fields->f_rboff_8_1, 0, 0, 8, 1, 32, total_length, buffer);
660 if (errmsg)
661 break;
662 }
87e6d782 663 break;
73589c9d 664 case OR1K_OPERAND_RBSF :
87e6d782
NC
665 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
666 break;
73589c9d 667 case OR1K_OPERAND_RD :
87e6d782
NC
668 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
669 break;
e4c4ac46
SH
670 case OR1K_OPERAND_RDD32F :
671 {
672{
673 FLD (f_r1) = ((FLD (f_rdd32)) & (31));
674 FLD (f_rdoff_10_1) = ((((SI) (FLD (f_rdd32)) >> (5))) & (1));
675}
676 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
677 if (errmsg)
678 break;
679 errmsg = insert_normal (cd, fields->f_rdoff_10_1, 0, 0, 10, 1, 32, total_length, buffer);
680 if (errmsg)
681 break;
682 }
683 break;
73589c9d
CS
684 case OR1K_OPERAND_RDDF :
685 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
87e6d782 686 break;
e4c4ac46
SH
687 case OR1K_OPERAND_RDDI :
688 {
689{
690 FLD (f_r1) = ((FLD (f_rdd32)) & (31));
691 FLD (f_rdoff_10_1) = ((((SI) (FLD (f_rdd32)) >> (5))) & (1));
692}
693 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
694 if (errmsg)
695 break;
696 errmsg = insert_normal (cd, fields->f_rdoff_10_1, 0, 0, 10, 1, 32, total_length, buffer);
697 if (errmsg)
698 break;
699 }
700 break;
73589c9d
CS
701 case OR1K_OPERAND_RDSF :
702 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
703 break;
704 case OR1K_OPERAND_SIMM16 :
705 errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_SIGN_OPT), 0, 15, 16, 32, total_length, buffer);
706 break;
707 case OR1K_OPERAND_SIMM16_SPLIT :
87e6d782
NC
708 {
709{
73589c9d
CS
710 FLD (f_imm16_25_5) = ((((INT) (FLD (f_simm16_split)) >> (11))) & (31));
711 FLD (f_imm16_10_11) = ((FLD (f_simm16_split)) & (2047));
87e6d782 712}
73589c9d 713 errmsg = insert_normal (cd, fields->f_imm16_25_5, 0, 0, 25, 5, 32, total_length, buffer);
87e6d782
NC
714 if (errmsg)
715 break;
73589c9d 716 errmsg = insert_normal (cd, fields->f_imm16_10_11, 0, 0, 10, 11, 32, total_length, buffer);
87e6d782
NC
717 if (errmsg)
718 break;
719 }
720 break;
73589c9d 721 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
722 errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 15, 16, 32, total_length, buffer);
723 break;
73589c9d
CS
724 case OR1K_OPERAND_UIMM16_SPLIT :
725 {
726{
727 FLD (f_imm16_25_5) = ((((UINT) (FLD (f_uimm16_split)) >> (11))) & (31));
728 FLD (f_imm16_10_11) = ((FLD (f_uimm16_split)) & (2047));
729}
730 errmsg = insert_normal (cd, fields->f_imm16_25_5, 0, 0, 25, 5, 32, total_length, buffer);
731 if (errmsg)
732 break;
733 errmsg = insert_normal (cd, fields->f_imm16_10_11, 0, 0, 10, 11, 32, total_length, buffer);
734 if (errmsg)
735 break;
736 }
737 break;
738 case OR1K_OPERAND_UIMM6 :
739 errmsg = insert_normal (cd, fields->f_uimm6, 0, 0, 5, 6, 32, total_length, buffer);
87e6d782
NC
740 break;
741
742 default :
743 /* xgettext:c-format */
a6743a54
AM
744 opcodes_error_handler
745 (_("internal error: unrecognized field %d while building insn"),
746 opindex);
87e6d782
NC
747 abort ();
748 }
749
750 return errmsg;
751}
752
73589c9d 753int or1k_cgen_extract_operand
47b0e7ad 754 (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
0e2ee3ca 755
87e6d782
NC
756/* Main entry point for operand extraction.
757 The result is <= 0 for error, >0 for success.
758 ??? Actual values aren't well defined right now.
759
760 This function is basically just a big switch statement. Earlier versions
761 used tables to look up the function to use, but
762 - if the table contains both assembler and disassembler functions then
763 the disassembler contains much of the assembler and vice-versa,
764 - there's a lot of inlining possibilities as things grow,
765 - using a switch statement avoids the function call overhead.
766
767 This function could be moved into `print_insn_normal', but keeping it
768 separate makes clear the interface between `print_insn_normal' and each of
9a2e995d 769 the handlers. */
87e6d782
NC
770
771int
73589c9d 772or1k_cgen_extract_operand (CGEN_CPU_DESC cd,
47b0e7ad
NC
773 int opindex,
774 CGEN_EXTRACT_INFO *ex_info,
775 CGEN_INSN_INT insn_value,
776 CGEN_FIELDS * fields,
777 bfd_vma pc)
87e6d782
NC
778{
779 /* Assume success (for those operands that are nops). */
780 int length = 1;
781 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
782
783 switch (opindex)
784 {
c8e98e36
SH
785 case OR1K_OPERAND_DISP21 :
786 {
787 long value;
788 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_ABS_ADDR), 0, 20, 21, 32, total_length, pc, & value);
bcd9f578 789 value = ((((value) + (((DI) (pc) >> (13))))) * (MAKEDI (0, 8192)));
c8e98e36
SH
790 fields->f_disp21 = value;
791 }
792 break;
73589c9d 793 case OR1K_OPERAND_DISP26 :
87e6d782
NC
794 {
795 long value;
796 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, pc, & value);
bcd9f578 797 value = ((((value) * (MAKEDI (0, 4)))) + (pc));
87e6d782
NC
798 fields->f_disp26 = value;
799 }
800 break;
73589c9d
CS
801 case OR1K_OPERAND_RA :
802 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
87e6d782 803 break;
e4c4ac46
SH
804 case OR1K_OPERAND_RAD32F :
805 {
806 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
807 if (length <= 0) break;
808 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_raoff_9_1);
809 if (length <= 0) break;
810 FLD (f_rad32) = ((FLD (f_r2)) | (((FLD (f_raoff_9_1)) << (5))));
811 }
812 break;
73589c9d 813 case OR1K_OPERAND_RADF :
e4c4ac46
SH
814 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
815 break;
816 case OR1K_OPERAND_RADI :
817 {
818 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
819 if (length <= 0) break;
820 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_raoff_9_1);
821 if (length <= 0) break;
822 FLD (f_rad32) = ((FLD (f_r2)) | (((FLD (f_raoff_9_1)) << (5))));
823 }
87e6d782 824 break;
73589c9d
CS
825 case OR1K_OPERAND_RASF :
826 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
87e6d782 827 break;
73589c9d
CS
828 case OR1K_OPERAND_RB :
829 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
87e6d782 830 break;
e4c4ac46
SH
831 case OR1K_OPERAND_RBD32F :
832 {
833 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
834 if (length <= 0) break;
835 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_rboff_8_1);
836 if (length <= 0) break;
837 FLD (f_rbd32) = ((FLD (f_r3)) | (((FLD (f_rboff_8_1)) << (5))));
838 }
839 break;
73589c9d 840 case OR1K_OPERAND_RBDF :
e4c4ac46
SH
841 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
842 break;
843 case OR1K_OPERAND_RBDI :
844 {
845 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
846 if (length <= 0) break;
847 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_rboff_8_1);
848 if (length <= 0) break;
849 FLD (f_rbd32) = ((FLD (f_r3)) | (((FLD (f_rboff_8_1)) << (5))));
850 }
87e6d782 851 break;
73589c9d 852 case OR1K_OPERAND_RBSF :
87e6d782
NC
853 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
854 break;
73589c9d
CS
855 case OR1K_OPERAND_RD :
856 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
857 break;
e4c4ac46
SH
858 case OR1K_OPERAND_RDD32F :
859 {
860 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
861 if (length <= 0) break;
862 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 1, 32, total_length, pc, & fields->f_rdoff_10_1);
863 if (length <= 0) break;
864 FLD (f_rdd32) = ((FLD (f_r1)) | (((FLD (f_rdoff_10_1)) << (5))));
865 }
866 break;
73589c9d
CS
867 case OR1K_OPERAND_RDDF :
868 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
869 break;
e4c4ac46
SH
870 case OR1K_OPERAND_RDDI :
871 {
872 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
873 if (length <= 0) break;
874 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 1, 32, total_length, pc, & fields->f_rdoff_10_1);
875 if (length <= 0) break;
876 FLD (f_rdd32) = ((FLD (f_r1)) | (((FLD (f_rdoff_10_1)) << (5))));
877 }
878 break;
73589c9d 879 case OR1K_OPERAND_RDSF :
87e6d782
NC
880 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
881 break;
73589c9d
CS
882 case OR1K_OPERAND_SIMM16 :
883 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_SIGN_OPT), 0, 15, 16, 32, total_length, pc, & fields->f_simm16);
87e6d782 884 break;
73589c9d 885 case OR1K_OPERAND_SIMM16_SPLIT :
87e6d782 886 {
73589c9d 887 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_imm16_25_5);
87e6d782 888 if (length <= 0) break;
73589c9d 889 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_imm16_10_11);
87e6d782 890 if (length <= 0) break;
73589c9d 891 FLD (f_simm16_split) = ((HI) (UINT) (((((FLD (f_imm16_25_5)) << (11))) | (FLD (f_imm16_10_11)))));
87e6d782
NC
892 }
893 break;
73589c9d 894 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
895 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_uimm16);
896 break;
73589c9d
CS
897 case OR1K_OPERAND_UIMM16_SPLIT :
898 {
899 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_imm16_25_5);
900 if (length <= 0) break;
901 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_imm16_10_11);
902 if (length <= 0) break;
903 FLD (f_uimm16_split) = ((UHI) (UINT) (((((FLD (f_imm16_25_5)) << (11))) | (FLD (f_imm16_10_11)))));
904 }
905 break;
906 case OR1K_OPERAND_UIMM6 :
907 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_uimm6);
87e6d782
NC
908 break;
909
910 default :
911 /* xgettext:c-format */
a6743a54
AM
912 opcodes_error_handler
913 (_("internal error: unrecognized field %d while decoding insn"),
914 opindex);
87e6d782
NC
915 abort ();
916 }
917
918 return length;
919}
920
43e65147 921cgen_insert_fn * const or1k_cgen_insert_handlers[] =
87e6d782
NC
922{
923 insert_insn_normal,
924};
925
43e65147 926cgen_extract_fn * const or1k_cgen_extract_handlers[] =
87e6d782
NC
927{
928 extract_insn_normal,
929};
930
73589c9d
CS
931int or1k_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
932bfd_vma or1k_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
0e2ee3ca 933
87e6d782
NC
934/* Getting values from cgen_fields is handled by a collection of functions.
935 They are distinguished by the type of the VALUE argument they return.
936 TODO: floating point, inlining support, remove cases where result type
937 not appropriate. */
938
939int
73589c9d 940or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
47b0e7ad
NC
941 int opindex,
942 const CGEN_FIELDS * fields)
87e6d782
NC
943{
944 int value;
945
946 switch (opindex)
947 {
c8e98e36
SH
948 case OR1K_OPERAND_DISP21 :
949 value = fields->f_disp21;
950 break;
73589c9d 951 case OR1K_OPERAND_DISP26 :
87e6d782
NC
952 value = fields->f_disp26;
953 break;
73589c9d
CS
954 case OR1K_OPERAND_RA :
955 value = fields->f_r2;
87e6d782 956 break;
e4c4ac46
SH
957 case OR1K_OPERAND_RAD32F :
958 value = fields->f_rad32;
959 break;
73589c9d 960 case OR1K_OPERAND_RADF :
e4c4ac46
SH
961 value = fields->f_r2;
962 break;
963 case OR1K_OPERAND_RADI :
964 value = fields->f_rad32;
87e6d782 965 break;
73589c9d
CS
966 case OR1K_OPERAND_RASF :
967 value = fields->f_r2;
87e6d782 968 break;
73589c9d
CS
969 case OR1K_OPERAND_RB :
970 value = fields->f_r3;
87e6d782 971 break;
e4c4ac46
SH
972 case OR1K_OPERAND_RBD32F :
973 value = fields->f_rbd32;
974 break;
73589c9d 975 case OR1K_OPERAND_RBDF :
e4c4ac46
SH
976 value = fields->f_r3;
977 break;
978 case OR1K_OPERAND_RBDI :
979 value = fields->f_rbd32;
87e6d782 980 break;
73589c9d 981 case OR1K_OPERAND_RBSF :
87e6d782
NC
982 value = fields->f_r3;
983 break;
73589c9d
CS
984 case OR1K_OPERAND_RD :
985 value = fields->f_r1;
986 break;
e4c4ac46
SH
987 case OR1K_OPERAND_RDD32F :
988 value = fields->f_rdd32;
989 break;
73589c9d 990 case OR1K_OPERAND_RDDF :
87e6d782
NC
991 value = fields->f_r1;
992 break;
e4c4ac46
SH
993 case OR1K_OPERAND_RDDI :
994 value = fields->f_rdd32;
995 break;
73589c9d
CS
996 case OR1K_OPERAND_RDSF :
997 value = fields->f_r1;
998 break;
999 case OR1K_OPERAND_SIMM16 :
87e6d782
NC
1000 value = fields->f_simm16;
1001 break;
73589c9d
CS
1002 case OR1K_OPERAND_SIMM16_SPLIT :
1003 value = fields->f_simm16_split;
87e6d782 1004 break;
73589c9d 1005 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
1006 value = fields->f_uimm16;
1007 break;
73589c9d
CS
1008 case OR1K_OPERAND_UIMM16_SPLIT :
1009 value = fields->f_uimm16_split;
1010 break;
1011 case OR1K_OPERAND_UIMM6 :
1012 value = fields->f_uimm6;
87e6d782
NC
1013 break;
1014
1015 default :
1016 /* xgettext:c-format */
a6743a54
AM
1017 opcodes_error_handler
1018 (_("internal error: unrecognized field %d while getting int operand"),
1019 opindex);
87e6d782
NC
1020 abort ();
1021 }
1022
1023 return value;
1024}
1025
1026bfd_vma
73589c9d 1027or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
47b0e7ad
NC
1028 int opindex,
1029 const CGEN_FIELDS * fields)
87e6d782
NC
1030{
1031 bfd_vma value;
1032
1033 switch (opindex)
1034 {
c8e98e36
SH
1035 case OR1K_OPERAND_DISP21 :
1036 value = fields->f_disp21;
1037 break;
73589c9d 1038 case OR1K_OPERAND_DISP26 :
87e6d782
NC
1039 value = fields->f_disp26;
1040 break;
73589c9d
CS
1041 case OR1K_OPERAND_RA :
1042 value = fields->f_r2;
87e6d782 1043 break;
e4c4ac46
SH
1044 case OR1K_OPERAND_RAD32F :
1045 value = fields->f_rad32;
1046 break;
73589c9d 1047 case OR1K_OPERAND_RADF :
e4c4ac46
SH
1048 value = fields->f_r2;
1049 break;
1050 case OR1K_OPERAND_RADI :
1051 value = fields->f_rad32;
87e6d782 1052 break;
73589c9d
CS
1053 case OR1K_OPERAND_RASF :
1054 value = fields->f_r2;
87e6d782 1055 break;
73589c9d
CS
1056 case OR1K_OPERAND_RB :
1057 value = fields->f_r3;
87e6d782 1058 break;
e4c4ac46
SH
1059 case OR1K_OPERAND_RBD32F :
1060 value = fields->f_rbd32;
1061 break;
73589c9d 1062 case OR1K_OPERAND_RBDF :
e4c4ac46
SH
1063 value = fields->f_r3;
1064 break;
1065 case OR1K_OPERAND_RBDI :
1066 value = fields->f_rbd32;
87e6d782 1067 break;
73589c9d 1068 case OR1K_OPERAND_RBSF :
87e6d782
NC
1069 value = fields->f_r3;
1070 break;
73589c9d
CS
1071 case OR1K_OPERAND_RD :
1072 value = fields->f_r1;
1073 break;
e4c4ac46
SH
1074 case OR1K_OPERAND_RDD32F :
1075 value = fields->f_rdd32;
1076 break;
73589c9d
CS
1077 case OR1K_OPERAND_RDDF :
1078 value = fields->f_r1;
1079 break;
e4c4ac46
SH
1080 case OR1K_OPERAND_RDDI :
1081 value = fields->f_rdd32;
1082 break;
73589c9d 1083 case OR1K_OPERAND_RDSF :
87e6d782
NC
1084 value = fields->f_r1;
1085 break;
73589c9d 1086 case OR1K_OPERAND_SIMM16 :
87e6d782
NC
1087 value = fields->f_simm16;
1088 break;
73589c9d
CS
1089 case OR1K_OPERAND_SIMM16_SPLIT :
1090 value = fields->f_simm16_split;
87e6d782 1091 break;
73589c9d 1092 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
1093 value = fields->f_uimm16;
1094 break;
73589c9d
CS
1095 case OR1K_OPERAND_UIMM16_SPLIT :
1096 value = fields->f_uimm16_split;
1097 break;
1098 case OR1K_OPERAND_UIMM6 :
1099 value = fields->f_uimm6;
87e6d782
NC
1100 break;
1101
1102 default :
1103 /* xgettext:c-format */
a6743a54
AM
1104 opcodes_error_handler
1105 (_("internal error: unrecognized field %d while getting vma operand"),
1106 opindex);
87e6d782
NC
1107 abort ();
1108 }
1109
1110 return value;
1111}
1112
73589c9d
CS
1113void or1k_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
1114void or1k_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
0e2ee3ca 1115
87e6d782
NC
1116/* Stuffing values in cgen_fields is handled by a collection of functions.
1117 They are distinguished by the type of the VALUE argument they accept.
1118 TODO: floating point, inlining support, remove cases where argument type
1119 not appropriate. */
1120
1121void
73589c9d 1122or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
47b0e7ad
NC
1123 int opindex,
1124 CGEN_FIELDS * fields,
1125 int value)
87e6d782
NC
1126{
1127 switch (opindex)
1128 {
c8e98e36
SH
1129 case OR1K_OPERAND_DISP21 :
1130 fields->f_disp21 = value;
1131 break;
73589c9d 1132 case OR1K_OPERAND_DISP26 :
87e6d782
NC
1133 fields->f_disp26 = value;
1134 break;
73589c9d
CS
1135 case OR1K_OPERAND_RA :
1136 fields->f_r2 = value;
87e6d782 1137 break;
e4c4ac46
SH
1138 case OR1K_OPERAND_RAD32F :
1139 fields->f_rad32 = value;
1140 break;
73589c9d 1141 case OR1K_OPERAND_RADF :
e4c4ac46
SH
1142 fields->f_r2 = value;
1143 break;
1144 case OR1K_OPERAND_RADI :
1145 fields->f_rad32 = value;
87e6d782 1146 break;
73589c9d
CS
1147 case OR1K_OPERAND_RASF :
1148 fields->f_r2 = value;
87e6d782 1149 break;
73589c9d
CS
1150 case OR1K_OPERAND_RB :
1151 fields->f_r3 = value;
87e6d782 1152 break;
e4c4ac46
SH
1153 case OR1K_OPERAND_RBD32F :
1154 fields->f_rbd32 = value;
1155 break;
73589c9d 1156 case OR1K_OPERAND_RBDF :
e4c4ac46
SH
1157 fields->f_r3 = value;
1158 break;
1159 case OR1K_OPERAND_RBDI :
1160 fields->f_rbd32 = value;
87e6d782 1161 break;
73589c9d 1162 case OR1K_OPERAND_RBSF :
87e6d782
NC
1163 fields->f_r3 = value;
1164 break;
73589c9d 1165 case OR1K_OPERAND_RD :
87e6d782
NC
1166 fields->f_r1 = value;
1167 break;
e4c4ac46
SH
1168 case OR1K_OPERAND_RDD32F :
1169 fields->f_rdd32 = value;
1170 break;
73589c9d
CS
1171 case OR1K_OPERAND_RDDF :
1172 fields->f_r1 = value;
1173 break;
e4c4ac46
SH
1174 case OR1K_OPERAND_RDDI :
1175 fields->f_rdd32 = value;
1176 break;
73589c9d
CS
1177 case OR1K_OPERAND_RDSF :
1178 fields->f_r1 = value;
1179 break;
1180 case OR1K_OPERAND_SIMM16 :
87e6d782
NC
1181 fields->f_simm16 = value;
1182 break;
73589c9d
CS
1183 case OR1K_OPERAND_SIMM16_SPLIT :
1184 fields->f_simm16_split = value;
87e6d782 1185 break;
73589c9d 1186 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
1187 fields->f_uimm16 = value;
1188 break;
73589c9d
CS
1189 case OR1K_OPERAND_UIMM16_SPLIT :
1190 fields->f_uimm16_split = value;
1191 break;
1192 case OR1K_OPERAND_UIMM6 :
1193 fields->f_uimm6 = value;
87e6d782
NC
1194 break;
1195
1196 default :
1197 /* xgettext:c-format */
a6743a54
AM
1198 opcodes_error_handler
1199 (_("internal error: unrecognized field %d while setting int operand"),
1200 opindex);
87e6d782
NC
1201 abort ();
1202 }
1203}
1204
1205void
73589c9d 1206or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
47b0e7ad
NC
1207 int opindex,
1208 CGEN_FIELDS * fields,
1209 bfd_vma value)
87e6d782
NC
1210{
1211 switch (opindex)
1212 {
c8e98e36
SH
1213 case OR1K_OPERAND_DISP21 :
1214 fields->f_disp21 = value;
1215 break;
73589c9d 1216 case OR1K_OPERAND_DISP26 :
87e6d782
NC
1217 fields->f_disp26 = value;
1218 break;
73589c9d
CS
1219 case OR1K_OPERAND_RA :
1220 fields->f_r2 = value;
87e6d782 1221 break;
e4c4ac46
SH
1222 case OR1K_OPERAND_RAD32F :
1223 fields->f_rad32 = value;
1224 break;
73589c9d 1225 case OR1K_OPERAND_RADF :
e4c4ac46
SH
1226 fields->f_r2 = value;
1227 break;
1228 case OR1K_OPERAND_RADI :
1229 fields->f_rad32 = value;
87e6d782 1230 break;
73589c9d
CS
1231 case OR1K_OPERAND_RASF :
1232 fields->f_r2 = value;
87e6d782 1233 break;
73589c9d
CS
1234 case OR1K_OPERAND_RB :
1235 fields->f_r3 = value;
87e6d782 1236 break;
e4c4ac46
SH
1237 case OR1K_OPERAND_RBD32F :
1238 fields->f_rbd32 = value;
1239 break;
73589c9d 1240 case OR1K_OPERAND_RBDF :
e4c4ac46
SH
1241 fields->f_r3 = value;
1242 break;
1243 case OR1K_OPERAND_RBDI :
1244 fields->f_rbd32 = value;
87e6d782 1245 break;
73589c9d 1246 case OR1K_OPERAND_RBSF :
87e6d782
NC
1247 fields->f_r3 = value;
1248 break;
73589c9d
CS
1249 case OR1K_OPERAND_RD :
1250 fields->f_r1 = value;
1251 break;
e4c4ac46
SH
1252 case OR1K_OPERAND_RDD32F :
1253 fields->f_rdd32 = value;
1254 break;
73589c9d 1255 case OR1K_OPERAND_RDDF :
87e6d782
NC
1256 fields->f_r1 = value;
1257 break;
e4c4ac46
SH
1258 case OR1K_OPERAND_RDDI :
1259 fields->f_rdd32 = value;
1260 break;
73589c9d
CS
1261 case OR1K_OPERAND_RDSF :
1262 fields->f_r1 = value;
1263 break;
1264 case OR1K_OPERAND_SIMM16 :
87e6d782
NC
1265 fields->f_simm16 = value;
1266 break;
73589c9d
CS
1267 case OR1K_OPERAND_SIMM16_SPLIT :
1268 fields->f_simm16_split = value;
87e6d782 1269 break;
73589c9d 1270 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
1271 fields->f_uimm16 = value;
1272 break;
73589c9d
CS
1273 case OR1K_OPERAND_UIMM16_SPLIT :
1274 fields->f_uimm16_split = value;
1275 break;
1276 case OR1K_OPERAND_UIMM6 :
1277 fields->f_uimm6 = value;
87e6d782
NC
1278 break;
1279
1280 default :
1281 /* xgettext:c-format */
a6743a54
AM
1282 opcodes_error_handler
1283 (_("internal error: unrecognized field %d while setting vma operand"),
1284 opindex);
87e6d782
NC
1285 abort ();
1286 }
1287}
1288
1289/* Function to call before using the instruction builder tables. */
1290
1291void
73589c9d 1292or1k_cgen_init_ibld_table (CGEN_CPU_DESC cd)
87e6d782 1293{
73589c9d
CS
1294 cd->insert_handlers = & or1k_cgen_insert_handlers[0];
1295 cd->extract_handlers = & or1k_cgen_extract_handlers[0];
87e6d782 1296
73589c9d
CS
1297 cd->insert_operand = or1k_cgen_insert_operand;
1298 cd->extract_operand = or1k_cgen_extract_operand;
87e6d782 1299
73589c9d
CS
1300 cd->get_int_operand = or1k_cgen_get_int_operand;
1301 cd->set_int_operand = or1k_cgen_set_int_operand;
1302 cd->get_vma_operand = or1k_cgen_get_vma_operand;
1303 cd->set_vma_operand = or1k_cgen_set_vma_operand;
87e6d782 1304}
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