Sync dlang demangling tests from upstream libiberty testsuite.
[deliverable/binutils-gdb.git] / opcodes / or1k-ibld.c
CommitLineData
73589c9d 1/* Instruction building/extraction support for or1k. -*- C -*-
87e6d782 2
47b0e7ad
NC
3 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
4 - the resultant file is machine generated, cgen-ibld.in isn't
87e6d782 5
2571583a 6 Copyright (C) 1996-2017 Free Software Foundation, Inc.
87e6d782 7
9b201bb5 8 This file is part of libopcodes.
87e6d782 9
9b201bb5 10 This library is free software; you can redistribute it and/or modify
47b0e7ad 11 it under the terms of the GNU General Public License as published by
9b201bb5 12 the Free Software Foundation; either version 3, or (at your option)
47b0e7ad 13 any later version.
87e6d782 14
9b201bb5
NC
15 It is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
87e6d782 19
47b0e7ad
NC
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
87e6d782
NC
23
24/* ??? Eventually more and more of this stuff can go to cpu-independent files.
25 Keep that in mind. */
26
27#include "sysdep.h"
87e6d782
NC
28#include <stdio.h>
29#include "ansidecl.h"
30#include "dis-asm.h"
31#include "bfd.h"
32#include "symcat.h"
73589c9d
CS
33#include "or1k-desc.h"
34#include "or1k-opc.h"
fe8afbc4 35#include "cgen/basic-modes.h"
87e6d782 36#include "opintl.h"
37111cc7 37#include "safe-ctype.h"
87e6d782 38
47b0e7ad 39#undef min
87e6d782 40#define min(a,b) ((a) < (b) ? (a) : (b))
47b0e7ad 41#undef max
87e6d782
NC
42#define max(a,b) ((a) > (b) ? (a) : (b))
43
44/* Used by the ifield rtx function. */
45#define FLD(f) (fields->f)
46
47static const char * insert_normal
ffead7ae
MM
48 (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
49 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
87e6d782 50static const char * insert_insn_normal
ffead7ae
MM
51 (CGEN_CPU_DESC, const CGEN_INSN *,
52 CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
87e6d782 53static int extract_normal
ffead7ae
MM
54 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
55 unsigned int, unsigned int, unsigned int, unsigned int,
56 unsigned int, unsigned int, bfd_vma, long *);
87e6d782 57static int extract_insn_normal
ffead7ae
MM
58 (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
59 CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
0e2ee3ca 60#if CGEN_INT_INSN_P
87e6d782 61static void put_insn_int_value
ffead7ae 62 (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
0e2ee3ca
NC
63#endif
64#if ! CGEN_INT_INSN_P
65static CGEN_INLINE void insert_1
ffead7ae 66 (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
0e2ee3ca 67static CGEN_INLINE int fill_cache
ffead7ae 68 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma);
0e2ee3ca 69static CGEN_INLINE long extract_1
ffead7ae 70 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
0e2ee3ca 71#endif
87e6d782
NC
72\f
73/* Operand insertion. */
74
75#if ! CGEN_INT_INSN_P
76
77/* Subroutine of insert_normal. */
78
79static CGEN_INLINE void
ffead7ae
MM
80insert_1 (CGEN_CPU_DESC cd,
81 unsigned long value,
82 int start,
83 int length,
84 int word_length,
85 unsigned char *bufp)
87e6d782
NC
86{
87 unsigned long x,mask;
88 int shift;
87e6d782 89
0e2ee3ca 90 x = cgen_get_insn_value (cd, bufp, word_length);
87e6d782
NC
91
92 /* Written this way to avoid undefined behaviour. */
93 mask = (((1L << (length - 1)) - 1) << 1) | 1;
94 if (CGEN_INSN_LSB0_P)
95 shift = (start + 1) - length;
96 else
97 shift = (word_length - (start + length));
98 x = (x & ~(mask << shift)) | ((value & mask) << shift);
99
0e2ee3ca 100 cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
87e6d782
NC
101}
102
103#endif /* ! CGEN_INT_INSN_P */
104
105/* Default insertion routine.
106
107 ATTRS is a mask of the boolean attributes.
108 WORD_OFFSET is the offset in bits from the start of the insn of the value.
109 WORD_LENGTH is the length of the word in bits in which the value resides.
110 START is the starting bit number in the word, architecture origin.
111 LENGTH is the length of VALUE in bits.
112 TOTAL_LENGTH is the total length of the insn in bits.
113
114 The result is an error message or NULL if success. */
115
116/* ??? This duplicates functionality with bfd's howto table and
117 bfd_install_relocation. */
118/* ??? This doesn't handle bfd_vma's. Create another function when
119 necessary. */
120
121static const char *
ffead7ae
MM
122insert_normal (CGEN_CPU_DESC cd,
123 long value,
124 unsigned int attrs,
125 unsigned int word_offset,
126 unsigned int start,
127 unsigned int length,
128 unsigned int word_length,
129 unsigned int total_length,
130 CGEN_INSN_BYTES_PTR buffer)
87e6d782
NC
131{
132 static char errbuf[100];
133 /* Written this way to avoid undefined behaviour. */
134 unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
135
136 /* If LENGTH is zero, this operand doesn't contribute to the value. */
137 if (length == 0)
138 return NULL;
139
b7cd1872 140 if (word_length > 8 * sizeof (CGEN_INSN_INT))
87e6d782
NC
141 abort ();
142
143 /* For architectures with insns smaller than the base-insn-bitsize,
144 word_length may be too big. */
145 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
146 {
147 if (word_offset == 0
148 && word_length > total_length)
149 word_length = total_length;
150 }
151
152 /* Ensure VALUE will fit. */
fc7bc883
RH
153 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
154 {
155 long minval = - (1L << (length - 1));
156 unsigned long maxval = mask;
43e65147 157
fc7bc883
RH
158 if ((value > 0 && (unsigned long) value > maxval)
159 || value < minval)
160 {
161 /* xgettext:c-format */
162 sprintf (errbuf,
163 _("operand out of range (%ld not between %ld and %lu)"),
164 value, minval, maxval);
165 return errbuf;
166 }
167 }
168 else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
87e6d782
NC
169 {
170 unsigned long maxval = mask;
ed963e2d
NC
171 unsigned long val = (unsigned long) value;
172
173 /* For hosts with a word size > 32 check to see if value has been sign
174 extended beyond 32 bits. If so then ignore these higher sign bits
175 as the user is attempting to store a 32-bit signed value into an
176 unsigned 32-bit field which is allowed. */
177 if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
178 val &= 0xFFFFFFFF;
179
180 if (val > maxval)
87e6d782
NC
181 {
182 /* xgettext:c-format */
183 sprintf (errbuf,
ed963e2d
NC
184 _("operand out of range (0x%lx not between 0 and 0x%lx)"),
185 val, maxval);
87e6d782
NC
186 return errbuf;
187 }
188 }
189 else
190 {
191 if (! cgen_signed_overflow_ok_p (cd))
192 {
193 long minval = - (1L << (length - 1));
194 long maxval = (1L << (length - 1)) - 1;
43e65147 195
87e6d782
NC
196 if (value < minval || value > maxval)
197 {
198 sprintf
199 /* xgettext:c-format */
200 (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
201 value, minval, maxval);
202 return errbuf;
203 }
204 }
205 }
206
207#if CGEN_INT_INSN_P
208
209 {
a143b004 210 int shift_within_word, shift_to_word, shift;
87e6d782 211
a143b004
AB
212 /* How to shift the value to BIT0 of the word. */
213 shift_to_word = total_length - (word_offset + word_length);
214
215 /* How to shift the value to the field within the word. */
87e6d782 216 if (CGEN_INSN_LSB0_P)
a143b004 217 shift_within_word = start + 1 - length;
87e6d782 218 else
a143b004
AB
219 shift_within_word = word_length - start - length;
220
221 /* The total SHIFT, then mask in the value. */
222 shift = shift_to_word + shift_within_word;
87e6d782
NC
223 *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
224 }
225
226#else /* ! CGEN_INT_INSN_P */
227
228 {
229 unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
230
231 insert_1 (cd, value, start, length, word_length, bufp);
232 }
233
234#endif /* ! CGEN_INT_INSN_P */
235
236 return NULL;
237}
238
239/* Default insn builder (insert handler).
240 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
241 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
242 recorded in host byte order, otherwise BUFFER is an array of bytes
243 and the value is recorded in target byte order).
244 The result is an error message or NULL if success. */
245
246static const char *
ffead7ae
MM
247insert_insn_normal (CGEN_CPU_DESC cd,
248 const CGEN_INSN * insn,
249 CGEN_FIELDS * fields,
250 CGEN_INSN_BYTES_PTR buffer,
251 bfd_vma pc)
87e6d782
NC
252{
253 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
254 unsigned long value;
255 const CGEN_SYNTAX_CHAR_TYPE * syn;
256
257 CGEN_INIT_INSERT (cd);
258 value = CGEN_INSN_BASE_VALUE (insn);
259
260 /* If we're recording insns as numbers (rather than a string of bytes),
261 target byte order handling is deferred until later. */
262
263#if CGEN_INT_INSN_P
264
265 put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
266 CGEN_FIELDS_BITSIZE (fields), value);
267
268#else
269
0e2ee3ca
NC
270 cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
271 (unsigned) CGEN_FIELDS_BITSIZE (fields)),
87e6d782
NC
272 value);
273
274#endif /* ! CGEN_INT_INSN_P */
275
276 /* ??? It would be better to scan the format's fields.
277 Still need to be able to insert a value based on the operand though;
278 e.g. storing a branch displacement that got resolved later.
279 Needs more thought first. */
280
281 for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
282 {
283 const char *errmsg;
284
285 if (CGEN_SYNTAX_CHAR_P (* syn))
286 continue;
287
288 errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
289 fields, buffer, pc);
290 if (errmsg)
291 return errmsg;
292 }
293
294 return NULL;
295}
296
0e2ee3ca 297#if CGEN_INT_INSN_P
87e6d782 298/* Cover function to store an insn value into an integral insn. Must go here
47b0e7ad 299 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
87e6d782
NC
300
301static void
ffead7ae
MM
302put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
303 CGEN_INSN_BYTES_PTR buf,
304 int length,
305 int insn_length,
306 CGEN_INSN_INT value)
87e6d782
NC
307{
308 /* For architectures with insns smaller than the base-insn-bitsize,
309 length may be too big. */
310 if (length > insn_length)
311 *buf = value;
312 else
313 {
314 int shift = insn_length - length;
315 /* Written this way to avoid undefined behaviour. */
316 CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
47b0e7ad 317
87e6d782
NC
318 *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
319 }
320}
0e2ee3ca 321#endif
87e6d782
NC
322\f
323/* Operand extraction. */
324
325#if ! CGEN_INT_INSN_P
326
327/* Subroutine of extract_normal.
328 Ensure sufficient bytes are cached in EX_INFO.
329 OFFSET is the offset in bytes from the start of the insn of the value.
330 BYTES is the length of the needed value.
331 Returns 1 for success, 0 for failure. */
332
333static CGEN_INLINE int
ffead7ae
MM
334fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
335 CGEN_EXTRACT_INFO *ex_info,
336 int offset,
337 int bytes,
338 bfd_vma pc)
87e6d782
NC
339{
340 /* It's doubtful that the middle part has already been fetched so
341 we don't optimize that case. kiss. */
0e2ee3ca 342 unsigned int mask;
87e6d782
NC
343 disassemble_info *info = (disassemble_info *) ex_info->dis_info;
344
345 /* First do a quick check. */
346 mask = (1 << bytes) - 1;
347 if (((ex_info->valid >> offset) & mask) == mask)
348 return 1;
349
350 /* Search for the first byte we need to read. */
351 for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
352 if (! (mask & ex_info->valid))
353 break;
354
355 if (bytes)
356 {
357 int status;
358
359 pc += offset;
360 status = (*info->read_memory_func)
361 (pc, ex_info->insn_bytes + offset, bytes, info);
362
363 if (status != 0)
364 {
365 (*info->memory_error_func) (status, pc, info);
366 return 0;
367 }
368
369 ex_info->valid |= ((1 << bytes) - 1) << offset;
370 }
371
372 return 1;
373}
374
375/* Subroutine of extract_normal. */
376
377static CGEN_INLINE long
ffead7ae
MM
378extract_1 (CGEN_CPU_DESC cd,
379 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
380 int start,
381 int length,
382 int word_length,
383 unsigned char *bufp,
384 bfd_vma pc ATTRIBUTE_UNUSED)
87e6d782
NC
385{
386 unsigned long x;
387 int shift;
47b0e7ad 388
e333d2c4
NC
389 x = cgen_get_insn_value (cd, bufp, word_length);
390
87e6d782
NC
391 if (CGEN_INSN_LSB0_P)
392 shift = (start + 1) - length;
393 else
394 shift = (word_length - (start + length));
395 return x >> shift;
396}
397
398#endif /* ! CGEN_INT_INSN_P */
399
400/* Default extraction routine.
401
402 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
403 or sometimes less for cases like the m32r where the base insn size is 32
404 but some insns are 16 bits.
405 ATTRS is a mask of the boolean attributes. We only need `SIGNED',
406 but for generality we take a bitmask of all of them.
407 WORD_OFFSET is the offset in bits from the start of the insn of the value.
408 WORD_LENGTH is the length of the word in bits in which the value resides.
409 START is the starting bit number in the word, architecture origin.
410 LENGTH is the length of VALUE in bits.
411 TOTAL_LENGTH is the total length of the insn in bits.
412
413 Returns 1 for success, 0 for failure. */
414
415/* ??? The return code isn't properly used. wip. */
416
417/* ??? This doesn't handle bfd_vma's. Create another function when
418 necessary. */
419
420static int
ffead7ae 421extract_normal (CGEN_CPU_DESC cd,
87e6d782 422#if ! CGEN_INT_INSN_P
ffead7ae 423 CGEN_EXTRACT_INFO *ex_info,
87e6d782 424#else
ffead7ae 425 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
87e6d782 426#endif
ffead7ae
MM
427 CGEN_INSN_INT insn_value,
428 unsigned int attrs,
429 unsigned int word_offset,
430 unsigned int start,
431 unsigned int length,
432 unsigned int word_length,
433 unsigned int total_length,
87e6d782 434#if ! CGEN_INT_INSN_P
ffead7ae 435 bfd_vma pc,
87e6d782 436#else
ffead7ae 437 bfd_vma pc ATTRIBUTE_UNUSED,
87e6d782 438#endif
ffead7ae 439 long *valuep)
87e6d782 440{
fc7bc883 441 long value, mask;
87e6d782
NC
442
443 /* If LENGTH is zero, this operand doesn't contribute to the value
444 so give it a standard value of zero. */
445 if (length == 0)
446 {
447 *valuep = 0;
448 return 1;
449 }
450
b7cd1872 451 if (word_length > 8 * sizeof (CGEN_INSN_INT))
87e6d782
NC
452 abort ();
453
454 /* For architectures with insns smaller than the insn-base-bitsize,
455 word_length may be too big. */
456 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
457 {
ed963e2d
NC
458 if (word_offset + word_length > total_length)
459 word_length = total_length - word_offset;
87e6d782
NC
460 }
461
fc7bc883 462 /* Does the value reside in INSN_VALUE, and at the right alignment? */
87e6d782 463
fc7bc883 464 if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
87e6d782
NC
465 {
466 if (CGEN_INSN_LSB0_P)
467 value = insn_value >> ((word_offset + start + 1) - length);
468 else
469 value = insn_value >> (total_length - ( word_offset + start + length));
470 }
471
472#if ! CGEN_INT_INSN_P
473
474 else
475 {
476 unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
477
b7cd1872 478 if (word_length > 8 * sizeof (CGEN_INSN_INT))
87e6d782
NC
479 abort ();
480
481 if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
482 return 0;
483
484 value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
485 }
486
487#endif /* ! CGEN_INT_INSN_P */
488
489 /* Written this way to avoid undefined behaviour. */
490 mask = (((1L << (length - 1)) - 1) << 1) | 1;
491
492 value &= mask;
493 /* sign extend? */
494 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
495 && (value & (1L << (length - 1))))
496 value |= ~mask;
497
498 *valuep = value;
499
500 return 1;
501}
502
503/* Default insn extractor.
504
505 INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
506 The extracted fields are stored in FIELDS.
507 EX_INFO is used to handle reading variable length insns.
508 Return the length of the insn in bits, or 0 if no match,
509 or -1 if an error occurs fetching data (memory_error_func will have
510 been called). */
511
512static int
ffead7ae
MM
513extract_insn_normal (CGEN_CPU_DESC cd,
514 const CGEN_INSN *insn,
515 CGEN_EXTRACT_INFO *ex_info,
516 CGEN_INSN_INT insn_value,
517 CGEN_FIELDS *fields,
518 bfd_vma pc)
87e6d782
NC
519{
520 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
521 const CGEN_SYNTAX_CHAR_TYPE *syn;
522
523 CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
524
525 CGEN_INIT_EXTRACT (cd);
526
527 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
528 {
529 int length;
530
531 if (CGEN_SYNTAX_CHAR_P (*syn))
532 continue;
533
534 length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
535 ex_info, insn_value, fields, pc);
536 if (length <= 0)
537 return length;
538 }
539
540 /* We recognized and successfully extracted this insn. */
541 return CGEN_INSN_BITSIZE (insn);
542}
543\f
47b0e7ad 544/* Machine generated code added here. */
87e6d782 545
73589c9d 546const char * or1k_cgen_insert_operand
47b0e7ad 547 (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
0e2ee3ca 548
87e6d782
NC
549/* Main entry point for operand insertion.
550
551 This function is basically just a big switch statement. Earlier versions
552 used tables to look up the function to use, but
553 - if the table contains both assembler and disassembler functions then
554 the disassembler contains much of the assembler and vice-versa,
555 - there's a lot of inlining possibilities as things grow,
556 - using a switch statement avoids the function call overhead.
557
558 This function could be moved into `parse_insn_normal', but keeping it
559 separate makes clear the interface between `parse_insn_normal' and each of
560 the handlers. It's also needed by GAS to insert operands that couldn't be
9a2e995d 561 resolved during parsing. */
87e6d782
NC
562
563const char *
73589c9d 564or1k_cgen_insert_operand (CGEN_CPU_DESC cd,
47b0e7ad
NC
565 int opindex,
566 CGEN_FIELDS * fields,
567 CGEN_INSN_BYTES_PTR buffer,
568 bfd_vma pc ATTRIBUTE_UNUSED)
87e6d782
NC
569{
570 const char * errmsg = NULL;
571 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
572
573 switch (opindex)
574 {
73589c9d 575 case OR1K_OPERAND_DISP26 :
87e6d782
NC
576 {
577 long value = fields->f_disp26;
fe8afbc4 578 value = ((SI) (((value) - (pc))) >> (2));
87e6d782
NC
579 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, buffer);
580 }
581 break;
73589c9d
CS
582 case OR1K_OPERAND_RA :
583 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
87e6d782 584 break;
73589c9d
CS
585 case OR1K_OPERAND_RADF :
586 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
87e6d782 587 break;
73589c9d
CS
588 case OR1K_OPERAND_RASF :
589 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
87e6d782 590 break;
73589c9d
CS
591 case OR1K_OPERAND_RB :
592 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
87e6d782 593 break;
73589c9d
CS
594 case OR1K_OPERAND_RBDF :
595 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
87e6d782 596 break;
73589c9d 597 case OR1K_OPERAND_RBSF :
87e6d782
NC
598 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
599 break;
73589c9d 600 case OR1K_OPERAND_RD :
87e6d782
NC
601 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
602 break;
73589c9d
CS
603 case OR1K_OPERAND_RDDF :
604 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
87e6d782 605 break;
73589c9d
CS
606 case OR1K_OPERAND_RDSF :
607 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
608 break;
609 case OR1K_OPERAND_SIMM16 :
610 errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_SIGN_OPT), 0, 15, 16, 32, total_length, buffer);
611 break;
612 case OR1K_OPERAND_SIMM16_SPLIT :
87e6d782
NC
613 {
614{
73589c9d
CS
615 FLD (f_imm16_25_5) = ((((INT) (FLD (f_simm16_split)) >> (11))) & (31));
616 FLD (f_imm16_10_11) = ((FLD (f_simm16_split)) & (2047));
87e6d782 617}
73589c9d 618 errmsg = insert_normal (cd, fields->f_imm16_25_5, 0, 0, 25, 5, 32, total_length, buffer);
87e6d782
NC
619 if (errmsg)
620 break;
73589c9d 621 errmsg = insert_normal (cd, fields->f_imm16_10_11, 0, 0, 10, 11, 32, total_length, buffer);
87e6d782
NC
622 if (errmsg)
623 break;
624 }
625 break;
73589c9d 626 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
627 errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 15, 16, 32, total_length, buffer);
628 break;
73589c9d
CS
629 case OR1K_OPERAND_UIMM16_SPLIT :
630 {
631{
632 FLD (f_imm16_25_5) = ((((UINT) (FLD (f_uimm16_split)) >> (11))) & (31));
633 FLD (f_imm16_10_11) = ((FLD (f_uimm16_split)) & (2047));
634}
635 errmsg = insert_normal (cd, fields->f_imm16_25_5, 0, 0, 25, 5, 32, total_length, buffer);
636 if (errmsg)
637 break;
638 errmsg = insert_normal (cd, fields->f_imm16_10_11, 0, 0, 10, 11, 32, total_length, buffer);
639 if (errmsg)
640 break;
641 }
642 break;
643 case OR1K_OPERAND_UIMM6 :
644 errmsg = insert_normal (cd, fields->f_uimm6, 0, 0, 5, 6, 32, total_length, buffer);
87e6d782
NC
645 break;
646
647 default :
648 /* xgettext:c-format */
649 fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
650 opindex);
651 abort ();
652 }
653
654 return errmsg;
655}
656
73589c9d 657int or1k_cgen_extract_operand
47b0e7ad 658 (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
0e2ee3ca 659
87e6d782
NC
660/* Main entry point for operand extraction.
661 The result is <= 0 for error, >0 for success.
662 ??? Actual values aren't well defined right now.
663
664 This function is basically just a big switch statement. Earlier versions
665 used tables to look up the function to use, but
666 - if the table contains both assembler and disassembler functions then
667 the disassembler contains much of the assembler and vice-versa,
668 - there's a lot of inlining possibilities as things grow,
669 - using a switch statement avoids the function call overhead.
670
671 This function could be moved into `print_insn_normal', but keeping it
672 separate makes clear the interface between `print_insn_normal' and each of
9a2e995d 673 the handlers. */
87e6d782
NC
674
675int
73589c9d 676or1k_cgen_extract_operand (CGEN_CPU_DESC cd,
47b0e7ad
NC
677 int opindex,
678 CGEN_EXTRACT_INFO *ex_info,
679 CGEN_INSN_INT insn_value,
680 CGEN_FIELDS * fields,
681 bfd_vma pc)
87e6d782
NC
682{
683 /* Assume success (for those operands that are nops). */
684 int length = 1;
685 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
686
687 switch (opindex)
688 {
73589c9d 689 case OR1K_OPERAND_DISP26 :
87e6d782
NC
690 {
691 long value;
692 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, pc, & value);
693 value = ((((value) << (2))) + (pc));
694 fields->f_disp26 = value;
695 }
696 break;
73589c9d
CS
697 case OR1K_OPERAND_RA :
698 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
87e6d782 699 break;
73589c9d
CS
700 case OR1K_OPERAND_RADF :
701 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
87e6d782 702 break;
73589c9d
CS
703 case OR1K_OPERAND_RASF :
704 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
87e6d782 705 break;
73589c9d
CS
706 case OR1K_OPERAND_RB :
707 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
87e6d782 708 break;
73589c9d
CS
709 case OR1K_OPERAND_RBDF :
710 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
87e6d782 711 break;
73589c9d 712 case OR1K_OPERAND_RBSF :
87e6d782
NC
713 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
714 break;
73589c9d
CS
715 case OR1K_OPERAND_RD :
716 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
717 break;
718 case OR1K_OPERAND_RDDF :
719 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
720 break;
721 case OR1K_OPERAND_RDSF :
87e6d782
NC
722 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
723 break;
73589c9d
CS
724 case OR1K_OPERAND_SIMM16 :
725 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_SIGN_OPT), 0, 15, 16, 32, total_length, pc, & fields->f_simm16);
87e6d782 726 break;
73589c9d 727 case OR1K_OPERAND_SIMM16_SPLIT :
87e6d782 728 {
73589c9d 729 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_imm16_25_5);
87e6d782 730 if (length <= 0) break;
73589c9d 731 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_imm16_10_11);
87e6d782 732 if (length <= 0) break;
73589c9d 733 FLD (f_simm16_split) = ((HI) (UINT) (((((FLD (f_imm16_25_5)) << (11))) | (FLD (f_imm16_10_11)))));
87e6d782
NC
734 }
735 break;
73589c9d 736 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
737 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_uimm16);
738 break;
73589c9d
CS
739 case OR1K_OPERAND_UIMM16_SPLIT :
740 {
741 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_imm16_25_5);
742 if (length <= 0) break;
743 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_imm16_10_11);
744 if (length <= 0) break;
745 FLD (f_uimm16_split) = ((UHI) (UINT) (((((FLD (f_imm16_25_5)) << (11))) | (FLD (f_imm16_10_11)))));
746 }
747 break;
748 case OR1K_OPERAND_UIMM6 :
749 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_uimm6);
87e6d782
NC
750 break;
751
752 default :
753 /* xgettext:c-format */
754 fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
755 opindex);
756 abort ();
757 }
758
759 return length;
760}
761
43e65147 762cgen_insert_fn * const or1k_cgen_insert_handlers[] =
87e6d782
NC
763{
764 insert_insn_normal,
765};
766
43e65147 767cgen_extract_fn * const or1k_cgen_extract_handlers[] =
87e6d782
NC
768{
769 extract_insn_normal,
770};
771
73589c9d
CS
772int or1k_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
773bfd_vma or1k_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
0e2ee3ca 774
87e6d782
NC
775/* Getting values from cgen_fields is handled by a collection of functions.
776 They are distinguished by the type of the VALUE argument they return.
777 TODO: floating point, inlining support, remove cases where result type
778 not appropriate. */
779
780int
73589c9d 781or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
47b0e7ad
NC
782 int opindex,
783 const CGEN_FIELDS * fields)
87e6d782
NC
784{
785 int value;
786
787 switch (opindex)
788 {
73589c9d 789 case OR1K_OPERAND_DISP26 :
87e6d782
NC
790 value = fields->f_disp26;
791 break;
73589c9d
CS
792 case OR1K_OPERAND_RA :
793 value = fields->f_r2;
87e6d782 794 break;
73589c9d
CS
795 case OR1K_OPERAND_RADF :
796 value = fields->f_r1;
87e6d782 797 break;
73589c9d
CS
798 case OR1K_OPERAND_RASF :
799 value = fields->f_r2;
87e6d782 800 break;
73589c9d
CS
801 case OR1K_OPERAND_RB :
802 value = fields->f_r3;
87e6d782 803 break;
73589c9d
CS
804 case OR1K_OPERAND_RBDF :
805 value = fields->f_r1;
87e6d782 806 break;
73589c9d 807 case OR1K_OPERAND_RBSF :
87e6d782
NC
808 value = fields->f_r3;
809 break;
73589c9d
CS
810 case OR1K_OPERAND_RD :
811 value = fields->f_r1;
812 break;
813 case OR1K_OPERAND_RDDF :
87e6d782
NC
814 value = fields->f_r1;
815 break;
73589c9d
CS
816 case OR1K_OPERAND_RDSF :
817 value = fields->f_r1;
818 break;
819 case OR1K_OPERAND_SIMM16 :
87e6d782
NC
820 value = fields->f_simm16;
821 break;
73589c9d
CS
822 case OR1K_OPERAND_SIMM16_SPLIT :
823 value = fields->f_simm16_split;
87e6d782 824 break;
73589c9d 825 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
826 value = fields->f_uimm16;
827 break;
73589c9d
CS
828 case OR1K_OPERAND_UIMM16_SPLIT :
829 value = fields->f_uimm16_split;
830 break;
831 case OR1K_OPERAND_UIMM6 :
832 value = fields->f_uimm6;
87e6d782
NC
833 break;
834
835 default :
836 /* xgettext:c-format */
837 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
838 opindex);
839 abort ();
840 }
841
842 return value;
843}
844
845bfd_vma
73589c9d 846or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
47b0e7ad
NC
847 int opindex,
848 const CGEN_FIELDS * fields)
87e6d782
NC
849{
850 bfd_vma value;
851
852 switch (opindex)
853 {
73589c9d 854 case OR1K_OPERAND_DISP26 :
87e6d782
NC
855 value = fields->f_disp26;
856 break;
73589c9d
CS
857 case OR1K_OPERAND_RA :
858 value = fields->f_r2;
87e6d782 859 break;
73589c9d
CS
860 case OR1K_OPERAND_RADF :
861 value = fields->f_r1;
87e6d782 862 break;
73589c9d
CS
863 case OR1K_OPERAND_RASF :
864 value = fields->f_r2;
87e6d782 865 break;
73589c9d
CS
866 case OR1K_OPERAND_RB :
867 value = fields->f_r3;
87e6d782 868 break;
73589c9d
CS
869 case OR1K_OPERAND_RBDF :
870 value = fields->f_r1;
87e6d782 871 break;
73589c9d 872 case OR1K_OPERAND_RBSF :
87e6d782
NC
873 value = fields->f_r3;
874 break;
73589c9d
CS
875 case OR1K_OPERAND_RD :
876 value = fields->f_r1;
877 break;
878 case OR1K_OPERAND_RDDF :
879 value = fields->f_r1;
880 break;
881 case OR1K_OPERAND_RDSF :
87e6d782
NC
882 value = fields->f_r1;
883 break;
73589c9d 884 case OR1K_OPERAND_SIMM16 :
87e6d782
NC
885 value = fields->f_simm16;
886 break;
73589c9d
CS
887 case OR1K_OPERAND_SIMM16_SPLIT :
888 value = fields->f_simm16_split;
87e6d782 889 break;
73589c9d 890 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
891 value = fields->f_uimm16;
892 break;
73589c9d
CS
893 case OR1K_OPERAND_UIMM16_SPLIT :
894 value = fields->f_uimm16_split;
895 break;
896 case OR1K_OPERAND_UIMM6 :
897 value = fields->f_uimm6;
87e6d782
NC
898 break;
899
900 default :
901 /* xgettext:c-format */
902 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
903 opindex);
904 abort ();
905 }
906
907 return value;
908}
909
73589c9d
CS
910void or1k_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
911void or1k_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
0e2ee3ca 912
87e6d782
NC
913/* Stuffing values in cgen_fields is handled by a collection of functions.
914 They are distinguished by the type of the VALUE argument they accept.
915 TODO: floating point, inlining support, remove cases where argument type
916 not appropriate. */
917
918void
73589c9d 919or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
47b0e7ad
NC
920 int opindex,
921 CGEN_FIELDS * fields,
922 int value)
87e6d782
NC
923{
924 switch (opindex)
925 {
73589c9d 926 case OR1K_OPERAND_DISP26 :
87e6d782
NC
927 fields->f_disp26 = value;
928 break;
73589c9d
CS
929 case OR1K_OPERAND_RA :
930 fields->f_r2 = value;
87e6d782 931 break;
73589c9d
CS
932 case OR1K_OPERAND_RADF :
933 fields->f_r1 = value;
87e6d782 934 break;
73589c9d
CS
935 case OR1K_OPERAND_RASF :
936 fields->f_r2 = value;
87e6d782 937 break;
73589c9d
CS
938 case OR1K_OPERAND_RB :
939 fields->f_r3 = value;
87e6d782 940 break;
73589c9d
CS
941 case OR1K_OPERAND_RBDF :
942 fields->f_r1 = value;
87e6d782 943 break;
73589c9d 944 case OR1K_OPERAND_RBSF :
87e6d782
NC
945 fields->f_r3 = value;
946 break;
73589c9d 947 case OR1K_OPERAND_RD :
87e6d782
NC
948 fields->f_r1 = value;
949 break;
73589c9d
CS
950 case OR1K_OPERAND_RDDF :
951 fields->f_r1 = value;
952 break;
953 case OR1K_OPERAND_RDSF :
954 fields->f_r1 = value;
955 break;
956 case OR1K_OPERAND_SIMM16 :
87e6d782
NC
957 fields->f_simm16 = value;
958 break;
73589c9d
CS
959 case OR1K_OPERAND_SIMM16_SPLIT :
960 fields->f_simm16_split = value;
87e6d782 961 break;
73589c9d 962 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
963 fields->f_uimm16 = value;
964 break;
73589c9d
CS
965 case OR1K_OPERAND_UIMM16_SPLIT :
966 fields->f_uimm16_split = value;
967 break;
968 case OR1K_OPERAND_UIMM6 :
969 fields->f_uimm6 = value;
87e6d782
NC
970 break;
971
972 default :
973 /* xgettext:c-format */
974 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
975 opindex);
976 abort ();
977 }
978}
979
980void
73589c9d 981or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
47b0e7ad
NC
982 int opindex,
983 CGEN_FIELDS * fields,
984 bfd_vma value)
87e6d782
NC
985{
986 switch (opindex)
987 {
73589c9d 988 case OR1K_OPERAND_DISP26 :
87e6d782
NC
989 fields->f_disp26 = value;
990 break;
73589c9d
CS
991 case OR1K_OPERAND_RA :
992 fields->f_r2 = value;
87e6d782 993 break;
73589c9d
CS
994 case OR1K_OPERAND_RADF :
995 fields->f_r1 = value;
87e6d782 996 break;
73589c9d
CS
997 case OR1K_OPERAND_RASF :
998 fields->f_r2 = value;
87e6d782 999 break;
73589c9d
CS
1000 case OR1K_OPERAND_RB :
1001 fields->f_r3 = value;
87e6d782 1002 break;
73589c9d
CS
1003 case OR1K_OPERAND_RBDF :
1004 fields->f_r1 = value;
87e6d782 1005 break;
73589c9d 1006 case OR1K_OPERAND_RBSF :
87e6d782
NC
1007 fields->f_r3 = value;
1008 break;
73589c9d
CS
1009 case OR1K_OPERAND_RD :
1010 fields->f_r1 = value;
1011 break;
1012 case OR1K_OPERAND_RDDF :
87e6d782
NC
1013 fields->f_r1 = value;
1014 break;
73589c9d
CS
1015 case OR1K_OPERAND_RDSF :
1016 fields->f_r1 = value;
1017 break;
1018 case OR1K_OPERAND_SIMM16 :
87e6d782
NC
1019 fields->f_simm16 = value;
1020 break;
73589c9d
CS
1021 case OR1K_OPERAND_SIMM16_SPLIT :
1022 fields->f_simm16_split = value;
87e6d782 1023 break;
73589c9d 1024 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
1025 fields->f_uimm16 = value;
1026 break;
73589c9d
CS
1027 case OR1K_OPERAND_UIMM16_SPLIT :
1028 fields->f_uimm16_split = value;
1029 break;
1030 case OR1K_OPERAND_UIMM6 :
1031 fields->f_uimm6 = value;
87e6d782
NC
1032 break;
1033
1034 default :
1035 /* xgettext:c-format */
1036 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
1037 opindex);
1038 abort ();
1039 }
1040}
1041
1042/* Function to call before using the instruction builder tables. */
1043
1044void
73589c9d 1045or1k_cgen_init_ibld_table (CGEN_CPU_DESC cd)
87e6d782 1046{
73589c9d
CS
1047 cd->insert_handlers = & or1k_cgen_insert_handlers[0];
1048 cd->extract_handlers = & or1k_cgen_extract_handlers[0];
87e6d782 1049
73589c9d
CS
1050 cd->insert_operand = or1k_cgen_insert_operand;
1051 cd->extract_operand = or1k_cgen_extract_operand;
87e6d782 1052
73589c9d
CS
1053 cd->get_int_operand = or1k_cgen_get_int_operand;
1054 cd->set_int_operand = or1k_cgen_set_int_operand;
1055 cd->get_vma_operand = or1k_cgen_get_vma_operand;
1056 cd->set_vma_operand = or1k_cgen_set_vma_operand;
87e6d782 1057}
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