[deliverable/binutils-gdb.git] / opcodes / ppc-dis.c

/* ppc-dis.c -- Disassemble PowerPC instructions
   Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
   2008, 2009, 2010 Free Software Foundation, Inc.
   Written by Ian Lance Taylor, Cygnus Support

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with this file; see the file COPYING.  If not, write to the
   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */

#include <stdio.h>
#include "sysdep.h"
#include "dis-asm.h"
#include "opintl.h"
#include "opcode/ppc.h"

/* This file provides several disassembler functions, all of which use
   the disassembler interface defined in dis-asm.h.  Several functions
   are provided because this file handles disassembly for the PowerPC
   in both big and little endian mode and also for the POWER (RS/6000)
   chip.  */
static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
			       ppc_cpu_t);

struct dis_private
{
  /* Stash the result of parsing disassembler_options here.  */
  ppc_cpu_t dialect;
};

#define POWERPC_DIALECT(INFO) \
  (((struct dis_private *) ((INFO)->private_data))->dialect)

struct ppc_mopt {
  const char *opt;
  ppc_cpu_t cpu;
  ppc_cpu_t sticky;
};

struct ppc_mopt ppc_opts[] = {
  { "403",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_403
		| PPC_OPCODE_32),
    0 },
  { "405",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_403
		| PPC_OPCODE_405 | PPC_OPCODE_32),
    0 },
  { "440",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32
		| PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
    0 },
  { "464",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32
		| PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
    0 },
  { "476",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ISEL
		| PPC_OPCODE_440 | PPC_OPCODE_476 | PPC_OPCODE_POWER4
		| PPC_OPCODE_POWER5),
    0 },
  { "601",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_601
		| PPC_OPCODE_32),
    0 },
  { "603",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32),
    0 },
  { "604",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32),
    0 },
  { "620",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64),
    0 },
  { "7400",    (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ALTIVEC
		| PPC_OPCODE_32),
    0 },
  { "7410",    (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ALTIVEC
		| PPC_OPCODE_32),
    0 },
  { "7450",    (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ALTIVEC
		| PPC_OPCODE_32),
    0 },
  { "7455",    (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ALTIVEC
		| PPC_OPCODE_32),
    0 },
  { "750cl",   (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS)
    , 0 },
  { "altivec", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC),
    PPC_OPCODE_ALTIVEC },
  { "any",     0,
    PPC_OPCODE_ANY },
  { "booke",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32),
    0 },
  { "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32),
    0 },
  { "cell",    (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64
		| PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
    0 },
  { "com",     (PPC_OPCODE_COMMON | PPC_OPCODE_32),
    0 },
  { "e300",    (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32
		| PPC_OPCODE_E300),
    0 },
  { "e500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
		| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
		| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
		| PPC_OPCODE_E500MC),
    0 },
  { "e500mc",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
		| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
		| PPC_OPCODE_E500MC),
    0 },
  { "e500mc64",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
		| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
		| PPC_OPCODE_64 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
		| PPC_OPCODE_POWER7),
    0 },
  { "e500x2",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
		| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
		| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
		| PPC_OPCODE_E500MC),
    0 },
  { "efs",     (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
    0 },
  { "power4",  (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64
		| PPC_OPCODE_POWER4),
    0 },
  { "power5",  (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64
		| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
    0 },
  { "power6",  (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64
		| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
		| PPC_OPCODE_ALTIVEC),
    0 },
  { "power7",  (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ISEL
		| PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5
		| PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC
		| PPC_OPCODE_VSX),
    0 },
  { "ppc",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32),
    0 },
  { "ppc32",   (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32),
    0 },
  { "ppc64",   (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64),
    0 },
  { "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64_BRIDGE
		    | PPC_OPCODE_64),
    0 },
  { "a2",      (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ISEL
		| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK
		| PPC_OPCODE_64 | PPC_OPCODE_A2),
    0 },
  { "ppcps",   (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS),
    0 },
  { "pwr",     (PPC_OPCODE_POWER | PPC_OPCODE_32),
    0 },
  { "pwr2",    (PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_32),
    0 },
  { "pwrx",    (PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_32),
    0 },
  { "spe",     (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
    PPC_OPCODE_SPE },
  { "vsx",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC),
    PPC_OPCODE_VSX },
};

/* Handle -m and -M options that set cpu type, and .machine arg.  */

ppc_cpu_t
ppc_parse_cpu (ppc_cpu_t ppc_cpu, const char *arg)
{
  /* Sticky bits.  */
  ppc_cpu_t retain_flags = ppc_cpu & (PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX
				      | PPC_OPCODE_SPE | PPC_OPCODE_ANY);
  unsigned int i;

  for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
    if (strcmp (ppc_opts[i].opt, arg) == 0)
      {
	if (ppc_opts[i].sticky)
	  {
	    retain_flags |= ppc_opts[i].sticky;
	    if ((ppc_cpu & ~(PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX
			     | PPC_OPCODE_SPE | PPC_OPCODE_ANY)) != 0)
	      break;
	  }
	ppc_cpu = ppc_opts[i].cpu;
	break;
      }
  if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0]))
    return 0;

  ppc_cpu |= retain_flags;
  return ppc_cpu;
}

/* Determine which set of machines to disassemble for.  */

static int
powerpc_init_dialect (struct disassemble_info *info)
{
  ppc_cpu_t dialect = 0;
  char *arg;
  struct dis_private *priv = calloc (sizeof (*priv), 1);

  if (priv == NULL)
    return FALSE;

  arg = info->disassembler_options;
  while (arg != NULL)
    {
      ppc_cpu_t new_cpu = 0;
      char *end = strchr (arg, ',');

      if (end != NULL)
	*end = 0;

      if ((new_cpu = ppc_parse_cpu (dialect, arg)) != 0)
	dialect = new_cpu;
      else if (strcmp (arg, "32") == 0)
	{
	  dialect &= ~PPC_OPCODE_64;
	  dialect |= PPC_OPCODE_32;
	}
      else if (strcmp (arg, "64") == 0)
	{
	  dialect |= PPC_OPCODE_64;
	  dialect &= ~PPC_OPCODE_32;
	}
      else
	fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg);

      if (end != NULL)
	*end++ = ',';
      arg = end;
    }

  if ((dialect & ~(PPC_OPCODE_32 | PPC_OPCODE_64)) == 0)
    {
      if (info->mach == bfd_mach_ppc64)
	dialect |= PPC_OPCODE_64;
      else
	dialect |= PPC_OPCODE_32;
      /* Choose a reasonable default.  */
      dialect |= (PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_CLASSIC
		  | PPC_OPCODE_601 | PPC_OPCODE_ALTIVEC);
    }

  info->private_data = priv;
  POWERPC_DIALECT(info) = dialect;

  return TRUE;
}

/* Print a big endian PowerPC instruction.  */

int
print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
{
  if (info->private_data == NULL && !powerpc_init_dialect (info))
    return -1;
  return print_insn_powerpc (memaddr, info, 1, POWERPC_DIALECT(info));
}

/* Print a little endian PowerPC instruction.  */

int
print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
{
  if (info->private_data == NULL && !powerpc_init_dialect (info))
    return -1;
  return print_insn_powerpc (memaddr, info, 0, POWERPC_DIALECT(info));
}

/* Print a POWER (RS/6000) instruction.  */

int
print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
{
  return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
}

/* Extract the operand value from the PowerPC or POWER instruction.  */

static long
operand_value_powerpc (const struct powerpc_operand *operand,
		       unsigned long insn, ppc_cpu_t dialect)
{
  long value;
  int invalid;
  /* Extract the value from the instruction.  */
  if (operand->extract)
    value = (*operand->extract) (insn, dialect, &invalid);
  else
    {
      value = (insn >> operand->shift) & operand->bitm;
      if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
	{
	  /* BITM is always some number of zeros followed by some
	     number of ones, followed by some numer of zeros.  */
	  unsigned long top = operand->bitm;
	  /* top & -top gives the rightmost 1 bit, so this
	     fills in any trailing zeros.  */
	  top |= (top & -top) - 1;
	  top &= ~(top >> 1);
	  value = (value ^ top) - top;
	}
    }

  return value;
}

/* Determine whether the optional operand(s) should be printed.  */

static int
skip_optional_operands (const unsigned char *opindex,
			unsigned long insn, ppc_cpu_t dialect)
{
  const struct powerpc_operand *operand;

  for (; *opindex != 0; opindex++)
    {
      operand = &powerpc_operands[*opindex];
      if ((operand->flags & PPC_OPERAND_NEXT) != 0
	  || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
	      && operand_value_powerpc (operand, insn, dialect) != 0))
	return 0;
    }

  return 1;
}

/* Print a PowerPC or POWER instruction.  */

static int
print_insn_powerpc (bfd_vma memaddr,
		    struct disassemble_info *info,
		    int bigendian,
		    ppc_cpu_t dialect)
{
  bfd_byte buffer[4];
  int status;
  unsigned long insn;
  const struct powerpc_opcode *opcode;
  const struct powerpc_opcode *opcode_end;
  unsigned long op;
  ppc_cpu_t dialect_orig = dialect;

  status = (*info->read_memory_func) (memaddr, buffer, 4, info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, memaddr, info);
      return -1;
    }

  if (bigendian)
    insn = bfd_getb32 (buffer);
  else
    insn = bfd_getl32 (buffer);

  /* Get the major opcode of the instruction.  */
  op = PPC_OP (insn);

  /* Find the first match in the opcode table.  We could speed this up
     a bit by doing a binary search on the major opcode.  */
  opcode_end = powerpc_opcodes + powerpc_num_opcodes;
 again:
  for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
    {
      unsigned long table_op;
      const unsigned char *opindex;
      const struct powerpc_operand *operand;
      int invalid;
      int need_comma;
      int need_paren;
      int skip_optional;

      table_op = PPC_OP (opcode->opcode);
      if (op < table_op)
	break;
      if (op > table_op)
	continue;

      if ((insn & opcode->mask) != opcode->opcode
	  || (opcode->flags & dialect) == 0
	  || (opcode->deprecated & dialect_orig) != 0)
	continue;

      /* Make two passes over the operands.  First see if any of them
	 have extraction functions, and, if they do, make sure the
	 instruction is valid.  */
      invalid = 0;
      for (opindex = opcode->operands; *opindex != 0; opindex++)
	{
	  operand = powerpc_operands + *opindex;
	  if (operand->extract)
	    (*operand->extract) (insn, dialect, &invalid);
	}
      if (invalid)
	continue;

      /* The instruction is valid.  */
      if (opcode->operands[0] != 0)
	(*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
      else
	(*info->fprintf_func) (info->stream, "%s", opcode->name);

      /* Now extract and print the operands.  */
      need_comma = 0;
      need_paren = 0;
      skip_optional = -1;
      for (opindex = opcode->operands; *opindex != 0; opindex++)
	{
	  long value;

	  operand = powerpc_operands + *opindex;

	  /* Operands that are marked FAKE are simply ignored.  We
	     already made sure that the extract function considered
	     the instruction to be valid.  */
	  if ((operand->flags & PPC_OPERAND_FAKE) != 0)
	    continue;

	  /* If all of the optional operands have the value zero,
	     then don't print any of them.  */
	  if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
	    {
	      if (skip_optional < 0)
		skip_optional = skip_optional_operands (opindex, insn,
							dialect);
	      if (skip_optional)
		continue;
	    }

	  value = operand_value_powerpc (operand, insn, dialect);

	  if (need_comma)
	    {
	      (*info->fprintf_func) (info->stream, ",");
	      need_comma = 0;
	    }

	  /* Print the operand as directed by the flags.  */
	  if ((operand->flags & PPC_OPERAND_GPR) != 0
	      || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
	    (*info->fprintf_func) (info->stream, "r%ld", value);
	  else if ((operand->flags & PPC_OPERAND_FPR) != 0)
	    (*info->fprintf_func) (info->stream, "f%ld", value);
	  else if ((operand->flags & PPC_OPERAND_VR) != 0)
	    (*info->fprintf_func) (info->stream, "v%ld", value);
	  else if ((operand->flags & PPC_OPERAND_VSR) != 0)
	    (*info->fprintf_func) (info->stream, "vs%ld", value);
	  else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
	    (*info->print_address_func) (memaddr + value, info);
	  else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
	    (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
	  else if ((operand->flags & PPC_OPERAND_FSL) != 0) 
	    (*info->fprintf_func) (info->stream, "fsl%ld", value);
	  else if ((operand->flags & PPC_OPERAND_FCR) != 0)
	    (*info->fprintf_func) (info->stream, "fcr%ld", value);
	  else if ((operand->flags & PPC_OPERAND_UDI) != 0)
	    (*info->fprintf_func) (info->stream, "%ld", value);
	  else if ((operand->flags & PPC_OPERAND_CR) != 0
		   && (dialect & PPC_OPCODE_PPC) != 0)
	    {
	      if (operand->bitm == 7)
		(*info->fprintf_func) (info->stream, "cr%ld", value);
	      else
		{
		  static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
		  int cr;
		  int cc;

		  cr = value >> 2;
		  if (cr != 0)
		    (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
		  cc = value & 3;
		  (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
		}
	    }
	  else
	    (*info->fprintf_func) (info->stream, "%ld", value);

	  if (need_paren)
	    {
	      (*info->fprintf_func) (info->stream, ")");
	      need_paren = 0;
	    }

	  if ((operand->flags & PPC_OPERAND_PARENS) == 0)
	    need_comma = 1;
	  else
	    {
	      (*info->fprintf_func) (info->stream, "(");
	      need_paren = 1;
	    }
	}

      /* We have found and printed an instruction; return.  */
      return 4;
    }

  if ((dialect & PPC_OPCODE_ANY) != 0)
    {
      dialect = ~PPC_OPCODE_ANY;
      goto again;
    }

  /* We could not find a match.  */
  (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);

  return 4;
}

void
print_ppc_disassembler_options (FILE *stream)
{
  unsigned int i, col;

  fprintf (stream, _("\n\
The following PPC specific disassembler options are supported for use with\n\
the -M switch:\n"));

  for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
    {
      col += fprintf (stream, " %s,", ppc_opts[i].opt);
      if (col > 66)
	{
	  fprintf (stream, "\n");
	  col = 0;
	}
    }
  fprintf (stream, " 32, 64\n");
}
Commit	Line	Data
252b5132	1	/* ppc-dis.c -- Disassemble PowerPC instructions
081ba1b3	2	Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
0dc93057	3	2008, 2009, 2010 Free Software Foundation, Inc.
252b5132 RH	4	Written by Ian Lance Taylor, Cygnus Support
252b5132 RH	5
9b201bb5 NC	6	This file is part of the GNU opcodes library.
	7
	8	This library is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 3, or (at your option)
	11	any later version.
	12
	13	It is distributed in the hope that it will be useful, but WITHOUT
	14	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	15	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	16	License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this file; see the file COPYING. If not, write to the
	20	Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
	21	MA 02110-1301, USA. */
252b5132 RH	22
252b5132 RH	23	#include <stdio.h>
252b5132 RH	24	#include "sysdep.h"
252b5132 RH	25	#include "dis-asm.h"
69fe9ce5	26	#include "opintl.h"
252b5132 RH	27	#include "opcode/ppc.h"
	28
	29	/* This file provides several disassembler functions, all of which use
	30	the disassembler interface defined in dis-asm.h. Several functions
	31	are provided because this file handles disassembly for the PowerPC
	32	in both big and little endian mode and also for the POWER (RS/6000)
	33	chip. */
fa452fa6 PB	34	static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
fa452fa6 PB	35	ppc_cpu_t);
252b5132	36
fa452fa6 PB	37	struct dis_private
	38	{
	39	/* Stash the result of parsing disassembler_options here. */
	40	ppc_cpu_t dialect;
	41	};
	42
	43	#define POWERPC_DIALECT(INFO) \
	44	(((struct dis_private *) ((INFO)->private_data))->dialect)
418c1742	45
69fe9ce5 AM	46	struct ppc_mopt {
	47	const char *opt;
	48	ppc_cpu_t cpu;
	49	ppc_cpu_t sticky;
	50	};
	51
	52	struct ppc_mopt ppc_opts[] = {
	53	{ "403", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_403
	54	\| PPC_OPCODE_32),
	55	0 },
	56	{ "405", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_403
	57	\| PPC_OPCODE_405 \| PPC_OPCODE_32),
	58	0 },
	59	{ "440", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_32
	60	\| PPC_OPCODE_440 \| PPC_OPCODE_ISEL \| PPC_OPCODE_RFMCI),
	61	0 },
	62	{ "464", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_32
	63	\| PPC_OPCODE_440 \| PPC_OPCODE_ISEL \| PPC_OPCODE_RFMCI),
	64	0 },
9fe54b1c PB	65	{ "476", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_ISEL
	66	\| PPC_OPCODE_440 \| PPC_OPCODE_476 \| PPC_OPCODE_POWER4
	67	\| PPC_OPCODE_POWER5),
	68	0 },
69fe9ce5 AM	69	{ "601", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_601
	70	\| PPC_OPCODE_32),
	71	0 },
	72	{ "603", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_32),
	73	0 },
	74	{ "604", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_32),
	75	0 },
	76	{ "620", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_64),
	77	0 },
	78	{ "7400", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_ALTIVEC
	79	\| PPC_OPCODE_32),
	80	0 },
	81	{ "7410", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_ALTIVEC
	82	\| PPC_OPCODE_32),
	83	0 },
	84	{ "7450", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_ALTIVEC
	85	\| PPC_OPCODE_32),
	86	0 },
	87	{ "7455", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_ALTIVEC
	88	\| PPC_OPCODE_32),
	89	0 },
	90	{ "750cl", (PPC_OPCODE_PPC \| PPC_OPCODE_PPCPS)
	91	, 0 },
	92	{ "altivec", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC),
	93	PPC_OPCODE_ALTIVEC },
	94	{ "any", 0,
	95	PPC_OPCODE_ANY },
	96	{ "booke", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_32),
	97	0 },
	98	{ "booke32", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_32),
	99	0 },
	100	{ "cell", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_64
	101	\| PPC_OPCODE_POWER4 \| PPC_OPCODE_CELL \| PPC_OPCODE_ALTIVEC),
	102	0 },
	103	{ "com", (PPC_OPCODE_COMMON \| PPC_OPCODE_32),
	104	0 },
	105	{ "e300", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_32
	106	\| PPC_OPCODE_E300),
	107	0 },
	108	{ "e500", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_SPE
	109	\| PPC_OPCODE_ISEL \| PPC_OPCODE_EFS \| PPC_OPCODE_BRLOCK
	110	\| PPC_OPCODE_PMR \| PPC_OPCODE_CACHELCK \| PPC_OPCODE_RFMCI
	111	\| PPC_OPCODE_E500MC),
	112	0 },
	113	{ "e500mc", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_ISEL
	114	\| PPC_OPCODE_PMR \| PPC_OPCODE_CACHELCK \| PPC_OPCODE_RFMCI
	115	\| PPC_OPCODE_E500MC),
	116	0 },
0dc93057 AM	117	{ "e500mc64", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_ISEL
	118	\| PPC_OPCODE_PMR \| PPC_OPCODE_CACHELCK \| PPC_OPCODE_RFMCI
	119	\| PPC_OPCODE_64 \| PPC_OPCODE_POWER5 \| PPC_OPCODE_POWER6
	120	\| PPC_OPCODE_POWER7),
	121	0 },
69fe9ce5 AM	122	{ "e500x2", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_SPE
	123	\| PPC_OPCODE_ISEL \| PPC_OPCODE_EFS \| PPC_OPCODE_BRLOCK
	124	\| PPC_OPCODE_PMR \| PPC_OPCODE_CACHELCK \| PPC_OPCODE_RFMCI
	125	\| PPC_OPCODE_E500MC),
	126	0 },
	127	{ "efs", (PPC_OPCODE_PPC \| PPC_OPCODE_EFS),
	128	0 },
	129	{ "power4", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_64
	130	\| PPC_OPCODE_POWER4),
	131	0 },
	132	{ "power5", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_64
	133	\| PPC_OPCODE_POWER4 \| PPC_OPCODE_POWER5),
	134	0 },
	135	{ "power6", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_64
	136	\| PPC_OPCODE_POWER4 \| PPC_OPCODE_POWER5 \| PPC_OPCODE_POWER6
	137	\| PPC_OPCODE_ALTIVEC),
	138	0 },
	139	{ "power7", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_ISEL
	140	\| PPC_OPCODE_64 \| PPC_OPCODE_POWER4 \| PPC_OPCODE_POWER5
	141	\| PPC_OPCODE_POWER6 \| PPC_OPCODE_POWER7 \| PPC_OPCODE_ALTIVEC
	142	\| PPC_OPCODE_VSX),
	143	0 },
	144	{ "ppc", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_32),
	145	0 },
	146	{ "ppc32", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_32),
	147	0 },
	148	{ "ppc64", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_64),
	149	0 },
	150	{ "ppc64bridge", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_64_BRIDGE
	151	\| PPC_OPCODE_64),
	152	0 },
634b50f2	153	{ "a2", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_ISEL
e0d602ec	154	\| PPC_OPCODE_POWER4 \| PPC_OPCODE_POWER5 \| PPC_OPCODE_CACHELCK
634b50f2	155	\| PPC_OPCODE_64 \| PPC_OPCODE_A2),
e0d602ec	156	0 },
69fe9ce5 AM	157	{ "ppcps", (PPC_OPCODE_PPC \| PPC_OPCODE_PPCPS),
	158	0 },
	159	{ "pwr", (PPC_OPCODE_POWER \| PPC_OPCODE_32),
	160	0 },
	161	{ "pwr2", (PPC_OPCODE_POWER \| PPC_OPCODE_POWER2 \| PPC_OPCODE_32),
	162	0 },
	163	{ "pwrx", (PPC_OPCODE_POWER \| PPC_OPCODE_POWER2 \| PPC_OPCODE_32),
	164	0 },
	165	{ "spe", (PPC_OPCODE_PPC \| PPC_OPCODE_EFS),
	166	PPC_OPCODE_SPE },
	167	{ "vsx", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC),
	168	PPC_OPCODE_VSX },
	169	};
	170
	171	/* Handle -m and -M options that set cpu type, and .machine arg. */
	172
	173	ppc_cpu_t
	174	ppc_parse_cpu (ppc_cpu_t ppc_cpu, const char *arg)
	175	{
	176	/* Sticky bits. */
	177	ppc_cpu_t retain_flags = ppc_cpu & (PPC_OPCODE_ALTIVEC \| PPC_OPCODE_VSX
	178	\| PPC_OPCODE_SPE \| PPC_OPCODE_ANY);
	179	unsigned int i;
	180
	181	for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
	182	if (strcmp (ppc_opts[i].opt, arg) == 0)
	183	{
	184	if (ppc_opts[i].sticky)
	185	{
	186	retain_flags \|= ppc_opts[i].sticky;
	187	if ((ppc_cpu & ~(PPC_OPCODE_ALTIVEC \| PPC_OPCODE_VSX
	188	\| PPC_OPCODE_SPE \| PPC_OPCODE_ANY)) != 0)
	189	break;
	190	}
	191	ppc_cpu = ppc_opts[i].cpu;
	192	break;
	193	}
	194	if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0]))
	195	return 0;
	196
	197	ppc_cpu \|= retain_flags;
	198	return ppc_cpu;
	199	}
	200
	201	/* Determine which set of machines to disassemble for. */
418c1742	202
661bd698	203	static int
fa452fa6	204	powerpc_init_dialect (struct disassemble_info *info)
418c1742	205	{
69fe9ce5 AM	206	ppc_cpu_t dialect = 0;
69fe9ce5 AM	207	char *arg;
fa452fa6 PB	208	struct dis_private priv = calloc (sizeof (priv), 1);
	209
	210	if (priv == NULL)
	211	return FALSE;
418c1742	212
69fe9ce5 AM	213	arg = info->disassembler_options;
	214	while (arg != NULL)
	215	{
	216	ppc_cpu_t new_cpu = 0;
	217	char *end = strchr (arg, ',');
9b4e5766	218
69fe9ce5 AM	219	if (end != NULL)
69fe9ce5 AM	220	*end = 0;
9b4e5766	221
69fe9ce5 AM	222	if ((new_cpu = ppc_parse_cpu (dialect, arg)) != 0)
	223	dialect = new_cpu;
	224	else if (strcmp (arg, "32") == 0)
	225	{
	226	dialect &= ~PPC_OPCODE_64;
	227	dialect \|= PPC_OPCODE_32;
	228	}
	229	else if (strcmp (arg, "64") == 0)
	230	{
	231	dialect \|= PPC_OPCODE_64;
	232	dialect &= ~PPC_OPCODE_32;
	233	}
	234	else
	235	fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg);
9622b051	236
69fe9ce5 AM	237	if (end != NULL)
	238	*end++ = ',';
	239	arg = end;
	240	}
661bd698	241
70dc4e32	242	if ((dialect & ~(PPC_OPCODE_32 \| PPC_OPCODE_64)) == 0)
802a735e	243	{
70dc4e32 PB	244	if (info->mach == bfd_mach_ppc64)
	245	dialect \|= PPC_OPCODE_64;
	246	else
	247	dialect \|= PPC_OPCODE_32;
69fe9ce5 AM	248	/* Choose a reasonable default. */
	249	dialect \|= (PPC_OPCODE_PPC \| PPC_OPCODE_COMMON \| PPC_OPCODE_CLASSIC
	250	\| PPC_OPCODE_601 \| PPC_OPCODE_ALTIVEC);
802a735e AM	251	}
802a735e AM	252
fa452fa6 PB	253	info->private_data = priv;
	254	POWERPC_DIALECT(info) = dialect;
	255
	256	return TRUE;
418c1742 MG	257	}
	258
	259	/* Print a big endian PowerPC instruction. */
252b5132 RH	260
252b5132 RH	261	int
823bbe9d	262	print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
252b5132	263	{
fa452fa6 PB	264	if (info->private_data == NULL && !powerpc_init_dialect (info))
	265	return -1;
	266	return print_insn_powerpc (memaddr, info, 1, POWERPC_DIALECT(info));
252b5132 RH	267	}
252b5132 RH	268
418c1742	269	/* Print a little endian PowerPC instruction. */
252b5132 RH	270
252b5132 RH	271	int
823bbe9d	272	print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
252b5132	273	{
fa452fa6 PB	274	if (info->private_data == NULL && !powerpc_init_dialect (info))
	275	return -1;
	276	return print_insn_powerpc (memaddr, info, 0, POWERPC_DIALECT(info));
252b5132 RH	277	}
	278
	279	/* Print a POWER (RS/6000) instruction. */
	280
	281	int
823bbe9d	282	print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
252b5132 RH	283	{
	284	return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
	285	}
	286
ea192fa3 PB	287	/* Extract the operand value from the PowerPC or POWER instruction. */
	288
	289	static long
	290	operand_value_powerpc (const struct powerpc_operand *operand,
fa452fa6	291	unsigned long insn, ppc_cpu_t dialect)
ea192fa3 PB	292	{
	293	long value;
	294	int invalid;
	295	/* Extract the value from the instruction. */
	296	if (operand->extract)
	297	value = (*operand->extract) (insn, dialect, &invalid);
	298	else
	299	{
	300	value = (insn >> operand->shift) & operand->bitm;
	301	if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
	302	{
	303	/* BITM is always some number of zeros followed by some
	304	number of ones, followed by some numer of zeros. */
	305	unsigned long top = operand->bitm;
	306	/* top & -top gives the rightmost 1 bit, so this
	307	fills in any trailing zeros. */
	308	top \|= (top & -top) - 1;
	309	top &= ~(top >> 1);
	310	value = (value ^ top) - top;
	311	}
	312	}
	313
	314	return value;
	315	}
	316
	317	/* Determine whether the optional operand(s) should be printed. */
	318
	319	static int
	320	skip_optional_operands (const unsigned char *opindex,
fa452fa6	321	unsigned long insn, ppc_cpu_t dialect)
ea192fa3 PB	322	{
	323	const struct powerpc_operand *operand;
	324
	325	for (; *opindex != 0; opindex++)
	326	{
	327	operand = &powerpc_operands[*opindex];
	328	if ((operand->flags & PPC_OPERAND_NEXT) != 0
	329	\|\| ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
	330	&& operand_value_powerpc (operand, insn, dialect) != 0))
	331	return 0;
	332	}
	333
	334	return 1;
	335	}
	336
252b5132 RH	337	/* Print a PowerPC or POWER instruction. */
	338
	339	static int
823bbe9d AM	340	print_insn_powerpc (bfd_vma memaddr,
	341	struct disassemble_info *info,
	342	int bigendian,
fa452fa6	343	ppc_cpu_t dialect)
252b5132 RH	344	{
	345	bfd_byte buffer[4];
	346	int status;
	347	unsigned long insn;
	348	const struct powerpc_opcode *opcode;
	349	const struct powerpc_opcode *opcode_end;
	350	unsigned long op;
70dc4e32	351	ppc_cpu_t dialect_orig = dialect;
252b5132 RH	352
	353	status = (*info->read_memory_func) (memaddr, buffer, 4, info);
	354	if (status != 0)
	355	{
	356	(*info->memory_error_func) (status, memaddr, info);
	357	return -1;
	358	}
	359
	360	if (bigendian)
	361	insn = bfd_getb32 (buffer);
	362	else
	363	insn = bfd_getl32 (buffer);
	364
	365	/* Get the major opcode of the instruction. */
	366	op = PPC_OP (insn);
	367
	368	/* Find the first match in the opcode table. We could speed this up
	369	a bit by doing a binary search on the major opcode. */
	370	opcode_end = powerpc_opcodes + powerpc_num_opcodes;
661bd698	371	again:
252b5132 RH	372	for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
	373	{
	374	unsigned long table_op;
	375	const unsigned char *opindex;
	376	const struct powerpc_operand *operand;
	377	int invalid;
	378	int need_comma;
	379	int need_paren;
ea192fa3	380	int skip_optional;
252b5132 RH	381
	382	table_op = PPC_OP (opcode->opcode);
	383	if (op < table_op)
	384	break;
	385	if (op > table_op)
	386	continue;
	387
	388	if ((insn & opcode->mask) != opcode->opcode
21169fcf	389	\|\| (opcode->flags & dialect) == 0
70dc4e32	390	\|\| (opcode->deprecated & dialect_orig) != 0)
252b5132 RH	391	continue;
	392
	393	/* Make two passes over the operands. First see if any of them
	394	have extraction functions, and, if they do, make sure the
	395	instruction is valid. */
	396	invalid = 0;
	397	for (opindex = opcode->operands; *opindex != 0; opindex++)
	398	{
	399	operand = powerpc_operands + *opindex;
	400	if (operand->extract)
802a735e	401	(*operand->extract) (insn, dialect, &invalid);
252b5132 RH	402	}
	403	if (invalid)
	404	continue;
	405
	406	/* The instruction is valid. */
252b5132	407	if (opcode->operands[0] != 0)
fdd12ef3 AM	408	(*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
	409	else
	410	(*info->fprintf_func) (info->stream, "%s", opcode->name);
252b5132 RH	411
	412	/* Now extract and print the operands. */
	413	need_comma = 0;
	414	need_paren = 0;
ea192fa3	415	skip_optional = -1;
252b5132 RH	416	for (opindex = opcode->operands; *opindex != 0; opindex++)
	417	{
	418	long value;
	419
	420	operand = powerpc_operands + *opindex;
	421
	422	/* Operands that are marked FAKE are simply ignored. We
	423	already made sure that the extract function considered
	424	the instruction to be valid. */
	425	if ((operand->flags & PPC_OPERAND_FAKE) != 0)
	426	continue;
	427
ea192fa3 PB	428	/* If all of the optional operands have the value zero,
ea192fa3 PB	429	then don't print any of them. */
65b650b4 AM	430	if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
	431	{
	432	if (skip_optional < 0)
	433	skip_optional = skip_optional_operands (opindex, insn,
	434	dialect);
	435	if (skip_optional)
	436	continue;
	437	}
252b5132	438
ea192fa3 PB	439	value = operand_value_powerpc (operand, insn, dialect);
ea192fa3 PB	440
252b5132 RH	441	if (need_comma)
	442	{
	443	(*info->fprintf_func) (info->stream, ",");
	444	need_comma = 0;
	445	}
	446
	447	/* Print the operand as directed by the flags. */
fdd12ef3 AM	448	if ((operand->flags & PPC_OPERAND_GPR) != 0
fdd12ef3 AM	449	\|\| ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
252b5132 RH	450	(*info->fprintf_func) (info->stream, "r%ld", value);
	451	else if ((operand->flags & PPC_OPERAND_FPR) != 0)
	452	(*info->fprintf_func) (info->stream, "f%ld", value);
786e2c0f C	453	else if ((operand->flags & PPC_OPERAND_VR) != 0)
786e2c0f C	454	(*info->fprintf_func) (info->stream, "v%ld", value);
9b4e5766 PB	455	else if ((operand->flags & PPC_OPERAND_VSR) != 0)
9b4e5766 PB	456	(*info->fprintf_func) (info->stream, "vs%ld", value);
252b5132 RH	457	else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
	458	(*info->print_address_func) (memaddr + value, info);
	459	else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
	460	(*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
081ba1b3 AM	461	else if ((operand->flags & PPC_OPERAND_FSL) != 0)
	462	(*info->fprintf_func) (info->stream, "fsl%ld", value);
	463	else if ((operand->flags & PPC_OPERAND_FCR) != 0)
	464	(*info->fprintf_func) (info->stream, "fcr%ld", value);
	465	else if ((operand->flags & PPC_OPERAND_UDI) != 0)
	466	(*info->fprintf_func) (info->stream, "%ld", value);
70dc4e32 PB	467	else if ((operand->flags & PPC_OPERAND_CR) != 0
70dc4e32 PB	468	&& (dialect & PPC_OPCODE_PPC) != 0)
252b5132	469	{
b84bf58a	470	if (operand->bitm == 7)
0fd3a477	471	(*info->fprintf_func) (info->stream, "cr%ld", value);
252b5132 RH	472	else
	473	{
	474	static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
	475	int cr;
	476	int cc;
	477
	478	cr = value >> 2;
	479	if (cr != 0)
8b4fa155	480	(info->fprintf_func) (info->stream, "4cr%d+", cr);
252b5132	481	cc = value & 3;
8b4fa155	482	(*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
252b5132 RH	483	}
252b5132 RH	484	}
70dc4e32 PB	485	else
70dc4e32 PB	486	(*info->fprintf_func) (info->stream, "%ld", value);
252b5132 RH	487
	488	if (need_paren)
	489	{
	490	(*info->fprintf_func) (info->stream, ")");
	491	need_paren = 0;
	492	}
	493
	494	if ((operand->flags & PPC_OPERAND_PARENS) == 0)
	495	need_comma = 1;
	496	else
	497	{
	498	(*info->fprintf_func) (info->stream, "(");
	499	need_paren = 1;
	500	}
	501	}
	502
	503	/* We have found and printed an instruction; return. */
	504	return 4;
	505	}
	506
661bd698 AM	507	if ((dialect & PPC_OPCODE_ANY) != 0)
	508	{
	509	dialect = ~PPC_OPCODE_ANY;
	510	goto again;
	511	}
	512
252b5132 RH	513	/* We could not find a match. */
	514	(*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
	515
	516	return 4;
	517	}
07dd56a9 NC	518
07dd56a9 NC	519	void
823bbe9d	520	print_ppc_disassembler_options (FILE *stream)
07dd56a9	521	{
69fe9ce5 AM	522	unsigned int i, col;
	523
	524	fprintf (stream, _("\n\
07dd56a9	525	The following PPC specific disassembler options are supported for use with\n\
69fe9ce5 AM	526	the -M switch:\n"));
	527
	528	for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
	529	{
	530	col += fprintf (stream, " %s,", ppc_opts[i].opt);
	531	if (col > 66)
	532	{
	533	fprintf (stream, "\n");
	534	col = 0;
	535	}
	536	}
	537	fprintf (stream, " 32, 64\n");
07dd56a9	538	}