[deliverable/binutils-gdb.git] / opcodes / ppc-dis.c

/* ppc-dis.c -- Disassemble PowerPC instructions
   Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
   2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
   Written by Ian Lance Taylor, Cygnus Support

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with this file; see the file COPYING.  If not, write to the
   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */

#include <stdio.h>
#include "sysdep.h"
#include "dis-asm.h"
#include "opintl.h"
#include "opcode/ppc.h"

/* This file provides several disassembler functions, all of which use
   the disassembler interface defined in dis-asm.h.  Several functions
   are provided because this file handles disassembly for the PowerPC
   in both big and little endian mode and also for the POWER (RS/6000)
   chip.  */
static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
			       ppc_cpu_t);

struct dis_private
{
  /* Stash the result of parsing disassembler_options here.  */
  ppc_cpu_t dialect;
};

#define POWERPC_DIALECT(INFO) \
  (((struct dis_private *) ((INFO)->private_data))->dialect)

struct ppc_mopt {
  const char *opt;
  ppc_cpu_t cpu;
  ppc_cpu_t sticky;
};

struct ppc_mopt ppc_opts[] = {
  { "403",     (PPC_OPCODE_PPC | PPC_OPCODE_403),
    0 },
  { "405",     (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405),
    0 },
  { "440",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
		| PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
    0 },
  { "464",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
		| PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
    0 },
  { "476",     (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440
		| PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
    0 },
  { "601",     (PPC_OPCODE_PPC | PPC_OPCODE_601),
    0 },
  { "603",     (PPC_OPCODE_PPC),
    0 },
  { "604",     (PPC_OPCODE_PPC),
    0 },
  { "620",     (PPC_OPCODE_PPC | PPC_OPCODE_64),
    0 },
  { "7400",    (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
    0 },
  { "7410",    (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
    0 },
  { "7450",    (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
    0 },
  { "7455",    (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
    0 },
  { "750cl",   (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS)
    , 0 },
  { "a2",      (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
		| PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
		| PPC_OPCODE_A2),
    0 },
  { "altivec", (PPC_OPCODE_PPC),
    PPC_OPCODE_ALTIVEC },
  { "any",     0,
    PPC_OPCODE_ANY },
  { "booke",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
    0 },
  { "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
    0 },
  { "cell",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
		| PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
    0 },
  { "com",     (PPC_OPCODE_COMMON),
    0 },
  { "e300",    (PPC_OPCODE_PPC | PPC_OPCODE_E300),
    0 },
  { "e500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
		| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
		| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
		| PPC_OPCODE_E500),
    0 },
  { "e500mc",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
		| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
		| PPC_OPCODE_E500MC),
    0 },
  { "e500mc64",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
		| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
		| PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
		| PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
    0 },
  { "e5500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
		| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
		| PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
		| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
		| PPC_OPCODE_POWER7),
    0 },
  { "e6500",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
		| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
		| PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
		| PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4
		| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
    0 },
  { "e500x2",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
		| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
		| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
		| PPC_OPCODE_E500),
    0 },
  { "efs",     (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
    0 },
  { "power4",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
    0 },
  { "power5",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
		| PPC_OPCODE_POWER5),
    0 },
  { "power6",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
		| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
    0 },
  { "power7",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
		| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
		| PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
    0 },
  { "ppc",     (PPC_OPCODE_PPC),
    0 },
  { "ppc32",   (PPC_OPCODE_PPC),
    0 },
  { "ppc64",   (PPC_OPCODE_PPC | PPC_OPCODE_64),
    0 },
  { "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE),
    0 },
  { "ppcps",   (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS),
    0 },
  { "pwr",     (PPC_OPCODE_POWER),
    0 },
  { "pwr2",    (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
    0 },
  { "pwr4",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
    0 },
  { "pwr5",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
		| PPC_OPCODE_POWER5),
    0 },
  { "pwr5x",   (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
		| PPC_OPCODE_POWER5),
    0 },
  { "pwr6",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
		| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
    0 },
  { "pwr7",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
		| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
		| PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
    0 },
  { "pwrx",    (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
    0 },
  { "spe",     (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
    PPC_OPCODE_SPE },
  { "titan",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
		| PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
    0 },
  { "vsx",     (PPC_OPCODE_PPC),
    PPC_OPCODE_VSX },
};

/* Handle -m and -M options that set cpu type, and .machine arg.  */

ppc_cpu_t
ppc_parse_cpu (ppc_cpu_t ppc_cpu, const char *arg)
{
  /* Sticky bits.  */
  ppc_cpu_t retain_flags = ppc_cpu & (PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX
				      | PPC_OPCODE_SPE | PPC_OPCODE_ANY);
  unsigned int i;

  for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
    if (strcmp (ppc_opts[i].opt, arg) == 0)
      {
	if (ppc_opts[i].sticky)
	  {
	    retain_flags |= ppc_opts[i].sticky;
	    if ((ppc_cpu & ~(ppc_cpu_t) (PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX
					 | PPC_OPCODE_SPE | PPC_OPCODE_ANY)) != 0)
	      break;
	  }
	ppc_cpu = ppc_opts[i].cpu;
	break;
      }
  if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0]))
    return 0;

  ppc_cpu |= retain_flags;
  return ppc_cpu;
}

/* Determine which set of machines to disassemble for.  */

static int
powerpc_init_dialect (struct disassemble_info *info)
{
  ppc_cpu_t dialect = 0;
  char *arg;
  struct dis_private *priv = calloc (sizeof (*priv), 1);

  if (priv == NULL)
    return FALSE;

  arg = info->disassembler_options;
  while (arg != NULL)
    {
      ppc_cpu_t new_cpu = 0;
      char *end = strchr (arg, ',');

      if (end != NULL)
	*end = 0;

      if ((new_cpu = ppc_parse_cpu (dialect, arg)) != 0)
	dialect = new_cpu;
      else if (strcmp (arg, "32") == 0)
	dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
      else if (strcmp (arg, "64") == 0)
	dialect |= PPC_OPCODE_64;
      else
	fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg);

      if (end != NULL)
	*end++ = ',';
      arg = end;
    }

  if ((dialect & ~(ppc_cpu_t) PPC_OPCODE_64) == 0)
    {
      if (info->mach == bfd_mach_ppc64)
	dialect |= PPC_OPCODE_64;
      else
	dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
      /* Choose a reasonable default.  */
      dialect |= (PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_601
		  | PPC_OPCODE_ALTIVEC);
    }

  info->private_data = priv;
  POWERPC_DIALECT(info) = dialect;

  return TRUE;
}

/* Print a big endian PowerPC instruction.  */

int
print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
{
  if (info->private_data == NULL && !powerpc_init_dialect (info))
    return -1;
  return print_insn_powerpc (memaddr, info, 1, POWERPC_DIALECT(info));
}

/* Print a little endian PowerPC instruction.  */

int
print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
{
  if (info->private_data == NULL && !powerpc_init_dialect (info))
    return -1;
  return print_insn_powerpc (memaddr, info, 0, POWERPC_DIALECT(info));
}

/* Print a POWER (RS/6000) instruction.  */

int
print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
{
  return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
}

/* Extract the operand value from the PowerPC or POWER instruction.  */

static long
operand_value_powerpc (const struct powerpc_operand *operand,
		       unsigned long insn, ppc_cpu_t dialect)
{
  long value;
  int invalid;
  /* Extract the value from the instruction.  */
  if (operand->extract)
    value = (*operand->extract) (insn, dialect, &invalid);
  else
    {
      value = (insn >> operand->shift) & operand->bitm;
      if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
	{
	  /* BITM is always some number of zeros followed by some
	     number of ones, followed by some numer of zeros.  */
	  unsigned long top = operand->bitm;
	  /* top & -top gives the rightmost 1 bit, so this
	     fills in any trailing zeros.  */
	  top |= (top & -top) - 1;
	  top &= ~(top >> 1);
	  value = (value ^ top) - top;
	}
    }

  return value;
}

/* Determine whether the optional operand(s) should be printed.  */

static int
skip_optional_operands (const unsigned char *opindex,
			unsigned long insn, ppc_cpu_t dialect)
{
  const struct powerpc_operand *operand;

  for (; *opindex != 0; opindex++)
    {
      operand = &powerpc_operands[*opindex];
      if ((operand->flags & PPC_OPERAND_NEXT) != 0
	  || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
	      && operand_value_powerpc (operand, insn, dialect) != 0))
	return 0;
    }

  return 1;
}

/* Print a PowerPC or POWER instruction.  */

static int
print_insn_powerpc (bfd_vma memaddr,
		    struct disassemble_info *info,
		    int bigendian,
		    ppc_cpu_t dialect)
{
  bfd_byte buffer[4];
  int status;
  unsigned long insn;
  const struct powerpc_opcode *opcode;
  const struct powerpc_opcode *opcode_end;
  unsigned long op;

  status = (*info->read_memory_func) (memaddr, buffer, 4, info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, memaddr, info);
      return -1;
    }

  if (bigendian)
    insn = bfd_getb32 (buffer);
  else
    insn = bfd_getl32 (buffer);

  /* Get the major opcode of the instruction.  */
  op = PPC_OP (insn);

  /* Find the first match in the opcode table.  We could speed this up
     a bit by doing a binary search on the major opcode.  */
  opcode_end = powerpc_opcodes + powerpc_num_opcodes;
 again:
  for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
    {
      unsigned long table_op;
      const unsigned char *opindex;
      const struct powerpc_operand *operand;
      int invalid;
      int need_comma;
      int need_paren;
      int skip_optional;

      table_op = PPC_OP (opcode->opcode);
      if (op < table_op)
	break;
      if (op > table_op)
	continue;

      if ((insn & opcode->mask) != opcode->opcode
	  || (opcode->flags & dialect) == 0
	  || (dialect != ~(ppc_cpu_t) PPC_OPCODE_ANY
	      && (opcode->deprecated & dialect) != 0))
	continue;

      /* Make two passes over the operands.  First see if any of them
	 have extraction functions, and, if they do, make sure the
	 instruction is valid.  */
      invalid = 0;
      for (opindex = opcode->operands; *opindex != 0; opindex++)
	{
	  operand = powerpc_operands + *opindex;
	  if (operand->extract)
	    (*operand->extract) (insn, dialect, &invalid);
	}
      if (invalid)
	continue;

      /* The instruction is valid.  */
      if (opcode->operands[0] != 0)
	(*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
      else
	(*info->fprintf_func) (info->stream, "%s", opcode->name);

      /* Now extract and print the operands.  */
      need_comma = 0;
      need_paren = 0;
      skip_optional = -1;
      for (opindex = opcode->operands; *opindex != 0; opindex++)
	{
	  long value;

	  operand = powerpc_operands + *opindex;

	  /* Operands that are marked FAKE are simply ignored.  We
	     already made sure that the extract function considered
	     the instruction to be valid.  */
	  if ((operand->flags & PPC_OPERAND_FAKE) != 0)
	    continue;

	  /* If all of the optional operands have the value zero,
	     then don't print any of them.  */
	  if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
	    {
	      if (skip_optional < 0)
		skip_optional = skip_optional_operands (opindex, insn,
							dialect);
	      if (skip_optional)
		continue;
	    }

	  value = operand_value_powerpc (operand, insn, dialect);

	  if (need_comma)
	    {
	      (*info->fprintf_func) (info->stream, ",");
	      need_comma = 0;
	    }

	  /* Print the operand as directed by the flags.  */
	  if ((operand->flags & PPC_OPERAND_GPR) != 0
	      || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
	    (*info->fprintf_func) (info->stream, "r%ld", value);
	  else if ((operand->flags & PPC_OPERAND_FPR) != 0)
	    (*info->fprintf_func) (info->stream, "f%ld", value);
	  else if ((operand->flags & PPC_OPERAND_VR) != 0)
	    (*info->fprintf_func) (info->stream, "v%ld", value);
	  else if ((operand->flags & PPC_OPERAND_VSR) != 0)
	    (*info->fprintf_func) (info->stream, "vs%ld", value);
	  else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
	    (*info->print_address_func) (memaddr + value, info);
	  else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
	    (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
	  else if ((operand->flags & PPC_OPERAND_FSL) != 0) 
	    (*info->fprintf_func) (info->stream, "fsl%ld", value);
	  else if ((operand->flags & PPC_OPERAND_FCR) != 0)
	    (*info->fprintf_func) (info->stream, "fcr%ld", value);
	  else if ((operand->flags & PPC_OPERAND_UDI) != 0)
	    (*info->fprintf_func) (info->stream, "%ld", value);
	  else if ((operand->flags & PPC_OPERAND_CR) != 0
		   && (dialect & PPC_OPCODE_PPC) != 0)
	    {
	      if (operand->bitm == 7)
		(*info->fprintf_func) (info->stream, "cr%ld", value);
	      else
		{
		  static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
		  int cr;
		  int cc;

		  cr = value >> 2;
		  if (cr != 0)
		    (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
		  cc = value & 3;
		  (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
		}
	    }
	  else
	    (*info->fprintf_func) (info->stream, "%ld", value);

	  if (need_paren)
	    {
	      (*info->fprintf_func) (info->stream, ")");
	      need_paren = 0;
	    }

	  if ((operand->flags & PPC_OPERAND_PARENS) == 0)
	    need_comma = 1;
	  else
	    {
	      (*info->fprintf_func) (info->stream, "(");
	      need_paren = 1;
	    }
	}

      /* We have found and printed an instruction; return.  */
      return 4;
    }

  if ((dialect & PPC_OPCODE_ANY) != 0)
    {
      dialect = ~(ppc_cpu_t) PPC_OPCODE_ANY;
      goto again;
    }

  /* We could not find a match.  */
  (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);

  return 4;
}

void
print_ppc_disassembler_options (FILE *stream)
{
  unsigned int i, col;

  fprintf (stream, _("\n\
The following PPC specific disassembler options are supported for use with\n\
the -M switch:\n"));

  for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
    {
      col += fprintf (stream, " %s,", ppc_opts[i].opt);
      if (col > 66)
	{
	  fprintf (stream, "\n");
	  col = 0;
	}
    }
  fprintf (stream, " 32, 64\n");
}
Commit	Line	Data
252b5132	1	/* ppc-dis.c -- Disassemble PowerPC instructions
081ba1b3	2	Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
aea77599	3	2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
252b5132 RH	4	Written by Ian Lance Taylor, Cygnus Support
252b5132 RH	5
9b201bb5 NC	6	This file is part of the GNU opcodes library.
	7
	8	This library is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 3, or (at your option)
	11	any later version.
	12
	13	It is distributed in the hope that it will be useful, but WITHOUT
	14	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	15	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	16	License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this file; see the file COPYING. If not, write to the
	20	Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
	21	MA 02110-1301, USA. */
252b5132 RH	22
252b5132 RH	23	#include <stdio.h>
252b5132 RH	24	#include "sysdep.h"
252b5132 RH	25	#include "dis-asm.h"
69fe9ce5	26	#include "opintl.h"
252b5132 RH	27	#include "opcode/ppc.h"
	28
	29	/* This file provides several disassembler functions, all of which use
	30	the disassembler interface defined in dis-asm.h. Several functions
	31	are provided because this file handles disassembly for the PowerPC
	32	in both big and little endian mode and also for the POWER (RS/6000)
	33	chip. */
fa452fa6 PB	34	static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
fa452fa6 PB	35	ppc_cpu_t);
252b5132	36
fa452fa6 PB	37	struct dis_private
	38	{
	39	/* Stash the result of parsing disassembler_options here. */
	40	ppc_cpu_t dialect;
	41	};
	42
	43	#define POWERPC_DIALECT(INFO) \
	44	(((struct dis_private *) ((INFO)->private_data))->dialect)
418c1742	45
69fe9ce5 AM	46	struct ppc_mopt {
	47	const char *opt;
	48	ppc_cpu_t cpu;
	49	ppc_cpu_t sticky;
	50	};
	51
	52	struct ppc_mopt ppc_opts[] = {
bdc70b4a	53	{ "403", (PPC_OPCODE_PPC \| PPC_OPCODE_403),
69fe9ce5	54	0 },
bdc70b4a	55	{ "405", (PPC_OPCODE_PPC \| PPC_OPCODE_403 \| PPC_OPCODE_405),
69fe9ce5	56	0 },
bdc70b4a AM	57	{ "440", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_440
bdc70b4a AM	58	\| PPC_OPCODE_ISEL \| PPC_OPCODE_RFMCI),
69fe9ce5	59	0 },
bdc70b4a AM	60	{ "464", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_440
bdc70b4a AM	61	\| PPC_OPCODE_ISEL \| PPC_OPCODE_RFMCI),
69fe9ce5	62	0 },
bdc70b4a AM	63	{ "476", (PPC_OPCODE_PPC \| PPC_OPCODE_ISEL \| PPC_OPCODE_440
bdc70b4a AM	64	\| PPC_OPCODE_476 \| PPC_OPCODE_POWER4 \| PPC_OPCODE_POWER5),
9fe54b1c	65	0 },
bdc70b4a	66	{ "601", (PPC_OPCODE_PPC \| PPC_OPCODE_601),
69fe9ce5	67	0 },
bdc70b4a	68	{ "603", (PPC_OPCODE_PPC),
69fe9ce5	69	0 },
bdc70b4a	70	{ "604", (PPC_OPCODE_PPC),
69fe9ce5	71	0 },
bdc70b4a	72	{ "620", (PPC_OPCODE_PPC \| PPC_OPCODE_64),
69fe9ce5	73	0 },
bdc70b4a	74	{ "7400", (PPC_OPCODE_PPC \| PPC_OPCODE_ALTIVEC),
69fe9ce5	75	0 },
bdc70b4a	76	{ "7410", (PPC_OPCODE_PPC \| PPC_OPCODE_ALTIVEC),
69fe9ce5	77	0 },
bdc70b4a	78	{ "7450", (PPC_OPCODE_PPC \| PPC_OPCODE_ALTIVEC),
69fe9ce5	79	0 },
bdc70b4a	80	{ "7455", (PPC_OPCODE_PPC \| PPC_OPCODE_ALTIVEC),
69fe9ce5 AM	81	0 },
	82	{ "750cl", (PPC_OPCODE_PPC \| PPC_OPCODE_PPCPS)
	83	, 0 },
bdc70b4a AM	84	{ "a2", (PPC_OPCODE_PPC \| PPC_OPCODE_ISEL \| PPC_OPCODE_POWER4
	85	\| PPC_OPCODE_POWER5 \| PPC_OPCODE_CACHELCK \| PPC_OPCODE_64
	86	\| PPC_OPCODE_A2),
cdc51b07	87	0 },
bdc70b4a	88	{ "altivec", (PPC_OPCODE_PPC),
69fe9ce5 AM	89	PPC_OPCODE_ALTIVEC },
	90	{ "any", 0,
	91	PPC_OPCODE_ANY },
bdc70b4a	92	{ "booke", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE),
69fe9ce5	93	0 },
bdc70b4a	94	{ "booke32", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE),
69fe9ce5	95	0 },
bdc70b4a AM	96	{ "cell", (PPC_OPCODE_PPC \| PPC_OPCODE_64 \| PPC_OPCODE_POWER4
bdc70b4a AM	97	\| PPC_OPCODE_CELL \| PPC_OPCODE_ALTIVEC),
69fe9ce5	98	0 },
bdc70b4a	99	{ "com", (PPC_OPCODE_COMMON),
69fe9ce5	100	0 },
bdc70b4a	101	{ "e300", (PPC_OPCODE_PPC \| PPC_OPCODE_E300),
69fe9ce5 AM	102	0 },
	103	{ "e500", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_SPE
	104	\| PPC_OPCODE_ISEL \| PPC_OPCODE_EFS \| PPC_OPCODE_BRLOCK
	105	\| PPC_OPCODE_PMR \| PPC_OPCODE_CACHELCK \| PPC_OPCODE_RFMCI
e01d869a	106	\| PPC_OPCODE_E500),
69fe9ce5 AM	107	0 },
	108	{ "e500mc", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_ISEL
	109	\| PPC_OPCODE_PMR \| PPC_OPCODE_CACHELCK \| PPC_OPCODE_RFMCI
	110	\| PPC_OPCODE_E500MC),
	111	0 },
0dc93057 AM	112	{ "e500mc64", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_ISEL
0dc93057 AM	113	\| PPC_OPCODE_PMR \| PPC_OPCODE_CACHELCK \| PPC_OPCODE_RFMCI
63d0fa4e AM	114	\| PPC_OPCODE_E500MC \| PPC_OPCODE_64 \| PPC_OPCODE_POWER5
63d0fa4e AM	115	\| PPC_OPCODE_POWER6 \| PPC_OPCODE_POWER7),
0dc93057	116	0 },
aea77599 AM	117	{ "e5500", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_ISEL
	118	\| PPC_OPCODE_PMR \| PPC_OPCODE_CACHELCK \| PPC_OPCODE_RFMCI
	119	\| PPC_OPCODE_E500MC \| PPC_OPCODE_64 \| PPC_OPCODE_POWER4
	120	\| PPC_OPCODE_POWER5 \| PPC_OPCODE_POWER6
	121	\| PPC_OPCODE_POWER7),
	122	0 },
	123	{ "e6500", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_ISEL
	124	\| PPC_OPCODE_PMR \| PPC_OPCODE_CACHELCK \| PPC_OPCODE_RFMCI
	125	\| PPC_OPCODE_E500MC \| PPC_OPCODE_64 \| PPC_OPCODE_ALTIVEC
	126	\| PPC_OPCODE_ALTIVEC2 \| PPC_OPCODE_E6500 \| PPC_OPCODE_POWER4
	127	\| PPC_OPCODE_POWER5 \| PPC_OPCODE_POWER6 \| PPC_OPCODE_POWER7),
	128	0 },
69fe9ce5 AM	129	{ "e500x2", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_SPE
	130	\| PPC_OPCODE_ISEL \| PPC_OPCODE_EFS \| PPC_OPCODE_BRLOCK
	131	\| PPC_OPCODE_PMR \| PPC_OPCODE_CACHELCK \| PPC_OPCODE_RFMCI
e01d869a	132	\| PPC_OPCODE_E500),
69fe9ce5 AM	133	0 },
	134	{ "efs", (PPC_OPCODE_PPC \| PPC_OPCODE_EFS),
	135	0 },
bdc70b4a	136	{ "power4", (PPC_OPCODE_PPC \| PPC_OPCODE_64 \| PPC_OPCODE_POWER4),
69fe9ce5	137	0 },
bdc70b4a AM	138	{ "power5", (PPC_OPCODE_PPC \| PPC_OPCODE_64 \| PPC_OPCODE_POWER4
bdc70b4a AM	139	\| PPC_OPCODE_POWER5),
69fe9ce5	140	0 },
bdc70b4a AM	141	{ "power6", (PPC_OPCODE_PPC \| PPC_OPCODE_64 \| PPC_OPCODE_POWER4
bdc70b4a AM	142	\| PPC_OPCODE_POWER5 \| PPC_OPCODE_POWER6 \| PPC_OPCODE_ALTIVEC),
69fe9ce5	143	0 },
bdc70b4a AM	144	{ "power7", (PPC_OPCODE_PPC \| PPC_OPCODE_ISEL \| PPC_OPCODE_64
	145	\| PPC_OPCODE_POWER4 \| PPC_OPCODE_POWER5 \| PPC_OPCODE_POWER6
	146	\| PPC_OPCODE_POWER7 \| PPC_OPCODE_ALTIVEC \| PPC_OPCODE_VSX),
69fe9ce5	147	0 },
bdc70b4a	148	{ "ppc", (PPC_OPCODE_PPC),
69fe9ce5	149	0 },
bdc70b4a	150	{ "ppc32", (PPC_OPCODE_PPC),
69fe9ce5	151	0 },
bdc70b4a	152	{ "ppc64", (PPC_OPCODE_PPC \| PPC_OPCODE_64),
69fe9ce5	153	0 },
bdc70b4a	154	{ "ppc64bridge", (PPC_OPCODE_PPC \| PPC_OPCODE_64_BRIDGE),
69fe9ce5 AM	155	0 },
	156	{ "ppcps", (PPC_OPCODE_PPC \| PPC_OPCODE_PPCPS),
	157	0 },
bdc70b4a	158	{ "pwr", (PPC_OPCODE_POWER),
69fe9ce5	159	0 },
bdc70b4a	160	{ "pwr2", (PPC_OPCODE_POWER \| PPC_OPCODE_POWER2),
cdc51b07	161	0 },
bdc70b4a	162	{ "pwr4", (PPC_OPCODE_PPC \| PPC_OPCODE_64 \| PPC_OPCODE_POWER4),
cdc51b07	163	0 },
bdc70b4a AM	164	{ "pwr5", (PPC_OPCODE_PPC \| PPC_OPCODE_64 \| PPC_OPCODE_POWER4
bdc70b4a AM	165	\| PPC_OPCODE_POWER5),
cdc51b07	166	0 },
bdc70b4a AM	167	{ "pwr5x", (PPC_OPCODE_PPC \| PPC_OPCODE_64 \| PPC_OPCODE_POWER4
bdc70b4a AM	168	\| PPC_OPCODE_POWER5),
cdc51b07	169	0 },
bdc70b4a AM	170	{ "pwr6", (PPC_OPCODE_PPC \| PPC_OPCODE_64 \| PPC_OPCODE_POWER4
bdc70b4a AM	171	\| PPC_OPCODE_POWER5 \| PPC_OPCODE_POWER6 \| PPC_OPCODE_ALTIVEC),
cdc51b07	172	0 },
bdc70b4a AM	173	{ "pwr7", (PPC_OPCODE_PPC \| PPC_OPCODE_ISEL \| PPC_OPCODE_64
	174	\| PPC_OPCODE_POWER4 \| PPC_OPCODE_POWER5 \| PPC_OPCODE_POWER6
	175	\| PPC_OPCODE_POWER7 \| PPC_OPCODE_ALTIVEC \| PPC_OPCODE_VSX),
69fe9ce5	176	0 },
bdc70b4a	177	{ "pwrx", (PPC_OPCODE_POWER \| PPC_OPCODE_POWER2),
69fe9ce5 AM	178	0 },
	179	{ "spe", (PPC_OPCODE_PPC \| PPC_OPCODE_EFS),
	180	PPC_OPCODE_SPE },
bdc70b4a AM	181	{ "titan", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_PMR
bdc70b4a AM	182	\| PPC_OPCODE_RFMCI \| PPC_OPCODE_TITAN),
ce3d2015	183	0 },
bdc70b4a	184	{ "vsx", (PPC_OPCODE_PPC),
69fe9ce5 AM	185	PPC_OPCODE_VSX },
	186	};
	187
	188	/* Handle -m and -M options that set cpu type, and .machine arg. */
	189
	190	ppc_cpu_t
	191	ppc_parse_cpu (ppc_cpu_t ppc_cpu, const char *arg)
	192	{
	193	/* Sticky bits. */
	194	ppc_cpu_t retain_flags = ppc_cpu & (PPC_OPCODE_ALTIVEC \| PPC_OPCODE_VSX
	195	\| PPC_OPCODE_SPE \| PPC_OPCODE_ANY);
	196	unsigned int i;
	197
	198	for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
	199	if (strcmp (ppc_opts[i].opt, arg) == 0)
	200	{
	201	if (ppc_opts[i].sticky)
	202	{
	203	retain_flags \|= ppc_opts[i].sticky;
7102e95e AS	204	if ((ppc_cpu & ~(ppc_cpu_t) (PPC_OPCODE_ALTIVEC \| PPC_OPCODE_VSX
7102e95e AS	205	\| PPC_OPCODE_SPE \| PPC_OPCODE_ANY)) != 0)
69fe9ce5 AM	206	break;
	207	}
	208	ppc_cpu = ppc_opts[i].cpu;
	209	break;
	210	}
	211	if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0]))
	212	return 0;
	213
	214	ppc_cpu \|= retain_flags;
	215	return ppc_cpu;
	216	}
	217
	218	/* Determine which set of machines to disassemble for. */
418c1742	219
661bd698	220	static int
fa452fa6	221	powerpc_init_dialect (struct disassemble_info *info)
418c1742	222	{
69fe9ce5 AM	223	ppc_cpu_t dialect = 0;
69fe9ce5 AM	224	char *arg;
fa452fa6 PB	225	struct dis_private priv = calloc (sizeof (priv), 1);
	226
	227	if (priv == NULL)
	228	return FALSE;
418c1742	229
69fe9ce5 AM	230	arg = info->disassembler_options;
	231	while (arg != NULL)
	232	{
	233	ppc_cpu_t new_cpu = 0;
	234	char *end = strchr (arg, ',');
9b4e5766	235
69fe9ce5 AM	236	if (end != NULL)
69fe9ce5 AM	237	*end = 0;
9b4e5766	238
69fe9ce5 AM	239	if ((new_cpu = ppc_parse_cpu (dialect, arg)) != 0)
	240	dialect = new_cpu;
	241	else if (strcmp (arg, "32") == 0)
7102e95e	242	dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
69fe9ce5	243	else if (strcmp (arg, "64") == 0)
bdc70b4a	244	dialect \|= PPC_OPCODE_64;
69fe9ce5 AM	245	else
69fe9ce5 AM	246	fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg);
9622b051	247
69fe9ce5 AM	248	if (end != NULL)
	249	*end++ = ',';
	250	arg = end;
	251	}
661bd698	252
7102e95e	253	if ((dialect & ~(ppc_cpu_t) PPC_OPCODE_64) == 0)
802a735e	254	{
70dc4e32 PB	255	if (info->mach == bfd_mach_ppc64)
	256	dialect \|= PPC_OPCODE_64;
	257	else
7102e95e	258	dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
69fe9ce5	259	/* Choose a reasonable default. */
bdc70b4a AM	260	dialect \|= (PPC_OPCODE_PPC \| PPC_OPCODE_COMMON \| PPC_OPCODE_601
bdc70b4a AM	261	\| PPC_OPCODE_ALTIVEC);
802a735e AM	262	}
802a735e AM	263
fa452fa6 PB	264	info->private_data = priv;
	265	POWERPC_DIALECT(info) = dialect;
	266
	267	return TRUE;
418c1742 MG	268	}
	269
	270	/* Print a big endian PowerPC instruction. */
252b5132 RH	271
252b5132 RH	272	int
823bbe9d	273	print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
252b5132	274	{
fa452fa6 PB	275	if (info->private_data == NULL && !powerpc_init_dialect (info))
	276	return -1;
	277	return print_insn_powerpc (memaddr, info, 1, POWERPC_DIALECT(info));
252b5132 RH	278	}
252b5132 RH	279
418c1742	280	/* Print a little endian PowerPC instruction. */
252b5132 RH	281
252b5132 RH	282	int
823bbe9d	283	print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
252b5132	284	{
fa452fa6 PB	285	if (info->private_data == NULL && !powerpc_init_dialect (info))
	286	return -1;
	287	return print_insn_powerpc (memaddr, info, 0, POWERPC_DIALECT(info));
252b5132 RH	288	}
	289
	290	/* Print a POWER (RS/6000) instruction. */
	291
	292	int
823bbe9d	293	print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
252b5132 RH	294	{
	295	return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
	296	}
	297
ea192fa3 PB	298	/* Extract the operand value from the PowerPC or POWER instruction. */
	299
	300	static long
	301	operand_value_powerpc (const struct powerpc_operand *operand,
fa452fa6	302	unsigned long insn, ppc_cpu_t dialect)
ea192fa3 PB	303	{
	304	long value;
	305	int invalid;
	306	/* Extract the value from the instruction. */
	307	if (operand->extract)
	308	value = (*operand->extract) (insn, dialect, &invalid);
	309	else
	310	{
	311	value = (insn >> operand->shift) & operand->bitm;
	312	if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
	313	{
	314	/* BITM is always some number of zeros followed by some
	315	number of ones, followed by some numer of zeros. */
	316	unsigned long top = operand->bitm;
	317	/* top & -top gives the rightmost 1 bit, so this
	318	fills in any trailing zeros. */
	319	top \|= (top & -top) - 1;
	320	top &= ~(top >> 1);
	321	value = (value ^ top) - top;
	322	}
	323	}
	324
	325	return value;
	326	}
	327
	328	/* Determine whether the optional operand(s) should be printed. */
	329
	330	static int
	331	skip_optional_operands (const unsigned char *opindex,
fa452fa6	332	unsigned long insn, ppc_cpu_t dialect)
ea192fa3 PB	333	{
	334	const struct powerpc_operand *operand;
	335
	336	for (; *opindex != 0; opindex++)
	337	{
	338	operand = &powerpc_operands[*opindex];
	339	if ((operand->flags & PPC_OPERAND_NEXT) != 0
	340	\|\| ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
	341	&& operand_value_powerpc (operand, insn, dialect) != 0))
	342	return 0;
	343	}
	344
	345	return 1;
	346	}
	347
252b5132 RH	348	/* Print a PowerPC or POWER instruction. */
	349
	350	static int
823bbe9d AM	351	print_insn_powerpc (bfd_vma memaddr,
	352	struct disassemble_info *info,
	353	int bigendian,
fa452fa6	354	ppc_cpu_t dialect)
252b5132 RH	355	{
	356	bfd_byte buffer[4];
	357	int status;
	358	unsigned long insn;
	359	const struct powerpc_opcode *opcode;
	360	const struct powerpc_opcode *opcode_end;
	361	unsigned long op;
	362
	363	status = (*info->read_memory_func) (memaddr, buffer, 4, info);
	364	if (status != 0)
	365	{
	366	(*info->memory_error_func) (status, memaddr, info);
	367	return -1;
	368	}
	369
	370	if (bigendian)
	371	insn = bfd_getb32 (buffer);
	372	else
	373	insn = bfd_getl32 (buffer);
	374
	375	/* Get the major opcode of the instruction. */
	376	op = PPC_OP (insn);
	377
	378	/* Find the first match in the opcode table. We could speed this up
	379	a bit by doing a binary search on the major opcode. */
	380	opcode_end = powerpc_opcodes + powerpc_num_opcodes;
661bd698	381	again:
252b5132 RH	382	for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
	383	{
	384	unsigned long table_op;
	385	const unsigned char *opindex;
	386	const struct powerpc_operand *operand;
	387	int invalid;
	388	int need_comma;
	389	int need_paren;
ea192fa3	390	int skip_optional;
252b5132 RH	391
	392	table_op = PPC_OP (opcode->opcode);
	393	if (op < table_op)
	394	break;
	395	if (op > table_op)
	396	continue;
	397
	398	if ((insn & opcode->mask) != opcode->opcode
21169fcf	399	\|\| (opcode->flags & dialect) == 0
8ebac3aa AM	400	\|\| (dialect != ~(ppc_cpu_t) PPC_OPCODE_ANY
8ebac3aa AM	401	&& (opcode->deprecated & dialect) != 0))
252b5132 RH	402	continue;
	403
	404	/* Make two passes over the operands. First see if any of them
	405	have extraction functions, and, if they do, make sure the
	406	instruction is valid. */
	407	invalid = 0;
	408	for (opindex = opcode->operands; *opindex != 0; opindex++)
	409	{
	410	operand = powerpc_operands + *opindex;
	411	if (operand->extract)
802a735e	412	(*operand->extract) (insn, dialect, &invalid);
252b5132 RH	413	}
	414	if (invalid)
	415	continue;
	416
	417	/* The instruction is valid. */
252b5132	418	if (opcode->operands[0] != 0)
fdd12ef3 AM	419	(*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
	420	else
	421	(*info->fprintf_func) (info->stream, "%s", opcode->name);
252b5132 RH	422
	423	/* Now extract and print the operands. */
	424	need_comma = 0;
	425	need_paren = 0;
ea192fa3	426	skip_optional = -1;
252b5132 RH	427	for (opindex = opcode->operands; *opindex != 0; opindex++)
	428	{
	429	long value;
	430
	431	operand = powerpc_operands + *opindex;
	432
	433	/* Operands that are marked FAKE are simply ignored. We
	434	already made sure that the extract function considered
	435	the instruction to be valid. */
	436	if ((operand->flags & PPC_OPERAND_FAKE) != 0)
	437	continue;
	438
ea192fa3 PB	439	/* If all of the optional operands have the value zero,
ea192fa3 PB	440	then don't print any of them. */
65b650b4 AM	441	if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
	442	{
	443	if (skip_optional < 0)
	444	skip_optional = skip_optional_operands (opindex, insn,
	445	dialect);
	446	if (skip_optional)
	447	continue;
	448	}
252b5132	449
ea192fa3 PB	450	value = operand_value_powerpc (operand, insn, dialect);
ea192fa3 PB	451
252b5132 RH	452	if (need_comma)
	453	{
	454	(*info->fprintf_func) (info->stream, ",");
	455	need_comma = 0;
	456	}
	457
	458	/* Print the operand as directed by the flags. */
fdd12ef3 AM	459	if ((operand->flags & PPC_OPERAND_GPR) != 0
fdd12ef3 AM	460	\|\| ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
252b5132 RH	461	(*info->fprintf_func) (info->stream, "r%ld", value);
	462	else if ((operand->flags & PPC_OPERAND_FPR) != 0)
	463	(*info->fprintf_func) (info->stream, "f%ld", value);
786e2c0f C	464	else if ((operand->flags & PPC_OPERAND_VR) != 0)
786e2c0f C	465	(*info->fprintf_func) (info->stream, "v%ld", value);
9b4e5766 PB	466	else if ((operand->flags & PPC_OPERAND_VSR) != 0)
9b4e5766 PB	467	(*info->fprintf_func) (info->stream, "vs%ld", value);
252b5132 RH	468	else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
	469	(*info->print_address_func) (memaddr + value, info);
	470	else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
	471	(*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
081ba1b3 AM	472	else if ((operand->flags & PPC_OPERAND_FSL) != 0)
	473	(*info->fprintf_func) (info->stream, "fsl%ld", value);
	474	else if ((operand->flags & PPC_OPERAND_FCR) != 0)
	475	(*info->fprintf_func) (info->stream, "fcr%ld", value);
	476	else if ((operand->flags & PPC_OPERAND_UDI) != 0)
	477	(*info->fprintf_func) (info->stream, "%ld", value);
70dc4e32 PB	478	else if ((operand->flags & PPC_OPERAND_CR) != 0
70dc4e32 PB	479	&& (dialect & PPC_OPCODE_PPC) != 0)
252b5132	480	{
b84bf58a	481	if (operand->bitm == 7)
0fd3a477	482	(*info->fprintf_func) (info->stream, "cr%ld", value);
252b5132 RH	483	else
	484	{
	485	static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
	486	int cr;
	487	int cc;
	488
	489	cr = value >> 2;
	490	if (cr != 0)
8b4fa155	491	(info->fprintf_func) (info->stream, "4cr%d+", cr);
252b5132	492	cc = value & 3;
8b4fa155	493	(*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
252b5132 RH	494	}
252b5132 RH	495	}
70dc4e32 PB	496	else
70dc4e32 PB	497	(*info->fprintf_func) (info->stream, "%ld", value);
252b5132 RH	498
	499	if (need_paren)
	500	{
	501	(*info->fprintf_func) (info->stream, ")");
	502	need_paren = 0;
	503	}
	504
	505	if ((operand->flags & PPC_OPERAND_PARENS) == 0)
	506	need_comma = 1;
	507	else
	508	{
	509	(*info->fprintf_func) (info->stream, "(");
	510	need_paren = 1;
	511	}
	512	}
	513
	514	/* We have found and printed an instruction; return. */
	515	return 4;
	516	}
	517
661bd698 AM	518	if ((dialect & PPC_OPCODE_ANY) != 0)
661bd698 AM	519	{
7102e95e	520	dialect = ~(ppc_cpu_t) PPC_OPCODE_ANY;
661bd698 AM	521	goto again;
	522	}
	523
252b5132 RH	524	/* We could not find a match. */
	525	(*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
	526
	527	return 4;
	528	}
07dd56a9 NC	529
07dd56a9 NC	530	void
823bbe9d	531	print_ppc_disassembler_options (FILE *stream)
07dd56a9	532	{
69fe9ce5 AM	533	unsigned int i, col;
	534
	535	fprintf (stream, _("\n\
07dd56a9	536	The following PPC specific disassembler options are supported for use with\n\
69fe9ce5 AM	537	the -M switch:\n"));
	538
	539	for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
	540	{
	541	col += fprintf (stream, " %s,", ppc_opts[i].opt);
	542	if (col > 66)
	543	{
	544	fprintf (stream, "\n");
	545	col = 0;
	546	}
	547	}
	548	fprintf (stream, " 32, 64\n");
07dd56a9	549	}