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* config/tc-i386.c (tc_x86_regname_to_dw2regnum): Use ARRAY_SIZE
[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c
CommitLineData
252b5132 1/* ppc-opc.c -- PowerPC opcode list
112290ab 2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003
060d22b0 3 Free Software Foundation, Inc.
252b5132
RH		 4 Written by Ian Lance Taylor, Cygnus Support
5
112290ab 6 This file is part of GDB, GAS, and the GNU binutils.
252b5132 7
112290ab
NC		 8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
252b5132 12
112290ab
NC		 13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
252b5132 17
112290ab
NC		 18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
252b5132
RH		 22
23#include <stdio.h>
0d8dfecf 24#include "sysdep.h"
252b5132
RH		 25#include "opcode/ppc.h"
26#include "opintl.h"
27
28/* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
33 the .text section.
34
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
37 file. */
38\f
39/* Local insertion and extraction functions. */
40
802a735e
AM		 41static unsigned long insert_bat
42 PARAMS ((unsigned long, long, int, const char **));
43static long extract_bat
44 PARAMS ((unsigned long, int, int *));
45static unsigned long insert_bba
46 PARAMS ((unsigned long, long, int, const char **));
47static long extract_bba
48 PARAMS ((unsigned long, int, int *));
49static unsigned long insert_bd
50 PARAMS ((unsigned long, long, int, const char **));
51static long extract_bd
52 PARAMS ((unsigned long, int, int *));
53static unsigned long insert_bdm
54 PARAMS ((unsigned long, long, int, const char **));
55static long extract_bdm
56 PARAMS ((unsigned long, int, int *));
57static unsigned long insert_bdp
58 PARAMS ((unsigned long, long, int, const char **));
59static long extract_bdp
60 PARAMS ((unsigned long, int, int *));
61static int valid_bo
62 PARAMS ((long, int));
63static unsigned long insert_bo
64 PARAMS ((unsigned long, long, int, const char **));
65static long extract_bo
66 PARAMS ((unsigned long, int, int *));
67static unsigned long insert_boe
68 PARAMS ((unsigned long, long, int, const char **));
69static long extract_boe
70 PARAMS ((unsigned long, int, int *));
adadcc0c
AM		 71static unsigned long insert_dq
72 PARAMS ((unsigned long, long, int, const char **));
73static long extract_dq
74 PARAMS ((unsigned long, int, int *));
802a735e
AM		 75static unsigned long insert_ds
76 PARAMS ((unsigned long, long, int, const char **));
77static long extract_ds
78 PARAMS ((unsigned long, int, int *));
79static unsigned long insert_de
80 PARAMS ((unsigned long, long, int, const char **));
81static long extract_de
82 PARAMS ((unsigned long, int, int *));
83static unsigned long insert_des
84 PARAMS ((unsigned long, long, int, const char **));
85static long extract_des
86 PARAMS ((unsigned long, int, int *));
87static unsigned long insert_li
88 PARAMS ((unsigned long, long, int, const char **));
89static long extract_li
90 PARAMS ((unsigned long, int, int *));
91static unsigned long insert_mbe
92 PARAMS ((unsigned long, long, int, const char **));
93static long extract_mbe
94 PARAMS ((unsigned long, int, int *));
95static unsigned long insert_mb6
96 PARAMS ((unsigned long, long, int, const char **));
97static long extract_mb6
98 PARAMS ((unsigned long, int, int *));
99static unsigned long insert_nb
100 PARAMS ((unsigned long, long, int, const char **));
101static long extract_nb
102 PARAMS ((unsigned long, int, int *));
103static unsigned long insert_nsi
104 PARAMS ((unsigned long, long, int, const char **));
105static long extract_nsi
106 PARAMS ((unsigned long, int, int *));
107static unsigned long insert_ral
108 PARAMS ((unsigned long, long, int, const char **));
109static unsigned long insert_ram
110 PARAMS ((unsigned long, long, int, const char **));
adadcc0c
AM		 111static unsigned long insert_raq
112 PARAMS ((unsigned long, long, int, const char **));
802a735e
AM		 113static unsigned long insert_ras
114 PARAMS ((unsigned long, long, int, const char **));
115static unsigned long insert_rbs
116 PARAMS ((unsigned long, long, int, const char **));
117static long extract_rbs
118 PARAMS ((unsigned long, int, int *));
adadcc0c
AM		 119static unsigned long insert_rsq
120 PARAMS ((unsigned long, long, int, const char **));
121static unsigned long insert_rtq
122 PARAMS ((unsigned long, long, int, const char **));
802a735e
AM		 123static unsigned long insert_sh6
124 PARAMS ((unsigned long, long, int, const char **));
125static long extract_sh6
126 PARAMS ((unsigned long, int, int *));
127static unsigned long insert_spr
128 PARAMS ((unsigned long, long, int, const char **));
129static long extract_spr
130 PARAMS ((unsigned long, int, int *));
131static unsigned long insert_tbr
132 PARAMS ((unsigned long, long, int, const char **));
133static long extract_tbr
134 PARAMS ((unsigned long, int, int *));
23976049
EZ		 135static unsigned long insert_ev2
136 PARAMS ((unsigned long, long, int, const char **));
137static long extract_ev2
138 PARAMS ((unsigned long, int, int *));
139static unsigned long insert_ev4
140 PARAMS ((unsigned long, long, int, const char **));
141static long extract_ev4
142 PARAMS ((unsigned long, int, int *));
143static unsigned long insert_ev8
144 PARAMS ((unsigned long, long, int, const char **));
145static long extract_ev8
146 PARAMS ((unsigned long, int, int *));
252b5132
RH		 147\f
148/* The operands table.
149
150 The fields are bits, shift, insert, extract, flags.
151
152 We used to put parens around the various additions, like the one
153 for BA just below. However, that caused trouble with feeble
154 compilers with a limit on depth of a parenthesized expression, like
155 (reportedly) the compiler in Microsoft Developer Studio 5. So we
156 omit the parens, since the macros are never used in a context where
157 the addition will be ambiguous. */
158
159const struct powerpc_operand powerpc_operands[] =
160{
161 /* The zero index is used to indicate the end of the list of
162 operands. */
163#define UNUSED 0
11b37b7b 164 { 0, 0, 0, 0, 0 },
252b5132
RH		 165
166 /* The BA field in an XL form instruction. */
167#define BA UNUSED + 1
168#define BA_MASK (0x1f << 16)
11b37b7b 169 { 5, 16, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 170
171 /* The BA field in an XL form instruction when it must be the same
172 as the BT field in the same instruction. */
173#define BAT BA + 1
11b37b7b 174 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
252b5132
RH		 175
176 /* The BB field in an XL form instruction. */
177#define BB BAT + 1
178#define BB_MASK (0x1f << 11)
11b37b7b 179 { 5, 11, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 180
181 /* The BB field in an XL form instruction when it must be the same
182 as the BA field in the same instruction. */
183#define BBA BB + 1
11b37b7b 184 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
252b5132
RH		 185
186 /* The BD field in a B form instruction. The lower two bits are
187 forced to zero. */
188#define BD BBA + 1
11b37b7b 189 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 190
191 /* The BD field in a B form instruction when absolute addressing is
192 used. */
193#define BDA BD + 1
11b37b7b 194 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 195
196 /* The BD field in a B form instruction when the - modifier is used.
197 This sets the y bit of the BO field appropriately. */
198#define BDM BDA + 1
11b37b7b
AM		 199 { 16, 0, insert_bdm, extract_bdm,
200 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 201
202 /* The BD field in a B form instruction when the - modifier is used
203 and absolute address is used. */
204#define BDMA BDM + 1
11b37b7b
AM		 205 { 16, 0, insert_bdm, extract_bdm,
206 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 207
208 /* The BD field in a B form instruction when the + modifier is used.
209 This sets the y bit of the BO field appropriately. */
210#define BDP BDMA + 1
11b37b7b
AM		 211 { 16, 0, insert_bdp, extract_bdp,
212 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 213
214 /* The BD field in a B form instruction when the + modifier is used
215 and absolute addressing is used. */
216#define BDPA BDP + 1
11b37b7b
AM		 217 { 16, 0, insert_bdp, extract_bdp,
218 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 219
220 /* The BF field in an X or XL form instruction. */
221#define BF BDPA + 1
11b37b7b 222 { 3, 23, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 223
224 /* An optional BF field. This is used for comparison instructions,
225 in which an omitted BF field is taken as zero. */
226#define OBF BF + 1
11b37b7b 227 { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132
RH		 228
229 /* The BFA field in an X or XL form instruction. */
230#define BFA OBF + 1
11b37b7b 231 { 3, 18, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 232
233 /* The BI field in a B form or XL form instruction. */
234#define BI BFA + 1
235#define BI_MASK (0x1f << 16)
11b37b7b 236 { 5, 16, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 237
238 /* The BO field in a B form instruction. Certain values are
239 illegal. */
240#define BO BI + 1
241#define BO_MASK (0x1f << 21)
11b37b7b 242 { 5, 21, insert_bo, extract_bo, 0 },
252b5132
RH		 243
244 /* The BO field in a B form instruction when the + or - modifier is
245 used. This is like the BO field, but it must be even. */
246#define BOE BO + 1
11b37b7b 247 { 5, 21, insert_boe, extract_boe, 0 },
252b5132
RH		 248
249 /* The BT field in an X or XL form instruction. */
250#define BT BOE + 1
11b37b7b 251 { 5, 21, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 252
253 /* The condition register number portion of the BI field in a B form
254 or XL form instruction. This is used for the extended
255 conditional branch mnemonics, which set the lower two bits of the
256 BI field. This field is optional. */
257#define CR BT + 1
11b37b7b 258 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132 259
23976049
EZ		 260 /* The CRB field in an X form instruction. */
261#define CRB CR + 1
262 { 5, 6, 0, 0, 0 },
263
264 /* The CRFD field in an X form instruction. */
265#define CRFD CRB + 1
0ec499f7 266 { 3, 23, 0, 0, PPC_OPERAND_CR },
23976049
EZ		 267
268 /* The CRFS field in an X form instruction. */
269#define CRFS CRFD + 1
0ec499f7 270 { 3, 0, 0, 0, PPC_OPERAND_CR },
23976049 271
418c1742 272 /* The CT field in an X form instruction. */
23976049 273#define CT CRFS + 1
1f613cde 274 { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
418c1742 275
252b5132
RH		 276 /* The D field in a D form instruction. This is a displacement off
277 a register, and implies that the next operand is a register in
278 parentheses. */
418c1742 279#define D CT + 1
11b37b7b 280 { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
252b5132 281
418c1742
MG		 282 /* The DE field in a DE form instruction. This is like D, but is 12
283 bits only. */
284#define DE D + 1
285 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
286
287 /* The DES field in a DES form instruction. This is like DS, but is 14
288 bits only (12 stored.) */
289#define DES DE + 1
290 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
291
adadcc0c
AM		 292 /* The DQ field in a DQ form instruction. This is like D, but the
293 lower four bits are forced to zero. */
294#define DQ DES + 1
295 { 16, 0, insert_dq, extract_dq,
296 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
297
252b5132
RH		 298 /* The DS field in a DS form instruction. This is like D, but the
299 lower two bits are forced to zero. */
adadcc0c 300#define DS DQ + 1
6ba045b1
AM		 301 { 16, 0, insert_ds, extract_ds,
302 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
252b5132
RH		 303
304 /* The E field in a wrteei instruction. */
305#define E DS + 1
11b37b7b 306 { 1, 15, 0, 0, 0 },
252b5132
RH		 307
308 /* The FL1 field in a POWER SC form instruction. */
309#define FL1 E + 1
11b37b7b 310 { 4, 12, 0, 0, 0 },
252b5132
RH		 311
312 /* The FL2 field in a POWER SC form instruction. */
313#define FL2 FL1 + 1
11b37b7b 314 { 3, 2, 0, 0, 0 },
252b5132
RH		 315
316 /* The FLM field in an XFL form instruction. */
317#define FLM FL2 + 1
11b37b7b 318 { 8, 17, 0, 0, 0 },
252b5132
RH		 319
320 /* The FRA field in an X or A form instruction. */
321#define FRA FLM + 1
322#define FRA_MASK (0x1f << 16)
11b37b7b 323 { 5, 16, 0, 0, PPC_OPERAND_FPR },
252b5132
RH		 324
325 /* The FRB field in an X or A form instruction. */
326#define FRB FRA + 1
327#define FRB_MASK (0x1f << 11)
11b37b7b 328 { 5, 11, 0, 0, PPC_OPERAND_FPR },
252b5132
RH		 329
330 /* The FRC field in an A form instruction. */
331#define FRC FRB + 1
332#define FRC_MASK (0x1f << 6)
11b37b7b 333 { 5, 6, 0, 0, PPC_OPERAND_FPR },
252b5132
RH		 334
335 /* The FRS field in an X form instruction or the FRT field in a D, X
336 or A form instruction. */
337#define FRS FRC + 1
338#define FRT FRS
11b37b7b 339 { 5, 21, 0, 0, PPC_OPERAND_FPR },
252b5132
RH		 340
341 /* The FXM field in an XFX instruction. */
342#define FXM FRS + 1
343#define FXM_MASK (0xff << 12)
11b37b7b 344 { 8, 12, 0, 0, 0 },
252b5132
RH		 345
346 /* The L field in a D or X form instruction. */
347#define L FXM + 1
11b37b7b 348 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
252b5132
RH		 349
350 /* The LEV field in a POWER SC form instruction. */
351#define LEV L + 1
11b37b7b 352 { 7, 5, 0, 0, 0 },
252b5132
RH		 353
354 /* The LI field in an I form instruction. The lower two bits are
355 forced to zero. */
356#define LI LEV + 1
11b37b7b 357 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 358
359 /* The LI field in an I form instruction when used as an absolute
360 address. */
361#define LIA LI + 1
11b37b7b 362 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132 363
6ba045b1
AM		 364 /* The LS field in an X (sync) form instruction. */
365#define LS LIA + 1
366 { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
367
252b5132 368 /* The MB field in an M form instruction. */
6ba045b1 369#define MB LS + 1
252b5132 370#define MB_MASK (0x1f << 6)
11b37b7b 371 { 5, 6, 0, 0, 0 },
252b5132
RH		 372
373 /* The ME field in an M form instruction. */
374#define ME MB + 1
375#define ME_MASK (0x1f << 1)
11b37b7b 376 { 5, 1, 0, 0, 0 },
252b5132
RH		 377
378 /* The MB and ME fields in an M form instruction expressed a single
379 operand which is a bitmask indicating which bits to select. This
380 is a two operand form using PPC_OPERAND_NEXT. See the
381 description in opcode/ppc.h for what this means. */
382#define MBE ME + 1
11b37b7b
AM		 383 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
384 { 32, 0, insert_mbe, extract_mbe, 0 },
252b5132
RH		 385
386 /* The MB or ME field in an MD or MDS form instruction. The high
387 bit is wrapped to the low end. */
388#define MB6 MBE + 2
389#define ME6 MB6
390#define MB6_MASK (0x3f << 5)
11b37b7b 391 { 6, 5, insert_mb6, extract_mb6, 0 },
252b5132 392
9fa87a06
MG		 393 /* The MO field in an mbar instruction. */
394#define MO MB6 + 1
395 { 5, 21, 0, 0, 0 },
396
252b5132
RH		 397 /* The NB field in an X form instruction. The value 32 is stored as
398 0. */
9fa87a06 399#define NB MO + 1
11b37b7b 400 { 6, 11, insert_nb, extract_nb, 0 },
252b5132
RH		 401
402 /* The NSI field in a D form instruction. This is the same as the
403 SI field, only negated. */
404#define NSI NB + 1
405 { 16, 0, insert_nsi, extract_nsi,
11b37b7b 406 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
252b5132 407
adadcc0c 408 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
914749f6 409#define RA NSI + 1
252b5132 410#define RA_MASK (0x1f << 16)
11b37b7b 411 { 5, 16, 0, 0, PPC_OPERAND_GPR },
252b5132 412
adadcc0c
AM		 413 /* The RA field in the DQ form lq instruction, which has special
414 value restrictions. */
415#define RAQ RA + 1
416 { 5, 16, insert_raq, 0, PPC_OPERAND_GPR },
417
252b5132
RH		 418 /* The RA field in a D or X form instruction which is an updating
419 load, which means that the RA field may not be zero and may not
420 equal the RT field. */
adadcc0c 421#define RAL RAQ + 1
11b37b7b 422 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
252b5132
RH		 423
424 /* The RA field in an lmw instruction, which has special value
425 restrictions. */
426#define RAM RAL + 1
11b37b7b 427 { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
252b5132
RH		 428
429 /* The RA field in a D or X form instruction which is an updating
430 store or an updating floating point load, which means that the RA
431 field may not be zero. */
432#define RAS RAM + 1
11b37b7b 433 { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
252b5132
RH		 434
435 /* The RB field in an X, XO, M, or MDS form instruction. */
436#define RB RAS + 1
437#define RB_MASK (0x1f << 11)
11b37b7b 438 { 5, 11, 0, 0, PPC_OPERAND_GPR },
252b5132
RH		 439
440 /* The RB field in an X form instruction when it must be the same as
441 the RS field in the instruction. This is used for extended
442 mnemonics like mr. */
443#define RBS RB + 1
11b37b7b 444 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
252b5132
RH		 445
446 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
447 instruction or the RT field in a D, DS, X, XFX or XO form
448 instruction. */
449#define RS RBS + 1
450#define RT RS
451#define RT_MASK (0x1f << 21)
11b37b7b 452 { 5, 21, 0, 0, PPC_OPERAND_GPR },
252b5132 453
adadcc0c
AM		 454 /* The RS field of the DS form stq instruction, which has special
455 value restrictions. */
456#define RSQ RS + 1
457 { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR },
458
459 /* The RT field of the DQ form lq instruction, which has special
460 value restrictions. */
461#define RTQ RSQ + 1
462 { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR },
463
252b5132 464 /* The SH field in an X or M form instruction. */
adadcc0c 465#define SH RTQ + 1
252b5132 466#define SH_MASK (0x1f << 11)
11b37b7b 467 { 5, 11, 0, 0, 0 },
252b5132
RH		 468
469 /* The SH field in an MD form instruction. This is split. */
470#define SH6 SH + 1
471#define SH6_MASK ((0x1f << 11) | (1 << 1))
11b37b7b 472 { 6, 1, insert_sh6, extract_sh6, 0 },
252b5132
RH		 473
474 /* The SI field in a D form instruction. */
475#define SI SH6 + 1
11b37b7b 476 { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
252b5132
RH		 477
478 /* The SI field in a D form instruction when we accept a wide range
479 of positive values. */
480#define SISIGNOPT SI + 1
11b37b7b 481 { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
252b5132
RH		 482
483 /* The SPR field in an XFX form instruction. This is flipped--the
484 lower 5 bits are stored in the upper 5 and vice- versa. */
485#define SPR SISIGNOPT + 1
914749f6 486#define PMR SPR
252b5132 487#define SPR_MASK (0x3ff << 11)
11b37b7b 488 { 10, 11, insert_spr, extract_spr, 0 },
252b5132
RH		 489
490 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
491#define SPRBAT SPR + 1
492#define SPRBAT_MASK (0x3 << 17)
11b37b7b 493 { 2, 17, 0, 0, 0 },
252b5132
RH		 494
495 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
496#define SPRG SPRBAT + 1
497#define SPRG_MASK (0x3 << 16)
11b37b7b 498 { 2, 16, 0, 0, 0 },
252b5132
RH		 499
500 /* The SR field in an X form instruction. */
501#define SR SPRG + 1
11b37b7b 502 { 4, 16, 0, 0, 0 },
252b5132 503
f5c120c5
MG		 504 /* The STRM field in an X AltiVec form instruction. */
505#define STRM SR + 1
506#define STRM_MASK (0x3 << 21)
507 { 2, 21, 0, 0, 0 },
508
252b5132 509 /* The SV field in a POWER SC form instruction. */
f5c120c5 510#define SV STRM + 1
11b37b7b 511 { 14, 2, 0, 0, 0 },
252b5132
RH		 512
513 /* The TBR field in an XFX form instruction. This is like the SPR
514 field, but it is optional. */
515#define TBR SV + 1
11b37b7b 516 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
252b5132
RH		 517
518 /* The TO field in a D or X form instruction. */
519#define TO TBR + 1
520#define TO_MASK (0x1f << 21)
11b37b7b 521 { 5, 21, 0, 0, 0 },
252b5132
RH		 522
523 /* The U field in an X form instruction. */
524#define U TO + 1
11b37b7b 525 { 4, 12, 0, 0, 0 },
252b5132
RH		 526
527 /* The UI field in a D form instruction. */
528#define UI U + 1
11b37b7b 529 { 16, 0, 0, 0, 0 },
786e2c0f 530
112290ab 531 /* The VA field in a VA, VX or VXR form instruction. */
786e2c0f
C		 532#define VA UI + 1
533#define VA_MASK (0x1f << 16)
6ba045b1 534 { 5, 16, 0, 0, PPC_OPERAND_VR },
786e2c0f 535
112290ab 536 /* The VB field in a VA, VX or VXR form instruction. */
786e2c0f
C		 537#define VB VA + 1
538#define VB_MASK (0x1f << 11)
6ba045b1 539 { 5, 11, 0, 0, PPC_OPERAND_VR },
786e2c0f 540
112290ab 541 /* The VC field in a VA form instruction. */
786e2c0f
C		 542#define VC VB + 1
543#define VC_MASK (0x1f << 6)
6ba045b1 544 { 5, 6, 0, 0, PPC_OPERAND_VR },
786e2c0f 545
112290ab 546 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
786e2c0f
C		 547#define VD VC + 1
548#define VS VD
549#define VD_MASK (0x1f << 21)
6ba045b1 550 { 5, 21, 0, 0, PPC_OPERAND_VR },
786e2c0f 551
112290ab 552 /* The SIMM field in a VX form instruction. */
786e2c0f 553#define SIMM VD + 1
11b37b7b 554 { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
786e2c0f 555
112290ab 556 /* The UIMM field in a VX form instruction. */
786e2c0f 557#define UIMM SIMM + 1
11b37b7b 558 { 5, 16, 0, 0, 0 },
786e2c0f 559
112290ab 560 /* The SHB field in a VA form instruction. */
786e2c0f 561#define SHB UIMM + 1
11b37b7b 562 { 4, 6, 0, 0, 0 },
ff3a6ee3 563
112290ab 564 /* The other UIMM field in a EVX form instruction. */
23976049
EZ		 565#define EVUIMM SHB + 1
566 { 5, 11, 0, 0, 0 },
567
112290ab 568 /* The other UIMM field in a half word EVX form instruction. */
23976049 569#define EVUIMM_2 EVUIMM + 1
95e172a5 570 { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
23976049 571
112290ab 572 /* The other UIMM field in a word EVX form instruction. */
23976049 573#define EVUIMM_4 EVUIMM_2 + 1
95e172a5 574 { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
23976049 575
112290ab 576 /* The other UIMM field in a double EVX form instruction. */
23976049 577#define EVUIMM_8 EVUIMM_4 + 1
ced05688 578 { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
23976049 579
ff3a6ee3 580 /* The WS field. */
23976049 581#define WS EVUIMM_8 + 1
ff3a6ee3
TR		 582#define WS_MASK (0x7 << 11)
583 { 3, 11, 0, 0, 0 },
584
5ae2e65e
AM		 585 /* The L field in an mtmsrd instruction */
586#define MTMSRD_L WS + 1
587 { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL },
588
252b5132
RH		 589};
590
591/* The functions used to insert and extract complicated operands. */
592
593/* The BA field in an XL form instruction when it must be the same as
594 the BT field in the same instruction. This operand is marked FAKE.
595 The insertion function just copies the BT field into the BA field,
596 and the extraction function just checks that the fields are the
597 same. */
598
599/*ARGSUSED*/
600static unsigned long
802a735e 601insert_bat (insn, value, dialect, errmsg)
252b5132 602 unsigned long insn;
9aaaa291 603 long value ATTRIBUTE_UNUSED;
802a735e 604 int dialect ATTRIBUTE_UNUSED;
9aaaa291 605 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 606{
607 return insn | (((insn >> 21) & 0x1f) << 16);
608}
609
610static long
802a735e 611extract_bat (insn, dialect, invalid)
252b5132 612 unsigned long insn;
802a735e 613 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 614 int *invalid;
615{
616 if (invalid != (int *) NULL
617 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
618 *invalid = 1;
619 return 0;
620}
621
622/* The BB field in an XL form instruction when it must be the same as
623 the BA field in the same instruction. This operand is marked FAKE.
624 The insertion function just copies the BA field into the BB field,
625 and the extraction function just checks that the fields are the
626 same. */
627
628/*ARGSUSED*/
629static unsigned long
802a735e 630insert_bba (insn, value, dialect, errmsg)
252b5132 631 unsigned long insn;
9aaaa291 632 long value ATTRIBUTE_UNUSED;
802a735e 633 int dialect ATTRIBUTE_UNUSED;
9aaaa291 634 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 635{
636 return insn | (((insn >> 16) & 0x1f) << 11);
637}
638
639static long
802a735e 640extract_bba (insn, dialect, invalid)
252b5132 641 unsigned long insn;
802a735e 642 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 643 int *invalid;
644{
645 if (invalid != (int *) NULL
646 && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
647 *invalid = 1;
648 return 0;
649}
650
651/* The BD field in a B form instruction. The lower two bits are
652 forced to zero. */
653
654/*ARGSUSED*/
655static unsigned long
802a735e 656insert_bd (insn, value, dialect, errmsg)
252b5132
RH		 657 unsigned long insn;
658 long value;
802a735e 659 int dialect ATTRIBUTE_UNUSED;
9aaaa291 660 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 661{
662 return insn | (value & 0xfffc);
663}
664
665/*ARGSUSED*/
666static long
802a735e 667extract_bd (insn, dialect, invalid)
252b5132 668 unsigned long insn;
802a735e 669 int dialect ATTRIBUTE_UNUSED;
9aaaa291 670 int *invalid ATTRIBUTE_UNUSED;
252b5132 671{
802a735e 672 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 673}
674
675/* The BD field in a B form instruction when the - modifier is used.
676 This modifier means that the branch is not expected to be taken.
94efba12
AM		 677 For chips built to versions of the architecture prior to version 2
678 (ie. not Power4 compatible), we set the y bit of the BO field to 1
679 if the offset is negative. When extracting, we require that the y
680 bit be 1 and that the offset be positive, since if the y bit is 0
681 we just want to print the normal form of the instruction.
682 Power4 compatible targets use two bits, "a", and "t", instead of
683 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
684 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
685 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
686 for branch on CTR. We only handle the taken/not-taken hint here. */
252b5132
RH		 687
688/*ARGSUSED*/
689static unsigned long
802a735e 690insert_bdm (insn, value, dialect, errmsg)
252b5132
RH		 691 unsigned long insn;
692 long value;
802a735e 693 int dialect;
9aaaa291 694 const char **errmsg ATTRIBUTE_UNUSED;
252b5132 695{
94efba12 696 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 697 {
698 if ((value & 0x8000) != 0)
699 insn |= 1 << 21;
700 }
701 else
702 {
703 if ((insn & (0x14 << 21)) == (0x04 << 21))
704 insn |= 0x02 << 21;
705 else if ((insn & (0x14 << 21)) == (0x10 << 21))
706 insn |= 0x08 << 21;
707 }
252b5132
RH		 708 return insn | (value & 0xfffc);
709}
710
711static long
802a735e 712extract_bdm (insn, dialect, invalid)
252b5132 713 unsigned long insn;
802a735e 714 int dialect;
252b5132
RH		 715 int *invalid;
716{
802a735e
AM		 717 if (invalid != (int *) NULL)
718 {
94efba12 719 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 720 {
721 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
722 *invalid = 1;
723 }
724 else
725 {
726 if ((insn & (0x17 << 21)) != (0x06 << 21)
727 && (insn & (0x1d << 21)) != (0x18 << 21))
728 *invalid = 1;
729 }
730 }
731 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 732}
733
734/* The BD field in a B form instruction when the + modifier is used.
735 This is like BDM, above, except that the branch is expected to be
736 taken. */
737
738/*ARGSUSED*/
739static unsigned long
802a735e 740insert_bdp (insn, value, dialect, errmsg)
252b5132
RH		 741 unsigned long insn;
742 long value;
802a735e 743 int dialect;
9aaaa291 744 const char **errmsg ATTRIBUTE_UNUSED;
252b5132 745{
94efba12 746 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 747 {
748 if ((value & 0x8000) == 0)
749 insn |= 1 << 21;
750 }
751 else
752 {
753 if ((insn & (0x14 << 21)) == (0x04 << 21))
754 insn |= 0x03 << 21;
755 else if ((insn & (0x14 << 21)) == (0x10 << 21))
756 insn |= 0x09 << 21;
757 }
252b5132
RH		 758 return insn | (value & 0xfffc);
759}
760
761static long
802a735e 762extract_bdp (insn, dialect, invalid)
252b5132 763 unsigned long insn;
802a735e 764 int dialect;
252b5132
RH		 765 int *invalid;
766{
802a735e
AM		 767 if (invalid != (int *) NULL)
768 {
94efba12 769 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 770 {
771 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
772 *invalid = 1;
773 }
774 else
775 {
776 if ((insn & (0x17 << 21)) != (0x07 << 21)
777 && (insn & (0x1d << 21)) != (0x19 << 21))
778 *invalid = 1;
779 }
780 }
781 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 782}
783
784/* Check for legal values of a BO field. */
785
786static int
802a735e 787valid_bo (value, dialect)
252b5132 788 long value;
802a735e 789 int dialect;
252b5132 790{
94efba12 791 if ((dialect & PPC_OPCODE_POWER4) == 0)
252b5132 792 {
802a735e
AM		 793 /* Certain encodings have bits that are required to be zero.
794 These are (z must be zero, y may be anything):
795 001zy
796 011zy
797 1z00y
798 1z01y
799 1z1zz
800 */
801 switch (value & 0x14)
802 {
803 default:
804 case 0:
805 return 1;
806 case 0x4:
807 return (value & 0x2) == 0;
808 case 0x10:
809 return (value & 0x8) == 0;
810 case 0x14:
811 return value == 0x14;
812 }
813 }
814 else
815 {
816 /* Certain encodings have bits that are required to be zero.
817 These are (z must be zero, a & t may be anything):
818 0000z
819 0001z
820 0100z
821 0101z
822 001at
823 011at
824 1a00t
825 1a01t
826 1z1zz
827 */
828 if ((value & 0x14) == 0)
829 return (value & 0x1) == 0;
830 else if ((value & 0x14) == 0x14)
831 return value == 0x14;
832 else
833 return 1;
252b5132
RH		 834 }
835}
836
837/* The BO field in a B form instruction. Warn about attempts to set
838 the field to an illegal value. */
839
840static unsigned long
802a735e 841insert_bo (insn, value, dialect, errmsg)
252b5132
RH		 842 unsigned long insn;
843 long value;
802a735e 844 int dialect;
252b5132
RH		 845 const char **errmsg;
846{
847 if (errmsg != (const char **) NULL
802a735e 848 && ! valid_bo (value, dialect))
252b5132
RH		 849 *errmsg = _("invalid conditional option");
850 return insn | ((value & 0x1f) << 21);
851}
852
853static long
802a735e 854extract_bo (insn, dialect, invalid)
252b5132 855 unsigned long insn;
802a735e 856 int dialect;
252b5132
RH		 857 int *invalid;
858{
859 long value;
860
861 value = (insn >> 21) & 0x1f;
862 if (invalid != (int *) NULL
802a735e 863 && ! valid_bo (value, dialect))
252b5132
RH		 864 *invalid = 1;
865 return value;
866}
867
868/* The BO field in a B form instruction when the + or - modifier is
869 used. This is like the BO field, but it must be even. When
870 extracting it, we force it to be even. */
871
872static unsigned long
802a735e 873insert_boe (insn, value, dialect, errmsg)
252b5132
RH		 874 unsigned long insn;
875 long value;
802a735e 876 int dialect;
252b5132
RH		 877 const char **errmsg;
878{
879 if (errmsg != (const char **) NULL)
880 {
802a735e 881 if (! valid_bo (value, dialect))
252b5132
RH		 882 *errmsg = _("invalid conditional option");
883 else if ((value & 1) != 0)
884 *errmsg = _("attempt to set y bit when using + or - modifier");
885 }
886 return insn | ((value & 0x1f) << 21);
887}
888
889static long
802a735e 890extract_boe (insn, dialect, invalid)
252b5132 891 unsigned long insn;
802a735e 892 int dialect;
252b5132
RH		 893 int *invalid;
894{
895 long value;
896
897 value = (insn >> 21) & 0x1f;
898 if (invalid != (int *) NULL
802a735e 899 && ! valid_bo (value, dialect))
252b5132
RH		 900 *invalid = 1;
901 return value & 0x1e;
902}
903
adadcc0c
AM		 904 /* The DQ field in a DQ form instruction. This is like D, but the
905 lower four bits are forced to zero. */
906
907/*ARGSUSED*/
908static unsigned long
909insert_dq (insn, value, dialect, errmsg)
910 unsigned long insn;
911 long value;
912 int dialect ATTRIBUTE_UNUSED;
913 const char ** errmsg ATTRIBUTE_UNUSED;
914{
915 if ((value & 0xf) != 0 && errmsg != NULL)
916 *errmsg = _("offset not a multiple of 16");
917 return insn | (value & 0xfff0);
918}
919
920/*ARGSUSED*/
921static long
922extract_dq (insn, dialect, invalid)
923 unsigned long insn;
924 int dialect ATTRIBUTE_UNUSED;
925 int *invalid ATTRIBUTE_UNUSED;
926{
927 return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
928}
929
23976049
EZ		 930static unsigned long
931insert_ev2 (insn, value, dialect, errmsg)
932 unsigned long insn;
933 long value;
934 int dialect ATTRIBUTE_UNUSED;
935 const char ** errmsg ATTRIBUTE_UNUSED;
936{
937 if ((value & 1) != 0 && errmsg != NULL)
938 *errmsg = _("offset not a multiple of 2");
939 if ((value > 62) != 0 && errmsg != NULL)
940 *errmsg = _("offset greater than 62");
914749f6 941 return insn | ((value & 0x3e) << 10);
23976049
EZ		 942}
943
944static long
945extract_ev2 (insn, dialect, invalid)
946 unsigned long insn;
947 int dialect ATTRIBUTE_UNUSED;
948 int * invalid ATTRIBUTE_UNUSED;
949{
914749f6 950 return (insn >> 10) & 0x3e;
23976049
EZ		 951}
952
953static unsigned long
954insert_ev4 (insn, value, dialect, errmsg)
955 unsigned long insn;
956 long value;
957 int dialect ATTRIBUTE_UNUSED;
958 const char ** errmsg ATTRIBUTE_UNUSED;
959{
960 if ((value & 3) != 0 && errmsg != NULL)
961 *errmsg = _("offset not a multiple of 4");
962 if ((value > 124) != 0 && errmsg != NULL)
963 *errmsg = _("offset greater than 124");
914749f6 964 return insn | ((value & 0x7c) << 9);
23976049
EZ		 965}
966
967static long
968extract_ev4 (insn, dialect, invalid)
969 unsigned long insn;
970 int dialect ATTRIBUTE_UNUSED;
971 int * invalid ATTRIBUTE_UNUSED;
972{
914749f6 973 return (insn >> 9) & 0x7c;
23976049
EZ		 974}
975
976static unsigned long
977insert_ev8 (insn, value, dialect, errmsg)
978 unsigned long insn;
979 long value;
980 int dialect ATTRIBUTE_UNUSED;
981 const char ** errmsg ATTRIBUTE_UNUSED;
982{
983 if ((value & 7) != 0 && errmsg != NULL)
984 *errmsg = _("offset not a multiple of 8");
985 if ((value > 248) != 0 && errmsg != NULL)
986 *errmsg = _("offset greater than 248");
987 return insn | ((value & 0xf8) << 8);
988}
989
990static long
991extract_ev8 (insn, dialect, invalid)
992 unsigned long insn;
993 int dialect ATTRIBUTE_UNUSED;
994 int * invalid ATTRIBUTE_UNUSED;
995{
996 return (insn >> 8) & 0xf8;
997}
998
252b5132
RH		 999/* The DS field in a DS form instruction. This is like D, but the
1000 lower two bits are forced to zero. */
1001
1002/*ARGSUSED*/
1003static unsigned long
802a735e 1004insert_ds (insn, value, dialect, errmsg)
252b5132
RH		 1005 unsigned long insn;
1006 long value;
802a735e 1007 int dialect ATTRIBUTE_UNUSED;
418c1742 1008 const char **errmsg;
252b5132 1009{
6ba045b1
AM		 1010 if ((value & 3) != 0 && errmsg != NULL)
1011 *errmsg = _("offset not a multiple of 4");
252b5132
RH		 1012 return insn | (value & 0xfffc);
1013}
1014
1015/*ARGSUSED*/
1016static long
802a735e 1017extract_ds (insn, dialect, invalid)
252b5132 1018 unsigned long insn;
802a735e 1019 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1020 int *invalid ATTRIBUTE_UNUSED;
252b5132 1021{
802a735e 1022 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 1023}
1024
418c1742
MG		 1025/* The DE field in a DE form instruction. */
1026
1027/*ARGSUSED*/
1028static unsigned long
802a735e 1029insert_de (insn, value, dialect, errmsg)
418c1742
MG		 1030 unsigned long insn;
1031 long value;
802a735e 1032 int dialect ATTRIBUTE_UNUSED;
418c1742
MG		 1033 const char **errmsg;
1034{
1035 if ((value > 2047 || value < -2048) && errmsg != NULL)
1036 *errmsg = _("offset not between -2048 and 2047");
1037 return insn | ((value << 4) & 0xfff0);
1038}
1039
1040/*ARGSUSED*/
1041static long
802a735e 1042extract_de (insn, dialect, invalid)
418c1742 1043 unsigned long insn;
802a735e 1044 int dialect ATTRIBUTE_UNUSED;
418c1742
MG		 1045 int *invalid ATTRIBUTE_UNUSED;
1046{
1047 return (insn & 0xfff0) >> 4;
1048}
1049
1050/* The DES field in a DES form instruction. */
1051
1052/*ARGSUSED*/
1053static unsigned long
802a735e 1054insert_des (insn, value, dialect, errmsg)
418c1742
MG		 1055 unsigned long insn;
1056 long value;
802a735e 1057 int dialect ATTRIBUTE_UNUSED;
418c1742
MG		 1058 const char **errmsg;
1059{
1060 if ((value > 8191 || value < -8192) && errmsg != NULL)
1061 *errmsg = _("offset not between -8192 and 8191");
1062 else if ((value & 3) != 0 && errmsg != NULL)
1063 *errmsg = _("offset not a multiple of 4");
1064 return insn | ((value << 2) & 0xfff0);
1065}
1066
1067/*ARGSUSED*/
1068static long
802a735e 1069extract_des (insn, dialect, invalid)
418c1742 1070 unsigned long insn;
802a735e 1071 int dialect ATTRIBUTE_UNUSED;
418c1742
MG		 1072 int *invalid ATTRIBUTE_UNUSED;
1073{
802a735e 1074 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
418c1742
MG		 1075}
1076
252b5132
RH		 1077/* The LI field in an I form instruction. The lower two bits are
1078 forced to zero. */
1079
1080/*ARGSUSED*/
1081static unsigned long
802a735e 1082insert_li (insn, value, dialect, errmsg)
252b5132
RH		 1083 unsigned long insn;
1084 long value;
802a735e 1085 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1086 const char **errmsg;
1087{
1088 if ((value & 3) != 0 && errmsg != (const char **) NULL)
1089 *errmsg = _("ignoring least significant bits in branch offset");
1090 return insn | (value & 0x3fffffc);
1091}
1092
1093/*ARGSUSED*/
1094static long
802a735e 1095extract_li (insn, dialect, invalid)
252b5132 1096 unsigned long insn;
802a735e 1097 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1098 int *invalid ATTRIBUTE_UNUSED;
252b5132 1099{
802a735e 1100 return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
252b5132
RH		 1101}
1102
1103/* The MB and ME fields in an M form instruction expressed as a single
1104 operand which is itself a bitmask. The extraction function always
1105 marks it as invalid, since we never want to recognize an
1106 instruction which uses a field of this type. */
1107
1108static unsigned long
802a735e 1109insert_mbe (insn, value, dialect, errmsg)
252b5132
RH		 1110 unsigned long insn;
1111 long value;
802a735e 1112 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1113 const char **errmsg;
1114{
1115 unsigned long uval, mask;
1116 int mb, me, mx, count, last;
1117
1118 uval = value;
1119
1120 if (uval == 0)
1121 {
1122 if (errmsg != (const char **) NULL)
1123 *errmsg = _("illegal bitmask");
1124 return insn;
1125 }
1126
1127 mb = 0;
1128 me = 32;
1129 if ((uval & 1) != 0)
1130 last = 1;
1131 else
1132 last = 0;
1133 count = 0;
1134
1135 /* mb: location of last 0->1 transition */
1136 /* me: location of last 1->0 transition */
1137 /* count: # transitions */
1138
3eb9799d 1139 for (mx = 0, mask = (long) 1 << 31; mx < 32; ++mx, mask >>= 1)
252b5132
RH		 1140 {
1141 if ((uval & mask) && !last)
1142 {
1143 ++count;
1144 mb = mx;
1145 last = 1;
1146 }
1147 else if (!(uval & mask) && last)
1148 {
1149 ++count;
1150 me = mx;
1151 last = 0;
1152 }
1153 }
1154 if (me == 0)
1155 me = 32;
1156
1157 if (count != 2 && (count != 0 || ! last))
1158 {
1159 if (errmsg != (const char **) NULL)
1160 *errmsg = _("illegal bitmask");
1161 }
1162
1163 return insn | (mb << 6) | ((me - 1) << 1);
1164}
1165
1166static long
802a735e 1167extract_mbe (insn, dialect, invalid)
252b5132 1168 unsigned long insn;
802a735e 1169 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1170 int *invalid;
1171{
1172 long ret;
1173 int mb, me;
1174 int i;
1175
1176 if (invalid != (int *) NULL)
1177 *invalid = 1;
1178
1179 mb = (insn >> 6) & 0x1f;
1180 me = (insn >> 1) & 0x1f;
1181 if (mb < me + 1)
1182 {
1183 ret = 0;
1184 for (i = mb; i <= me; i++)
1185 ret |= (long) 1 << (31 - i);
1186 }
1187 else if (mb == me + 1)
1188 ret = ~0;
1189 else /* (mb > me + 1) */
1190 {
1191 ret = ~ (long) 0;
1192 for (i = me + 1; i < mb; i++)
1193 ret &= ~ ((long) 1 << (31 - i));
1194 }
1195 return ret;
1196}
1197
1198/* The MB or ME field in an MD or MDS form instruction. The high bit
1199 is wrapped to the low end. */
1200
1201/*ARGSUSED*/
1202static unsigned long
802a735e 1203insert_mb6 (insn, value, dialect, errmsg)
252b5132
RH		 1204 unsigned long insn;
1205 long value;
802a735e 1206 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1207 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1208{
1209 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1210}
1211
1212/*ARGSUSED*/
1213static long
802a735e 1214extract_mb6 (insn, dialect, invalid)
252b5132 1215 unsigned long insn;
802a735e 1216 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1217 int *invalid ATTRIBUTE_UNUSED;
252b5132
RH		 1218{
1219 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1220}
1221
1222/* The NB field in an X form instruction. The value 32 is stored as
1223 0. */
1224
1225static unsigned long
802a735e 1226insert_nb (insn, value, dialect, errmsg)
252b5132
RH		 1227 unsigned long insn;
1228 long value;
802a735e 1229 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1230 const char **errmsg;
1231{
1232 if (value < 0 || value > 32)
1233 *errmsg = _("value out of range");
1234 if (value == 32)
1235 value = 0;
1236 return insn | ((value & 0x1f) << 11);
1237}
1238
1239/*ARGSUSED*/
1240static long
802a735e 1241extract_nb (insn, dialect, invalid)
252b5132 1242 unsigned long insn;
802a735e 1243 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1244 int *invalid ATTRIBUTE_UNUSED;
252b5132
RH		 1245{
1246 long ret;
1247
1248 ret = (insn >> 11) & 0x1f;
1249 if (ret == 0)
1250 ret = 32;
1251 return ret;
1252}
1253
1254/* The NSI field in a D form instruction. This is the same as the SI
1255 field, only negated. The extraction function always marks it as
1256 invalid, since we never want to recognize an instruction which uses
1257 a field of this type. */
1258
1259/*ARGSUSED*/
1260static unsigned long
802a735e 1261insert_nsi (insn, value, dialect, errmsg)
252b5132
RH		 1262 unsigned long insn;
1263 long value;
802a735e 1264 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1265 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1266{
1267 return insn | ((- value) & 0xffff);
1268}
1269
1270static long
802a735e 1271extract_nsi (insn, dialect, invalid)
252b5132 1272 unsigned long insn;
802a735e 1273 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1274 int *invalid;
1275{
1276 if (invalid != (int *) NULL)
1277 *invalid = 1;
802a735e 1278 return - (((insn & 0xffff) ^ 0x8000) - 0x8000);
252b5132
RH		 1279}
1280
1281/* The RA field in a D or X form instruction which is an updating
1282 load, which means that the RA field may not be zero and may not
1283 equal the RT field. */
1284
1285static unsigned long
802a735e 1286insert_ral (insn, value, dialect, errmsg)
252b5132
RH		 1287 unsigned long insn;
1288 long value;
802a735e 1289 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1290 const char **errmsg;
1291{
1292 if (value == 0
1293 || (unsigned long) value == ((insn >> 21) & 0x1f))
1294 *errmsg = "invalid register operand when updating";
1295 return insn | ((value & 0x1f) << 16);
1296}
1297
1298/* The RA field in an lmw instruction, which has special value
1299 restrictions. */
1300
1301static unsigned long
802a735e 1302insert_ram (insn, value, dialect, errmsg)
252b5132
RH		 1303 unsigned long insn;
1304 long value;
802a735e 1305 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1306 const char **errmsg;
1307{
1308 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1309 *errmsg = _("index register in load range");
1310 return insn | ((value & 0x1f) << 16);
1311}
1312
adadcc0c
AM		 1313 /* The RA field in the DQ form lq instruction, which has special
1314 value restrictions. */
1315
1316/*ARGSUSED*/
1317static unsigned long
1318insert_raq (insn, value, dialect, errmsg)
1319 unsigned long insn;
1320 long value;
1321 int dialect ATTRIBUTE_UNUSED;
1322 const char **errmsg;
1323{
1324 long rtvalue = (insn & RT_MASK) >> 21;
1325
1326 if (value == rtvalue && errmsg != NULL)
1327 *errmsg = _("source and target register operands must be different");
1328 return insn | ((value & 0x1f) << 16);
1329}
1330
252b5132
RH		 1331/* The RA field in a D or X form instruction which is an updating
1332 store or an updating floating point load, which means that the RA
1333 field may not be zero. */
1334
1335static unsigned long
802a735e 1336insert_ras (insn, value, dialect, errmsg)
252b5132
RH		 1337 unsigned long insn;
1338 long value;
802a735e 1339 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1340 const char **errmsg;
1341{
1342 if (value == 0)
1343 *errmsg = _("invalid register operand when updating");
1344 return insn | ((value & 0x1f) << 16);
1345}
1346
1347/* The RB field in an X form instruction when it must be the same as
1348 the RS field in the instruction. This is used for extended
1349 mnemonics like mr. This operand is marked FAKE. The insertion
1350 function just copies the BT field into the BA field, and the
1351 extraction function just checks that the fields are the same. */
1352
1353/*ARGSUSED*/
1354static unsigned long
802a735e 1355insert_rbs (insn, value, dialect, errmsg)
252b5132 1356 unsigned long insn;
9aaaa291 1357 long value ATTRIBUTE_UNUSED;
802a735e 1358 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1359 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1360{
1361 return insn | (((insn >> 21) & 0x1f) << 11);
1362}
1363
1364static long
802a735e 1365extract_rbs (insn, dialect, invalid)
252b5132 1366 unsigned long insn;
802a735e 1367 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1368 int *invalid;
1369{
1370 if (invalid != (int *) NULL
1371 && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1372 *invalid = 1;
1373 return 0;
1374}
1375
adadcc0c
AM		 1376 /* The RT field of the DQ form lq instruction, which has special
1377 value restrictions. */
1378
1379/*ARGSUSED*/
1380static unsigned long
1381insert_rtq (insn, value, dialect, errmsg)
1382 unsigned long insn;
1383 long value;
1384 int dialect ATTRIBUTE_UNUSED;
1385 const char **errmsg;
1386{
1387 if ((value & 1) != 0 && errmsg != NULL)
1388 *errmsg = _("target register operand must be even");
1389 return insn | ((value & 0x1f) << 21);
1390}
1391
1392 /* The RS field of the DS form stq instruction, which has special
1393 value restrictions. */
1394
1395/*ARGSUSED*/
1396static unsigned long
1397insert_rsq (insn, value, dialect, errmsg)
1398 unsigned long insn;
1399 long value ATTRIBUTE_UNUSED;
1400 int dialect ATTRIBUTE_UNUSED;
1401 const char **errmsg;
1402{
1403 if ((value & 1) != 0 && errmsg != NULL)
1404 *errmsg = _("source register operand must be even");
1405 return insn | ((value & 0x1f) << 21);
1406}
1407
252b5132
RH		 1408/* The SH field in an MD form instruction. This is split. */
1409
1410/*ARGSUSED*/
1411static unsigned long
802a735e 1412insert_sh6 (insn, value, dialect, errmsg)
252b5132
RH		 1413 unsigned long insn;
1414 long value;
802a735e 1415 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1416 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1417{
1418 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1419}
1420
1421/*ARGSUSED*/
1422static long
802a735e 1423extract_sh6 (insn, dialect, invalid)
252b5132 1424 unsigned long insn;
802a735e 1425 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1426 int *invalid ATTRIBUTE_UNUSED;
252b5132
RH		 1427{
1428 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1429}
1430
1431/* The SPR field in an XFX form instruction. This is flipped--the
1432 lower 5 bits are stored in the upper 5 and vice- versa. */
1433
1434static unsigned long
802a735e 1435insert_spr (insn, value, dialect, errmsg)
252b5132
RH		 1436 unsigned long insn;
1437 long value;
802a735e 1438 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1439 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1440{
1441 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1442}
1443
1444static long
802a735e 1445extract_spr (insn, dialect, invalid)
252b5132 1446 unsigned long insn;
802a735e 1447 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1448 int *invalid ATTRIBUTE_UNUSED;
252b5132
RH		 1449{
1450 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1451}
1452
1453/* The TBR field in an XFX instruction. This is just like SPR, but it
1454 is optional. When TBR is omitted, it must be inserted as 268 (the
1455 magic number of the TB register). These functions treat 0
1456 (indicating an omitted optional operand) as 268. This means that
1457 ``mftb 4,0'' is not handled correctly. This does not matter very
1458 much, since the architecture manual does not define mftb as
1459 accepting any values other than 268 or 269. */
1460
1461#define TB (268)
1462
1463static unsigned long
802a735e 1464insert_tbr (insn, value, dialect, errmsg)
252b5132
RH		 1465 unsigned long insn;
1466 long value;
802a735e 1467 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1468 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1469{
1470 if (value == 0)
1471 value = TB;
1472 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1473}
1474
1475static long
802a735e 1476extract_tbr (insn, dialect, invalid)
252b5132 1477 unsigned long insn;
802a735e 1478 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1479 int *invalid ATTRIBUTE_UNUSED;
252b5132
RH		 1480{
1481 long ret;
1482
1483 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1484 if (ret == TB)
1485 ret = 0;
1486 return ret;
1487}
1488\f
1489/* Macros used to form opcodes. */
1490
1491/* The main opcode. */
1492#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1493#define OP_MASK OP (0x3f)
1494
1495/* The main opcode combined with a trap code in the TO field of a D
1496 form instruction. Used for extended mnemonics for the trap
1497 instructions. */
1498#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1499#define OPTO_MASK (OP_MASK | TO_MASK)
1500
1501/* The main opcode combined with a comparison size bit in the L field
1502 of a D form or X form instruction. Used for extended mnemonics for
1503 the comparison instructions. */
1504#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1505#define OPL_MASK OPL (0x3f,1)
1506
1507/* An A form instruction. */
1508#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1509#define A_MASK A (0x3f, 0x1f, 1)
1510
1511/* An A_MASK with the FRB field fixed. */
1512#define AFRB_MASK (A_MASK | FRB_MASK)
1513
1514/* An A_MASK with the FRC field fixed. */
1515#define AFRC_MASK (A_MASK | FRC_MASK)
1516
1517/* An A_MASK with the FRA and FRC fields fixed. */
1518#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1519
1520/* A B form instruction. */
1521#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1522#define B_MASK B (0x3f, 1, 1)
1523
1524/* A B form instruction setting the BO field. */
1525#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1526#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1527
1528/* A BBO_MASK with the y bit of the BO field removed. This permits
1529 matching a conditional branch regardless of the setting of the y
94efba12 1530 bit. Similarly for the 'at' bits used for power4 branch hints. */
802a735e
AM		 1531#define Y_MASK (((unsigned long) 1) << 21)
1532#define AT1_MASK (((unsigned long) 3) << 21)
1533#define AT2_MASK (((unsigned long) 9) << 21)
1534#define BBOY_MASK (BBO_MASK &~ Y_MASK)
1535#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
252b5132
RH		 1536
1537/* A B form instruction setting the BO field and the condition bits of
1538 the BI field. */
1539#define BBOCB(op, bo, cb, aa, lk) \
1540 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1541#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1542
1543/* A BBOCB_MASK with the y bit of the BO field removed. */
1544#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
802a735e
AM		 1545#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1546#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
252b5132
RH		 1547
1548/* A BBOYCB_MASK in which the BI field is fixed. */
1549#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
802a735e 1550#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
252b5132 1551
23976049
EZ		 1552/* An Context form instruction. */
1553#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1554#define CTX_MASK CTX(0x3f, 0x7)
1555
1556/* An User Context form instruction. */
1557#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1558#define UCTX_MASK UCTX(0x3f, 0x1f)
1559
252b5132
RH		 1560/* The main opcode mask with the RA field clear. */
1561#define DRA_MASK (OP_MASK | RA_MASK)
1562
1563/* A DS form instruction. */
1564#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1565#define DS_MASK DSO (0x3f, 3)
1566
418c1742
MG		 1567/* A DE form instruction. */
1568#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1569#define DE_MASK DEO (0x3e, 0xf)
1570
23976049
EZ		 1571/* An EVSEL form instruction. */
1572#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1573#define EVSEL_MASK EVSEL(0x3f, 0xff)
1574
252b5132
RH		 1575/* An M form instruction. */
1576#define M(op, rc) (OP (op) | ((rc) & 1))
1577#define M_MASK M (0x3f, 1)
1578
1579/* An M form instruction with the ME field specified. */
1580#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1581
1582/* An M_MASK with the MB and ME fields fixed. */
1583#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1584
1585/* An M_MASK with the SH and ME fields fixed. */
1586#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1587
1588/* An MD form instruction. */
1589#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1590#define MD_MASK MD (0x3f, 0x7, 1)
1591
1592/* An MD_MASK with the MB field fixed. */
1593#define MDMB_MASK (MD_MASK | MB6_MASK)
1594
1595/* An MD_MASK with the SH field fixed. */
1596#define MDSH_MASK (MD_MASK | SH6_MASK)
1597
1598/* An MDS form instruction. */
1599#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1600#define MDS_MASK MDS (0x3f, 0xf, 1)
1601
1602/* An MDS_MASK with the MB field fixed. */
1603#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1604
1605/* An SC form instruction. */
1606#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1607#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1608
112290ab 1609/* An VX form instruction. */
786e2c0f
C		 1610#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1611
112290ab 1612/* The mask for an VX form instruction. */
786e2c0f
C		 1613#define VX_MASK VX(0x3f, 0x7ff)
1614
112290ab 1615/* An VA form instruction. */
2613489e 1616#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
786e2c0f 1617
112290ab 1618/* The mask for an VA form instruction. */
2613489e 1619#define VXA_MASK VXA(0x3f, 0x3f)
786e2c0f 1620
112290ab 1621/* An VXR form instruction. */
786e2c0f
C		 1622#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1623
112290ab 1624/* The mask for a VXR form instruction. */
786e2c0f
C		 1625#define VXR_MASK VXR(0x3f, 0x3ff, 1)
1626
252b5132
RH		 1627/* An X form instruction. */
1628#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1629
1630/* An X form instruction with the RC bit specified. */
1631#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1632
1633/* The mask for an X form instruction. */
1634#define X_MASK XRC (0x3f, 0x3ff, 1)
1635
1636/* An X_MASK with the RA field fixed. */
1637#define XRA_MASK (X_MASK | RA_MASK)
1638
1639/* An X_MASK with the RB field fixed. */
1640#define XRB_MASK (X_MASK | RB_MASK)
1641
1642/* An X_MASK with the RT field fixed. */
1643#define XRT_MASK (X_MASK | RT_MASK)
1644
1645/* An X_MASK with the RA and RB fields fixed. */
1646#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1647
112290ab 1648/* An XRARB_MASK, but with the L bit clear. */
5ae2e65e
AM		 1649#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1650
252b5132
RH		 1651/* An X_MASK with the RT and RA fields fixed. */
1652#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1653
98acc1c5
AM		 1654/* An XRTRA_MASK, but with L bit clear. */
1655#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1656
252b5132
RH		 1657/* An X form comparison instruction. */
1658#define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1659
1660/* The mask for an X form comparison instruction. */
1661#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1662
1663/* The mask for an X form comparison instruction with the L field
1664 fixed. */
1665#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1666
1667/* An X form trap instruction with the TO field specified. */
1668#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1669#define XTO_MASK (X_MASK | TO_MASK)
1670
e0c21649
GK		 1671/* An X form tlb instruction with the SH field specified. */
1672#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1673#define XTLB_MASK (X_MASK | SH_MASK)
1674
6ba045b1
AM		 1675/* An X form sync instruction. */
1676#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1677
1678/* An X form sync instruction with everything filled in except the LS field. */
1679#define XSYNC_MASK (0xff9fffff)
1680
f5c120c5
MG		 1681/* An X form AltiVec dss instruction. */
1682#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1683#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1684
252b5132
RH		 1685/* An XFL form instruction. */
1686#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1687#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1688
23976049
EZ		 1689/* An X form isel instruction. */
1690#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1691#define XISEL_MASK XISEL(0x3f, 0x1f)
1692
252b5132
RH		 1693/* An XL form instruction with the LK field set to 0. */
1694#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1695
1696/* An XL form instruction which uses the LK field. */
1697#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1698
1699/* The mask for an XL form instruction. */
1700#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1701
1702/* An XL form instruction which explicitly sets the BO field. */
1703#define XLO(op, bo, xop, lk) \
1704 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1705#define XLO_MASK (XL_MASK | BO_MASK)
1706
1707/* An XL form instruction which explicitly sets the y bit of the BO
1708 field. */
1709#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1710#define XLYLK_MASK (XL_MASK | Y_MASK)
1711
1712/* An XL form instruction which sets the BO field and the condition
1713 bits of the BI field. */
1714#define XLOCB(op, bo, cb, xop, lk) \
1715 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1716#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1717
1718/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1719#define XLBB_MASK (XL_MASK | BB_MASK)
1720#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1721#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1722
1723/* An XL_MASK with the BO and BB fields fixed. */
1724#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1725
1726/* An XL_MASK with the BO, BI and BB fields fixed. */
1727#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1728
1729/* An XO form instruction. */
1730#define XO(op, xop, oe, rc) \
1731 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1732#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1733
1734/* An XO_MASK with the RB field fixed. */
1735#define XORB_MASK (XO_MASK | RB_MASK)
1736
1737/* An XS form instruction. */
1738#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1739#define XS_MASK XS (0x3f, 0x1ff, 1)
1740
1741/* A mask for the FXM version of an XFX form instruction. */
1742#define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11))
1743
1744/* An XFX form instruction with the FXM field filled in. */
1745#define XFXM(op, xop, fxm) \
1746 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1747
1748/* An XFX form instruction with the SPR field filled in. */
1749#define XSPR(op, xop, spr) \
1750 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1751#define XSPR_MASK (X_MASK | SPR_MASK)
1752
1753/* An XFX form instruction with the SPR field filled in except for the
1754 SPRBAT field. */
1755#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1756
1757/* An XFX form instruction with the SPR field filled in except for the
1758 SPRG field. */
1759#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1760
1761/* An X form instruction with everything filled in except the E field. */
1762#define XE_MASK (0xffff7fff)
1763
23976049
EZ		 1764/* An X form user context instruction. */
1765#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1766#define XUC_MASK XUC(0x3f, 0x1f)
1767
252b5132
RH		 1768/* The BO encodings used in extended conditional branch mnemonics. */
1769#define BODNZF (0x0)
1770#define BODNZFP (0x1)
1771#define BODZF (0x2)
1772#define BODZFP (0x3)
252b5132
RH		 1773#define BODNZT (0x8)
1774#define BODNZTP (0x9)
1775#define BODZT (0xa)
1776#define BODZTP (0xb)
802a735e
AM		 1777
1778#define BOF (0x4)
1779#define BOFP (0x5)
94efba12
AM		 1780#define BOFM4 (0x6)
1781#define BOFP4 (0x7)
252b5132
RH		 1782#define BOT (0xc)
1783#define BOTP (0xd)
94efba12
AM		 1784#define BOTM4 (0xe)
1785#define BOTP4 (0xf)
802a735e 1786
252b5132
RH		 1787#define BODNZ (0x10)
1788#define BODNZP (0x11)
1789#define BODZ (0x12)
1790#define BODZP (0x13)
94efba12
AM		 1791#define BODNZM4 (0x18)
1792#define BODNZP4 (0x19)
1793#define BODZM4 (0x1a)
1794#define BODZP4 (0x1b)
802a735e 1795
252b5132
RH		 1796#define BOU (0x14)
1797
1798/* The BI condition bit encodings used in extended conditional branch
1799 mnemonics. */
1800#define CBLT (0)
1801#define CBGT (1)
1802#define CBEQ (2)
1803#define CBSO (3)
1804
1805/* The TO encodings used in extended trap mnemonics. */
1806#define TOLGT (0x1)
1807#define TOLLT (0x2)
1808#define TOEQ (0x4)
1809#define TOLGE (0x5)
1810#define TOLNL (0x5)
1811#define TOLLE (0x6)
1812#define TOLNG (0x6)
1813#define TOGT (0x8)
1814#define TOGE (0xc)
1815#define TONL (0xc)
1816#define TOLT (0x10)
1817#define TOLE (0x14)
1818#define TONG (0x14)
1819#define TONE (0x18)
1820#define TOU (0x1f)
1821\f
1822/* Smaller names for the flags so each entry in the opcodes table will
1823 fit on a single line. */
1824#undef PPC
1825#define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY
1826#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
94efba12
AM		 1827#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1828#define POWER4 PPC_OPCODE_POWER4 | PPCCOM
802a735e
AM		 1829#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
1830#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
252b5132 1831#define PPCONLY PPC_OPCODE_PPC
418c1742 1832#define PPC403 PPC_OPCODE_403
e0c21649 1833#define PPC405 PPC403
252b5132
RH		 1834#define PPC750 PPC
1835#define PPC860 PPC
1cbbfaf9 1836#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC
252b5132
RH		 1837#define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY
1838#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1839#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1840#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
1841#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1842#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
1843#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
1844#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1845#define MFDEC1 PPC_OPCODE_POWER
dde1b132 1846#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
418c1742
MG		 1847#define BOOKE PPC_OPCODE_BOOKE
1848#define BOOKE64 PPC_OPCODE_BOOKE64
23976049
EZ		 1849#define CLASSIC PPC_OPCODE_CLASSIC
1850#define PPCSPE PPC_OPCODE_SPE
1851#define PPCISEL PPC_OPCODE_ISEL
1852#define PPCEFS PPC_OPCODE_EFS
1853#define PPCBRLK PPC_OPCODE_BRLOCK
1854#define PPCPMR PPC_OPCODE_PMR
1855#define PPCCHLK PPC_OPCODE_CACHELCK
dde1b132 1856#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
23976049 1857#define PPCRFMCI PPC_OPCODE_RFMCI
252b5132
RH		 1858\f
1859/* The opcode table.
1860
1861 The format of the opcode table is:
1862
1863 NAME OPCODE MASK FLAGS { OPERANDS }
1864
1865 NAME is the name of the instruction.
1866 OPCODE is the instruction opcode.
1867 MASK is the opcode mask; this is used to tell the disassembler
1868 which bits in the actual opcode must match OPCODE.
1869 FLAGS are flags indicated what processors support the instruction.
1870 OPERANDS is the list of operands.
1871
1872 The disassembler reads the table in order and prints the first
1873 instruction which matches, so this table is sorted to put more
1874 specific instructions before more general instructions. It is also
1875 sorted by major opcode. */
1876
1877const struct powerpc_opcode powerpc_opcodes[] = {
adadcc0c 1878{ "attn", X(0,256), X_MASK, POWER4, { 0 } },
252b5132
RH		 1879{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1880{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1881{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1882{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1883{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1884{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1885{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1886{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1887{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1888{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1889{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1890{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1891{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1892{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1893{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1894
1895{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1896{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1897{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1898{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1899{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1900{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1901{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1902{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1903{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1904{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1905{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1906{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1907{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1908{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1909{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1910{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1911{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1912{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1913{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1914{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1915{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1916{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1917{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1918{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1919{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1920{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1921{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1922{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1923{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1924{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
e0c21649
GK		 1925
1926{ "macchw", XO(4,172,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1927{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1928{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1929{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1930{ "macchws", XO(4,236,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1931{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1932{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1933{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1934{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1935{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1936{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1937{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1938{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1939{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1940{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1941{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1942{ "machhw", XO(4,44,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1943{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1944{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1945{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1946{ "machhws", XO(4,108,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1947{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1948{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1949{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1950{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1951{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1952{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1953{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1954{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1955{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1956{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1957{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1958{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1959{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1960{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1961{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1962{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1963{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1964{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1965{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1966{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1967{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1968{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1969{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1970{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1971{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1972{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1973{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1974{ "mulchw", XRC(4,168,0), X_MASK, PPC405, { RT, RA, RB } },
1975{ "mulchw.", XRC(4,168,1), X_MASK, PPC405, { RT, RA, RB } },
1976{ "mulchwu", XRC(4,136,0), X_MASK, PPC405, { RT, RA, RB } },
1977{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405, { RT, RA, RB } },
1978{ "mulhhw", XRC(4,40,0), X_MASK, PPC405, { RT, RA, RB } },
1979{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405, { RT, RA, RB } },
1980{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405, { RT, RA, RB } },
1981{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405, { RT, RA, RB } },
1982{ "mullhw", XRC(4,424,0), X_MASK, PPC405, { RT, RA, RB } },
1983{ "mullhw.", XRC(4,424,1), X_MASK, PPC405, { RT, RA, RB } },
1984{ "mullhwu", XRC(4,392,0), X_MASK, PPC405, { RT, RA, RB } },
1985{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405, { RT, RA, RB } },
1986{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1987{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1988{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1989{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1990{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1991{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1992{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1993{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1994{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1995{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1996{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1997{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1998{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1999{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405, { RT, RA, RB } },
2000{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405, { RT, RA, RB } },
2001{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405, { RT, RA, RB } },
2002{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405, { RT, RA, RB } },
2003{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405, { RT, RA, RB } },
2004{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405, { RT, RA, RB } },
2005{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405, { RT, RA, RB } },
2006{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405, { RT, RA, RB } },
2007{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405, { RT, RA, RB } },
2008{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } },
2009{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } },
786e2c0f 2010{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
f5c120c5 2011{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
786e2c0f
C		 2012{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
2013{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
2014{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
2015{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
2016{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
2017{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
2018{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
2019{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
2020{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
2021{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
2022{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
2023{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
2024{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
2025{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
2026{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
2027{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
2028{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
2029{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
2030{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
2031{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2032{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2033{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2034{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2035{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2036{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2037{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2038{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2039{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2040{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2041{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2042{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2043{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2044{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2045{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2046{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2047{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2048{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2049{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2050{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2051{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2052{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2053{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2054{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2055{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2056{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2057{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2058{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2059{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2060{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2061{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
2062{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
294b41b3 2063{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
786e2c0f
C		 2064{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
2065{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
2066{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
2067{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
2068{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
2069{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
2070{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
2071{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2072{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2073{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
2074{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
2075{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
2076{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
2077{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
2078{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
2079{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
2080{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2081{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
2082{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
2083{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2084{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2085{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2086{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2087{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2088{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2089{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
d2f75a6f
GK		 2090{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2091{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2092{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
786e2c0f
C		 2093{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2094{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2095{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2096{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2097{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2098{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2099{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2100{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2101{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2102{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2103{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2104{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2105{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2106{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2107{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2108{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2109{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2110{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2111{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2112{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2113{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2114{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2115{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2116{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2117{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2118{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2119{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2120{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2121{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2122{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
2123{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2124{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2125{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2126{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2127{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2128{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
1da5001c 2129{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
786e2c0f
C		 2130{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2131{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2132{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2133{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2134{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2135{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2136{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2137{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2138{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2139{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2140{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2141{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2142{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2143{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2144{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2145{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2146{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2147{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2148{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2149{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2150{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2151{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2152{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2153{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2154{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2155{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2156{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2157{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2158{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2159{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2160{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2161{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2162{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2163{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2164{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2165{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2166{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
252b5132 2167
914749f6
AH		 2168{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2169{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2170{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2171{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2172{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2173{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2174{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2175{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2176{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2177{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2178{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2179{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2180{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2181
2182{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2183
2184{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2185{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
dde1b132 2186{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
914749f6
AH		 2187{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2188{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2189{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2190{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2191{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
dde1b132 2192{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
914749f6
AH		 2193{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2194
2195{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2196{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2197{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2198{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2199{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2200{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2201{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2202{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2203{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2204{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
fe587977
AH		 2205{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2206{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2207{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2208{ "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
23976049
EZ		 2209
2210{ "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2211{ "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2212{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2213{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2214{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
914749f6 2215{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
23976049
EZ		 2216
2217{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2218{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2219{ "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2220{ "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2221{ "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2222{ "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2223{ "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2224{ "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2225{ "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2226{ "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2227{ "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2228{ "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2229{ "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2230{ "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2231{ "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2232{ "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2233{ "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2234{ "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2235{ "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2236{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2237{ "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2238{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2239
2240{ "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2241{ "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2242{ "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2243{ "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2244{ "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2245{ "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2246{ "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2247{ "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2248{ "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2249{ "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2250{ "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2251{ "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2252{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2253{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2254
914749f6
AH		 2255{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2256{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2257{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2258{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2259{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2260{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2261{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
23976049
EZ		 2262{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2263{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2264{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2265{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2266{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2267{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
914749f6
AH		 2268{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2269{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2270{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2271{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2272{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2273{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2274{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2275{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2276{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2277{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2278
2279{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2280{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2281{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2282{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2283{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2284{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2285{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
23976049
EZ		 2286{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2287{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2288{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2289{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2290{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2291{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
914749f6
AH		 2292{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2293{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2294{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2295{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2296{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2297{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2298{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2299{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2300{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2301{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2302
914749f6
AH		 2303{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2304{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2305{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2306{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2307{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2308{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2309{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2310{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2311{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2312{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2313{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2314{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2315{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2316{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2317{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2318{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2319
2320{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2321{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2322{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2323{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2324{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2325{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2326{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2327{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2328{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2329{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2330{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2331{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2332
2333{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2334{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2335{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2336{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2337{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2338{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2339{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2340{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2341{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2342{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2343{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2344{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2345
2346{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2347{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2348{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2349{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2350{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2351{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2352
2353{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2354{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2355{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2356{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2357{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2358{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2359
2360{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2361{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2362{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2363{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2364{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2365{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2366{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2367{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2368
914749f6
AH		 2369{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2370{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2371
914749f6 2372{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
914749f6
AH		 2373{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2374{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2375{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2376
914749f6 2377{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
914749f6
AH		 2378{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2379{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2380{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2381
914749f6
AH		 2382{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2383{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2384{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2385{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2386{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2387{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2388{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2389{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2390
2391{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2392{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2393{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2394{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2395
2396{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2397{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2398{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2399{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2400
2401{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2402{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2403{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2404{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2405
2406{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2407{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2408{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2409{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2410
2411{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2412
2413{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2414{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
23976049 2415
252b5132
RH		 2416{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2417{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2418
2419{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2420{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2421
2422{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2423
418c1742
MG		 2424{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2425{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2426{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2427{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2428
252b5132
RH		 2429{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2430{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
2431{ "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } },
2432{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2433
2434{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2435{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
2436{ "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } },
2437{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2438
2439{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2440{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2441{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2442
2443{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2444{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2445{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2446
2447{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2448{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2449{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } },
2450{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } },
2451{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } },
2452{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } },
2453
2454{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2455{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2456{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } },
2457{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } },
2458{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } },
2459
112290ab
NC		 2460{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2461{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2462{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2463{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2464{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2465{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2466{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2467{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2468{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2469{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2470{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2471{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2472{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2473{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2474{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2475{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2476{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2477{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2478{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2479{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2480{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2481{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2482{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2483{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2484{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2485{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2486{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2487{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
802a735e
AM		 2488{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2489{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2490{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2491{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2492{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2493{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2494{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2495{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2496{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2497{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2498{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2499{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2500{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2501{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2502{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2503{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2504{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2505{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2506{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2507{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2508{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2509{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2510{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2511{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2512{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2513{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2514{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2515{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2516{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2517{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2518{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2519{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2520{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2521{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2522{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2523{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2524{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2525{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2526{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2527{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2528{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2529{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2530{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2531{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2532{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2533{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2534{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2535{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2536{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2537{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2538{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2539{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2540{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2541{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2542{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2543{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2544{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2545{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2546{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2547{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2548{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2549{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2550{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2551{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2552{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2553{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2554{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2555{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2556{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2557{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2558{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2559{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2560{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2561{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2562{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2563{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2564{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2565{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2566{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2567{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2568{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2569{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2570{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2571{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2572{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2573{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2574{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2575{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2576{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2577{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2578{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2579{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2580{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2581{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2582{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2583{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2584{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2585{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2586{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2587{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2588{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2589{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2590{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2591{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2592{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2593{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2594{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2595{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2596{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2597{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2598{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2599{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2600{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2601{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2602{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2603{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2604{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2605{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2606{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2607{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2608{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2609{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2610{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2611{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2612{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2613{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2614{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2615{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2616{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2617{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2618{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2619{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2620{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2621{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2622{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2623{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2624{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2625{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2626{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2627{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2628{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2629{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2630{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2631{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
94efba12
AM		 2632{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2633{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2634{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2635{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2636{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2637{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2638{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2639{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2640{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2641{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2642{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2643{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2644{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2645{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2646{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2647{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2648{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2649{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2650{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2651{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2652{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2653{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2654{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2655{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
802a735e
AM		 2656{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2657{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2658{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2659{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2660{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2661{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2662{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2663{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2664{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2665{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2666{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2667{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2668{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2669{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2670{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2671{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2672{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2673{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2674{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2675{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2676{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2677{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2678{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2679{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2680{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2681{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2682{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2683{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2684{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2685{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2686{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2687{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
94efba12
AM		 2688{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2689{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2690{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2691{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2692{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2693{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2694{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2695{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2696{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2697{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2698{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2699{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2700{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2701{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2702{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2703{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2704{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2705{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2706{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2707{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2708{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2709{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2710{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2711{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
d2f75a6f
GK		 2712{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2713{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
252b5132 2714{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
d2f75a6f
GK		 2715{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2716{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
252b5132 2717{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
d2f75a6f
GK		 2718{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2719{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
252b5132 2720{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
d2f75a6f
GK		 2721{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2722{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
252b5132
RH		 2723{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2724
2725{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
2726{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
2727{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
2728{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2729{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2730
418c1742
MG		 2731{ "b", B(18,0,0), B_MASK, COM, { LI } },
2732{ "bl", B(18,0,1), B_MASK, COM, { LI } },
2733{ "ba", B(18,1,0), B_MASK, COM, { LIA } },
2734{ "bla", B(18,1,1), B_MASK, COM, { LIA } },
252b5132 2735
112290ab 2736{ "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
252b5132
RH		 2737
2738{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2739{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2740{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2741{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2742{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12
AM		 2743{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2744{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2745{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2746{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2747{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12
AM		 2748{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2749{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2750{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2751{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2752{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12
AM		 2753{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2754{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2755{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2756{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2757{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12
AM		 2758{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2759{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2760{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2761{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2762{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2763{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2764{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2765{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2766{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2767{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2768{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2769{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2770{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2771{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2772{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2773{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2774{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2775{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2776{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2777{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2778{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2779{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2780{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2781{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2782{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2783{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2784{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2785{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2786{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2787{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2788{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2789{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2790{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2791{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2792{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2793{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2794{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2795{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2796{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2797{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2798{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2799{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2800{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2801{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2802{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2803{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2804{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2805{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2806{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2807{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2808{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2809{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2810{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2811{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2812{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2813{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2814{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2815{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2816{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2817{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2818{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2819{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2820{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2821{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2822{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2823{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2824{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2825{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2826{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2827{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2828{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2829{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2830{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2831{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2832{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2833{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2834{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2835{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2836{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2837{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2838{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2839{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2840{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2841{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2842{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2843{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2844{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2845{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2846{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2847{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2848{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2849{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2850{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2851{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2852{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2853{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2854{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2855{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2856{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2857{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2858{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2859{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2860{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2861{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2862{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2863{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2864{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2865{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2866{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2867{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2868{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2869{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2870{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2871{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2872{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2873{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2874{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2875{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2876{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2877{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2878{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2879{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2880{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2881{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2882{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2883{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2884{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2885{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2886{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2887{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2888{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2889{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2890{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2891{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2892{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2893{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2894{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2895{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2896{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2897{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2898{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2899{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2900{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2901{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2902{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2903{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2904{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2905{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2906{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2907{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2908{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2909{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2910{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2911{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2912{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2913{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2914{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2915{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2916{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2917{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2918{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2919{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2920{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2921{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2922{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2923{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2924{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2925{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2926{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2927{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2928{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2929{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2930{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2931{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2932{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2933{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2934{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2935{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2936{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2937{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2938{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2939{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2940{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2941{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2942{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2943{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2944{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2945{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2946{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2947{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2948{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2949{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132
RH		 2950{ "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } },
2951{ "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } },
d2f75a6f
GK		 2952{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2953{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2954{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2955{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
252b5132
RH		 2956{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2957{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
418c1742
MG		 2958{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
2959{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
252b5132 2960
f509565f
GK		 2961{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
2962
252b5132
RH		 2963{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
2964{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
112290ab 2965{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
252b5132
RH		 2966
2967{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
e0c21649 2968{ "rfci", XL(19,51), 0xffffffff, PPC403, { 0 } },
9fa87a06 2969{ "rfci", XL(19,51), 0xffffffff, BOOKE, { 0 } },
252b5132
RH		 2970
2971{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
2972
2973{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
2974
2975{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
2976{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
2977
2978{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2979{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
2980
2981{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
2982
2983{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
2984
2985{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2986{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
2987
2988{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
2989
2990{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
2991{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
2992
2993{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
2994{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
2995{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2996{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2997{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2998{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2999{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3000{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3001{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3002{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3003{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3004{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3005{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3006{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3007{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3008{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3009{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3010{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3011{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3012{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3013{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3014{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3015{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3016{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3017{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3018{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3019{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3020{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3021{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3022{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3023{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3024{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3025{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3026{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3027{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3028{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3029{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3030{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3031{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3032{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3033{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3034{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3035{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3036{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3037{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3038{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3039{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3040{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3041{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3042{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3043{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3044{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3045{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3046{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3047{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3048{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3049{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3050{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3051{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3052{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3053{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3054{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3055{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3056{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3057{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3058{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3059{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3060{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3061{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3062{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3063{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3064{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3065{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3066{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3067{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3068{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3069{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3070{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3071{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3072{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3073{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3074{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3075{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3076{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3077{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3078{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3079{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3080{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3081{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3082{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3083{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3084{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3085{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3086{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3087{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3088{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3089{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3090{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3091{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3092{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3093{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3094{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3095{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3096{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3097{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3098{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3099{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3100{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3101{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3102{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3103{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3104{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3105{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3106{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3107{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3108{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3109{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3110{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3111{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3112{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3113{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3114{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3115{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 3116{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3117{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3118{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3119{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
252b5132 3120{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 3121{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3122{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3123{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3124{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
252b5132 3125{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 3126{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3127{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3128{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3129{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
252b5132 3130{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 3131{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3132{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3133{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3134{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
252b5132 3135{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } },
d2f75a6f
GK		 3136{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3137{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
252b5132 3138{ "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } },
d2f75a6f
GK		 3139{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3140{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
252b5132
RH		 3141{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3142{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
418c1742
MG		 3143{ "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
3144{ "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
252b5132
RH		 3145
3146{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3147{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3148
3149{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3150{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3151
3152{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3153{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3154{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3155{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3156{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3157{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3158{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3159{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3160
3161{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3162{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3163
418c1742
MG		 3164{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
3165{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
3166{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
3167{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
3168
252b5132
RH		 3169{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3170{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3171{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3172{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3173{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3174{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3175
3176{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3177{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3178{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3179
3180{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3181{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3182
3183{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3184{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3185
3186{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3187{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3188
3189{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3190{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3191
3192{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3193{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3194
3195{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3196{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3197{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3198{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3199{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3200{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3201
3202{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3203{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3204
3205{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3206{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3207
3208{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3209{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3210
3211{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3212{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3213{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3214{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3215
3216{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3217{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3218
3219{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3220{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3221{ "cmp", X(31,0), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
3222{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3223
3224{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3225{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3226{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3227{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3228{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3229{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3230{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3231{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3232{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3233{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3234{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3235{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3236{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3237{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3238{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3239{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3240{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3241{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3242{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3243{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3244{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3245{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3246{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3247{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3248{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3249{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3250{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3251{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3252{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
3253{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3254{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3255
3256{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3257{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3258{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3259{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3260{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3261{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3262{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3263{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3264{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3265{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3266{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3267{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3268
3269{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3270{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3271
3272{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3273{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3274{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3275{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3276{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3277{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3278{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3279{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3280
3281{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3282{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3283
dde1b132
NC		 3284{ "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3285{ "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3286{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3287{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
23976049 3288
252b5132
RH		 3289{ "mfcr", X(31,19), XRARB_MASK, COM, { RT } },
3290
3291{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
3292
3293{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } },
3294
418c1742
MG		 3295{ "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } },
3296
252b5132
RH		 3297{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } },
3298{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3299
3300{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3301{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3302{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3303{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3304
3305{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3306{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3307{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3308{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3309
3310{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3311{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3312
3313{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3314{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3315
3316{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3317{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3318
418c1742
MG		 3319{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3320
3321{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA, RB } },
3322
252b5132
RH		 3323{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3324{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3325{ "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
3326{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3327
3328{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3329{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3330{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3331{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3332{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3333{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3334{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3335{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3336
3337{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3338
3339{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3340
3341{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3342{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3343
418c1742
MG		 3344{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3345
3346{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3347
252b5132
RH		 3348{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3349{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3350
418c1742
MG		 3351{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3352{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
252b5132
RH		 3353
3354{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3355{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3356{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3357{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3358{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3359{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3360{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3361{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3362{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3363{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3364{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3365{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3366{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3367{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3368{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3369
3370{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3371{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3372
3373{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3374{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3375
f509565f
GK		 3376{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3377
252b5132
RH		 3378{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3379
3380{ "ldarx", X(31,84), X_MASK, PPC64, { RT, RA, RB } },
3381
3382{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
3383
3384{ "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } },
3385
418c1742
MG		 3386{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3387
3388{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA, RB } },
3389
252b5132
RH		 3390{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3391{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3392{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3393{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3394
3395{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3396{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3397{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3398{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3399
f509565f
GK		 3400{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3401
2dd46b8b 3402{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
252b5132
RH		 3403
3404{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3405
3406{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3407{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3408{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3409{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3410
418c1742
MG		 3411{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA, RB } },
3412
3413{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3414
252b5132 3415{ "wrtee", X(31,131), XRARB_MASK, PPC403, { RS } },
9fa87a06 3416{ "wrtee", X(31,131), XRARB_MASK, BOOKE, { RS } },
252b5132 3417
23976049
EZ		 3418{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3419
252b5132
RH		 3420{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3421{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3422{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3423{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3424{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3425{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3426{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3427{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3428
3429{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3430{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3431{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3432{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3433{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3434{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3435{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3436{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3437
dde1b132 3438{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 3439
252b5132
RH		 3440{ "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM, { RS }},
3441{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3442
3443{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3444
3445{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA, RB } },
3446
3447{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
3448
3449{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } },
3450{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3451
418c1742
MG		 3452{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA, RB } },
3453
3454{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA, RB } },
3455
252b5132
RH		 3456{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3457{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3458
3459{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3460{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3461
3462{ "wrteei", X(31,163), XE_MASK, PPC403, { E } },
9fa87a06 3463{ "wrteei", X(31,163), XE_MASK, BOOKE, { E } },
252b5132 3464
23976049 3465{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
dde1b132 3466{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 3467
82674a1f 3468{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
f509565f 3469
252b5132
RH		 3470{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3471
3472{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3473{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA, RB } },
3474
3475{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3476{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3477
418c1742
MG		 3478{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3479
252b5132
RH		 3480{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3481{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3482{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3483{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3484{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3485{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3486{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3487{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3488
3489{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3490{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3491{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3492{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3493{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3494{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3495{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3496{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3497
3498{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3499
3500{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } },
3501
418c1742 3502{ "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } },
252b5132
RH		 3503
3504{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3505{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3506
3507{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3508{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3509
418c1742
MG		 3510{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA, RB } },
3511
23976049
EZ		 3512{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3513
252b5132
RH		 3514{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3515{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3516{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3517{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3518{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3519{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3520{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3521{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3522
3523{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3524{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3525{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3526{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3527
3528{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3529{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3530{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3531{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3532{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3533{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3534{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3535{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3536
3537{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3538{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3539{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3540{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3541{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3542{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3543{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3544{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3545
dde1b132 3546{ "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
252b5132
RH		 3547{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3548{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3549
418c1742 3550{ "dcbtst", X(31,246), XRT_MASK, PPC, { CT, RA, RB } },
252b5132
RH		 3551
3552{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3553
3554{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3555{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3556
418c1742
MG		 3557{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3558
3559{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3560
9fa87a06
MG		 3561{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3562
0152a4c6
MG		 3563{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3564
252b5132
RH		 3565{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3566{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3567{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3568{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3569
3570{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3571{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3572{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3573{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3574{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3575{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3576{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3577{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3578
c1a34e60
AM		 3579{ "tlbiel", X(31,274), XRTRA_MASK, POWER4, { RB } },
3580
418c1742
MG		 3581{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3582
252b5132
RH		 3583{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3584{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3585
418c1742 3586{ "dcbt", X(31,278), XRT_MASK, PPC, { CT, RA, RB } },
252b5132
RH		 3587
3588{ "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } },
3589
252b5132
RH		 3590{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3591{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3592
418c1742
MG		 3593{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3594
3595{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA, RB } },
3596
98acc1c5 3597{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
252b5132
RH		 3598{ "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } },
3599
3600{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3601
3602{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3603
3604{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3605{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3606
418c1742
MG		 3607{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3608
dde1b132
NC		 3609{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3610{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3611{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3612{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3613{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3614{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3615{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3616{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3617{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3618{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3619{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3620{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3621{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
252b5132
RH		 3622{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3623{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3624{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3625{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3626{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3627{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3628{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3629{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3630{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3631{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3632{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3633{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3634{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3635{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3636{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3637{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3638{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3639{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3640{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3641{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3642{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3643{ "mfdcr", X(31,323), X_MASK, PPC403, { RT, SPR } },
3644{ "mfdcr", X(31,323), X_MASK, BOOKE, { RT, SPR } },
252b5132
RH		 3645
3646{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3647{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3648{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3649{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3650
914749f6 3651{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
23976049 3652
dde1b132
NC		 3653{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3654{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3655{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3656{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3657{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3658{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3659{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3660{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3661{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3662{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3663{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3664{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3665{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3666{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3667{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3668{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3669{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3670{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3671{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
3672{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
3673{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3674{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3675{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3676{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3677{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3678{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3679{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3680{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3681{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3682{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3683{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3684{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3685{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3686{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3687{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3688{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3689{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3690{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3691{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3692{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } },
3693{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
3694{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
3695{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
914749f6 3696{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
dde1b132
NC		 3697{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3698{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3699{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
3700{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3701{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3702{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3703{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3704{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3705{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3706{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3707{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3708{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
3709{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
3710{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
3711{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3712{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
3713{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
3714{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
3715{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
3716{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
3717{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
3718{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
3719{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
3720{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
3721{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
3722{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3723{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3724{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3725{ "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3726{ "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3727{ "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3728{ "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3729{ "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3730{ "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3731{ "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3732{ "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3733{ "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3734{ "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3735{ "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3736{ "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3737{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3738{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3739{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
914749f6 3740{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
dde1b132
NC		 3741{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3742{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3743{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3744{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3745{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3746{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3747{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3748{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3749{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3750{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3751{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3752{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3753{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3754{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3755{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3756{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3757{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3758{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3759{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3760{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3761{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3762{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3763{ "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3764{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3765{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3766{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3767{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3768{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3769{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3770{ "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3771{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3772{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3773{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3774{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3775{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3776{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3777{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3778{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3779{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3780{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3781{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3782{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3783{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3784{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3785{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
e0c21649
GK		 3786{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3787{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3788{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3789{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
252b5132
RH		 3790{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3791{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
e0c21649 3792{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
252b5132 3793{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
e0c21649 3794{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
252b5132 3795{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
e0c21649 3796{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
252b5132 3797{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
e0c21649 3798{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
252b5132 3799{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
e0c21649 3800{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
252b5132 3801{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
dde1b132
NC		 3802{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
3803{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3804{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3805{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3806{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
3807{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3808{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3809{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3810{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3811{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3812{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3813{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
3814{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3815{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3816{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3817{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3818{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3819{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3820{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3821{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3822{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3823{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3824{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3825{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3826{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3827{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3828{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3829{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3830{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3831{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
252b5132
RH		 3832
3833{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } },
3834
f5c120c5
MG		 3835{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3836{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3837
252b5132
RH		 3838{ "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } },
3839
418c1742
MG		 3840{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA, RB } },
3841
f5c120c5
MG		 3842{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3843{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3844
e0c21649 3845{ "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } },
252b5132
RH		 3846
3847{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3848{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3849{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3850{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3851
3852{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3853{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3854{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3855{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3856
3857{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3858
23976049
EZ		 3859{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3860{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
42a2f80a 3861{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
252b5132
RH		 3862
3863{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3864
3865{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3866
418c1742
MG		 3867{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3868
9fa87a06
MG		 3869{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3870
23976049
EZ		 3871{ "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3872
418c1742
MG		 3873{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3874{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3875
3876{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3877{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3878
dde1b132 3879{ "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 3880
6ba045b1
AM		 3881{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3882
252b5132
RH		 3883{ "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } },
3884
3885{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3886
3887{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3888
3889{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3890
3891{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3892
3893{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3894{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3895
3896{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3897{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3898
418c1742
MG		 3899{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA, RB } },
3900
252b5132
RH		 3901{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3902
3903{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
3904
3905{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3906
418c1742
MG		 3907{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3908
252b5132
RH		 3909{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
3910{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3911{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
3912{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3913
dde1b132
NC		 3914{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RT } },
3915{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RT } },
3916{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RT } },
3917{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RT } },
3918{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RT } },
3919{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RT } },
3920{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RT } },
3921{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RT } },
3922{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RT } },
3923{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RT } },
3924{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RT } },
3925{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RT } },
3926{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RT } },
252b5132
RH		 3927{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RT } },
3928{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RT } },
3929{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RT } },
3930{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RT } },
3931{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RT } },
3932{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RT } },
3933{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RT } },
3934{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RT } },
3935{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RT } },
3936{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RT } },
3937{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RT } },
3938{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RT } },
3939{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RT } },
3940{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RT } },
3941{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RT } },
3942{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RT } },
3943{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RT } },
3944{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RT } },
3945{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RT } },
3946{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3947{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RT } },
3948{ "mtdcr", X(31,451), X_MASK, PPC403, { SPR, RS } },
3949{ "mtdcr", X(31,451), X_MASK, BOOKE, { SPR, RS } },
252b5132 3950
418c1742
MG		 3951{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3952{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3953
252b5132
RH		 3954{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3955{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3956{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3957{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3958
418c1742
MG		 3959{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3960{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3961
252b5132
RH		 3962{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
3963{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
3964{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
3965{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
3966
dde1b132
NC		 3967{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
3968{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
3969{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
3970{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
3971{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
3972{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
3973{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
3974{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
3975{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
3976{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
3977{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
3978{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
3979{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
3980{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
3981{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
3982{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
3983{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
3984{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
3985{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
3986{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
3987{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
3988{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RT } },
3989{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RT } },
3990{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RT } },
3991{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RT } },
3992{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RT } },
3993{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RT } },
3994{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RT } },
3995{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RT } },
3996{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RT } },
3997{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RT } },
3998{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RT } },
3999{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RT } },
4000{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RT } },
4001{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RT } },
4002{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RT } },
4003{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RT } },
4004{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RT } },
4005{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
4006{ "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } },
4007{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RT } },
4008{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } },
4009{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RT } },
4010{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RT } },
4011{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405, { RT } },
4012{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, BOOKE, { RS } },
4013{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405, { RT } },
4014{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, BOOKE, { RS } },
4015{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405, { RT } },
4016{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, BOOKE, { RS } },
4017{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405, { RT } },
4018{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, BOOKE, { RS } },
4019{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
4020{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
4021{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
4022{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
4023{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
4024{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
4025{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
4026{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
4027{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
4028{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
4029{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
4030{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
4031{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
4032{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
4033{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
4034{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
4035{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
4036{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
4037{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
4038{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
4039{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
4040{ "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
4041{ "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
4042{ "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
4043{ "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
4044{ "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
4045{ "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
4046{ "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
4047{ "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
4048{ "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
4049{ "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
4050{ "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
4051{ "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
4052{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
42a2f80a 4053{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
dde1b132 4054{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
914749f6 4055{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
dde1b132
NC		 4056{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4057{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4058{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4059{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4060{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
4061{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
4062{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
4063{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RT } },
4064{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RT } },
4065{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RT } },
4066{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RT } },
4067{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RT } },
4068{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RT } },
4069{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RT } },
4070{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RT } },
4071{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RT } },
4072{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RT } },
4073{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RT } },
4074{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RT } },
4075{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RT } },
4076{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RT } },
4077{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RT } },
4078{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RT } },
4079{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RT } },
4080{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RT } },
4081{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RT } },
4082{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RT } },
4083{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RT } },
4084{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RT } },
4085{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RT } },
4086{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RT } },
4087{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RT } },
4088{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RT } },
4089{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RT } },
4090{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RT } },
4091{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RT } },
4092{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RT } },
4093{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RT } },
4094{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RT } },
4095{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RT } },
4096{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RT } },
4097{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RT } },
4098{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RT } },
4099{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RT } },
4100{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RT } },
4101{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RT } },
4102{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RT } },
4103{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RT } },
4104{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RT } },
4105{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RT } },
4106{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RT } },
4107{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RT } },
4108{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RT } },
4109{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RT } },
4110{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RT } },
4111{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RT } },
4112{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RT } },
4113{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RT } },
4114{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RT } },
4115{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RT } },
4116{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RT } },
4117{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RT } },
4118{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
252b5132
RH		 4119
4120{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4121
4122{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4123{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4124
418c1742
MG		 4125{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4126
4db3857a 4127{ "dcread", X(31,486), X_MASK, PPC403, { RT, RA, RB }},
252b5132 4128
914749f6 4129{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
23976049
EZ		 4130
4131{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4132
252b5132 4133{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
418c1742 4134{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
252b5132
RH		 4135{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4136{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
418c1742 4137{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
252b5132
RH		 4138{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4139
4140{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4141{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4142{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4143{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4144
418c1742
MG		 4145{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4146{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4147
252b5132
RH		 4148{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4149{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4150{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4151{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4152
dde1b132 4153{ "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 4154
252b5132
RH		 4155{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
4156
4157{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4158
418c1742
MG		 4159{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4160
252b5132
RH		 4161{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
4162
23976049 4163{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
dde1b132 4164{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
418c1742 4165
252b5132
RH		 4166{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4167
4168{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } },
4169{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4170
4171{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA, RB } },
4172{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4173
4174{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB } },
4175
4176{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4177{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4178{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4179{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4180
4181{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4182{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4183
4184{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4185{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4186
4187{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4188{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4189
418c1742
MG		 4190{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA, RB } },
4191
4192{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA, RB } },
4193
23976049 4194{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
252b5132
RH		 4195{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4196
4197{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4198
418c1742
MG		 4199{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4200
252b5132
RH		 4201{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4202
4203{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } },
4204{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } },
4205
6ba045b1
AM		 4206{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPCONLY, { 0 } },
4207{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
b6be6416 4208{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
6ba045b1 4209{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
252b5132
RH		 4210{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4211
4212{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } },
4213
418c1742
MG		 4214{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA, RB } },
4215
252b5132
RH		 4216{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4217
4218{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4219
4220{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4221
418c1742
MG		 4222{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4223
252b5132
RH		 4224{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4225
4226{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } },
4227{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA, RB } },
4228
4229{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA, RB } },
4230{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA, RB } },
4231
4232{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA, RB } },
4233
4234{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4235{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4236
4237{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4238{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4239
418c1742
MG		 4240{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA, RB } },
4241
4242{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA, RB } },
4243
252b5132
RH		 4244{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4245
4246{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4247{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4248
418c1742
MG		 4249{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4250
252b5132
RH		 4251{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } },
4252{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB } },
4253
4254{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA, RB } },
4255
4256{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4257{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4258
4259{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4260{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4261
418c1742
MG		 4262{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA, RB } },
4263
e0c21649 4264{ "dcba", X(31,758), XRT_MASK, PPC405, { RA, RB } },
9fa87a06 4265{ "dcba", X(31,758), XRT_MASK, BOOKE, { RA, RB } },
e0c21649 4266
252b5132
RH		 4267{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4268
4269{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4270{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4271
418c1742
MG		 4272{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4273
4274{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4275
4276{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
dde1b132 4277{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
418c1742 4278
252b5132
RH		 4279{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } },
4280
4281{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4282{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4283{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4284{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4285
4286{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4287{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4288
418c1742
MG		 4289{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA, RB } },
4290
4291{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA, RB } },
4292{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA, RB } },
4293
252b5132
RH		 4294{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4295
f5c120c5 4296{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
eb0fdfed 4297{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
f5c120c5 4298
252b5132
RH		 4299{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4300{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4301{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4302{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4303
6ba045b1
AM		 4304{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4305
b6be6416 4306{ "mbar", X(31,854), X_MASK, BOOKE, { MO } },
252b5132
RH		 4307{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4308
9fa87a06
MG		 4309{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
4310{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
252b5132 4311
9fa87a06 4312{ "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
7d4a12d2 4313{ "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } },
dde1b132
NC		 4314{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4315{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
418c1742 4316
6ba045b1
AM		 4317{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4318
252b5132
RH		 4319{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } },
4320
4321{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4322{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4323
4324{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4325{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4326
4327{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4328{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4329{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4330{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4331
418c1742
MG		 4332{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA, RB } },
4333
4334{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA, RB } },
4335
2e32aab9 4336{ "tlbre", X(31,946), X_MASK, BOOKE, { 0 } },
418c1742 4337
e0c21649
GK		 4338{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4339{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
1c7c333e 4340{ "tlbre", X(31,946), X_MASK, PPC403, { RS, RA, SH } },
252b5132
RH		 4341
4342{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4343{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4344
4345{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4346{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4347
418c1742
MG		 4348{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4349
e0c21649 4350{ "iccci", X(31,966), XRT_MASK, PPC403, { RA, RB } },
252b5132 4351
2e32aab9
NC		 4352{ "tlbwe", X(31,978), X_MASK, BOOKE, { 0 } },
4353
252b5132 4354{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
e0c21649
GK		 4355
4356{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4357{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
252b5132
RH		 4358{ "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } },
4359
4360{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4361
4362{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
4363
dde1b132
NC		 4364{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4365{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
252b5132
RH		 4366
4367{ "icread", X(31,998), XRT_MASK, PPC403, { RA, RB } },
4368
418c1742
MG		 4369{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4370{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA, RB } },
4371
252b5132
RH		 4372{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4373
4374{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4375{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4376
418c1742
MG		 4377{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4378
786e2c0f
C		 4379{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4380{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4381{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4382{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4383{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4384{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4385{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4386{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4387{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4388{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4389{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4390{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4391
252b5132
RH		 4392{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } },
4393{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } },
4394
4395{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4396{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA } },
4397
4398{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA } },
4399
4400{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4401
4402{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } },
4403{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA } },
4404
4405{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4406{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA } },
4407
4408{ "stb", OP(38), OP_MASK, COM, { RS, D, RA } },
4409
4410{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4411
4412{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA } },
4413
4414{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4415
4416{ "lha", OP(42), OP_MASK, COM, { RT, D, RA } },
4417
4418{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4419
4420{ "sth", OP(44), OP_MASK, COM, { RS, D, RA } },
4421
4422{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4423
4424{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4425{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA } },
4426
4427{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } },
4428{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA } },
4429
4430{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } },
4431
4432{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4433
4434{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } },
4435
4436{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4437
4438{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } },
4439
4440{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4441
4442{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } },
4443
4444{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4445
adadcc0c
AM		 4446{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
4447
252b5132
RH		 4448{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
4449
4450{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
4451
418c1742
MG		 4452{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA } },
4453{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4454{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA } },
4455{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4456{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA } },
4457{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4458{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA } },
4459{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4460{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA } },
4461{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4462{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA } },
4463{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4464{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA } },
4465{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4466
802a735e
AM		 4467{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA } },
4468
4469{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4470
4471{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } },
4472
252b5132
RH		 4473{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4474{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4475
4476{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4477{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4478
4479{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4480{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4481
4482{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4483{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4484
4485{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4486{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4487
4488{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4489{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4490
4491{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4492{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4493
4494{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4495{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4496
4497{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4498{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4499
4500{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4501{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4502
4503{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4504
4505{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4506
418c1742 4507{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA } },
418c1742 4508{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA } },
418c1742
MG		 4509{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA } },
4510{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4511{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA } },
4512{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4513{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA } },
4514{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4515{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA } },
4516{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4517{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA } },
4518{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4519
802a735e
AM		 4520{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } },
4521
4522{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
4523
adadcc0c
AM		 4524{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA } },
4525
252b5132
RH		 4526{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4527
4528{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4529{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4530
4531{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4532{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
4533{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4534{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4535
4536{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4537{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
4538{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4539{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4540
4541{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4542{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4543{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4544{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4545
4546{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4547{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4548{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4549{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4550
4551{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4552{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4553{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4554{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4555
4556{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4557{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4558
4559{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4560{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4561
4562{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4563{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4564{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4565{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4566
4567{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4568{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4569
4570{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4571{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4572{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4573{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4574
4575{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4576{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4577{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4578{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4579
4580{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4581{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4582{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4583{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4584
4585{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4586{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4587{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4588{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4589
4590{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4591
4592{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4593{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
4594
4595{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
4596{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
4597
4598{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4599
4600{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4601{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4602
4603{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4604{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4605
4606{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4607{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4608
4609{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4610{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4611
4612{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4613{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4614
4615{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4616{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4617
4618{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
4619{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
4620
4621{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
4622{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
4623
4624{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
4625{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
4626
4627{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
4628{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
4629
4630};
4631
4632const int powerpc_num_opcodes =
4633 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4634\f
4635/* The macro table. This is only used by the assembler. */
4636
4637/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4638 when x=0; 32-x when x is between 1 and 31; are negative if x is
4639 negative; and are 32 or more otherwise. This is what you want
4640 when, for instance, you are emulating a right shift by a
4641 rotate-left-and-mask, because the underlying instructions support
4642 shifts of size 0 but not shifts of size 32. By comparison, when
4643 extracting x bits from some word you want to use just 32-x, because
4644 the underlying instructions don't support extracting 0 bits but do
4645 support extracting the whole word (32 bits in this case). */
4646
4647const struct powerpc_macro powerpc_macros[] = {
4648{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
4649{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
4650{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4651{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4652{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4653{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4654{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4655{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4656{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
4657{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
4658{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4659{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4660{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
4661{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
4662{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
4663{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
4664
4665{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
4666{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
29ef7e54
AM		 4667{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4668{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
252b5132
RH		 4669{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4670{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4671{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4672{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4673{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4674{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4675{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
4676{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
4677{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
4678{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
4679{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4680{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4681{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4682{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4683{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
4684{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
4685{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4686{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
252b5132
RH		 4687};
4688
4689const int powerpc_num_macros =
4690 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
GDB Binutils - Deliverables
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