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[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c
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252b5132 1/* ppc-opc.c -- PowerPC opcode list
5e8cb021 2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
6b069ee7
AM		 3 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
252b5132
RH		 5 Written by Ian Lance Taylor, Cygnus Support
6
9b201bb5 7 This file is part of the GNU opcodes library.
252b5132 8
9b201bb5
NC		 9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
252b5132 13
9b201bb5
NC		 14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
252b5132 18
112290ab 19 You should have received a copy of the GNU General Public License
9b201bb5
NC		 20 along with this file; see the file COPYING. If not, write to the
21 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
252b5132
RH		 23
24#include <stdio.h>
0d8dfecf 25#include "sysdep.h"
252b5132
RH		 26#include "opcode/ppc.h"
27#include "opintl.h"
28
29/* This file holds the PowerPC opcode table. The opcode table
30 includes almost all of the extended instruction mnemonics. This
31 permits the disassembler to use them, and simplifies the assembler
32 logic, at the cost of increasing the table size. The table is
33 strictly constant data, so the compiler should be able to put it in
34 the .text section.
35
36 This file also holds the operand table. All knowledge about
37 inserting operands into instructions and vice-versa is kept in this
38 file. */
39\f
40/* Local insertion and extraction functions. */
41
fa452fa6
PB		 42static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
43static long extract_bat (unsigned long, ppc_cpu_t, int *);
44static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
45static long extract_bba (unsigned long, ppc_cpu_t, int *);
46static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
47static long extract_bdm (unsigned long, ppc_cpu_t, int *);
48static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
49static long extract_bdp (unsigned long, ppc_cpu_t, int *);
50static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
51static long extract_bo (unsigned long, ppc_cpu_t, int *);
52static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
53static long extract_boe (unsigned long, ppc_cpu_t, int *);
54static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
55static long extract_fxm (unsigned long, ppc_cpu_t, int *);
56static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
57static long extract_mbe (unsigned long, ppc_cpu_t, int *);
58static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
59static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
60static long extract_nb (unsigned long, ppc_cpu_t, int *);
989993d8 61static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **);
fa452fa6
PB		 62static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
63static long extract_nsi (unsigned long, ppc_cpu_t, int *);
64static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
65static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
66static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
67static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
68static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
69static long extract_rbs (unsigned long, ppc_cpu_t, int *);
989993d8 70static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **);
fa452fa6
PB		 71static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
72static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
73static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
74static long extract_spr (unsigned long, ppc_cpu_t, int *);
75static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
76static long extract_sprg (unsigned long, ppc_cpu_t, int *);
77static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
78static long extract_tbr (unsigned long, ppc_cpu_t, int *);
9b4e5766
PB		 79static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
80static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
81static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
82static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
83static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
84static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
85static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
86static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
066be9f7
PB		 87static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
88static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
89static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
90static long extract_dm (unsigned long, ppc_cpu_t, int *);
252b5132
RH		 91\f
92/* The operands table.
93
717bbdf1 94 The fields are bitm, shift, insert, extract, flags.
252b5132
RH		 95
96 We used to put parens around the various additions, like the one
97 for BA just below. However, that caused trouble with feeble
98 compilers with a limit on depth of a parenthesized expression, like
99 (reportedly) the compiler in Microsoft Developer Studio 5. So we
100 omit the parens, since the macros are never used in a context where
101 the addition will be ambiguous. */
102
103const struct powerpc_operand powerpc_operands[] =
104{
105 /* The zero index is used to indicate the end of the list of
106 operands. */
107#define UNUSED 0
bbac1f2a 108 { 0, 0, NULL, NULL, 0 },
252b5132
RH		 109
110 /* The BA field in an XL form instruction. */
111#define BA UNUSED + 1
717bbdf1
AM		 112 /* The BI field in a B form or XL form instruction. */
113#define BI BA
114#define BI_MASK (0x1f << 16)
b84bf58a 115 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 116
117 /* The BA field in an XL form instruction when it must be the same
118 as the BT field in the same instruction. */
119#define BAT BA + 1
b84bf58a 120 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
252b5132
RH		 121
122 /* The BB field in an XL form instruction. */
123#define BB BAT + 1
124#define BB_MASK (0x1f << 11)
b84bf58a 125 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 126
127 /* The BB field in an XL form instruction when it must be the same
128 as the BA field in the same instruction. */
129#define BBA BB + 1
b84bf58a 130 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
252b5132
RH		 131
132 /* The BD field in a B form instruction. The lower two bits are
133 forced to zero. */
134#define BD BBA + 1
b84bf58a 135 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 136
137 /* The BD field in a B form instruction when absolute addressing is
138 used. */
139#define BDA BD + 1
b84bf58a 140 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 141
142 /* The BD field in a B form instruction when the - modifier is used.
143 This sets the y bit of the BO field appropriately. */
144#define BDM BDA + 1
b84bf58a 145 { 0xfffc, 0, insert_bdm, extract_bdm,
11b37b7b 146 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 147
148 /* The BD field in a B form instruction when the - modifier is used
149 and absolute address is used. */
150#define BDMA BDM + 1
b84bf58a 151 { 0xfffc, 0, insert_bdm, extract_bdm,
11b37b7b 152 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 153
154 /* The BD field in a B form instruction when the + modifier is used.
155 This sets the y bit of the BO field appropriately. */
156#define BDP BDMA + 1
b84bf58a 157 { 0xfffc, 0, insert_bdp, extract_bdp,
11b37b7b 158 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 159
160 /* The BD field in a B form instruction when the + modifier is used
161 and absolute addressing is used. */
162#define BDPA BDP + 1
b84bf58a 163 { 0xfffc, 0, insert_bdp, extract_bdp,
11b37b7b 164 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 165
166 /* The BF field in an X or XL form instruction. */
167#define BF BDPA + 1
717bbdf1
AM		 168 /* The CRFD field in an X form instruction. */
169#define CRFD BF
b84bf58a 170 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
252b5132 171
ea192fa3
PB		 172 /* The BF field in an X or XL form instruction. */
173#define BFF BF + 1
174 { 0x7, 23, NULL, NULL, 0 },
175
252b5132
RH		 176 /* An optional BF field. This is used for comparison instructions,
177 in which an omitted BF field is taken as zero. */
ea192fa3 178#define OBF BFF + 1
b84bf58a 179 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132
RH		 180
181 /* The BFA field in an X or XL form instruction. */
182#define BFA OBF + 1
b84bf58a 183 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
252b5132 184
252b5132
RH		 185 /* The BO field in a B form instruction. Certain values are
186 illegal. */
717bbdf1 187#define BO BFA + 1
252b5132 188#define BO_MASK (0x1f << 21)
b84bf58a 189 { 0x1f, 21, insert_bo, extract_bo, 0 },
252b5132
RH		 190
191 /* The BO field in a B form instruction when the + or - modifier is
192 used. This is like the BO field, but it must be even. */
193#define BOE BO + 1
b84bf58a 194 { 0x1e, 21, insert_boe, extract_boe, 0 },
252b5132 195
d0618d1c 196#define BH BOE + 1
b84bf58a 197 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
d0618d1c 198
252b5132 199 /* The BT field in an X or XL form instruction. */
d0618d1c 200#define BT BH + 1
b84bf58a 201 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 202
203 /* The condition register number portion of the BI field in a B form
204 or XL form instruction. This is used for the extended
205 conditional branch mnemonics, which set the lower two bits of the
206 BI field. This field is optional. */
207#define CR BT + 1
b84bf58a 208 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132 209
23976049
EZ		 210 /* The CRB field in an X form instruction. */
211#define CRB CR + 1
717bbdf1
AM		 212 /* The MB field in an M form instruction. */
213#define MB CRB
214#define MB_MASK (0x1f << 6)
b84bf58a 215 { 0x1f, 6, NULL, NULL, 0 },
23976049 216
23976049 217 /* The CRFS field in an X form instruction. */
717bbdf1 218#define CRFS CRB + 1
b84bf58a 219 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
23976049 220
418c1742 221 /* The CT field in an X form instruction. */
23976049 222#define CT CRFS + 1
717bbdf1
AM		 223 /* The MO field in an mbar instruction. */
224#define MO CT
b84bf58a 225 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
418c1742 226
252b5132
RH		 227 /* The D field in a D form instruction. This is a displacement off
228 a register, and implies that the next operand is a register in
229 parentheses. */
418c1742 230#define D CT + 1
b84bf58a 231 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
252b5132 232
adadcc0c
AM		 233 /* The DQ field in a DQ form instruction. This is like D, but the
234 lower four bits are forced to zero. */
2f3bb96a 235#define DQ D + 1
b84bf58a
AM		 236 { 0xfff0, 0, NULL, NULL,
237 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
adadcc0c 238
252b5132
RH		 239 /* The DS field in a DS form instruction. This is like D, but the
240 lower two bits are forced to zero. */
adadcc0c 241#define DS DQ + 1
b84bf58a
AM		 242 { 0xfffc, 0, NULL, NULL,
243 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
252b5132 244
19a6653c
AM		 245 /* The DUIS field in a XFX form instruction, 10 bits unsigned imediate */
246#define DUIS DS + 1
247 { 0x3ff, 11, NULL, NULL, 0 },
248
252b5132 249 /* The E field in a wrteei instruction. */
c3d65c1c 250 /* And the W bit in the pair singles instructions. */
19a6653c 251#define E DUIS + 1
c3d65c1c 252#define PSW E
b84bf58a 253 { 0x1, 15, NULL, NULL, 0 },
252b5132
RH		 254
255 /* The FL1 field in a POWER SC form instruction. */
256#define FL1 E + 1
717bbdf1
AM		 257 /* The U field in an X form instruction. */
258#define U FL1
b84bf58a 259 { 0xf, 12, NULL, NULL, 0 },
252b5132
RH		 260
261 /* The FL2 field in a POWER SC form instruction. */
262#define FL2 FL1 + 1
b84bf58a 263 { 0x7, 2, NULL, NULL, 0 },
252b5132
RH		 264
265 /* The FLM field in an XFL form instruction. */
266#define FLM FL2 + 1
b84bf58a 267 { 0xff, 17, NULL, NULL, 0 },
252b5132
RH		 268
269 /* The FRA field in an X or A form instruction. */
270#define FRA FLM + 1
271#define FRA_MASK (0x1f << 16)
b84bf58a 272 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
252b5132 273
989993d8
JB		 274 /* The FRAp field of DFP instructions. */
275#define FRAp FRA + 1
276 { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR },
277
252b5132 278 /* The FRB field in an X or A form instruction. */
989993d8 279#define FRB FRAp + 1
252b5132 280#define FRB_MASK (0x1f << 11)
b84bf58a 281 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
252b5132 282
989993d8
JB		 283 /* The FRBp field of DFP instructions. */
284#define FRBp FRB + 1
285 { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR },
286
252b5132 287 /* The FRC field in an A form instruction. */
989993d8 288#define FRC FRBp + 1
252b5132 289#define FRC_MASK (0x1f << 6)
b84bf58a 290 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 291
292 /* The FRS field in an X form instruction or the FRT field in a D, X
293 or A form instruction. */
294#define FRS FRC + 1
295#define FRT FRS
b84bf58a 296 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
252b5132 297
989993d8
JB		 298 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
299 instructions. */
300#define FRSp FRS + 1
301#define FRTp FRSp
302 { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR },
303
252b5132 304 /* The FXM field in an XFX instruction. */
989993d8 305#define FXM FRSp + 1
b84bf58a 306 { 0xff, 12, insert_fxm, extract_fxm, 0 },
c168870a
AM		 307
308 /* Power4 version for mfcr. */
309#define FXM4 FXM + 1
b84bf58a 310 { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
252b5132
RH		 311
312 /* The L field in a D or X form instruction. */
c168870a 313#define L FXM4 + 1
b84bf58a 314 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
252b5132 315
1ed8e1e4
AM		 316 /* The LEV field in a POWER SVC form instruction. */
317#define SVC_LEV L + 1
b84bf58a 318 { 0x7f, 5, NULL, NULL, 0 },
252b5132 319
1ed8e1e4
AM		 320 /* The LEV field in an SC form instruction. */
321#define LEV SVC_LEV + 1
b84bf58a 322 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
1ed8e1e4 323
252b5132
RH		 324 /* The LI field in an I form instruction. The lower two bits are
325 forced to zero. */
326#define LI LEV + 1
b84bf58a 327 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 328
329 /* The LI field in an I form instruction when used as an absolute
330 address. */
331#define LIA LI + 1
b84bf58a 332 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132 333
066be9f7 334 /* The LS or WC field in an X (sync or wait) form instruction. */
6ba045b1 335#define LS LIA + 1
066be9f7 336#define WC LS
b84bf58a 337 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
6ba045b1 338
252b5132 339 /* The ME field in an M form instruction. */
717bbdf1 340#define ME LS + 1
252b5132 341#define ME_MASK (0x1f << 1)
b84bf58a 342 { 0x1f, 1, NULL, NULL, 0 },
252b5132
RH		 343
344 /* The MB and ME fields in an M form instruction expressed a single
345 operand which is a bitmask indicating which bits to select. This
346 is a two operand form using PPC_OPERAND_NEXT. See the
347 description in opcode/ppc.h for what this means. */
348#define MBE ME + 1
b84bf58a 349 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
eb42fac1 350 { -1, 0, insert_mbe, extract_mbe, 0 },
252b5132
RH		 351
352 /* The MB or ME field in an MD or MDS form instruction. The high
353 bit is wrapped to the low end. */
354#define MB6 MBE + 2
355#define ME6 MB6
356#define MB6_MASK (0x3f << 5)
b84bf58a 357 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
252b5132
RH		 358
359 /* The NB field in an X form instruction. The value 32 is stored as
360 0. */
717bbdf1 361#define NB MB6 + 1
b84bf58a 362 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
252b5132 363
989993d8
JB		 364 /* The NBI field in an lswi instruction, which has special value
365 restrictions. The value 32 is stored as 0. */
366#define NBI NB + 1
367 { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 },
368
252b5132
RH		 369 /* The NSI field in a D form instruction. This is the same as the
370 SI field, only negated. */
989993d8 371#define NSI NBI + 1
b84bf58a 372 { 0xffff, 0, insert_nsi, extract_nsi,
11b37b7b 373 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
252b5132 374
adadcc0c 375 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
914749f6 376#define RA NSI + 1
252b5132 377#define RA_MASK (0x1f << 16)
b84bf58a 378 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
252b5132 379
fdd12ef3
AM		 380 /* As above, but 0 in the RA field means zero, not r0. */
381#define RA0 RA + 1
b84bf58a 382 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
fdd12ef3 383
989993d8 384 /* The RA field in the DQ form lq or an lswx instruction, which have special
adadcc0c 385 value restrictions. */
fdd12ef3 386#define RAQ RA0 + 1
989993d8 387#define RAX RAQ
b84bf58a 388 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
adadcc0c 389
252b5132
RH		 390 /* The RA field in a D or X form instruction which is an updating
391 load, which means that the RA field may not be zero and may not
392 equal the RT field. */
adadcc0c 393#define RAL RAQ + 1
b84bf58a 394 { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
252b5132
RH		 395
396 /* The RA field in an lmw instruction, which has special value
397 restrictions. */
398#define RAM RAL + 1
b84bf58a 399 { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
252b5132
RH		 400
401 /* The RA field in a D or X form instruction which is an updating
402 store or an updating floating point load, which means that the RA
403 field may not be zero. */
404#define RAS RAM + 1
b84bf58a 405 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
252b5132 406
cee62821
PB		 407 /* The RA field of the tlbwe, dccci and iccci instructions,
408 which are optional. */
fdd12ef3 409#define RAOPT RAS + 1
b84bf58a 410 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 411
252b5132 412 /* The RB field in an X, XO, M, or MDS form instruction. */
fdd12ef3 413#define RB RAOPT + 1
252b5132 414#define RB_MASK (0x1f << 11)
b84bf58a 415 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
252b5132
RH		 416
417 /* The RB field in an X form instruction when it must be the same as
418 the RS field in the instruction. This is used for extended
419 mnemonics like mr. */
420#define RBS RB + 1
b84bf58a 421 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
252b5132 422
989993d8
JB		 423 /* The RB field in an lswx instruction, which has special value
424 restrictions. */
425#define RBX RBS + 1
426 { 0x1f, 11, insert_rbx, NULL, PPC_OPERAND_GPR },
427
cee62821 428 /* The RB field of the dccci and iccci instructions, which are optional. */
989993d8 429#define RBOPT RBX + 1
cee62821
PB		 430 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
431
252b5132
RH		 432 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
433 instruction or the RT field in a D, DS, X, XFX or XO form
434 instruction. */
cee62821 435#define RS RBOPT + 1
252b5132
RH		 436#define RT RS
437#define RT_MASK (0x1f << 21)
b84bf58a 438 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
252b5132 439
717bbdf1
AM		 440 /* The RS and RT fields of the DS form stq instruction, which have
441 special value restrictions. */
adadcc0c 442#define RSQ RS + 1
717bbdf1 443#define RTQ RSQ
b84bf58a 444 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
adadcc0c 445
1f6c9eb0 446 /* The RS field of the tlbwe instruction, which is optional. */
717bbdf1 447#define RSO RSQ + 1
eed0d89a 448#define RTO RSO
b84bf58a 449 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 450
252b5132 451 /* The SH field in an X or M form instruction. */
1f6c9eb0 452#define SH RSO + 1
252b5132 453#define SH_MASK (0x1f << 11)
717bbdf1
AM		 454 /* The other UIMM field in a EVX form instruction. */
455#define EVUIMM SH
b84bf58a 456 { 0x1f, 11, NULL, NULL, 0 },
252b5132
RH		 457
458 /* The SH field in an MD form instruction. This is split. */
459#define SH6 SH + 1
460#define SH6_MASK ((0x1f << 11) | (1 << 1))
b84bf58a 461 { 0x3f, -1, insert_sh6, extract_sh6, 0 },
252b5132 462
1f6c9eb0
ZW		 463 /* The SH field of the tlbwe instruction, which is optional. */
464#define SHO SH6 + 1
b84bf58a 465 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
1f6c9eb0 466
252b5132 467 /* The SI field in a D form instruction. */
1f6c9eb0 468#define SI SHO + 1
b84bf58a 469 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
252b5132
RH		 470
471 /* The SI field in a D form instruction when we accept a wide range
472 of positive values. */
473#define SISIGNOPT SI + 1
b84bf58a 474 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
252b5132
RH		 475
476 /* The SPR field in an XFX form instruction. This is flipped--the
477 lower 5 bits are stored in the upper 5 and vice- versa. */
478#define SPR SISIGNOPT + 1
914749f6 479#define PMR SPR
252b5132 480#define SPR_MASK (0x3ff << 11)
b84bf58a 481 { 0x3ff, 11, insert_spr, extract_spr, 0 },
252b5132
RH		 482
483 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
484#define SPRBAT SPR + 1
485#define SPRBAT_MASK (0x3 << 17)
b84bf58a 486 { 0x3, 17, NULL, NULL, 0 },
252b5132
RH		 487
488 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
489#define SPRG SPRBAT + 1
b84bf58a 490 { 0x1f, 16, insert_sprg, extract_sprg, 0 },
252b5132
RH		 491
492 /* The SR field in an X form instruction. */
493#define SR SPRG + 1
b84bf58a 494 { 0xf, 16, NULL, NULL, 0 },
252b5132 495
f5c120c5
MG		 496 /* The STRM field in an X AltiVec form instruction. */
497#define STRM SR + 1
19a6653c
AM		 498 /* The T field in a tlbilx form instruction. */
499#define T STRM
b84bf58a 500 { 0x3, 21, NULL, NULL, 0 },
f5c120c5 501
252b5132 502 /* The SV field in a POWER SC form instruction. */
f5c120c5 503#define SV STRM + 1
b84bf58a 504 { 0x3fff, 2, NULL, NULL, 0 },
252b5132
RH		 505
506 /* The TBR field in an XFX form instruction. This is like the SPR
507 field, but it is optional. */
508#define TBR SV + 1
b84bf58a 509 { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
252b5132
RH		 510
511 /* The TO field in a D or X form instruction. */
512#define TO TBR + 1
19a6653c 513#define DUI TO
252b5132 514#define TO_MASK (0x1f << 21)
b84bf58a 515 { 0x1f, 21, NULL, NULL, 0 },
252b5132 516
252b5132 517 /* The UI field in a D form instruction. */
717bbdf1 518#define UI TO + 1
b84bf58a 519 { 0xffff, 0, NULL, NULL, 0 },
786e2c0f 520
112290ab 521 /* The VA field in a VA, VX or VXR form instruction. */
786e2c0f 522#define VA UI + 1
b84bf58a 523 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 524
112290ab 525 /* The VB field in a VA, VX or VXR form instruction. */
786e2c0f 526#define VB VA + 1
b84bf58a 527 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 528
112290ab 529 /* The VC field in a VA form instruction. */
786e2c0f 530#define VC VB + 1
b84bf58a 531 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 532
112290ab 533 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
786e2c0f
C		 534#define VD VC + 1
535#define VS VD
b84bf58a 536 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 537
8dbcd839 538 /* The SIMM field in a VX form instruction, and TE in Z form. */
786e2c0f 539#define SIMM VD + 1
8dbcd839 540#define TE SIMM
b84bf58a 541 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
786e2c0f 542
8dbcd839 543 /* The UIMM field in a VX form instruction. */
786e2c0f 544#define UIMM SIMM + 1
b84bf58a 545 { 0x1f, 16, NULL, NULL, 0 },
786e2c0f 546
112290ab 547 /* The SHB field in a VA form instruction. */
786e2c0f 548#define SHB UIMM + 1
b84bf58a 549 { 0xf, 6, NULL, NULL, 0 },
ff3a6ee3 550
112290ab 551 /* The other UIMM field in a half word EVX form instruction. */
717bbdf1 552#define EVUIMM_2 SHB + 1
b84bf58a 553 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
23976049 554
112290ab 555 /* The other UIMM field in a word EVX form instruction. */
23976049 556#define EVUIMM_4 EVUIMM_2 + 1
b84bf58a 557 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
23976049 558
112290ab 559 /* The other UIMM field in a double EVX form instruction. */
23976049 560#define EVUIMM_8 EVUIMM_4 + 1
b84bf58a 561 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
23976049 562
ff3a6ee3 563 /* The WS field. */
23976049 564#define WS EVUIMM_8 + 1
b84bf58a 565 { 0x7, 11, NULL, NULL, 0 },
ff3a6ee3 566
c3d65c1c
BE		 567 /* PowerPC paired singles extensions. */
568 /* W bit in the pair singles instructions for x type instructions. */
569#define PSWM WS + 1
570 { 0x1, 10, 0, 0, 0 },
571
572 /* IDX bits for quantization in the pair singles instructions. */
573#define PSQ PSWM + 1
574 { 0x7, 12, 0, 0, 0 },
575
576 /* IDX bits for quantization in the pair singles x-type instructions. */
577#define PSQM PSQ + 1
578 { 0x7, 7, 0, 0, 0 },
579
580 /* Smaller D field for quantization in the pair singles instructions. */
581#define PSD PSQM + 1
582 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
583
584#define A_L PSD + 1
ea192fa3 585#define W A_L
c3d65c1c 586#define MTMSRD_L W
b84bf58a 587 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
5ae2e65e 588
c3d65c1c 589#define RMC MTMSRD_L + 1
b84bf58a 590 { 0x3, 9, NULL, NULL, 0 },
702f0fb4
PB		 591
592#define R RMC + 1
b84bf58a 593 { 0x1, 16, NULL, NULL, 0 },
702f0fb4
PB		 594
595#define SP R + 1
b84bf58a 596 { 0x3, 19, NULL, NULL, 0 },
702f0fb4
PB		 597
598#define S SP + 1
b84bf58a 599 { 0x1, 20, NULL, NULL, 0 },
702f0fb4
PB		 600
601 /* SH field starting at bit position 16. */
602#define SH16 S + 1
0bbdef92
AM		 603 /* The DCM and DGM fields in a Z form instruction. */
604#define DCM SH16
605#define DGM DCM
b84bf58a 606 { 0x3f, 10, NULL, NULL, 0 },
702f0fb4 607
702f0fb4 608 /* The EH field in larx instruction. */
717bbdf1 609#define EH SH16 + 1
b84bf58a 610 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
ea192fa3
PB		 611
612 /* The L field in an mtfsf or XFL form instruction. */
613#define XFL_L EH + 1
614 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
081ba1b3
AM		 615
616 /* Xilinx APU related masks and macros */
617#define FCRT XFL_L + 1
618#define FCRT_MASK (0x1f << 21)
619 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
620
621 /* Xilinx FSL related masks and macros */
622#define FSL FCRT + 1
623#define FSL_MASK (0x1f << 11)
624 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
625
626 /* Xilinx UDI related masks and macros */
627#define URT FSL + 1
628 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
629
630#define URA URT + 1
631 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
632
633#define URB URA + 1
634 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
635
636#define URC URB + 1
637 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
638
9b4e5766
PB		 639 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
640#define XS6 URC + 1
641#define XT6 XS6
642 { 0x3f, -1, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
643
644 /* The XA field in an XX3 form instruction. This is split. */
645#define XA6 XT6 + 1
646 { 0x3f, -1, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
647
066be9f7 648 /* The XB field in an XX2 or XX3 form instruction. This is split. */
9b4e5766
PB		 649#define XB6 XA6 + 1
650 { 0x3f, -1, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
651
652 /* The XB field in an XX3 form instruction when it must be the same as
653 the XA field in the instruction. This is used in extended mnemonics
654 like xvmovdp. This is split. */
655#define XB6S XB6 + 1
656 { 0x3f, -1, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
657
066be9f7
PB		 658 /* The XC field in an XX4 form instruction. This is split. */
659#define XC6 XB6S + 1
660 { 0x3f, -1, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
661
662 /* The DM or SHW field in an XX3 form instruction. */
663#define DM XC6 + 1
664#define SHW DM
9b4e5766 665 { 0x3, 8, NULL, NULL, 0 },
066be9f7
PB		 666
667 /* The DM field in an extended mnemonic XX3 form instruction. */
668#define DMEX DM + 1
669 { 0x3, 8, insert_dm, extract_dm, 0 },
670
671 /* The UIM field in an XX2 form instruction. */
672#define UIM DMEX + 1
673 { 0x3, 16, NULL, NULL, 0 },
e0d602ec
BE		 674
675#define ERAT_T UIM + 1
676 { 0x7, 21, NULL, NULL, 0 },
252b5132
RH		 677};
678
b84bf58a
AM		 679const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
680 / sizeof (powerpc_operands[0]));
681
252b5132
RH		 682/* The functions used to insert and extract complicated operands. */
683
684/* The BA field in an XL form instruction when it must be the same as
685 the BT field in the same instruction. This operand is marked FAKE.
686 The insertion function just copies the BT field into the BA field,
687 and the extraction function just checks that the fields are the
688 same. */
689
252b5132 690static unsigned long
2fbfdc41
AM		 691insert_bat (unsigned long insn,
692 long value ATTRIBUTE_UNUSED,
fa452fa6 693 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 694 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 695{
696 return insn | (((insn >> 21) & 0x1f) << 16);
697}
698
699static long
2fbfdc41 700extract_bat (unsigned long insn,
fa452fa6 701 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 702 int *invalid)
252b5132 703{
8427c424 704 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
252b5132
RH		 705 *invalid = 1;
706 return 0;
707}
708
709/* The BB field in an XL form instruction when it must be the same as
710 the BA field in the same instruction. This operand is marked FAKE.
711 The insertion function just copies the BA field into the BB field,
712 and the extraction function just checks that the fields are the
713 same. */
714
252b5132 715static unsigned long
2fbfdc41
AM		 716insert_bba (unsigned long insn,
717 long value ATTRIBUTE_UNUSED,
fa452fa6 718 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 719 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 720{
721 return insn | (((insn >> 16) & 0x1f) << 11);
722}
723
724static long
2fbfdc41 725extract_bba (unsigned long insn,
fa452fa6 726 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 727 int *invalid)
252b5132 728{
8427c424 729 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 730 *invalid = 1;
731 return 0;
732}
733
252b5132
RH		 734/* The BD field in a B form instruction when the - modifier is used.
735 This modifier means that the branch is not expected to be taken.
94efba12
AM		 736 For chips built to versions of the architecture prior to version 2
737 (ie. not Power4 compatible), we set the y bit of the BO field to 1
738 if the offset is negative. When extracting, we require that the y
739 bit be 1 and that the offset be positive, since if the y bit is 0
740 we just want to print the normal form of the instruction.
741 Power4 compatible targets use two bits, "a", and "t", instead of
742 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
743 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
744 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
ba4e851b
AM		 745 for branch on CTR. We only handle the taken/not-taken hint here.
746 Note that we don't relax the conditions tested here when
747 disassembling with -Many because insns using extract_bdm and
748 extract_bdp always occur in pairs. One or the other will always
749 be valid. */
252b5132 750
8ebac3aa
AM		 751#define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
752
252b5132 753static unsigned long
2fbfdc41
AM		 754insert_bdm (unsigned long insn,
755 long value,
fa452fa6 756 ppc_cpu_t dialect,
2fbfdc41 757 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 758{
8ebac3aa 759 if ((dialect & ISA_V2) == 0)
802a735e
AM		 760 {
761 if ((value & 0x8000) != 0)
762 insn |= 1 << 21;
763 }
764 else
765 {
766 if ((insn & (0x14 << 21)) == (0x04 << 21))
767 insn |= 0x02 << 21;
768 else if ((insn & (0x14 << 21)) == (0x10 << 21))
769 insn |= 0x08 << 21;
770 }
252b5132
RH		 771 return insn | (value & 0xfffc);
772}
773
774static long
2fbfdc41 775extract_bdm (unsigned long insn,
fa452fa6 776 ppc_cpu_t dialect,
2fbfdc41 777 int *invalid)
252b5132 778{
8ebac3aa 779 if ((dialect & ISA_V2) == 0)
802a735e 780 {
8427c424
AM		 781 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
782 *invalid = 1;
802a735e 783 }
8427c424
AM		 784 else
785 {
786 if ((insn & (0x17 << 21)) != (0x06 << 21)
787 && (insn & (0x1d << 21)) != (0x18 << 21))
788 *invalid = 1;
789 }
790
802a735e 791 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 792}
793
794/* The BD field in a B form instruction when the + modifier is used.
795 This is like BDM, above, except that the branch is expected to be
796 taken. */
797
252b5132 798static unsigned long
2fbfdc41
AM		 799insert_bdp (unsigned long insn,
800 long value,
fa452fa6 801 ppc_cpu_t dialect,
2fbfdc41 802 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 803{
8ebac3aa 804 if ((dialect & ISA_V2) == 0)
802a735e
AM		 805 {
806 if ((value & 0x8000) == 0)
807 insn |= 1 << 21;
808 }
809 else
810 {
811 if ((insn & (0x14 << 21)) == (0x04 << 21))
812 insn |= 0x03 << 21;
813 else if ((insn & (0x14 << 21)) == (0x10 << 21))
814 insn |= 0x09 << 21;
815 }
252b5132
RH		 816 return insn | (value & 0xfffc);
817}
818
819static long
2fbfdc41 820extract_bdp (unsigned long insn,
fa452fa6 821 ppc_cpu_t dialect,
2fbfdc41 822 int *invalid)
252b5132 823{
8ebac3aa 824 if ((dialect & ISA_V2) == 0)
802a735e 825 {
8427c424
AM		 826 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
827 *invalid = 1;
828 }
829 else
830 {
831 if ((insn & (0x17 << 21)) != (0x07 << 21)
832 && (insn & (0x1d << 21)) != (0x19 << 21))
833 *invalid = 1;
802a735e 834 }
8427c424 835
802a735e 836 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 837}
838
8ebac3aa
AM		 839static inline int
840valid_bo_pre_v2 (long value)
252b5132 841{
8ebac3aa
AM		 842 /* Certain encodings have bits that are required to be zero.
843 These are (z must be zero, y may be anything):
844 0000y
845 0001y
846 001zy
847 0100y
848 0101y
849 011zy
850 1z00y
851 1z01y
852 1z1zz
853 */
854 if ((value & 0x14) == 0)
855 return 1;
856 else if ((value & 0x14) == 0x4)
857 return (value & 0x2) == 0;
858 else if ((value & 0x14) == 0x10)
859 return (value & 0x8) == 0;
860 else
861 return value == 0x14;
862}
ba4e851b 863
8ebac3aa
AM		 864static inline int
865valid_bo_post_v2 (long value)
866{
ba4e851b
AM		 867 /* Certain encodings have bits that are required to be zero.
868 These are (z must be zero, a & t may be anything):
869 0000z
870 0001z
8ebac3aa 871 001at
ba4e851b
AM		 872 0100z
873 0101z
ba4e851b
AM		 874 011at
875 1a00t
876 1a01t
877 1z1zz
878 */
879 if ((value & 0x14) == 0)
880 return (value & 0x1) == 0;
881 else if ((value & 0x14) == 0x14)
882 return value == 0x14;
802a735e 883 else
ba4e851b 884 return 1;
252b5132
RH		 885}
886
8ebac3aa
AM		 887/* Check for legal values of a BO field. */
888
889static int
890valid_bo (long value, ppc_cpu_t dialect, int extract)
891{
892 int valid_y = valid_bo_pre_v2 (value);
893 int valid_at = valid_bo_post_v2 (value);
894
895 /* When disassembling with -Many, accept either encoding on the
896 second pass through opcodes. */
897 if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY)
898 return valid_y || valid_at;
899 if ((dialect & ISA_V2) == 0)
900 return valid_y;
901 else
902 return valid_at;
903}
904
252b5132
RH		 905/* The BO field in a B form instruction. Warn about attempts to set
906 the field to an illegal value. */
907
908static unsigned long
2fbfdc41
AM		 909insert_bo (unsigned long insn,
910 long value,
fa452fa6 911 ppc_cpu_t dialect,
2fbfdc41 912 const char **errmsg)
252b5132 913{
ba4e851b 914 if (!valid_bo (value, dialect, 0))
252b5132 915 *errmsg = _("invalid conditional option");
989993d8
JB		 916 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
917 *errmsg = _("invalid counter access");
252b5132
RH		 918 return insn | ((value & 0x1f) << 21);
919}
920
921static long
2fbfdc41 922extract_bo (unsigned long insn,
fa452fa6 923 ppc_cpu_t dialect,
2fbfdc41 924 int *invalid)
252b5132
RH		 925{
926 long value;
927
928 value = (insn >> 21) & 0x1f;
ba4e851b 929 if (!valid_bo (value, dialect, 1))
252b5132
RH		 930 *invalid = 1;
931 return value;
932}
933
934/* The BO field in a B form instruction when the + or - modifier is
935 used. This is like the BO field, but it must be even. When
936 extracting it, we force it to be even. */
937
938static unsigned long
2fbfdc41
AM		 939insert_boe (unsigned long insn,
940 long value,
fa452fa6 941 ppc_cpu_t dialect,
2fbfdc41 942 const char **errmsg)
252b5132 943{
ba4e851b 944 if (!valid_bo (value, dialect, 0))
8427c424 945 *errmsg = _("invalid conditional option");
989993d8
JB		 946 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
947 *errmsg = _("invalid counter access");
8427c424
AM		 948 else if ((value & 1) != 0)
949 *errmsg = _("attempt to set y bit when using + or - modifier");
950
252b5132
RH		 951 return insn | ((value & 0x1f) << 21);
952}
953
954static long
2fbfdc41 955extract_boe (unsigned long insn,
fa452fa6 956 ppc_cpu_t dialect,
2fbfdc41 957 int *invalid)
252b5132
RH		 958{
959 long value;
960
961 value = (insn >> 21) & 0x1f;
ba4e851b 962 if (!valid_bo (value, dialect, 1))
252b5132
RH		 963 *invalid = 1;
964 return value & 0x1e;
965}
966
2fbfdc41
AM		 967/* FXM mask in mfcr and mtcrf instructions. */
968
969static unsigned long
970insert_fxm (unsigned long insn,
971 long value,
fa452fa6 972 ppc_cpu_t dialect,
2fbfdc41 973 const char **errmsg)
c168870a 974{
98e69875
AM		 975 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
976 one bit of the mask field is set. */
977 if ((insn & (1 << 20)) != 0)
978 {
979 if (value == 0 || (value & -value) != value)
980 {
981 *errmsg = _("invalid mask field");
982 value = 0;
983 }
984 }
985
c168870a
AM		 986 /* If the optional field on mfcr is missing that means we want to use
987 the old form of the instruction that moves the whole cr. In that
988 case we'll have VALUE zero. There doesn't seem to be a way to
989 distinguish this from the case where someone writes mfcr %r3,0. */
98e69875 990 else if (value == 0)
c168870a
AM		 991 ;
992
993 /* If only one bit of the FXM field is set, we can use the new form
661bd698 994 of the instruction, which is faster. Unlike the Power4 branch hint
a30e9cc4
AM		 995 encoding, this is not backward compatible. Do not generate the
996 new form unless -mpower4 has been given, or -many and the two
997 operand form of mfcr was used. */
998 else if ((value & -value) == value
999 && ((dialect & PPC_OPCODE_POWER4) != 0
1000 || ((dialect & PPC_OPCODE_ANY) != 0
1001 && (insn & (0x3ff << 1)) == 19 << 1)))
c168870a
AM		 1002 insn |= 1 << 20;
1003
1004 /* Any other value on mfcr is an error. */
1005 else if ((insn & (0x3ff << 1)) == 19 << 1)
1006 {
8427c424 1007 *errmsg = _("ignoring invalid mfcr mask");
c168870a
AM		 1008 value = 0;
1009 }
1010
1011 return insn | ((value & 0xff) << 12);
1012}
1013
2fbfdc41
AM		 1014static long
1015extract_fxm (unsigned long insn,
fa452fa6 1016 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1017 int *invalid)
c168870a
AM		 1018{
1019 long mask = (insn >> 12) & 0xff;
1020
1021 /* Is this a Power4 insn? */
1022 if ((insn & (1 << 20)) != 0)
1023 {
98e69875
AM		 1024 /* Exactly one bit of MASK should be set. */
1025 if (mask == 0 || (mask & -mask) != mask)
8427c424 1026 *invalid = 1;
c168870a
AM		 1027 }
1028
1029 /* Check that non-power4 form of mfcr has a zero MASK. */
1030 else if ((insn & (0x3ff << 1)) == 19 << 1)
1031 {
8427c424 1032 if (mask != 0)
c168870a
AM		 1033 *invalid = 1;
1034 }
1035
1036 return mask;
1037}
1038
252b5132
RH		 1039/* The MB and ME fields in an M form instruction expressed as a single
1040 operand which is itself a bitmask. The extraction function always
1041 marks it as invalid, since we never want to recognize an
1042 instruction which uses a field of this type. */
1043
1044static unsigned long
2fbfdc41
AM		 1045insert_mbe (unsigned long insn,
1046 long value,
fa452fa6 1047 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1048 const char **errmsg)
252b5132
RH		 1049{
1050 unsigned long uval, mask;
1051 int mb, me, mx, count, last;
1052
1053 uval = value;
1054
1055 if (uval == 0)
1056 {
8427c424 1057 *errmsg = _("illegal bitmask");
252b5132
RH		 1058 return insn;
1059 }
1060
1061 mb = 0;
1062 me = 32;
1063 if ((uval & 1) != 0)
1064 last = 1;
1065 else
1066 last = 0;
1067 count = 0;
1068
1069 /* mb: location of last 0->1 transition */
1070 /* me: location of last 1->0 transition */
1071 /* count: # transitions */
1072
0deb7ac5 1073 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
252b5132
RH		 1074 {
1075 if ((uval & mask) && !last)
1076 {
1077 ++count;
1078 mb = mx;
1079 last = 1;
1080 }
1081 else if (!(uval & mask) && last)
1082 {
1083 ++count;
1084 me = mx;
1085 last = 0;
1086 }
1087 }
1088 if (me == 0)
1089 me = 32;
1090
1091 if (count != 2 && (count != 0 || ! last))
8427c424 1092 *errmsg = _("illegal bitmask");
252b5132
RH		 1093
1094 return insn | (mb << 6) | ((me - 1) << 1);
1095}
1096
1097static long
2fbfdc41 1098extract_mbe (unsigned long insn,
fa452fa6 1099 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1100 int *invalid)
252b5132
RH		 1101{
1102 long ret;
1103 int mb, me;
1104 int i;
1105
8427c424 1106 *invalid = 1;
252b5132
RH		 1107
1108 mb = (insn >> 6) & 0x1f;
1109 me = (insn >> 1) & 0x1f;
1110 if (mb < me + 1)
1111 {
1112 ret = 0;
1113 for (i = mb; i <= me; i++)
0deb7ac5 1114 ret |= 1L << (31 - i);
252b5132
RH		 1115 }
1116 else if (mb == me + 1)
8427c424 1117 ret = ~0;
252b5132
RH		 1118 else /* (mb > me + 1) */
1119 {
2fbfdc41 1120 ret = ~0;
252b5132 1121 for (i = me + 1; i < mb; i++)
0deb7ac5 1122 ret &= ~(1L << (31 - i));
252b5132
RH		 1123 }
1124 return ret;
1125}
1126
1127/* The MB or ME field in an MD or MDS form instruction. The high bit
1128 is wrapped to the low end. */
1129
252b5132 1130static unsigned long
2fbfdc41
AM		 1131insert_mb6 (unsigned long insn,
1132 long value,
fa452fa6 1133 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1134 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1135{
1136 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1137}
1138
252b5132 1139static long
2fbfdc41 1140extract_mb6 (unsigned long insn,
fa452fa6 1141 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1142 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1143{
1144 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1145}
1146
1147/* The NB field in an X form instruction. The value 32 is stored as
1148 0. */
1149
252b5132 1150static long
2fbfdc41 1151extract_nb (unsigned long insn,
fa452fa6 1152 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1153 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1154{
1155 long ret;
1156
1157 ret = (insn >> 11) & 0x1f;
1158 if (ret == 0)
1159 ret = 32;
1160 return ret;
1161}
1162
989993d8
JB		 1163/* The NB field in an lswi instruction, which has special value
1164 restrictions. The value 32 is stored as 0. */
1165
1166static unsigned long
1167insert_nbi (unsigned long insn,
1168 long value,
1169 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1170 const char **errmsg ATTRIBUTE_UNUSED)
1171{
1172 long rtvalue = (insn & RT_MASK) >> 21;
1173 long ravalue = (insn & RA_MASK) >> 16;
1174
1175 if (value == 0)
1176 value = 32;
1177 if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32
1178 : ravalue))
1179 *errmsg = _("address register in load range");
1180 return insn | ((value & 0x1f) << 11);
1181}
1182
252b5132
RH		 1183/* The NSI field in a D form instruction. This is the same as the SI
1184 field, only negated. The extraction function always marks it as
1185 invalid, since we never want to recognize an instruction which uses
1186 a field of this type. */
1187
252b5132 1188static unsigned long
2fbfdc41
AM		 1189insert_nsi (unsigned long insn,
1190 long value,
fa452fa6 1191 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1192 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1193{
2fbfdc41 1194 return insn | (-value & 0xffff);
252b5132
RH		 1195}
1196
1197static long
2fbfdc41 1198extract_nsi (unsigned long insn,
fa452fa6 1199 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1200 int *invalid)
252b5132 1201{
8427c424 1202 *invalid = 1;
2fbfdc41 1203 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
252b5132
RH		 1204}
1205
1206/* The RA field in a D or X form instruction which is an updating
1207 load, which means that the RA field may not be zero and may not
1208 equal the RT field. */
1209
1210static unsigned long
2fbfdc41
AM		 1211insert_ral (unsigned long insn,
1212 long value,
fa452fa6 1213 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1214 const char **errmsg)
252b5132
RH		 1215{
1216 if (value == 0
1217 || (unsigned long) value == ((insn >> 21) & 0x1f))
1218 *errmsg = "invalid register operand when updating";
1219 return insn | ((value & 0x1f) << 16);
1220}
1221
1222/* The RA field in an lmw instruction, which has special value
1223 restrictions. */
1224
1225static unsigned long
2fbfdc41
AM		 1226insert_ram (unsigned long insn,
1227 long value,
fa452fa6 1228 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1229 const char **errmsg)
252b5132
RH		 1230{
1231 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1232 *errmsg = _("index register in load range");
1233 return insn | ((value & 0x1f) << 16);
1234}
1235
989993d8 1236/* The RA field in the DQ form lq or an lswx instruction, which have special
8427c424 1237 value restrictions. */
adadcc0c 1238
adadcc0c 1239static unsigned long
2fbfdc41
AM		 1240insert_raq (unsigned long insn,
1241 long value,
fa452fa6 1242 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1243 const char **errmsg)
adadcc0c
AM		 1244{
1245 long rtvalue = (insn & RT_MASK) >> 21;
1246
8427c424 1247 if (value == rtvalue)
adadcc0c
AM		 1248 *errmsg = _("source and target register operands must be different");
1249 return insn | ((value & 0x1f) << 16);
1250}
1251
252b5132
RH		 1252/* The RA field in a D or X form instruction which is an updating
1253 store or an updating floating point load, which means that the RA
1254 field may not be zero. */
1255
1256static unsigned long
2fbfdc41
AM		 1257insert_ras (unsigned long insn,
1258 long value,
fa452fa6 1259 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1260 const char **errmsg)
252b5132
RH		 1261{
1262 if (value == 0)
1263 *errmsg = _("invalid register operand when updating");
1264 return insn | ((value & 0x1f) << 16);
1265}
1266
1267/* The RB field in an X form instruction when it must be the same as
1268 the RS field in the instruction. This is used for extended
1269 mnemonics like mr. This operand is marked FAKE. The insertion
1270 function just copies the BT field into the BA field, and the
1271 extraction function just checks that the fields are the same. */
1272
252b5132 1273static unsigned long
2fbfdc41
AM		 1274insert_rbs (unsigned long insn,
1275 long value ATTRIBUTE_UNUSED,
fa452fa6 1276 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1277 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1278{
1279 return insn | (((insn >> 21) & 0x1f) << 11);
1280}
1281
1282static long
2fbfdc41 1283extract_rbs (unsigned long insn,
fa452fa6 1284 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1285 int *invalid)
252b5132 1286{
8427c424 1287 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 1288 *invalid = 1;
1289 return 0;
1290}
1291
989993d8
JB		 1292/* The RB field in an lswx instruction, which has special value
1293 restrictions. */
1294
1295static unsigned long
1296insert_rbx (unsigned long insn,
1297 long value,
1298 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1299 const char **errmsg)
1300{
1301 long rtvalue = (insn & RT_MASK) >> 21;
1302
1303 if (value == rtvalue)
1304 *errmsg = _("source and target register operands must be different");
1305 return insn | ((value & 0x1f) << 11);
1306}
1307
252b5132
RH		 1308/* The SH field in an MD form instruction. This is split. */
1309
252b5132 1310static unsigned long
2fbfdc41
AM		 1311insert_sh6 (unsigned long insn,
1312 long value,
fa452fa6 1313 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1314 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1315{
1316 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1317}
1318
252b5132 1319static long
2fbfdc41 1320extract_sh6 (unsigned long insn,
fa452fa6 1321 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1322 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1323{
1324 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1325}
1326
1327/* The SPR field in an XFX form instruction. This is flipped--the
1328 lower 5 bits are stored in the upper 5 and vice- versa. */
1329
1330static unsigned long
2fbfdc41
AM		 1331insert_spr (unsigned long insn,
1332 long value,
fa452fa6 1333 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1334 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1335{
1336 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1337}
1338
1339static long
2fbfdc41 1340extract_spr (unsigned long insn,
fa452fa6 1341 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1342 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1343{
1344 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1345}
1346
da99ee72
AM		 1347/* Some dialects have 8 SPRG registers instead of the standard 4. */
1348
1349static unsigned long
1350insert_sprg (unsigned long insn,
1351 long value,
fa452fa6 1352 ppc_cpu_t dialect,
da99ee72
AM		 1353 const char **errmsg)
1354{
da99ee72
AM		 1355 if (value > 7
1356 || (value > 3
081ba1b3 1357 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0))
da99ee72
AM		 1358 *errmsg = _("invalid sprg number");
1359
1360 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1361 user mode. Anything else must use spr 272..279. */
1362 if (value <= 3 || (insn & 0x100) != 0)
1363 value |= 0x10;
1364
1365 return insn | ((value & 0x17) << 16);
1366}
1367
1368static long
1369extract_sprg (unsigned long insn,
fa452fa6 1370 ppc_cpu_t dialect,
da99ee72
AM		 1371 int *invalid)
1372{
1373 unsigned long val = (insn >> 16) & 0x1f;
1374
1375 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1376 If not BOOKE or 405, then both use only 272..275. */
e1c93c69
AM		 1377 if ((val - 0x10 > 3 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0)
1378 || (val - 0x10 > 7 && (insn & 0x100) != 0)
1379 || val <= 3
1380 || (val & 8) != 0)
da99ee72
AM		 1381 *invalid = 1;
1382 return val & 7;
1383}
1384
252b5132
RH		 1385/* The TBR field in an XFX instruction. This is just like SPR, but it
1386 is optional. When TBR is omitted, it must be inserted as 268 (the
1387 magic number of the TB register). These functions treat 0
1388 (indicating an omitted optional operand) as 268. This means that
1389 ``mftb 4,0'' is not handled correctly. This does not matter very
1390 much, since the architecture manual does not define mftb as
1391 accepting any values other than 268 or 269. */
1392
1393#define TB (268)
1394
1395static unsigned long
2fbfdc41
AM		 1396insert_tbr (unsigned long insn,
1397 long value,
fa452fa6 1398 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1399 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1400{
1401 if (value == 0)
1402 value = TB;
1403 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1404}
1405
1406static long
2fbfdc41 1407extract_tbr (unsigned long insn,
fa452fa6 1408 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1409 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1410{
1411 long ret;
1412
1413 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1414 if (ret == TB)
1415 ret = 0;
1416 return ret;
1417}
9b4e5766
PB		 1418
1419/* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
1420
1421static unsigned long
1422insert_xt6 (unsigned long insn,
1423 long value,
1424 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1425 const char **errmsg ATTRIBUTE_UNUSED)
1426{
1427 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
1428}
1429
1430static long
1431extract_xt6 (unsigned long insn,
1432 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1433 int *invalid ATTRIBUTE_UNUSED)
1434{
1435 return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
1436}
1437
1438/* The XA field in an XX3 form instruction. This is split. */
1439
1440static unsigned long
1441insert_xa6 (unsigned long insn,
1442 long value,
1443 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1444 const char **errmsg ATTRIBUTE_UNUSED)
1445{
1446 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
1447}
1448
1449static long
1450extract_xa6 (unsigned long insn,
1451 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1452 int *invalid ATTRIBUTE_UNUSED)
1453{
1454 return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1455}
1456
1457/* The XB field in an XX3 form instruction. This is split. */
1458
1459static unsigned long
1460insert_xb6 (unsigned long insn,
1461 long value,
1462 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1463 const char **errmsg ATTRIBUTE_UNUSED)
1464{
1465 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1466}
1467
1468static long
1469extract_xb6 (unsigned long insn,
1470 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1471 int *invalid ATTRIBUTE_UNUSED)
1472{
1473 return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
1474}
1475
1476/* The XB field in an XX3 form instruction when it must be the same as
1477 the XA field in the instruction. This is used for extended
1478 mnemonics like xvmovdp. This operand is marked FAKE. The insertion
1479 function just copies the XA field into the XB field, and the
1480 extraction function just checks that the fields are the same. */
1481
1482static unsigned long
1483insert_xb6s (unsigned long insn,
1484 long value ATTRIBUTE_UNUSED,
1485 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1486 const char **errmsg ATTRIBUTE_UNUSED)
1487{
1488 return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
1489}
1490
1491static long
1492extract_xb6s (unsigned long insn,
1493 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1494 int *invalid)
1495{
1496 if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
1497 || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
1498 *invalid = 1;
1499 return 0;
1500}
066be9f7
PB		 1501
1502/* The XC field in an XX4 form instruction. This is split. */
1503
1504static unsigned long
1505insert_xc6 (unsigned long insn,
1506 long value,
1507 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1508 const char **errmsg ATTRIBUTE_UNUSED)
1509{
1510 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
1511}
1512
1513static long
1514extract_xc6 (unsigned long insn,
1515 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1516 int *invalid ATTRIBUTE_UNUSED)
1517{
1518 return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
1519}
1520
1521static unsigned long
1522insert_dm (unsigned long insn,
1523 long value,
1524 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1525 const char **errmsg)
1526{
1527 if (value != 0 && value != 1)
1528 *errmsg = _("invalid constant");
1529 return insn | (((value) ? 3 : 0) << 8);
1530}
1531
1532static long
1533extract_dm (unsigned long insn,
1534 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1535 int *invalid)
1536{
1537 long value;
1538
1539 value = (insn >> 8) & 3;
1540 if (value != 0 && value != 3)
1541 *invalid = 1;
1542 return (value) ? 1 : 0;
1543}
252b5132
RH		 1544\f
1545/* Macros used to form opcodes. */
1546
1547/* The main opcode. */
1548#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1549#define OP_MASK OP (0x3f)
1550
1551/* The main opcode combined with a trap code in the TO field of a D
1552 form instruction. Used for extended mnemonics for the trap
1553 instructions. */
1554#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1555#define OPTO_MASK (OP_MASK | TO_MASK)
1556
1557/* The main opcode combined with a comparison size bit in the L field
1558 of a D form or X form instruction. Used for extended mnemonics for
1559 the comparison instructions. */
1560#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1561#define OPL_MASK OPL (0x3f,1)
1562
1563/* An A form instruction. */
1564#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1565#define A_MASK A (0x3f, 0x1f, 1)
1566
1567/* An A_MASK with the FRB field fixed. */
1568#define AFRB_MASK (A_MASK | FRB_MASK)
1569
1570/* An A_MASK with the FRC field fixed. */
1571#define AFRC_MASK (A_MASK | FRC_MASK)
1572
1573/* An A_MASK with the FRA and FRC fields fixed. */
1574#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1575
702f0fb4
PB		 1576/* An AFRAFRC_MASK, but with L bit clear. */
1577#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1578
252b5132
RH		 1579/* A B form instruction. */
1580#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1581#define B_MASK B (0x3f, 1, 1)
1582
1583/* A B form instruction setting the BO field. */
1584#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1585#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1586
1587/* A BBO_MASK with the y bit of the BO field removed. This permits
1588 matching a conditional branch regardless of the setting of the y
94efba12 1589 bit. Similarly for the 'at' bits used for power4 branch hints. */
de866fcc 1590#define Y_MASK (((unsigned long) 1) << 21)
802a735e
AM		 1591#define AT1_MASK (((unsigned long) 3) << 21)
1592#define AT2_MASK (((unsigned long) 9) << 21)
1593#define BBOY_MASK (BBO_MASK &~ Y_MASK)
1594#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
252b5132
RH		 1595
1596/* A B form instruction setting the BO field and the condition bits of
1597 the BI field. */
1598#define BBOCB(op, bo, cb, aa, lk) \
1599 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1600#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1601
1602/* A BBOCB_MASK with the y bit of the BO field removed. */
1603#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
802a735e
AM		 1604#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1605#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
252b5132
RH		 1606
1607/* A BBOYCB_MASK in which the BI field is fixed. */
1608#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
802a735e 1609#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
252b5132 1610
23976049
EZ		 1611/* An Context form instruction. */
1612#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
fdd12ef3 1613#define CTX_MASK CTX(0x3f, 0x7)
23976049
EZ		 1614
1615/* An User Context form instruction. */
1616#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
fdd12ef3 1617#define UCTX_MASK UCTX(0x3f, 0x1f)
23976049 1618
252b5132
RH		 1619/* The main opcode mask with the RA field clear. */
1620#define DRA_MASK (OP_MASK | RA_MASK)
1621
1622/* A DS form instruction. */
1623#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1624#define DS_MASK DSO (0x3f, 3)
1625
23976049
EZ		 1626/* An EVSEL form instruction. */
1627#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1628#define EVSEL_MASK EVSEL(0x3f, 0xff)
1629
252b5132
RH		 1630/* An M form instruction. */
1631#define M(op, rc) (OP (op) | ((rc) & 1))
1632#define M_MASK M (0x3f, 1)
1633
1634/* An M form instruction with the ME field specified. */
1635#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1636
1637/* An M_MASK with the MB and ME fields fixed. */
1638#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1639
1640/* An M_MASK with the SH and ME fields fixed. */
1641#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1642
1643/* An MD form instruction. */
1644#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1645#define MD_MASK MD (0x3f, 0x7, 1)
1646
1647/* An MD_MASK with the MB field fixed. */
1648#define MDMB_MASK (MD_MASK | MB6_MASK)
1649
1650/* An MD_MASK with the SH field fixed. */
1651#define MDSH_MASK (MD_MASK | SH6_MASK)
1652
1653/* An MDS form instruction. */
1654#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1655#define MDS_MASK MDS (0x3f, 0xf, 1)
1656
1657/* An MDS_MASK with the MB field fixed. */
1658#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1659
1660/* An SC form instruction. */
1661#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1662#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1663
112290ab 1664/* An VX form instruction. */
786e2c0f
C		 1665#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1666
112290ab 1667/* The mask for an VX form instruction. */
786e2c0f
C		 1668#define VX_MASK VX(0x3f, 0x7ff)
1669
112290ab 1670/* An VA form instruction. */
2613489e 1671#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
786e2c0f 1672
112290ab 1673/* The mask for an VA form instruction. */
2613489e 1674#define VXA_MASK VXA(0x3f, 0x3f)
786e2c0f 1675
112290ab 1676/* An VXR form instruction. */
786e2c0f
C		 1677#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1678
112290ab 1679/* The mask for a VXR form instruction. */
786e2c0f
C		 1680#define VXR_MASK VXR(0x3f, 0x3ff, 1)
1681
252b5132
RH		 1682/* An X form instruction. */
1683#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1684
066be9f7
PB		 1685/* An XX2 form instruction. */
1686#define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
1687
9b4e5766
PB		 1688/* An XX3 form instruction. */
1689#define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
1690
066be9f7
PB		 1691/* An XX3 form instruction with the RC bit specified. */
1692#define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
1693
1694/* An XX4 form instruction. */
1695#define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
9b4e5766 1696
702f0fb4
PB		 1697/* A Z form instruction. */
1698#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1699
252b5132
RH		 1700/* An X form instruction with the RC bit specified. */
1701#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1702
702f0fb4
PB		 1703/* A Z form instruction with the RC bit specified. */
1704#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1705
252b5132
RH		 1706/* The mask for an X form instruction. */
1707#define X_MASK XRC (0x3f, 0x3ff, 1)
1708
e0d602ec
BE		 1709/* An X form wait instruction with everything filled in except the WC field. */
1710#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
1711
9b4e5766
PB		 1712/* The mask for an XX1 form instruction. */
1713#define XX1_MASK X (0x3f, 0x3ff)
1714
066be9f7
PB		 1715/* The mask for an XX2 form instruction. */
1716#define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
1717
1718/* The mask for an XX2 form instruction with the UIM bits specified. */
1719#define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
1720
1721/* The mask for an XX2 form instruction with the BF bits specified. */
1722#define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
1723
9b4e5766
PB		 1724/* The mask for an XX3 form instruction. */
1725#define XX3_MASK XX3 (0x3f, 0xff)
1726
066be9f7
PB		 1727/* The mask for an XX3 form instruction with the BF bits specified. */
1728#define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
1729
1730/* The mask for an XX3 form instruction with the DM or SHW bits specified. */
9b4e5766 1731#define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
066be9f7
PB		 1732#define XX3SHW_MASK XX3DM_MASK
1733
1734/* The mask for an XX4 form instruction. */
1735#define XX4_MASK XX4 (0x3f, 0x3)
1736
1737/* An X form wait instruction with everything filled in except the WC field. */
1738#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
9b4e5766 1739
702f0fb4
PB		 1740/* The mask for a Z form instruction. */
1741#define Z_MASK ZRC (0x3f, 0x1ff, 1)
0bbdef92 1742#define Z2_MASK ZRC (0x3f, 0xff, 1)
702f0fb4 1743
252b5132
RH		 1744/* An X_MASK with the RA field fixed. */
1745#define XRA_MASK (X_MASK | RA_MASK)
1746
ea192fa3
PB		 1747/* An XRA_MASK with the W field clear. */
1748#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
1749
252b5132
RH		 1750/* An X_MASK with the RB field fixed. */
1751#define XRB_MASK (X_MASK | RB_MASK)
1752
1753/* An X_MASK with the RT field fixed. */
1754#define XRT_MASK (X_MASK | RT_MASK)
1755
702f0fb4
PB		 1756/* An XRT_MASK mask with the L bits clear. */
1757#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1758
252b5132
RH		 1759/* An X_MASK with the RA and RB fields fixed. */
1760#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1761
112290ab 1762/* An XRARB_MASK, but with the L bit clear. */
5ae2e65e
AM		 1763#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1764
252b5132
RH		 1765/* An X_MASK with the RT and RA fields fixed. */
1766#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1767
98acc1c5
AM		 1768/* An XRTRA_MASK, but with L bit clear. */
1769#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1770
f3806e43
BE		 1771/* An X form instruction with the L bit specified. */
1772#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
252b5132 1773
e0d602ec
BE		 1774/* An X form instruction with the L bits specified. */
1775#define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1776
19a6653c
AM		 1777/* An X form instruction with RT fields specified */
1778#define XRT(op, xop, rt) (X ((op), (xop)) \
1779 | ((((unsigned long)(rt)) & 0x1f) << 21))
1780
1781/* An X form instruction with RT and RA fields specified */
1782#define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
1783 | ((((unsigned long)(rt)) & 0x1f) << 21) \
1784 | ((((unsigned long)(ra)) & 0x1f) << 16))
1785
252b5132
RH		 1786/* The mask for an X form comparison instruction. */
1787#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1788
520ceea4
BE		 1789/* The mask for an X form comparison instruction with the L field
1790 fixed. */
1791#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
252b5132
RH		 1792
1793/* An X form trap instruction with the TO field specified. */
1794#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1795#define XTO_MASK (X_MASK | TO_MASK)
1796
e0c21649
GK		 1797/* An X form tlb instruction with the SH field specified. */
1798#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1799#define XTLB_MASK (X_MASK | SH_MASK)
1800
6ba045b1
AM		 1801/* An X form sync instruction. */
1802#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1803
1804/* An X form sync instruction with everything filled in except the LS field. */
1805#define XSYNC_MASK (0xff9fffff)
1806
702f0fb4
PB		 1807/* An X_MASK, but with the EH bit clear. */
1808#define XEH_MASK (X_MASK & ~((unsigned long )1))
1809
f5c120c5
MG		 1810/* An X form AltiVec dss instruction. */
1811#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1812#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1813
252b5132
RH		 1814/* An XFL form instruction. */
1815#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
ea192fa3 1816#define XFL_MASK XFL (0x3f, 0x3ff, 1)
252b5132 1817
23976049 1818/* An X form isel instruction. */
de866fcc
AM		 1819#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1820#define XISEL_MASK XISEL(0x3f, 0x1f)
23976049 1821
252b5132
RH		 1822/* An XL form instruction with the LK field set to 0. */
1823#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1824
1825/* An XL form instruction which uses the LK field. */
1826#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1827
1828/* The mask for an XL form instruction. */
1829#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1830
1831/* An XL form instruction which explicitly sets the BO field. */
1832#define XLO(op, bo, xop, lk) \
1833 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1834#define XLO_MASK (XL_MASK | BO_MASK)
1835
1836/* An XL form instruction which explicitly sets the y bit of the BO
1837 field. */
1838#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1839#define XLYLK_MASK (XL_MASK | Y_MASK)
1840
1841/* An XL form instruction which sets the BO field and the condition
1842 bits of the BI field. */
1843#define XLOCB(op, bo, cb, xop, lk) \
1844 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1845#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1846
1847/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1848#define XLBB_MASK (XL_MASK | BB_MASK)
1849#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1850#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1851
d0618d1c
AM		 1852/* A mask for branch instructions using the BH field. */
1853#define XLBH_MASK (XL_MASK | (0x1c << 11))
1854
252b5132
RH		 1855/* An XL_MASK with the BO and BB fields fixed. */
1856#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1857
1858/* An XL_MASK with the BO, BI and BB fields fixed. */
1859#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1860
e01d869a
AM		 1861/* An X form mbar instruction with MO field. */
1862#define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
1863
252b5132
RH		 1864/* An XO form instruction. */
1865#define XO(op, xop, oe, rc) \
1866 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1867#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1868
1869/* An XO_MASK with the RB field fixed. */
1870#define XORB_MASK (XO_MASK | RB_MASK)
1871
c3d65c1c
BE		 1872/* An XOPS form instruction for paired singles. */
1873#define XOPS(op, xop, rc) \
1874 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1875#define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
1876
1877
252b5132
RH		 1878/* An XS form instruction. */
1879#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1880#define XS_MASK XS (0x3f, 0x1ff, 1)
1881
1882/* A mask for the FXM version of an XFX form instruction. */
98e69875 1883#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
252b5132
RH		 1884
1885/* An XFX form instruction with the FXM field filled in. */
98e69875
AM		 1886#define XFXM(op, xop, fxm, p4) \
1887 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1888 | ((unsigned long)(p4) << 20))
252b5132
RH		 1889
1890/* An XFX form instruction with the SPR field filled in. */
1891#define XSPR(op, xop, spr) \
1892 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1893#define XSPR_MASK (X_MASK | SPR_MASK)
1894
1895/* An XFX form instruction with the SPR field filled in except for the
1896 SPRBAT field. */
1897#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1898
1899/* An XFX form instruction with the SPR field filled in except for the
1900 SPRG field. */
b84bf58a 1901#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
252b5132
RH		 1902
1903/* An X form instruction with everything filled in except the E field. */
1904#define XE_MASK (0xffff7fff)
1905
23976049
EZ		 1906/* An X form user context instruction. */
1907#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1908#define XUC_MASK XUC(0x3f, 0x1f)
1909
c3d65c1c
BE		 1910/* An XW form instruction. */
1911#define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
1912/* The mask for a G form instruction. rc not supported at present. */
1913#define XW_MASK XW (0x3f, 0x3f, 0)
1914
081ba1b3
AM		 1915/* An APU form instruction. */
1916#define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
1917
1918/* The mask for an APU form instruction. */
1919#define APU_MASK APU (0x3f, 0x3ff, 1)
1920#define APU_RT_MASK (APU_MASK | RT_MASK)
1921#define APU_RA_MASK (APU_MASK | RA_MASK)
1922
252b5132
RH		 1923/* The BO encodings used in extended conditional branch mnemonics. */
1924#define BODNZF (0x0)
1925#define BODNZFP (0x1)
1926#define BODZF (0x2)
1927#define BODZFP (0x3)
252b5132
RH		 1928#define BODNZT (0x8)
1929#define BODNZTP (0x9)
1930#define BODZT (0xa)
1931#define BODZTP (0xb)
802a735e
AM		 1932
1933#define BOF (0x4)
1934#define BOFP (0x5)
94efba12
AM		 1935#define BOFM4 (0x6)
1936#define BOFP4 (0x7)
252b5132
RH		 1937#define BOT (0xc)
1938#define BOTP (0xd)
94efba12
AM		 1939#define BOTM4 (0xe)
1940#define BOTP4 (0xf)
802a735e 1941
252b5132
RH		 1942#define BODNZ (0x10)
1943#define BODNZP (0x11)
1944#define BODZ (0x12)
1945#define BODZP (0x13)
94efba12
AM		 1946#define BODNZM4 (0x18)
1947#define BODNZP4 (0x19)
1948#define BODZM4 (0x1a)
1949#define BODZP4 (0x1b)
802a735e 1950
252b5132
RH		 1951#define BOU (0x14)
1952
1953/* The BI condition bit encodings used in extended conditional branch
1954 mnemonics. */
1955#define CBLT (0)
1956#define CBGT (1)
1957#define CBEQ (2)
1958#define CBSO (3)
1959
1960/* The TO encodings used in extended trap mnemonics. */
1961#define TOLGT (0x1)
1962#define TOLLT (0x2)
1963#define TOEQ (0x4)
1964#define TOLGE (0x5)
1965#define TOLNL (0x5)
1966#define TOLLE (0x6)
1967#define TOLNG (0x6)
1968#define TOGT (0x8)
1969#define TOGE (0xc)
1970#define TONL (0xc)
1971#define TOLT (0x10)
1972#define TOLE (0x14)
1973#define TONG (0x14)
1974#define TONE (0x18)
1975#define TOU (0x1f)
1976\f
1977/* Smaller names for the flags so each entry in the opcodes table will
1978 fit on a single line. */
1cb0a767 1979#define PPCNONE 0
252b5132 1980#undef PPC
de866fcc 1981#define PPC PPC_OPCODE_PPC
661bd698 1982#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
661bd698 1983#define POWER4 PPC_OPCODE_POWER4
1ed8e1e4 1984#define POWER5 PPC_OPCODE_POWER5
702f0fb4 1985#define POWER6 PPC_OPCODE_POWER6
066be9f7 1986#define POWER7 PPC_OPCODE_POWER7
ede602d7 1987#define CELL PPC_OPCODE_CELL
bdc70b4a 1988#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
6b069ee7 1989#define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
bdc70b4a 1990 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
418c1742 1991#define PPC403 PPC_OPCODE_403
081ba1b3 1992#define PPC405 PPC_OPCODE_405
7d5b217e 1993#define PPC440 PPC_OPCODE_440
c8187e15 1994#define PPC464 PPC440
9fe54b1c 1995#define PPC476 PPC_OPCODE_476
252b5132 1996#define PPC750 PPC
33e8d5ac 1997#define PPC7450 PPC
252b5132 1998#define PPC860 PPC
c3d65c1c 1999#define PPCPS PPC_OPCODE_PPCPS
a404d431 2000#define PPCVEC PPC_OPCODE_ALTIVEC
9b4e5766 2001#define PPCVSX PPC_OPCODE_VSX
de866fcc
AM		 2002#define POWER PPC_OPCODE_POWER
2003#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
81a0b7e2
AM		 2004#define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2005#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
de866fcc 2006#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
de866fcc 2007#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
661bd698 2008#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
de866fcc 2009#define MFDEC1 PPC_OPCODE_POWER
bdc70b4a 2010#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
418c1742 2011#define BOOKE PPC_OPCODE_BOOKE
6b069ee7 2012#define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_EFS
36ae0db3 2013#define PPCE300 PPC_OPCODE_E300
23976049 2014#define PPCSPE PPC_OPCODE_SPE
de866fcc 2015#define PPCISEL PPC_OPCODE_ISEL
23976049 2016#define PPCEFS PPC_OPCODE_EFS
de866fcc 2017#define PPCBRLK PPC_OPCODE_BRLOCK
23976049 2018#define PPCPMR PPC_OPCODE_PMR
de866fcc 2019#define PPCCHLK PPC_OPCODE_CACHELCK
23976049 2020#define PPCRFMCI PPC_OPCODE_RFMCI
19a6653c 2021#define E500MC PPC_OPCODE_E500MC
634b50f2 2022#define PPCA2 PPC_OPCODE_A2
ce3d2015
AM		 2023#define TITAN PPC_OPCODE_TITAN
2024#define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
e01d869a 2025#define E500 PPC_OPCODE_E500
252b5132
RH		 2026\f
2027/* The opcode table.
2028
2029 The format of the opcode table is:
2030
8ebac3aa 2031 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
252b5132
RH		 2032
2033 NAME is the name of the instruction.
2034 OPCODE is the instruction opcode.
2035 MASK is the opcode mask; this is used to tell the disassembler
2036 which bits in the actual opcode must match OPCODE.
8ebac3aa
AM		 2037 FLAGS are flags indicating which processors support the instruction.
2038 ANTI indicates which processors don't support the instruction.
252b5132
RH		 2039 OPERANDS is the list of operands.
2040
2041 The disassembler reads the table in order and prints the first
2042 instruction which matches, so this table is sorted to put more
de866fcc
AM		 2043 specific instructions before more general instructions.
2044
2045 This table must be sorted by major opcode. Please try to keep it
2046 vaguely sorted within major opcode too, except of course where
2047 constrained otherwise by disassembler operation. */
252b5132
RH		 2048
2049const struct powerpc_opcode powerpc_opcodes[] = {
9fe54b1c 2050{"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476, {0}},
1cb0a767
PB		 2051{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2052{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2053{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2054{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2055{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2056{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2057{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2058{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2059{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2060{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2061{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2062{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2063{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2064{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2065{"tdi", OP(2), OP_MASK, PPC64, PPCNONE, {TO, RA, SI}},
2066
2067{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2068{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2069{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2070{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2071{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2072{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2073{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2074{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2075{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2076{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2077{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2078{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2079{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2080{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2081{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2082{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2083{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2084{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2085{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2086{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2087{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2088{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2089{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2090{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2091{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2092{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2093{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2094{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2095{"twi", OP(3), OP_MASK, PPCCOM, PPCNONE, {TO, RA, SI}},
2096{"ti", OP(3), OP_MASK, PWRCOM, PPCNONE, {TO, RA, SI}},
2097
2098{"ps_cmpu0", X (4, 0), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
2099{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2100{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2101{"vrlb", VX (4, 4), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2102{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2103{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2104{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2105{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}},
2106{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2107{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, PPCNONE, {FRS,RA,RB,PSWM,PSQM}},
2108{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
ce3d2015
AM		 2109{"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2110{"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2111{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2112{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2113{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2114{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2115{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
ce3d2015 2116{"machhwu", XO (4, 12,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767 2117{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
ce3d2015 2118{"machhwu.", XO (4, 12,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2119{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
2120{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
2121{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2122{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2123{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2124{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2125{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
2126{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
2127{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
2128{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2129{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
2130{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2131{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
2132{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
2133{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
2134{"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2135{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
2136{"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2137{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
2138{"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2139{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
2140{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2141{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
2142{"vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, SHB}},
2143{"ps_sel", A (4, 23,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2144{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VC, VB}},
2145{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2146{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VC, VB}},
2147{"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2148{"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2149{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
2150{"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
2151{"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2152{"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2153{"ps_msub", A (4, 28,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2154{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2155{"ps_madd", A (4, 29,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2156{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2157{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2158{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2159{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2160{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2161{"ps_cmpo0", X (4, 32), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
2162{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2163{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2164{"vrlh", VX (4, 68), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2165{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2166{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2167{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2168{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}},
2169{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2170{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, PPCNONE, {FRS,RA,RB,PSWM,PSQM}},
2171{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2172{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
ce3d2015 2173{"mulhhw", XRC(4, 40,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767 2174{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
ce3d2015
AM		 2175{"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2176{"machhw", XO (4, 44,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2177{"machhw.", XO (4, 44,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2178{"nmachhw", XO (4, 46,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2179{"nmachhw.", XO (4, 46,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2180{"ps_cmpu1", X (4, 64), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
2181{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2182{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2183{"vrlw", VX (4, 132), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2184{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2185{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2186{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2187{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2188{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
ce3d2015
AM		 2189{"machhwsu", XO (4, 76,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2190{"machhwsu.", XO (4, 76,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2191{"ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
2192{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2193{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
ce3d2015
AM		 2194{"machhws", XO (4, 108,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2195{"machhws.", XO (4, 108,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2196{"nmachhws", XO (4, 110,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2197{"nmachhws.", XO (4, 110,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2198{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2199{"vslb", VX (4, 260), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2200{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2201{"vrefp", VX (4, 266), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2202{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2203{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2204{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
ce3d2015 2205{"mulchwu", XRC(4, 136,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767 2206{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
ce3d2015
AM		 2207{"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2208{"macchwu", XO (4, 140,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2209{"macchwu.", XO (4, 140,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2210{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2211{"vslh", VX (4, 324), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2212{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2213{"vrsqrtefp", VX (4, 330), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2214{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2215{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
ce3d2015
AM		 2216{"mulchw", XRC(4, 168,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2217{"mulchw.", XRC(4, 168,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2218{"macchw", XO (4, 172,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2219{"macchw.", XO (4, 172,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2220{"nmacchw", XO (4, 174,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2221{"nmacchw.", XO (4, 174,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2222{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2223{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2224{"vslw", VX (4, 388), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2225{"vexptefp", VX (4, 394), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2226{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2227{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
ce3d2015
AM		 2228{"macchwsu", XO (4, 204,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2229{"macchwsu.", XO (4, 204,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2230{"vsl", VX (4, 452), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2231{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2232{"vlogefp", VX (4, 458), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2233{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
ce3d2015
AM		 2234{"macchws", XO (4, 236,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2235{"macchws.", XO (4, 236,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2236{"nmacchws", XO (4, 238,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2237{"nmacchws.", XO (4, 238,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2238{"evaddw", VX (4, 512), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2239{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2240{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, PPCNONE, {RS, RB, UIMM}},
2241{"vminub", VX (4, 514), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2242{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2243{"evsubw", VX (4, 516), VX_MASK, PPCSPE, PPCNONE, {RS, RB, RA}},
2244{"vsrb", VX (4, 516), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2245{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, PPCNONE, {RS, UIMM, RB}},
2246{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, PPCNONE, {RS, RB, UIMM}},
2247{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2248{"evabs", VX (4, 520), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2249{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2250{"evneg", VX (4, 521), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2251{"evextsb", VX (4, 522), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2252{"vrfin", VX (4, 522), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2253{"evextsh", VX (4, 523), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2254{"evrndw", VX (4, 524), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2255{"vspltb", VX (4, 524), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
2256{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2257{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2258{"vupkhsb", VX (4, 526), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2259{"brinc", VX (4, 527), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2260{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2261{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2262{"evand", VX (4, 529), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2263{"evandc", VX (4, 530), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2264{"evxor", VX (4, 534), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2265{"evmr", VX (4, 535), VX_MASK, PPCSPE, PPCNONE, {RS, RA, BBA}},
2266{"evor", VX (4, 535), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2267{"evnor", VX (4, 536), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2268{"evnot", VX (4, 536), VX_MASK, PPCSPE, PPCNONE, {RS, RA, BBA}},
2269{"get", APU(4, 268,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
2270{"eveqv", VX (4, 537), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2271{"evorc", VX (4, 539), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2272{"evnand", VX (4, 542), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2273{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2274{"evsrws", VX (4, 545), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2275{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}},
2276{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}},
2277{"evslw", VX (4, 548), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2278{"evslwi", VX (4, 550), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}},
2279{"evrlw", VX (4, 552), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2280{"evsplati", VX (4, 553), VX_MASK, PPCSPE, PPCNONE, {RS, SIMM}},
2281{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}},
2282{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, PPCNONE, {RS, SIMM}},
2283{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2284{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2285{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2286{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2287{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2288{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2289{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2290{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2291{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2292{"cget", APU(4, 284,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
2293{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2294{"vminuh", VX (4, 578), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2295{"vsrh", VX (4, 580), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2296{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2297{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2298{"vrfiz", VX (4, 586), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2299{"vsplth", VX (4, 588), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
2300{"vupkhsh", VX (4, 590), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2301{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
2302{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, PPCNONE, {RS, RA, RB, CRFS}},
2303{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
2304{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2305{"vadduws", VX (4, 640), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2306{"evfssub", VX (4, 641), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2307{"vminuw", VX (4, 642), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2308{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2309{"vsrw", VX (4, 644), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2310{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2311{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2312{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2313{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2314{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2315{"vrfip", VX (4, 650), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2316{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2317{"vspltw", VX (4, 652), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
2318{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2319{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2320{"vupklsb", VX (4, 654), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2321{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2322{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2323{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2324{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2325{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2326{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2327{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2328{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2329{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2330{"put", APU(4, 332,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
2331{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2332{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2333{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2334{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2335{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
2336{"efsadd", VX (4, 704), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2337{"efssub", VX (4, 705), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2338{"efsabs", VX (4, 708), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
2339{"vsr", VX (4, 708), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2340{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
2341{"efsneg", VX (4, 710), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
2342{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2343{"efsmul", VX (4, 712), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2344{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2345{"vrfim", VX (4, 714), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2346{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2347{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2348{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2349{"vupklsh", VX (4, 718), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2350{"efscfd", VX (4, 719), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2351{"efscfui", VX (4, 720), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2352{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2353{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2354{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2355{"efsctui", VX (4, 724), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2356{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2357{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2358{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2359{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2360{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
2361{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2362{"efststgt", VX (4, 732), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2363{"efststlt", VX (4, 733), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2364{"efststeq", VX (4, 734), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2365{"efdadd", VX (4, 736), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2366{"efdsub", VX (4, 737), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2367{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2368{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2369{"efdabs", VX (4, 740), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
2370{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
2371{"efdneg", VX (4, 742), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
2372{"efdmul", VX (4, 744), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2373{"efddiv", VX (4, 745), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2374{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2375{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2376{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2377{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2378{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2379{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2380{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2381{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2382{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2383{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2384{"efdctui", VX (4, 756), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2385{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2386{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2387{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2388{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2389{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
2390{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2391{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2392{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2393{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2394{"evlddx", VX (4, 768), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2395{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2396{"evldd", VX (4, 769), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
2397{"evldwx", VX (4, 770), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2398{"vminsb", VX (4, 770), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2399{"evldw", VX (4, 771), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
2400{"evldhx", VX (4, 772), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2401{"vsrab", VX (4, 772), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2402{"evldh", VX (4, 773), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
2403{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2404{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2405{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2406{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}},
2407{"vcfux", VX (4, 778), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
2408{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2409{"vspltisb", VX (4, 780), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}},
2410{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}},
2411{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2412{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2413{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}},
ce3d2015 2414{"mullhwu", XRC(4, 392,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767 2415{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015 2416{"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2417{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2418{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2419{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2420{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2421{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
ce3d2015 2422{"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767 2423{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015 2424{"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2425{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2426{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2427{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2428{"evstddx", VX (4, 800), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2429{"evstdd", VX (4, 801), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
2430{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2431{"evstdw", VX (4, 803), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
2432{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2433{"evstdh", VX (4, 805), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
2434{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2435{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2436{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2437{"evstwho", VX (4, 821), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2438{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2439{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2440{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2441{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2442{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2443{"vminsh", VX (4, 834), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2444{"vsrah", VX (4, 836), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2445{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2446{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2447{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
2448{"vspltish", VX (4, 844), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}},
2449{"vupkhpx", VX (4, 846), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
ce3d2015
AM		 2450{"mullhw", XRC(4, 424,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2451{"mullhw.", XRC(4, 424,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2452{"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2453{"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2454{"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2455{"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2456{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2457{"vminsw", VX (4, 898), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2458{"vsraw", VX (4, 900), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2459{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2460{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
2461{"vspltisw", VX (4, 908), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}},
ce3d2015
AM		 2462{"maclhwsu", XO (4, 460,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2463{"maclhwsu.", XO (4, 460,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2464{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2465{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
2466{"vupklpx", VX (4, 974), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
ce3d2015
AM		 2467{"maclhws", XO (4, 492,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2468{"maclhws.", XO (4, 492,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2469{"nmaclhws", XO (4, 494,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2470{"nmaclhws.", XO (4, 494,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2471{"vsububm", VX (4,1024), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2472{"vavgub", VX (4,1026), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2473{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2474{"vand", VX (4,1028), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2475{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2476{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2477{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
1cb0a767
PB		 2478{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2479{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2480{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2481{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2482{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2483{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2484{"vslo", VX (4,1036), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2485{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2486{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015
AM		 2487{"machhwuo", XO (4, 12,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2488{"machhwuo.", XO (4, 12,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2489{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2490{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2491{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2492{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2493{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2494{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2495{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2496{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2497{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2498{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2499{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2500{"vavguh", VX (4,1090), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2501{"vandc", VX (4,1092), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2502{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2503{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2504{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
1cb0a767
PB		 2505{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2506{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2507{"vminfp", VX (4,1098), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2508{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2509{"vsro", VX (4,1100), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2510{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2511{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2512{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015 2513{"machhwo", XO (4, 44,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767 2514{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015 2515{"machhwo.", XO (4, 44,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2516{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2517{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015
AM		 2518{"nmachhwo", XO (4, 46,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2519{"nmachhwo.", XO (4, 46,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2520{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2521{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2522{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2523{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2524{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2525{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2526{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2527{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2528{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2529{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2530{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2531{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2532{"vavguw", VX (4,1154), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2533{"vor", VX (4,1156), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2534{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2535{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2536{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
ce3d2015
AM		 2537{"machhwsuo", XO (4, 76,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2538{"machhwsuo.", XO (4, 76,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2539{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2540{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2541{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2542{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2543{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2544{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2545{"evmra", VX (4,1220), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2546{"vxor", VX (4,1220), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2547{"evdivws", VX (4,1222), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2548{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2549{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2550{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
1cb0a767
PB		 2551{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2552{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2553{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2554{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2555{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
ce3d2015
AM		 2556{"machhwso", XO (4, 108,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2557{"machhwso.", XO (4, 108,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2558{"nmachhwso", XO (4, 110,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2559{"nmachhwso.", XO (4, 110,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2560{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2561{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2562{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2563{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2564{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2565{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2566{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2567{"vnor", VX (4,1284), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2568{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
9fe54b1c
PB		 2569{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2570{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
1cb0a767
PB		 2571{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2572{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2573{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2574{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2575{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2576{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2577{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015
AM		 2578{"macchwuo", XO (4, 140,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2579{"macchwuo.", XO (4, 140,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2580{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2581{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2582{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2583{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2584{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2585{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2586{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2587{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2588{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2589{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2590{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
1cb0a767
PB		 2591{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2592{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2593{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015 2594{"macchwo", XO (4, 172,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767 2595{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015 2596{"macchwo.", XO (4, 172,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2597{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2598{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015
AM		 2599{"nmacchwo", XO (4, 174,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2600{"nmacchwo.", XO (4, 174,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2601{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2602{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2603{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2604{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2605{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2606{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2607{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
9fe54b1c
PB		 2608{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2609{"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
1cb0a767
PB		 2610{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2611{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2612{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2613{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2614{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2615{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2616{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015
AM		 2617{"macchwsuo", XO (4, 204,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2618{"macchwsuo.", XO (4, 204,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2619{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2620{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2621{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2622{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2623{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2624{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2625{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2626{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2627{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2628{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2629{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
1cb0a767
PB		 2630{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2631{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2632{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015 2633{"macchwso", XO (4, 236,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767 2634{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015 2635{"macchwso.", XO (4, 236,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2636{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2637{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
ce3d2015
AM		 2638{"nmacchwso", XO (4, 238,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2639{"nmacchwso.", XO (4, 238,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2640{"vsububs", VX (4,1536), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2641{"mfvscr", VX (4,1540), VX_MASK, PPCVEC, PPCNONE, {VD}},
2642{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2643{"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2644{"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
1cb0a767
PB		 2645{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2646{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2647{"mtvscr", VX (4,1604), VX_MASK, PPCVEC, PPCNONE, {VB}},
2648{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2649{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2650{"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2651{"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
1cb0a767
PB		 2652{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2653{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2654{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2655{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
1cb0a767
PB		 2656{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2657{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2658{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2659{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
1cb0a767
PB		 2660{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2661{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2662{"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2663{"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
1cb0a767 2664{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
ce3d2015
AM		 2665{"maclhwuo", XO (4, 396,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2666{"maclhwuo.", XO (4, 396,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2667{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2668{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2669{"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2670{"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
ce3d2015
AM		 2671{"maclhwo", XO (4, 428,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2672{"maclhwo.", XO (4, 428,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2673{"nmaclhwo", XO (4, 430,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2674{"nmaclhwo.", XO (4, 430,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2675{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2676{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2677{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2678{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
1cb0a767 2679{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
ce3d2015
AM		 2680{"maclhwsuo", XO (4, 460,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2681{"maclhwsuo.", XO (4, 460,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767 2682{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
9fe54b1c
PB		 2683{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2684{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
ce3d2015
AM		 2685{"maclhwso", XO (4, 492,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2686{"maclhwso.", XO (4, 492,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2687{"nmaclhwso", XO (4, 494,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
2688{"nmaclhwso.", XO (4, 494,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 2689{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, PPCNONE, {RA, RB}},
2690
2691{"mulli", OP(7), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
2692{"muli", OP(7), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
2693
2694{"subfic", OP(8), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
2695{"sfi", OP(8), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
2696
2697{"dozi", OP(9), OP_MASK, M601, PPCNONE, {RT, RA, SI}},
2698
2699{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, UI}},
2700{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, UI}},
2701{"cmpli", OP(10), OP_MASK, PPC, PPCNONE, {BF, L, RA, UI}},
bdc70b4a 2702{"cmpli", OP(10), OP_MASK, PWRCOM, PPC, {BF, RA, UI}},
1cb0a767
PB		 2703
2704{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, SI}},
2705{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, SI}},
2706{"cmpi", OP(11), OP_MASK, PPC, PPCNONE, {BF, L, RA, SI}},
bdc70b4a 2707{"cmpi", OP(11), OP_MASK, PWRCOM, PPC, {BF, RA, SI}},
1cb0a767
PB		 2708
2709{"addic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
2710{"ai", OP(12), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
2711{"subic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, NSI}},
2712
2713{"addic.", OP(13), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
2714{"ai.", OP(13), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
2715{"subic.", OP(13), OP_MASK, PPCCOM, PPCNONE, {RT, RA, NSI}},
2716
2717{"li", OP(14), DRA_MASK, PPCCOM, PPCNONE, {RT, SI}},
2718{"lil", OP(14), DRA_MASK, PWRCOM, PPCNONE, {RT, SI}},
2719{"addi", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SI}},
2720{"cal", OP(14), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
2721{"subi", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSI}},
2722{"la", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, D, RA0}},
2723
2724{"lis", OP(15), DRA_MASK, PPCCOM, PPCNONE, {RT, SISIGNOPT}},
2725{"liu", OP(15), DRA_MASK, PWRCOM, PPCNONE, {RT, SISIGNOPT}},
2726{"addis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SISIGNOPT}},
2727{"cau", OP(15), OP_MASK, PWRCOM, PPCNONE, {RT, RA0, SISIGNOPT}},
2728{"subis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSI}},
2729
2730{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
2731{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
2732{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BD}},
2733{"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCNONE, {BD}},
2734{"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
2735{"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
2736{"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BD}},
2737{"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCNONE, {BD}},
2738{"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
2739{"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
2740{"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDA}},
2741{"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCNONE, {BDA}},
2742{"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
2743{"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
2744{"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDA}},
2745{"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCNONE, {BDA}},
2746{"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
2747{"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
2748{"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCNONE, {BD}},
2749{"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
2750{"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
2751{"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCNONE, {BD}},
2752{"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
2753{"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
2754{"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCNONE, {BDA}},
2755{"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
2756{"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
2757{"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCNONE, {BDA}},
2758
2759{"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2760{"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2761{"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2762{"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2763{"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2764{"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2765{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2766{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2767{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2768{"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2769{"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2770{"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2771{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2772{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2773{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2774{"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2775{"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2776{"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2777{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2778{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2779{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2780{"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2781{"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2782{"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2783{"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2784{"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2785{"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2786{"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2787{"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2788{"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2789{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2790{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2791{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2792{"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2793{"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2794{"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2795{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2796{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2797{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2798{"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2799{"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2800{"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2801{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2802{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2803{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2804{"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2805{"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2806{"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2807{"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2808{"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2809{"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2810{"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2811{"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2812{"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2813{"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2814{"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2815{"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2816{"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2817{"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2818{"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2819{"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2820{"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2821{"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2822{"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2823{"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2824{"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
2825{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2826{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2827{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2828{"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2829{"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2830{"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
2831{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2832{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2833{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2834{"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2835{"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2836{"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
2837{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2838{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2839{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2840{"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2841{"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2842{"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
2843
2844{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2845{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2846{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2847{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2848{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2849{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2850{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2851{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2852{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2853{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2854{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2855{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2856{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2857{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2858{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2859{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2860{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2861{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2862{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2863{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2864{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2865{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2866{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2867{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2868{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2869{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2870{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2871{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2872{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2873{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2874{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2875{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2876{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2877{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2878{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2879{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2880{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2881{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2882{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2883{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2884{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2885{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
2886{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2887{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2888{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2889{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2890{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2891{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
2892{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2893{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2894{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2895{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2896{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2897{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
2898{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2899{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2900{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2901{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2902{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2903{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
2904
8ebac3aa
AM		 2905{"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
2906{"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
1cb0a767 2907{"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
8ebac3aa
AM		 2908{"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
2909{"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
1cb0a767 2910{"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
8ebac3aa
AM		 2911{"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
2912{"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
1cb0a767 2913{"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
8ebac3aa
AM		 2914{"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
2915{"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
1cb0a767 2916{"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
8ebac3aa
AM		 2917{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
2918{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
1cb0a767 2919{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
8ebac3aa
AM		 2920{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
2921{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
1cb0a767 2922{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
8ebac3aa
AM		 2923{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
2924{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
1cb0a767 2925{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
8ebac3aa
AM		 2926{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
2927{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
1cb0a767
PB		 2928{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
2929
2930{"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
2931{"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
2932{"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
2933{"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
2934{"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
2935{"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
2936{"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
2937{"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
2938{"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
2939{"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
2940{"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
2941{"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
2942{"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
2943{"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
2944{"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
2945{"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
2946
8ebac3aa
AM		 2947{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
2948{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
1cb0a767 2949{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
8ebac3aa
AM		 2950{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
2951{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
1cb0a767 2952{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
8ebac3aa
AM		 2953{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
2954{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
1cb0a767 2955{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
8ebac3aa
AM		 2956{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
2957{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
1cb0a767 2958{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
8ebac3aa
AM		 2959{"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
2960{"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
1cb0a767 2961{"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
8ebac3aa
AM		 2962{"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
2963{"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
1cb0a767 2964{"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
8ebac3aa
AM		 2965{"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
2966{"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
1cb0a767 2967{"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
8ebac3aa
AM		 2968{"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
2969{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
1cb0a767
PB		 2970{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
2971
2972{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
2973{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
2974{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
2975{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
2976{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
2977{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
2978{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
2979{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
2980{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
2981{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
2982{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
2983{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
2984{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
2985{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
2986{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
2987{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
2988
2989{"bc-", B(16,0,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDM}},
2990{"bc+", B(16,0,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDP}},
2991{"bc", B(16,0,0), B_MASK, COM, PPCNONE, {BO, BI, BD}},
2992{"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDM}},
2993{"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDP}},
2994{"bcl", B(16,0,1), B_MASK, COM, PPCNONE, {BO, BI, BD}},
2995{"bca-", B(16,1,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDMA}},
2996{"bca+", B(16,1,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDPA}},
2997{"bca", B(16,1,0), B_MASK, COM, PPCNONE, {BO, BI, BDA}},
2998{"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDMA}},
2999{"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDPA}},
3000{"bcla", B(16,1,1), B_MASK, COM, PPCNONE, {BO, BI, BDA}},
3001
3002{"svc", SC(17,0,0), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}},
3003{"svcl", SC(17,0,1), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}},
3004{"sc", SC(17,1,0), SC_MASK, PPC, PPCNONE, {LEV}},
3005{"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCNONE, {SV}},
3006{"svcla", SC(17,1,1), SC_MASK, POWER, PPCNONE, {SV}},
3007
3008{"b", B(18,0,0), B_MASK, COM, PPCNONE, {LI}},
3009{"bl", B(18,0,1), B_MASK, COM, PPCNONE, {LI}},
3010{"ba", B(18,1,0), B_MASK, COM, PPCNONE, {LIA}},
3011{"bla", B(18,1,1), B_MASK, COM, PPCNONE, {LIA}},
3012
3013{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}},
3014
3015{"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
8ebac3aa 3016{"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
1cb0a767 3017{"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
8ebac3aa
AM		 3018{"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
3019{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
3020{"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
1cb0a767 3021{"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
8ebac3aa 3022{"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
1cb0a767 3023{"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
8ebac3aa
AM		 3024{"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
3025{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
3026{"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
1cb0a767
PB		 3027{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
3028{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCNONE, {0}},
3029{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
3030{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCNONE, {0}},
8ebac3aa
AM		 3031{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
3032{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
3033{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
3034{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
3035{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
3036{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
3037{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
3038{"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
1cb0a767
PB		 3039
3040{"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3041{"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3042{"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3043{"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3044{"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3045{"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3046{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3047{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3048{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3049{"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3050{"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3051{"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3052{"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3053{"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3054{"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3055{"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3056{"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3057{"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3058{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3059{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3060{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3061{"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3062{"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3063{"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3064{"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3065{"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3066{"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3067{"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3068{"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3069{"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3070{"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3071{"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3072{"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3073{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3074{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3075{"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3076{"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3077{"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3078{"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa
AM		 3079{"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3080{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3081{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3082{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3083{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3084{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3085{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3086{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3087{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3088{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3089{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3090{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3091{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3092{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3093{"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3094{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3095{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3096{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3097{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3098{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3099{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3100{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3101{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3102{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3103{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3104{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3105{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3106{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3107{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3108{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3109{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3110{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3111{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3112{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3113{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3114{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3115{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3116{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3117{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3118{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3119{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3120{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3121{"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
1cb0a767 3122{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3123{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3124{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3125{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3126{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3127{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3128{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3129{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3130{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3131{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3132{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3133{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3134{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3135{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3136{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3137{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3138{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3139{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3140{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3141{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3142{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3143{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3144{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3145{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3146{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767
PB		 3147{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3148{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa
AM		 3149{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3150{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3151{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3152{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3153{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3154{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3155{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3156{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3157{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3158{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3159{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3160{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3161{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3162{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3163{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3164{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3165{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3166{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3167{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3168{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3169{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3170{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3171{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3172{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3173{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3174{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3175{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3176{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3177{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3178{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3179{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
1cb0a767
PB		 3180
3181{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa 3182{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3183{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa
AM		 3184{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3185{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3186{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3187{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa 3188{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3189{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa
AM		 3190{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3191{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3192{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3193{"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa 3194{"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767
PB		 3195{"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
3196{"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa 3197{"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3198{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
8ebac3aa
AM		 3199{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3200{"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3201{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3202{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3203{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3204{"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
1cb0a767 3205{"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa 3206{"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3207{"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa
AM		 3208{"bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3209{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3210{"bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3211{"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa 3212{"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3213{"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa
AM		 3214{"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3215{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3216{"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3217{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa 3218{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767
PB		 3219{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
3220{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa 3221{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3222{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
8ebac3aa
AM		 3223{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3224{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3225{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3226{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3227{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3228{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
1cb0a767
PB		 3229
3230{"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3231{"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3232{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3233{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3234{"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
3235{"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
3236{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
3237{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
3238
3239{"rfid", XL(19,18), 0xffffffff, PPC64, PPCNONE, {0}},
3240
3241{"crnot", XL(19,33), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}},
3242{"crnor", XL(19,33), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
9fe54b1c 3243{"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCNONE, {0}},
1cb0a767
PB		 3244
3245{"rfdi", XL(19,39), 0xffffffff, E500MC, PPCNONE, {0}},
3246{"rfi", XL(19,50), 0xffffffff, COM, PPCNONE, {0}},
9fe54b1c 3247{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {0}},
1cb0a767
PB		 3248
3249{"rfsvc", XL(19,82), 0xffffffff, POWER, PPCNONE, {0}},
3250
e0d602ec 3251{"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}},
1cb0a767
PB		 3252
3253{"crandc", XL(19,129), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3254
3255{"isync", XL(19,150), 0xffffffff, PPCCOM, PPCNONE, {0}},
3256{"ics", XL(19,150), 0xffffffff, PWRCOM, PPCNONE, {0}},
3257
3258{"crclr", XL(19,193), XL_MASK, PPCCOM, PPCNONE, {BT, BAT, BBA}},
3259{"crxor", XL(19,193), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3260
3261{"dnh", X(19,198), X_MASK, E500MC, PPCNONE, {DUI, DUIS}},
3262
3263{"crnand", XL(19,225), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3264
3265{"crand", XL(19,257), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3266
9fe54b1c 3267{"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476, {0}},
1cb0a767
PB		 3268
3269{"crset", XL(19,289), XL_MASK, PPCCOM, PPCNONE, {BT, BAT, BBA}},
3270{"creqv", XL(19,289), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3271
3272{"doze", XL(19,402), 0xffffffff, POWER6, PPCNONE, {0}},
3273
3274{"crorc", XL(19,417), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3275
3276{"nap", XL(19,434), 0xffffffff, POWER6, PPCNONE, {0}},
3277
3278{"crmove", XL(19,449), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}},
3279{"cror", XL(19,449), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3280
3281{"sleep", XL(19,466), 0xffffffff, POWER6, PPCNONE, {0}},
3282{"rvwinkle", XL(19,498), 0xffffffff, POWER6, PPCNONE, {0}},
3283
3284{"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCNONE, {0}},
3285{"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCNONE, {0}},
3286
3287{"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3288{"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3289{"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3290{"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3291{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3292{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3293{"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3294{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3295{"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3296{"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3297{"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3298{"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3299{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3300{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3301{"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3302{"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3303{"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3304{"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3305{"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3306{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3307{"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3308{"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3309{"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3310{"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3311{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3312{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3313{"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa
AM		 3314{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3315{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3316{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3317{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3318{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3319{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3320{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3321{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3322{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3323{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3324{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3325{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3326{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3327{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3328{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3329{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3330{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3331{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3332{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3333{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3334{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3335{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3336{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3337{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3338{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3339{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3340{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3341{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3342{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3343{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3344{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3345{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3346{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3347{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3348{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3349{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3350{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3351{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3352{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3353{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3354{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3355{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3356{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
1cb0a767 3357{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3358{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3359{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3360{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3361{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3362{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3363{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3364{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3365{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3366{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3367{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3368{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3369{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3370{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3371{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3372{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3373{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa 3374{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
1cb0a767 3375{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
8ebac3aa
AM		 3376{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3377{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3378{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3379{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3380{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3381{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3382{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3383{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3384{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3385{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3386{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3387{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3388{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3389{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3390{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3391{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3392{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3393{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3394{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3395{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3396{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3397{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3398{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3399{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3400{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3401{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3402{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3403{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3404{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3405{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3406{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
1cb0a767
PB		 3407
3408{"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa 3409{"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3410{"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa
AM		 3411{"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3412{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3413{"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3414{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3415{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3416{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3417{"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
1cb0a767 3418{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa 3419{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
1cb0a767 3420{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
8ebac3aa
AM		 3421{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3422{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3423{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3424{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3425{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3426{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3427{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
1cb0a767
PB		 3428
3429{"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3430{"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3431{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3432{"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3433{"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
3434{"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
3435{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
3436{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
3437
3438{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3439{"rlimi", M(20,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3440
3441{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3442{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3443
3444{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, SH}},
3445{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}},
3446{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3447{"rlinm", M(21,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3448{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, SH}},
3449{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}},
3450{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3451{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3452
3453{"rlmi", M(22,0), M_MASK, M601, PPCNONE, {RA, RS, RB, MBE, ME}},
3454{"rlmi.", M(22,1), M_MASK, M601, PPCNONE, {RA, RS, RB, MBE, ME}},
3455
3456{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
3457{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
3458{"rlnm", M(23,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
3459{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
3460{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
3461{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
3462
3463{"nop", OP(24), 0xffffffff, PPCCOM, PPCNONE, {0}},
3464{"ori", OP(24), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
3465{"oril", OP(24), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
3466
3467{"oris", OP(25), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
3468{"oriu", OP(25), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
3469
3470{"xori", OP(26), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
3471{"xoril", OP(26), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
3472
3473{"xoris", OP(27), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
3474{"xoriu", OP(27), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
3475
3476{"andi.", OP(28), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
3477{"andil.", OP(28), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
3478
3479{"andis.", OP(29), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
3480{"andiu.", OP(29), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
3481
3482{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
3483{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCNONE, {RA, RS, MB6}},
3484{"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
3485{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
3486{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCNONE, {RA, RS, MB6}},
3487{"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
3488
3489{"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, ME6}},
3490{"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, ME6}},
3491
3492{"rldic", MD(30,2,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
3493{"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
3494
3495{"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
3496{"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
3497
3498{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCNONE, {RA, RS, RB}},
3499{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, MB6}},
3500{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCNONE, {RA, RS, RB}},
3501{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, MB6}},
3502
3503{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, ME6}},
3504{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, ME6}},
3505
3506{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}},
3507{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}},
3508{"cmp", X(31,0), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}},
bdc70b4a 3509{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
1cb0a767
PB		 3510
3511{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3512{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3513{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3514{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3515{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3516{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3517{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3518{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3519{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3520{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3521{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3522{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3523{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3524{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3525{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3526{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3527{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3528{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3529{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3530{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3531{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3532{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3533{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3534{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3535{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3536{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3537{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3538{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3539{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, PPCNONE, {0}},
3540{"tw", X(31,4), X_MASK, PPCCOM, PPCNONE, {TO, RA, RB}},
3541{"t", X(31,4), X_MASK, PWRCOM, PPCNONE, {TO, RA, RB}},
3542
3543{"lvsl", X(31,6), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
3544{"lvebx", X(31,7), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
3545{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
3546
3547{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3548{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
81a0b7e2 3549{"subc", XO(31,8,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}},
1cb0a767
PB		 3550{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3551{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
3552{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}},
3553
3554{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
3555{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
3556
3557{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3558{"a", XO(31,10,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
3559{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3560{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
3561
3562{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
3563{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
3564
3565{"isellt", X(31,15), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}},
3566
e0d602ec
BE		 3567{"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, PPCNONE, {0}},
3568{"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, PPCNONE, {0}},
3569{"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, PPCNONE, {RA0, RB}},
3570{"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, PPCNONE, {T, RA0, RB}},
858d7a6d 3571
1cb0a767 3572{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, PPCNONE, {RT, FXM4}},
70dc4e32 3573{"mfcr", XFXM(31,19,0,0), XRARB_MASK, COM, POWER4, {RT}},
09a8ad8d 3574{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, PPCNONE, {RT, FXM}},
1cb0a767
PB		 3575
3576{"lwarx", X(31,20), XEH_MASK, PPC, PPCNONE, {RT, RA0, RB, EH}},
de866fcc 3577
1cb0a767
PB		 3578{"ldx", X(31,21), X_MASK, PPC64, PPCNONE, {RT, RA0, RB}},
3579
9fe54b1c 3580{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {CT, RA, RB}},
1cb0a767
PB		 3581
3582{"lwzx", X(31,23), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}},
3583{"lx", X(31,23), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
de866fcc 3584
1cb0a767
PB		 3585{"slw", XRC(31,24,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
3586{"sl", XRC(31,24,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
3587{"slw.", XRC(31,24,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
3588{"sl.", XRC(31,24,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
de866fcc 3589
1cb0a767
PB		 3590{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}},
3591{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
3592{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}},
3593{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
de866fcc 3594
1cb0a767
PB		 3595{"sld", XRC(31,27,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
3596{"sld.", XRC(31,27,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
de866fcc 3597
1cb0a767
PB		 3598{"and", XRC(31,28,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3599{"and.", XRC(31,28,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
de866fcc 3600
e0d602ec
BE		 3601{"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
3602{"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
de866fcc 3603
e0d602ec
BE		 3604{"ldepx", X(31,29), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
3605{"lwepx", X(31,31), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
de866fcc 3606
1cb0a767
PB		 3607{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}},
3608{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}},
3609{"cmpl", X(31,32), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}},
bdc70b4a 3610{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
de866fcc 3611
1cb0a767
PB		 3612{"lvsr", X(31,38), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
3613{"lvehx", X(31,39), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
3614{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
de866fcc 3615
1cb0a767 3616{"iselgt", X(31,47), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}},
de866fcc 3617
1cb0a767 3618{"lvewx", X(31,71), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
de866fcc 3619
066be9f7
PB		 3620{"addg6s", XO(31,74,0,0), XO_MASK, POWER6, PPCNONE, {RT, RA, RB}},
3621
1cb0a767 3622{"iseleq", X(31,79), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}},
de866fcc 3623
ce3d2015 3624{"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, PPCNONE, {RT, RA, RB, CRB}},
de866fcc 3625
1cb0a767
PB		 3626{"subf", XO(31,40,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
3627{"sub", XO(31,40,0,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
3628{"subf.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
3629{"sub.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
de866fcc 3630
e0d602ec
BE		 3631{"eratilx", X(31,51), X_MASK, PPCA2, PPCNONE, {ERAT_T, RA, RB}},
3632
066be9f7
PB		 3633{"lbarx", X(31,52), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}},
3634
1cb0a767 3635{"ldux", X(31,53), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}},
de866fcc 3636
1cb0a767 3637{"dcbst", X(31,54), XRT_MASK, PPC, PPCNONE, {RA, RB}},
de866fcc 3638
1cb0a767
PB		 3639{"lwzux", X(31,55), X_MASK, PPCCOM, PPCNONE, {RT, RAL, RB}},
3640{"lux", X(31,55), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
de866fcc 3641
1cb0a767
PB		 3642{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
3643{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
de866fcc 3644
1cb0a767
PB		 3645{"andc", XRC(31,60,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3646{"andc.", XRC(31,60,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
de866fcc 3647
e0d602ec
BE		 3648{"waitrsv", X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
3649{"waitimpl", X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
3650{"wait", X(31,62), XWC_MASK, POWER7|E500MC|PPCA2, PPCNONE, {WC}},
19a6653c 3651
e0d602ec 3652{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}},
19a6653c 3653
1cb0a767
PB		 3654{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3655{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3656{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3657{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3658{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3659{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3660{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3661{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3662{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3663{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3664{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3665{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3666{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3667{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3668{"td", X(31,68), X_MASK, PPC64, PPCNONE, {TO, RA, RB}},
de866fcc 3669
1cb0a767
PB		 3670{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
3671{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
3672{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
de866fcc 3673
1cb0a767
PB		 3674{"mulhw", XO(31,75,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
3675{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
de866fcc 3676
ce3d2015
AM		 3677{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, PPCNONE, {RA, RS, RB}},
3678{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, PPCNONE, {RA, RS, RB}},
de866fcc 3679
1cb0a767 3680{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, PPCNONE, {SR, RS}},
de866fcc 3681
1cb0a767 3682{"mfmsr", X(31,83), XRARB_MASK, COM, PPCNONE, {RT}},
de866fcc 3683
1cb0a767 3684{"ldarx", X(31,84), XEH_MASK, PPC64, PPCNONE, {RT, RA0, RB, EH}},
de866fcc 3685
9fe54b1c 3686{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA, RB}},
1cb0a767 3687{"dcbf", X(31,86), XLRT_MASK, PPC, PPCNONE, {RA, RB, L}},
de866fcc 3688
1cb0a767 3689{"lbzx", X(31,87), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
de866fcc 3690
e0d602ec 3691{"lbepx", X(31,95), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
de866fcc 3692
1cb0a767
PB		 3693{"lvx", X(31,103), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
3694{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
de866fcc 3695
1cb0a767
PB		 3696{"neg", XO(31,104,0,0), XORB_MASK, COM, PPCNONE, {RT, RA}},
3697{"neg.", XO(31,104,0,1), XORB_MASK, COM, PPCNONE, {RT, RA}},
de866fcc 3698
1cb0a767
PB		 3699{"mul", XO(31,107,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
3700{"mul.", XO(31,107,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
de866fcc 3701
1cb0a767 3702{"mtsrdin", X(31,114), XRA_MASK, PPC64, PPCNONE, {RS, RB}},
de866fcc 3703
066be9f7
PB		 3704{"lharx", X(31,116), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}},
3705
1cb0a767 3706{"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}},
de866fcc 3707
1cb0a767 3708{"lbzux", X(31,119), X_MASK, COM, PPCNONE, {RT, RAL, RB}},
de866fcc 3709
1cb0a767 3710{"popcntb", X(31,122), XRB_MASK, POWER5, PPCNONE, {RA, RS}},
de866fcc 3711
1cb0a767
PB		 3712{"not", XRC(31,124,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
3713{"nor", XRC(31,124,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3714{"not.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
3715{"nor.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
de866fcc 3716
e0d602ec 3717{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}},
19a6653c 3718
9fe54b1c 3719{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RS}},
de866fcc 3720
ce3d2015 3721{"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}},
de866fcc 3722
1cb0a767
PB		 3723{"stvebx", X(31,135), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
3724{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
de866fcc 3725
1cb0a767
PB		 3726{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3727{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
3728{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3729{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
de866fcc 3730
1cb0a767
PB		 3731{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3732{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
3733{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3734{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
de866fcc 3735
1cb0a767 3736{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
de866fcc 3737
1cb0a767 3738{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, PPCNONE, {RS}},
09a8ad8d
AM		 3739{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, PPCNONE, {FXM, RS}},
3740{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, PPCNONE, {FXM, RS}},
de866fcc 3741
1cb0a767 3742{"mtmsr", X(31,146), XRLARB_MASK, COM, PPCNONE, {RS, A_L}},
de866fcc 3743
e0d602ec
BE		 3744{"eratsx", XRC(31,147,0), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
3745{"eratsx.", XRC(31,147,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
3746
1cb0a767 3747{"stdx", X(31,149), X_MASK, PPC64, PPCNONE, {RS, RA0, RB}},
de866fcc 3748
1cb0a767 3749{"stwcx.", XRC(31,150,1), X_MASK, PPC, PPCNONE, {RS, RA0, RB}},
de866fcc 3750
1cb0a767
PB		 3751{"stwx", X(31,151), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}},
3752{"stx", X(31,151), X_MASK, PWRCOM, PPCNONE, {RS, RA, RB}},
de866fcc 3753
1cb0a767
PB		 3754{"slq", XRC(31,152,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
3755{"slq.", XRC(31,152,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
de866fcc 3756
1cb0a767
PB		 3757{"sle", XRC(31,153,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
3758{"sle.", XRC(31,153,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
de866fcc 3759
9fe54b1c 3760{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS}},
de866fcc 3761
e0d602ec 3762{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}},
19a6653c 3763
e0d602ec 3764{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}},
de866fcc 3765
9fe54b1c 3766{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {E}},
de866fcc 3767
ce3d2015 3768{"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}},
de866fcc 3769
1cb0a767
PB		 3770{"stvehx", X(31,167), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
3771{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
de866fcc 3772
1cb0a767 3773{"dcbtlse", X(31,174), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
de866fcc 3774
1cb0a767 3775{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, PPCNONE, {RS, A_L}},
de866fcc 3776
e0d602ec
BE		 3777{"eratre", X(31,179), X_MASK, PPCA2, PPCNONE, {RT, RA, WS}},
3778
1cb0a767 3779{"stdux", X(31,181), X_MASK, PPC64, PPCNONE, {RS, RAS, RB}},
de866fcc 3780
e0d602ec
BE		 3781{"wchkall", X(31,182), X_MASK, PPCA2, PPCNONE, {OBF}},
3782
1cb0a767
PB		 3783{"stwux", X(31,183), X_MASK, PPCCOM, PPCNONE, {RS, RAS, RB}},
3784{"stux", X(31,183), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
de866fcc 3785
1cb0a767
PB		 3786{"sliq", XRC(31,184,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
3787{"sliq.", XRC(31,184,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
de866fcc 3788
e0d602ec 3789{"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, PPCNONE, {RA, RS}},
252b5132 3790
1cb0a767
PB		 3791{"stvewx", X(31,199), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
3792{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
252b5132 3793
1cb0a767
PB		 3794{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3795{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
3796{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3797{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
252b5132 3798
1cb0a767
PB		 3799{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3800{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
3801{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3802{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
418c1742 3803
e0d602ec 3804{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2, PPCNONE, {RB}},
19a6653c 3805
bdc70b4a 3806{"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
418c1742 3807
e0d602ec
BE		 3808{"eratwe", X(31,211), X_MASK, PPCA2, PPCNONE, {RS, RA, WS}},
3809
3810{"ldawx.", XRC(31,212,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
3811
1cb0a767 3812{"stdcx.", XRC(31,214,1), X_MASK, PPC64, PPCNONE, {RS, RA0, RB}},
252b5132 3813
1cb0a767 3814{"stbx", X(31,215), X_MASK, COM, PPCNONE, {RS, RA0, RB}},
252b5132 3815
1cb0a767
PB		 3816{"sllq", XRC(31,216,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
3817{"sllq.", XRC(31,216,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
252b5132 3818
1cb0a767
PB		 3819{"sleq", XRC(31,217,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
3820{"sleq.", XRC(31,217,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
252b5132 3821
e0d602ec 3822{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}},
252b5132 3823
ce3d2015 3824{"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}},
7d5b217e 3825
1cb0a767
PB		 3826{"stvx", X(31,231), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
3827{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
f509565f 3828
1cb0a767
PB		 3829{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3830{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
3831{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3832{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
252b5132 3833
1cb0a767
PB		 3834{"mulld", XO(31,233,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
3835{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
252b5132 3836
1cb0a767
PB		 3837{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3838{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
3839{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3840{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
252b5132 3841
1cb0a767
PB		 3842{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3843{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
3844{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3845{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
252b5132 3846
e0d602ec
BE		 3847{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
3848{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC|PPCA2, PPCNONE, {RB}},
bdc70b4a
AM		 3849{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
3850{"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
418c1742 3851
066be9f7 3852{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, PPCNONE, {RA, RB}},
80890a61 3853{"dcbtst", X(31,246), X_MASK, POWER4, PPCNONE, {RA, RB, CT}},
70dc4e32 3854{"dcbtst", X(31,246), X_MASK, PPC, POWER4, {CT, RA, RB}},
418c1742 3855
1cb0a767 3856{"stbux", X(31,247), X_MASK, COM, PPCNONE, {RS, RAS, RB}},
252b5132 3857
1cb0a767
PB		 3858{"slliq", XRC(31,248,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
3859{"slliq.", XRC(31,248,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
252b5132 3860
e0d602ec 3861{"bpermd", X(31,252), X_MASK, POWER7|PPCA2, PPCNONE, {RA, RS, RB}},
066be9f7 3862
e0d602ec 3863{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
19a6653c 3864
ce3d2015 3865{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
e0d602ec 3866{"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, PPCNONE, {RS, RA}},
252b5132 3867
1cb0a767 3868{"icbt", X(31,262), XRT_MASK, PPC403, PPCNONE, {RA, RB}},
1ed8e1e4 3869
1cb0a767
PB		 3870{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
3871{"doz", XO(31,264,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
3872{"doz.", XO(31,264,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
252b5132 3873
1cb0a767
PB		 3874{"add", XO(31,266,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3875{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
3876{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3877{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
418c1742 3878
e0d602ec 3879{"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}},
19a6653c 3880
9fe54b1c 3881{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, PPC476, {RB, L}},
418c1742 3882
ce3d2015 3883{"mfapidi", X(31,275), X_MASK, BOOKE, TITAN, {RT, RA}},
1cb0a767
PB		 3884
3885{"lscbx", XRC(31,277,0), X_MASK, M601, PPCNONE, {RT, RA, RB}},
3886{"lscbx.", XRC(31,277,1), X_MASK, M601, PPCNONE, {RT, RA, RB}},
3887
066be9f7 3888{"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, PPCNONE, {RA, RB}},
80890a61 3889{"dcbt", X(31,278), X_MASK, POWER4, PPCNONE, {RA, RB, CT}},
70dc4e32 3890{"dcbt", X(31,278), X_MASK, PPC, POWER4, {CT, RA, RB}},
1cb0a767
PB		 3891
3892{"lhzx", X(31,279), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
3893
066be9f7
PB		 3894{"cdtbcd", X(31,282), XRB_MASK, POWER6, PPCNONE, {RA, RS}},
3895
1cb0a767
PB		 3896{"eqv", XRC(31,284,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3897{"eqv.", XRC(31,284,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3898
e0d602ec 3899{"lhepx", X(31,287), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 3900
3901{"mfdcrux", X(31,291), X_MASK, PPC464, PPCNONE, {RS, RA}},
3902
ce3d2015 3903{"tlbie", X(31,306), XRTLRA_MASK, PPC, TITAN, {RB, L}},
1cb0a767
PB		 3904{"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}},
3905
ce3d2015 3906{"eciwx", X(31,310), X_MASK, PPC, TITAN, {RT, RA, RB}},
1cb0a767
PB		 3907
3908{"lhzux", X(31,311), X_MASK, COM, PPCNONE, {RT, RAL, RB}},
3909
066be9f7
PB		 3910{"cbcdtd", X(31,314), XRB_MASK, POWER6, PPCNONE, {RA, RS}},
3911
1cb0a767
PB		 3912{"xor", XRC(31,316,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3913{"xor.", XRC(31,316,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3914
e0d602ec 3915{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
1cb0a767
PB		 3916
3917{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, PPCNONE, {RT}},
3918{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, PPCNONE, {RT}},
3919{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, PPCNONE, {RT}},
3920{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, PPCNONE, {RT}},
3921{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, PPCNONE, {RT}},
3922{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, PPCNONE, {RT}},
3923{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, PPCNONE, {RT}},
3924{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, PPCNONE, {RT}},
3925{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, PPCNONE, {RT}},
3926{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, PPCNONE, {RT}},
3927{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, PPCNONE, {RT}},
3928{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, PPCNONE, {RT}},
3929{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, PPCNONE, {RT}},
3930{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, PPCNONE, {RT}},
3931{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, PPCNONE, {RT}},
3932{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, PPCNONE, {RT}},
3933{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, PPCNONE, {RT}},
3934{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, PPCNONE, {RT}},
3935{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, PPCNONE, {RT}},
3936{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, PPCNONE, {RT}},
3937{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, PPCNONE, {RT}},
3938{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, PPCNONE, {RT}},
3939{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, PPCNONE, {RT}},
3940{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, PPCNONE, {RT}},
3941{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, PPCNONE, {RT}},
3942{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, PPCNONE, {RT}},
3943{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, PPCNONE, {RT}},
3944{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, PPCNONE, {RT}},
3945{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, PPCNONE, {RT}},
3946{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, PPCNONE, {RT}},
3947{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, PPCNONE, {RT}},
3948{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, PPCNONE, {RT}},
3949{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, PPCNONE, {RT}},
3950{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, PPCNONE, {RT}},
ce3d2015 3951{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN, {RT, SPR}},
e0d602ec 3952{"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, PPCNONE, {RT, SPR}},
1cb0a767 3953
ce3d2015 3954{"dcread", X(31,326), X_MASK, PPC476|TITAN, PPCNONE, {RT, RA, RB}},
9fe54b1c 3955
1cb0a767
PB		 3956{"div", XO(31,331,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
3957{"div.", XO(31,331,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
3958
066be9f7
PB		 3959{"lxvdsx", X(31,332), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
3960
1cb0a767
PB		 3961{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, PPCNONE, {RT, PMR}},
3962
3963{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, PPCNONE, {RT}},
3964{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, PPCNONE, {RT}},
ce3d2015
AM		 3965{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
3966{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
1cb0a767
PB		 3967{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, PPCNONE, {RT}},
3968{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, PPCNONE, {RT}},
3969{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, PPCNONE, {RT}},
3970{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, PPCNONE, {RT}},
ce3d2015
AM		 3971{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
3972{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
bdc70b4a 3973{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}},
1cb0a767 3974{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, PPCNONE, {RT}},
ce3d2015 3975{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}},
1cb0a767
PB		 3976{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, PPCNONE, {RT}},
3977{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, PPCNONE, {RT}},
3978{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, PPCNONE, {RT}},
3979{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3980{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3981{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3982{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3983{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3984{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3985{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, PPCNONE, {RT}},
3986{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, PPCNONE, {RT}},
3987{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, PPCNONE, {RT}},
3988{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, PPCNONE, {RT}},
3989{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, PPCNONE, {RT}},
3990{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, PPCNONE, {RT}},
3991{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, PPCNONE, {RT}},
3992{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, PPCNONE, {RT}},
3993{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, PPCNONE, {RT}},
3994{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, PPCNONE, {RT}},
3995{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, PPCNONE, {RT}},
3996{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, PPCNONE, {RT}},
3997{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, PPCNONE, {RT}},
3998{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, PPCNONE, {RT}},
3999{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, PPCNONE, {RT}},
4000{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, PPCNONE, {RT}},
4001{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, PPCNONE, {RT}},
4002{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4003{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, PPCNONE, {RT, SPRG}},
4004{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}},
4005{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}},
4006{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}},
4007{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}},
4008{"mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4009{"mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4010{"mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4011{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, PPCNONE, {RT}},
4012{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, PPCNONE, {RT}},
4013{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, PPCNONE, {RT}},
4014{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, PPCNONE, {RT}},
4015{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, PPCNONE, {RT}},
ce3d2015 4016{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
1cb0a767
PB		 4017{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4018{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, PPCNONE, {RT}},
4019{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4020{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4021{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4022{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4023{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4024{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4025{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4026{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4027{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4028{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4029{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4030{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4031{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4032{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4033{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4034{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4035{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4036{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4037{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4038{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4039{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4040{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4041{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4042{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4043{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4044{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4045{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4046{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4047{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4048{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, PPCNONE, {RT}},
4049{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
4050{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, PPCNONE, {RT}},
4051{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, PPCNONE, {RT}},
4052{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
ce3d2015 4053{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
1cb0a767 4054{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
ce3d2015 4055{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
1cb0a767
PB		 4056{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
4057{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, PPCNONE, {RT}},
ce3d2015
AM		 4058{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
4059{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
1cb0a767
PB		 4060{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, PPCNONE, {RT}},
4061{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, PPCNONE, {RT}},
4062{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, PPCNONE, {RT}},
4063{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, PPCNONE, {RT}},
4064{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, PPCNONE, {RT}},
4065{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, PPCNONE, {RT}},
4066{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}},
4067{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}},
4068{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}},
ce3d2015 4069{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}},
1cb0a767
PB		 4070{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, PPCNONE, {RT}},
4071{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, PPCNONE, {RT}},
4072{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, PPCNONE, {RT}},
4073{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, PPCNONE, {RT}},
4074{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, PPCNONE, {RT}},
4075{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, PPCNONE, {RT}},
4076{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, PPCNONE, {RT}},
4077{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, PPCNONE, {RT}},
4078{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, PPCNONE, {RT}},
4079{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, PPCNONE, {RT}},
4080{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, PPCNONE, {RT}},
4081{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, PPCNONE, {RT}},
4082{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, PPCNONE, {RT}},
4083{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, PPCNONE, {RT}},
4084{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, PPCNONE, {RT}},
4085{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, PPCNONE, {RT}},
4086{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, PPCNONE, {RT}},
4087{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, PPCNONE, {RT}},
4088{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, PPCNONE, {RT}},
4089{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, PPCNONE, {RT}},
4090{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, PPCNONE, {RT}},
4091{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, PPCNONE, {RT}},
ce3d2015
AM		 4092{"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, PPCNONE, {RT}},
4093{"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, PPCNONE, {RT}},
4094{"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, PPCNONE, {RT}},
4095{"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, PPCNONE, {RT}},
4096{"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, PPCNONE, {RT}},
4097{"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, PPCNONE, {RT}},
4098{"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, PPCNONE, {RT}},
4099{"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, PPCNONE, {RT}},
4100{"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, PPCNONE, {RT}},
4101{"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, PPCNONE, {RT}},
1cb0a767
PB		 4102{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, PPCNONE, {RT}},
4103{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, PPCNONE, {RT}},
4104{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, PPCNONE, {RT}},
4105{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, PPCNONE, {RT}},
4106{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, PPCNONE, {RT}},
4107{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, PPCNONE, {RT}},
4108{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, PPCNONE, {RT}},
4109{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, PPCNONE, {RT}},
4110{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, PPCNONE, {RT}},
ce3d2015
AM		 4111{"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, PPCNONE, {RT}},
4112{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, PPCNONE, {RT}},
1cb0a767
PB		 4113{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, PPCNONE, {RT}},
4114{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, PPCNONE, {RT}},
4115{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, PPCNONE, {RT}},
4116{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, PPCNONE, {RT}},
4117{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, PPCNONE, {RT}},
4118{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, PPCNONE, {RT}},
4119{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, PPCNONE, {RT}},
4120{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, PPCNONE, {RT}},
4121{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, PPCNONE, {RT}},
4122{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, PPCNONE, {RT}},
4123{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, PPCNONE, {RT}},
4124{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, PPCNONE, {RT}},
4125{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, PPCNONE, {RT}},
4126{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, PPCNONE, {RT}},
4127{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, PPCNONE, {RT}},
4128{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, PPCNONE, {RT}},
ce3d2015 4129{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, PPCNONE, {RT}},
1cb0a767
PB		 4130{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, PPCNONE, {RT}},
4131{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, PPCNONE, {RT}},
4132{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, PPCNONE, {RT}},
4133{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, PPCNONE, {RT}},
4134{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, PPCNONE, {RT}},
4135{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, PPCNONE, {RT}},
4136{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, PPCNONE, {RT}},
4137{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, PPCNONE, {RT}},
4138{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, PPCNONE, {RT}},
4139{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, PPCNONE, {RT}},
4140{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, PPCNONE, {RT}},
4141{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, PPCNONE, {RT}},
4142{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, PPCNONE, {RT}},
ce3d2015 4143{"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, PPCNONE, {RS}},
1cb0a767
PB		 4144{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, PPCNONE, {RT}},
4145{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, PPCNONE, {RT}},
4146{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, PPCNONE, {RT}},
4147{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, PPCNONE, {RT}},
4148{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, PPCNONE, {RT}},
4149{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, PPCNONE, {RT}},
4150{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, PPCNONE, {RT}},
4151{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, PPCNONE, {RT}},
4152{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, PPCNONE, {RT}},
4153{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, PPCNONE, {RT}},
4154{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, PPCNONE, {RT}},
4155{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, PPCNONE, {RT}},
4156{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, PPCNONE, {RT}},
4157{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, PPCNONE, {RT}},
4158{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, PPCNONE, {RT}},
4159{"mfspr", X(31,339), X_MASK, COM, PPCNONE, {RT, SPR}},
4160
4161{"lwax", X(31,341), X_MASK, PPC64, PPCNONE, {RT, RA0, RB}},
4162
4163{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
4164
4165{"lhax", X(31,343), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
4166
4167{"lvxl", X(31,359), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
4168
4169{"abs", XO(31,360,0,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
4170{"abs.", XO(31,360,0,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
4171
4172{"divs", XO(31,363,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4173{"divs.", XO(31,363,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4174
ce3d2015 4175{"tlbia", X(31,370), 0xffffffff, PPC, TITAN, {0}},
1cb0a767 4176
bdc70b4a
AM		 4177{"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371, {RT}},
4178{"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371, {RT}},
4179{"mftb", X(31,371), X_MASK, PPC|PPCA2, NO371|POWER7, {RT, TBR}},
1cb0a767
PB		 4180
4181{"lwaux", X(31,373), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}},
4182
4183{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
4184
4185{"lhaux", X(31,375), X_MASK, COM, PPCNONE, {RT, RAL, RB}},
4186
e0d602ec 4187{"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, PPCNONE, {RA, RS}},
066be9f7 4188
ce3d2015 4189{"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
e0d602ec 4190{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, PPCNONE, {RA, RS}},
1cb0a767 4191
ce3d2015 4192{"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}},
1cb0a767
PB		 4193{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
4194
51b5d4a8
AM		 4195{"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4196{"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4197{"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4198{"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
066be9f7 4199
1cb0a767
PB		 4200{"dcblce", X(31,398), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
4201
4202{"slbmte", X(31,402), XRA_MASK, PPC64, PPCNONE, {RS, RB}},
4203
2f7f7710
AM		 4204{"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, PPCNONE, {RS, RA, RB}},
4205{"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, PPCNONE, {RS, RA, RB}},
e0d602ec 4206
1cb0a767
PB		 4207{"sthx", X(31,407), X_MASK, COM, PPCNONE, {RS, RA0, RB}},
4208
4209{"orc", XRC(31,412,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
4210{"orc.", XRC(31,412,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
4211
e0d602ec 4212{"sthepx", X(31,415), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}},
1cb0a767
PB		 4213
4214{"mtdcrux", X(31,419), X_MASK, PPC464, PPCNONE, {RA, RS}},
4215
51b5d4a8
AM		 4216{"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4217{"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4218{"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4219{"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
066be9f7 4220
1cb0a767
PB		 4221{"slbie", X(31,434), XRTRA_MASK, PPC64, PPCNONE, {RB}},
4222
ce3d2015 4223{"ecowx", X(31,438), X_MASK, PPC, TITAN, {RT, RA, RB}},
1cb0a767
PB		 4224
4225{"sthux", X(31,439), X_MASK, COM, PPCNONE, {RS, RAS, RB}},
4226
4227{"mdors", 0x7f9ce378, 0xffffffff, E500MC, PPCNONE, {0}},
4228
4229{"mr", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
4230{"or", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
4231{"mr.", XRC(31,444,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
4232{"or.", XRC(31,444,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
4233
4234{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, PPCNONE, {RS}},
4235{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, PPCNONE, {RS}},
4236{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, PPCNONE, {RS}},
4237{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, PPCNONE, {RS}},
4238{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, PPCNONE, {RS}},
4239{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, PPCNONE, {RS}},
4240{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, PPCNONE, {RS}},
4241{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, PPCNONE, {RS}},
4242{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, PPCNONE, {RS}},
4243{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, PPCNONE, {RS}},
4244{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, PPCNONE, {RS}},
4245{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, PPCNONE, {RS}},
4246{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, PPCNONE, {RS}},
4247{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, PPCNONE, {RS}},
4248{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, PPCNONE, {RS}},
4249{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, PPCNONE, {RS}},
4250{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, PPCNONE, {RS}},
4251{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, PPCNONE, {RS}},
4252{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, PPCNONE, {RS}},
4253{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, PPCNONE, {RS}},
4254{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, PPCNONE, {RS}},
4255{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, PPCNONE, {RS}},
4256{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, PPCNONE, {RS}},
4257{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, PPCNONE, {RS}},
4258{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, PPCNONE, {RS}},
4259{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, PPCNONE, {RS}},
4260{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, PPCNONE, {RS}},
4261{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, PPCNONE, {RS}},
4262{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, PPCNONE, {RS}},
4263{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, PPCNONE, {RS}},
4264{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, PPCNONE, {RS}},
4265{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, PPCNONE, {RS}},
4266{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, PPCNONE, {RS}},
4267{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, PPCNONE, {RS}},
ce3d2015 4268{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN, {SPR, RS}},
e0d602ec 4269{"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, PPCNONE, {SPR, RS}},
1cb0a767 4270
cee62821 4271{"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
9fe54b1c 4272{"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, PPCNONE, {CT}},
1cb0a767
PB		 4273
4274{"divdu", XO(31,457,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
4275{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
4276
4277{"divwu", XO(31,459,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4278{"divwu.", XO(31,459,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4279
4280{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, PPCNONE, {PMR, RS}},
4281
4282{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, PPCNONE, {RS}},
4283{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, PPCNONE, {RS}},
4284{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, PPCNONE, {RS}},
ce3d2015 4285{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, PPCNONE, {RS}},
1cb0a767 4286{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, PPCNONE, {RS}},
ce3d2015
AM		 4287{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
4288{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}},
4289{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}},
4290{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}},
1cb0a767
PB		 4291{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, PPCNONE, {RS}},
4292{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, PPCNONE, {RS}},
ce3d2015 4293{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}},
1cb0a767
PB		 4294{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, PPCNONE, {RS}},
4295{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, PPCNONE, {RS}},
4296{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, PPCNONE, {RS}},
4297{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4298{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4299{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4300{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4301{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4302{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4303{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4304{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, PPCNONE, {RS}},
4305{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, PPCNONE, {RS}},
4306{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, PPCNONE, {RS}},
4307{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, PPCNONE, {RS}},
4308{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, PPCNONE, {RS}},
4309{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, PPCNONE, {RS}},
4310{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, PPCNONE, {RS}},
4311{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, PPCNONE, {RS}},
4312{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, PPCNONE, {RS}},
4313{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, PPCNONE, {RS}},
4314{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, PPCNONE, {RS}},
4315{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, PPCNONE, {RS}},
4316{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, PPCNONE, {RS}},
4317{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, PPCNONE, {RS}},
4318{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, PPCNONE, {RS}},
4319{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, PPCNONE, {RS}},
4320{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, PPCNONE, {RS}},
4321{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4322{"mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, PPCNONE, {SPRG, RS}},
4323{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, PPCNONE, {RS}},
4324{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, PPCNONE, {RS}},
4325{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, PPCNONE, {RS}},
4326{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, PPCNONE, {RS}},
4327{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}},
4328{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}},
4329{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}},
4330{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}},
4331{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, PPCNONE, {RS}},
ce3d2015 4332{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}},
1cb0a767
PB		 4333{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, PPCNONE, {RS}},
4334{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, PPCNONE, {RS}},
4335{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4336{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4337{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4338{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4339{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4340{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4341{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4342{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4343{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4344{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4345{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4346{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4347{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4348{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4349{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4350{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4351{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4352{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4353{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4354{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4355{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4356{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4357{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4358{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4359{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4360{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4361{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4362{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4363{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4364{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4365{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
4366{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, PPCNONE, {RS}},
4367{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, PPCNONE, {RS}},
4368{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
ce3d2015 4369{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
1cb0a767 4370{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
ce3d2015 4371{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
1cb0a767
PB		 4372{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
4373{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, PPCNONE, {RS}},
ce3d2015
AM		 4374{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
4375{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
1cb0a767
PB		 4376{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}},
4377{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}},
4378{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}},
ce3d2015
AM		 4379{"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, PPCNONE, {RS}},
4380{"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, PPCNONE, {RS}},
4381{"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, PPCNONE, {RS}},
4382{"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, PPCNONE, {RS}},
4383{"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, PPCNONE, {RS}},
4384{"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, PPCNONE, {RS}},
1cb0a767
PB		 4385{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, PPCNONE, {RS}},
4386{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, PPCNONE, {RS}},
4387{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, PPCNONE, {RS}},
4388{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, PPCNONE, {RS}},
4389{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, PPCNONE, {RS}},
4390{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, PPCNONE, {RS}},
4391{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, PPCNONE, {RS}},
4392{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, PPCNONE, {RS}},
4393{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, PPCNONE, {RS}},
ce3d2015
AM		 4394{"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, PPCNONE, {RS}},
4395{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, PPCNONE, {RS}},
1cb0a767
PB		 4396{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, PPCNONE, {RS}},
4397{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, PPCNONE, {RS}},
4398{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, PPCNONE, {RS}},
4399{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, PPCNONE, {RS}},
4400{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, PPCNONE, {RS}},
4401{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, PPCNONE, {RS}},
4402{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, PPCNONE, {RS}},
4403{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, PPCNONE, {RS}},
4404{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, PPCNONE, {RS}},
4405{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, PPCNONE, {RS}},
4406{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, PPCNONE, {RS}},
4407{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, PPCNONE, {RS}},
4408{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, PPCNONE, {RS}},
4409{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, PPCNONE, {RS}},
4410{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, PPCNONE, {RS}},
4411{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, PPCNONE, {RS}},
4412{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, PPCNONE, {RS}},
4413{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, PPCNONE, {RS}},
4414{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, PPCNONE, {RS}},
4415{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, PPCNONE, {RS}},
4416{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, PPCNONE, {RS}},
4417{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, PPCNONE, {RS}},
4418{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, PPCNONE, {RS}},
4419{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, PPCNONE, {RS}},
4420{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, PPCNONE, {RS}},
4421{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, PPCNONE, {RS}},
4422{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, PPCNONE, {RS}},
4423{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, PPCNONE, {RS}},
4424{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, PPCNONE, {RS}},
ce3d2015 4425{"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, PPCNONE, {RS}},
1cb0a767
PB		 4426{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, PPCNONE, {RS}},
4427{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, PPCNONE, {RS}},
4428{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, PPCNONE, {RS}},
4429{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, PPCNONE, {RS}},
4430{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, PPCNONE, {RS}},
4431{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, PPCNONE, {RS}},
4432{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, PPCNONE, {RS}},
4433{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, PPCNONE, {RS}},
4434{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, PPCNONE, {RS}},
4435{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, PPCNONE, {RS}},
4436{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, PPCNONE, {RS}},
4437{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, PPCNONE, {RS}},
4438{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, PPCNONE, {RS}},
4439{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, PPCNONE, {RS}},
4440{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, PPCNONE, {RS}},
4441{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, PPCNONE, {RS}},
4442{"mtspr", X(31,467), X_MASK, COM, PPCNONE, {SPR, RS}},
4443
4444{"dcbi", X(31,470), XRT_MASK, PPC, PPCNONE, {RA, RB}},
4445
4446{"nand", XRC(31,476,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
4447{"nand.", XRC(31,476,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
4448
4449{"dsn", X(31,483), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
4450
9fe54b1c 4451{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA, RB}},
1cb0a767 4452
ce3d2015 4453{"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}},
1cb0a767
PB		 4454
4455{"stvxl", X(31,487), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
4456
4457{"nabs", XO(31,488,0,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
4458{"nabs.", XO(31,488,0,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
4459
4460{"divd", XO(31,489,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
4461{"divd.", XO(31,489,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
4462
4463{"divw", XO(31,491,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4464{"divw.", XO(31,491,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4465
4466{"icbtlse", X(31,494), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
4467
4468{"slbia", X(31,498), 0xffffffff, PPC64, PPCNONE, {0}},
4469
4470{"cli", X(31,502), XRB_MASK, POWER, PPCNONE, {RT, RA}},
4471
e0d602ec 4472{"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, PPCNONE, {RA, RS}},
066be9f7 4473
9fe54b1c 4474{"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS, RB}},
1cb0a767 4475
066be9f7 4476{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, POWER7, {BF}},
252b5132 4477
1cb0a767 4478{"lbdx", X(31,515), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
19a6653c 4479
1cb0a767 4480{"bblels", X(31,518), X_MASK, PPCBRLK, PPCNONE, {0}},
252b5132 4481
1cb0a767
PB		 4482{"lvlx", X(31,519), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
4483{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
252b5132 4484
1cb0a767
PB		 4485{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4486{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
81a0b7e2 4487{"subco", XO(31,8,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}},
1cb0a767
PB		 4488{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4489{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
81a0b7e2 4490{"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}},
252b5132 4491
1cb0a767
PB		 4492{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4493{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4494{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4495{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
252b5132 4496
1cb0a767 4497{"clcs", X(31,531), XRB_MASK, M601, PPCNONE, {RT, RA}},
418c1742 4498
e0d602ec 4499{"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RT, RA0, RB}},
418c1742 4500
989993d8 4501{"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}},
1cb0a767 4502{"lsx", X(31,533), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
252b5132 4503
1cb0a767
PB		 4504{"lwbrx", X(31,534), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}},
4505{"lbrx", X(31,534), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
252b5132 4506
e01d869a 4507{"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
702f0fb4 4508
1cb0a767
PB		 4509{"srw", XRC(31,536,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
4510{"sr", XRC(31,536,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
4511{"srw.", XRC(31,536,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
4512{"sr.", XRC(31,536,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
252b5132 4513
1cb0a767
PB		 4514{"rrib", XRC(31,537,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4515{"rrib.", XRC(31,537,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
23976049 4516
1cb0a767
PB		 4517{"srd", XRC(31,539,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
4518{"srd.", XRC(31,539,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
f509565f 4519
1cb0a767
PB		 4520{"maskir", XRC(31,541,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4521{"maskir.", XRC(31,541,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
252b5132 4522
1cb0a767 4523{"lhdx", X(31,547), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
19a6653c 4524
1cb0a767 4525{"bbelr", X(31,550), X_MASK, PPCBRLK, PPCNONE, {0}},
418c1742 4526
1cb0a767
PB		 4527{"lvrx", X(31,551), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
4528{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
252b5132 4529
1cb0a767
PB		 4530{"subfo", XO(31,40,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4531{"subo", XO(31,40,1,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
4532{"subfo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4533{"subo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
252b5132 4534
1cb0a767 4535{"tlbsync", X(31,566), 0xffffffff, PPC, PPCNONE, {0}},
252b5132 4536
e01d869a 4537{"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
252b5132 4538
1cb0a767 4539{"lwdx", X(31,579), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
19a6653c 4540
1cb0a767 4541{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
081ba1b3 4542
066be9f7
PB		 4543{"lxsdx", X(31,588), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
4544
bdc70b4a 4545{"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
252b5132 4546
989993d8 4547{"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RA0, NBI}},
1cb0a767 4548{"lsi", X(31,597), X_MASK, PWRCOM, PPCNONE, {RT, RA0, NB}},
252b5132 4549
e01d869a 4550{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
1cb0a767 4551{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}},
9fe54b1c
PB		 4552{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}},
4553{"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}},
e01d869a
AM		 4554{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, PPCNONE, {0}},
4555{"lwsync", X(31,598), 0xffffffff, E500, PPCNONE, {0}},
1cb0a767 4556{"dcs", X(31,598), 0xffffffff, PWRCOM, PPCNONE, {0}},
418c1742 4557
e01d869a 4558{"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
23976049 4559
066be9f7 4560{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
e0d602ec 4561{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, PPCNONE, {FRT, RA, RB}},
252b5132 4562
1cb0a767 4563{"lddx", X(31,611), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
19a6653c 4564
1cb0a767 4565{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
081ba1b3 4566
1cb0a767
PB		 4567{"nego", XO(31,104,1,0), XORB_MASK, COM, PPCNONE, {RT, RA}},
4568{"nego.", XO(31,104,1,1), XORB_MASK, COM, PPCNONE, {RT, RA}},
252b5132 4569
1cb0a767
PB		 4570{"mulo", XO(31,107,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4571{"mulo.", XO(31,107,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
252b5132 4572
81a0b7e2 4573{"mfsri", X(31,627), X_MASK, M601, PPCNONE, {RT, RA, RB}},
252b5132 4574
81a0b7e2 4575{"dclst", X(31,630), XRB_MASK, M601, PPCNONE, {RS, RA}},
252b5132 4576
e01d869a 4577{"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
252b5132 4578
1cb0a767 4579{"stbdx", X(31,643), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
19a6653c 4580
1cb0a767
PB		 4581{"stvlx", X(31,647), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
4582{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
23976049 4583
1cb0a767
PB		 4584{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4585{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4586{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4587{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
252b5132 4588
1cb0a767
PB		 4589{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4590{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4591{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4592{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
252b5132 4593
bdc70b4a 4594{"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
418c1742 4595
e0d602ec 4596{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RS, RA0, RB}},
252b5132 4597
f383de66 4598{"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},
1cb0a767 4599{"stsx", X(31,661), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
418c1742 4600
1cb0a767
PB		 4601{"stwbrx", X(31,662), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}},
4602{"stbrx", X(31,662), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
252b5132 4603
e01d869a 4604{"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
ede602d7 4605
1cb0a767
PB		 4606{"srq", XRC(31,664,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4607{"srq.", XRC(31,664,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
252b5132 4608
1cb0a767
PB		 4609{"sre", XRC(31,665,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4610{"sre.", XRC(31,665,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
252b5132 4611
1cb0a767 4612{"sthdx", X(31,675), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
19a6653c 4613
1cb0a767
PB		 4614{"stvrx", X(31,679), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
4615{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
252b5132 4616
066be9f7
PB		 4617{"stbcx.", XRC(31,694,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}},
4618
e01d869a 4619{"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
252b5132 4620
1cb0a767
PB		 4621{"sriq", XRC(31,696,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
4622{"sriq.", XRC(31,696,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
252b5132 4623
1cb0a767 4624{"stwdx", X(31,707), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
19a6653c 4625
1cb0a767 4626{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
081ba1b3 4627
066be9f7
PB		 4628{"stxsdx", X(31,716), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
4629
1cb0a767
PB		 4630{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4631{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
4632{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4633{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
418c1742 4634
1cb0a767
PB		 4635{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4636{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
4637{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4638{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
fdd12ef3 4639
f383de66 4640{"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},
1cb0a767 4641{"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}},
252b5132 4642
066be9f7
PB		 4643{"sthcx.", XRC(31,726,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}},
4644
e01d869a 4645{"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
252b5132 4646
1cb0a767
PB		 4647{"srlq", XRC(31,728,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4648{"srlq.", XRC(31,728,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
418c1742 4649
1cb0a767
PB		 4650{"sreq", XRC(31,729,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4651{"sreq.", XRC(31,729,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
252b5132 4652
066be9f7 4653{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
e0d602ec 4654{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, PPCNONE, {FRS, RA, RB}},
252b5132 4655
1cb0a767 4656{"stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
19a6653c 4657
1cb0a767 4658{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
081ba1b3 4659
1cb0a767
PB		 4660{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4661{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
4662{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4663{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
252b5132 4664
1cb0a767
PB		 4665{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
4666{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
252b5132 4667
1cb0a767
PB		 4668{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4669{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
4670{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4671{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
418c1742 4672
1cb0a767
PB		 4673{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4674{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4675{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4676{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
702f0fb4 4677
9fe54b1c 4678{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}},
1cb0a767 4679{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
252b5132 4680
e01d869a 4681{"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
252b5132 4682
1cb0a767
PB		 4683{"srliq", XRC(31,760,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
4684{"srliq.", XRC(31,760,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
252b5132 4685
1cb0a767
PB		 4686{"lvlxl", X(31,775), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
4687{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
ede602d7 4688
1cb0a767
PB		 4689{"dozo", XO(31,264,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4690{"dozo.", XO(31,264,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
252b5132 4691
1cb0a767
PB		 4692{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4693{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4694{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4695{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
252b5132 4696
066be9f7
PB		 4697{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
4698
9fe54b1c 4699{"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}},
252b5132 4700
1cb0a767 4701{"lwzcix", X(31,789), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
252b5132 4702
1cb0a767 4703{"lhbrx", X(31,790), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
252b5132 4704
989993d8 4705{"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA, RB}},
c72ab5f2 4706{"lfqx", X(31,791), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}},
418c1742 4707
1cb0a767
PB		 4708{"sraw", XRC(31,792,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
4709{"sra", XRC(31,792,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
4710{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
4711{"sra.", XRC(31,792,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
fdd12ef3 4712
1cb0a767
PB		 4713{"srad", XRC(31,794,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
4714{"srad.", XRC(31,794,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
252b5132 4715
1cb0a767 4716{"lfddx", X(31,803), X_MASK, E500MC, PPCNONE, {FRT, RA, RB}},
19a6653c 4717
1cb0a767 4718{"lvrxl", X(31,807), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
252b5132 4719
81a0b7e2 4720{"rac", X(31,818), X_MASK, M601, PPCNONE, {RT, RA, RB}},
252b5132 4721
e0d602ec
BE		 4722{"erativax", X(31,819), X_MASK, PPCA2, PPCNONE, {RS, RA0, RB}},
4723
1cb0a767 4724{"lhzcix", X(31,821), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
252b5132 4725
1cb0a767 4726{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, PPCNONE, {STRM}},
252b5132 4727
1cb0a767 4728{"lfqux", X(31,823), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}},
fdd12ef3 4729
1cb0a767
PB		 4730{"srawi", XRC(31,824,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, SH}},
4731{"srai", XRC(31,824,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}},
4732{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, SH}},
4733{"srai.", XRC(31,824,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}},
702f0fb4 4734
1cb0a767
PB		 4735{"sradi", XS(31,413,0), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
4736{"sradi.", XS(31,413,1), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
e0c21649 4737
1cb0a767
PB		 4738{"divo", XO(31,331,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4739{"divo.", XO(31,331,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
252b5132 4740
1cb0a767 4741{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
9b4e5766 4742
e0d602ec
BE		 4743{"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, PPCNONE, {RA, RB}},
4744
1cb0a767 4745{"slbmfev", X(31,851), XRA_MASK, PPC64, PPCNONE, {RT, RB}},
252b5132 4746
1cb0a767 4747{"lbzcix", X(31,853), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
418c1742 4748
9fe54b1c
PB		 4749{"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}},
4750{"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, PPCNONE, {MO}},
e01d869a 4751{"eieio", XMBAR(31,854,1),0xffffffff, E500, PPCNONE, {0}},
9fe54b1c 4752{"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, PPCNONE, {0}},
418c1742 4753
9fe54b1c 4754{"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, RA0, RB}},
418c1742 4755
1cb0a767
PB		 4756{"abso", XO(31,360,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
4757{"abso.", XO(31,360,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
702f0fb4 4758
1cb0a767
PB		 4759{"divso", XO(31,363,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4760{"divso.", XO(31,363,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
252b5132 4761
1cb0a767 4762{"ldcix", X(31,885), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
252b5132 4763
e0d602ec 4764{"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, PPCNONE, {FRT, RA0, RB}},
066be9f7 4765
1cb0a767
PB		 4766{"stvlxl", X(31,903), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
4767{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
252b5132 4768
51b5d4a8
AM		 4769{"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4770{"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4771{"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4772{"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
066be9f7
PB		 4773
4774{"stxvw4x", X(31,908), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
4775
9fe54b1c
PB		 4776{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA, RB}},
4777{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA, RB}},
252b5132 4778
1cb0a767 4779{"slbmfee", X(31,915), XRA_MASK, PPC64, PPCNONE, {RT, RB}},
702f0fb4 4780
1cb0a767 4781{"stwcix", X(31,917), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
f5c120c5 4782
1cb0a767 4783{"sthbrx", X(31,918), X_MASK, COM, PPCNONE, {RS, RA0, RB}},
252b5132 4784
989993d8 4785{"stfdpx", X(31,919), X_MASK, POWER6, POWER7, {FRSp, RA, RB}},
c72ab5f2 4786{"stfqx", X(31,919), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}},
6ba045b1 4787
1cb0a767
PB		 4788{"sraq", XRC(31,920,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4789{"sraq.", XRC(31,920,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
702f0fb4 4790
1cb0a767
PB		 4791{"srea", XRC(31,921,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4792{"srea.", XRC(31,921,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
252b5132 4793
1cb0a767
PB		 4794{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}},
4795{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
4796{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}},
4797{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
702f0fb4 4798
1cb0a767 4799{"stfddx", X(31,931), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}},
19a6653c 4800
85d4ac0b
AM		 4801{"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, PPCNONE, {RA0, RB}},
4802{"wclrall", X(31,934), XRARB_MASK, PPCA2, PPCNONE, {L}},
4803{"wclr", X(31,934), X_MASK, PPCA2, PPCNONE, {L, RA0, RB}},
4804
1cb0a767 4805{"stvrxl", X(31,935), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
6ba045b1 4806
51b5d4a8
AM		 4807{"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4808{"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4809{"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4810{"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
066be9f7 4811
e0d602ec
BE		 4812{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
4813{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
9fe54b1c 4814{"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
702f0fb4 4815
1cb0a767 4816{"sthcix", X(31,949), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
252b5132 4817
51b5d4a8
AM		 4818{"icswepx", XRC(31,950,0), X_MASK, PPCA2, PPCNONE, {RS, RA, RB}},
4819{"icswepx.", XRC(31,950,1), X_MASK, PPCA2, PPCNONE, {RS, RA, RB}},
4820
1cb0a767 4821{"stfqux", X(31,951), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}},
252b5132 4822
1cb0a767
PB		 4823{"sraiq", XRC(31,952,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
4824{"sraiq.", XRC(31,952,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
252b5132 4825
1cb0a767
PB		 4826{"extsb", XRC(31,954,0), XRB_MASK, PPC, PPCNONE, {RA, RS}},
4827{"extsb.", XRC(31,954,1), XRB_MASK, PPC, PPCNONE, {RA, RS}},
252b5132 4828
cee62821 4829{"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
9fe54b1c 4830{"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, PPCNONE, {CT}},
418c1742 4831
1cb0a767
PB		 4832{"divduo", XO(31,457,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
4833{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
702f0fb4 4834
1cb0a767
PB		 4835{"divwuo", XO(31,459,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4836{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
252b5132 4837
1cb0a767 4838{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
9b4e5766 4839
9fe54b1c 4840{"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
1cb0a767
PB		 4841{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
4842{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
9fe54b1c 4843{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
418c1742 4844
1cb0a767 4845{"stbcix", X(31,981), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
252b5132 4846
1cb0a767 4847{"icbi", X(31,982), XRT_MASK, PPC, PPCNONE, {RA, RB}},
252b5132 4848
e01d869a 4849{"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
702f0fb4 4850
1cb0a767
PB		 4851{"extsw", XRC(31,986,0), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
4852{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
252b5132 4853
e0d602ec 4854{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}},
19a6653c 4855
ce3d2015 4856{"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, PPCNONE, {RA, RB}},
252b5132 4857
1cb0a767
PB		 4858{"nabso", XO(31,488,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
4859{"nabso.", XO(31,488,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
252b5132 4860
1cb0a767
PB		 4861{"divdo", XO(31,489,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
4862{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
418c1742 4863
1cb0a767
PB		 4864{"divwo", XO(31,491,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4865{"divwo.", XO(31,491,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
702f0fb4 4866
ce3d2015 4867{"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},
252b5132 4868
1cb0a767 4869{"stdcix", X(31,1013), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
418c1742 4870
1cb0a767
PB		 4871{"dcbz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA, RB}},
4872{"dclz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA, RB}},
786e2c0f 4873
e0d602ec 4874{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}},
ede602d7 4875
9fe54b1c 4876{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA, RB}},
252b5132 4877
1cb0a767
PB		 4878{"cctpl", 0x7c210b78, 0xffffffff, CELL, PPCNONE, {0}},
4879{"cctpm", 0x7c421378, 0xffffffff, CELL, PPCNONE, {0}},
4880{"cctph", 0x7c631b78, 0xffffffff, CELL, PPCNONE, {0}},
252b5132 4881
1cb0a767
PB		 4882{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
4883{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
4884{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, PPCNONE, {0}},
252b5132 4885
1cb0a767
PB		 4886{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, PPCNONE, {0}},
4887{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, PPCNONE, {0}},
4888{"db12cyc", 0x7fdef378, 0xffffffff, CELL, PPCNONE, {0}},
4889{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, PPCNONE, {0}},
252b5132 4890
1cb0a767
PB		 4891{"lwz", OP(32), OP_MASK, PPCCOM, PPCNONE, {RT, D, RA0}},
4892{"l", OP(32), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
252b5132 4893
1cb0a767
PB		 4894{"lwzu", OP(33), OP_MASK, PPCCOM, PPCNONE, {RT, D, RAL}},
4895{"lu", OP(33), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
252b5132 4896
1cb0a767 4897{"lbz", OP(34), OP_MASK, COM, PPCNONE, {RT, D, RA0}},
252b5132 4898
1cb0a767 4899{"lbzu", OP(35), OP_MASK, COM, PPCNONE, {RT, D, RAL}},
252b5132 4900
1cb0a767
PB		 4901{"stw", OP(36), OP_MASK, PPCCOM, PPCNONE, {RS, D, RA0}},
4902{"st", OP(36), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}},
252b5132 4903
1cb0a767
PB		 4904{"stwu", OP(37), OP_MASK, PPCCOM, PPCNONE, {RS, D, RAS}},
4905{"stu", OP(37), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}},
252b5132 4906
1cb0a767 4907{"stb", OP(38), OP_MASK, COM, PPCNONE, {RS, D, RA0}},
252b5132 4908
1cb0a767 4909{"stbu", OP(39), OP_MASK, COM, PPCNONE, {RS, D, RAS}},
252b5132 4910
1cb0a767 4911{"lhz", OP(40), OP_MASK, COM, PPCNONE, {RT, D, RA0}},
252b5132 4912
1cb0a767 4913{"lhzu", OP(41), OP_MASK, COM, PPCNONE, {RT, D, RAL}},
252b5132 4914
1cb0a767 4915{"lha", OP(42), OP_MASK, COM, PPCNONE, {RT, D, RA0}},
252b5132 4916
1cb0a767 4917{"lhau", OP(43), OP_MASK, COM, PPCNONE, {RT, D, RAL}},
252b5132 4918
1cb0a767 4919{"sth", OP(44), OP_MASK, COM, PPCNONE, {RS, D, RA0}},
252b5132 4920
1cb0a767 4921{"sthu", OP(45), OP_MASK, COM, PPCNONE, {RS, D, RAS}},
252b5132 4922
1cb0a767
PB		 4923{"lmw", OP(46), OP_MASK, PPCCOM, PPCNONE, {RT, D, RAM}},
4924{"lm", OP(46), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
252b5132 4925
1cb0a767
PB		 4926{"stmw", OP(47), OP_MASK, PPCCOM, PPCNONE, {RS, D, RA0}},
4927{"stm", OP(47), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}},
252b5132 4928
e01d869a 4929{"lfs", OP(48), OP_MASK, COM, PPCEFS, {FRT, D, RA0}},
252b5132 4930
e01d869a 4931{"lfsu", OP(49), OP_MASK, COM, PPCEFS, {FRT, D, RAS}},
252b5132 4932
e01d869a 4933{"lfd", OP(50), OP_MASK, COM, PPCEFS, {FRT, D, RA0}},
252b5132 4934
e01d869a 4935{"lfdu", OP(51), OP_MASK, COM, PPCEFS, {FRT, D, RAS}},
252b5132 4936
e01d869a 4937{"stfs", OP(52), OP_MASK, COM, PPCEFS, {FRS, D, RA0}},
adadcc0c 4938
e01d869a 4939{"stfsu", OP(53), OP_MASK, COM, PPCEFS, {FRS, D, RAS}},
252b5132 4940
e01d869a 4941{"stfd", OP(54), OP_MASK, COM, PPCEFS, {FRS, D, RA0}},
c3d65c1c 4942
e01d869a 4943{"stfdu", OP(55), OP_MASK, COM, PPCEFS, {FRS, D, RAS}},
252b5132 4944
9fe54b1c 4945{"lq", OP(56), OP_MASK, POWER4, PPC476, {RTQ, DQ, RAQ}},
1cb0a767 4946{"psq_l", OP(56), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}},
70dc4e32 4947{"lfq", OP(56), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}},
418c1742 4948
989993d8 4949{"lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRTp, D, RA0}},
1cb0a767 4950{"psq_lu", OP(57), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}},
70dc4e32 4951{"lfqu", OP(57), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}},
802a735e 4952
1cb0a767
PB		 4953{"ld", DSO(58,0), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}},
4954{"ldu", DSO(58,1), DS_MASK, PPC64, PPCNONE, {RT, DS, RAL}},
4955{"lwa", DSO(58,2), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}},
702f0fb4 4956
1cb0a767
PB		 4957{"dadd", XRC(59,2,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
4958{"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
252b5132 4959
1cb0a767
PB		 4960{"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}},
4961{"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}},
252b5132 4962
e01d869a
AM		 4963{"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
4964{"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
252b5132 4965
e01d869a
AM		 4966{"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
4967{"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
252b5132 4968
e01d869a
AM		 4969{"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
4970{"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
252b5132 4971
ce3d2015
AM		 4972{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN, {FRT, FRB}},
4973{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN, {FRT, FRB}},
252b5132 4974
066be9f7 4975{"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
70dc4e32 4976{"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
066be9f7 4977{"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
70dc4e32 4978{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
1ed8e1e4 4979
e01d869a
AM		 4980{"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS, {FRT, FRA, FRC}},
4981{"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS, {FRT, FRA, FRC}},
252b5132 4982
066be9f7 4983{"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
70dc4e32 4984{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
066be9f7 4985{"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
70dc4e32 4986{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
252b5132 4987
e01d869a
AM		 4988{"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
4989{"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
252b5132 4990
e01d869a
AM		 4991{"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
4992{"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
252b5132 4993
e01d869a
AM		 4994{"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
4995{"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
702f0fb4 4996
e01d869a
AM		 4997{"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
4998{"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
702f0fb4 4999
1cb0a767
PB		 5000{"dmul", XRC(59,34,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
5001{"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
702f0fb4 5002
1cb0a767
PB		 5003{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
5004{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
702f0fb4 5005
1cb0a767
PB		 5006{"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
5007{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
702f0fb4 5008
1cb0a767
PB		 5009{"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCNONE, {TE, FRT,FRB,RMC}},
5010{"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCNONE, {TE, FRT,FRB,RMC}},
702f0fb4 5011
1cb0a767
PB		 5012{"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
5013{"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
702f0fb4 5014
1cb0a767
PB		 5015{"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
5016{"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
702f0fb4 5017
1cb0a767 5018{"dcmpo", X(59,130), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
702f0fb4 5019
1cb0a767
PB		 5020{"dtstex", X(59,162), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
5021{"dtstdc", Z(59,194), Z_MASK, POWER6, PPCNONE, {BF, FRA, DCM}},
5022{"dtstdg", Z(59,226), Z_MASK, POWER6, PPCNONE, {BF, FRA, DGM}},
702f0fb4 5023
1cb0a767
PB		 5024{"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
5025{"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
702f0fb4 5026
1cb0a767
PB		 5027{"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
5028{"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
702f0fb4 5029
1cb0a767
PB		 5030{"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
5031{"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
702f0fb4 5032
1cb0a767
PB		 5033{"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}},
5034{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}},
702f0fb4 5035
1cb0a767
PB		 5036{"dxex", XRC(59,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
5037{"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
702f0fb4 5038
1cb0a767
PB		 5039{"dsub", XRC(59,514,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
5040{"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
702f0fb4 5041
1cb0a767
PB		 5042{"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
5043{"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
702f0fb4 5044
1cb0a767 5045{"dcmpu", X(59,642), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
702f0fb4 5046
1cb0a767 5047{"dtstsf", X(59,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
702f0fb4 5048
1cb0a767
PB		 5049{"drsp", XRC(59,770,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
5050{"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
702f0fb4 5051
066be9f7
PB		 5052{"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
5053{"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
5054
1cb0a767
PB		 5055{"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}},
5056{"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}},
252b5132 5057
e0d602ec
BE		 5058{"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
5059{"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
066be9f7 5060
1cb0a767
PB		 5061{"diex", XRC(59,866,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
5062{"diex.", XRC(59,866,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
8dbcd839 5063
e0d602ec
BE		 5064{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
5065{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
066be9f7 5066
066be9f7
PB		 5067{"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, SHW}},
5068{"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, XC6}},
5069{"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S, DMEX}},
1cb0a767 5070{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
066be9f7 5071{"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
1cb0a767
PB		 5072{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5073{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, DM}},
066be9f7
PB		 5074{"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5075{"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5076{"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5077{"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
5078{"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5079{"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5080{"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
5081{"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5082{"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5083{"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5084{"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5085{"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5086{"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
5087{"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5088{"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5089{"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5090{"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5091{"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5092{"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5093{"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5094{"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5095{"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5096{"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5097{"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5098{"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5099{"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5100{"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5101{"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5102{"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5103{"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5104{"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5105{"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5106{"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5107{"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5108{"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
5109{"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5110{"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5111{"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5112{"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5113{"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5114{"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5115{"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5116{"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
5117{"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5118{"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5119{"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5120{"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5121{"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5122{"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5123{"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5124{"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5125{"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5126{"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5127{"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
5128{"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5129{"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5130{"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5131{"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5132{"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5133{"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5134{"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5135{"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5136{"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5137{"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5138{"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5139{"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5140{"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5141{"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5142{"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCNONE, {XT6, XB6, UIM}},
5143{"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5144{"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5145{"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5146{"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5147{"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
5148{"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5149{"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5150{"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5151{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5152{"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5153{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5154{"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5155{"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5156{"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5157{"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5158{"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5159{"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5160{"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5161{"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5162{"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
5163{"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5164{"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5165{"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5166{"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5167{"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5168{"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5169{"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5170{"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5171{"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5172{"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5173{"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5174{"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5175{"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
5176{"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
1cb0a767
PB		 5177{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
5178{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
066be9f7
PB		 5179{"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5180{"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5181{"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5182{"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5183{"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5184{"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5185{"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5186{"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5187{"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5188{"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5189{"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5190{"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5191{"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5192{"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5193{"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5194{"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5195{"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5196{"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5197{"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5198{"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5199{"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5200{"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5201{"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5202{"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5203{"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5204{"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5205{"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5206{"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5207{"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
9b4e5766 5208
c72ab5f2 5209{"psq_st", OP(60), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
70dc4e32 5210{"stfq", OP(60), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}},
418c1742 5211
989993d8 5212{"stfdp", OP(61), OP_MASK, POWER6, POWER7, {FRSp, D, RA0}},
c72ab5f2 5213{"psq_stu", OP(61), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
70dc4e32 5214{"stfqu", OP(61), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}},
c72ab5f2 5215
1cb0a767
PB		 5216{"std", DSO(62,0), DS_MASK, PPC64, PPCNONE, {RS, DS, RA0}},
5217{"stdu", DSO(62,1), DS_MASK, PPC64, PPCNONE, {RS, DS, RAS}},
9fe54b1c 5218{"stq", DSO(62,2), DS_MASK, POWER4, PPC476, {RSQ, DS, RA0}},
fdd12ef3 5219
e01d869a 5220{"fcmpu", X(63,0), X_MASK|(3<<21), COM, PPCEFS, {BF, FRA, FRB}},
252b5132 5221
989993d8
JB		 5222{"daddq", XRC(63,2,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
5223{"daddq.", XRC(63,2,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
702f0fb4 5224
989993d8
JB		 5225{"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp, RMC}},
5226{"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp, RMC}},
702f0fb4 5227
9fe54b1c
PB		 5228{"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, FRA, FRB}},
5229{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, FRA, FRB}},
702f0fb4 5230
e01d869a
AM		 5231{"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
5232{"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
252b5132 5233
e01d869a 5234{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}},
81a0b7e2 5235{"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}},
e01d869a 5236{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}},
81a0b7e2 5237{"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}},
252b5132 5238
e01d869a 5239{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}},
81a0b7e2 5240{"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}},
e01d869a 5241{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}},
81a0b7e2 5242{"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}},
252b5132 5243
e01d869a 5244{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
1cb0a767 5245{"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
e01d869a 5246{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
1cb0a767 5247{"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
252b5132 5248
e01d869a 5249{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
1cb0a767 5250{"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
e01d869a 5251{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
1cb0a767 5252{"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
252b5132 5253
e01d869a 5254{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
1cb0a767 5255{"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
e01d869a 5256{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
1cb0a767 5257{"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
252b5132 5258
ce3d2015
AM		 5259{"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN, {FRT, FRB}},
5260{"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN, {FRT, FRB}},
252b5132 5261
e01d869a
AM		 5262{"fsel", A(63,23,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
5263{"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
252b5132 5264
066be9f7 5265{"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
70dc4e32 5266{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
066be9f7 5267{"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
70dc4e32 5268{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
1ed8e1e4 5269
e01d869a 5270{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC}},
1cb0a767 5271{"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}},
e01d869a 5272{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC}},
1cb0a767 5273{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}},
252b5132 5274
066be9f7 5275{"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
70dc4e32 5276{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
066be9f7 5277{"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
70dc4e32 5278{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
252b5132 5279
e01d869a 5280{"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
1cb0a767 5281{"fms", A(63,28,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
e01d869a 5282{"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
1cb0a767 5283{"fms.", A(63,28,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
252b5132 5284
e01d869a 5285{"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
1cb0a767 5286{"fma", A(63,29,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
e01d869a 5287{"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
1cb0a767 5288{"fma.", A(63,29,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
252b5132 5289
e01d869a 5290{"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
1cb0a767 5291{"fnms", A(63,30,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
e01d869a 5292{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
1cb0a767 5293{"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
252b5132 5294
e01d869a 5295{"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
1cb0a767 5296{"fnma", A(63,31,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
e01d869a 5297{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
1cb0a767 5298{"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
252b5132 5299
e01d869a 5300{"fcmpo", X(63,32), X_MASK|(3<<21), COM, PPCEFS, {BF, FRA, FRB}},
252b5132 5301
989993d8
JB		 5302{"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
5303{"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
702f0fb4 5304
a08fc942
PB		 5305{"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp, RMC}},
5306{"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp, RMC}},
702f0fb4 5307
1cb0a767
PB		 5308{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCNONE, {BT}},
5309{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCNONE, {BT}},
252b5132 5310
e01d869a
AM		 5311{"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
5312{"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
252b5132 5313
1cb0a767 5314{"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}},
252b5132 5315
989993d8
JB		 5316{"dscliq", ZRC(63,66,0), Z_MASK, POWER6, PPCNONE, {FRTp, FRAp, SH16}},
5317{"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, PPCNONE, {FRTp, FRAp, SH16}},
702f0fb4 5318
989993d8
JB		 5319{"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, PPCNONE, {TE, FRTp, FRBp, RMC}},
5320{"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, PPCNONE, {TE, FRTp, FRBp, RMC}},
702f0fb4 5321
1cb0a767
PB		 5322{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCNONE, {BT}},
5323{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCNONE, {BT}},
252b5132 5324
e01d869a
AM		 5325{"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
5326{"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
252b5132 5327
989993d8
JB		 5328{"dscriq", ZRC(63,98,0), Z_MASK, POWER6, PPCNONE, {FRTp, FRAp, SH16}},
5329{"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, PPCNONE, {FRTp, FRAp, SH16}},
702f0fb4 5330
989993d8
JB		 5331{"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}},
5332{"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}},
702f0fb4 5333
066be9f7
PB		 5334{"ftdiv", X(63,128), X_MASK|(3<<21), POWER7, PPCNONE, {BF, FRA, FRB}},
5335
989993d8 5336{"dcmpoq", X(63,130), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}},
702f0fb4 5337
9fe54b1c
PB		 5338{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
5339{"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
5340{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
5341{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
252b5132 5342
e01d869a
AM		 5343{"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
5344{"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
252b5132 5345
066be9f7
PB		 5346{"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
5347{"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
5348{"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
5349{"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
5350
5351{"ftsqrt", X(63,160), X_MASK|(3<<21|FRA_MASK), POWER7, PPCNONE, {BF, FRB}},
5352
a08fc942 5353{"dtstexq", X(63,162), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}},
989993d8
JB		 5354{"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCNONE, {BF, FRAp, DCM}},
5355{"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCNONE, {BF, FRAp, DGM}},
702f0fb4 5356
989993d8
JB		 5357{"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}},
5358{"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}},
702f0fb4 5359
a08fc942
PB		 5360{"dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCNONE, {FRTp, FRB}},
5361{"dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCNONE, {FRTp, FRB}},
702f0fb4 5362
e01d869a
AM		 5363{"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
5364{"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
252b5132 5365
a08fc942
PB		 5366{"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRBp}},
5367{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRBp}},
702f0fb4 5368
989993d8
JB		 5369{"ddedpdq", XRC(63,322,0), X_MASK, POWER6, PPCNONE, {SP, FRTp, FRBp}},
5370{"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, PPCNONE, {SP, FRTp, FRBp}},
702f0fb4 5371
a08fc942
PB		 5372{"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRBp}},
5373{"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRBp}},
702f0fb4 5374
1cb0a767
PB		 5375{"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
5376{"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
5377{"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
5378{"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
5379{"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
5380{"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
5381{"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
5382{"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
ce7a772b 5383
989993d8
JB		 5384{"dsubq", XRC(63,514,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
5385{"dsubq.", XRC(63,514,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
702f0fb4 5386
989993d8
JB		 5387{"ddivq", XRC(63,546,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
5388{"ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
702f0fb4 5389
e01d869a
AM		 5390{"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS, {FRT}},
5391{"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS, {FRT}},
252b5132 5392
989993d8 5393{"dcmpuq", X(63,642), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}},
702f0fb4 5394
a08fc942 5395{"dtstsfq", X(63,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRBp}},
702f0fb4 5396
9fe54b1c 5397{"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
e01d869a 5398{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS, {FLM, FRB}},
9fe54b1c 5399{"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
e01d869a 5400{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS, {FLM, FRB}},
252b5132 5401
989993d8
JB		 5402{"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCNONE, {FRTp, FRBp}},
5403{"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCNONE, {FRTp, FRBp}},
702f0fb4 5404
a08fc942
PB		 5405{"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCNONE, {FRTp, FRB}},
5406{"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCNONE, {FRTp, FRB}},
702f0fb4 5407
1cb0a767 5408{"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
9fe54b1c 5409{"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
1cb0a767 5410{"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
9fe54b1c 5411{"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
252b5132 5412
1cb0a767 5413{"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
9fe54b1c 5414{"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
1cb0a767 5415{"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
9fe54b1c 5416{"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
252b5132 5417
989993d8
JB		 5418{"denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCNONE, {S, FRTp, FRBp}},
5419{"denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCNONE, {S, FRTp, FRBp}},
702f0fb4 5420
1cb0a767 5421{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
9fe54b1c 5422{"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
1cb0a767 5423{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
9fe54b1c 5424{"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
252b5132 5425
a08fc942
PB		 5426{"diexq", XRC(63,866,0), X_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp}},
5427{"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp}},
702f0fb4 5428
e0d602ec
BE		 5429{"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
5430{"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
066be9f7 5431
e0d602ec
BE		 5432{"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
5433{"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
066be9f7 5434
e0d602ec
BE		 5435{"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
5436{"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
252b5132
RH		 5437};
5438
5439const int powerpc_num_opcodes =
5440 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
5441\f
5442/* The macro table. This is only used by the assembler. */
5443
5444/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
5445 when x=0; 32-x when x is between 1 and 31; are negative if x is
5446 negative; and are 32 or more otherwise. This is what you want
5447 when, for instance, you are emulating a right shift by a
5448 rotate-left-and-mask, because the underlying instructions support
5449 shifts of size 0 but not shifts of size 32. By comparison, when
5450 extracting x bits from some word you want to use just 32-x, because
5451 the underlying instructions don't support extracting 0 bits but do
5452 support extracting the whole word (32 bits in this case). */
5453
5454const struct powerpc_macro powerpc_macros[] = {
de866fcc
AM		 5455{"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"},
5456{"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"},
bdc7fcfe
AM		 5457{"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
5458{"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
de866fcc
AM		 5459{"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"},
5460{"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
5461{"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
5462{"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
5463{"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"},
5464{"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"},
5465{"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
5466{"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
5467{"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"},
5468{"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"},
5469{"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"},
5470{"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"},
5471
5472{"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
5473{"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
5474{"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
5475{"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
5476{"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
5477{"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
5478{"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
5479{"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
5480{"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
5481{"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
5482{"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
5483{"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
5484{"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
5485{"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
5486{"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5487{"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5488{"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5489{"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5490{"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
5491{"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
5492{"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
5493{"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
252b5132
RH		 5494};
5495
5496const int powerpc_num_macros =
5497 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
GDB Binutils - Deliverables
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