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include/opcode/
[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c
CommitLineData
252b5132 1/* ppc-opc.c -- PowerPC opcode list
112290ab 2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003
060d22b0 3 Free Software Foundation, Inc.
252b5132
RH		 4 Written by Ian Lance Taylor, Cygnus Support
5
112290ab 6 This file is part of GDB, GAS, and the GNU binutils.
252b5132 7
112290ab
NC		 8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
252b5132 12
112290ab
NC		 13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
252b5132 17
112290ab
NC		 18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
252b5132
RH		 22
23#include <stdio.h>
0d8dfecf 24#include "sysdep.h"
252b5132
RH		 25#include "opcode/ppc.h"
26#include "opintl.h"
27
28/* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
33 the .text section.
34
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
37 file. */
38\f
39/* Local insertion and extraction functions. */
40
802a735e
AM		 41static unsigned long insert_bat
42 PARAMS ((unsigned long, long, int, const char **));
43static long extract_bat
44 PARAMS ((unsigned long, int, int *));
45static unsigned long insert_bba
46 PARAMS ((unsigned long, long, int, const char **));
47static long extract_bba
48 PARAMS ((unsigned long, int, int *));
49static unsigned long insert_bd
50 PARAMS ((unsigned long, long, int, const char **));
51static long extract_bd
52 PARAMS ((unsigned long, int, int *));
53static unsigned long insert_bdm
54 PARAMS ((unsigned long, long, int, const char **));
55static long extract_bdm
56 PARAMS ((unsigned long, int, int *));
57static unsigned long insert_bdp
58 PARAMS ((unsigned long, long, int, const char **));
59static long extract_bdp
60 PARAMS ((unsigned long, int, int *));
61static int valid_bo
62 PARAMS ((long, int));
63static unsigned long insert_bo
64 PARAMS ((unsigned long, long, int, const char **));
65static long extract_bo
66 PARAMS ((unsigned long, int, int *));
67static unsigned long insert_boe
68 PARAMS ((unsigned long, long, int, const char **));
69static long extract_boe
70 PARAMS ((unsigned long, int, int *));
71static unsigned long insert_ds
72 PARAMS ((unsigned long, long, int, const char **));
73static long extract_ds
74 PARAMS ((unsigned long, int, int *));
75static unsigned long insert_de
76 PARAMS ((unsigned long, long, int, const char **));
77static long extract_de
78 PARAMS ((unsigned long, int, int *));
79static unsigned long insert_des
80 PARAMS ((unsigned long, long, int, const char **));
81static long extract_des
82 PARAMS ((unsigned long, int, int *));
83static unsigned long insert_li
84 PARAMS ((unsigned long, long, int, const char **));
85static long extract_li
86 PARAMS ((unsigned long, int, int *));
87static unsigned long insert_mbe
88 PARAMS ((unsigned long, long, int, const char **));
89static long extract_mbe
90 PARAMS ((unsigned long, int, int *));
91static unsigned long insert_mb6
92 PARAMS ((unsigned long, long, int, const char **));
93static long extract_mb6
94 PARAMS ((unsigned long, int, int *));
95static unsigned long insert_nb
96 PARAMS ((unsigned long, long, int, const char **));
97static long extract_nb
98 PARAMS ((unsigned long, int, int *));
99static unsigned long insert_nsi
100 PARAMS ((unsigned long, long, int, const char **));
101static long extract_nsi
102 PARAMS ((unsigned long, int, int *));
103static unsigned long insert_ral
104 PARAMS ((unsigned long, long, int, const char **));
105static unsigned long insert_ram
106 PARAMS ((unsigned long, long, int, const char **));
107static unsigned long insert_ras
108 PARAMS ((unsigned long, long, int, const char **));
109static unsigned long insert_rbs
110 PARAMS ((unsigned long, long, int, const char **));
111static long extract_rbs
112 PARAMS ((unsigned long, int, int *));
113static unsigned long insert_sh6
114 PARAMS ((unsigned long, long, int, const char **));
115static long extract_sh6
116 PARAMS ((unsigned long, int, int *));
117static unsigned long insert_spr
118 PARAMS ((unsigned long, long, int, const char **));
119static long extract_spr
120 PARAMS ((unsigned long, int, int *));
121static unsigned long insert_tbr
122 PARAMS ((unsigned long, long, int, const char **));
123static long extract_tbr
124 PARAMS ((unsigned long, int, int *));
23976049
EZ		 125static unsigned long insert_ev2
126 PARAMS ((unsigned long, long, int, const char **));
127static long extract_ev2
128 PARAMS ((unsigned long, int, int *));
129static unsigned long insert_ev4
130 PARAMS ((unsigned long, long, int, const char **));
131static long extract_ev4
132 PARAMS ((unsigned long, int, int *));
133static unsigned long insert_ev8
134 PARAMS ((unsigned long, long, int, const char **));
135static long extract_ev8
136 PARAMS ((unsigned long, int, int *));
252b5132
RH		 137\f
138/* The operands table.
139
140 The fields are bits, shift, insert, extract, flags.
141
142 We used to put parens around the various additions, like the one
143 for BA just below. However, that caused trouble with feeble
144 compilers with a limit on depth of a parenthesized expression, like
145 (reportedly) the compiler in Microsoft Developer Studio 5. So we
146 omit the parens, since the macros are never used in a context where
147 the addition will be ambiguous. */
148
149const struct powerpc_operand powerpc_operands[] =
150{
151 /* The zero index is used to indicate the end of the list of
152 operands. */
153#define UNUSED 0
11b37b7b 154 { 0, 0, 0, 0, 0 },
252b5132
RH		 155
156 /* The BA field in an XL form instruction. */
157#define BA UNUSED + 1
158#define BA_MASK (0x1f << 16)
11b37b7b 159 { 5, 16, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 160
161 /* The BA field in an XL form instruction when it must be the same
162 as the BT field in the same instruction. */
163#define BAT BA + 1
11b37b7b 164 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
252b5132
RH		 165
166 /* The BB field in an XL form instruction. */
167#define BB BAT + 1
168#define BB_MASK (0x1f << 11)
11b37b7b 169 { 5, 11, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 170
171 /* The BB field in an XL form instruction when it must be the same
172 as the BA field in the same instruction. */
173#define BBA BB + 1
11b37b7b 174 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
252b5132
RH		 175
176 /* The BD field in a B form instruction. The lower two bits are
177 forced to zero. */
178#define BD BBA + 1
11b37b7b 179 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 180
181 /* The BD field in a B form instruction when absolute addressing is
182 used. */
183#define BDA BD + 1
11b37b7b 184 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 185
186 /* The BD field in a B form instruction when the - modifier is used.
187 This sets the y bit of the BO field appropriately. */
188#define BDM BDA + 1
11b37b7b
AM		 189 { 16, 0, insert_bdm, extract_bdm,
190 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 191
192 /* The BD field in a B form instruction when the - modifier is used
193 and absolute address is used. */
194#define BDMA BDM + 1
11b37b7b
AM		 195 { 16, 0, insert_bdm, extract_bdm,
196 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 197
198 /* The BD field in a B form instruction when the + modifier is used.
199 This sets the y bit of the BO field appropriately. */
200#define BDP BDMA + 1
11b37b7b
AM		 201 { 16, 0, insert_bdp, extract_bdp,
202 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 203
204 /* The BD field in a B form instruction when the + modifier is used
205 and absolute addressing is used. */
206#define BDPA BDP + 1
11b37b7b
AM		 207 { 16, 0, insert_bdp, extract_bdp,
208 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 209
210 /* The BF field in an X or XL form instruction. */
211#define BF BDPA + 1
11b37b7b 212 { 3, 23, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 213
214 /* An optional BF field. This is used for comparison instructions,
215 in which an omitted BF field is taken as zero. */
216#define OBF BF + 1
11b37b7b 217 { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132
RH		 218
219 /* The BFA field in an X or XL form instruction. */
220#define BFA OBF + 1
11b37b7b 221 { 3, 18, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 222
223 /* The BI field in a B form or XL form instruction. */
224#define BI BFA + 1
225#define BI_MASK (0x1f << 16)
11b37b7b 226 { 5, 16, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 227
228 /* The BO field in a B form instruction. Certain values are
229 illegal. */
230#define BO BI + 1
231#define BO_MASK (0x1f << 21)
11b37b7b 232 { 5, 21, insert_bo, extract_bo, 0 },
252b5132
RH		 233
234 /* The BO field in a B form instruction when the + or - modifier is
235 used. This is like the BO field, but it must be even. */
236#define BOE BO + 1
11b37b7b 237 { 5, 21, insert_boe, extract_boe, 0 },
252b5132
RH		 238
239 /* The BT field in an X or XL form instruction. */
240#define BT BOE + 1
11b37b7b 241 { 5, 21, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 242
243 /* The condition register number portion of the BI field in a B form
244 or XL form instruction. This is used for the extended
245 conditional branch mnemonics, which set the lower two bits of the
246 BI field. This field is optional. */
247#define CR BT + 1
11b37b7b 248 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132 249
23976049
EZ		 250 /* The CRB field in an X form instruction. */
251#define CRB CR + 1
252 { 5, 6, 0, 0, 0 },
253
254 /* The CRFD field in an X form instruction. */
255#define CRFD CRB + 1
0ec499f7 256 { 3, 23, 0, 0, PPC_OPERAND_CR },
23976049
EZ		 257
258 /* The CRFS field in an X form instruction. */
259#define CRFS CRFD + 1
0ec499f7 260 { 3, 0, 0, 0, PPC_OPERAND_CR },
23976049 261
418c1742 262 /* The CT field in an X form instruction. */
23976049 263#define CT CRFS + 1
1f613cde 264 { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
418c1742 265
252b5132
RH		 266 /* The D field in a D form instruction. This is a displacement off
267 a register, and implies that the next operand is a register in
268 parentheses. */
418c1742 269#define D CT + 1
11b37b7b 270 { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
252b5132 271
418c1742
MG		 272 /* The DE field in a DE form instruction. This is like D, but is 12
273 bits only. */
274#define DE D + 1
275 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
276
277 /* The DES field in a DES form instruction. This is like DS, but is 14
278 bits only (12 stored.) */
279#define DES DE + 1
280 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
281
252b5132
RH		 282 /* The DS field in a DS form instruction. This is like D, but the
283 lower two bits are forced to zero. */
418c1742 284#define DS DES + 1
6ba045b1
AM		 285 { 16, 0, insert_ds, extract_ds,
286 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
252b5132
RH		 287
288 /* The E field in a wrteei instruction. */
289#define E DS + 1
11b37b7b 290 { 1, 15, 0, 0, 0 },
252b5132
RH		 291
292 /* The FL1 field in a POWER SC form instruction. */
293#define FL1 E + 1
11b37b7b 294 { 4, 12, 0, 0, 0 },
252b5132
RH		 295
296 /* The FL2 field in a POWER SC form instruction. */
297#define FL2 FL1 + 1
11b37b7b 298 { 3, 2, 0, 0, 0 },
252b5132
RH		 299
300 /* The FLM field in an XFL form instruction. */
301#define FLM FL2 + 1
11b37b7b 302 { 8, 17, 0, 0, 0 },
252b5132
RH		 303
304 /* The FRA field in an X or A form instruction. */
305#define FRA FLM + 1
306#define FRA_MASK (0x1f << 16)
11b37b7b 307 { 5, 16, 0, 0, PPC_OPERAND_FPR },
252b5132
RH		 308
309 /* The FRB field in an X or A form instruction. */
310#define FRB FRA + 1
311#define FRB_MASK (0x1f << 11)
11b37b7b 312 { 5, 11, 0, 0, PPC_OPERAND_FPR },
252b5132
RH		 313
314 /* The FRC field in an A form instruction. */
315#define FRC FRB + 1
316#define FRC_MASK (0x1f << 6)
11b37b7b 317 { 5, 6, 0, 0, PPC_OPERAND_FPR },
252b5132
RH		 318
319 /* The FRS field in an X form instruction or the FRT field in a D, X
320 or A form instruction. */
321#define FRS FRC + 1
322#define FRT FRS
11b37b7b 323 { 5, 21, 0, 0, PPC_OPERAND_FPR },
252b5132
RH		 324
325 /* The FXM field in an XFX instruction. */
326#define FXM FRS + 1
327#define FXM_MASK (0xff << 12)
11b37b7b 328 { 8, 12, 0, 0, 0 },
252b5132
RH		 329
330 /* The L field in a D or X form instruction. */
331#define L FXM + 1
11b37b7b 332 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
252b5132
RH		 333
334 /* The LEV field in a POWER SC form instruction. */
335#define LEV L + 1
11b37b7b 336 { 7, 5, 0, 0, 0 },
252b5132
RH		 337
338 /* The LI field in an I form instruction. The lower two bits are
339 forced to zero. */
340#define LI LEV + 1
11b37b7b 341 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 342
343 /* The LI field in an I form instruction when used as an absolute
344 address. */
345#define LIA LI + 1
11b37b7b 346 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132 347
6ba045b1
AM		 348 /* The LS field in an X (sync) form instruction. */
349#define LS LIA + 1
350 { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
351
252b5132 352 /* The MB field in an M form instruction. */
6ba045b1 353#define MB LS + 1
252b5132 354#define MB_MASK (0x1f << 6)
11b37b7b 355 { 5, 6, 0, 0, 0 },
252b5132
RH		 356
357 /* The ME field in an M form instruction. */
358#define ME MB + 1
359#define ME_MASK (0x1f << 1)
11b37b7b 360 { 5, 1, 0, 0, 0 },
252b5132
RH		 361
362 /* The MB and ME fields in an M form instruction expressed a single
363 operand which is a bitmask indicating which bits to select. This
364 is a two operand form using PPC_OPERAND_NEXT. See the
365 description in opcode/ppc.h for what this means. */
366#define MBE ME + 1
11b37b7b
AM		 367 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
368 { 32, 0, insert_mbe, extract_mbe, 0 },
252b5132
RH		 369
370 /* The MB or ME field in an MD or MDS form instruction. The high
371 bit is wrapped to the low end. */
372#define MB6 MBE + 2
373#define ME6 MB6
374#define MB6_MASK (0x3f << 5)
11b37b7b 375 { 6, 5, insert_mb6, extract_mb6, 0 },
252b5132 376
9fa87a06
MG		 377 /* The MO field in an mbar instruction. */
378#define MO MB6 + 1
379 { 5, 21, 0, 0, 0 },
380
252b5132
RH		 381 /* The NB field in an X form instruction. The value 32 is stored as
382 0. */
9fa87a06 383#define NB MO + 1
11b37b7b 384 { 6, 11, insert_nb, extract_nb, 0 },
252b5132
RH		 385
386 /* The NSI field in a D form instruction. This is the same as the
387 SI field, only negated. */
388#define NSI NB + 1
389 { 16, 0, insert_nsi, extract_nsi,
11b37b7b 390 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 391
392 /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
914749f6 393#define RA NSI + 1
252b5132 394#define RA_MASK (0x1f << 16)
11b37b7b 395 { 5, 16, 0, 0, PPC_OPERAND_GPR },
252b5132
RH		 396
397 /* The RA field in a D or X form instruction which is an updating
398 load, which means that the RA field may not be zero and may not
399 equal the RT field. */
400#define RAL RA + 1
11b37b7b 401 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
252b5132
RH		 402
403 /* The RA field in an lmw instruction, which has special value
404 restrictions. */
405#define RAM RAL + 1
11b37b7b 406 { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
252b5132
RH		 407
408 /* The RA field in a D or X form instruction which is an updating
409 store or an updating floating point load, which means that the RA
410 field may not be zero. */
411#define RAS RAM + 1
11b37b7b 412 { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
252b5132
RH		 413
414 /* The RB field in an X, XO, M, or MDS form instruction. */
415#define RB RAS + 1
416#define RB_MASK (0x1f << 11)
11b37b7b 417 { 5, 11, 0, 0, PPC_OPERAND_GPR },
252b5132
RH		 418
419 /* The RB field in an X form instruction when it must be the same as
420 the RS field in the instruction. This is used for extended
421 mnemonics like mr. */
422#define RBS RB + 1
11b37b7b 423 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
252b5132
RH		 424
425 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
426 instruction or the RT field in a D, DS, X, XFX or XO form
427 instruction. */
428#define RS RBS + 1
429#define RT RS
430#define RT_MASK (0x1f << 21)
11b37b7b 431 { 5, 21, 0, 0, PPC_OPERAND_GPR },
252b5132
RH		 432
433 /* The SH field in an X or M form instruction. */
434#define SH RS + 1
435#define SH_MASK (0x1f << 11)
11b37b7b 436 { 5, 11, 0, 0, 0 },
252b5132
RH		 437
438 /* The SH field in an MD form instruction. This is split. */
439#define SH6 SH + 1
440#define SH6_MASK ((0x1f << 11) | (1 << 1))
11b37b7b 441 { 6, 1, insert_sh6, extract_sh6, 0 },
252b5132
RH		 442
443 /* The SI field in a D form instruction. */
444#define SI SH6 + 1
11b37b7b 445 { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
252b5132
RH		 446
447 /* The SI field in a D form instruction when we accept a wide range
448 of positive values. */
449#define SISIGNOPT SI + 1
11b37b7b 450 { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
252b5132
RH		 451
452 /* The SPR field in an XFX form instruction. This is flipped--the
453 lower 5 bits are stored in the upper 5 and vice- versa. */
454#define SPR SISIGNOPT + 1
914749f6 455#define PMR SPR
252b5132 456#define SPR_MASK (0x3ff << 11)
11b37b7b 457 { 10, 11, insert_spr, extract_spr, 0 },
252b5132
RH		 458
459 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
460#define SPRBAT SPR + 1
461#define SPRBAT_MASK (0x3 << 17)
11b37b7b 462 { 2, 17, 0, 0, 0 },
252b5132
RH		 463
464 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
465#define SPRG SPRBAT + 1
466#define SPRG_MASK (0x3 << 16)
11b37b7b 467 { 2, 16, 0, 0, 0 },
252b5132
RH		 468
469 /* The SR field in an X form instruction. */
470#define SR SPRG + 1
11b37b7b 471 { 4, 16, 0, 0, 0 },
252b5132 472
f5c120c5
MG		 473 /* The STRM field in an X AltiVec form instruction. */
474#define STRM SR + 1
475#define STRM_MASK (0x3 << 21)
476 { 2, 21, 0, 0, 0 },
477
252b5132 478 /* The SV field in a POWER SC form instruction. */
f5c120c5 479#define SV STRM + 1
11b37b7b 480 { 14, 2, 0, 0, 0 },
252b5132
RH		 481
482 /* The TBR field in an XFX form instruction. This is like the SPR
483 field, but it is optional. */
484#define TBR SV + 1
11b37b7b 485 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
252b5132
RH		 486
487 /* The TO field in a D or X form instruction. */
488#define TO TBR + 1
489#define TO_MASK (0x1f << 21)
11b37b7b 490 { 5, 21, 0, 0, 0 },
252b5132
RH		 491
492 /* The U field in an X form instruction. */
493#define U TO + 1
11b37b7b 494 { 4, 12, 0, 0, 0 },
252b5132
RH		 495
496 /* The UI field in a D form instruction. */
497#define UI U + 1
11b37b7b 498 { 16, 0, 0, 0, 0 },
786e2c0f 499
112290ab 500 /* The VA field in a VA, VX or VXR form instruction. */
786e2c0f
C		 501#define VA UI + 1
502#define VA_MASK (0x1f << 16)
6ba045b1 503 { 5, 16, 0, 0, PPC_OPERAND_VR },
786e2c0f 504
112290ab 505 /* The VB field in a VA, VX or VXR form instruction. */
786e2c0f
C		 506#define VB VA + 1
507#define VB_MASK (0x1f << 11)
6ba045b1 508 { 5, 11, 0, 0, PPC_OPERAND_VR },
786e2c0f 509
112290ab 510 /* The VC field in a VA form instruction. */
786e2c0f
C		 511#define VC VB + 1
512#define VC_MASK (0x1f << 6)
6ba045b1 513 { 5, 6, 0, 0, PPC_OPERAND_VR },
786e2c0f 514
112290ab 515 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
786e2c0f
C		 516#define VD VC + 1
517#define VS VD
518#define VD_MASK (0x1f << 21)
6ba045b1 519 { 5, 21, 0, 0, PPC_OPERAND_VR },
786e2c0f 520
112290ab 521 /* The SIMM field in a VX form instruction. */
786e2c0f 522#define SIMM VD + 1
11b37b7b 523 { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
786e2c0f 524
112290ab 525 /* The UIMM field in a VX form instruction. */
786e2c0f 526#define UIMM SIMM + 1
11b37b7b 527 { 5, 16, 0, 0, 0 },
786e2c0f 528
112290ab 529 /* The SHB field in a VA form instruction. */
786e2c0f 530#define SHB UIMM + 1
11b37b7b 531 { 4, 6, 0, 0, 0 },
ff3a6ee3 532
112290ab 533 /* The other UIMM field in a EVX form instruction. */
23976049
EZ		 534#define EVUIMM SHB + 1
535 { 5, 11, 0, 0, 0 },
536
112290ab 537 /* The other UIMM field in a half word EVX form instruction. */
23976049 538#define EVUIMM_2 EVUIMM + 1
95e172a5 539 { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
23976049 540
112290ab 541 /* The other UIMM field in a word EVX form instruction. */
23976049 542#define EVUIMM_4 EVUIMM_2 + 1
95e172a5 543 { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
23976049 544
112290ab 545 /* The other UIMM field in a double EVX form instruction. */
23976049 546#define EVUIMM_8 EVUIMM_4 + 1
ced05688 547 { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
23976049 548
ff3a6ee3 549 /* The WS field. */
23976049 550#define WS EVUIMM_8 + 1
ff3a6ee3
TR		 551#define WS_MASK (0x7 << 11)
552 { 3, 11, 0, 0, 0 },
553
5ae2e65e
AM		 554 /* The L field in an mtmsrd instruction */
555#define MTMSRD_L WS + 1
556 { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL },
557
252b5132
RH		 558};
559
560/* The functions used to insert and extract complicated operands. */
561
562/* The BA field in an XL form instruction when it must be the same as
563 the BT field in the same instruction. This operand is marked FAKE.
564 The insertion function just copies the BT field into the BA field,
565 and the extraction function just checks that the fields are the
566 same. */
567
568/*ARGSUSED*/
569static unsigned long
802a735e 570insert_bat (insn, value, dialect, errmsg)
252b5132 571 unsigned long insn;
9aaaa291 572 long value ATTRIBUTE_UNUSED;
802a735e 573 int dialect ATTRIBUTE_UNUSED;
9aaaa291 574 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 575{
576 return insn | (((insn >> 21) & 0x1f) << 16);
577}
578
579static long
802a735e 580extract_bat (insn, dialect, invalid)
252b5132 581 unsigned long insn;
802a735e 582 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 583 int *invalid;
584{
585 if (invalid != (int *) NULL
586 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
587 *invalid = 1;
588 return 0;
589}
590
591/* The BB field in an XL form instruction when it must be the same as
592 the BA field in the same instruction. This operand is marked FAKE.
593 The insertion function just copies the BA field into the BB field,
594 and the extraction function just checks that the fields are the
595 same. */
596
597/*ARGSUSED*/
598static unsigned long
802a735e 599insert_bba (insn, value, dialect, errmsg)
252b5132 600 unsigned long insn;
9aaaa291 601 long value ATTRIBUTE_UNUSED;
802a735e 602 int dialect ATTRIBUTE_UNUSED;
9aaaa291 603 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 604{
605 return insn | (((insn >> 16) & 0x1f) << 11);
606}
607
608static long
802a735e 609extract_bba (insn, dialect, invalid)
252b5132 610 unsigned long insn;
802a735e 611 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 612 int *invalid;
613{
614 if (invalid != (int *) NULL
615 && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
616 *invalid = 1;
617 return 0;
618}
619
620/* The BD field in a B form instruction. The lower two bits are
621 forced to zero. */
622
623/*ARGSUSED*/
624static unsigned long
802a735e 625insert_bd (insn, value, dialect, errmsg)
252b5132
RH		 626 unsigned long insn;
627 long value;
802a735e 628 int dialect ATTRIBUTE_UNUSED;
9aaaa291 629 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 630{
631 return insn | (value & 0xfffc);
632}
633
634/*ARGSUSED*/
635static long
802a735e 636extract_bd (insn, dialect, invalid)
252b5132 637 unsigned long insn;
802a735e 638 int dialect ATTRIBUTE_UNUSED;
9aaaa291 639 int *invalid ATTRIBUTE_UNUSED;
252b5132 640{
802a735e 641 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 642}
643
644/* The BD field in a B form instruction when the - modifier is used.
645 This modifier means that the branch is not expected to be taken.
94efba12
AM		 646 For chips built to versions of the architecture prior to version 2
647 (ie. not Power4 compatible), we set the y bit of the BO field to 1
648 if the offset is negative. When extracting, we require that the y
649 bit be 1 and that the offset be positive, since if the y bit is 0
650 we just want to print the normal form of the instruction.
651 Power4 compatible targets use two bits, "a", and "t", instead of
652 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
653 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
654 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
655 for branch on CTR. We only handle the taken/not-taken hint here. */
252b5132
RH		 656
657/*ARGSUSED*/
658static unsigned long
802a735e 659insert_bdm (insn, value, dialect, errmsg)
252b5132
RH		 660 unsigned long insn;
661 long value;
802a735e 662 int dialect;
9aaaa291 663 const char **errmsg ATTRIBUTE_UNUSED;
252b5132 664{
94efba12 665 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 666 {
667 if ((value & 0x8000) != 0)
668 insn |= 1 << 21;
669 }
670 else
671 {
672 if ((insn & (0x14 << 21)) == (0x04 << 21))
673 insn |= 0x02 << 21;
674 else if ((insn & (0x14 << 21)) == (0x10 << 21))
675 insn |= 0x08 << 21;
676 }
252b5132
RH		 677 return insn | (value & 0xfffc);
678}
679
680static long
802a735e 681extract_bdm (insn, dialect, invalid)
252b5132 682 unsigned long insn;
802a735e 683 int dialect;
252b5132
RH		 684 int *invalid;
685{
802a735e
AM		 686 if (invalid != (int *) NULL)
687 {
94efba12 688 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 689 {
690 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
691 *invalid = 1;
692 }
693 else
694 {
695 if ((insn & (0x17 << 21)) != (0x06 << 21)
696 && (insn & (0x1d << 21)) != (0x18 << 21))
697 *invalid = 1;
698 }
699 }
700 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 701}
702
703/* The BD field in a B form instruction when the + modifier is used.
704 This is like BDM, above, except that the branch is expected to be
705 taken. */
706
707/*ARGSUSED*/
708static unsigned long
802a735e 709insert_bdp (insn, value, dialect, errmsg)
252b5132
RH		 710 unsigned long insn;
711 long value;
802a735e 712 int dialect;
9aaaa291 713 const char **errmsg ATTRIBUTE_UNUSED;
252b5132 714{
94efba12 715 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 716 {
717 if ((value & 0x8000) == 0)
718 insn |= 1 << 21;
719 }
720 else
721 {
722 if ((insn & (0x14 << 21)) == (0x04 << 21))
723 insn |= 0x03 << 21;
724 else if ((insn & (0x14 << 21)) == (0x10 << 21))
725 insn |= 0x09 << 21;
726 }
252b5132
RH		 727 return insn | (value & 0xfffc);
728}
729
730static long
802a735e 731extract_bdp (insn, dialect, invalid)
252b5132 732 unsigned long insn;
802a735e 733 int dialect;
252b5132
RH		 734 int *invalid;
735{
802a735e
AM		 736 if (invalid != (int *) NULL)
737 {
94efba12 738 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 739 {
740 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
741 *invalid = 1;
742 }
743 else
744 {
745 if ((insn & (0x17 << 21)) != (0x07 << 21)
746 && (insn & (0x1d << 21)) != (0x19 << 21))
747 *invalid = 1;
748 }
749 }
750 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 751}
752
753/* Check for legal values of a BO field. */
754
755static int
802a735e 756valid_bo (value, dialect)
252b5132 757 long value;
802a735e 758 int dialect;
252b5132 759{
94efba12 760 if ((dialect & PPC_OPCODE_POWER4) == 0)
252b5132 761 {
802a735e
AM		 762 /* Certain encodings have bits that are required to be zero.
763 These are (z must be zero, y may be anything):
764 001zy
765 011zy
766 1z00y
767 1z01y
768 1z1zz
769 */
770 switch (value & 0x14)
771 {
772 default:
773 case 0:
774 return 1;
775 case 0x4:
776 return (value & 0x2) == 0;
777 case 0x10:
778 return (value & 0x8) == 0;
779 case 0x14:
780 return value == 0x14;
781 }
782 }
783 else
784 {
785 /* Certain encodings have bits that are required to be zero.
786 These are (z must be zero, a & t may be anything):
787 0000z
788 0001z
789 0100z
790 0101z
791 001at
792 011at
793 1a00t
794 1a01t
795 1z1zz
796 */
797 if ((value & 0x14) == 0)
798 return (value & 0x1) == 0;
799 else if ((value & 0x14) == 0x14)
800 return value == 0x14;
801 else
802 return 1;
252b5132
RH		 803 }
804}
805
806/* The BO field in a B form instruction. Warn about attempts to set
807 the field to an illegal value. */
808
809static unsigned long
802a735e 810insert_bo (insn, value, dialect, errmsg)
252b5132
RH		 811 unsigned long insn;
812 long value;
802a735e 813 int dialect;
252b5132
RH		 814 const char **errmsg;
815{
816 if (errmsg != (const char **) NULL
802a735e 817 && ! valid_bo (value, dialect))
252b5132
RH		 818 *errmsg = _("invalid conditional option");
819 return insn | ((value & 0x1f) << 21);
820}
821
822static long
802a735e 823extract_bo (insn, dialect, invalid)
252b5132 824 unsigned long insn;
802a735e 825 int dialect;
252b5132
RH		 826 int *invalid;
827{
828 long value;
829
830 value = (insn >> 21) & 0x1f;
831 if (invalid != (int *) NULL
802a735e 832 && ! valid_bo (value, dialect))
252b5132
RH		 833 *invalid = 1;
834 return value;
835}
836
837/* The BO field in a B form instruction when the + or - modifier is
838 used. This is like the BO field, but it must be even. When
839 extracting it, we force it to be even. */
840
841static unsigned long
802a735e 842insert_boe (insn, value, dialect, errmsg)
252b5132
RH		 843 unsigned long insn;
844 long value;
802a735e 845 int dialect;
252b5132
RH		 846 const char **errmsg;
847{
848 if (errmsg != (const char **) NULL)
849 {
802a735e 850 if (! valid_bo (value, dialect))
252b5132
RH		 851 *errmsg = _("invalid conditional option");
852 else if ((value & 1) != 0)
853 *errmsg = _("attempt to set y bit when using + or - modifier");
854 }
855 return insn | ((value & 0x1f) << 21);
856}
857
858static long
802a735e 859extract_boe (insn, dialect, invalid)
252b5132 860 unsigned long insn;
802a735e 861 int dialect;
252b5132
RH		 862 int *invalid;
863{
864 long value;
865
866 value = (insn >> 21) & 0x1f;
867 if (invalid != (int *) NULL
802a735e 868 && ! valid_bo (value, dialect))
252b5132
RH		 869 *invalid = 1;
870 return value & 0x1e;
871}
872
23976049
EZ		 873static unsigned long
874insert_ev2 (insn, value, dialect, errmsg)
875 unsigned long insn;
876 long value;
877 int dialect ATTRIBUTE_UNUSED;
878 const char ** errmsg ATTRIBUTE_UNUSED;
879{
880 if ((value & 1) != 0 && errmsg != NULL)
881 *errmsg = _("offset not a multiple of 2");
882 if ((value > 62) != 0 && errmsg != NULL)
883 *errmsg = _("offset greater than 62");
914749f6 884 return insn | ((value & 0x3e) << 10);
23976049
EZ		 885}
886
887static long
888extract_ev2 (insn, dialect, invalid)
889 unsigned long insn;
890 int dialect ATTRIBUTE_UNUSED;
891 int * invalid ATTRIBUTE_UNUSED;
892{
914749f6 893 return (insn >> 10) & 0x3e;
23976049
EZ		 894}
895
896static unsigned long
897insert_ev4 (insn, value, dialect, errmsg)
898 unsigned long insn;
899 long value;
900 int dialect ATTRIBUTE_UNUSED;
901 const char ** errmsg ATTRIBUTE_UNUSED;
902{
903 if ((value & 3) != 0 && errmsg != NULL)
904 *errmsg = _("offset not a multiple of 4");
905 if ((value > 124) != 0 && errmsg != NULL)
906 *errmsg = _("offset greater than 124");
914749f6 907 return insn | ((value & 0x7c) << 9);
23976049
EZ		 908}
909
910static long
911extract_ev4 (insn, dialect, invalid)
912 unsigned long insn;
913 int dialect ATTRIBUTE_UNUSED;
914 int * invalid ATTRIBUTE_UNUSED;
915{
914749f6 916 return (insn >> 9) & 0x7c;
23976049
EZ		 917}
918
919static unsigned long
920insert_ev8 (insn, value, dialect, errmsg)
921 unsigned long insn;
922 long value;
923 int dialect ATTRIBUTE_UNUSED;
924 const char ** errmsg ATTRIBUTE_UNUSED;
925{
926 if ((value & 7) != 0 && errmsg != NULL)
927 *errmsg = _("offset not a multiple of 8");
928 if ((value > 248) != 0 && errmsg != NULL)
929 *errmsg = _("offset greater than 248");
930 return insn | ((value & 0xf8) << 8);
931}
932
933static long
934extract_ev8 (insn, dialect, invalid)
935 unsigned long insn;
936 int dialect ATTRIBUTE_UNUSED;
937 int * invalid ATTRIBUTE_UNUSED;
938{
939 return (insn >> 8) & 0xf8;
940}
941
252b5132
RH		 942/* The DS field in a DS form instruction. This is like D, but the
943 lower two bits are forced to zero. */
944
945/*ARGSUSED*/
946static unsigned long
802a735e 947insert_ds (insn, value, dialect, errmsg)
252b5132
RH		 948 unsigned long insn;
949 long value;
802a735e 950 int dialect ATTRIBUTE_UNUSED;
418c1742 951 const char **errmsg;
252b5132 952{
6ba045b1
AM		 953 if ((value & 3) != 0 && errmsg != NULL)
954 *errmsg = _("offset not a multiple of 4");
252b5132
RH		 955 return insn | (value & 0xfffc);
956}
957
958/*ARGSUSED*/
959static long
802a735e 960extract_ds (insn, dialect, invalid)
252b5132 961 unsigned long insn;
802a735e 962 int dialect ATTRIBUTE_UNUSED;
9aaaa291 963 int *invalid ATTRIBUTE_UNUSED;
252b5132 964{
802a735e 965 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 966}
967
418c1742
MG		 968/* The DE field in a DE form instruction. */
969
970/*ARGSUSED*/
971static unsigned long
802a735e 972insert_de (insn, value, dialect, errmsg)
418c1742
MG		 973 unsigned long insn;
974 long value;
802a735e 975 int dialect ATTRIBUTE_UNUSED;
418c1742
MG		 976 const char **errmsg;
977{
978 if ((value > 2047 || value < -2048) && errmsg != NULL)
979 *errmsg = _("offset not between -2048 and 2047");
980 return insn | ((value << 4) & 0xfff0);
981}
982
983/*ARGSUSED*/
984static long
802a735e 985extract_de (insn, dialect, invalid)
418c1742 986 unsigned long insn;
802a735e 987 int dialect ATTRIBUTE_UNUSED;
418c1742
MG		 988 int *invalid ATTRIBUTE_UNUSED;
989{
990 return (insn & 0xfff0) >> 4;
991}
992
993/* The DES field in a DES form instruction. */
994
995/*ARGSUSED*/
996static unsigned long
802a735e 997insert_des (insn, value, dialect, errmsg)
418c1742
MG		 998 unsigned long insn;
999 long value;
802a735e 1000 int dialect ATTRIBUTE_UNUSED;
418c1742
MG		 1001 const char **errmsg;
1002{
1003 if ((value > 8191 || value < -8192) && errmsg != NULL)
1004 *errmsg = _("offset not between -8192 and 8191");
1005 else if ((value & 3) != 0 && errmsg != NULL)
1006 *errmsg = _("offset not a multiple of 4");
1007 return insn | ((value << 2) & 0xfff0);
1008}
1009
1010/*ARGSUSED*/
1011static long
802a735e 1012extract_des (insn, dialect, invalid)
418c1742 1013 unsigned long insn;
802a735e 1014 int dialect ATTRIBUTE_UNUSED;
418c1742
MG		 1015 int *invalid ATTRIBUTE_UNUSED;
1016{
802a735e 1017 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
418c1742
MG		 1018}
1019
252b5132
RH		 1020/* The LI field in an I form instruction. The lower two bits are
1021 forced to zero. */
1022
1023/*ARGSUSED*/
1024static unsigned long
802a735e 1025insert_li (insn, value, dialect, errmsg)
252b5132
RH		 1026 unsigned long insn;
1027 long value;
802a735e 1028 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1029 const char **errmsg;
1030{
1031 if ((value & 3) != 0 && errmsg != (const char **) NULL)
1032 *errmsg = _("ignoring least significant bits in branch offset");
1033 return insn | (value & 0x3fffffc);
1034}
1035
1036/*ARGSUSED*/
1037static long
802a735e 1038extract_li (insn, dialect, invalid)
252b5132 1039 unsigned long insn;
802a735e 1040 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1041 int *invalid ATTRIBUTE_UNUSED;
252b5132 1042{
802a735e 1043 return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
252b5132
RH		 1044}
1045
1046/* The MB and ME fields in an M form instruction expressed as a single
1047 operand which is itself a bitmask. The extraction function always
1048 marks it as invalid, since we never want to recognize an
1049 instruction which uses a field of this type. */
1050
1051static unsigned long
802a735e 1052insert_mbe (insn, value, dialect, errmsg)
252b5132
RH		 1053 unsigned long insn;
1054 long value;
802a735e 1055 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1056 const char **errmsg;
1057{
1058 unsigned long uval, mask;
1059 int mb, me, mx, count, last;
1060
1061 uval = value;
1062
1063 if (uval == 0)
1064 {
1065 if (errmsg != (const char **) NULL)
1066 *errmsg = _("illegal bitmask");
1067 return insn;
1068 }
1069
1070 mb = 0;
1071 me = 32;
1072 if ((uval & 1) != 0)
1073 last = 1;
1074 else
1075 last = 0;
1076 count = 0;
1077
1078 /* mb: location of last 0->1 transition */
1079 /* me: location of last 1->0 transition */
1080 /* count: # transitions */
1081
3eb9799d 1082 for (mx = 0, mask = (long) 1 << 31; mx < 32; ++mx, mask >>= 1)
252b5132
RH		 1083 {
1084 if ((uval & mask) && !last)
1085 {
1086 ++count;
1087 mb = mx;
1088 last = 1;
1089 }
1090 else if (!(uval & mask) && last)
1091 {
1092 ++count;
1093 me = mx;
1094 last = 0;
1095 }
1096 }
1097 if (me == 0)
1098 me = 32;
1099
1100 if (count != 2 && (count != 0 || ! last))
1101 {
1102 if (errmsg != (const char **) NULL)
1103 *errmsg = _("illegal bitmask");
1104 }
1105
1106 return insn | (mb << 6) | ((me - 1) << 1);
1107}
1108
1109static long
802a735e 1110extract_mbe (insn, dialect, invalid)
252b5132 1111 unsigned long insn;
802a735e 1112 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1113 int *invalid;
1114{
1115 long ret;
1116 int mb, me;
1117 int i;
1118
1119 if (invalid != (int *) NULL)
1120 *invalid = 1;
1121
1122 mb = (insn >> 6) & 0x1f;
1123 me = (insn >> 1) & 0x1f;
1124 if (mb < me + 1)
1125 {
1126 ret = 0;
1127 for (i = mb; i <= me; i++)
1128 ret |= (long) 1 << (31 - i);
1129 }
1130 else if (mb == me + 1)
1131 ret = ~0;
1132 else /* (mb > me + 1) */
1133 {
1134 ret = ~ (long) 0;
1135 for (i = me + 1; i < mb; i++)
1136 ret &= ~ ((long) 1 << (31 - i));
1137 }
1138 return ret;
1139}
1140
1141/* The MB or ME field in an MD or MDS form instruction. The high bit
1142 is wrapped to the low end. */
1143
1144/*ARGSUSED*/
1145static unsigned long
802a735e 1146insert_mb6 (insn, value, dialect, errmsg)
252b5132
RH		 1147 unsigned long insn;
1148 long value;
802a735e 1149 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1150 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1151{
1152 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1153}
1154
1155/*ARGSUSED*/
1156static long
802a735e 1157extract_mb6 (insn, dialect, invalid)
252b5132 1158 unsigned long insn;
802a735e 1159 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1160 int *invalid ATTRIBUTE_UNUSED;
252b5132
RH		 1161{
1162 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1163}
1164
1165/* The NB field in an X form instruction. The value 32 is stored as
1166 0. */
1167
1168static unsigned long
802a735e 1169insert_nb (insn, value, dialect, errmsg)
252b5132
RH		 1170 unsigned long insn;
1171 long value;
802a735e 1172 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1173 const char **errmsg;
1174{
1175 if (value < 0 || value > 32)
1176 *errmsg = _("value out of range");
1177 if (value == 32)
1178 value = 0;
1179 return insn | ((value & 0x1f) << 11);
1180}
1181
1182/*ARGSUSED*/
1183static long
802a735e 1184extract_nb (insn, dialect, invalid)
252b5132 1185 unsigned long insn;
802a735e 1186 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1187 int *invalid ATTRIBUTE_UNUSED;
252b5132
RH		 1188{
1189 long ret;
1190
1191 ret = (insn >> 11) & 0x1f;
1192 if (ret == 0)
1193 ret = 32;
1194 return ret;
1195}
1196
1197/* The NSI field in a D form instruction. This is the same as the SI
1198 field, only negated. The extraction function always marks it as
1199 invalid, since we never want to recognize an instruction which uses
1200 a field of this type. */
1201
1202/*ARGSUSED*/
1203static unsigned long
802a735e 1204insert_nsi (insn, value, dialect, errmsg)
252b5132
RH		 1205 unsigned long insn;
1206 long value;
802a735e 1207 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1208 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1209{
1210 return insn | ((- value) & 0xffff);
1211}
1212
1213static long
802a735e 1214extract_nsi (insn, dialect, invalid)
252b5132 1215 unsigned long insn;
802a735e 1216 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1217 int *invalid;
1218{
1219 if (invalid != (int *) NULL)
1220 *invalid = 1;
802a735e 1221 return - (((insn & 0xffff) ^ 0x8000) - 0x8000);
252b5132
RH		 1222}
1223
1224/* The RA field in a D or X form instruction which is an updating
1225 load, which means that the RA field may not be zero and may not
1226 equal the RT field. */
1227
1228static unsigned long
802a735e 1229insert_ral (insn, value, dialect, errmsg)
252b5132
RH		 1230 unsigned long insn;
1231 long value;
802a735e 1232 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1233 const char **errmsg;
1234{
1235 if (value == 0
1236 || (unsigned long) value == ((insn >> 21) & 0x1f))
1237 *errmsg = "invalid register operand when updating";
1238 return insn | ((value & 0x1f) << 16);
1239}
1240
1241/* The RA field in an lmw instruction, which has special value
1242 restrictions. */
1243
1244static unsigned long
802a735e 1245insert_ram (insn, value, dialect, errmsg)
252b5132
RH		 1246 unsigned long insn;
1247 long value;
802a735e 1248 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1249 const char **errmsg;
1250{
1251 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1252 *errmsg = _("index register in load range");
1253 return insn | ((value & 0x1f) << 16);
1254}
1255
1256/* The RA field in a D or X form instruction which is an updating
1257 store or an updating floating point load, which means that the RA
1258 field may not be zero. */
1259
1260static unsigned long
802a735e 1261insert_ras (insn, value, dialect, errmsg)
252b5132
RH		 1262 unsigned long insn;
1263 long value;
802a735e 1264 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1265 const char **errmsg;
1266{
1267 if (value == 0)
1268 *errmsg = _("invalid register operand when updating");
1269 return insn | ((value & 0x1f) << 16);
1270}
1271
1272/* The RB field in an X form instruction when it must be the same as
1273 the RS field in the instruction. This is used for extended
1274 mnemonics like mr. This operand is marked FAKE. The insertion
1275 function just copies the BT field into the BA field, and the
1276 extraction function just checks that the fields are the same. */
1277
1278/*ARGSUSED*/
1279static unsigned long
802a735e 1280insert_rbs (insn, value, dialect, errmsg)
252b5132 1281 unsigned long insn;
9aaaa291 1282 long value ATTRIBUTE_UNUSED;
802a735e 1283 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1284 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1285{
1286 return insn | (((insn >> 21) & 0x1f) << 11);
1287}
1288
1289static long
802a735e 1290extract_rbs (insn, dialect, invalid)
252b5132 1291 unsigned long insn;
802a735e 1292 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1293 int *invalid;
1294{
1295 if (invalid != (int *) NULL
1296 && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1297 *invalid = 1;
1298 return 0;
1299}
1300
1301/* The SH field in an MD form instruction. This is split. */
1302
1303/*ARGSUSED*/
1304static unsigned long
802a735e 1305insert_sh6 (insn, value, dialect, errmsg)
252b5132
RH		 1306 unsigned long insn;
1307 long value;
802a735e 1308 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1309 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1310{
1311 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1312}
1313
1314/*ARGSUSED*/
1315static long
802a735e 1316extract_sh6 (insn, dialect, invalid)
252b5132 1317 unsigned long insn;
802a735e 1318 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1319 int *invalid ATTRIBUTE_UNUSED;
252b5132
RH		 1320{
1321 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1322}
1323
1324/* The SPR field in an XFX form instruction. This is flipped--the
1325 lower 5 bits are stored in the upper 5 and vice- versa. */
1326
1327static unsigned long
802a735e 1328insert_spr (insn, value, dialect, errmsg)
252b5132
RH		 1329 unsigned long insn;
1330 long value;
802a735e 1331 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1332 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1333{
1334 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1335}
1336
1337static long
802a735e 1338extract_spr (insn, dialect, invalid)
252b5132 1339 unsigned long insn;
802a735e 1340 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1341 int *invalid ATTRIBUTE_UNUSED;
252b5132
RH		 1342{
1343 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1344}
1345
1346/* The TBR field in an XFX instruction. This is just like SPR, but it
1347 is optional. When TBR is omitted, it must be inserted as 268 (the
1348 magic number of the TB register). These functions treat 0
1349 (indicating an omitted optional operand) as 268. This means that
1350 ``mftb 4,0'' is not handled correctly. This does not matter very
1351 much, since the architecture manual does not define mftb as
1352 accepting any values other than 268 or 269. */
1353
1354#define TB (268)
1355
1356static unsigned long
802a735e 1357insert_tbr (insn, value, dialect, errmsg)
252b5132
RH		 1358 unsigned long insn;
1359 long value;
802a735e 1360 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1361 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1362{
1363 if (value == 0)
1364 value = TB;
1365 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1366}
1367
1368static long
802a735e 1369extract_tbr (insn, dialect, invalid)
252b5132 1370 unsigned long insn;
802a735e 1371 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1372 int *invalid ATTRIBUTE_UNUSED;
252b5132
RH		 1373{
1374 long ret;
1375
1376 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1377 if (ret == TB)
1378 ret = 0;
1379 return ret;
1380}
1381\f
1382/* Macros used to form opcodes. */
1383
1384/* The main opcode. */
1385#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1386#define OP_MASK OP (0x3f)
1387
1388/* The main opcode combined with a trap code in the TO field of a D
1389 form instruction. Used for extended mnemonics for the trap
1390 instructions. */
1391#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1392#define OPTO_MASK (OP_MASK | TO_MASK)
1393
1394/* The main opcode combined with a comparison size bit in the L field
1395 of a D form or X form instruction. Used for extended mnemonics for
1396 the comparison instructions. */
1397#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1398#define OPL_MASK OPL (0x3f,1)
1399
1400/* An A form instruction. */
1401#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1402#define A_MASK A (0x3f, 0x1f, 1)
1403
1404/* An A_MASK with the FRB field fixed. */
1405#define AFRB_MASK (A_MASK | FRB_MASK)
1406
1407/* An A_MASK with the FRC field fixed. */
1408#define AFRC_MASK (A_MASK | FRC_MASK)
1409
1410/* An A_MASK with the FRA and FRC fields fixed. */
1411#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1412
1413/* A B form instruction. */
1414#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1415#define B_MASK B (0x3f, 1, 1)
1416
1417/* A B form instruction setting the BO field. */
1418#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1419#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1420
1421/* A BBO_MASK with the y bit of the BO field removed. This permits
1422 matching a conditional branch regardless of the setting of the y
94efba12 1423 bit. Similarly for the 'at' bits used for power4 branch hints. */
802a735e
AM		 1424#define Y_MASK (((unsigned long) 1) << 21)
1425#define AT1_MASK (((unsigned long) 3) << 21)
1426#define AT2_MASK (((unsigned long) 9) << 21)
1427#define BBOY_MASK (BBO_MASK &~ Y_MASK)
1428#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
252b5132
RH		 1429
1430/* A B form instruction setting the BO field and the condition bits of
1431 the BI field. */
1432#define BBOCB(op, bo, cb, aa, lk) \
1433 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1434#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1435
1436/* A BBOCB_MASK with the y bit of the BO field removed. */
1437#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
802a735e
AM		 1438#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1439#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
252b5132
RH		 1440
1441/* A BBOYCB_MASK in which the BI field is fixed. */
1442#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
802a735e 1443#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
252b5132 1444
23976049
EZ		 1445/* An Context form instruction. */
1446#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1447#define CTX_MASK CTX(0x3f, 0x7)
1448
1449/* An User Context form instruction. */
1450#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1451#define UCTX_MASK UCTX(0x3f, 0x1f)
1452
252b5132
RH		 1453/* The main opcode mask with the RA field clear. */
1454#define DRA_MASK (OP_MASK | RA_MASK)
1455
1456/* A DS form instruction. */
1457#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1458#define DS_MASK DSO (0x3f, 3)
1459
418c1742
MG		 1460/* A DE form instruction. */
1461#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1462#define DE_MASK DEO (0x3e, 0xf)
1463
23976049
EZ		 1464/* An EVSEL form instruction. */
1465#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1466#define EVSEL_MASK EVSEL(0x3f, 0xff)
1467
252b5132
RH		 1468/* An M form instruction. */
1469#define M(op, rc) (OP (op) | ((rc) & 1))
1470#define M_MASK M (0x3f, 1)
1471
1472/* An M form instruction with the ME field specified. */
1473#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1474
1475/* An M_MASK with the MB and ME fields fixed. */
1476#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1477
1478/* An M_MASK with the SH and ME fields fixed. */
1479#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1480
1481/* An MD form instruction. */
1482#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1483#define MD_MASK MD (0x3f, 0x7, 1)
1484
1485/* An MD_MASK with the MB field fixed. */
1486#define MDMB_MASK (MD_MASK | MB6_MASK)
1487
1488/* An MD_MASK with the SH field fixed. */
1489#define MDSH_MASK (MD_MASK | SH6_MASK)
1490
1491/* An MDS form instruction. */
1492#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1493#define MDS_MASK MDS (0x3f, 0xf, 1)
1494
1495/* An MDS_MASK with the MB field fixed. */
1496#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1497
1498/* An SC form instruction. */
1499#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1500#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1501
112290ab 1502/* An VX form instruction. */
786e2c0f
C		 1503#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1504
112290ab 1505/* The mask for an VX form instruction. */
786e2c0f
C		 1506#define VX_MASK VX(0x3f, 0x7ff)
1507
112290ab 1508/* An VA form instruction. */
2613489e 1509#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
786e2c0f 1510
112290ab 1511/* The mask for an VA form instruction. */
2613489e 1512#define VXA_MASK VXA(0x3f, 0x3f)
786e2c0f 1513
112290ab 1514/* An VXR form instruction. */
786e2c0f
C		 1515#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1516
112290ab 1517/* The mask for a VXR form instruction. */
786e2c0f
C		 1518#define VXR_MASK VXR(0x3f, 0x3ff, 1)
1519
252b5132
RH		 1520/* An X form instruction. */
1521#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1522
1523/* An X form instruction with the RC bit specified. */
1524#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1525
1526/* The mask for an X form instruction. */
1527#define X_MASK XRC (0x3f, 0x3ff, 1)
1528
1529/* An X_MASK with the RA field fixed. */
1530#define XRA_MASK (X_MASK | RA_MASK)
1531
1532/* An X_MASK with the RB field fixed. */
1533#define XRB_MASK (X_MASK | RB_MASK)
1534
1535/* An X_MASK with the RT field fixed. */
1536#define XRT_MASK (X_MASK | RT_MASK)
1537
1538/* An X_MASK with the RA and RB fields fixed. */
1539#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1540
112290ab 1541/* An XRARB_MASK, but with the L bit clear. */
5ae2e65e
AM		 1542#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1543
252b5132
RH		 1544/* An X_MASK with the RT and RA fields fixed. */
1545#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1546
98acc1c5
AM		 1547/* An XRTRA_MASK, but with L bit clear. */
1548#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1549
252b5132
RH		 1550/* An X form comparison instruction. */
1551#define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1552
1553/* The mask for an X form comparison instruction. */
1554#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1555
1556/* The mask for an X form comparison instruction with the L field
1557 fixed. */
1558#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1559
1560/* An X form trap instruction with the TO field specified. */
1561#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1562#define XTO_MASK (X_MASK | TO_MASK)
1563
e0c21649
GK		 1564/* An X form tlb instruction with the SH field specified. */
1565#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1566#define XTLB_MASK (X_MASK | SH_MASK)
1567
6ba045b1
AM		 1568/* An X form sync instruction. */
1569#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1570
1571/* An X form sync instruction with everything filled in except the LS field. */
1572#define XSYNC_MASK (0xff9fffff)
1573
f5c120c5
MG		 1574/* An X form AltiVec dss instruction. */
1575#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1576#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1577
252b5132
RH		 1578/* An XFL form instruction. */
1579#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1580#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1581
23976049
EZ		 1582/* An X form isel instruction. */
1583#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1584#define XISEL_MASK XISEL(0x3f, 0x1f)
1585
252b5132
RH		 1586/* An XL form instruction with the LK field set to 0. */
1587#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1588
1589/* An XL form instruction which uses the LK field. */
1590#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1591
1592/* The mask for an XL form instruction. */
1593#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1594
1595/* An XL form instruction which explicitly sets the BO field. */
1596#define XLO(op, bo, xop, lk) \
1597 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1598#define XLO_MASK (XL_MASK | BO_MASK)
1599
1600/* An XL form instruction which explicitly sets the y bit of the BO
1601 field. */
1602#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1603#define XLYLK_MASK (XL_MASK | Y_MASK)
1604
1605/* An XL form instruction which sets the BO field and the condition
1606 bits of the BI field. */
1607#define XLOCB(op, bo, cb, xop, lk) \
1608 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1609#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1610
1611/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1612#define XLBB_MASK (XL_MASK | BB_MASK)
1613#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1614#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1615
1616/* An XL_MASK with the BO and BB fields fixed. */
1617#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1618
1619/* An XL_MASK with the BO, BI and BB fields fixed. */
1620#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1621
1622/* An XO form instruction. */
1623#define XO(op, xop, oe, rc) \
1624 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1625#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1626
1627/* An XO_MASK with the RB field fixed. */
1628#define XORB_MASK (XO_MASK | RB_MASK)
1629
1630/* An XS form instruction. */
1631#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1632#define XS_MASK XS (0x3f, 0x1ff, 1)
1633
1634/* A mask for the FXM version of an XFX form instruction. */
1635#define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11))
1636
1637/* An XFX form instruction with the FXM field filled in. */
1638#define XFXM(op, xop, fxm) \
1639 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1640
1641/* An XFX form instruction with the SPR field filled in. */
1642#define XSPR(op, xop, spr) \
1643 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1644#define XSPR_MASK (X_MASK | SPR_MASK)
1645
1646/* An XFX form instruction with the SPR field filled in except for the
1647 SPRBAT field. */
1648#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1649
1650/* An XFX form instruction with the SPR field filled in except for the
1651 SPRG field. */
1652#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1653
1654/* An X form instruction with everything filled in except the E field. */
1655#define XE_MASK (0xffff7fff)
1656
23976049
EZ		 1657/* An X form user context instruction. */
1658#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1659#define XUC_MASK XUC(0x3f, 0x1f)
1660
252b5132
RH		 1661/* The BO encodings used in extended conditional branch mnemonics. */
1662#define BODNZF (0x0)
1663#define BODNZFP (0x1)
1664#define BODZF (0x2)
1665#define BODZFP (0x3)
252b5132
RH		 1666#define BODNZT (0x8)
1667#define BODNZTP (0x9)
1668#define BODZT (0xa)
1669#define BODZTP (0xb)
802a735e
AM		 1670
1671#define BOF (0x4)
1672#define BOFP (0x5)
94efba12
AM		 1673#define BOFM4 (0x6)
1674#define BOFP4 (0x7)
252b5132
RH		 1675#define BOT (0xc)
1676#define BOTP (0xd)
94efba12
AM		 1677#define BOTM4 (0xe)
1678#define BOTP4 (0xf)
802a735e 1679
252b5132
RH		 1680#define BODNZ (0x10)
1681#define BODNZP (0x11)
1682#define BODZ (0x12)
1683#define BODZP (0x13)
94efba12
AM		 1684#define BODNZM4 (0x18)
1685#define BODNZP4 (0x19)
1686#define BODZM4 (0x1a)
1687#define BODZP4 (0x1b)
802a735e 1688
252b5132
RH		 1689#define BOU (0x14)
1690
1691/* The BI condition bit encodings used in extended conditional branch
1692 mnemonics. */
1693#define CBLT (0)
1694#define CBGT (1)
1695#define CBEQ (2)
1696#define CBSO (3)
1697
1698/* The TO encodings used in extended trap mnemonics. */
1699#define TOLGT (0x1)
1700#define TOLLT (0x2)
1701#define TOEQ (0x4)
1702#define TOLGE (0x5)
1703#define TOLNL (0x5)
1704#define TOLLE (0x6)
1705#define TOLNG (0x6)
1706#define TOGT (0x8)
1707#define TOGE (0xc)
1708#define TONL (0xc)
1709#define TOLT (0x10)
1710#define TOLE (0x14)
1711#define TONG (0x14)
1712#define TONE (0x18)
1713#define TOU (0x1f)
1714\f
1715/* Smaller names for the flags so each entry in the opcodes table will
1716 fit on a single line. */
1717#undef PPC
1718#define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY
1719#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
94efba12
AM		 1720#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1721#define POWER4 PPC_OPCODE_POWER4 | PPCCOM
802a735e
AM		 1722#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
1723#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
252b5132 1724#define PPCONLY PPC_OPCODE_PPC
418c1742 1725#define PPC403 PPC_OPCODE_403
e0c21649 1726#define PPC405 PPC403
252b5132
RH		 1727#define PPC750 PPC
1728#define PPC860 PPC
1cbbfaf9 1729#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC
252b5132
RH		 1730#define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY
1731#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1732#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1733#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
1734#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1735#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
1736#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
1737#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1738#define MFDEC1 PPC_OPCODE_POWER
dde1b132 1739#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
418c1742
MG		 1740#define BOOKE PPC_OPCODE_BOOKE
1741#define BOOKE64 PPC_OPCODE_BOOKE64
23976049
EZ		 1742#define CLASSIC PPC_OPCODE_CLASSIC
1743#define PPCSPE PPC_OPCODE_SPE
1744#define PPCISEL PPC_OPCODE_ISEL
1745#define PPCEFS PPC_OPCODE_EFS
1746#define PPCBRLK PPC_OPCODE_BRLOCK
1747#define PPCPMR PPC_OPCODE_PMR
1748#define PPCCHLK PPC_OPCODE_CACHELCK
dde1b132 1749#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
23976049 1750#define PPCRFMCI PPC_OPCODE_RFMCI
252b5132
RH		 1751\f
1752/* The opcode table.
1753
1754 The format of the opcode table is:
1755
1756 NAME OPCODE MASK FLAGS { OPERANDS }
1757
1758 NAME is the name of the instruction.
1759 OPCODE is the instruction opcode.
1760 MASK is the opcode mask; this is used to tell the disassembler
1761 which bits in the actual opcode must match OPCODE.
1762 FLAGS are flags indicated what processors support the instruction.
1763 OPERANDS is the list of operands.
1764
1765 The disassembler reads the table in order and prints the first
1766 instruction which matches, so this table is sorted to put more
1767 specific instructions before more general instructions. It is also
1768 sorted by major opcode. */
1769
1770const struct powerpc_opcode powerpc_opcodes[] = {
1771{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1772{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1773{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1774{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1775{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1776{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1777{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1778{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1779{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1780{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1781{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1782{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1783{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1784{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1785{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1786
1787{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1788{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1789{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1790{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1791{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1792{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1793{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1794{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1795{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1796{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1797{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1798{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1799{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1800{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1801{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1802{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1803{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1804{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1805{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1806{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1807{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1808{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1809{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1810{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1811{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1812{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1813{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1814{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1815{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1816{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
e0c21649
GK		 1817
1818{ "macchw", XO(4,172,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1819{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1820{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1821{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1822{ "macchws", XO(4,236,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1823{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1824{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1825{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1826{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1827{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1828{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1829{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1830{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1831{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1832{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1833{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1834{ "machhw", XO(4,44,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1835{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1836{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1837{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1838{ "machhws", XO(4,108,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1839{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1840{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1841{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1842{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1843{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1844{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1845{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1846{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1847{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1848{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1849{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1850{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1851{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1852{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1853{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1854{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1855{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1856{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1857{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1858{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1859{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1860{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1861{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1862{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1863{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1864{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1865{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1866{ "mulchw", XRC(4,168,0), X_MASK, PPC405, { RT, RA, RB } },
1867{ "mulchw.", XRC(4,168,1), X_MASK, PPC405, { RT, RA, RB } },
1868{ "mulchwu", XRC(4,136,0), X_MASK, PPC405, { RT, RA, RB } },
1869{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405, { RT, RA, RB } },
1870{ "mulhhw", XRC(4,40,0), X_MASK, PPC405, { RT, RA, RB } },
1871{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405, { RT, RA, RB } },
1872{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405, { RT, RA, RB } },
1873{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405, { RT, RA, RB } },
1874{ "mullhw", XRC(4,424,0), X_MASK, PPC405, { RT, RA, RB } },
1875{ "mullhw.", XRC(4,424,1), X_MASK, PPC405, { RT, RA, RB } },
1876{ "mullhwu", XRC(4,392,0), X_MASK, PPC405, { RT, RA, RB } },
1877{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405, { RT, RA, RB } },
1878{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1879{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1880{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1881{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1882{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1883{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1884{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1885{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1886{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1887{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1888{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1889{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1890{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1891{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1892{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1893{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1894{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1895{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1896{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1897{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1898{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1899{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1900{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1901{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } },
786e2c0f 1902{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
f5c120c5 1903{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
786e2c0f
C		 1904{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
1905{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
1906{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
1907{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
1908{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
1909{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
1910{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
1911{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
1912{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
1913{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
1914{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
1915{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
1916{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
1917{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
1918{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
1919{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
1920{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
1921{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
1922{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
1923{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1924{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1925{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1926{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1927{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1928{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1929{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1930{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1931{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1932{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1933{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1934{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1935{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1936{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1937{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1938{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1939{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1940{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1941{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1942{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1943{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1944{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1945{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1946{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1947{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1948{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1949{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1950{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1951{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1952{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1953{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
1954{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
294b41b3 1955{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
786e2c0f
C		 1956{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
1957{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
1958{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
1959{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
1960{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
1961{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
1962{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
1963{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1964{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1965{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
1966{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
1967{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
1968{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
1969{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
1970{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
1971{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
1972{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1973{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
1974{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
1975{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
1976{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
1977{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
1978{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
1979{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1980{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1981{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
d2f75a6f
GK		 1982{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1983{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1984{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
786e2c0f
C		 1985{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
1986{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
1987{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
1988{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
1989{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
1990{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
1991{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
1992{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
1993{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
1994{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
1995{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
1996{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1997{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
1998{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
1999{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2000{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2001{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2002{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2003{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2004{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2005{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2006{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2007{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2008{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2009{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2010{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2011{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2012{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2013{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2014{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
2015{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2016{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2017{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2018{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2019{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2020{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
1da5001c 2021{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
786e2c0f
C		 2022{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2023{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2024{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2025{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2026{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2027{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2028{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2029{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2030{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2031{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2032{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2033{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2034{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2035{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2036{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2037{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2038{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2039{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2040{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2041{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2042{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2043{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2044{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2045{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2046{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2047{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2048{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2049{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2050{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2051{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2052{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2053{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2054{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2055{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2056{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2057{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2058{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
252b5132 2059
914749f6
AH		 2060{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2061{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2062{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2063{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2064{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2065{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2066{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2067{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2068{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2069{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2070{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2071{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2072{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2073
2074{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2075
2076{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2077{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
dde1b132 2078{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
914749f6
AH		 2079{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2080{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2081{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2082{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2083{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
dde1b132 2084{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
914749f6
AH		 2085{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2086
2087{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2088{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2089{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2090{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2091{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2092{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2093{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2094{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2095{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2096{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
fe587977
AH		 2097{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2098{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2099{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2100{ "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
23976049
EZ		 2101
2102{ "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2103{ "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2104{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2105{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2106{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
914749f6 2107{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
23976049
EZ		 2108
2109{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2110{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2111{ "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2112{ "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2113{ "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2114{ "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2115{ "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2116{ "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2117{ "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2118{ "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2119{ "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2120{ "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2121{ "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2122{ "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2123{ "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2124{ "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2125{ "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2126{ "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2127{ "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2128{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2129{ "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2130{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2131
2132{ "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2133{ "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2134{ "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2135{ "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2136{ "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2137{ "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2138{ "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2139{ "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2140{ "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2141{ "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2142{ "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2143{ "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2144{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2145{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2146
914749f6
AH		 2147{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2148{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2149{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2150{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2151{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2152{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2153{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
23976049
EZ		 2154{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2155{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2156{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2157{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2158{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2159{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
914749f6
AH		 2160{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2161{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2162{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2163{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2164{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2165{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2166{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2167{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2168{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2169{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2170
2171{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2172{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2173{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2174{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2175{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2176{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2177{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
23976049
EZ		 2178{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2179{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2180{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2181{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2182{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2183{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
914749f6
AH		 2184{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2185{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2186{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2187{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2188{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2189{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2190{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2191{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2192{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2193{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2194
914749f6
AH		 2195{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2196{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2197{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2198{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2199{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2200{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2201{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2202{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2203{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2204{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2205{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2206{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2207{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2208{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2209{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2210{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2211
2212{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2213{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2214{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2215{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2216{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2217{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2218{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2219{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2220{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2221{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2222{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2223{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2224
2225{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2226{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2227{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2228{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2229{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2230{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2231{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2232{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2233{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2234{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2235{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2236{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2237
2238{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2239{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2240{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2241{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2242{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2243{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2244
2245{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2246{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2247{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2248{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2249{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2250{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2251
2252{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2253{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2254{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2255{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2256{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2257{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2258{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2259{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2260
914749f6
AH		 2261{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2262{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2263
914749f6 2264{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
914749f6
AH		 2265{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2266{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2267{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2268
914749f6 2269{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
914749f6
AH		 2270{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2271{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2272{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2273
914749f6
AH		 2274{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2275{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2276{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2277{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2278{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2279{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2280{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2281{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2282
2283{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2284{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2285{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2286{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2287
2288{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2289{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2290{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2291{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2292
2293{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2294{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2295{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2296{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2297
2298{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2299{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2300{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2301{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2302
2303{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2304
2305{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2306{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
23976049 2307
252b5132
RH		 2308{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2309{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2310
2311{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2312{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2313
2314{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2315
418c1742
MG		 2316{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2317{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2318{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2319{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2320
252b5132
RH		 2321{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2322{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
2323{ "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } },
2324{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2325
2326{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2327{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
2328{ "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } },
2329{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2330
2331{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2332{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2333{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2334
2335{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2336{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2337{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2338
2339{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2340{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2341{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } },
2342{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } },
2343{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } },
2344{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } },
2345
2346{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2347{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2348{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } },
2349{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } },
2350{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } },
2351
112290ab
NC		 2352{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2353{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2354{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2355{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2356{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2357{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2358{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2359{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2360{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2361{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2362{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2363{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2364{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2365{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2366{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2367{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2368{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2369{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2370{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2371{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2372{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2373{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2374{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2375{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2376{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2377{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2378{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2379{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
802a735e
AM		 2380{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2381{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2382{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2383{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2384{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2385{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2386{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2387{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2388{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2389{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2390{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2391{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2392{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2393{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2394{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2395{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2396{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2397{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2398{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2399{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2400{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2401{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2402{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2403{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2404{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2405{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2406{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2407{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2408{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2409{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2410{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2411{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2412{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2413{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2414{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2415{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2416{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2417{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2418{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2419{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2420{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2421{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2422{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2423{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2424{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2425{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2426{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2427{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2428{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2429{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2430{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2431{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2432{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2433{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2434{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2435{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2436{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2437{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2438{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2439{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2440{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2441{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2442{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2443{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2444{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2445{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2446{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2447{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2448{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2449{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2450{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2451{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2452{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2453{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2454{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2455{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2456{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2457{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2458{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2459{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2460{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2461{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2462{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2463{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2464{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2465{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2466{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2467{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2468{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2469{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2470{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2471{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2472{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2473{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2474{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2475{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2476{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2477{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2478{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2479{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2480{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2481{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2482{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2483{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2484{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2485{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2486{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2487{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2488{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2489{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2490{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2491{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2492{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2493{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2494{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2495{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2496{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2497{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2498{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2499{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2500{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2501{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2502{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2503{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2504{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2505{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2506{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2507{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2508{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2509{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2510{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2511{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2512{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2513{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2514{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2515{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2516{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2517{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2518{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2519{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2520{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2521{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2522{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2523{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
94efba12
AM		 2524{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2525{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2526{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2527{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2528{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2529{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2530{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2531{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2532{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2533{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2534{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2535{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2536{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2537{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2538{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2539{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2540{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2541{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2542{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2543{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2544{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2545{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2546{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2547{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
802a735e
AM		 2548{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2549{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2550{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2551{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2552{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2553{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2554{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2555{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2556{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2557{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2558{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2559{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2560{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2561{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2562{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2563{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2564{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2565{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2566{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2567{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2568{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2569{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2570{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2571{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2572{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2573{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2574{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2575{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2576{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2577{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2578{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2579{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
94efba12
AM		 2580{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2581{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2582{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2583{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2584{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2585{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2586{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2587{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2588{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2589{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2590{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2591{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2592{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2593{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2594{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2595{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2596{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2597{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2598{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2599{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2600{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2601{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2602{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2603{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
d2f75a6f
GK		 2604{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2605{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
252b5132 2606{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
d2f75a6f
GK		 2607{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2608{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
252b5132 2609{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
d2f75a6f
GK		 2610{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2611{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
252b5132 2612{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
d2f75a6f
GK		 2613{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2614{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
252b5132
RH		 2615{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2616
2617{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
2618{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
2619{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
2620{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2621{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2622
418c1742
MG		 2623{ "b", B(18,0,0), B_MASK, COM, { LI } },
2624{ "bl", B(18,0,1), B_MASK, COM, { LI } },
2625{ "ba", B(18,1,0), B_MASK, COM, { LIA } },
2626{ "bla", B(18,1,1), B_MASK, COM, { LIA } },
252b5132 2627
112290ab 2628{ "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
252b5132
RH		 2629
2630{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2631{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2632{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2633{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2634{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12
AM		 2635{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2636{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2637{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2638{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2639{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12
AM		 2640{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2641{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2642{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2643{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2644{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12
AM		 2645{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2646{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2647{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2648{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2649{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12
AM		 2650{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2651{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2652{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2653{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2654{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2655{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2656{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2657{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2658{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2659{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2660{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2661{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2662{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2663{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2664{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2665{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2666{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2667{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2668{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2669{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2670{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2671{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2672{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2673{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2674{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2675{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2676{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2677{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2678{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2679{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2680{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2681{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2682{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2683{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2684{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2685{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2686{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2687{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2688{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2689{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2690{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2691{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2692{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2693{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2694{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2695{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2696{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2697{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2698{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2699{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2700{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2701{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2702{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2703{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2704{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2705{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2706{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2707{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2708{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2709{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2710{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2711{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2712{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2713{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2714{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2715{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2716{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2717{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2718{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2719{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2720{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2721{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2722{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2723{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2724{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2725{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2726{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2727{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2728{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2729{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2730{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2731{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2732{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2733{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2734{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2735{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2736{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2737{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2738{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2739{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2740{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2741{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2742{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2743{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2744{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2745{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2746{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2747{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2748{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2749{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2750{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2751{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2752{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2753{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2754{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2755{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2756{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2757{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2758{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2759{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2760{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2761{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2762{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2763{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2764{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2765{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2766{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2767{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2768{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2769{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2770{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2771{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2772{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2773{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2774{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2775{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2776{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2777{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2778{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2779{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2780{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2781{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2782{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2783{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2784{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2785{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2786{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2787{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2788{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2789{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2790{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2791{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2792{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2793{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2794{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2795{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2796{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2797{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2798{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2799{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2800{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2801{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2802{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2803{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2804{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2805{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2806{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2807{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2808{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2809{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2810{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2811{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2812{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2813{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2814{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2815{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2816{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2817{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2818{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2819{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2820{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2821{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2822{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2823{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2824{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2825{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2826{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2827{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2828{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2829{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2830{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2831{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2832{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2833{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2834{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2835{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2836{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2837{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2838{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2839{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2840{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2841{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132
RH		 2842{ "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } },
2843{ "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } },
d2f75a6f
GK		 2844{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2845{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2846{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2847{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
252b5132
RH		 2848{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2849{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
418c1742
MG		 2850{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
2851{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
252b5132 2852
f509565f
GK		 2853{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
2854
252b5132
RH		 2855{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
2856{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
112290ab 2857{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
252b5132
RH		 2858
2859{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
e0c21649 2860{ "rfci", XL(19,51), 0xffffffff, PPC403, { 0 } },
9fa87a06 2861{ "rfci", XL(19,51), 0xffffffff, BOOKE, { 0 } },
252b5132
RH		 2862
2863{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
2864
2865{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
2866
2867{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
2868{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
2869
2870{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2871{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
2872
2873{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
2874
2875{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
2876
2877{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2878{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
2879
2880{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
2881
2882{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
2883{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
2884
2885{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
2886{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
2887{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2888{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2889{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2890{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2891{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2892{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2893{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2894{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2895{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2896{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2897{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2898{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2899{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2900{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2901{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2902{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2903{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2904{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2905{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2906{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2907{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2908{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2909{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2910{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2911{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2912{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2913{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2914{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2915{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2916{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2917{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2918{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2919{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2920{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2921{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2922{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2923{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2924{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2925{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2926{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2927{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2928{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2929{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2930{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2931{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2932{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2933{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2934{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2935{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2936{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2937{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2938{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2939{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2940{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2941{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2942{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2943{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2944{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2945{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2946{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2947{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2948{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2949{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2950{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2951{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2952{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2953{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2954{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2955{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2956{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2957{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2958{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2959{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2960{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2961{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2962{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2963{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2964{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2965{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2966{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2967{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2968{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2969{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2970{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2971{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2972{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2973{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2974{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2975{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2976{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2977{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2978{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2979{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2980{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2981{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2982{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2983{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2984{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2985{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2986{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2987{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2988{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2989{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2990{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2991{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2992{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2993{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2994{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2995{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2996{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2997{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2998{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2999{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3000{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3001{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3002{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3003{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3004{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3005{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3006{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3007{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 3008{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3009{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3010{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3011{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
252b5132 3012{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 3013{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3014{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3015{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3016{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
252b5132 3017{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 3018{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3019{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3020{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3021{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
252b5132 3022{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 3023{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3024{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3025{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3026{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
252b5132 3027{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } },
d2f75a6f
GK		 3028{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3029{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
252b5132 3030{ "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } },
d2f75a6f
GK		 3031{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3032{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
252b5132
RH		 3033{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3034{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
418c1742
MG		 3035{ "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
3036{ "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
252b5132
RH		 3037
3038{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3039{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3040
3041{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3042{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3043
3044{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3045{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3046{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3047{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3048{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3049{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3050{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3051{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3052
3053{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3054{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3055
418c1742
MG		 3056{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
3057{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
3058{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
3059{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
3060
252b5132
RH		 3061{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3062{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3063{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3064{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3065{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3066{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3067
3068{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3069{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3070{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3071
3072{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3073{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3074
3075{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3076{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3077
3078{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3079{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3080
3081{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3082{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3083
3084{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3085{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3086
3087{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3088{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3089{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3090{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3091{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3092{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3093
3094{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3095{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3096
3097{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3098{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3099
3100{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3101{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3102
3103{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3104{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3105{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3106{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3107
3108{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3109{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3110
3111{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3112{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3113{ "cmp", X(31,0), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
3114{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3115
3116{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3117{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3118{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3119{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3120{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3121{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3122{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3123{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3124{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3125{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3126{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3127{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3128{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3129{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3130{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3131{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3132{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3133{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3134{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3135{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3136{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3137{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3138{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3139{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3140{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3141{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3142{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3143{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3144{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
3145{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3146{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3147
3148{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3149{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3150{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3151{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3152{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3153{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3154{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3155{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3156{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3157{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3158{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3159{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3160
3161{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3162{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3163
3164{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3165{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3166{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3167{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3168{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3169{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3170{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3171{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3172
3173{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3174{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3175
dde1b132
NC		 3176{ "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3177{ "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3178{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3179{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
23976049 3180
252b5132
RH		 3181{ "mfcr", X(31,19), XRARB_MASK, COM, { RT } },
3182
3183{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
3184
3185{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } },
3186
418c1742
MG		 3187{ "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } },
3188
252b5132
RH		 3189{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } },
3190{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3191
3192{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3193{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3194{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3195{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3196
3197{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3198{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3199{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3200{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3201
3202{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3203{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3204
3205{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3206{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3207
3208{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3209{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3210
418c1742
MG		 3211{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3212
3213{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA, RB } },
3214
252b5132
RH		 3215{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3216{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3217{ "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
3218{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3219
3220{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3221{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3222{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3223{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3224{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3225{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3226{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3227{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3228
3229{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3230
3231{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3232
3233{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3234{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3235
418c1742
MG		 3236{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3237
3238{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3239
252b5132
RH		 3240{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3241{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3242
418c1742
MG		 3243{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3244{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
252b5132
RH		 3245
3246{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3247{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3248{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3249{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3250{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3251{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3252{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3253{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3254{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3255{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3256{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3257{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3258{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3259{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3260{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3261
3262{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3263{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3264
3265{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3266{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3267
f509565f
GK		 3268{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3269
252b5132
RH		 3270{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3271
3272{ "ldarx", X(31,84), X_MASK, PPC64, { RT, RA, RB } },
3273
3274{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
3275
3276{ "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } },
3277
418c1742
MG		 3278{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3279
3280{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA, RB } },
3281
252b5132
RH		 3282{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3283{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3284{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3285{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3286
3287{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3288{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3289{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3290{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3291
f509565f
GK		 3292{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3293
2dd46b8b 3294{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
252b5132
RH		 3295
3296{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3297
3298{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3299{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3300{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3301{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3302
418c1742
MG		 3303{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA, RB } },
3304
3305{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3306
252b5132 3307{ "wrtee", X(31,131), XRARB_MASK, PPC403, { RS } },
9fa87a06 3308{ "wrtee", X(31,131), XRARB_MASK, BOOKE, { RS } },
252b5132 3309
23976049
EZ		 3310{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3311
252b5132
RH		 3312{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3313{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3314{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3315{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3316{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3317{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3318{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3319{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3320
3321{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3322{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3323{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3324{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3325{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3326{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3327{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3328{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3329
dde1b132 3330{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 3331
252b5132
RH		 3332{ "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM, { RS }},
3333{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3334
3335{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3336
3337{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA, RB } },
3338
3339{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
3340
3341{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } },
3342{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3343
418c1742
MG		 3344{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA, RB } },
3345
3346{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA, RB } },
3347
252b5132
RH		 3348{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3349{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3350
3351{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3352{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3353
3354{ "wrteei", X(31,163), XE_MASK, PPC403, { E } },
9fa87a06 3355{ "wrteei", X(31,163), XE_MASK, BOOKE, { E } },
252b5132 3356
23976049 3357{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
dde1b132 3358{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 3359
82674a1f 3360{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
f509565f 3361
252b5132
RH		 3362{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3363
3364{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3365{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA, RB } },
3366
3367{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3368{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3369
418c1742
MG		 3370{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3371
252b5132
RH		 3372{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3373{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3374{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3375{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3376{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3377{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3378{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3379{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3380
3381{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3382{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3383{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3384{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3385{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3386{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3387{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3388{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3389
3390{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3391
3392{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } },
3393
418c1742 3394{ "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } },
252b5132
RH		 3395
3396{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3397{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3398
3399{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3400{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3401
418c1742
MG		 3402{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA, RB } },
3403
23976049
EZ		 3404{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3405
252b5132
RH		 3406{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3407{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3408{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3409{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3410{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3411{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3412{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3413{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3414
3415{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3416{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3417{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3418{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3419
3420{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3421{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3422{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3423{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3424{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3425{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3426{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3427{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3428
3429{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3430{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3431{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3432{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3433{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3434{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3435{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3436{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3437
dde1b132 3438{ "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
252b5132
RH		 3439{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3440{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3441
418c1742 3442{ "dcbtst", X(31,246), XRT_MASK, PPC, { CT, RA, RB } },
252b5132
RH		 3443
3444{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3445
3446{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3447{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3448
418c1742
MG		 3449{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3450
3451{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3452
9fa87a06
MG		 3453{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3454
0152a4c6
MG		 3455{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3456
252b5132
RH		 3457{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3458{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3459{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3460{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3461
3462{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3463{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3464{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3465{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3466{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3467{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3468{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3469{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3470
c1a34e60
AM		 3471{ "tlbiel", X(31,274), XRTRA_MASK, POWER4, { RB } },
3472
418c1742
MG		 3473{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3474
252b5132
RH		 3475{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3476{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3477
418c1742 3478{ "dcbt", X(31,278), XRT_MASK, PPC, { CT, RA, RB } },
252b5132
RH		 3479
3480{ "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } },
3481
252b5132
RH		 3482{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3483{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3484
418c1742
MG		 3485{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3486
3487{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA, RB } },
3488
98acc1c5 3489{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
252b5132
RH		 3490{ "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } },
3491
3492{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3493
3494{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3495
3496{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3497{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3498
418c1742
MG		 3499{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3500
dde1b132
NC		 3501{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3502{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3503{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3504{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3505{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3506{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3507{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3508{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3509{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3510{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3511{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3512{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3513{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
252b5132
RH		 3514{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3515{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3516{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3517{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3518{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3519{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3520{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3521{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3522{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3523{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3524{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3525{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3526{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3527{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3528{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3529{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3530{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3531{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3532{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3533{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3534{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3535{ "mfdcr", X(31,323), X_MASK, PPC403, { RT, SPR } },
3536{ "mfdcr", X(31,323), X_MASK, BOOKE, { RT, SPR } },
252b5132
RH		 3537
3538{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3539{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3540{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3541{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3542
914749f6 3543{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
23976049 3544
dde1b132
NC		 3545{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3546{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3547{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3548{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3549{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3550{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3551{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3552{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3553{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3554{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3555{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3556{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3557{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3558{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3559{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3560{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3561{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3562{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3563{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
3564{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
3565{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3566{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3567{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3568{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3569{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3570{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3571{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3572{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3573{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3574{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3575{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3576{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3577{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3578{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3579{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3580{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3581{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3582{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3583{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3584{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } },
3585{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
3586{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
3587{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
914749f6 3588{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
dde1b132
NC		 3589{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3590{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3591{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
3592{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3593{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3594{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3595{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3596{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3597{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3598{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3599{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3600{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
3601{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
3602{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
3603{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3604{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
3605{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
3606{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
3607{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
3608{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
3609{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
3610{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
3611{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
3612{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
3613{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
3614{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3615{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3616{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3617{ "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3618{ "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3619{ "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3620{ "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3621{ "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3622{ "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3623{ "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3624{ "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3625{ "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3626{ "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3627{ "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3628{ "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3629{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3630{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3631{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
914749f6 3632{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
dde1b132
NC		 3633{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3634{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3635{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3636{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3637{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3638{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3639{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3640{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3641{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3642{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3643{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3644{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3645{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3646{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3647{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3648{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3649{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3650{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3651{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3652{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3653{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3654{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3655{ "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3656{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3657{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3658{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3659{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3660{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3661{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3662{ "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3663{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3664{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3665{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3666{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3667{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3668{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3669{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3670{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3671{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3672{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3673{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3674{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3675{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3676{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3677{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
e0c21649
GK		 3678{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3679{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3680{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3681{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
252b5132
RH		 3682{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3683{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
e0c21649 3684{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
252b5132 3685{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
e0c21649 3686{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
252b5132 3687{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
e0c21649 3688{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
252b5132 3689{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
e0c21649 3690{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
252b5132 3691{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
e0c21649 3692{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
252b5132 3693{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
dde1b132
NC		 3694{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
3695{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3696{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3697{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3698{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
3699{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3700{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3701{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3702{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3703{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3704{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3705{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
3706{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3707{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3708{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3709{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3710{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3711{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3712{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3713{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3714{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3715{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3716{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3717{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3718{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3719{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3720{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3721{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3722{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3723{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
252b5132
RH		 3724
3725{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } },
3726
f5c120c5
MG		 3727{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3728{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3729
252b5132
RH		 3730{ "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } },
3731
418c1742
MG		 3732{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA, RB } },
3733
f5c120c5
MG		 3734{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3735{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3736
e0c21649 3737{ "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } },
252b5132
RH		 3738
3739{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3740{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3741{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3742{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3743
3744{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3745{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3746{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3747{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3748
3749{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3750
23976049
EZ		 3751{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3752{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
42a2f80a 3753{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
252b5132
RH		 3754
3755{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3756
3757{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3758
418c1742
MG		 3759{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3760
9fa87a06
MG		 3761{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3762
23976049
EZ		 3763{ "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3764
418c1742
MG		 3765{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3766{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3767
3768{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3769{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3770
dde1b132 3771{ "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 3772
6ba045b1
AM		 3773{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3774
252b5132
RH		 3775{ "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } },
3776
3777{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3778
3779{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3780
3781{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3782
3783{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3784
3785{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3786{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3787
3788{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3789{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3790
418c1742
MG		 3791{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA, RB } },
3792
252b5132
RH		 3793{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3794
3795{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
3796
3797{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3798
418c1742
MG		 3799{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3800
252b5132
RH		 3801{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
3802{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3803{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
3804{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3805
dde1b132
NC		 3806{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RT } },
3807{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RT } },
3808{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RT } },
3809{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RT } },
3810{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RT } },
3811{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RT } },
3812{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RT } },
3813{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RT } },
3814{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RT } },
3815{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RT } },
3816{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RT } },
3817{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RT } },
3818{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RT } },
252b5132
RH		 3819{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RT } },
3820{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RT } },
3821{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RT } },
3822{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RT } },
3823{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RT } },
3824{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RT } },
3825{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RT } },
3826{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RT } },
3827{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RT } },
3828{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RT } },
3829{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RT } },
3830{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RT } },
3831{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RT } },
3832{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RT } },
3833{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RT } },
3834{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RT } },
3835{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RT } },
3836{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RT } },
3837{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RT } },
3838{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3839{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RT } },
3840{ "mtdcr", X(31,451), X_MASK, PPC403, { SPR, RS } },
3841{ "mtdcr", X(31,451), X_MASK, BOOKE, { SPR, RS } },
252b5132 3842
418c1742
MG		 3843{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3844{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3845
252b5132
RH		 3846{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3847{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3848{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3849{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3850
418c1742
MG		 3851{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3852{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3853
252b5132
RH		 3854{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
3855{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
3856{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
3857{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
3858
dde1b132
NC		 3859{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
3860{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
3861{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
3862{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
3863{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
3864{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
3865{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
3866{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
3867{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
3868{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
3869{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
3870{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
3871{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
3872{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
3873{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
3874{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
3875{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
3876{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
3877{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
3878{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
3879{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
3880{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RT } },
3881{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RT } },
3882{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RT } },
3883{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RT } },
3884{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RT } },
3885{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RT } },
3886{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RT } },
3887{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RT } },
3888{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RT } },
3889{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RT } },
3890{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RT } },
3891{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RT } },
3892{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RT } },
3893{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RT } },
3894{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RT } },
3895{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RT } },
3896{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RT } },
3897{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
3898{ "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } },
3899{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RT } },
3900{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } },
3901{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RT } },
3902{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RT } },
3903{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405, { RT } },
3904{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, BOOKE, { RS } },
3905{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405, { RT } },
3906{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, BOOKE, { RS } },
3907{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405, { RT } },
3908{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, BOOKE, { RS } },
3909{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405, { RT } },
3910{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, BOOKE, { RS } },
3911{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
3912{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
3913{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
3914{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
3915{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
3916{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
3917{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
3918{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
3919{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
3920{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
3921{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
3922{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
3923{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
3924{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
3925{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
3926{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
3927{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
3928{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
3929{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
3930{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
3931{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
3932{ "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
3933{ "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
3934{ "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
3935{ "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
3936{ "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
3937{ "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
3938{ "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
3939{ "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
3940{ "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
3941{ "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
3942{ "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
3943{ "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
3944{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
42a2f80a 3945{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
dde1b132 3946{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
914749f6 3947{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
dde1b132
NC		 3948{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3949{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3950{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3951{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3952{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
3953{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
3954{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
3955{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RT } },
3956{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RT } },
3957{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RT } },
3958{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RT } },
3959{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RT } },
3960{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RT } },
3961{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RT } },
3962{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RT } },
3963{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RT } },
3964{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RT } },
3965{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RT } },
3966{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RT } },
3967{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RT } },
3968{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RT } },
3969{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RT } },
3970{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RT } },
3971{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RT } },
3972{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RT } },
3973{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RT } },
3974{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RT } },
3975{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RT } },
3976{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RT } },
3977{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RT } },
3978{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RT } },
3979{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RT } },
3980{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RT } },
3981{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RT } },
3982{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RT } },
3983{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RT } },
3984{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RT } },
3985{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RT } },
3986{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RT } },
3987{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RT } },
3988{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RT } },
3989{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RT } },
3990{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RT } },
3991{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RT } },
3992{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RT } },
3993{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RT } },
3994{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RT } },
3995{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RT } },
3996{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RT } },
3997{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RT } },
3998{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RT } },
3999{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RT } },
4000{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RT } },
4001{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RT } },
4002{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RT } },
4003{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RT } },
4004{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RT } },
4005{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RT } },
4006{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RT } },
4007{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RT } },
4008{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RT } },
4009{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RT } },
4010{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
252b5132
RH		 4011
4012{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4013
4014{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4015{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4016
418c1742
MG		 4017{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4018
4db3857a 4019{ "dcread", X(31,486), X_MASK, PPC403, { RT, RA, RB }},
252b5132 4020
914749f6 4021{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
23976049
EZ		 4022
4023{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4024
252b5132 4025{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
418c1742 4026{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
252b5132
RH		 4027{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4028{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
418c1742 4029{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
252b5132
RH		 4030{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4031
4032{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4033{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4034{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4035{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4036
418c1742
MG		 4037{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4038{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4039
252b5132
RH		 4040{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4041{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4042{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4043{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4044
dde1b132 4045{ "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 4046
252b5132
RH		 4047{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
4048
4049{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4050
418c1742
MG		 4051{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4052
252b5132
RH		 4053{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
4054
23976049 4055{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
dde1b132 4056{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
418c1742 4057
252b5132
RH		 4058{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4059
4060{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } },
4061{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4062
4063{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA, RB } },
4064{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4065
4066{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB } },
4067
4068{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4069{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4070{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4071{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4072
4073{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4074{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4075
4076{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4077{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4078
4079{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4080{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4081
418c1742
MG		 4082{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA, RB } },
4083
4084{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA, RB } },
4085
23976049 4086{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
252b5132
RH		 4087{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4088
4089{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4090
418c1742
MG		 4091{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4092
252b5132
RH		 4093{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4094
4095{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } },
4096{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } },
4097
6ba045b1
AM		 4098{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPCONLY, { 0 } },
4099{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
b6be6416 4100{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
6ba045b1 4101{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
252b5132
RH		 4102{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4103
4104{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } },
4105
418c1742
MG		 4106{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA, RB } },
4107
252b5132
RH		 4108{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4109
4110{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4111
4112{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4113
418c1742
MG		 4114{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4115
252b5132
RH		 4116{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4117
4118{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } },
4119{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA, RB } },
4120
4121{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA, RB } },
4122{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA, RB } },
4123
4124{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA, RB } },
4125
4126{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4127{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4128
4129{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4130{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4131
418c1742
MG		 4132{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA, RB } },
4133
4134{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA, RB } },
4135
252b5132
RH		 4136{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4137
4138{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4139{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4140
418c1742
MG		 4141{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4142
252b5132
RH		 4143{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } },
4144{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB } },
4145
4146{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA, RB } },
4147
4148{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4149{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4150
4151{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4152{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4153
418c1742
MG		 4154{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA, RB } },
4155
e0c21649 4156{ "dcba", X(31,758), XRT_MASK, PPC405, { RA, RB } },
9fa87a06 4157{ "dcba", X(31,758), XRT_MASK, BOOKE, { RA, RB } },
e0c21649 4158
252b5132
RH		 4159{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4160
4161{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4162{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4163
418c1742
MG		 4164{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4165
4166{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4167
4168{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
dde1b132 4169{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
418c1742 4170
252b5132
RH		 4171{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } },
4172
4173{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4174{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4175{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4176{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4177
4178{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4179{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4180
418c1742
MG		 4181{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA, RB } },
4182
4183{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA, RB } },
4184{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA, RB } },
4185
252b5132
RH		 4186{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4187
f5c120c5 4188{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
eb0fdfed 4189{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
f5c120c5 4190
252b5132
RH		 4191{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4192{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4193{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4194{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4195
6ba045b1
AM		 4196{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4197
b6be6416 4198{ "mbar", X(31,854), X_MASK, BOOKE, { MO } },
252b5132
RH		 4199{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4200
9fa87a06
MG		 4201{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
4202{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
252b5132 4203
9fa87a06 4204{ "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
7d4a12d2 4205{ "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } },
dde1b132
NC		 4206{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4207{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
418c1742 4208
6ba045b1
AM		 4209{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4210
252b5132
RH		 4211{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } },
4212
4213{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4214{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4215
4216{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4217{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4218
4219{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4220{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4221{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4222{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4223
418c1742
MG		 4224{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA, RB } },
4225
4226{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA, RB } },
4227
2e32aab9 4228{ "tlbre", X(31,946), X_MASK, BOOKE, { 0 } },
418c1742 4229
e0c21649
GK		 4230{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4231{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
1c7c333e 4232{ "tlbre", X(31,946), X_MASK, PPC403, { RS, RA, SH } },
252b5132
RH		 4233
4234{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4235{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4236
4237{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4238{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4239
418c1742
MG		 4240{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4241
e0c21649 4242{ "iccci", X(31,966), XRT_MASK, PPC403, { RA, RB } },
252b5132 4243
2e32aab9
NC		 4244{ "tlbwe", X(31,978), X_MASK, BOOKE, { 0 } },
4245
252b5132 4246{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
e0c21649
GK		 4247
4248{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4249{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
252b5132
RH		 4250{ "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } },
4251
4252{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4253
4254{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
4255
dde1b132
NC		 4256{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4257{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
252b5132
RH		 4258
4259{ "icread", X(31,998), XRT_MASK, PPC403, { RA, RB } },
4260
418c1742
MG		 4261{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4262{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA, RB } },
4263
252b5132
RH		 4264{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4265
4266{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4267{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4268
418c1742
MG		 4269{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4270
786e2c0f
C		 4271{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4272{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4273{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4274{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4275{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4276{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4277{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4278{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4279{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4280{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4281{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4282{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4283
252b5132
RH		 4284{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } },
4285{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } },
4286
4287{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4288{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA } },
4289
4290{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA } },
4291
4292{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4293
4294{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } },
4295{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA } },
4296
4297{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4298{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA } },
4299
4300{ "stb", OP(38), OP_MASK, COM, { RS, D, RA } },
4301
4302{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4303
4304{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA } },
4305
4306{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4307
4308{ "lha", OP(42), OP_MASK, COM, { RT, D, RA } },
4309
4310{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4311
4312{ "sth", OP(44), OP_MASK, COM, { RS, D, RA } },
4313
4314{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4315
4316{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4317{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA } },
4318
4319{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } },
4320{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA } },
4321
4322{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } },
4323
4324{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4325
4326{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } },
4327
4328{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4329
4330{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } },
4331
4332{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4333
4334{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } },
4335
4336{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4337
4338{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
4339
4340{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
4341
418c1742
MG		 4342{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA } },
4343{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4344{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA } },
4345{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4346{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA } },
4347{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4348{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA } },
4349{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4350{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA } },
4351{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4352{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA } },
4353{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4354{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA } },
4355{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4356
802a735e
AM		 4357{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA } },
4358
4359{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4360
4361{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } },
4362
252b5132
RH		 4363{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4364{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4365
4366{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4367{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4368
4369{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4370{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4371
4372{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4373{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4374
4375{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4376{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4377
4378{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4379{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4380
4381{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4382{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4383
4384{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4385{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4386
4387{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4388{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4389
4390{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4391{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4392
4393{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4394
4395{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4396
418c1742 4397{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA } },
418c1742 4398{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA } },
418c1742
MG		 4399{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA } },
4400{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4401{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA } },
4402{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4403{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA } },
4404{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4405{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA } },
4406{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4407{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA } },
4408{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4409
802a735e
AM		 4410{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } },
4411
4412{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
4413
252b5132
RH		 4414{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4415
4416{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4417{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4418
4419{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4420{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
4421{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4422{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4423
4424{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4425{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
4426{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4427{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4428
4429{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4430{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4431{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4432{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4433
4434{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4435{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4436{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4437{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4438
4439{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4440{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4441{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4442{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4443
4444{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4445{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4446
4447{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4448{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4449
4450{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4451{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4452{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4453{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4454
4455{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4456{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4457
4458{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4459{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4460{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4461{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4462
4463{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4464{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4465{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4466{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4467
4468{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4469{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4470{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4471{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4472
4473{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4474{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4475{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4476{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4477
4478{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4479
4480{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4481{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
4482
4483{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
4484{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
4485
4486{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4487
4488{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4489{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4490
4491{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4492{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4493
4494{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4495{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4496
4497{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4498{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4499
4500{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4501{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4502
4503{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4504{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4505
4506{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
4507{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
4508
4509{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
4510{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
4511
4512{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
4513{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
4514
4515{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
4516{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
4517
4518};
4519
4520const int powerpc_num_opcodes =
4521 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4522\f
4523/* The macro table. This is only used by the assembler. */
4524
4525/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4526 when x=0; 32-x when x is between 1 and 31; are negative if x is
4527 negative; and are 32 or more otherwise. This is what you want
4528 when, for instance, you are emulating a right shift by a
4529 rotate-left-and-mask, because the underlying instructions support
4530 shifts of size 0 but not shifts of size 32. By comparison, when
4531 extracting x bits from some word you want to use just 32-x, because
4532 the underlying instructions don't support extracting 0 bits but do
4533 support extracting the whole word (32 bits in this case). */
4534
4535const struct powerpc_macro powerpc_macros[] = {
4536{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
4537{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
4538{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4539{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4540{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4541{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4542{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4543{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4544{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
4545{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
4546{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4547{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4548{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
4549{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
4550{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
4551{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
4552
4553{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
4554{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
29ef7e54
AM		 4555{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4556{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
252b5132
RH		 4557{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4558{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4559{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4560{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4561{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4562{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4563{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
4564{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
4565{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
4566{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
4567{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4568{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4569{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4570{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4571{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
4572{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
4573{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4574{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
252b5132
RH		 4575};
4576
4577const int powerpc_num_macros =
4578 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
GDB Binutils - Deliverables
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