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[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c
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252b5132 1/* ppc-opc.c -- PowerPC opcode list
6f2750fe 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
252b5132
RH		 3 Written by Ian Lance Taylor, Cygnus Support
4
9b201bb5 5 This file is part of the GNU opcodes library.
252b5132 6
9b201bb5
NC		 7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
252b5132 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
252b5132 16
112290ab 17 You should have received a copy of the GNU General Public License
9b201bb5
NC		 18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
252b5132 21
0d8dfecf 22#include "sysdep.h"
df7b86aa 23#include <stdio.h>
252b5132
RH		 24#include "opcode/ppc.h"
25#include "opintl.h"
26
27/* This file holds the PowerPC opcode table. The opcode table
28 includes almost all of the extended instruction mnemonics. This
29 permits the disassembler to use them, and simplifies the assembler
30 logic, at the cost of increasing the table size. The table is
31 strictly constant data, so the compiler should be able to put it in
32 the .text section.
33
34 This file also holds the operand table. All knowledge about
35 inserting operands into instructions and vice-versa is kept in this
36 file. */
37\f
38/* Local insertion and extraction functions. */
39
b9c361e0
JL		 40static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **);
41static long extract_arx (unsigned long, ppc_cpu_t, int *);
42static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **);
43static long extract_ary (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 44static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
45static long extract_bat (unsigned long, ppc_cpu_t, int *);
46static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
47static long extract_bba (unsigned long, ppc_cpu_t, int *);
48static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
49static long extract_bdm (unsigned long, ppc_cpu_t, int *);
50static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
51static long extract_bdp (unsigned long, ppc_cpu_t, int *);
52static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
53static long extract_bo (unsigned long, ppc_cpu_t, int *);
54static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
55static long extract_boe (unsigned long, ppc_cpu_t, int *);
7b934113 56static unsigned long insert_esync (unsigned long, long, ppc_cpu_t, const char **);
a680de9a
PB		 57static unsigned long insert_dcmxs (unsigned long, long, ppc_cpu_t, const char **);
58static long extract_dcmxs (unsigned long, ppc_cpu_t, int *);
59static unsigned long insert_dxd (unsigned long, long, ppc_cpu_t, const char **);
60static long extract_dxd (unsigned long, ppc_cpu_t, int *);
61static unsigned long insert_dxdn (unsigned long, long, ppc_cpu_t, const char **);
62static long extract_dxdn (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 63static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
64static long extract_fxm (unsigned long, ppc_cpu_t, int *);
b9c361e0
JL		 65static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
66static long extract_li20 (unsigned long, ppc_cpu_t, int *);
aea77599 67static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
fa452fa6
PB		 68static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
69static long extract_mbe (unsigned long, ppc_cpu_t, int *);
70static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
71static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
72static long extract_nb (unsigned long, ppc_cpu_t, int *);
989993d8 73static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **);
fa452fa6
PB		 74static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
75static long extract_nsi (unsigned long, ppc_cpu_t, int *);
b9c361e0
JL		 76static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **);
77static long extract_oimm (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 78static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
79static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
80static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
81static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
82static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
83static long extract_rbs (unsigned long, ppc_cpu_t, int *);
989993d8 84static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **);
b9c361e0
JL		 85static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **);
86static long extract_rx (unsigned long, ppc_cpu_t, int *);
87static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **);
88static long extract_ry (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 89static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
90static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
b9c361e0
JL		 91static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **);
92static long extract_sci8 (unsigned long, ppc_cpu_t, int *);
93static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **);
94static long extract_sci8n (unsigned long, ppc_cpu_t, int *);
95static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **);
96static long extract_sd4h (unsigned long, ppc_cpu_t, int *);
97static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **);
98static long extract_sd4w (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 99static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
100static long extract_spr (unsigned long, ppc_cpu_t, int *);
101static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
102static long extract_sprg (unsigned long, ppc_cpu_t, int *);
103static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
104static long extract_tbr (unsigned long, ppc_cpu_t, int *);
9b4e5766
PB		 105static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
106static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
a680de9a
PB		 107static unsigned long insert_xtq6 (unsigned long, long, ppc_cpu_t, const char **);
108static long extract_xtq6 (unsigned long, ppc_cpu_t, int *);
9b4e5766
PB		 109static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
110static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
111static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
112static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
113static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
114static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
066be9f7
PB		 115static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
116static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
117static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
118static long extract_dm (unsigned long, ppc_cpu_t, int *);
b9c361e0
JL		 119static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **);
120static long extract_vlesi (unsigned long, ppc_cpu_t, int *);
121static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **);
122static long extract_vlensi (unsigned long, ppc_cpu_t, int *);
123static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **);
124static long extract_vleui (unsigned long, ppc_cpu_t, int *);
125static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **);
126static long extract_vleil (unsigned long, ppc_cpu_t, int *);
252b5132
RH		 127\f
128/* The operands table.
129
717bbdf1 130 The fields are bitm, shift, insert, extract, flags.
252b5132
RH		 131
132 We used to put parens around the various additions, like the one
133 for BA just below. However, that caused trouble with feeble
134 compilers with a limit on depth of a parenthesized expression, like
135 (reportedly) the compiler in Microsoft Developer Studio 5. So we
136 omit the parens, since the macros are never used in a context where
137 the addition will be ambiguous. */
138
139const struct powerpc_operand powerpc_operands[] =
140{
141 /* The zero index is used to indicate the end of the list of
142 operands. */
143#define UNUSED 0
bbac1f2a 144 { 0, 0, NULL, NULL, 0 },
252b5132
RH		 145
146 /* The BA field in an XL form instruction. */
147#define BA UNUSED + 1
717bbdf1
AM		 148 /* The BI field in a B form or XL form instruction. */
149#define BI BA
150#define BI_MASK (0x1f << 16)
b9c361e0 151 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
252b5132
RH		 152
153 /* The BA field in an XL form instruction when it must be the same
154 as the BT field in the same instruction. */
155#define BAT BA + 1
b84bf58a 156 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
252b5132
RH		 157
158 /* The BB field in an XL form instruction. */
159#define BB BAT + 1
160#define BB_MASK (0x1f << 11)
b9c361e0 161 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT },
252b5132
RH		 162
163 /* The BB field in an XL form instruction when it must be the same
164 as the BA field in the same instruction. */
165#define BBA BB + 1
c7a5aa9c
PB		 166 /* The VB field in a VX form instruction when it must be the same
167 as the VA field in the same instruction. */
168#define VBA BBA
b84bf58a 169 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
252b5132
RH		 170
171 /* The BD field in a B form instruction. The lower two bits are
172 forced to zero. */
173#define BD BBA + 1
b84bf58a 174 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 175
176 /* The BD field in a B form instruction when absolute addressing is
177 used. */
178#define BDA BD + 1
b84bf58a 179 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 180
181 /* The BD field in a B form instruction when the - modifier is used.
182 This sets the y bit of the BO field appropriately. */
183#define BDM BDA + 1
b84bf58a 184 { 0xfffc, 0, insert_bdm, extract_bdm,
e43de63c 185 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 186
187 /* The BD field in a B form instruction when the - modifier is used
188 and absolute address is used. */
189#define BDMA BDM + 1
b84bf58a 190 { 0xfffc, 0, insert_bdm, extract_bdm,
e43de63c 191 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 192
193 /* The BD field in a B form instruction when the + modifier is used.
194 This sets the y bit of the BO field appropriately. */
195#define BDP BDMA + 1
b84bf58a 196 { 0xfffc, 0, insert_bdp, extract_bdp,
e43de63c 197 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 198
199 /* The BD field in a B form instruction when the + modifier is used
200 and absolute addressing is used. */
201#define BDPA BDP + 1
b84bf58a 202 { 0xfffc, 0, insert_bdp, extract_bdp,
e43de63c 203 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 204
205 /* The BF field in an X or XL form instruction. */
206#define BF BDPA + 1
717bbdf1
AM		 207 /* The CRFD field in an X form instruction. */
208#define CRFD BF
b9c361e0
JL		 209 /* The CRD field in an XL form instruction. */
210#define CRD BF
211 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG },
252b5132 212
ea192fa3
PB		 213 /* The BF field in an X or XL form instruction. */
214#define BFF BF + 1
215 { 0x7, 23, NULL, NULL, 0 },
216
252b5132
RH		 217 /* An optional BF field. This is used for comparison instructions,
218 in which an omitted BF field is taken as zero. */
ea192fa3 219#define OBF BFF + 1
b9c361e0 220 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
252b5132
RH		 221
222 /* The BFA field in an X or XL form instruction. */
223#define BFA OBF + 1
b9c361e0 224 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG },
252b5132 225
252b5132
RH		 226 /* The BO field in a B form instruction. Certain values are
227 illegal. */
717bbdf1 228#define BO BFA + 1
252b5132 229#define BO_MASK (0x1f << 21)
b84bf58a 230 { 0x1f, 21, insert_bo, extract_bo, 0 },
252b5132
RH		 231
232 /* The BO field in a B form instruction when the + or - modifier is
233 used. This is like the BO field, but it must be even. */
234#define BOE BO + 1
b84bf58a 235 { 0x1e, 21, insert_boe, extract_boe, 0 },
252b5132 236
6fd3a02d
PB		 237 /* The RM field in an X form instruction. */
238#define RM BOE + 1
239 { 0x3, 11, NULL, NULL, 0 },
240
241#define BH RM + 1
b84bf58a 242 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
d0618d1c 243
252b5132 244 /* The BT field in an X or XL form instruction. */
d0618d1c 245#define BT BH + 1
b9c361e0
JL		 246 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT },
247
248 /* The BI16 field in a BD8 form instruction. */
249#define BI16 BT + 1
250 { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT },
251
252 /* The BI32 field in a BD15 form instruction. */
253#define BI32 BI16 + 1
254 { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
255
256 /* The BO32 field in a BD15 form instruction. */
257#define BO32 BI32 + 1
258 { 0x3, 20, NULL, NULL, 0 },
259
260 /* The B8 field in a BD8 form instruction. */
261#define B8 BO32 + 1
262 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
263
264 /* The B15 field in a BD15 form instruction. The lowest bit is
265 forced to zero. */
266#define B15 B8 + 1
267 { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
268
269 /* The B24 field in a BD24 form instruction. The lowest bit is
270 forced to zero. */
271#define B24 B15 + 1
272 { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 273
274 /* The condition register number portion of the BI field in a B form
275 or XL form instruction. This is used for the extended
276 conditional branch mnemonics, which set the lower two bits of the
277 BI field. This field is optional. */
b9c361e0
JL		 278#define CR B24 + 1
279 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
252b5132 280
23976049
EZ		 281 /* The CRB field in an X form instruction. */
282#define CRB CR + 1
717bbdf1
AM		 283 /* The MB field in an M form instruction. */
284#define MB CRB
285#define MB_MASK (0x1f << 6)
b84bf58a 286 { 0x1f, 6, NULL, NULL, 0 },
23976049 287
b9c361e0
JL		 288 /* The CRD32 field in an XL form instruction. */
289#define CRD32 CRB + 1
290 { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG },
291
23976049 292 /* The CRFS field in an X form instruction. */
b9c361e0
JL		 293#define CRFS CRD32 + 1
294 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG },
295
296#define CRS CRFS + 1
297 { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
23976049 298
418c1742 299 /* The CT field in an X form instruction. */
b9c361e0 300#define CT CRS + 1
717bbdf1
AM		 301 /* The MO field in an mbar instruction. */
302#define MO CT
b84bf58a 303 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
418c1742 304
252b5132
RH		 305 /* The D field in a D form instruction. This is a displacement off
306 a register, and implies that the next operand is a register in
307 parentheses. */
418c1742 308#define D CT + 1
b84bf58a 309 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
252b5132 310
b9c361e0
JL		 311 /* The D8 field in a D form instruction. This is a displacement off
312 a register, and implies that the next operand is a register in
313 parentheses. */
314#define D8 D + 1
315 { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
316
a680de9a
PB		 317 /* The DCMX field in an X form instruction. */
318#define DCMX D8 + 1
319 { 0x7f, 16, NULL, NULL, 0 },
320
321 /* The split DCMX field in an X form instruction. */
322#define DCMXS DCMX + 1
323 { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 },
324
adadcc0c
AM		 325 /* The DQ field in a DQ form instruction. This is like D, but the
326 lower four bits are forced to zero. */
a680de9a 327#define DQ DCMXS + 1
b84bf58a
AM		 328 { 0xfff0, 0, NULL, NULL,
329 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
adadcc0c 330
252b5132
RH		 331 /* The DS field in a DS form instruction. This is like D, but the
332 lower two bits are forced to zero. */
adadcc0c 333#define DS DQ + 1
b84bf58a
AM		 334 { 0xfffc, 0, NULL, NULL,
335 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
252b5132 336
c0637f3a
PB		 337 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
338 unsigned imediate */
19a6653c 339#define DUIS DS + 1
c0637f3a 340#define BHRBE DUIS
19a6653c
AM		 341 { 0x3ff, 11, NULL, NULL, 0 },
342
a680de9a
PB		 343 /* The split D field in a DX form instruction. */
344#define DXD DUIS + 1
345 { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd,
346 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
347
348 /* The split ND field in a DX form instruction.
349 This is the same as the DX field, only negated. */
350#define NDXD DXD + 1
351 { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn,
352 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
353
252b5132 354 /* The E field in a wrteei instruction. */
c3d65c1c 355 /* And the W bit in the pair singles instructions. */
c0637f3a 356 /* And the ST field in a VX form instruction. */
a680de9a 357#define E NDXD + 1
c3d65c1c 358#define PSW E
c0637f3a 359#define ST E
b84bf58a 360 { 0x1, 15, NULL, NULL, 0 },
252b5132
RH		 361
362 /* The FL1 field in a POWER SC form instruction. */
363#define FL1 E + 1
717bbdf1
AM		 364 /* The U field in an X form instruction. */
365#define U FL1
b84bf58a 366 { 0xf, 12, NULL, NULL, 0 },
252b5132
RH		 367
368 /* The FL2 field in a POWER SC form instruction. */
369#define FL2 FL1 + 1
b84bf58a 370 { 0x7, 2, NULL, NULL, 0 },
252b5132
RH		 371
372 /* The FLM field in an XFL form instruction. */
373#define FLM FL2 + 1
b84bf58a 374 { 0xff, 17, NULL, NULL, 0 },
252b5132
RH		 375
376 /* The FRA field in an X or A form instruction. */
377#define FRA FLM + 1
378#define FRA_MASK (0x1f << 16)
b84bf58a 379 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
252b5132 380
989993d8
JB		 381 /* The FRAp field of DFP instructions. */
382#define FRAp FRA + 1
383 { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR },
384
252b5132 385 /* The FRB field in an X or A form instruction. */
989993d8 386#define FRB FRAp + 1
252b5132 387#define FRB_MASK (0x1f << 11)
b84bf58a 388 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
252b5132 389
989993d8
JB		 390 /* The FRBp field of DFP instructions. */
391#define FRBp FRB + 1
392 { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR },
393
252b5132 394 /* The FRC field in an A form instruction. */
989993d8 395#define FRC FRBp + 1
252b5132 396#define FRC_MASK (0x1f << 6)
b84bf58a 397 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 398
399 /* The FRS field in an X form instruction or the FRT field in a D, X
400 or A form instruction. */
401#define FRS FRC + 1
402#define FRT FRS
b84bf58a 403 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
252b5132 404
989993d8
JB		 405 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
406 instructions. */
407#define FRSp FRS + 1
408#define FRTp FRSp
409 { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR },
410
252b5132 411 /* The FXM field in an XFX instruction. */
989993d8 412#define FXM FRSp + 1
b84bf58a 413 { 0xff, 12, insert_fxm, extract_fxm, 0 },
c168870a
AM		 414
415 /* Power4 version for mfcr. */
416#define FXM4 FXM + 1
e43de63c
AM		 417 { 0xff, 12, insert_fxm, extract_fxm,
418 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
11a0cf2e
PB		 419 /* If the FXM4 operand is ommitted, use the sentinel value -1. */
420 { -1, -1, NULL, NULL, 0},
252b5132 421
b9c361e0 422 /* The IMM20 field in an LI instruction. */
11a0cf2e 423#define IMM20 FXM4 + 2
b9c361e0
JL		 424 { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},
425
252b5132 426 /* The L field in a D or X form instruction. */
b9c361e0 427#define L IMM20 + 1
a5721ba2
AM		 428 { 0x1, 21, NULL, NULL, 0 },
429
430 /* The optional L field in tlbie and tlbiel instructions. */
431#define LOPT L + 1
5817ffd1 432 /* The R field in a HTM X form instruction. */
a5721ba2 433#define HTM_R LOPT
b84bf58a 434 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
252b5132 435
a5721ba2
AM		 436 /* The optional (for 32-bit) L field in cmp[l][i] instructions. */
437#define L32OPT LOPT + 1
438 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 },
a680de9a 439
a5721ba2
AM		 440 /* The L field in dcbf instruction. */
441#define L2OPT L32OPT + 1
442 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
a680de9a 443
1ed8e1e4 444 /* The LEV field in a POWER SVC form instruction. */
a5721ba2 445#define SVC_LEV L2OPT + 1
b84bf58a 446 { 0x7f, 5, NULL, NULL, 0 },
252b5132 447
1ed8e1e4
AM		 448 /* The LEV field in an SC form instruction. */
449#define LEV SVC_LEV + 1
b84bf58a 450 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
1ed8e1e4 451
252b5132
RH		 452 /* The LI field in an I form instruction. The lower two bits are
453 forced to zero. */
454#define LI LEV + 1
b84bf58a 455 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 456
457 /* The LI field in an I form instruction when used as an absolute
458 address. */
459#define LIA LI + 1
b84bf58a 460 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132 461
066be9f7 462 /* The LS or WC field in an X (sync or wait) form instruction. */
6ba045b1 463#define LS LIA + 1
066be9f7 464#define WC LS
7b934113 465 { 0x3, 21, insert_ls, NULL, PPC_OPERAND_OPTIONAL },
6ba045b1 466
252b5132 467 /* The ME field in an M form instruction. */
717bbdf1 468#define ME LS + 1
252b5132 469#define ME_MASK (0x1f << 1)
b84bf58a 470 { 0x1f, 1, NULL, NULL, 0 },
252b5132
RH		 471
472 /* The MB and ME fields in an M form instruction expressed a single
473 operand which is a bitmask indicating which bits to select. This
474 is a two operand form using PPC_OPERAND_NEXT. See the
475 description in opcode/ppc.h for what this means. */
476#define MBE ME + 1
b84bf58a 477 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
eb42fac1 478 { -1, 0, insert_mbe, extract_mbe, 0 },
252b5132
RH		 479
480 /* The MB or ME field in an MD or MDS form instruction. The high
481 bit is wrapped to the low end. */
482#define MB6 MBE + 2
483#define ME6 MB6
484#define MB6_MASK (0x3f << 5)
b84bf58a 485 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
252b5132
RH		 486
487 /* The NB field in an X form instruction. The value 32 is stored as
488 0. */
717bbdf1 489#define NB MB6 + 1
b84bf58a 490 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
252b5132 491
989993d8
JB		 492 /* The NBI field in an lswi instruction, which has special value
493 restrictions. The value 32 is stored as 0. */
494#define NBI NB + 1
495 { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 },
496
252b5132
RH		 497 /* The NSI field in a D form instruction. This is the same as the
498 SI field, only negated. */
989993d8 499#define NSI NBI + 1
b84bf58a 500 { 0xffff, 0, insert_nsi, extract_nsi,
e43de63c
AM		 501 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
502
503 /* The NSI field in a D form instruction when we accept a wide range
504 of positive values. */
505#define NSISIGNOPT NSI + 1
514e58b7 506 { 0xffff, 0, insert_nsi, extract_nsi,
e43de63c 507 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
252b5132 508
adadcc0c 509 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
e43de63c 510#define RA NSISIGNOPT + 1
252b5132 511#define RA_MASK (0x1f << 16)
b84bf58a 512 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
252b5132 513
fdd12ef3
AM		 514 /* As above, but 0 in the RA field means zero, not r0. */
515#define RA0 RA + 1
b84bf58a 516 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
fdd12ef3 517
989993d8 518 /* The RA field in the DQ form lq or an lswx instruction, which have special
adadcc0c 519 value restrictions. */
fdd12ef3 520#define RAQ RA0 + 1
989993d8 521#define RAX RAQ
b84bf58a 522 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
adadcc0c 523
252b5132
RH		 524 /* The RA field in a D or X form instruction which is an updating
525 load, which means that the RA field may not be zero and may not
526 equal the RT field. */
adadcc0c 527#define RAL RAQ + 1
b84bf58a 528 { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
252b5132
RH		 529
530 /* The RA field in an lmw instruction, which has special value
531 restrictions. */
532#define RAM RAL + 1
b84bf58a 533 { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
252b5132
RH		 534
535 /* The RA field in a D or X form instruction which is an updating
536 store or an updating floating point load, which means that the RA
537 field may not be zero. */
538#define RAS RAM + 1
b84bf58a 539 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
252b5132 540
cee62821
PB		 541 /* The RA field of the tlbwe, dccci and iccci instructions,
542 which are optional. */
fdd12ef3 543#define RAOPT RAS + 1
b84bf58a 544 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 545
252b5132 546 /* The RB field in an X, XO, M, or MDS form instruction. */
fdd12ef3 547#define RB RAOPT + 1
252b5132 548#define RB_MASK (0x1f << 11)
b84bf58a 549 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
252b5132
RH		 550
551 /* The RB field in an X form instruction when it must be the same as
552 the RS field in the instruction. This is used for extended
553 mnemonics like mr. */
554#define RBS RB + 1
b84bf58a 555 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
252b5132 556
989993d8
JB		 557 /* The RB field in an lswx instruction, which has special value
558 restrictions. */
559#define RBX RBS + 1
560 { 0x1f, 11, insert_rbx, NULL, PPC_OPERAND_GPR },
561
cee62821 562 /* The RB field of the dccci and iccci instructions, which are optional. */
989993d8 563#define RBOPT RBX + 1
cee62821
PB		 564 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
565
a680de9a
PB		 566 /* The RC register field in an maddld, maddhd or maddhdu instruction. */
567#define RC RBOPT + 1
568 { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR },
569
252b5132
RH		 570 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
571 instruction or the RT field in a D, DS, X, XFX or XO form
572 instruction. */
a680de9a 573#define RS RC + 1
252b5132
RH		 574#define RT RS
575#define RT_MASK (0x1f << 21)
b9c361e0 576#define RD RS
b84bf58a 577 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
252b5132 578
588925d0
PB		 579 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
580 which have special value restrictions. */
adadcc0c 581#define RSQ RS + 1
717bbdf1 582#define RTQ RSQ
588925d0 583 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR },
adadcc0c 584
1f6c9eb0 585 /* The RS field of the tlbwe instruction, which is optional. */
717bbdf1 586#define RSO RSQ + 1
eed0d89a 587#define RTO RSO
b84bf58a 588 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 589
b9c361e0
JL		 590 /* The RX field of the SE_RR form instruction. */
591#define RX RSO + 1
592 { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR },
593
594 /* The ARX field of the SE_RR form instruction. */
595#define ARX RX + 1
596 { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR },
597
598 /* The RY field of the SE_RR form instruction. */
599#define RY ARX + 1
600#define RZ RY
601 { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR },
602
603 /* The ARY field of the SE_RR form instruction. */
604#define ARY RY + 1
605 { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR },
606
607 /* The SCLSCI8 field in a D form instruction. */
608#define SCLSCI8 ARY + 1
609 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 },
610
611 /* The SCLSCI8N field in a D form instruction. This is the same as the
612 SCLSCI8 field, only negated. */
613#define SCLSCI8N SCLSCI8 + 1
614 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n,
e43de63c 615 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
b9c361e0
JL		 616
617 /* The SD field of the SD4 form instruction. */
618#define SE_SD SCLSCI8N + 1
619 { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS },
620
621 /* The SD field of the SD4 form instruction, for halfword. */
622#define SE_SDH SE_SD + 1
623 { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS },
624
625 /* The SD field of the SD4 form instruction, for word. */
626#define SE_SDW SE_SDH + 1
627 { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS },
628
252b5132 629 /* The SH field in an X or M form instruction. */
b9c361e0 630#define SH SE_SDW + 1
252b5132 631#define SH_MASK (0x1f << 11)
717bbdf1
AM		 632 /* The other UIMM field in a EVX form instruction. */
633#define EVUIMM SH
a680de9a
PB		 634 /* The FC field in an atomic X form instruction. */
635#define FC SH
b84bf58a 636 { 0x1f, 11, NULL, NULL, 0 },
252b5132 637
5817ffd1
PB		 638 /* The SI field in a HTM X form instruction. */
639#define HTM_SI SH + 1
640 { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED },
641
252b5132 642 /* The SH field in an MD form instruction. This is split. */
5817ffd1 643#define SH6 HTM_SI + 1
252b5132 644#define SH6_MASK ((0x1f << 11) | (1 << 1))
b9c361e0 645 { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
252b5132 646
1f6c9eb0
ZW		 647 /* The SH field of the tlbwe instruction, which is optional. */
648#define SHO SH6 + 1
b84bf58a 649 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
1f6c9eb0 650
252b5132 651 /* The SI field in a D form instruction. */
1f6c9eb0 652#define SI SHO + 1
b84bf58a 653 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
252b5132
RH		 654
655 /* The SI field in a D form instruction when we accept a wide range
656 of positive values. */
657#define SISIGNOPT SI + 1
b84bf58a 658 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
252b5132 659
b9c361e0
JL		 660 /* The SI8 field in a D form instruction. */
661#define SI8 SISIGNOPT + 1
662 { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
663
252b5132
RH		 664 /* The SPR field in an XFX form instruction. This is flipped--the
665 lower 5 bits are stored in the upper 5 and vice- versa. */
b9c361e0 666#define SPR SI8 + 1
914749f6 667#define PMR SPR
aea77599 668#define TMR SPR
252b5132 669#define SPR_MASK (0x3ff << 11)
b84bf58a 670 { 0x3ff, 11, insert_spr, extract_spr, 0 },
252b5132
RH		 671
672 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
673#define SPRBAT SPR + 1
674#define SPRBAT_MASK (0x3 << 17)
b84bf58a 675 { 0x3, 17, NULL, NULL, 0 },
252b5132
RH		 676
677 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
678#define SPRG SPRBAT + 1
b84bf58a 679 { 0x1f, 16, insert_sprg, extract_sprg, 0 },
252b5132
RH		 680
681 /* The SR field in an X form instruction. */
682#define SR SPRG + 1
fb048c26
PB		 683 /* The 4-bit UIMM field in a VX form instruction. */
684#define UIMM4 SR
b84bf58a 685 { 0xf, 16, NULL, NULL, 0 },
252b5132 686
f5c120c5
MG		 687 /* The STRM field in an X AltiVec form instruction. */
688#define STRM SR + 1
19a6653c
AM		 689 /* The T field in a tlbilx form instruction. */
690#define T STRM
a5721ba2
AM		 691 /* The L field in wclr instructions. */
692#define L2 STRM
b84bf58a 693 { 0x3, 21, NULL, NULL, 0 },
f5c120c5 694
aea77599
AM		 695 /* The ESYNC field in an X (sync) form instruction. */
696#define ESYNC STRM + 1
7b934113 697 { 0xf, 16, insert_esync, NULL, PPC_OPERAND_OPTIONAL },
aea77599 698
252b5132 699 /* The SV field in a POWER SC form instruction. */
aea77599 700#define SV ESYNC + 1
b84bf58a 701 { 0x3fff, 2, NULL, NULL, 0 },
252b5132
RH		 702
703 /* The TBR field in an XFX form instruction. This is like the SPR
704 field, but it is optional. */
705#define TBR SV + 1
e43de63c
AM		 706 { 0x3ff, 11, insert_tbr, extract_tbr,
707 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
11a0cf2e
PB		 708 /* If the TBR operand is ommitted, use the value 268. */
709 { -1, 268, NULL, NULL, 0},
252b5132
RH		 710
711 /* The TO field in a D or X form instruction. */
11a0cf2e 712#define TO TBR + 2
19a6653c 713#define DUI TO
252b5132 714#define TO_MASK (0x1f << 21)
b84bf58a 715 { 0x1f, 21, NULL, NULL, 0 },
252b5132 716
252b5132 717 /* The UI field in a D form instruction. */
717bbdf1 718#define UI TO + 1
b84bf58a 719 { 0xffff, 0, NULL, NULL, 0 },
786e2c0f 720
a47622ac
AM		 721#define UISIGNOPT UI + 1
722 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT },
723
b9c361e0 724 /* The IMM field in an SE_IM5 instruction. */
a47622ac 725#define UI5 UISIGNOPT + 1
b9c361e0
JL		 726 { 0x1f, 4, NULL, NULL, 0 },
727
728 /* The OIMM field in an SE_OIM5 instruction. */
729#define OIMM5 UI5 + 1
730 { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 },
731
732 /* The UI7 field in an SE_LI instruction. */
733#define UI7 OIMM5 + 1
734 { 0x7f, 4, NULL, NULL, 0 },
735
112290ab 736 /* The VA field in a VA, VX or VXR form instruction. */
b9c361e0 737#define VA UI7 + 1
b84bf58a 738 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 739
112290ab 740 /* The VB field in a VA, VX or VXR form instruction. */
786e2c0f 741#define VB VA + 1
b84bf58a 742 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 743
112290ab 744 /* The VC field in a VA form instruction. */
786e2c0f 745#define VC VB + 1
b84bf58a 746 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 747
112290ab 748 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
786e2c0f
C		 749#define VD VC + 1
750#define VS VD
b84bf58a 751 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 752
8dbcd839 753 /* The SIMM field in a VX form instruction, and TE in Z form. */
786e2c0f 754#define SIMM VD + 1
8dbcd839 755#define TE SIMM
b84bf58a 756 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
786e2c0f 757
8dbcd839 758 /* The UIMM field in a VX form instruction. */
786e2c0f 759#define UIMM SIMM + 1
aea77599 760#define DCTL UIMM
b84bf58a 761 { 0x1f, 16, NULL, NULL, 0 },
786e2c0f 762
fb048c26
PB		 763 /* The 3-bit UIMM field in a VX form instruction. */
764#define UIMM3 UIMM + 1
765 { 0x7, 16, NULL, NULL, 0 },
766
a680de9a
PB		 767 /* The 6-bit UIM field in a X form instruction. */
768#define UIM6 UIMM3 + 1
769 { 0x3f, 16, NULL, NULL, 0 },
770
c0637f3a 771 /* The SIX field in a VX form instruction. */
a680de9a 772#define SIX UIM6 + 1
c0637f3a
PB		 773 { 0xf, 11, NULL, NULL, 0 },
774
775 /* The PS field in a VX form instruction. */
776#define PS SIX + 1
777 { 0x1, 9, NULL, NULL, 0 },
778
112290ab 779 /* The SHB field in a VA form instruction. */
c0637f3a 780#define SHB PS + 1
b84bf58a 781 { 0xf, 6, NULL, NULL, 0 },
ff3a6ee3 782
112290ab 783 /* The other UIMM field in a half word EVX form instruction. */
717bbdf1 784#define EVUIMM_2 SHB + 1
b84bf58a 785 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
23976049 786
112290ab 787 /* The other UIMM field in a word EVX form instruction. */
23976049 788#define EVUIMM_4 EVUIMM_2 + 1
b84bf58a 789 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
23976049 790
112290ab 791 /* The other UIMM field in a double EVX form instruction. */
23976049 792#define EVUIMM_8 EVUIMM_4 + 1
b84bf58a 793 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
23976049 794
6fd3a02d 795 /* The WS or DRM field in an X form instruction. */
23976049 796#define WS EVUIMM_8 + 1
6fd3a02d 797#define DRM WS
b84bf58a 798 { 0x7, 11, NULL, NULL, 0 },
ff3a6ee3 799
c3d65c1c
BE		 800 /* PowerPC paired singles extensions. */
801 /* W bit in the pair singles instructions for x type instructions. */
802#define PSWM WS + 1
b9c361e0
JL		 803 /* The BO16 field in a BD8 form instruction. */
804#define BO16 PSWM
c3d65c1c
BE		 805 { 0x1, 10, 0, 0, 0 },
806
807 /* IDX bits for quantization in the pair singles instructions. */
808#define PSQ PSWM + 1
809 { 0x7, 12, 0, 0, 0 },
810
811 /* IDX bits for quantization in the pair singles x-type instructions. */
812#define PSQM PSQ + 1
813 { 0x7, 7, 0, 0, 0 },
814
815 /* Smaller D field for quantization in the pair singles instructions. */
816#define PSD PSQM + 1
817 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
818
a680de9a 819 /* The L field in an mtmsrd or A form instruction or R or W in an X form. */
c3d65c1c 820#define A_L PSD + 1
ea192fa3 821#define W A_L
a680de9a 822#define X_R A_L
b84bf58a 823 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
5ae2e65e 824
19dfcc89 825 /* The RMC or CY field in a Z23 form instruction. */
99a2c561 826#define RMC A_L + 1
19dfcc89 827#define CY RMC
b84bf58a 828 { 0x3, 9, NULL, NULL, 0 },
702f0fb4
PB		 829
830#define R RMC + 1
b84bf58a 831 { 0x1, 16, NULL, NULL, 0 },
702f0fb4 832
a680de9a
PB		 833#define RIC R + 1
834 { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL },
835
836#define PRS RIC + 1
837 { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
838
839#define SP PRS + 1
b84bf58a 840 { 0x3, 19, NULL, NULL, 0 },
702f0fb4
PB		 841
842#define S SP + 1
b84bf58a 843 { 0x1, 20, NULL, NULL, 0 },
702f0fb4 844
c0637f3a
PB		 845 /* The S field in a XL form instruction. */
846#define SXL S + 1
11a0cf2e
PB		 847 { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
848 /* If the SXL operand is ommitted, use the value 1. */
849 { -1, 1, NULL, NULL, 0},
c0637f3a 850
702f0fb4 851 /* SH field starting at bit position 16. */
11a0cf2e 852#define SH16 SXL + 2
0bbdef92
AM		 853 /* The DCM and DGM fields in a Z form instruction. */
854#define DCM SH16
855#define DGM DCM
b84bf58a 856 { 0x3f, 10, NULL, NULL, 0 },
702f0fb4 857
702f0fb4 858 /* The EH field in larx instruction. */
717bbdf1 859#define EH SH16 + 1
b84bf58a 860 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
ea192fa3
PB		 861
862 /* The L field in an mtfsf or XFL form instruction. */
5817ffd1 863 /* The A field in a HTM X form instruction. */
ea192fa3 864#define XFL_L EH + 1
5817ffd1 865#define HTM_A XFL_L
ea192fa3 866 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
081ba1b3
AM		 867
868 /* Xilinx APU related masks and macros */
869#define FCRT XFL_L + 1
870#define FCRT_MASK (0x1f << 21)
871 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
872
43e65147 873 /* Xilinx FSL related masks and macros */
081ba1b3
AM		 874#define FSL FCRT + 1
875#define FSL_MASK (0x1f << 11)
43e65147 876 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
081ba1b3 877
43e65147 878 /* Xilinx UDI related masks and macros */
081ba1b3
AM		 879#define URT FSL + 1
880 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
881
882#define URA URT + 1
883 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
884
885#define URB URA + 1
886 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
887
888#define URC URB + 1
889 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
890
b9c361e0
JL		 891 /* The VLESIMM field in a D form instruction. */
892#define VLESIMM URC + 1
893 { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
e43de63c 894 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
b9c361e0
JL		 895
896 /* The VLENSIMM field in a D form instruction. */
897#define VLENSIMM VLESIMM + 1
898 { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi,
e43de63c 899 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
b9c361e0
JL		 900
901 /* The VLEUIMM field in a D form instruction. */
902#define VLEUIMM VLENSIMM + 1
903 { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 },
904
905 /* The VLEUIMML field in a D form instruction. */
906#define VLEUIMML VLEUIMM + 1
907 { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 },
908
9b4e5766 909 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
b9c361e0 910#define XS6 VLEUIMML + 1
9b4e5766 911#define XT6 XS6
b9c361e0 912 { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
9b4e5766 913
a680de9a
PB		 914 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
915#define XSQ6 XT6 + 1
916#define XTQ6 XSQ6
917 { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR },
918
9b4e5766 919 /* The XA field in an XX3 form instruction. This is split. */
a680de9a 920#define XA6 XTQ6 + 1
b9c361e0 921 { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
9b4e5766 922
066be9f7 923 /* The XB field in an XX2 or XX3 form instruction. This is split. */
9b4e5766 924#define XB6 XA6 + 1
b9c361e0 925 { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
9b4e5766
PB		 926
927 /* The XB field in an XX3 form instruction when it must be the same as
928 the XA field in the instruction. This is used in extended mnemonics
929 like xvmovdp. This is split. */
930#define XB6S XB6 + 1
b9c361e0 931 { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
9b4e5766 932
066be9f7
PB		 933 /* The XC field in an XX4 form instruction. This is split. */
934#define XC6 XB6S + 1
b9c361e0 935 { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
066be9f7
PB		 936
937 /* The DM or SHW field in an XX3 form instruction. */
938#define DM XC6 + 1
939#define SHW DM
9b4e5766 940 { 0x3, 8, NULL, NULL, 0 },
066be9f7
PB		 941
942 /* The DM field in an extended mnemonic XX3 form instruction. */
943#define DMEX DM + 1
944 { 0x3, 8, insert_dm, extract_dm, 0 },
945
946 /* The UIM field in an XX2 form instruction. */
947#define UIM DMEX + 1
fb048c26
PB		 948 /* The 2-bit UIMM field in a VX form instruction. */
949#define UIMM2 UIM
a680de9a
PB		 950 /* The 2-bit L field in a darn instruction. */
951#define LRAND UIM
066be9f7 952 { 0x3, 16, NULL, NULL, 0 },
e0d602ec
BE		 953
954#define ERAT_T UIM + 1
955 { 0x7, 21, NULL, NULL, 0 },
4bc0608a
PB		 956
957#define IH ERAT_T + 1
958 { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
a680de9a
PB		 959
960 /* The 8-bit IMM8 field in a XX1 form instruction. */
961#define IMM8 IH + 1
1178da44 962 { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT },
252b5132
RH		 963};
964
b84bf58a
AM		 965const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
966 / sizeof (powerpc_operands[0]));
967
252b5132
RH		 968/* The functions used to insert and extract complicated operands. */
969
b9c361e0
JL		 970/* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
971
972static unsigned long
973insert_arx (unsigned long insn,
974 long value,
975 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
976 const char **errmsg ATTRIBUTE_UNUSED)
977{
978 if (value >= 8 && value < 24)
979 return insn | ((value - 8) & 0xf);
980 else
981 {
982 *errmsg = _("invalid register");
983 return 0;
984 }
985}
986
987static long
988extract_arx (unsigned long insn,
989 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
990 int *invalid ATTRIBUTE_UNUSED)
43e65147 991{
b9c361e0
JL		 992 return (insn & 0xf) + 8;
993}
994
995static unsigned long
996insert_ary (unsigned long insn,
997 long value,
998 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
999 const char **errmsg ATTRIBUTE_UNUSED)
1000{
1001 if (value >= 8 && value < 24)
1002 return insn | (((value - 8) & 0xf) << 4);
1003 else
1004 {
1005 *errmsg = _("invalid register");
1006 return 0;
1007 }
1008}
1009
1010static long
1011extract_ary (unsigned long insn,
1012 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1013 int *invalid ATTRIBUTE_UNUSED)
1014{
1015 return ((insn >> 4) & 0xf) + 8;
1016}
1017
1018static unsigned long
1019insert_rx (unsigned long insn,
1020 long value,
1021 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1022 const char **errmsg)
1023{
1024 if (value >= 0 && value < 8)
1025 return insn | value;
1026 else if (value >= 24 && value <= 31)
1027 return insn | (value - 16);
1028 else
1029 {
1030 *errmsg = _("invalid register");
1031 return 0;
1032 }
1033}
1034
1035static long
1036extract_rx (unsigned long insn,
1037 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1038 int *invalid ATTRIBUTE_UNUSED)
1039{
1040 int value = insn & 0xf;
1041 if (value >= 0 && value < 8)
1042 return value;
1043 else
1044 return value + 16;
1045}
1046
1047static unsigned long
1048insert_ry (unsigned long insn,
1049 long value,
1050 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1051 const char **errmsg)
1052{
1053 if (value >= 0 && value < 8)
1054 return insn | (value << 4);
1055 else if (value >= 24 && value <= 31)
1056 return insn | ((value - 16) << 4);
1057 else
1058 {
1059 *errmsg = _("invalid register");
1060 return 0;
1061 }
1062}
1063
1064static long
1065extract_ry (unsigned long insn,
1066 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1067 int *invalid ATTRIBUTE_UNUSED)
1068{
1069 int value = (insn >> 4) & 0xf;
1070 if (value >= 0 && value < 8)
1071 return value;
1072 else
1073 return value + 16;
1074}
1075
252b5132
RH		 1076/* The BA field in an XL form instruction when it must be the same as
1077 the BT field in the same instruction. This operand is marked FAKE.
1078 The insertion function just copies the BT field into the BA field,
1079 and the extraction function just checks that the fields are the
1080 same. */
1081
252b5132 1082static unsigned long
2fbfdc41
AM		 1083insert_bat (unsigned long insn,
1084 long value ATTRIBUTE_UNUSED,
fa452fa6 1085 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1086 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1087{
1088 return insn | (((insn >> 21) & 0x1f) << 16);
1089}
1090
1091static long
2fbfdc41 1092extract_bat (unsigned long insn,
fa452fa6 1093 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1094 int *invalid)
252b5132 1095{
8427c424 1096 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
252b5132
RH		 1097 *invalid = 1;
1098 return 0;
1099}
1100
1101/* The BB field in an XL form instruction when it must be the same as
1102 the BA field in the same instruction. This operand is marked FAKE.
1103 The insertion function just copies the BA field into the BB field,
1104 and the extraction function just checks that the fields are the
1105 same. */
1106
252b5132 1107static unsigned long
2fbfdc41
AM		 1108insert_bba (unsigned long insn,
1109 long value ATTRIBUTE_UNUSED,
fa452fa6 1110 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1111 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1112{
1113 return insn | (((insn >> 16) & 0x1f) << 11);
1114}
1115
1116static long
2fbfdc41 1117extract_bba (unsigned long insn,
fa452fa6 1118 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1119 int *invalid)
252b5132 1120{
8427c424 1121 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 1122 *invalid = 1;
1123 return 0;
1124}
1125
252b5132
RH		 1126/* The BD field in a B form instruction when the - modifier is used.
1127 This modifier means that the branch is not expected to be taken.
94efba12
AM		 1128 For chips built to versions of the architecture prior to version 2
1129 (ie. not Power4 compatible), we set the y bit of the BO field to 1
1130 if the offset is negative. When extracting, we require that the y
1131 bit be 1 and that the offset be positive, since if the y bit is 0
1132 we just want to print the normal form of the instruction.
1133 Power4 compatible targets use two bits, "a", and "t", instead of
1134 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
1135 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
1136 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
ba4e851b
AM		 1137 for branch on CTR. We only handle the taken/not-taken hint here.
1138 Note that we don't relax the conditions tested here when
1139 disassembling with -Many because insns using extract_bdm and
1140 extract_bdp always occur in pairs. One or the other will always
1141 be valid. */
252b5132 1142
8ebac3aa
AM		 1143#define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1144
252b5132 1145static unsigned long
2fbfdc41
AM		 1146insert_bdm (unsigned long insn,
1147 long value,
fa452fa6 1148 ppc_cpu_t dialect,
2fbfdc41 1149 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1150{
8ebac3aa 1151 if ((dialect & ISA_V2) == 0)
802a735e
AM		 1152 {
1153 if ((value & 0x8000) != 0)
1154 insn |= 1 << 21;
1155 }
1156 else
1157 {
1158 if ((insn & (0x14 << 21)) == (0x04 << 21))
1159 insn |= 0x02 << 21;
1160 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1161 insn |= 0x08 << 21;
1162 }
252b5132
RH		 1163 return insn | (value & 0xfffc);
1164}
1165
1166static long
2fbfdc41 1167extract_bdm (unsigned long insn,
fa452fa6 1168 ppc_cpu_t dialect,
2fbfdc41 1169 int *invalid)
252b5132 1170{
8ebac3aa 1171 if ((dialect & ISA_V2) == 0)
802a735e 1172 {
8427c424
AM		 1173 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
1174 *invalid = 1;
802a735e 1175 }
8427c424
AM		 1176 else
1177 {
1178 if ((insn & (0x17 << 21)) != (0x06 << 21)
1179 && (insn & (0x1d << 21)) != (0x18 << 21))
1180 *invalid = 1;
1181 }
1182
802a735e 1183 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 1184}
1185
1186/* The BD field in a B form instruction when the + modifier is used.
1187 This is like BDM, above, except that the branch is expected to be
1188 taken. */
1189
252b5132 1190static unsigned long
2fbfdc41
AM		 1191insert_bdp (unsigned long insn,
1192 long value,
fa452fa6 1193 ppc_cpu_t dialect,
2fbfdc41 1194 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1195{
8ebac3aa 1196 if ((dialect & ISA_V2) == 0)
802a735e
AM		 1197 {
1198 if ((value & 0x8000) == 0)
1199 insn |= 1 << 21;
1200 }
1201 else
1202 {
1203 if ((insn & (0x14 << 21)) == (0x04 << 21))
1204 insn |= 0x03 << 21;
1205 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1206 insn |= 0x09 << 21;
1207 }
252b5132
RH		 1208 return insn | (value & 0xfffc);
1209}
1210
1211static long
2fbfdc41 1212extract_bdp (unsigned long insn,
fa452fa6 1213 ppc_cpu_t dialect,
2fbfdc41 1214 int *invalid)
252b5132 1215{
8ebac3aa 1216 if ((dialect & ISA_V2) == 0)
802a735e 1217 {
8427c424
AM		 1218 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
1219 *invalid = 1;
1220 }
1221 else
1222 {
1223 if ((insn & (0x17 << 21)) != (0x07 << 21)
1224 && (insn & (0x1d << 21)) != (0x19 << 21))
1225 *invalid = 1;
802a735e 1226 }
8427c424 1227
802a735e 1228 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 1229}
1230
8ebac3aa
AM		 1231static inline int
1232valid_bo_pre_v2 (long value)
252b5132 1233{
8ebac3aa
AM		 1234 /* Certain encodings have bits that are required to be zero.
1235 These are (z must be zero, y may be anything):
43e65147
L		 1236 0000y
1237 0001y
8ebac3aa 1238 001zy
43e65147
L		 1239 0100y
1240 0101y
8ebac3aa
AM		 1241 011zy
1242 1z00y
1243 1z01y
1244 1z1zz
1245 */
1246 if ((value & 0x14) == 0)
1247 return 1;
1248 else if ((value & 0x14) == 0x4)
1249 return (value & 0x2) == 0;
1250 else if ((value & 0x14) == 0x10)
1251 return (value & 0x8) == 0;
1252 else
1253 return value == 0x14;
1254}
ba4e851b 1255
8ebac3aa
AM		 1256static inline int
1257valid_bo_post_v2 (long value)
1258{
ba4e851b
AM		 1259 /* Certain encodings have bits that are required to be zero.
1260 These are (z must be zero, a & t may be anything):
1261 0000z
1262 0001z
8ebac3aa 1263 001at
ba4e851b
AM		 1264 0100z
1265 0101z
ba4e851b
AM		 1266 011at
1267 1a00t
1268 1a01t
1269 1z1zz
1270 */
1271 if ((value & 0x14) == 0)
1272 return (value & 0x1) == 0;
1273 else if ((value & 0x14) == 0x14)
1274 return value == 0x14;
802a735e 1275 else
ba4e851b 1276 return 1;
252b5132
RH		 1277}
1278
8ebac3aa
AM		 1279/* Check for legal values of a BO field. */
1280
1281static int
1282valid_bo (long value, ppc_cpu_t dialect, int extract)
1283{
1284 int valid_y = valid_bo_pre_v2 (value);
1285 int valid_at = valid_bo_post_v2 (value);
1286
1287 /* When disassembling with -Many, accept either encoding on the
1288 second pass through opcodes. */
1289 if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY)
1290 return valid_y || valid_at;
1291 if ((dialect & ISA_V2) == 0)
1292 return valid_y;
1293 else
1294 return valid_at;
1295}
1296
252b5132
RH		 1297/* The BO field in a B form instruction. Warn about attempts to set
1298 the field to an illegal value. */
1299
1300static unsigned long
2fbfdc41
AM		 1301insert_bo (unsigned long insn,
1302 long value,
fa452fa6 1303 ppc_cpu_t dialect,
2fbfdc41 1304 const char **errmsg)
252b5132 1305{
ba4e851b 1306 if (!valid_bo (value, dialect, 0))
252b5132 1307 *errmsg = _("invalid conditional option");
989993d8
JB		 1308 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1309 *errmsg = _("invalid counter access");
252b5132
RH		 1310 return insn | ((value & 0x1f) << 21);
1311}
1312
1313static long
2fbfdc41 1314extract_bo (unsigned long insn,
fa452fa6 1315 ppc_cpu_t dialect,
2fbfdc41 1316 int *invalid)
252b5132
RH		 1317{
1318 long value;
1319
1320 value = (insn >> 21) & 0x1f;
ba4e851b 1321 if (!valid_bo (value, dialect, 1))
252b5132
RH		 1322 *invalid = 1;
1323 return value;
1324}
1325
1326/* The BO field in a B form instruction when the + or - modifier is
1327 used. This is like the BO field, but it must be even. When
1328 extracting it, we force it to be even. */
1329
1330static unsigned long
2fbfdc41
AM		 1331insert_boe (unsigned long insn,
1332 long value,
fa452fa6 1333 ppc_cpu_t dialect,
2fbfdc41 1334 const char **errmsg)
252b5132 1335{
ba4e851b 1336 if (!valid_bo (value, dialect, 0))
8427c424 1337 *errmsg = _("invalid conditional option");
989993d8
JB		 1338 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1339 *errmsg = _("invalid counter access");
8427c424
AM		 1340 else if ((value & 1) != 0)
1341 *errmsg = _("attempt to set y bit when using + or - modifier");
1342
252b5132
RH		 1343 return insn | ((value & 0x1f) << 21);
1344}
1345
1346static long
2fbfdc41 1347extract_boe (unsigned long insn,
fa452fa6 1348 ppc_cpu_t dialect,
2fbfdc41 1349 int *invalid)
252b5132
RH		 1350{
1351 long value;
1352
1353 value = (insn >> 21) & 0x1f;
ba4e851b 1354 if (!valid_bo (value, dialect, 1))
252b5132
RH		 1355 *invalid = 1;
1356 return value & 0x1e;
1357}
1358
a680de9a
PB		 1359/* The DCMX field in a X form instruction when the field is split
1360 into separate DC, DM and DX fields. */
1361
1362static unsigned long
1363insert_dcmxs (unsigned long insn,
1364 long value,
1365 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1366 const char **errmsg ATTRIBUTE_UNUSED)
1367{
1368 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3) | (value & 0x40);
1369}
1370
1371static long
1372extract_dcmxs (unsigned long insn,
1373 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1374 int *invalid ATTRIBUTE_UNUSED)
1375{
1376 return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1377}
1378
1379/* The D field in a DX form instruction when the field is split
1380 into separate D0, D1 and D2 fields. */
1381
1382static unsigned long
1383insert_dxd (unsigned long insn,
1384 long value,
1385 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1386 const char **errmsg ATTRIBUTE_UNUSED)
1387{
1388 return insn | (value & 0xffc1) | ((value & 0x3e) << 15);
1389}
1390
1391static long
1392extract_dxd (unsigned long insn,
1393 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1394 int *invalid ATTRIBUTE_UNUSED)
1395{
1396 unsigned long dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e);
1397 return (dxd ^ 0x8000) - 0x8000;
1398}
1399
1400static unsigned long
1401insert_dxdn (unsigned long insn,
1402 long value,
1403 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1404 const char **errmsg ATTRIBUTE_UNUSED)
1405{
1406 return insert_dxd (insn, -value, dialect, errmsg);
1407}
1408
1409static long
1410extract_dxdn (unsigned long insn,
1411 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1412 int *invalid ATTRIBUTE_UNUSED)
1413{
1414 return -extract_dxd (insn, dialect, invalid);
1415}
1416
2fbfdc41
AM		 1417/* FXM mask in mfcr and mtcrf instructions. */
1418
1419static unsigned long
1420insert_fxm (unsigned long insn,
1421 long value,
fa452fa6 1422 ppc_cpu_t dialect,
2fbfdc41 1423 const char **errmsg)
c168870a 1424{
98e69875
AM		 1425 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1426 one bit of the mask field is set. */
1427 if ((insn & (1 << 20)) != 0)
1428 {
1429 if (value == 0 || (value & -value) != value)
1430 {
1431 *errmsg = _("invalid mask field");
1432 value = 0;
1433 }
1434 }
1435
c168870a 1436 /* If only one bit of the FXM field is set, we can use the new form
661bd698 1437 of the instruction, which is faster. Unlike the Power4 branch hint
a30e9cc4
AM		 1438 encoding, this is not backward compatible. Do not generate the
1439 new form unless -mpower4 has been given, or -many and the two
1440 operand form of mfcr was used. */
11a0cf2e
PB		 1441 else if (value > 0
1442 && (value & -value) == value
a30e9cc4
AM		 1443 && ((dialect & PPC_OPCODE_POWER4) != 0
1444 || ((dialect & PPC_OPCODE_ANY) != 0
1445 && (insn & (0x3ff << 1)) == 19 << 1)))
c168870a
AM		 1446 insn |= 1 << 20;
1447
1448 /* Any other value on mfcr is an error. */
1449 else if ((insn & (0x3ff << 1)) == 19 << 1)
1450 {
11a0cf2e
PB		 1451 /* A value of -1 means we used the one operand form of
1452 mfcr which is valid. */
1453 if (value != -1)
b817670b 1454 *errmsg = _("invalid mfcr mask");
c168870a
AM		 1455 value = 0;
1456 }
1457
1458 return insn | ((value & 0xff) << 12);
1459}
1460
2fbfdc41
AM		 1461static long
1462extract_fxm (unsigned long insn,
fa452fa6 1463 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1464 int *invalid)
c168870a
AM		 1465{
1466 long mask = (insn >> 12) & 0xff;
1467
1468 /* Is this a Power4 insn? */
1469 if ((insn & (1 << 20)) != 0)
1470 {
98e69875
AM		 1471 /* Exactly one bit of MASK should be set. */
1472 if (mask == 0 || (mask & -mask) != mask)
8427c424 1473 *invalid = 1;
c168870a
AM		 1474 }
1475
1476 /* Check that non-power4 form of mfcr has a zero MASK. */
1477 else if ((insn & (0x3ff << 1)) == 19 << 1)
1478 {
8427c424 1479 if (mask != 0)
c168870a 1480 *invalid = 1;
11a0cf2e
PB		 1481 else
1482 mask = -1;
c168870a
AM		 1483 }
1484
1485 return mask;
1486}
1487
b9c361e0
JL		 1488static unsigned long
1489insert_li20 (unsigned long insn,
1490 long value,
1491 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1492 const char **errmsg ATTRIBUTE_UNUSED)
1493{
1494 return insn | ((value & 0xf0000) >> 5) | ((value & 0x0f800) << 5) | (value & 0x7ff);
1495}
1496
1497static long
1498extract_li20 (unsigned long insn,
1499 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1500 int *invalid ATTRIBUTE_UNUSED)
1501{
1502 long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
1503
1504 return ext
1505 | (((insn >> 11) & 0xf) << 16)
1506 | (((insn >> 17) & 0xf) << 12)
1507 | (((insn >> 16) & 0x1) << 11)
1508 | (insn & 0x7ff);
1509}
1510
7b934113
PB		 1511/* The 2-bit L field in a SYNC or WC field in a WAIT instruction.
1512 For SYNC, some L values are reserved:
1513 * Value 3 is reserved on newer server cpus.
1514 * Values 2 and 3 are reserved on all other cpus. */
aea77599
AM		 1515
1516static unsigned long
1517insert_ls (unsigned long insn,
1518 long value,
7b934113
PB		 1519 ppc_cpu_t dialect,
1520 const char **errmsg)
1521{
1522 /* For SYNC, some L values are illegal. */
1523 if (((insn >> 1) & 0x3ff) == 598)
1524 {
1525 long max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1;
1526 if (value > max_lvalue)
1527 {
1528 *errmsg = _("illegal L operand value");
1529 return insn;
1530 }
1531 }
1532
1533 return insn | ((value & 0x3) << 21);
1534}
1535
1536/* The 4-bit E field in a sync instruction that accepts 2 operands.
1537 If ESYNC is non-zero, then the L field must be either 0 or 1 and
1538 the complement of ESYNC-bit2. */
1539
1540static unsigned long
1541insert_esync (unsigned long insn,
1542 long value,
a680de9a 1543 ppc_cpu_t dialect,
7b934113 1544 const char **errmsg)
aea77599 1545{
a680de9a 1546 unsigned long ls = (insn >> 21) & 0x03;
aea77599 1547
aea77599
AM		 1548 if (value == 0)
1549 {
a680de9a
PB		 1550 if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1)
1551 || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2))
1552 *errmsg = _("illegal L operand value");
aea77599
AM		 1553 return insn;
1554 }
7b934113
PB		 1555
1556 if ((ls & ~0x1)
1557 || (((value >> 1) & 0x1) ^ ls) == 0)
1558 *errmsg = _("incompatible L operand value");
1559
1560 return insn | ((value & 0xf) << 16);
aea77599
AM		 1561}
1562
252b5132
RH		 1563/* The MB and ME fields in an M form instruction expressed as a single
1564 operand which is itself a bitmask. The extraction function always
1565 marks it as invalid, since we never want to recognize an
1566 instruction which uses a field of this type. */
1567
1568static unsigned long
2fbfdc41
AM		 1569insert_mbe (unsigned long insn,
1570 long value,
fa452fa6 1571 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1572 const char **errmsg)
252b5132
RH		 1573{
1574 unsigned long uval, mask;
1575 int mb, me, mx, count, last;
1576
1577 uval = value;
1578
1579 if (uval == 0)
1580 {
8427c424 1581 *errmsg = _("illegal bitmask");
252b5132
RH		 1582 return insn;
1583 }
1584
1585 mb = 0;
1586 me = 32;
1587 if ((uval & 1) != 0)
1588 last = 1;
1589 else
1590 last = 0;
1591 count = 0;
1592
1593 /* mb: location of last 0->1 transition */
1594 /* me: location of last 1->0 transition */
1595 /* count: # transitions */
1596
0deb7ac5 1597 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
252b5132
RH		 1598 {
1599 if ((uval & mask) && !last)
1600 {
1601 ++count;
1602 mb = mx;
1603 last = 1;
1604 }
1605 else if (!(uval & mask) && last)
1606 {
1607 ++count;
1608 me = mx;
1609 last = 0;
1610 }
1611 }
1612 if (me == 0)
1613 me = 32;
1614
1615 if (count != 2 && (count != 0 || ! last))
8427c424 1616 *errmsg = _("illegal bitmask");
252b5132
RH		 1617
1618 return insn | (mb << 6) | ((me - 1) << 1);
1619}
1620
1621static long
2fbfdc41 1622extract_mbe (unsigned long insn,
fa452fa6 1623 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1624 int *invalid)
252b5132
RH		 1625{
1626 long ret;
1627 int mb, me;
1628 int i;
1629
8427c424 1630 *invalid = 1;
252b5132
RH		 1631
1632 mb = (insn >> 6) & 0x1f;
1633 me = (insn >> 1) & 0x1f;
1634 if (mb < me + 1)
1635 {
1636 ret = 0;
1637 for (i = mb; i <= me; i++)
0deb7ac5 1638 ret |= 1L << (31 - i);
252b5132
RH		 1639 }
1640 else if (mb == me + 1)
8427c424 1641 ret = ~0;
252b5132
RH		 1642 else /* (mb > me + 1) */
1643 {
2fbfdc41 1644 ret = ~0;
252b5132 1645 for (i = me + 1; i < mb; i++)
0deb7ac5 1646 ret &= ~(1L << (31 - i));
252b5132
RH		 1647 }
1648 return ret;
1649}
1650
1651/* The MB or ME field in an MD or MDS form instruction. The high bit
1652 is wrapped to the low end. */
1653
252b5132 1654static unsigned long
2fbfdc41
AM		 1655insert_mb6 (unsigned long insn,
1656 long value,
fa452fa6 1657 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1658 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1659{
1660 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1661}
1662
252b5132 1663static long
2fbfdc41 1664extract_mb6 (unsigned long insn,
fa452fa6 1665 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1666 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1667{
1668 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1669}
1670
1671/* The NB field in an X form instruction. The value 32 is stored as
1672 0. */
1673
252b5132 1674static long
2fbfdc41 1675extract_nb (unsigned long insn,
fa452fa6 1676 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1677 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1678{
1679 long ret;
1680
1681 ret = (insn >> 11) & 0x1f;
1682 if (ret == 0)
1683 ret = 32;
1684 return ret;
1685}
1686
989993d8
JB		 1687/* The NB field in an lswi instruction, which has special value
1688 restrictions. The value 32 is stored as 0. */
1689
1690static unsigned long
1691insert_nbi (unsigned long insn,
1692 long value,
1693 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1694 const char **errmsg ATTRIBUTE_UNUSED)
1695{
1696 long rtvalue = (insn & RT_MASK) >> 21;
1697 long ravalue = (insn & RA_MASK) >> 16;
1698
1699 if (value == 0)
1700 value = 32;
1701 if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32
1702 : ravalue))
1703 *errmsg = _("address register in load range");
1704 return insn | ((value & 0x1f) << 11);
1705}
1706
252b5132
RH		 1707/* The NSI field in a D form instruction. This is the same as the SI
1708 field, only negated. The extraction function always marks it as
1709 invalid, since we never want to recognize an instruction which uses
1710 a field of this type. */
1711
252b5132 1712static unsigned long
2fbfdc41
AM		 1713insert_nsi (unsigned long insn,
1714 long value,
fa452fa6 1715 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1716 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1717{
2fbfdc41 1718 return insn | (-value & 0xffff);
252b5132
RH		 1719}
1720
1721static long
2fbfdc41 1722extract_nsi (unsigned long insn,
fa452fa6 1723 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1724 int *invalid)
252b5132 1725{
8427c424 1726 *invalid = 1;
2fbfdc41 1727 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
252b5132
RH		 1728}
1729
1730/* The RA field in a D or X form instruction which is an updating
1731 load, which means that the RA field may not be zero and may not
1732 equal the RT field. */
1733
1734static unsigned long
2fbfdc41
AM		 1735insert_ral (unsigned long insn,
1736 long value,
fa452fa6 1737 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1738 const char **errmsg)
252b5132
RH		 1739{
1740 if (value == 0
1741 || (unsigned long) value == ((insn >> 21) & 0x1f))
1742 *errmsg = "invalid register operand when updating";
1743 return insn | ((value & 0x1f) << 16);
1744}
1745
1746/* The RA field in an lmw instruction, which has special value
1747 restrictions. */
1748
1749static unsigned long
2fbfdc41
AM		 1750insert_ram (unsigned long insn,
1751 long value,
fa452fa6 1752 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1753 const char **errmsg)
252b5132
RH		 1754{
1755 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1756 *errmsg = _("index register in load range");
1757 return insn | ((value & 0x1f) << 16);
1758}
1759
989993d8 1760/* The RA field in the DQ form lq or an lswx instruction, which have special
8427c424 1761 value restrictions. */
adadcc0c 1762
adadcc0c 1763static unsigned long
2fbfdc41
AM		 1764insert_raq (unsigned long insn,
1765 long value,
fa452fa6 1766 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1767 const char **errmsg)
adadcc0c
AM		 1768{
1769 long rtvalue = (insn & RT_MASK) >> 21;
1770
8427c424 1771 if (value == rtvalue)
adadcc0c
AM		 1772 *errmsg = _("source and target register operands must be different");
1773 return insn | ((value & 0x1f) << 16);
1774}
1775
252b5132
RH		 1776/* The RA field in a D or X form instruction which is an updating
1777 store or an updating floating point load, which means that the RA
1778 field may not be zero. */
1779
1780static unsigned long
2fbfdc41
AM		 1781insert_ras (unsigned long insn,
1782 long value,
fa452fa6 1783 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1784 const char **errmsg)
252b5132
RH		 1785{
1786 if (value == 0)
1787 *errmsg = _("invalid register operand when updating");
1788 return insn | ((value & 0x1f) << 16);
1789}
1790
1791/* The RB field in an X form instruction when it must be the same as
1792 the RS field in the instruction. This is used for extended
1793 mnemonics like mr. This operand is marked FAKE. The insertion
1794 function just copies the BT field into the BA field, and the
1795 extraction function just checks that the fields are the same. */
1796
252b5132 1797static unsigned long
2fbfdc41
AM		 1798insert_rbs (unsigned long insn,
1799 long value ATTRIBUTE_UNUSED,
fa452fa6 1800 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1801 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1802{
1803 return insn | (((insn >> 21) & 0x1f) << 11);
1804}
1805
1806static long
2fbfdc41 1807extract_rbs (unsigned long insn,
fa452fa6 1808 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1809 int *invalid)
252b5132 1810{
8427c424 1811 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 1812 *invalid = 1;
1813 return 0;
1814}
1815
989993d8
JB		 1816/* The RB field in an lswx instruction, which has special value
1817 restrictions. */
1818
1819static unsigned long
1820insert_rbx (unsigned long insn,
1821 long value,
1822 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1823 const char **errmsg)
1824{
1825 long rtvalue = (insn & RT_MASK) >> 21;
1826
1827 if (value == rtvalue)
1828 *errmsg = _("source and target register operands must be different");
1829 return insn | ((value & 0x1f) << 11);
1830}
1831
b9c361e0
JL		 1832/* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1833static unsigned long
1834insert_sci8 (unsigned long insn,
1835 long value,
1836 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1837 const char **errmsg)
1838{
943d398f
AM		 1839 unsigned int fill_scale = 0;
1840 unsigned long ui8 = value;
b9c361e0 1841
943d398f
AM		 1842 if ((ui8 & 0xffffff00) == 0)
1843 ;
1844 else if ((ui8 & 0xffffff00) == 0xffffff00)
1845 fill_scale = 0x400;
1846 else if ((ui8 & 0xffff00ff) == 0)
b9c361e0 1847 {
943d398f
AM		 1848 fill_scale = 1 << 8;
1849 ui8 >>= 8;
b9c361e0 1850 }
943d398f 1851 else if ((ui8 & 0xffff00ff) == 0xffff00ff)
b9c361e0 1852 {
943d398f
AM		 1853 fill_scale = 0x400 | (1 << 8);
1854 ui8 >>= 8;
b9c361e0 1855 }
943d398f 1856 else if ((ui8 & 0xff00ffff) == 0)
b9c361e0 1857 {
943d398f
AM		 1858 fill_scale = 2 << 8;
1859 ui8 >>= 16;
b9c361e0 1860 }
943d398f 1861 else if ((ui8 & 0xff00ffff) == 0xff00ffff)
b9c361e0 1862 {
943d398f
AM		 1863 fill_scale = 0x400 | (2 << 8);
1864 ui8 >>= 16;
b9c361e0 1865 }
943d398f 1866 else if ((ui8 & 0x00ffffff) == 0)
b9c361e0 1867 {
943d398f
AM		 1868 fill_scale = 3 << 8;
1869 ui8 >>= 24;
b9c361e0 1870 }
943d398f 1871 else if ((ui8 & 0x00ffffff) == 0x00ffffff)
b9c361e0 1872 {
943d398f
AM		 1873 fill_scale = 0x400 | (3 << 8);
1874 ui8 >>= 24;
b9c361e0 1875 }
943d398f 1876 else
b9c361e0 1877 {
943d398f
AM		 1878 *errmsg = _("illegal immediate value");
1879 ui8 = 0;
b9c361e0 1880 }
b9c361e0 1881
943d398f 1882 return insn | fill_scale | (ui8 & 0xff);
b9c361e0
JL		 1883}
1884
1885static long
1886extract_sci8 (unsigned long insn,
1887 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1888 int *invalid ATTRIBUTE_UNUSED)
1889{
943d398f
AM		 1890 int fill = insn & 0x400;
1891 int scale_factor = (insn & 0x300) >> 5;
1892 long value = (insn & 0xff) << scale_factor;
1893
1894 if (fill != 0)
1895 value |= ~((long) 0xff << scale_factor);
1896 return value;
b9c361e0
JL		 1897}
1898
1899static unsigned long
1900insert_sci8n (unsigned long insn,
1901 long value,
943d398f 1902 ppc_cpu_t dialect,
b9c361e0
JL		 1903 const char **errmsg)
1904{
943d398f 1905 return insert_sci8 (insn, -value, dialect, errmsg);
b9c361e0
JL		 1906}
1907
1908static long
1909extract_sci8n (unsigned long insn,
943d398f
AM		 1910 ppc_cpu_t dialect,
1911 int *invalid)
b9c361e0 1912{
943d398f 1913 return -extract_sci8 (insn, dialect, invalid);
b9c361e0
JL		 1914}
1915
1916static unsigned long
1917insert_sd4h (unsigned long insn,
1918 long value,
1919 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1920 const char **errmsg ATTRIBUTE_UNUSED)
1921{
1922 return insn | ((value & 0x1e) << 7);
1923}
1924
1925static long
1926extract_sd4h (unsigned long insn,
1927 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1928 int *invalid ATTRIBUTE_UNUSED)
1929{
1930 return ((insn >> 8) & 0xf) << 1;
1931}
1932
1933static unsigned long
1934insert_sd4w (unsigned long insn,
1935 long value,
1936 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1937 const char **errmsg ATTRIBUTE_UNUSED)
1938{
1939 return insn | ((value & 0x3c) << 6);
1940}
1941
1942static long
1943extract_sd4w (unsigned long insn,
1944 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1945 int *invalid ATTRIBUTE_UNUSED)
1946{
1947 return ((insn >> 8) & 0xf) << 2;
1948}
1949
1950static unsigned long
1951insert_oimm (unsigned long insn,
1952 long value,
1953 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1954 const char **errmsg ATTRIBUTE_UNUSED)
1955{
1956 return insn | (((value - 1) & 0x1f) << 4);
1957}
1958
1959static long
1960extract_oimm (unsigned long insn,
1961 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1962 int *invalid ATTRIBUTE_UNUSED)
1963{
1964 return ((insn >> 4) & 0x1f) + 1;
1965}
1966
252b5132
RH		 1967/* The SH field in an MD form instruction. This is split. */
1968
252b5132 1969static unsigned long
2fbfdc41
AM		 1970insert_sh6 (unsigned long insn,
1971 long value,
fa452fa6 1972 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1973 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1974{
6fd3a02d
PB		 1975 /* SH6 operand in the rldixor instructions. */
1976 if (PPC_OP (insn) == 4)
1977 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 5);
1978 else
1979 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
252b5132
RH		 1980}
1981
252b5132 1982static long
2fbfdc41 1983extract_sh6 (unsigned long insn,
fa452fa6 1984 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1985 int *invalid ATTRIBUTE_UNUSED)
252b5132 1986{
6fd3a02d
PB		 1987 /* SH6 operand in the rldixor instructions. */
1988 if (PPC_OP (insn) == 4)
1989 return ((insn >> 6) & 0x1f) | ((insn << 5) & 0x20);
1990 else
1991 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
252b5132
RH		 1992}
1993
1994/* The SPR field in an XFX form instruction. This is flipped--the
1995 lower 5 bits are stored in the upper 5 and vice- versa. */
1996
1997static unsigned long
2fbfdc41
AM		 1998insert_spr (unsigned long insn,
1999 long value,
fa452fa6 2000 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 2001 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 2002{
2003 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
2004}
2005
2006static long
2fbfdc41 2007extract_spr (unsigned long insn,
fa452fa6 2008 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 2009 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 2010{
2011 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
2012}
2013
da99ee72 2014/* Some dialects have 8 SPRG registers instead of the standard 4. */
14b57c7c 2015#define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405)
da99ee72
AM		 2016
2017static unsigned long
2018insert_sprg (unsigned long insn,
2019 long value,
fa452fa6 2020 ppc_cpu_t dialect,
da99ee72
AM		 2021 const char **errmsg)
2022{
da99ee72 2023 if (value > 7
98c76446 2024 || (value > 3 && (dialect & ALLOW8_SPRG) == 0))
da99ee72
AM		 2025 *errmsg = _("invalid sprg number");
2026
2027 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
2028 user mode. Anything else must use spr 272..279. */
2029 if (value <= 3 || (insn & 0x100) != 0)
2030 value |= 0x10;
2031
2032 return insn | ((value & 0x17) << 16);
2033}
2034
2035static long
2036extract_sprg (unsigned long insn,
fa452fa6 2037 ppc_cpu_t dialect,
da99ee72
AM		 2038 int *invalid)
2039{
2040 unsigned long val = (insn >> 16) & 0x1f;
2041
2042 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
98c76446
AM		 2043 If not BOOKE, 405 or VLE, then both use only 272..275. */
2044 if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0)
e1c93c69
AM		 2045 || (val - 0x10 > 7 && (insn & 0x100) != 0)
2046 || val <= 3
2047 || (val & 8) != 0)
da99ee72
AM		 2048 *invalid = 1;
2049 return val & 7;
2050}
2051
252b5132 2052/* The TBR field in an XFX instruction. This is just like SPR, but it
11a0cf2e 2053 is optional. */
252b5132 2054
252b5132 2055static unsigned long
2fbfdc41
AM		 2056insert_tbr (unsigned long insn,
2057 long value,
fa452fa6 2058 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
8514e4db 2059 const char **errmsg)
252b5132 2060{
8514e4db
AM		 2061 if (value != 268 && value != 269)
2062 *errmsg = _("invalid tbr number");
252b5132
RH		 2063 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
2064}
2065
2066static long
2fbfdc41 2067extract_tbr (unsigned long insn,
fa452fa6 2068 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
8514e4db 2069 int *invalid)
252b5132
RH		 2070{
2071 long ret;
2072
2073 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
8514e4db
AM		 2074 if (ret != 268 && ret != 269)
2075 *invalid = 1;
252b5132
RH		 2076 return ret;
2077}
9b4e5766
PB		 2078
2079/* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
2080
2081static unsigned long
2082insert_xt6 (unsigned long insn,
2083 long value,
2084 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2085 const char **errmsg ATTRIBUTE_UNUSED)
2086{
2087 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
2088}
2089
2090static long
2091extract_xt6 (unsigned long insn,
2092 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2093 int *invalid ATTRIBUTE_UNUSED)
2094{
2095 return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
2096}
2097
a680de9a
PB		 2098/* The XT and XS fields in an DQ form VSX instruction. This is split. */
2099static unsigned long
2100insert_xtq6 (unsigned long insn,
2101 long value,
2102 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2103 const char **errmsg ATTRIBUTE_UNUSED)
2104{
2105 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2);
2106}
2107
2108static long
2109extract_xtq6 (unsigned long insn,
2110 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2111 int *invalid ATTRIBUTE_UNUSED)
2112{
2113 return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f);
2114}
2115
9b4e5766
PB		 2116/* The XA field in an XX3 form instruction. This is split. */
2117
2118static unsigned long
2119insert_xa6 (unsigned long insn,
2120 long value,
2121 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2122 const char **errmsg ATTRIBUTE_UNUSED)
2123{
2124 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
2125}
2126
2127static long
2128extract_xa6 (unsigned long insn,
2129 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2130 int *invalid ATTRIBUTE_UNUSED)
2131{
2132 return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
2133}
2134
2135/* The XB field in an XX3 form instruction. This is split. */
2136
2137static unsigned long
2138insert_xb6 (unsigned long insn,
2139 long value,
2140 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2141 const char **errmsg ATTRIBUTE_UNUSED)
2142{
2143 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
2144}
2145
2146static long
2147extract_xb6 (unsigned long insn,
2148 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2149 int *invalid ATTRIBUTE_UNUSED)
2150{
2151 return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
2152}
2153
2154/* The XB field in an XX3 form instruction when it must be the same as
2155 the XA field in the instruction. This is used for extended
2156 mnemonics like xvmovdp. This operand is marked FAKE. The insertion
2157 function just copies the XA field into the XB field, and the
2158 extraction function just checks that the fields are the same. */
2159
2160static unsigned long
2161insert_xb6s (unsigned long insn,
2162 long value ATTRIBUTE_UNUSED,
2163 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2164 const char **errmsg ATTRIBUTE_UNUSED)
2165{
2166 return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
2167}
2168
2169static long
2170extract_xb6s (unsigned long insn,
2171 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2172 int *invalid)
2173{
2174 if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
2175 || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
2176 *invalid = 1;
2177 return 0;
2178}
066be9f7
PB		 2179
2180/* The XC field in an XX4 form instruction. This is split. */
2181
2182static unsigned long
2183insert_xc6 (unsigned long insn,
2184 long value,
2185 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2186 const char **errmsg ATTRIBUTE_UNUSED)
2187{
2188 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
2189}
2190
2191static long
2192extract_xc6 (unsigned long insn,
2193 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2194 int *invalid ATTRIBUTE_UNUSED)
2195{
2196 return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
2197}
2198
2199static unsigned long
2200insert_dm (unsigned long insn,
2201 long value,
2202 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2203 const char **errmsg)
2204{
2205 if (value != 0 && value != 1)
2206 *errmsg = _("invalid constant");
2207 return insn | (((value) ? 3 : 0) << 8);
2208}
2209
2210static long
2211extract_dm (unsigned long insn,
2212 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2213 int *invalid)
2214{
2215 long value;
2216
2217 value = (insn >> 8) & 3;
2218 if (value != 0 && value != 3)
2219 *invalid = 1;
2220 return (value) ? 1 : 0;
2221}
7b934113 2222
b9c361e0
JL		 2223/* The VLESIMM field in an I16A form instruction. This is split. */
2224
2225static unsigned long
2226insert_vlesi (unsigned long insn,
2227 long value,
2228 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2229 const char **errmsg ATTRIBUTE_UNUSED)
2230{
2231 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2232}
2233
2234static long
2235extract_vlesi (unsigned long insn,
2236 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2237 int *invalid ATTRIBUTE_UNUSED)
2238{
b9c361e0 2239 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
9f0682fe 2240 value = (value ^ 0x8000) - 0x8000;
b9c361e0
JL		 2241 return value;
2242}
2243
2244static unsigned long
2245insert_vlensi (unsigned long insn,
2246 long value,
2247 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2248 const char **errmsg ATTRIBUTE_UNUSED)
2249{
2250 value = -value;
2251 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2252}
2253static long
2254extract_vlensi (unsigned long insn,
2255 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2256 int *invalid ATTRIBUTE_UNUSED)
2257{
2258 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
9f0682fe
AM		 2259 value = (value ^ 0x8000) - 0x8000;
2260 /* Don't use for disassembly. */
b9c361e0
JL		 2261 *invalid = 1;
2262 return -value;
2263}
2264
2265/* The VLEUIMM field in an I16A form instruction. This is split. */
2266
2267static unsigned long
2268insert_vleui (unsigned long insn,
2269 long value,
2270 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2271 const char **errmsg ATTRIBUTE_UNUSED)
2272{
2273 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2274}
2275
2276static long
2277extract_vleui (unsigned long insn,
2278 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2279 int *invalid ATTRIBUTE_UNUSED)
2280{
2281 return ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2282}
2283
2284/* The VLEUIMML field in an I16L form instruction. This is split. */
2285
2286static unsigned long
2287insert_vleil (unsigned long insn,
2288 long value,
2289 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2290 const char **errmsg ATTRIBUTE_UNUSED)
2291{
2292 return insn | ((value & 0xf800) << 5) | (value & 0x7ff);
2293}
2294
2295static long
2296extract_vleil (unsigned long insn,
2297 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2298 int *invalid ATTRIBUTE_UNUSED)
2299{
2300 return ((insn >> 5) & 0xf800) | (insn & 0x7ff);
2301}
2302
252b5132
RH		 2303\f
2304/* Macros used to form opcodes. */
2305
2306/* The main opcode. */
2307#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
2308#define OP_MASK OP (0x3f)
2309
2310/* The main opcode combined with a trap code in the TO field of a D
2311 form instruction. Used for extended mnemonics for the trap
2312 instructions. */
2313#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
2314#define OPTO_MASK (OP_MASK | TO_MASK)
2315
2316/* The main opcode combined with a comparison size bit in the L field
2317 of a D form or X form instruction. Used for extended mnemonics for
2318 the comparison instructions. */
2319#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
2320#define OPL_MASK OPL (0x3f,1)
2321
b9c361e0
JL		 2322/* The main opcode combined with an update code in D form instruction.
2323 Used for extended mnemonics for VLE memory instructions. */
2324#define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
2325#define OPVUP_MASK OPVUP (0x3f, 0xff)
2326
dfdaec14
AJ		 2327/* The main opcode combined with an update code and the RT fields specified in
2328 D form instruction. Used for VLE volatile context save/restore
2329 instructions. */
2330#define OPVUPRT(x,vup,rt) (OPVUP (x, vup) | ((((unsigned long)(rt)) & 0x1f) << 21))
2331#define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f)
2332
252b5132
RH		 2333/* An A form instruction. */
2334#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
2335#define A_MASK A (0x3f, 0x1f, 1)
2336
2337/* An A_MASK with the FRB field fixed. */
2338#define AFRB_MASK (A_MASK | FRB_MASK)
2339
2340/* An A_MASK with the FRC field fixed. */
2341#define AFRC_MASK (A_MASK | FRC_MASK)
2342
2343/* An A_MASK with the FRA and FRC fields fixed. */
2344#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
2345
702f0fb4
PB		 2346/* An AFRAFRC_MASK, but with L bit clear. */
2347#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
2348
252b5132
RH		 2349/* A B form instruction. */
2350#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
2351#define B_MASK B (0x3f, 1, 1)
2352
b9c361e0
JL		 2353/* A BD8 form instruction. This is a 16-bit instruction. */
2354#define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
2355#define BD8_MASK BD8 (0x3f, 1, 1)
2356
2357/* Another BD8 form instruction. This is a 16-bit instruction. */
2358#define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
2359#define BD8IO_MASK BD8IO (0x1f)
2360
2361/* A BD8 form instruction for simplified mnemonics. */
2362#define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2363/* A mask that excludes BO32 and BI32. */
2364#define EBD8IO1_MASK 0xf800
2365/* A mask that includes BO32 and excludes BI32. */
2366#define EBD8IO2_MASK 0xfc00
2367/* A mask that include BO32 AND BI32. */
2368#define EBD8IO3_MASK 0xff00
2369
2370/* A BD15 form instruction. */
2371#define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
2372#define BD15_MASK BD15 (0x3f, 0xf, 1)
2373
2374/* A BD15 form instruction for extended conditional branch mnemonics. */
2375#define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
2376#define EBD15_MASK 0xfff00001
2377
2378/* A BD15 form instruction for extended conditional branch mnemonics with BI. */
2379#define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
2380 | (((aa) & 0xf) << 22) \
2381 | (((bo) & 0x3) << 20) \
2382 | (((bi) & 0x3) << 16) \
2383 | ((lk) & 1)
2384#define EBD15BI_MASK 0xfff30001
2385
2386/* A BD24 form instruction. */
2387#define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
2388#define BD24_MASK BD24 (0x3f, 1, 1)
2389
252b5132
RH		 2390/* A B form instruction setting the BO field. */
2391#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2392#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
2393
2394/* A BBO_MASK with the y bit of the BO field removed. This permits
2395 matching a conditional branch regardless of the setting of the y
94efba12 2396 bit. Similarly for the 'at' bits used for power4 branch hints. */
de866fcc 2397#define Y_MASK (((unsigned long) 1) << 21)
802a735e
AM		 2398#define AT1_MASK (((unsigned long) 3) << 21)
2399#define AT2_MASK (((unsigned long) 9) << 21)
2400#define BBOY_MASK (BBO_MASK &~ Y_MASK)
2401#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
252b5132
RH		 2402
2403/* A B form instruction setting the BO field and the condition bits of
2404 the BI field. */
2405#define BBOCB(op, bo, cb, aa, lk) \
2406 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
2407#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
2408
2409/* A BBOCB_MASK with the y bit of the BO field removed. */
2410#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
802a735e
AM		 2411#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
2412#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
252b5132
RH		 2413
2414/* A BBOYCB_MASK in which the BI field is fixed. */
2415#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
802a735e 2416#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
252b5132 2417
b9c361e0
JL		 2418/* A VLE C form instruction. */
2419#define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
2420#define C_LK_MASK C_LK(0x7fff, 1)
2421#define C(x) ((((unsigned long)(x)) & 0xffff))
2422#define C_MASK C(0xffff)
2423
23976049
EZ		 2424/* An Context form instruction. */
2425#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
fdd12ef3 2426#define CTX_MASK CTX(0x3f, 0x7)
23976049
EZ		 2427
2428/* An User Context form instruction. */
2429#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
fdd12ef3 2430#define UCTX_MASK UCTX(0x3f, 0x1f)
23976049 2431
252b5132
RH		 2432/* The main opcode mask with the RA field clear. */
2433#define DRA_MASK (OP_MASK | RA_MASK)
2434
a680de9a
PB		 2435/* A DQ form VSX instruction. */
2436#define DQX(op, xop) (OP (op) | ((xop) & 0x7))
2437#define DQX_MASK DQX (0x3f, 7)
2438
252b5132
RH		 2439/* A DS form instruction. */
2440#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
2441#define DS_MASK DSO (0x3f, 3)
2442
a680de9a
PB		 2443/* An DX form instruction. */
2444#define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2445#define DX_MASK DX (0x3f, 0x1f)
2446
23976049
EZ		 2447/* An EVSEL form instruction. */
2448#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
2449#define EVSEL_MASK EVSEL(0x3f, 0xff)
2450
b9c361e0
JL		 2451/* An IA16 form instruction. */
2452#define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2453#define IA16_MASK IA16(0x3f, 0x1f)
2454
2455/* An I16A form instruction. */
2456#define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2457#define I16A_MASK I16A(0x3f, 0x1f)
2458
2459/* An I16L form instruction. */
2460#define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2461#define I16L_MASK I16L(0x3f, 0x1f)
2462
2463/* An IM7 form instruction. */
2464#define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
2465#define IM7_MASK IM7(0x1f)
2466
252b5132
RH		 2467/* An M form instruction. */
2468#define M(op, rc) (OP (op) | ((rc) & 1))
2469#define M_MASK M (0x3f, 1)
2470
b9c361e0
JL		 2471/* An LI20 form instruction. */
2472#define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
2473#define LI20_MASK LI20(0x3f, 0x1)
2474
252b5132
RH		 2475/* An M form instruction with the ME field specified. */
2476#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
2477
2478/* An M_MASK with the MB and ME fields fixed. */
2479#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2480
2481/* An M_MASK with the SH and ME fields fixed. */
2482#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
2483
2484/* An MD form instruction. */
2485#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
2486#define MD_MASK MD (0x3f, 0x7, 1)
2487
2488/* An MD_MASK with the MB field fixed. */
2489#define MDMB_MASK (MD_MASK | MB6_MASK)
2490
2491/* An MD_MASK with the SH field fixed. */
2492#define MDSH_MASK (MD_MASK | SH6_MASK)
2493
2494/* An MDS form instruction. */
2495#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
2496#define MDS_MASK MDS (0x3f, 0xf, 1)
2497
2498/* An MDS_MASK with the MB field fixed. */
2499#define MDSMB_MASK (MDS_MASK | MB6_MASK)
2500
2501/* An SC form instruction. */
2502#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
2503#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
2504
b9c361e0
JL		 2505/* An SCI8 form instruction. */
2506#define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
2507#define SCI8_MASK SCI8(0x3f, 0x1f)
2508
2509/* An SCI8 form instruction. */
2510#define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
2511#define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2512
2513/* An SD4 form instruction. This is a 16-bit instruction. */
43e65147 2514#define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
b9c361e0
JL		 2515#define SD4_MASK SD4(0xf)
2516
2517/* An SE_IM5 form instruction. This is a 16-bit instruction. */
2518#define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
2519#define SE_IM5_MASK SE_IM5(0x3f, 1)
2520
2521/* An SE_R form instruction. This is a 16-bit instruction. */
2522#define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
2523#define SE_R_MASK SE_R(0x3f, 0x3f)
2524
2525/* An SE_RR form instruction. This is a 16-bit instruction. */
2526#define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
2527#define SE_RR_MASK SE_RR(0x3f, 3)
2528
2529/* A VX form instruction. */
786e2c0f
C		 2530#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2531
112290ab 2532/* The mask for an VX form instruction. */
786e2c0f
C		 2533#define VX_MASK VX(0x3f, 0x7ff)
2534
fb048c26
PB		 2535/* A VX_MASK with the VA field fixed. */
2536#define VXVA_MASK (VX_MASK | (0x1f << 16))
2537
2538/* A VX_MASK with the VB field fixed. */
2539#define VXVB_MASK (VX_MASK | (0x1f << 11))
2540
2541/* A VX_MASK with the VA and VB fields fixed. */
2542#define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2543
2544/* A VX_MASK with the VD and VA fields fixed. */
2545#define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2546
2547/* A VX_MASK with a UIMM4 field. */
2548#define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
2549
2550/* A VX_MASK with a UIMM3 field. */
2551#define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2552
2553/* A VX_MASK with a UIMM2 field. */
2554#define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
2555
c0637f3a
PB		 2556/* A VX_MASK with a PS field. */
2557#define VXPS_MASK (VX_MASK & ~(0x1 << 9))
2558
a680de9a
PB		 2559/* A VX_MASK with the VA field fixed with a PS field. */
2560#define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9))
2561
b9c361e0 2562/* A VA form instruction. */
2613489e 2563#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
786e2c0f 2564
112290ab 2565/* The mask for an VA form instruction. */
2613489e 2566#define VXA_MASK VXA(0x3f, 0x3f)
786e2c0f 2567
382c72e9
PB		 2568/* A VXA_MASK with a SHB field. */
2569#define VXASHB_MASK (VXA_MASK | (1 << 10))
2570
b9c361e0 2571/* A VXR form instruction. */
786e2c0f
C		 2572#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
2573
112290ab 2574/* The mask for a VXR form instruction. */
786e2c0f
C		 2575#define VXR_MASK VXR(0x3f, 0x3ff, 1)
2576
a680de9a
PB		 2577/* A VX form instruction with a VA tertiary opcode. */
2578#define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16))
2579
6fd3a02d
PB		 2580#define VXASH(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2581#define VXASH_MASK VXASH (0x3f, 0x1f)
2582
252b5132
RH		 2583/* An X form instruction. */
2584#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2585
a680de9a
PB		 2586/* A X form instruction for Quad-Precision FP Instructions. */
2587#define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16))
2588
b9c361e0
JL		 2589/* An EX form instruction. */
2590#define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2591
2592/* The mask for an EX form instruction. */
2593#define EX_MASK EX (0x3f, 0x7ff)
2594
066be9f7
PB		 2595/* An XX2 form instruction. */
2596#define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
2597
a680de9a
PB		 2598/* A XX2 form instruction with the VA bits specified. */
2599#define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16))
2600
9b4e5766
PB		 2601/* An XX3 form instruction. */
2602#define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
2603
066be9f7
PB		 2604/* An XX3 form instruction with the RC bit specified. */
2605#define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
2606
2607/* An XX4 form instruction. */
2608#define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
9b4e5766 2609
702f0fb4
PB		 2610/* A Z form instruction. */
2611#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
2612
252b5132
RH		 2613/* An X form instruction with the RC bit specified. */
2614#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
2615
a680de9a
PB		 2616/* A X form instruction for Quad-Precision FP Instructions with RC bit. */
2617#define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1))
2618
6fd3a02d
PB		 2619/* An X form instruction with the RA bits specified as two ops. */
2620#define XMMF(op, xop, mop0, mop1) (X ((op), (xop)) | ((mop0) & 3) << 19 | ((mop1) & 7) << 16)
2621
702f0fb4
PB		 2622/* A Z form instruction with the RC bit specified. */
2623#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
2624
252b5132
RH		 2625/* The mask for an X form instruction. */
2626#define X_MASK XRC (0x3f, 0x3ff, 1)
2627
a680de9a
PB		 2628/* The mask for an X form instruction with the BF bits specified. */
2629#define XBF_MASK (X_MASK | (3 << 21))
2630
e0d602ec
BE		 2631/* An X form wait instruction with everything filled in except the WC field. */
2632#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2633
9b4e5766
PB		 2634/* The mask for an XX1 form instruction. */
2635#define XX1_MASK X (0x3f, 0x3ff)
2636
c0637f3a
PB		 2637/* An XX1_MASK with the RB field fixed. */
2638#define XX1RB_MASK (XX1_MASK | RB_MASK)
2639
066be9f7
PB		 2640/* The mask for an XX2 form instruction. */
2641#define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
2642
2643/* The mask for an XX2 form instruction with the UIM bits specified. */
2644#define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
2645
a680de9a
PB		 2646/* The mask for an XX2 form instruction with the 4 UIM bits specified. */
2647#define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20))
2648
066be9f7
PB		 2649/* The mask for an XX2 form instruction with the BF bits specified. */
2650#define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
2651
a680de9a
PB		 2652/* The mask for an XX2 form instruction with the BF and DCMX bits specified. */
2653#define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1)
2654
2655/* The mask for an XX2 form instruction with a split DCMX bits specified. */
2656#define XX2DCMXS_MASK XX2 (0x3f, 0x1ee)
2657
9b4e5766
PB		 2658/* The mask for an XX3 form instruction. */
2659#define XX3_MASK XX3 (0x3f, 0xff)
2660
066be9f7
PB		 2661/* The mask for an XX3 form instruction with the BF bits specified. */
2662#define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
2663
2664/* The mask for an XX3 form instruction with the DM or SHW bits specified. */
9b4e5766 2665#define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
066be9f7
PB		 2666#define XX3SHW_MASK XX3DM_MASK
2667
2668/* The mask for an XX4 form instruction. */
2669#define XX4_MASK XX4 (0x3f, 0x3)
2670
2671/* An X form wait instruction with everything filled in except the WC field. */
2672#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
9b4e5766 2673
6fd3a02d
PB		 2674/* The mask for an XMMF form instruction. */
2675#define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1))
2676
702f0fb4
PB		 2677/* The mask for a Z form instruction. */
2678#define Z_MASK ZRC (0x3f, 0x1ff, 1)
0bbdef92 2679#define Z2_MASK ZRC (0x3f, 0xff, 1)
702f0fb4 2680
a680de9a 2681/* An X_MASK with the RA/VA field fixed. */
252b5132 2682#define XRA_MASK (X_MASK | RA_MASK)
a680de9a 2683#define XVA_MASK XRA_MASK
252b5132 2684
a680de9a 2685/* An XRA_MASK with the A_L/W field clear. */
ea192fa3 2686#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
a680de9a 2687#define XRLA_MASK XWRA_MASK
ea192fa3 2688
252b5132
RH		 2689/* An X_MASK with the RB field fixed. */
2690#define XRB_MASK (X_MASK | RB_MASK)
2691
2692/* An X_MASK with the RT field fixed. */
2693#define XRT_MASK (X_MASK | RT_MASK)
2694
702f0fb4
PB		 2695/* An XRT_MASK mask with the L bits clear. */
2696#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
2697
252b5132
RH		 2698/* An X_MASK with the RA and RB fields fixed. */
2699#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
2700
a680de9a
PB		 2701/* An XBF_MASK with the RA and RB fields fixed. */
2702#define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK)
2703
112290ab 2704/* An XRARB_MASK, but with the L bit clear. */
5ae2e65e
AM		 2705#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
2706
a680de9a
PB		 2707/* An XRARB_MASK, but with the L bits in a darn instruction clear. */
2708#define XLRAND_MASK (XRARB_MASK & ~((unsigned long) 3 << 16))
2709
252b5132
RH		 2710/* An X_MASK with the RT and RA fields fixed. */
2711#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
2712
5817ffd1
PB		 2713/* An X_MASK with the RT and RB fields fixed. */
2714#define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
2715
98acc1c5
AM		 2716/* An XRTRA_MASK, but with L bit clear. */
2717#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
2718
5817ffd1
PB		 2719/* An X_MASK with the RT, RA and RB fields fixed. */
2720#define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
2721
2722/* An XRTRARB_MASK, but with L bit clear. */
2723#define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21))
2724
2725/* An XRTRARB_MASK, but with A bit clear. */
2726#define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25))
2727
2728/* An XRTRARB_MASK, but with BF bits clear. */
2729#define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23))
2730
f3806e43
BE		 2731/* An X form instruction with the L bit specified. */
2732#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
252b5132 2733
e0d602ec
BE		 2734/* An X form instruction with the L bits specified. */
2735#define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2736
5817ffd1
PB		 2737/* An X form instruction with the L bit and RC bit specified. */
2738#define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21))
2739
19a6653c
AM		 2740/* An X form instruction with RT fields specified */
2741#define XRT(op, xop, rt) (X ((op), (xop)) \
2742 | ((((unsigned long)(rt)) & 0x1f) << 21))
2743
2744/* An X form instruction with RT and RA fields specified */
2745#define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
2746 | ((((unsigned long)(rt)) & 0x1f) << 21) \
2747 | ((((unsigned long)(ra)) & 0x1f) << 16))
2748
252b5132
RH		 2749/* The mask for an X form comparison instruction. */
2750#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
2751
520ceea4
BE		 2752/* The mask for an X form comparison instruction with the L field
2753 fixed. */
2754#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
252b5132
RH		 2755
2756/* An X form trap instruction with the TO field specified. */
2757#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
2758#define XTO_MASK (X_MASK | TO_MASK)
2759
e0c21649
GK		 2760/* An X form tlb instruction with the SH field specified. */
2761#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
2762#define XTLB_MASK (X_MASK | SH_MASK)
2763
6ba045b1
AM		 2764/* An X form sync instruction. */
2765#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2766
2767/* An X form sync instruction with everything filled in except the LS field. */
2768#define XSYNC_MASK (0xff9fffff)
2769
aea77599
AM		 2770/* An X form sync instruction with everything filled in except the L and E fields. */
2771#define XSYNCLE_MASK (0xff90ffff)
2772
702f0fb4
PB		 2773/* An X_MASK, but with the EH bit clear. */
2774#define XEH_MASK (X_MASK & ~((unsigned long )1))
2775
f5c120c5
MG		 2776/* An X form AltiVec dss instruction. */
2777#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
2778#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
2779
252b5132
RH		 2780/* An XFL form instruction. */
2781#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
ea192fa3 2782#define XFL_MASK XFL (0x3f, 0x3ff, 1)
252b5132 2783
23976049 2784/* An X form isel instruction. */
de866fcc
AM		 2785#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2786#define XISEL_MASK XISEL(0x3f, 0x1f)
23976049 2787
252b5132
RH		 2788/* An XL form instruction with the LK field set to 0. */
2789#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2790
2791/* An XL form instruction which uses the LK field. */
2792#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
2793
2794/* The mask for an XL form instruction. */
2795#define XL_MASK XLLK (0x3f, 0x3ff, 1)
2796
c0637f3a
PB		 2797/* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
2798#define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
2799
252b5132
RH		 2800/* An XL form instruction which explicitly sets the BO field. */
2801#define XLO(op, bo, xop, lk) \
2802 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2803#define XLO_MASK (XL_MASK | BO_MASK)
2804
2805/* An XL form instruction which explicitly sets the y bit of the BO
2806 field. */
2807#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
2808#define XLYLK_MASK (XL_MASK | Y_MASK)
2809
2810/* An XL form instruction which sets the BO field and the condition
2811 bits of the BI field. */
2812#define XLOCB(op, bo, cb, xop, lk) \
2813 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
2814#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
2815
2816/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
2817#define XLBB_MASK (XL_MASK | BB_MASK)
2818#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
2819#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
2820
d0618d1c
AM		 2821/* A mask for branch instructions using the BH field. */
2822#define XLBH_MASK (XL_MASK | (0x1c << 11))
2823
252b5132
RH		 2824/* An XL_MASK with the BO and BB fields fixed. */
2825#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
2826
2827/* An XL_MASK with the BO, BI and BB fields fixed. */
2828#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
2829
e01d869a
AM		 2830/* An X form mbar instruction with MO field. */
2831#define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
2832
252b5132
RH		 2833/* An XO form instruction. */
2834#define XO(op, xop, oe, rc) \
2835 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
2836#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
2837
2838/* An XO_MASK with the RB field fixed. */
2839#define XORB_MASK (XO_MASK | RB_MASK)
2840
c3d65c1c
BE		 2841/* An XOPS form instruction for paired singles. */
2842#define XOPS(op, xop, rc) \
2843 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2844#define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
2845
2846
252b5132
RH		 2847/* An XS form instruction. */
2848#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
2849#define XS_MASK XS (0x3f, 0x1ff, 1)
2850
2851/* A mask for the FXM version of an XFX form instruction. */
98e69875 2852#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
252b5132
RH		 2853
2854/* An XFX form instruction with the FXM field filled in. */
98e69875
AM		 2855#define XFXM(op, xop, fxm, p4) \
2856 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
2857 | ((unsigned long)(p4) << 20))
252b5132
RH		 2858
2859/* An XFX form instruction with the SPR field filled in. */
2860#define XSPR(op, xop, spr) \
2861 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
2862#define XSPR_MASK (X_MASK | SPR_MASK)
2863
2864/* An XFX form instruction with the SPR field filled in except for the
2865 SPRBAT field. */
2866#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
2867
2868/* An XFX form instruction with the SPR field filled in except for the
2869 SPRG field. */
b84bf58a 2870#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
252b5132
RH		 2871
2872/* An X form instruction with everything filled in except the E field. */
2873#define XE_MASK (0xffff7fff)
2874
23976049
EZ		 2875/* An X form user context instruction. */
2876#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2877#define XUC_MASK XUC(0x3f, 0x1f)
2878
c3d65c1c
BE		 2879/* An XW form instruction. */
2880#define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
2881/* The mask for a G form instruction. rc not supported at present. */
2882#define XW_MASK XW (0x3f, 0x3f, 0)
2883
081ba1b3
AM		 2884/* An APU form instruction. */
2885#define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
2886
2887/* The mask for an APU form instruction. */
2888#define APU_MASK APU (0x3f, 0x3ff, 1)
2889#define APU_RT_MASK (APU_MASK | RT_MASK)
2890#define APU_RA_MASK (APU_MASK | RA_MASK)
2891
252b5132
RH		 2892/* The BO encodings used in extended conditional branch mnemonics. */
2893#define BODNZF (0x0)
2894#define BODNZFP (0x1)
2895#define BODZF (0x2)
2896#define BODZFP (0x3)
252b5132
RH		 2897#define BODNZT (0x8)
2898#define BODNZTP (0x9)
2899#define BODZT (0xa)
2900#define BODZTP (0xb)
802a735e
AM		 2901
2902#define BOF (0x4)
2903#define BOFP (0x5)
94efba12
AM		 2904#define BOFM4 (0x6)
2905#define BOFP4 (0x7)
252b5132
RH		 2906#define BOT (0xc)
2907#define BOTP (0xd)
94efba12
AM		 2908#define BOTM4 (0xe)
2909#define BOTP4 (0xf)
802a735e 2910
252b5132
RH		 2911#define BODNZ (0x10)
2912#define BODNZP (0x11)
2913#define BODZ (0x12)
2914#define BODZP (0x13)
94efba12
AM		 2915#define BODNZM4 (0x18)
2916#define BODNZP4 (0x19)
2917#define BODZM4 (0x1a)
2918#define BODZP4 (0x1b)
802a735e 2919
252b5132
RH		 2920#define BOU (0x14)
2921
b9c361e0
JL		 2922/* The BO16 encodings used in extended VLE conditional branch mnemonics. */
2923#define BO16F (0x0)
2924#define BO16T (0x1)
2925
2926/* The BO32 encodings used in extended VLE conditional branch mnemonics. */
2927#define BO32F (0x0)
2928#define BO32T (0x1)
2929#define BO32DNZ (0x2)
2930#define BO32DZ (0x3)
2931
252b5132
RH		 2932/* The BI condition bit encodings used in extended conditional branch
2933 mnemonics. */
2934#define CBLT (0)
2935#define CBGT (1)
2936#define CBEQ (2)
2937#define CBSO (3)
2938
2939/* The TO encodings used in extended trap mnemonics. */
2940#define TOLGT (0x1)
2941#define TOLLT (0x2)
2942#define TOEQ (0x4)
2943#define TOLGE (0x5)
2944#define TOLNL (0x5)
2945#define TOLLE (0x6)
2946#define TOLNG (0x6)
2947#define TOGT (0x8)
2948#define TOGE (0xc)
2949#define TONL (0xc)
2950#define TOLT (0x10)
2951#define TOLE (0x14)
2952#define TONG (0x14)
2953#define TONE (0x18)
2954#define TOU (0x1f)
2955\f
2956/* Smaller names for the flags so each entry in the opcodes table will
2957 fit on a single line. */
2958#undef PPC
de866fcc 2959#define PPC PPC_OPCODE_PPC
661bd698 2960#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
661bd698 2961#define POWER4 PPC_OPCODE_POWER4
1ed8e1e4 2962#define POWER5 PPC_OPCODE_POWER5
702f0fb4 2963#define POWER6 PPC_OPCODE_POWER6
066be9f7 2964#define POWER7 PPC_OPCODE_POWER7
5817ffd1 2965#define POWER8 PPC_OPCODE_POWER8
a680de9a 2966#define POWER9 PPC_OPCODE_POWER9
ede602d7 2967#define CELL PPC_OPCODE_CELL
bdc70b4a 2968#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
6b069ee7 2969#define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
bdc70b4a 2970 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
418c1742 2971#define PPC403 PPC_OPCODE_403
081ba1b3 2972#define PPC405 PPC_OPCODE_405
7d5b217e 2973#define PPC440 PPC_OPCODE_440
c8187e15 2974#define PPC464 PPC440
9fe54b1c 2975#define PPC476 PPC_OPCODE_476
ef5a96d5
AM		 2976#define PPC750 PPC_OPCODE_750
2977#define PPC7450 PPC_OPCODE_7450
2978#define PPC860 PPC_OPCODE_860
c3d65c1c 2979#define PPCPS PPC_OPCODE_PPCPS
a404d431 2980#define PPCVEC PPC_OPCODE_ALTIVEC
aea77599 2981#define PPCVEC2 PPC_OPCODE_ALTIVEC2
a680de9a 2982#define PPCVEC3 PPC_OPCODE_ALTIVEC2
9b4e5766 2983#define PPCVSX PPC_OPCODE_VSX
c0637f3a 2984#define PPCVSX2 PPC_OPCODE_VSX
a680de9a 2985#define PPCVSX3 PPC_OPCODE_VSX3
de866fcc
AM		 2986#define POWER PPC_OPCODE_POWER
2987#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
81a0b7e2
AM		 2988#define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2989#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
de866fcc 2990#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
de866fcc 2991#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
661bd698 2992#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
de866fcc 2993#define MFDEC1 PPC_OPCODE_POWER
bdc70b4a 2994#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
418c1742 2995#define BOOKE PPC_OPCODE_BOOKE
14b57c7c 2996#define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
36ae0db3 2997#define PPCE300 PPC_OPCODE_E300
14b57c7c
AM		 2998#define PPCSPE PPC_OPCODE_SPE
2999#define PPCISEL PPC_OPCODE_ISEL
3000#define PPCEFS PPC_OPCODE_EFS
de866fcc 3001#define PPCBRLK PPC_OPCODE_BRLOCK
23976049 3002#define PPCPMR PPC_OPCODE_PMR
aea77599 3003#define PPCTMR PPC_OPCODE_TMR
de866fcc 3004#define PPCCHLK PPC_OPCODE_CACHELCK
23976049 3005#define PPCRFMCI PPC_OPCODE_RFMCI
19a6653c 3006#define E500MC PPC_OPCODE_E500MC
634b50f2 3007#define PPCA2 PPC_OPCODE_A2
43e65147 3008#define TITAN PPC_OPCODE_TITAN
14b57c7c 3009#define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
e01d869a 3010#define E500 PPC_OPCODE_E500
aea77599 3011#define E6500 PPC_OPCODE_E6500
b9c361e0 3012#define PPCVLE PPC_OPCODE_VLE
5817ffd1 3013#define PPCHTM PPC_OPCODE_HTM
dfdaec14 3014#define E200Z4 PPC_OPCODE_E200Z4
4fff86c5
PB		 3015/* The list of embedded processors that use the embedded operand ordering
3016 for the 3 operand dcbt and dcbtst instructions. */
3017#define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
14b57c7c 3018 | PPC_OPCODE_A2)
4fff86c5
PB		 3019
3020
252b5132
RH		 3021\f
3022/* The opcode table.
3023
3024 The format of the opcode table is:
3025
8ebac3aa 3026 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
252b5132
RH		 3027
3028 NAME is the name of the instruction.
3029 OPCODE is the instruction opcode.
3030 MASK is the opcode mask; this is used to tell the disassembler
3031 which bits in the actual opcode must match OPCODE.
8ebac3aa
AM		 3032 FLAGS are flags indicating which processors support the instruction.
3033 ANTI indicates which processors don't support the instruction.
252b5132
RH		 3034 OPERANDS is the list of operands.
3035
3036 The disassembler reads the table in order and prints the first
3037 instruction which matches, so this table is sorted to put more
de866fcc
AM		 3038 specific instructions before more general instructions.
3039
3040 This table must be sorted by major opcode. Please try to keep it
3041 vaguely sorted within major opcode too, except of course where
3042 constrained otherwise by disassembler operation. */
252b5132
RH		 3043
3044const struct powerpc_opcode powerpc_opcodes[] = {
14b57c7c
AM		 3045{"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}},
3046{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3047{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3048{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3049{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3050{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3051{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3052{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3053{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3054{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3055{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3056{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3057{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3058{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3059{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3060{"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3061{"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}},
3062
3063{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3064{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3065{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3066{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3067{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3068{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3069{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3070{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3071{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3072{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3073{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3074{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3075{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3076{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3077{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3078{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3079{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3080{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3081{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3082{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3083{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3084{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3085{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3086{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3087{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3088{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3089{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3090{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3091{"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3092{"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3093{"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}},
3094{"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}},
3095
3096{"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3097{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3098{"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
3099{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3100{"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3101{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3102{"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3103{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3104{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3105{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
3106{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3107{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
3108{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3109{"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3110{"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3111{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3112{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3113{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3114{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3115{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3116{"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3117{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3118{"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3119{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3120{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3121{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3122{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3123{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3124{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3125{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3126{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3127{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3128{"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
3129{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3130{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3131{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3132{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3133{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3134{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3135{"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3136{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3137{"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3138{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3139{"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3140{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3141{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3142{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3143{"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}},
3144{"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3145{"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3146{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
3147{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3148{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
3149{"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3150{"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3151{"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3152{"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3153{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3154{"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3155{"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3156{"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3157{"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3158{"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3159{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3160{"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3161{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3162{"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
3163{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3164{"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3165{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3166{"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3167{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3168{"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3169{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3170{"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3171{"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3172{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3173{"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3174{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3175{"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3176{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3177{"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3178{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3179{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3180{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
3181{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3182{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
3183{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3184{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3185{"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3186{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3187{"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3188{"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3189{"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3190{"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3191{"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3192{"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3193{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3194{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3195{"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3196{"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3197{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3198{"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3199{"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3200{"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3201{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3202{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3203{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3204{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3205{"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3206{"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3207{"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3208{"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3209{"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3210{"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3211{"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3212{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3213{"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3214{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3215{"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3216{"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3217{"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3218{"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3219{"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3220{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3221{"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3222{"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3223{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3224{"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3225{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3226{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3227{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3228{"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3229{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3230{"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3231{"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3232{"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3233{"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3234{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3235{"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3236{"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3237{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3238{"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3239{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3240{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3241{"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3242{"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3243{"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3244{"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3245{"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3246{"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3247{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3248{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3249{"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3250{"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3251{"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3252{"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3253{"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3254{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3255{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3256{"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3257{"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3258{"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3259{"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3260{"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3261{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3262{"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3263{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3264{"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3265{"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3266{"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3267{"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3268{"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3269{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3270{"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
3271{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3272{"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3273{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3274{"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
3275{"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3276{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
3277{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3278{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3279{"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}},
3280{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3281{"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}},
3282{"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}},
3283{"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3284{"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}},
3285{"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}},
3286{"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}},
3287{"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3288{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},
3289{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},
3290{"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3291{"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3292{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3293{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3294{"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3295{"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3296{"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3297{"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
3298{"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3299{"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3300{"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
3301{"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3302{"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3303{"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3304{"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3305{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3306{"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3307{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3308{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3309{"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3310{"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3311{"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3312{"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}},
3313{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3314{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}},
3315{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3316{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3317{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3318{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3319{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3320{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3321{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3322{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3323{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3324{"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3325{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3326{"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3327{"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3328{"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3329{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3330{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3331{"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3332{"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}},
3333{"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3334{"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3335{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3336{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},
3337{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3338{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3339{"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3340{"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3341{"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3342{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},
3343{"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3344{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
3345{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
3346{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3347{"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3348{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3349{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3350{"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3351{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3352{"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
3353{"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3354{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3355{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3356{"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3357{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
3358{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
3359{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
3360{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
3361{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
3362{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
3363{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
3364{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
3365{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},
3366{"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3367{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},
3368{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3369{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3370{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3371{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3372{"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3373{"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3374{"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3375{"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
3376{"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3377{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
3378{"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
3379{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3380{"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3381{"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3382{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3383{"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3384{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3385{"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3386{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3387{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3388{"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3389{"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
3390{"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
3391{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
3392{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
3393{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
3394{"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
3395{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
3396{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
3397{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
3398{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
3399{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3400{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
3401{"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3402{"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3403{"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3404{"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3405{"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3406{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}},
3407{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}},
3408{"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
3409{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
3410{"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
3411{"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3412{"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3413{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}},
3414{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}},
3415{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3416{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3417{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3418{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
3419{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}},
3420{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}},
3421{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
3422{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
3423{"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
3424{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
3425{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
3426{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
3427{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}},
3428{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3429{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}},
3430{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3431{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3432{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3433{"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3434{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3435{"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3436{"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3437{"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3438{"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3439{"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3440{"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3441{"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3442{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3443{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3444{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3445{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3446{"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3447{"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3448{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3449{"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3450{"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3451{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3452{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3453{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3454{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3455{"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3456{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3457{"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3458{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3459{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3460{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3461{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3462{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3463{"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3464{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3465{"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3466{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3467{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3468{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3469{"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3470{"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3471{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3472{"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3473{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3474{"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3475{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3476{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3477{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3478{"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3479{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3480{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3481{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3482{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3483{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3484{"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3485{"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3486{"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3487{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3488{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3489{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3490{"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3491{"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3492{"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3493{"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3494{"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3495{"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3496{"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3497{"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3498{"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3499{"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3500{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3501{"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3502{"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3503{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3504{"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3505{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3506{"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3507{"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3508{"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3509{"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3510{"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3511{"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3512{"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3513{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3514{"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3515{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3516{"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3517{"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3518{"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3519{"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3520{"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3521{"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3522{"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3523{"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3524{"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
3525{"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3526{"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3527{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3528{"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3529{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3530{"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3531{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3532{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3533{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3534{"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3535{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3536{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3537{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3538{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3539{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3540{"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3541{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3542{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3543{"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3544{"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3545{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3546{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3547{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3548{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3549{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3550{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3551{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3552{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3553{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3554{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3555{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3556{"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
3557{"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3558{"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3559{"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3560{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3561{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3562{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3563{"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3564{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3565{"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3566{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3567{"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3568{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3569{"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3570{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3571{"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3572{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3573{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3574{"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3575{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3576{"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3577{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3578{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3579{"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3580{"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3581{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3582{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3583{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3584{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3585{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3586{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3587{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3588{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3589{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3590{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3591{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3592{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3593{"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3594{"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3595{"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3596{"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
3597{"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3598{"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3599{"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3600{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3601{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3602{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3603{"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3604{"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3605{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3606{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3607{"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3608{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}},
3609{"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3610{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}},
3611{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}},
3612{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}},
3613{"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}},
3614{"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3615{"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3616{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3617{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3618{"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3619{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3620{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3621{"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3622{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}},
3623{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},
3624{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},
3625{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},
3626{"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3627{"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3628{"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3629{"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3630{"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3631{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3632{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3633{"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3634{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3635{"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3636{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3637{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3638{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3639{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3640{"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
3641{"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3642{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3643{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3644{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3645{"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3646{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3647{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3648{"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3649{"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3650{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3651{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3652{"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3653{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3654{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3655{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3656{"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3657{"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3658{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3659{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3660{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3661{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3662{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3663{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3664{"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3665{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3666{"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3667{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3668{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3669{"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3670{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3671{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3672{"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3673{"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3674{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3675{"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3676{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3677{"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3678{"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3679{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3680{"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3681{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3682{"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3683{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3684{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3685{"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3686{"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3687{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3688{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3689{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3690{"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3691{"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3692{"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3693{"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3694{"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3695{"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3696{"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3697{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3698{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3699{"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3700{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3701{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3702{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3703{"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3704{"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3705{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3706{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3707{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3708{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3709{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3710{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3711{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3712{"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3713{"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3714{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3715{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3716{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3717{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3718{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3719{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3720{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3721{"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3722{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3723{"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3724{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3725{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3726{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3727{"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}},
3728{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3729{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3730{"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3731{"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3732{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3733{"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3734{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3735{"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3736{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3737{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3738{"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3739{"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3740{"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3741{"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
3742{"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
3743{"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3744{"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3745{"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3746{"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3747{"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3748{"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3749{"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3750{"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3751{"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3752{"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3753{"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3754{"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3755{"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3756{"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3757{"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}},
3758{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
9fe54b1c
PB		 3759{"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3760{"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3761{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3762{"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3763{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3764{"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}},
3765{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3766{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
9fe54b1c
PB		 3767{"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3768{"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3769{"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3770{"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3771{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3772{"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
3773{"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3774{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
9fe54b1c
PB		 3775{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3776{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3777{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3778{"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3779{"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3780{"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
3781{"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3782{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
9fe54b1c 3783{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c 3784{"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
9fe54b1c 3785{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3786{"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3787{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3788{"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3789{"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3790{"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3791{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
9fe54b1c
PB		 3792{"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3793{"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3794{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3795{"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3796{"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3797{"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3798{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3799{"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3800{"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3801{"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3802{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3803{"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
9fe54b1c
PB		 3804{"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3805{"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3806{"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3807{"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3808{"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3809{"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3810{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3811{"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3812{"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3813{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
9fe54b1c
PB		 3814{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3815{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3816{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3817{"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3818{"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3819{"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3820{"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3821{"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3822{"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3823{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
9fe54b1c 3824{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c 3825{"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
9fe54b1c 3826{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3827{"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3828{"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3829{"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3830{"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3831{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}},
3832
3833{"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3834{"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3835
3836{"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3837{"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3838
3839{"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}},
3840
3841{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}},
3842{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}},
a5721ba2 3843{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}},
14b57c7c
AM		 3844{"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}},
3845
3846{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}},
3847{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}},
a5721ba2 3848{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}},
14b57c7c
AM		 3849{"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}},
3850
3851{"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3852{"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3853{"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
3854
3855{"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3856{"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3857{"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
3858
3859{"li", OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}},
3860{"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}},
3861{"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}},
3862{"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
3863{"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}},
3864{"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
3865
3866{"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE, {RT, SISIGNOPT}},
3867{"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE, {RT, SISIGNOPT}},
3868{"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
3869{"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
3870{"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}},
3871
3872{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3873{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3874{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
3875{"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
3876{"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3877{"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3878{"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
3879{"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
3880{"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3881{"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3882{"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
3883{"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
3884{"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3885{"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3886{"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
3887{"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
3888{"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3889{"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3890{"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCVLE, {BD}},
3891{"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3892{"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3893{"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCVLE, {BD}},
3894{"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3895{"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3896{"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCVLE, {BDA}},
3897{"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3898{"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3899{"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCVLE, {BDA}},
3900
3901{"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3902{"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3903{"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3904{"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3905{"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3906{"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3907{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3908{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3909{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3910{"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3911{"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3912{"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3913{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3914{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3915{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3916{"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3917{"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3918{"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3919{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3920{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3921{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3922{"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3923{"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3924{"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3925{"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3926{"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3927{"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3928{"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3929{"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3930{"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3931{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3932{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3933{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3934{"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3935{"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3936{"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3937{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3938{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3939{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3940{"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3941{"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3942{"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3943{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3944{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3945{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3946{"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3947{"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3948{"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3949{"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3950{"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3951{"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3952{"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3953{"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3954{"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3955{"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3956{"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3957{"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3958{"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3959{"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3960{"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3961{"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3962{"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3963{"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3964{"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3965{"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3966{"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
3967{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3968{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3969{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3970{"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3971{"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3972{"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
3973{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3974{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3975{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3976{"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3977{"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3978{"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
3979{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3980{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3981{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3982{"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3983{"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3984{"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
3985
3986{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3987{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3988{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3989{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3990{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3991{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3992{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3993{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3994{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3995{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3996{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3997{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3998{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3999{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4000{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4001{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4002{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4003{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4004{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4005{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4006{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4007{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4008{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4009{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4010{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4011{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4012{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4013{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4014{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4015{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4016{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4017{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4018{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4019{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4020{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4021{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4022{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4023{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4024{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4025{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4026{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4027{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4028{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4029{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4030{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4031{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4032{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4033{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4034{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4035{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4036{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4037{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4038{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4039{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4040{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4041{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4042{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4043{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4044{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4045{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4046
4047{"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4048{"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4049{"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4050{"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4051{"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4052{"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4053{"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4054{"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4055{"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4056{"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4057{"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4058{"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4059{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4060{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4061{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4062{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4063{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4064{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4065{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4066{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4067{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4068{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4069{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4070{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4071
4072{"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4073{"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4074{"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4075{"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4076{"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4077{"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4078{"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4079{"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4080{"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4081{"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4082{"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4083{"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4084{"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4085{"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4086{"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4087{"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4088
4089{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4090{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4091{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4092{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4093{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4094{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4095{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4096{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4097{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4098{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4099{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4100{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4101{"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4102{"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4103{"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4104{"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4105{"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4106{"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4107{"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4108{"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4109{"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4110{"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4111{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4112{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4113
4114{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4115{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4116{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4117{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4118{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4119{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4120{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4121{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4122{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4123{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4124{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4125{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4126{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4127{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4128{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4129{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4130
4131{"bc-", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
4132{"bc+", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
4133{"bc", B(16,0,0), B_MASK, COM, PPCVLE, {BO, BI, BD}},
4134{"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
4135{"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
4136{"bcl", B(16,0,1), B_MASK, COM, PPCVLE, {BO, BI, BD}},
4137{"bca-", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
4138{"bca+", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
4139{"bca", B(16,1,0), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
4140{"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
4141{"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
4142{"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
4143
4144{"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
4145{"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
4146{"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}},
4147{"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
4148{"svcla", SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}},
4149
4150{"b", B(18,0,0), B_MASK, COM, PPCVLE, {LI}},
4151{"bl", B(18,0,1), B_MASK, COM, PPCVLE, {LI}},
4152{"ba", B(18,1,0), B_MASK, COM, PPCVLE, {LIA}},
4153{"bla", B(18,1,1), B_MASK, COM, PPCVLE, {LIA}},
4154
4155{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
4156
4157{"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}},
4158{"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}},
4159
4160{"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4161{"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4162{"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4163{"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4164{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4165{"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4166{"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4167{"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4168{"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4169{"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4170{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4171{"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4172{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4173{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
4174{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4175{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
4176{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4177{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4178{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4179{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4180{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4181{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4182{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4183{"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4184
4185{"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4186{"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4187{"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4188{"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4189{"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4190{"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4191{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4192{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4193{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4194{"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4195{"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4196{"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4197{"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4198{"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4199{"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4200{"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4201{"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4202{"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4203{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4204{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4205{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4206{"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4207{"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4208{"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4209{"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4210{"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4211{"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4212{"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4213{"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4214{"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4215{"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4216{"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4217{"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4218{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4219{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4220{"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4221{"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4222{"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4223{"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4224{"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4225{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4226{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4227{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4228{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4229{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4230{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4231{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4232{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4233{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4234{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4235{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4236{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4237{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4238{"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4239{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4240{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4241{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4242{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4243{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4244{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4245{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4246{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4247{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4248{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4249{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4250{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4251{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4252{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4253{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4254{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4255{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4256{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4257{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4258{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4259{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4260{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4261{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4262{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4263{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4264{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4265{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4266{"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4267{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4268{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4269{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4270{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4271{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4272{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4273{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4274{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4275{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4276{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4277{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4278{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4279{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4280{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4281{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4282{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4283{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4284{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4285{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4286{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4287{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4288{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4289{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4290{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4291{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4292{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4293{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4294{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4295{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4296{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4297{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4298{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4299{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4300{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4301{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4302{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4303{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4304{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4305{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4306{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4307{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4308{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4309{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4310{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4311{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4312{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4313{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4314{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4315{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4316{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4317{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4318{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4319{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4320{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4321{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4322{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4323{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4324{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4325
4326{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4327{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4328{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4329{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4330{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4331{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4332{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4333{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4334{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4335{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4336{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4337{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4338{"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4339{"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4340{"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4341{"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4342{"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4343{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4344{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4345{"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4346{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4347{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4348{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4349{"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4350{"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4351{"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4352{"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4353{"bdnztlrl-", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4354{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4355{"bdnztlrl+", XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4356{"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4357{"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4358{"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4359{"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4360{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4361{"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4362{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4363{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4364{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4365{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4366{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4367{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4368{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4369{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4370{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4371{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4372{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4373{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4374
4375{"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4376{"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4377{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4378{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4379{"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4380{"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4381{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4382{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4383
4384{"rfid", XL(19,18), 0xffffffff, PPC64, PPCVLE, {0}},
4385
4386{"crnot", XL(19,33), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
4387{"crnor", XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4388{"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}},
4389
4390{"rfdi", XL(19,39), 0xffffffff, E500MC, PPCVLE, {0}},
4391{"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}},
4392{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}},
4393
4394{"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}},
4395
4396{"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}},
4397
4398{"crandc", XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4399
4400{"rfebb", XL(19,146), XLS_MASK, POWER8, PPCVLE, {SXL}},
4401
4402{"isync", XL(19,150), 0xffffffff, PPCCOM, PPCVLE, {0}},
4403{"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}},
4404
4405{"crclr", XL(19,193), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
4406{"crxor", XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4407
4408{"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}},
4409
4410{"crnand", XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4411
4412{"crand", XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4413
4414{"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476|PPCVLE, {0}},
4415
4416{"crset", XL(19,289), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
4417{"creqv", XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4418
4419{"urfid", XL(19,306), 0xffffffff, POWER9, PPCVLE, {0}},
4420{"stop", XL(19,370), 0xffffffff, POWER9, PPCVLE, {0}},
4421
4422{"doze", XL(19,402), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4423
4424{"crorc", XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4425
4426{"nap", XL(19,434), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4427
4428{"crmove", XL(19,449), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
4429{"cror", XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4430
4431{"sleep", XL(19,466), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4432{"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4433
4434{"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCVLE, {0}},
4435{"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCVLE, {0}},
4436
4437{"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4438{"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4439{"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4440{"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4441{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4442{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4443{"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4444{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4445{"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4446{"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4447{"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4448{"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4449{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4450{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4451{"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4452{"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4453{"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4454{"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4455{"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4456{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4457{"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4458{"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4459{"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4460{"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4461{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4462{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4463{"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4464{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4465{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4466{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4467{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4468{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4469{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4470{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4471{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4472{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4473{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4474{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4475{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4476{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4477{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4478{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4479{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4480{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4481{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4482{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4483{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4484{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4485{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4486{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4487{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4488{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4489{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4490{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4491{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4492{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4493{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4494{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4495{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4496{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4497{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4498{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4499{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4500{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4501{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4502{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4503{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4504{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4505{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4506{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4507{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4508{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4509{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4510{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4511{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4512{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4513{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4514{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4515{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4516{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4517{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4518{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4519{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4520{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4521{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4522{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4523{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4524{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4525{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4526{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4527{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4528{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4529{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4530{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4531{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4532{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4533{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4534{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4535{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4536{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4537{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4538{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4539{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4540{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4541{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4542{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4543{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4544{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4545{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4546{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4547{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4548{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4549{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4550{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4551{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4552{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4553{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4554{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4555{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4556{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4557
4558{"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4559{"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4560{"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4561{"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4562{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4563{"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4564{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4565{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4566{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4567{"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4568{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4569{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4570{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4571{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4572{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4573{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4574{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4575{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4576{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4577{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4578
4579{"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4580{"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4581{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4582{"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4583{"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4584{"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4585{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4586{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4587
4588{"bctar-", XLYLK(19,560,0,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4589{"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4590{"bctar+", XLYLK(19,560,1,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4591{"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4592{"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
4593{"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
4594
4595{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4596{"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4597
4598{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4599{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4600
4601{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4602{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4603{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4604{"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4605{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4606{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4607{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4608{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4609
4610{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4611{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4612
4613{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4614{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4615{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4616{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4617{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4618{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4619
4620{"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}},
4621{"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4622{"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4623
4624{"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4625{"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4626
4627{"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}},
4628{"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4629{"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4630
4631{"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4632{"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4633
4634{"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4635{"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4636
4637{"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4638{"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4639
4640{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
4641{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
4642{"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4643{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
4644{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
4645{"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4646
4647{"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
4648{"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
4649
4650{"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4651{"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4652
4653{"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4654{"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4655
4656{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4657{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4658{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4659{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4660
4661{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4662{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4663
4664{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4665{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
a5721ba2 4666{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
bdc70b4a 4667{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
1cb0a767 4668
14b57c7c
AM		 4669{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4670{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4671{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4672{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4673{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}},
4674{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}},
4675{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4676{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4677{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4678{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4679{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4680{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4681{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4682{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4683{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4684{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4685{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4686{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4687{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4688{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4689{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4690{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4691{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4692{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4693{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4694{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4695{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4696{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4697{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}},
4698{"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}},
4699{"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}},
4700{"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}},
4701{"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
4702
4703{"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4704{"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4705{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4706
4707{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4708{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4709{"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4710{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4711{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4712{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4713
4714{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4715{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4716
4717{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4718{"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4719{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4720{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4721
4722{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4723{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4724
4725{"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
4726
4727{"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4728
4729{"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}},
4730{"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}},
4731{"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4732{"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}},
4733
4734{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}},
4735{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}},
4736
4737{"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}},
4738
4739{"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},
4740
4741{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}},
4742
4743{"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
4744{"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4745
4746{"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4747{"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4748{"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4749{"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4750
4751{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
4752{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
4753{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
4754{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
4755
4756{"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}},
4757{"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}},
4758
4759{"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}},
4760{"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}},
4761
4762{"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
4763{"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
4764
4765{"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4766
4767{"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}},
4768{"wait", X(31,30), XWC_MASK, POWER9, 0, {WC}},
4769
4770{"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4771
4772{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4773{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
a5721ba2 4774{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
bdc70b4a 4775{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
de866fcc 4776
14b57c7c
AM		 4777{"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4778{"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4779{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
de866fcc 4780
14b57c7c 4781{"mviwsplt", X(31,46), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
e67ed0e8 4782
14b57c7c 4783{"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
de866fcc 4784
14b57c7c 4785{"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
de866fcc 4786
14b57c7c 4787{"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}},
066be9f7 4788
14b57c7c 4789{"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
c0637f3a 4790
14b57c7c 4791{"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
de866fcc 4792
14b57c7c 4793{"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}},
de866fcc 4794
14b57c7c
AM		 4795{"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4796{"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}},
4797{"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4798{"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}},
de866fcc 4799
14b57c7c
AM		 4800{"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
4801{"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
4802{"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4803{"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}},
e0d602ec 4804
14b57c7c 4805{"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
066be9f7 4806
14b57c7c 4807{"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}},
43e65147 4808
14b57c7c 4809{"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}},
43e65147 4810
14b57c7c
AM		 4811{"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}},
4812{"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
de866fcc 4813
14b57c7c
AM		 4814{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}},
4815{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}},
de866fcc 4816
14b57c7c
AM		 4817{"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}},
4818{"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}},
de866fcc 4819
14b57c7c
AM		 4820{"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
4821{"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
4822{"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}},
43e65147 4823
14b57c7c 4824{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
19a6653c 4825
14b57c7c
AM		 4826{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}},
4827{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}},
4828{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}},
4829{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}},
4830{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}},
4831{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}},
4832{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}},
4833{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}},
4834{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}},
4835{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}},
4836{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}},
4837{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}},
4838{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}},
4839{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}},
4840{"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}},
4841{"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}},
de866fcc 4842
14b57c7c
AM		 4843{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4844{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4845{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
43e65147 4846
14b57c7c
AM		 4847{"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4848{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
de866fcc 4849
14b57c7c
AM		 4850{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
4851{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
de866fcc 4852
14b57c7c 4853{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}},
de866fcc 4854
14b57c7c 4855{"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}},
43e65147 4856
14b57c7c 4857{"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
de866fcc 4858
c7a8dbf9 4859{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},
a5721ba2 4860{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}},
de866fcc 4861
14b57c7c 4862{"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
43e65147 4863
14b57c7c 4864{"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
de866fcc 4865
14b57c7c 4866{"dni", XRC(31,97,1), XRB_MASK, E6500, 0, {DUI, DCTL}},
aea77599 4867
14b57c7c
AM		 4868{"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4869{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
de866fcc 4870
14b57c7c
AM		 4871{"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}},
4872{"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}},
de866fcc 4873
14b57c7c
AM		 4874{"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
4875{"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
de866fcc 4876
14b57c7c 4877{"mvidsplt", X(31,110), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
aea77599 4878
14b57c7c 4879{"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}},
de866fcc 4880
14b57c7c
AM		 4881{"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
4882{"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4883{"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
c0637f3a 4884
14b57c7c 4885{"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
066be9f7 4886
14b57c7c 4887{"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}},
de866fcc 4888
14b57c7c 4889{"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}},
43e65147 4890
14b57c7c 4891{"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}},
de866fcc 4892
14b57c7c
AM		 4893{"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RBS}},
4894{"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}},
4895{"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RBS}},
4896{"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}},
19a6653c 4897
14b57c7c 4898{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
43e65147 4899
fd486b63 4900{"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
a680de9a 4901
14b57c7c 4902{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}},
43e65147 4903
14b57c7c 4904{"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
de866fcc 4905
14b57c7c
AM		 4906{"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4907{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
de866fcc 4908
14b57c7c
AM		 4909{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4910{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4911{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4912{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
de866fcc 4913
14b57c7c
AM		 4914{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4915{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4916{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4917{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
de866fcc 4918
14b57c7c 4919{"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
c0637f3a 4920
14b57c7c
AM		 4921{"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}},
4922{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
de866fcc 4923
14b57c7c
AM		 4924{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, 0, {RS}},
4925{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}},
4926{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}},
de866fcc 4927
14b57c7c 4928{"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}},
de866fcc 4929
14b57c7c 4930{"mtsle", X(31,147), XRTLRARB_MASK, POWER8, 0, {L}},
c0637f3a 4931
14b57c7c
AM		 4932{"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}},
4933{"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
e0d602ec 4934
14b57c7c 4935{"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}},
43e65147 4936
14b57c7c 4937{"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}},
43e65147 4938
14b57c7c
AM		 4939{"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
4940{"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}},
de866fcc 4941
14b57c7c
AM		 4942{"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}},
4943{"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}},
de866fcc 4944
14b57c7c
AM		 4945{"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}},
4946{"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}},
de866fcc 4947
14b57c7c 4948{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}},
de866fcc 4949
14b57c7c 4950{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
43e65147 4951
14b57c7c 4952{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
43e65147 4953
14b57c7c 4954{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}},
43e65147 4955
14b57c7c 4956{"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
de866fcc 4957
14b57c7c
AM		 4958{"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4959{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
de866fcc 4960
14b57c7c 4961{"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
19dfcc89 4962
14b57c7c
AM		 4963{"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}},
4964{"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
de866fcc 4965
14b57c7c 4966{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}},
de866fcc 4967
14b57c7c
AM		 4968{"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
4969{"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
4970{"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
4971{"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}},
e0d602ec 4972
14b57c7c 4973{"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}},
de866fcc 4974
14b57c7c
AM		 4975{"stqcx.", XRC(31,182,1), X_MASK, POWER8, 0, {RSQ, RA0, RB}},
4976{"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}},
e0d602ec 4977
14b57c7c
AM		 4978{"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}},
4979{"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
de866fcc 4980
14b57c7c
AM		 4981{"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}},
4982{"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}},
de866fcc 4983
14b57c7c 4984{"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}},
252b5132 4985
14b57c7c 4986{"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}},
a680de9a 4987
14b57c7c 4988{"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},
aea77599 4989
14b57c7c
AM		 4990{"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4991{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 4992
14b57c7c
AM		 4993{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
4994{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
4995{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
4996{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
252b5132 4997
14b57c7c
AM		 4998{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
4999{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5000{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5001{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
418c1742 5002
14b57c7c 5003{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
19a6653c 5004
14b57c7c 5005{"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
418c1742 5006
14b57c7c
AM		 5007{"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5008{"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5009{"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5010{"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}},
e0d602ec 5011
14b57c7c 5012{"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
e0d602ec 5013
14b57c7c 5014{"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}},
43e65147 5015
14b57c7c 5016{"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}},
252b5132 5017
14b57c7c
AM		 5018{"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}},
5019{"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 5020
14b57c7c
AM		 5021{"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
5022{"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 5023
14b57c7c 5024{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
43e65147 5025
14b57c7c 5026{"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}},
a680de9a 5027
14b57c7c 5028{"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
7d5b217e 5029
14b57c7c
AM		 5030{"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5031{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
f509565f 5032
14b57c7c
AM		 5033{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5034{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5035{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5036{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
252b5132 5037
14b57c7c
AM		 5038{"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5039{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
43e65147 5040
14b57c7c
AM		 5041{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5042{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5043{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5044{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
252b5132 5045
14b57c7c
AM		 5046{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5047{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5048{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5049{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 5050
14b57c7c
AM		 5051{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
5052{"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
5053{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
bdc70b4a 5054{"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
418c1742 5055
14b57c7c
AM		 5056{"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5057{"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5058{"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
c0637f3a 5059
14b57c7c
AM		 5060{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5061{"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5062{"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5063{"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
4fff86c5 5064
14b57c7c 5065{"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}},
252b5132 5066
14b57c7c
AM		 5067{"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}},
5068{"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}},
252b5132 5069
14b57c7c 5070{"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}},
066be9f7 5071
14b57c7c 5072{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
19a6653c 5073
14b57c7c
AM		 5074{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
5075{"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}},
252b5132 5076
14b57c7c 5077{"lvexbx", X(31,261), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 5078
14b57c7c 5079{"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}},
1ed8e1e4 5080
14b57c7c 5081{"lvepxl", X(31,263), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 5082
14b57c7c
AM		 5083{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5084{"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5085{"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 5086
14b57c7c 5087{"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}},
a680de9a 5088
14b57c7c
AM		 5089{"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5090{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5091{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5092{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
418c1742 5093
14b57c7c 5094{"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}},
a680de9a 5095
14b57c7c
AM		 5096{"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}},
5097{"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 5098
14b57c7c 5099{"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}},
19a6653c 5100
14b57c7c 5101{"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}},
a5721ba2 5102{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}},
418c1742 5103
14b57c7c 5104{"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
1cb0a767 5105
14b57c7c 5106{"lqarx", X(31,276), XEH_MASK, POWER8, 0, {RTQ, RAX, RBX, EH}},
c0637f3a 5107
14b57c7c
AM		 5108{"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}},
5109{"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},
1cb0a767 5110
14b57c7c
AM		 5111{"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5112{"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5113{"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5114{"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
4fff86c5 5115
14b57c7c 5116{"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}},
1cb0a767 5117
14b57c7c 5118{"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}},
066be9f7 5119
14b57c7c
AM		 5120{"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}},
5121{"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}},
1cb0a767 5122
14b57c7c 5123{"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
1cb0a767 5124
14b57c7c 5125{"mfdcrux", X(31,291), X_MASK, PPC464, 0, {RS, RA}},
1cb0a767 5126
14b57c7c
AM		 5127{"lvexhx", X(31,293), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5128{"lvepx", X(31,295), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 5129
14b57c7c 5130{"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 5131
14b57c7c 5132{"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
c0637f3a 5133
14b57c7c
AM		 5134{"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
5135{"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},
a5721ba2 5136{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}},
14b57c7c 5137{"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},
1cb0a767 5138
14b57c7c 5139{"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},
a680de9a 5140
14b57c7c 5141{"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}},
a680de9a 5142
14b57c7c 5143{"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
1cb0a767 5144
14b57c7c 5145{"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}},
1cb0a767 5146
14b57c7c 5147{"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}},
066be9f7 5148
14b57c7c
AM		 5149{"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}},
5150{"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}},
1cb0a767 5151
14b57c7c 5152{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
1cb0a767 5153
14b57c7c
AM		 5154{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}},
5155{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}},
5156{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}},
5157{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}},
5158{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}},
5159{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}},
5160{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}},
5161{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}},
5162{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}},
5163{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}},
5164{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}},
5165{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}},
5166{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}},
5167{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}},
5168{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}},
5169{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}},
5170{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}},
5171{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}},
5172{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}},
5173{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}},
5174{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}},
5175{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}},
5176{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}},
5177{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}},
5178{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}},
5179{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}},
5180{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}},
5181{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}},
5182{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}},
5183{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}},
5184{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}},
5185{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}},
5186{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}},
5187{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}},
5188{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
5189{"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}},
1cb0a767 5190
14b57c7c 5191{"lvexwx", X(31,325), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 5192
14b57c7c 5193{"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}},
9fe54b1c 5194
14b57c7c
AM		 5195{"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5196{"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
1cb0a767 5197
14b57c7c 5198{"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
066be9f7 5199
14b57c7c
AM		 5200{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
5201{"mftmr", X(31,366), X_MASK, PPCTMR|E6500, 0, {RT, TMR}},
1cb0a767 5202
14b57c7c
AM		 5203{"slbsync", X(31,338), 0xffffffff, POWER9, 0, {0}},
5204
5205{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}},
5206{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}},
5207{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
5208{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
5209{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}},
5210{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}},
5211{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}},
5212{"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}},
5213{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}},
5214{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
5215{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
bdc70b4a 5216{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}},
14b57c7c
AM		 5217{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}},
5218{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}},
5219{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}},
5220{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}},
5221{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}},
5222{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}},
5223{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}},
5224{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}},
5225{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}},
5226{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}},
5227{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}},
5228{"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}},
5229{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}},
5230{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}},
5231{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}},
5232{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}},
5233{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}},
5234{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}},
5235{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}},
5236{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}},
5237{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}},
5238{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}},
5239{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}},
5240{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}},
5241{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}},
5242{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}},
5243{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}},
5244{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}},
5245{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}},
5246{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}},
5247{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}},
5248{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5249{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5250{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5251{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5252{"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5253{"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}},
5254{"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5255{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}},
5256{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}},
5257{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}},
5258{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}},
5259{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}},
5260{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
5261{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}},
5262{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}},
5263{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}},
5264{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}},
5265{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}},
5266{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}},
5267{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}},
5268{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}},
5269{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}},
5270{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}},
5271{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}},
5272{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}},
5273{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}},
5274{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}},
5275{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}},
5276{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}},
5277{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}},
5278{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}},
5279{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}},
5280{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}},
5281{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}},
5282{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}},
5283{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}},
5284{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}},
5285{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}},
5286{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}},
5287{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}},
5288{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}},
5289{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}},
5290{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}},
5291{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}},
5292{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}},
5293{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}},
5294{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}},
5295{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}},
5296{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, 0, {RT}},
5297{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5298{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, 0, {RT}},
5299{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5300{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}},
5301{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}},
5302{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5303{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5304{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}},
5305{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}},
5306{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}},
5307{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}},
5308{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}},
5309{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}},
5310{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}},
5311{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}},
5312{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}},
5313{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}},
5314{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}},
5315{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}},
5316{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}},
5317{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}},
5318{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}},
5319{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}},
5320{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}},
5321{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}},
5322{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}},
5323{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}},
5324{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}},
5325{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}},
5326{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}},
5327{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}},
5328{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}},
5329{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}},
5330{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}},
5331{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}},
5332{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}},
5333{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}},
5334{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}},
5335{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}},
5336{"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}},
5337{"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}},
5338{"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}},
5339{"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}},
5340{"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}},
5341{"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}},
5342{"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}},
5343{"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}},
5344{"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}},
5345{"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}},
5346{"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}},
5347{"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}},
5348{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}},
5349{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}},
5350{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}},
5351{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}},
5352{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}},
5353{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}},
5354{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}},
5355{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}},
5356{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}},
5357{"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}},
5358{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}},
5359{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}},
5360{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}},
5361{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}},
5362{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}},
5363{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}},
5364{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}},
5365{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}},
5366{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}},
5367{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}},
5368{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}},
5369{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}},
5370{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}},
5371{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}},
5372{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}},
5373{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}},
5374{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}},
5375{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}},
5376{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}},
5377{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}},
5378{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}},
5379{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}},
5380{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}},
5381{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}},
5382{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}},
5383{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}},
5384{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}},
5385{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}},
5386{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}},
5387{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}},
5388{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}},
5389{"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}},
5390{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}},
5391{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}},
5392{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}},
5393{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}},
5394{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}},
5395{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}},
5396{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}},
5397{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}},
5398{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}},
5399{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}},
5400{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}},
5401{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}},
5402{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}},
5403{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}},
5404{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}},
5405{"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}},
5406
5407{"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}},
5408
5409{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
5410
5411{"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}},
5412
5413{"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5414
5415{"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}},
5416{"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}},
5417
5418{"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5419{"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5420
5421{"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5422
5423{"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}},
1cb0a767 5424
db76a700 5425{"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}},
14b57c7c 5426{"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
db76a700 5427{"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}},
1cb0a767 5428
14b57c7c 5429{"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}},
1cb0a767 5430
14b57c7c 5431{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
1cb0a767 5432
14b57c7c 5433{"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}},
1cb0a767 5434
14b57c7c 5435{"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
066be9f7 5436
14b57c7c
AM		 5437{"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
5438{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}},
1cb0a767 5439
14b57c7c 5440{"stvexbx", X(31,389), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 5441
14b57c7c
AM		 5442{"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5443{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
1cb0a767 5444
14b57c7c
AM		 5445{"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5446{"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5447{"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5448{"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
066be9f7 5449
14b57c7c
AM		 5450{"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5451{"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
a680de9a 5452
14b57c7c 5453{"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
1cb0a767 5454
14b57c7c 5455{"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}},
1cb0a767 5456
14b57c7c 5457{"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}},
a680de9a 5458
14b57c7c 5459{"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}},
c0637f3a 5460
14b57c7c
AM		 5461{"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
5462{"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
e0d602ec 5463
14b57c7c 5464{"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}},
1cb0a767 5465
14b57c7c
AM		 5466{"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}},
5467{"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}},
1cb0a767 5468
14b57c7c 5469{"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
1cb0a767 5470
14b57c7c 5471{"mtdcrux", X(31,419), X_MASK, PPC464, 0, {RA, RS}},
1cb0a767 5472
14b57c7c 5473{"stvexhx", X(31,421), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 5474
14b57c7c 5475{"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}},
aea77599 5476
14b57c7c
AM		 5477{"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5478{"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5479{"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5480{"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
066be9f7 5481
14b57c7c 5482{"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
a680de9a 5483
14b57c7c 5484{"clrbhrb", X(31,430), 0xffffffff, POWER8, 0, {0}},
c0637f3a 5485
14b57c7c 5486{"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}},
1cb0a767 5487
14b57c7c 5488{"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 5489
14b57c7c 5490{"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
1cb0a767 5491
14b57c7c 5492{"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
1cb0a767 5493
14b57c7c 5494{"mdors", 0x7f9ce378, 0xffffffff, E500MC, 0, {0}},
1cb0a767 5495
14b57c7c 5496{"miso", 0x7f5ad378, 0xffffffff, E6500, 0, {0}},
aea77599 5497
9f6a6cc0 5498/* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
14b57c7c
AM		 5499 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
5500{"yield", 0x7f7bdb78, 0xffffffff, POWER7, 0, {0}},
5501{"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, 0, {0}},
5502{"mdoom", 0x7fdef378, 0xffffffff, POWER7, 0, {0}},
5503{"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RBS}},
5504{"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},
5505{"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RBS}},
5506{"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}},
5507
5508{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}},
5509{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}},
5510{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}},
5511{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}},
5512{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}},
5513{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}},
5514{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}},
5515{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}},
5516{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}},
5517{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}},
5518{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}},
5519{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}},
5520{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}},
5521{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}},
5522{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}},
5523{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}},
5524{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}},
5525{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}},
5526{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}},
5527{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}},
5528{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}},
5529{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}},
5530{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}},
5531{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}},
5532{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}},
5533{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}},
5534{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}},
5535{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}},
5536{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}},
5537{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}},
5538{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}},
5539{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}},
5540{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}},
5541{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}},
5542{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}},
5543{"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}},
5544
5545{"stvexwx", X(31,453), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5546
5547{"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
5548{"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
5549
5550{"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5551{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5552
5553{"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5554{"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5555
5556{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
5557{"mttmr", X(31,494), X_MASK, PPCTMR|E6500, 0, {TMR, RS}},
5558
5559{"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}},
5560
5561{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}},
5562{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}},
5563{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}},
5564{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}},
5565{"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}},
5566{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}},
5567{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
5568{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}},
5569{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}},
5570{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}},
5571{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, 0, {RS}},
5572{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, 0, {RS}},
5573{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}},
5574{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}},
5575{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}},
5576{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}},
5577{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}},
5578{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}},
5579{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}},
5580{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}},
5581{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}},
5582{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}},
5583{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}},
5584{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}},
5585{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}},
5586{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}},
5587{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, 0, {RS}},
5588{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, 0, {RS}},
5589{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, 0, {RS}},
5590{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, 0, {RS}},
5591{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}},
5592{"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}},
5593{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}},
5594{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}},
5595{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}},
5596{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}},
5597{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}},
5598{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}},
5599{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}},
5600{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}},
5601{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}},
5602{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}},
5603{"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}},
5604{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}},
5605{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}},
5606{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}},
5607{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}},
5608{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5609{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5610{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5611{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5612{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, 0, {RS}},
5613{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}},
5614{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}},
5615{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}},
5616{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}},
5617{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}},
5618{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}},
5619{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}},
5620{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}},
5621{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}},
5622{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}},
5623{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}},
5624{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}},
5625{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}},
5626{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}},
5627{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}},
5628{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}},
5629{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}},
5630{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}},
5631{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}},
5632{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}},
5633{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, 0, {RS}},
5634{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, 0, {RS}},
5635{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, 0, {RS}},
5636{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, 0, {RS}},
5637{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, 0, {RS}},
5638{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, 0, {RS}},
5639{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, 0, {RS}},
5640{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, 0, {RS}},
5641{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, 0, {RS}},
5642{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, 0, {RS}},
5643{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}},
5644{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}},
5645{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}},
5646{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}},
5647{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}},
5648{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}},
5649{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, 0, {RS}},
5650{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5651{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, 0, {RS}},
5652{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5653{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}},
5654{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}},
5655{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5656{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5657{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}},
5658{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}},
5659{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}},
5660{"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}},
5661{"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}},
5662{"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}},
5663{"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, 0, {RS}},
5664{"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, 0, {RS}},
5665{"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}},
5666{"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}},
5667{"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}},
5668{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}},
5669{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}},
5670{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}},
5671{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, 0, {RS}},
5672{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, 0, {RS}},
5673{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, 0, {RS}},
5674{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, 0, {RS}},
5675{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, 0, {RS}},
5676{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, 0, {RS}},
5677{"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, 0, {RS}},
5678{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0, {RS}},
5679{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, 0, {RS}},
5680{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, 0, {RS}},
5681{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, 0, {RS}},
5682{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, 0, {RS}},
5683{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, 0, {RS}},
5684{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, 0, {RS}},
5685{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, 0, {RS}},
5686{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, 0, {RS}},
5687{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, 0, {RS}},
5688{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, 0, {RS}},
5689{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, 0, {RS}},
5690{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, 0, {RS}},
5691{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, 0, {RS}},
5692{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, 0, {RS}},
5693{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, 0, {RS}},
5694{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, 0, {RS}},
5695{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, 0, {RS}},
5696{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, 0, {RS}},
5697{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, 0, {RS}},
5698{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, 0, {RS}},
5699{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, 0, {RS}},
5700{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, 0, {RS}},
5701{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, 0, {RS}},
5702{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, 0, {RS}},
5703{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, 0, {RS}},
5704{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, 0, {RS}},
5705{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}},
5706{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}},
5707{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}},
5708{"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}},
5709{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}},
5710{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}},
5711{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}},
5712{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}},
5713{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}},
5714{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}},
5715{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, 0, {RS}},
5716{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, 0, {RS}},
5717{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, 0, {RS}},
5718{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, 0, {RS}},
5719{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, 0, {RS}},
5720{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, 0, {RS}},
5721{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, 0, {RS}},
5722{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, 0, {RS}},
5723{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, 0, {RS}},
5724{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, 0, {RS}},
5725{"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}},
5726
5727{"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}},
5728
5729{"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}},
5730{"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}},
5731
5732{"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}},
5733
5734{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}},
5735
5736{"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5737
5738{"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5739
5740{"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}},
5741{"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}},
5742
5743{"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5744{"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5745
5746{"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5747{"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5748
5749{"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
5750
5751{"slbia", X(31,498), 0xff1fffff, POWER6, 0, {IH}},
4bc0608a 5752{"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}},
1cb0a767 5753
14b57c7c 5754{"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}},
1cb0a767 5755
14b57c7c 5756{"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
066be9f7 5757
14b57c7c 5758{"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}},
1cb0a767 5759
14b57c7c 5760{"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}},
252b5132 5761
dfdaec14 5762{"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
14b57c7c 5763{"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},
19a6653c 5764
14b57c7c 5765{"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
252b5132 5766
14b57c7c
AM		 5767{"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}},
5768{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 5769
14b57c7c
AM		 5770{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5771{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5772{"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
5773{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5774{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5775{"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
43e65147 5776
14b57c7c
AM		 5777{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5778{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5779{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5780{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 5781
14b57c7c 5782{"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
c0637f3a 5783
14b57c7c 5784{"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}},
418c1742 5785
14b57c7c 5786{"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}},
418c1742 5787
14b57c7c
AM		 5788{"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}},
5789{"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 5790
14b57c7c
AM		 5791{"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
5792{"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 5793
14b57c7c 5794{"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
702f0fb4 5795
14b57c7c
AM		 5796{"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5797{"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
5798{"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5799{"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
252b5132 5800
14b57c7c
AM		 5801{"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}},
5802{"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}},
23976049 5803
14b57c7c
AM		 5804{"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}},
5805{"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}},
a680de9a 5806
14b57c7c
AM		 5807{"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}},
5808{"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}},
f509565f 5809
14b57c7c
AM		 5810{"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},
5811{"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 5812
dfdaec14 5813{"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
14b57c7c 5814{"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},
19a6653c 5815
14b57c7c 5816{"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 5817
14b57c7c 5818{"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}},
418c1742 5819
14b57c7c
AM		 5820{"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}},
5821{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 5822
14b57c7c
AM		 5823{"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5824{"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}},
5825{"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5826{"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}},
252b5132 5827
14b57c7c 5828{"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}},
252b5132 5829
14b57c7c 5830{"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
252b5132 5831
14b57c7c
AM		 5832{"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}},
5833{"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}},
a680de9a 5834
14b57c7c 5835{"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
a680de9a 5836
dfdaec14 5837{"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
14b57c7c 5838{"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},
19a6653c 5839
14b57c7c 5840{"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 5841
14b57c7c 5842{"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}},
a680de9a 5843
14b57c7c 5844{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
081ba1b3 5845
14b57c7c 5846{"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
066be9f7 5847
14b57c7c 5848{"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
252b5132 5849
14b57c7c
AM		 5850{"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}},
5851{"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}},
252b5132 5852
dc302c00 5853{"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},
e01d869a 5854{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
14b57c7c 5855{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}},
fd486b63
PB		 5856{"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}},
5857{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}},
14b57c7c
AM		 5858{"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}},
5859{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
5860{"lwsync", X(31,598), 0xffffffff, E500, 0, {0}},
5861{"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}},
418c1742 5862
14b57c7c 5863{"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
23976049 5864
066be9f7 5865{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
14b57c7c 5866{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}},
252b5132 5867
14b57c7c 5868{"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}},
19a6653c 5869
14b57c7c 5870{"lvswx", X(31,613), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 5871
14b57c7c 5872{"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}},
a680de9a 5873
14b57c7c 5874{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
081ba1b3 5875
14b57c7c
AM		 5876{"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}},
5877{"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}},
252b5132 5878
14b57c7c
AM		 5879{"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
5880{"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 5881
14b57c7c 5882{"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},
252b5132 5883
14b57c7c 5884{"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}},
252b5132 5885
14b57c7c 5886{"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
252b5132 5887
dfdaec14 5888{"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
14b57c7c 5889{"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}},
19a6653c 5890
14b57c7c
AM		 5891{"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
5892{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
23976049 5893
14b57c7c 5894{"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
c0637f3a 5895
14b57c7c 5896{"tbegin.", XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}},
5817ffd1 5897
14b57c7c
AM		 5898{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5899{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5900{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5901{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 5902
14b57c7c
AM		 5903{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5904{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5905{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5906{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 5907
14b57c7c 5908{"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
418c1742 5909
14b57c7c 5910{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}},
252b5132 5911
14b57c7c
AM		 5912{"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},
5913{"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
418c1742 5914
14b57c7c
AM		 5915{"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
5916{"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
252b5132 5917
14b57c7c 5918{"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
ede602d7 5919
14b57c7c
AM		 5920{"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}},
5921{"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 5922
14b57c7c
AM		 5923{"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},
5924{"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 5925
dfdaec14 5926{"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
14b57c7c 5927{"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}},
19a6653c 5928
14b57c7c 5929{"stvfrx", X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 5930
14b57c7c
AM		 5931{"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}},
5932{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 5933
14b57c7c
AM		 5934{"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}},
5935{"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}},
5817ffd1 5936
14b57c7c 5937{"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
066be9f7 5938
14b57c7c 5939{"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
252b5132 5940
14b57c7c
AM		 5941{"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},
5942{"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
252b5132 5943
dfdaec14 5944{"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},
14b57c7c 5945{"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}},
19a6653c 5946
14b57c7c 5947{"stvflx", X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 5948
14b57c7c 5949{"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}},
a680de9a 5950
14b57c7c 5951{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
081ba1b3 5952
14b57c7c 5953{"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
066be9f7 5954
14b57c7c 5955{"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}},
5817ffd1 5956
14b57c7c
AM		 5957{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5958{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5959{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5960{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
418c1742 5961
14b57c7c
AM		 5962{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5963{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5964{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5965{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
fdd12ef3 5966
14b57c7c
AM		 5967{"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},
5968{"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}},
252b5132 5969
14b57c7c 5970{"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
066be9f7 5971
14b57c7c 5972{"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
252b5132 5973
14b57c7c
AM		 5974{"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}},
5975{"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}},
418c1742 5976
14b57c7c
AM		 5977{"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}},
5978{"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 5979
066be9f7 5980{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
14b57c7c 5981{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}},
252b5132 5982
14b57c7c 5983{"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}},
19a6653c 5984
14b57c7c 5985{"stvswx", X(31,741), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 5986
14b57c7c 5987{"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}},
a680de9a 5988
14b57c7c 5989{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
081ba1b3 5990
14b57c7c
AM		 5991{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5992{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5993{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5994{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
252b5132 5995
14b57c7c
AM		 5996{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5997{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
252b5132 5998
14b57c7c
AM		 5999{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6000{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6001{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6002{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
418c1742 6003
14b57c7c
AM		 6004{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6005{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6006{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6007{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
702f0fb4 6008
14b57c7c
AM		 6009{"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6010{"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6011{"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}},
5817ffd1 6012
14b57c7c 6013{"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}},
a680de9a 6014
14b57c7c
AM		 6015{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
6016{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}},
252b5132 6017
14b57c7c 6018{"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
252b5132 6019
14b57c7c
AM		 6020{"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}},
6021{"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}},
252b5132 6022
14b57c7c 6023{"lvsm", X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
a680de9a 6024
fd486b63 6025{"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},
a680de9a 6026
14b57c7c
AM		 6027{"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6028{"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},
6029{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
ede602d7 6030
14b57c7c
AM		 6031{"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6032{"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 6033
14b57c7c
AM		 6034{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6035{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6036{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6037{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 6038
14b57c7c
AM		 6039{"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}},
6040{"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}},
a680de9a 6041
14b57c7c
AM		 6042{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
6043{"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
066be9f7 6044
14b57c7c 6045{"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
5817ffd1 6046
14b57c7c 6047{"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
252b5132 6048
14b57c7c 6049{"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}},
252b5132 6050
14b57c7c 6051{"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}},
252b5132 6052
14b57c7c
AM		 6053{"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA0, RB}},
6054{"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}},
418c1742 6055
14b57c7c
AM		 6056{"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6057{"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6058{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6059{"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
fdd12ef3 6060
14b57c7c
AM		 6061{"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}},
6062{"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}},
252b5132 6063
14b57c7c 6064{"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}},
19a6653c 6065
14b57c7c
AM		 6066{"lvtrxl", X(31,805), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6067{"stvepx", X(31,807), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6068{"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}},
252b5132 6069
14b57c7c
AM		 6070{"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6071{"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 6072
14b57c7c 6073{"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
5817ffd1 6074
14b57c7c 6075{"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}},
252b5132 6076
14b57c7c 6077{"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}},
e0d602ec 6078
14b57c7c 6079{"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}},
252b5132 6080
14b57c7c 6081{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, 0, {STRM}},
252b5132 6082
14b57c7c 6083{"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}},
fdd12ef3 6084
14b57c7c
AM		 6085{"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6086{"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}},
6087{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6088{"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}},
702f0fb4 6089
14b57c7c
AM		 6090{"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}},
6091{"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}},
e0c21649 6092
14b57c7c 6093{"lvtlxl", X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 6094
fd486b63 6095{"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}},
a680de9a 6096
14b57c7c
AM		 6097{"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6098{"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 6099
14b57c7c 6100{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
a680de9a 6101{"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}},
9b4e5766 6102
14b57c7c 6103{"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
5817ffd1 6104
14b57c7c 6105{"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}},
e0d602ec 6106
fd486b63 6107{"slbiag", X(31,850), XRARB_MASK, POWER9, 0, {RS}},
14b57c7c 6108{"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
a680de9a 6109{"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}},
252b5132 6110
14b57c7c 6111{"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}},
418c1742 6112
9fe54b1c 6113{"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}},
14b57c7c
AM		 6114{"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}},
6115{"eieio", XMBAR(31,854,1),0xffffffff, E500, 0, {0}},
6116{"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, 0, {0}},
418c1742 6117
14b57c7c 6118{"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}},
418c1742 6119
14b57c7c 6120{"lvswxl", X(31,869), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 6121
14b57c7c
AM		 6122{"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}},
6123{"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}},
702f0fb4 6124
14b57c7c
AM		 6125{"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6126{"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 6127
14b57c7c 6128{"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 6129
14b57c7c 6130{"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
5817ffd1 6131
14b57c7c 6132{"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}},
a680de9a 6133
14b57c7c 6134{"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}},
252b5132 6135
14b57c7c 6136{"msgsync", X(31,886), 0xffffffff, POWER9, 0, {0}},
a680de9a 6137
14b57c7c 6138{"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}},
066be9f7 6139
14b57c7c
AM		 6140{"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}},
6141{"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}},
a680de9a 6142
fd486b63 6143{"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}},
a680de9a 6144
14b57c7c
AM		 6145{"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},
6146{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 6147
14b57c7c
AM		 6148{"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6149{"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6150{"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6151{"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
066be9f7 6152
14b57c7c
AM		 6153{"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
6154{"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
066be9f7 6155
14b57c7c 6156{"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}},
5817ffd1 6157
14b57c7c
AM		 6158{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
6159{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
252b5132 6160
14b57c7c 6161{"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
a680de9a 6162{"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}},
702f0fb4 6163
14b57c7c 6164{"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}},
f5c120c5 6165
14b57c7c 6166{"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}},
252b5132 6167
14b57c7c
AM		 6168{"stfdpx", X(31,919), X_MASK, POWER6, POWER7, {FRSp, RA0, RB}},
6169{"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}},
6ba045b1 6170
14b57c7c
AM		 6171{"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}},
6172{"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}},
702f0fb4 6173
14b57c7c
AM		 6174{"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}},
6175{"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 6176
14b57c7c
AM		 6177{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
6178{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
6179{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
6180{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
702f0fb4 6181
14b57c7c 6182{"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}},
19a6653c 6183
14b57c7c 6184{"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 6185
14b57c7c 6186{"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}},
a5721ba2
AM		 6187{"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L2}},
6188{"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}},
85d4ac0b 6189
14b57c7c 6190{"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
6ba045b1 6191
14b57c7c
AM		 6192{"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6193{"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6194{"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6195{"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
066be9f7 6196
14b57c7c
AM		 6197{"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6198{"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
a680de9a 6199
14b57c7c 6200{"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}},
5817ffd1 6201
e0d602ec
BE		 6202{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
6203{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
14b57c7c 6204{"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
702f0fb4 6205
14b57c7c 6206{"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}},
252b5132 6207
14b57c7c
AM		 6208{"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}},
6209{"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}},
51b5d4a8 6210
14b57c7c 6211{"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}},
252b5132 6212
14b57c7c
AM		 6213{"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}},
6214{"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}},
252b5132 6215
14b57c7c
AM		 6216{"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}},
6217{"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}},
252b5132 6218
14b57c7c 6219{"stvflxl", X(31,965), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 6220
14b57c7c
AM		 6221{"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
6222{"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
43e65147 6223
14b57c7c
AM		 6224{"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6225{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
43e65147 6226
14b57c7c
AM		 6227{"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6228{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
252b5132 6229
14b57c7c 6230{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
a680de9a 6231{"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}},
9b4e5766 6232
9fe54b1c 6233{"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
14b57c7c
AM		 6234{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}},
6235{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}},
6236{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
418c1742 6237
14b57c7c 6238{"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}},
c4e676f1 6239
14b57c7c 6240{"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}},
252b5132 6241
14b57c7c 6242{"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}},
252b5132 6243
14b57c7c 6244{"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
702f0fb4 6245
14b57c7c
AM		 6246{"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}},
6247{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}},
252b5132 6248
14b57c7c 6249{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
19a6653c 6250
14b57c7c 6251{"stvswxl", X(31,997), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 6252
14b57c7c 6253{"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}},
252b5132 6254
14b57c7c
AM		 6255{"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}},
6256{"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}},
252b5132 6257
14b57c7c
AM		 6258{"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6259{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
43e65147 6260
14b57c7c
AM		 6261{"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6262{"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
418c1742 6263
14b57c7c 6264{"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
a680de9a 6265
14b57c7c 6266{"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, 0, {0}},
702f0fb4 6267
14b57c7c 6268{"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},
252b5132 6269
14b57c7c 6270{"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}},
418c1742 6271
14b57c7c
AM		 6272{"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
6273{"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
786e2c0f 6274
14b57c7c 6275{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
ede602d7 6276
14b57c7c 6277{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}},
252b5132 6278
14b57c7c
AM		 6279{"cctpl", 0x7c210b78, 0xffffffff, CELL, 0, {0}},
6280{"cctpm", 0x7c421378, 0xffffffff, CELL, 0, {0}},
6281{"cctph", 0x7c631b78, 0xffffffff, CELL, 0, {0}},
252b5132 6282
14b57c7c
AM		 6283{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6284{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6285{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}},
252b5132 6286
14b57c7c
AM		 6287{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, 0, {0}},
6288{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, 0, {0}},
6289{"db12cyc", 0x7fdef378, 0xffffffff, CELL, 0, {0}},
6290{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, 0, {0}},
252b5132 6291
14b57c7c
AM		 6292{"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
6293{"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
252b5132 6294
14b57c7c
AM		 6295{"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}},
6296{"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
252b5132 6297
14b57c7c 6298{"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
252b5132 6299
14b57c7c 6300{"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
252b5132 6301
14b57c7c
AM		 6302{"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
6303{"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
252b5132 6304
14b57c7c
AM		 6305{"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}},
6306{"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
252b5132 6307
14b57c7c 6308{"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
252b5132 6309
14b57c7c 6310{"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
252b5132 6311
14b57c7c 6312{"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
252b5132 6313
14b57c7c 6314{"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
252b5132 6315
14b57c7c 6316{"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
252b5132 6317
14b57c7c 6318{"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
252b5132 6319
14b57c7c 6320{"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
252b5132 6321
14b57c7c 6322{"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
252b5132 6323
14b57c7c
AM		 6324{"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}},
6325{"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
252b5132 6326
14b57c7c
AM		 6327{"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
6328{"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
252b5132 6329
14b57c7c 6330{"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
252b5132 6331
14b57c7c 6332{"lfsu", OP(49), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
252b5132 6333
14b57c7c 6334{"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
252b5132 6335
14b57c7c 6336{"lfdu", OP(51), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
252b5132 6337
14b57c7c 6338{"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
adadcc0c 6339
14b57c7c 6340{"stfsu", OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
252b5132 6341
14b57c7c 6342{"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
c3d65c1c 6343
14b57c7c 6344{"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
252b5132 6345
14b57c7c
AM		 6346{"lq", OP(56), OP_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}},
6347{"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6348{"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
418c1742 6349
14b57c7c
AM		 6350{"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
6351{"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
6352{"lfdp", OP(57), OP_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}},
6353{"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6354{"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
802a735e 6355
14b57c7c
AM		 6356{"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
6357{"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}},
6358{"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
702f0fb4 6359
14b57c7c
AM		 6360{"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6361{"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
252b5132 6362
14b57c7c
AM		 6363{"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
6364{"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
252b5132 6365
14b57c7c
AM		 6366{"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6367{"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
252b5132 6368
14b57c7c
AM		 6369{"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6370{"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
252b5132 6371
14b57c7c
AM		 6372{"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6373{"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
252b5132 6374
14b57c7c
AM		 6375{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
6376{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
252b5132 6377
14b57c7c
AM		 6378{"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6379{"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6380{"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6381{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
1ed8e1e4 6382
14b57c7c
AM		 6383{"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6384{"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
252b5132 6385
14b57c7c
AM		 6386{"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6387{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6388{"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6389{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
252b5132 6390
14b57c7c
AM		 6391{"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6392{"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6393
14b57c7c
AM		 6394{"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6395{"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6396
14b57c7c
AM		 6397{"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6398{"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
702f0fb4 6399
14b57c7c
AM		 6400{"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6401{"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
702f0fb4 6402
14b57c7c
AM		 6403{"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6404{"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
702f0fb4 6405
14b57c7c
AM		 6406{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
6407{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
702f0fb4 6408
14b57c7c
AM		 6409{"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6410{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
702f0fb4 6411
14b57c7c
AM		 6412{"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
6413{"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
702f0fb4 6414
14b57c7c
AM		 6415{"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6416{"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
702f0fb4 6417
14b57c7c
AM		 6418{"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6419{"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
702f0fb4 6420
14b57c7c 6421{"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
702f0fb4 6422
14b57c7c
AM		 6423{"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6424{"dtstdc", Z(59,194), Z_MASK, POWER6, PPCVLE, {BF, FRA, DCM}},
6425{"dtstdg", Z(59,226), Z_MASK, POWER6, PPCVLE, {BF, FRA, DGM}},
6426
6427{"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6428{"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6429
6430{"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6431{"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6432
6433{"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6434{"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6435
6436{"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
6437{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
6438
6439{"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6440{"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6441
6442{"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6443{"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6444
6445{"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6446{"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6447
6448{"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6449
6450{"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6451{"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}},
6452
6453{"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6454{"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6455
6456{"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6457{"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6458
6459{"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
6460{"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
6461
6462{"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6463{"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6464
6465{"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6466{"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6467
6468{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6469{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6470
6471{"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6472{"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6473{"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, SHW}},
6474{"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6475{"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6476{"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6477{"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}},
6478{"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6479{"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6480{"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S, DMEX}},
6481{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6482{"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6483{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6484{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, DM}},
6485{"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6486{"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6487{"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6488{"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6489{"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6490{"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6491{"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6492{"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6493{"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6494{"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6495{"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6496{"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6497{"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6498{"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6499{"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6500{"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6501{"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6502{"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6503{"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6504{"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6505{"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6506{"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6507{"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6508{"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6509{"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6510{"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6511{"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6512{"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6513{"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6514{"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6515{"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6516{"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCVLE, {BF, XA6, XB6}},
6517{"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6518{"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6519{"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6520{"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6521{"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6522{"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6523{"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6524{"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6525{"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6526{"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6527{"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6528{"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6529{"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6530{"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6531{"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6532{"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6533{"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6534{"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6535{"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6536{"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCVLE, {XT6, XB6, UIM}},
6537{"xxextractuw", XX2(60,165), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
6538{"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6539{"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6540{"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6541{"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6542{"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6543{"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6544{"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6545{"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6546{"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3, PPCVLE, {XT6, IMM8}},
6547{"xxinsertw", XX2(60,181), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
6548{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6549{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6550{"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6551{"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6552{"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6553{"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6554{"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6555{"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6556{"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6557{"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6558{"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6559{"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6560{"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6561{"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6562{"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6563{"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6564{"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6565{"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6566{"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6567{"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6568{"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6569{"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6570{"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6571{"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6572{"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6573{"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6574{"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6575{"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6576{"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6577{"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6578{"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6579{"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6580{"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6581{"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6582{"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6583{"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6584{"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6585{"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6586{"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6587{"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6588{"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6589{"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6590{"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6591{"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6592{"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
6593{"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6594{"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6595{"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6596{"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6597{"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6598{"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6599{"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6600{"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6601{"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6602{"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6603{"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6604{"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6605{"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6606{"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6607{"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6608{"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
6609{"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
6610{"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6611{"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6612{"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6613{"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6614{"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6615{"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6616{"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6617{"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
6618{"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6619{"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6620{"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6621{"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6622{"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6623{"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6624{"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6625{"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6626{"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6627{"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6628{"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6629{"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6630{"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6631{"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6632{"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6633{"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6634{"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6635{"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
6636{"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6637{"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6638{"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6639{"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6640{"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6641{"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6642{"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6643{"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6644{"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}},
6645{"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6646{"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6647{"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6648{"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6649{"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6650{"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6651{"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6652{"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6653{"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6654{"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6655{"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6656{"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6657{"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6658{"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6659{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6660{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6661{"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6662{"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6663{"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6664{"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
6665{"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6666{"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6667{"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6668{"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6669
6670{"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
6671{"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
6672
6673{"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}},
6674{"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}},
6675{"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
6676{"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
6677{"stfdp", OP(61), OP_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}},
6678{"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
6679{"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
6680
6681{"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}},
6682{"stdu", DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}},
6683{"stq", DSO(62,2), DS_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}},
6684
6685{"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
6686
6687{"daddq", XRC(63,2,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6688{"daddq.", XRC(63,2,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6689
6690{"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
6691{"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
6692
6693{"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6694{"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6695
6696{"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6697{"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6698
6699{"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
6700{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
6701
6702{"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6703{"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6704
6705{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6706{"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6707{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6708{"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6709
6710{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6711{"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6712{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6713{"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6714
6715{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6716{"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6717{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6718{"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6719
6720{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6721{"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6722{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6723{"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6724
6725{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6726{"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6727{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6728{"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6729
6730{"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
6731{"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
6732
6733{"fsel", A(63,23,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6734{"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6735
6736{"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6737{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6738{"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6739{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
1ed8e1e4 6740
14b57c7c
AM		 6741{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6742{"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
6743{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6744{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
252b5132 6745
14b57c7c
AM		 6746{"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6747{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6748{"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6749{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
252b5132 6750
14b57c7c
AM		 6751{"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6752{"fms", A(63,28,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6753{"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6754{"fms.", A(63,28,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6755
14b57c7c
AM		 6756{"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6757{"fma", A(63,29,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6758{"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6759{"fma.", A(63,29,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6760
14b57c7c
AM		 6761{"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6762{"fnms", A(63,30,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6763{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6764{"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6765
14b57c7c
AM		 6766{"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6767{"fnma", A(63,31,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6768{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6769{"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6770
14b57c7c 6771{"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
252b5132 6772
14b57c7c
AM		 6773{"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6774{"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
702f0fb4 6775
14b57c7c
AM		 6776{"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
6777{"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
702f0fb4 6778
14b57c7c
AM		 6779{"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6780{"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6781
14b57c7c 6782{"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
a680de9a 6783
14b57c7c
AM		 6784{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BT}},
6785{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BT}},
252b5132 6786
14b57c7c
AM		 6787{"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6788{"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
252b5132 6789
14b57c7c 6790{"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
252b5132 6791
14b57c7c
AM		 6792{"dscliq", ZRC(63,66,0), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6793{"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
702f0fb4 6794
14b57c7c
AM		 6795{"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
6796{"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
702f0fb4 6797
14b57c7c
AM		 6798{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BT}},
6799{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BT}},
252b5132 6800
14b57c7c
AM		 6801{"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6802{"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
252b5132 6803
14b57c7c
AM		 6804{"dscriq", ZRC(63,98,0), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6805{"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
702f0fb4 6806
14b57c7c
AM		 6807{"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6808{"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
702f0fb4 6809
14b57c7c 6810{"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6811
14b57c7c 6812{"ftdiv", X(63,128), XBF_MASK, POWER7, PPCVLE, {BF, FRA, FRB}},
066be9f7 6813
14b57c7c 6814{"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
702f0fb4 6815
14b57c7c 6816{"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
a680de9a 6817
14b57c7c
AM		 6818{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
6819{"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
6820{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
6821{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
252b5132 6822
14b57c7c
AM		 6823{"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6824{"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
252b5132 6825
14b57c7c
AM		 6826{"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6827{"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6828{"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6829{"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
066be9f7 6830
14b57c7c 6831{"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCVLE, {BF, FRB}},
066be9f7 6832
14b57c7c 6833{"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
a680de9a 6834
14b57c7c 6835{"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
a680de9a 6836
14b57c7c
AM		 6837{"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DCM}},
6838{"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DGM}},
702f0fb4 6839
14b57c7c
AM		 6840{"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6841{"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
702f0fb4 6842
14b57c7c
AM		 6843{"dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6844{"dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
702f0fb4 6845
14b57c7c
AM		 6846{"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6847{"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
252b5132 6848
14b57c7c
AM		 6849{"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6850{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
702f0fb4 6851
14b57c7c
AM		 6852{"ddedpdq", XRC(63,322,0), X_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
6853{"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
702f0fb4 6854
14b57c7c
AM		 6855{"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6856{"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
702f0fb4 6857
14b57c7c
AM		 6858{"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6859{"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6860
14b57c7c
AM		 6861{"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6862{"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
a680de9a 6863
14b57c7c
AM		 6864{"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6865{"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6866
14b57c7c
AM		 6867{"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6868{"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
a680de9a 6869
14b57c7c
AM		 6870{"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6871{"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6872
14b57c7c
AM		 6873{"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6874{"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
a680de9a 6875
14b57c7c
AM		 6876{"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6877{"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6878
14b57c7c
AM		 6879{"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6880{"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
ce7a772b 6881
14b57c7c
AM		 6882{"dsubq", XRC(63,514,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6883{"dsubq.", XRC(63,514,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
702f0fb4 6884
14b57c7c
AM		 6885{"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6886{"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6887
14b57c7c
AM		 6888{"ddivq", XRC(63,546,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6889{"ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
702f0fb4 6890
14b57c7c
AM		 6891{"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6892{"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6893
14b57c7c
AM		 6894{"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
6895{"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
252b5132 6896
6fd3a02d
PB		 6897{"mffsce", XMMF(63,583,0,1), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
6898{"mffscdrn", XMMF(63,583,2,4), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
6899{"mffscdrni", XMMF(63,583,2,5), XMMF_MASK|(3<<14), POWER9, PPCVLE, {FRT, DRM}},
6900{"mffscrn", XMMF(63,583,2,6), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
6901{"mffscrni", XMMF(63,583,2,7), XMMF_MASK|(7<<13), POWER9, PPCVLE, {FRT, RM}},
6902{"mffsl", XMMF(63,583,3,0), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
6903
14b57c7c 6904{"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
702f0fb4 6905
14b57c7c 6906{"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
a680de9a 6907
14b57c7c
AM		 6908{"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}},
6909{"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}},
a680de9a 6910
14b57c7c 6911{"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}},
702f0fb4 6912
14b57c7c
AM		 6913{"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
6914{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
6915{"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
6916{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
252b5132 6917
14b57c7c
AM		 6918{"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
6919{"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
702f0fb4 6920
14b57c7c
AM		 6921{"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6922{"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
702f0fb4 6923
14b57c7c
AM		 6924{"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6925{"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6926{"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6927{"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6928{"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6929{"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6930{"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
a680de9a 6931
14b57c7c
AM		 6932{"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6933{"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6934{"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6935{"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
252b5132 6936
14b57c7c
AM		 6937{"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6938{"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6939{"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6940{"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
252b5132 6941
14b57c7c
AM		 6942{"denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
6943{"denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
702f0fb4 6944
14b57c7c
AM		 6945{"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6946{"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6947{"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6948{"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6949{"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6950{"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6951{"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6952{"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6953{"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
a680de9a 6954
14b57c7c 6955{"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
c0637f3a 6956
14b57c7c
AM		 6957{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6958{"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6959{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6960{"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
252b5132 6961
14b57c7c
AM		 6962{"diexq", XRC(63,866,0), X_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
6963{"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
702f0fb4 6964
14b57c7c 6965{"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6966
14b57c7c
AM		 6967{"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6968{"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
066be9f7 6969
14b57c7c
AM		 6970{"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6971{"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
066be9f7 6972
14b57c7c 6973{"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
c0637f3a 6974
14b57c7c
AM		 6975{"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6976{"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
252b5132
RH		 6977};
6978
6979const int powerpc_num_opcodes =
6980 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
6981\f
b9c361e0
JL		 6982/* The VLE opcode table.
6983
6984 The format of this opcode table is the same as the main opcode table. */
6985
6986const struct powerpc_opcode vle_opcodes[] = {
14b57c7c
AM		 6987{"se_illegal", C(0), C_MASK, PPCVLE, 0, {}},
6988{"se_isync", C(1), C_MASK, PPCVLE, 0, {}},
6989{"se_sc", C(2), C_MASK, PPCVLE, 0, {}},
6990{"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, 0, {}},
6991{"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, 0, {}},
6992{"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, 0, {}},
6993{"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, 0, {}},
6994{"se_rfi", C(8), C_MASK, PPCVLE, 0, {}},
6995{"se_rfci", C(9), C_MASK, PPCVLE, 0, {}},
6996{"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}},
6997{"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}},
6998{"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}},
6999{"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}},
7000{"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}},
7001{"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, 0, {RX}},
7002{"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, 0, {RX}},
7003{"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, 0, {RX}},
7004{"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, 0, {RX}},
7005{"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, 0, {RX}},
7006{"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, 0, {RX}},
7007{"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, 0, {RX}},
7008{"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7009{"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}},
7010{"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}},
7011{"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7012{"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7013{"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7014{"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7015{"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7016{"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7017{"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7018{"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7019
7020{"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
dfdaec14 7021{"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
14b57c7c 7022{"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
dfdaec14 7023{"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
14b57c7c
AM		 7024{"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7025{"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7026{"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7027{"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7028{"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7029{"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7030{"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7031{"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7032{"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7033{"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7034{"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7035{"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7036{"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, 0, {0}},
7037{"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7038{"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7039{"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7040{"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7041{"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7042{"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7043{"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7044{"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7045{"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7046{"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7047{"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7048{"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7049{"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
dfdaec14
AJ		 7050{"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7051{"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7052{"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7053{"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7054{"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7055{"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7056{"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7057{"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7058{"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7059{"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
14b57c7c
AM		 7060{"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
7061{"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7062{"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}},
7063
7064{"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7065{"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7066{"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7067{"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7068{"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7069{"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7070{"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7071
7072{"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7073{"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7074{"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7075
7076{"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7077{"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7078{"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7079{"se_nop", SE_RR(17,0), 0xffff, PPCVLE, 0, {0}},
7080{"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7081{"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7082{"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7083{"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7084{"se_li", IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}},
7085
7086{"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7087{"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7088{"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7089{"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7090
7091{"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7092{"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7093{"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7094{"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7095{"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7096{"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7097{"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7098
7099{"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7100{"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7101{"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7102{"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7103{"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7104{"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
7105{"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
7106{"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
14b57c7c
AM		 7107{"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7108{"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
14b57c7c
AM		 7109{"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
7110{"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7111{"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
7112{"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7113{"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}},
7114{"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}},
7115{"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}},
7116{"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}},
7117{"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}},
7118{"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
7119{"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
7120{"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
7121{"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
7122{"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7123{"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7124{"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7125{"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7126{"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7127{"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7128{"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7129{"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7130{"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7131{"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7132{"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7133{"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7134{"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7135{"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7136{"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7137{"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7138{"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7139{"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7140{"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7141{"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7142{"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7143{"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7144{"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7145{"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7146{"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
7147{"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
7148
7149{"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7150{"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7151{"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7152{"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7153
7154{"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
7155{"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
7156{"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7157{"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7158{"e_crnot", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7159{"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7160{"e_crclr", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7161{"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7162{"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}},
7163{"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7164{"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7165
7166{"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7167
7168{"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
7169{"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
7170
7171{"e_crset", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7172{"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7173
7174{"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7175{"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7176
7177{"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7178
7179{"e_crmove", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7180{"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7181
7182{"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, 0, {RS}},
7183
7184{"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7185{"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7186
7187{"se_lbz", SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
7188
7189{"se_stb", SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
7190
7191{"se_lhz", SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
7192
7193{"se_sth", SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
7194
7195{"se_lwz", SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
7196
7197{"se_stw", SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
7198
7199{"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7200{"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7201{"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7202{"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7203{"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7204{"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7205{"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7206{"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
7207{"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7208{"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7209{"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7210{"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7211{"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7212{"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
7213{"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}},
7214{"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}},
7215{"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}},
b9c361e0
JL		 7216};
7217
7218const int vle_num_opcodes =
7219 sizeof (vle_opcodes) / sizeof (vle_opcodes[0]);
7220\f
252b5132
RH		 7221/* The macro table. This is only used by the assembler. */
7222
7223/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
7224 when x=0; 32-x when x is between 1 and 31; are negative if x is
7225 negative; and are 32 or more otherwise. This is what you want
7226 when, for instance, you are emulating a right shift by a
7227 rotate-left-and-mask, because the underlying instructions support
7228 shifts of size 0 but not shifts of size 32. By comparison, when
7229 extracting x bits from some word you want to use just 32-x, because
7230 the underlying instructions don't support extracting 0 bits but do
7231 support extracting the whole word (32 bits in this case). */
7232
7233const struct powerpc_macro powerpc_macros[] = {
de866fcc
AM		 7234{"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"},
7235{"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"},
bdc7fcfe
AM		 7236{"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
7237{"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
de866fcc
AM		 7238{"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"},
7239{"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
7240{"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
7241{"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
7242{"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"},
7243{"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"},
7244{"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
7245{"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
7246{"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"},
7247{"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"},
7248{"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"},
14b57c7c 7249{"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"},
de866fcc
AM		 7250
7251{"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
7252{"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
7253{"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7254{"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7255{"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7256{"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7257{"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7258{"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7259{"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7260{"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7261{"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
7262{"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
7263{"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
7264{"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
7265{"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7266{"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7267{"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7268{"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7269{"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
7270{"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
7271{"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
7272{"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
a4ebc835
AM		 7273
7274{"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"},
7275{"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7276{"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7277{"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7278{"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"},
7279{"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7280{"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"},
7281{"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7282{"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"},
7283{"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"},
7284{"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
252b5132
RH		 7285};
7286
7287const int powerpc_num_macros =
7288 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
GDB Binutils - Deliverables
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