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* remote.c (extended_remote_can_run): Delete.
[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c
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252b5132 1/* ppc-opc.c -- PowerPC opcode list
5e8cb021 2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
930bb4cf 3 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
252b5132
RH		 4 Written by Ian Lance Taylor, Cygnus Support
5
9b201bb5 6 This file is part of the GNU opcodes library.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
112290ab 18 You should have received a copy of the GNU General Public License
9b201bb5
NC		 19 along with this file; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132
RH		 22
23#include <stdio.h>
0d8dfecf 24#include "sysdep.h"
252b5132
RH		 25#include "opcode/ppc.h"
26#include "opintl.h"
27
28/* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
33 the .text section.
34
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
37 file. */
38\f
39/* Local insertion and extraction functions. */
40
fa452fa6
PB		 41static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
42static long extract_bat (unsigned long, ppc_cpu_t, int *);
43static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
44static long extract_bba (unsigned long, ppc_cpu_t, int *);
45static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
46static long extract_bdm (unsigned long, ppc_cpu_t, int *);
47static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
48static long extract_bdp (unsigned long, ppc_cpu_t, int *);
49static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
50static long extract_bo (unsigned long, ppc_cpu_t, int *);
51static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
52static long extract_boe (unsigned long, ppc_cpu_t, int *);
53static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
54static long extract_fxm (unsigned long, ppc_cpu_t, int *);
55static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
56static long extract_mbe (unsigned long, ppc_cpu_t, int *);
57static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
58static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
59static long extract_nb (unsigned long, ppc_cpu_t, int *);
60static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
61static long extract_nsi (unsigned long, ppc_cpu_t, int *);
62static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
63static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
64static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
65static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
66static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
67static long extract_rbs (unsigned long, ppc_cpu_t, int *);
68static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
69static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
70static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
71static long extract_spr (unsigned long, ppc_cpu_t, int *);
72static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
73static long extract_sprg (unsigned long, ppc_cpu_t, int *);
74static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
75static long extract_tbr (unsigned long, ppc_cpu_t, int *);
9b4e5766
PB		 76static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
77static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
78static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
79static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
80static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
81static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
82static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
83static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
252b5132
RH		 84\f
85/* The operands table.
86
717bbdf1 87 The fields are bitm, shift, insert, extract, flags.
252b5132
RH		 88
89 We used to put parens around the various additions, like the one
90 for BA just below. However, that caused trouble with feeble
91 compilers with a limit on depth of a parenthesized expression, like
92 (reportedly) the compiler in Microsoft Developer Studio 5. So we
93 omit the parens, since the macros are never used in a context where
94 the addition will be ambiguous. */
95
96const struct powerpc_operand powerpc_operands[] =
97{
98 /* The zero index is used to indicate the end of the list of
99 operands. */
100#define UNUSED 0
bbac1f2a 101 { 0, 0, NULL, NULL, 0 },
252b5132
RH		 102
103 /* The BA field in an XL form instruction. */
104#define BA UNUSED + 1
717bbdf1
AM		 105 /* The BI field in a B form or XL form instruction. */
106#define BI BA
107#define BI_MASK (0x1f << 16)
b84bf58a 108 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 109
110 /* The BA field in an XL form instruction when it must be the same
111 as the BT field in the same instruction. */
112#define BAT BA + 1
b84bf58a 113 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
252b5132
RH		 114
115 /* The BB field in an XL form instruction. */
116#define BB BAT + 1
117#define BB_MASK (0x1f << 11)
b84bf58a 118 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 119
120 /* The BB field in an XL form instruction when it must be the same
121 as the BA field in the same instruction. */
122#define BBA BB + 1
b84bf58a 123 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
252b5132
RH		 124
125 /* The BD field in a B form instruction. The lower two bits are
126 forced to zero. */
127#define BD BBA + 1
b84bf58a 128 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 129
130 /* The BD field in a B form instruction when absolute addressing is
131 used. */
132#define BDA BD + 1
b84bf58a 133 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 134
135 /* The BD field in a B form instruction when the - modifier is used.
136 This sets the y bit of the BO field appropriately. */
137#define BDM BDA + 1
b84bf58a 138 { 0xfffc, 0, insert_bdm, extract_bdm,
11b37b7b 139 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 140
141 /* The BD field in a B form instruction when the - modifier is used
142 and absolute address is used. */
143#define BDMA BDM + 1
b84bf58a 144 { 0xfffc, 0, insert_bdm, extract_bdm,
11b37b7b 145 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 146
147 /* The BD field in a B form instruction when the + modifier is used.
148 This sets the y bit of the BO field appropriately. */
149#define BDP BDMA + 1
b84bf58a 150 { 0xfffc, 0, insert_bdp, extract_bdp,
11b37b7b 151 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 152
153 /* The BD field in a B form instruction when the + modifier is used
154 and absolute addressing is used. */
155#define BDPA BDP + 1
b84bf58a 156 { 0xfffc, 0, insert_bdp, extract_bdp,
11b37b7b 157 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 158
159 /* The BF field in an X or XL form instruction. */
160#define BF BDPA + 1
717bbdf1
AM		 161 /* The CRFD field in an X form instruction. */
162#define CRFD BF
b84bf58a 163 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
252b5132 164
ea192fa3
PB		 165 /* The BF field in an X or XL form instruction. */
166#define BFF BF + 1
167 { 0x7, 23, NULL, NULL, 0 },
168
252b5132
RH		 169 /* An optional BF field. This is used for comparison instructions,
170 in which an omitted BF field is taken as zero. */
ea192fa3 171#define OBF BFF + 1
b84bf58a 172 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132
RH		 173
174 /* The BFA field in an X or XL form instruction. */
175#define BFA OBF + 1
b84bf58a 176 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
252b5132 177
252b5132
RH		 178 /* The BO field in a B form instruction. Certain values are
179 illegal. */
717bbdf1 180#define BO BFA + 1
252b5132 181#define BO_MASK (0x1f << 21)
b84bf58a 182 { 0x1f, 21, insert_bo, extract_bo, 0 },
252b5132
RH		 183
184 /* The BO field in a B form instruction when the + or - modifier is
185 used. This is like the BO field, but it must be even. */
186#define BOE BO + 1
b84bf58a 187 { 0x1e, 21, insert_boe, extract_boe, 0 },
252b5132 188
d0618d1c 189#define BH BOE + 1
b84bf58a 190 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
d0618d1c 191
252b5132 192 /* The BT field in an X or XL form instruction. */
d0618d1c 193#define BT BH + 1
b84bf58a 194 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 195
196 /* The condition register number portion of the BI field in a B form
197 or XL form instruction. This is used for the extended
198 conditional branch mnemonics, which set the lower two bits of the
199 BI field. This field is optional. */
200#define CR BT + 1
b84bf58a 201 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132 202
23976049
EZ		 203 /* The CRB field in an X form instruction. */
204#define CRB CR + 1
717bbdf1
AM		 205 /* The MB field in an M form instruction. */
206#define MB CRB
207#define MB_MASK (0x1f << 6)
b84bf58a 208 { 0x1f, 6, NULL, NULL, 0 },
23976049 209
23976049 210 /* The CRFS field in an X form instruction. */
717bbdf1 211#define CRFS CRB + 1
b84bf58a 212 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
23976049 213
418c1742 214 /* The CT field in an X form instruction. */
23976049 215#define CT CRFS + 1
717bbdf1
AM		 216 /* The MO field in an mbar instruction. */
217#define MO CT
b84bf58a 218 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
418c1742 219
252b5132
RH		 220 /* The D field in a D form instruction. This is a displacement off
221 a register, and implies that the next operand is a register in
222 parentheses. */
418c1742 223#define D CT + 1
b84bf58a 224 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
252b5132 225
adadcc0c
AM		 226 /* The DQ field in a DQ form instruction. This is like D, but the
227 lower four bits are forced to zero. */
2f3bb96a 228#define DQ D + 1
b84bf58a
AM		 229 { 0xfff0, 0, NULL, NULL,
230 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
adadcc0c 231
252b5132
RH		 232 /* The DS field in a DS form instruction. This is like D, but the
233 lower two bits are forced to zero. */
adadcc0c 234#define DS DQ + 1
b84bf58a
AM		 235 { 0xfffc, 0, NULL, NULL,
236 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
252b5132 237
19a6653c
AM		 238 /* The DUIS field in a XFX form instruction, 10 bits unsigned imediate */
239#define DUIS DS + 1
240 { 0x3ff, 11, NULL, NULL, 0 },
241
252b5132 242 /* The E field in a wrteei instruction. */
c3d65c1c 243 /* And the W bit in the pair singles instructions. */
19a6653c 244#define E DUIS + 1
c3d65c1c 245#define PSW E
b84bf58a 246 { 0x1, 15, NULL, NULL, 0 },
252b5132
RH		 247
248 /* The FL1 field in a POWER SC form instruction. */
249#define FL1 E + 1
717bbdf1
AM		 250 /* The U field in an X form instruction. */
251#define U FL1
b84bf58a 252 { 0xf, 12, NULL, NULL, 0 },
252b5132
RH		 253
254 /* The FL2 field in a POWER SC form instruction. */
255#define FL2 FL1 + 1
b84bf58a 256 { 0x7, 2, NULL, NULL, 0 },
252b5132
RH		 257
258 /* The FLM field in an XFL form instruction. */
259#define FLM FL2 + 1
b84bf58a 260 { 0xff, 17, NULL, NULL, 0 },
252b5132
RH		 261
262 /* The FRA field in an X or A form instruction. */
263#define FRA FLM + 1
264#define FRA_MASK (0x1f << 16)
b84bf58a 265 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 266
267 /* The FRB field in an X or A form instruction. */
268#define FRB FRA + 1
269#define FRB_MASK (0x1f << 11)
b84bf58a 270 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 271
272 /* The FRC field in an A form instruction. */
273#define FRC FRB + 1
274#define FRC_MASK (0x1f << 6)
b84bf58a 275 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 276
277 /* The FRS field in an X form instruction or the FRT field in a D, X
278 or A form instruction. */
279#define FRS FRC + 1
280#define FRT FRS
b84bf58a 281 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 282
283 /* The FXM field in an XFX instruction. */
284#define FXM FRS + 1
b84bf58a 285 { 0xff, 12, insert_fxm, extract_fxm, 0 },
c168870a
AM		 286
287 /* Power4 version for mfcr. */
288#define FXM4 FXM + 1
b84bf58a 289 { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
252b5132
RH		 290
291 /* The L field in a D or X form instruction. */
c168870a 292#define L FXM4 + 1
b84bf58a 293 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
252b5132 294
1ed8e1e4
AM		 295 /* The LEV field in a POWER SVC form instruction. */
296#define SVC_LEV L + 1
b84bf58a 297 { 0x7f, 5, NULL, NULL, 0 },
252b5132 298
1ed8e1e4
AM		 299 /* The LEV field in an SC form instruction. */
300#define LEV SVC_LEV + 1
b84bf58a 301 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
1ed8e1e4 302
252b5132
RH		 303 /* The LI field in an I form instruction. The lower two bits are
304 forced to zero. */
305#define LI LEV + 1
b84bf58a 306 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 307
308 /* The LI field in an I form instruction when used as an absolute
309 address. */
310#define LIA LI + 1
b84bf58a 311 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132 312
6ba045b1
AM		 313 /* The LS field in an X (sync) form instruction. */
314#define LS LIA + 1
b84bf58a 315 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
6ba045b1 316
252b5132 317 /* The ME field in an M form instruction. */
717bbdf1 318#define ME LS + 1
252b5132 319#define ME_MASK (0x1f << 1)
b84bf58a 320 { 0x1f, 1, NULL, NULL, 0 },
252b5132
RH		 321
322 /* The MB and ME fields in an M form instruction expressed a single
323 operand which is a bitmask indicating which bits to select. This
324 is a two operand form using PPC_OPERAND_NEXT. See the
325 description in opcode/ppc.h for what this means. */
326#define MBE ME + 1
b84bf58a 327 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
eb42fac1 328 { -1, 0, insert_mbe, extract_mbe, 0 },
252b5132
RH		 329
330 /* The MB or ME field in an MD or MDS form instruction. The high
331 bit is wrapped to the low end. */
332#define MB6 MBE + 2
333#define ME6 MB6
334#define MB6_MASK (0x3f << 5)
b84bf58a 335 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
252b5132
RH		 336
337 /* The NB field in an X form instruction. The value 32 is stored as
338 0. */
717bbdf1 339#define NB MB6 + 1
b84bf58a 340 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
252b5132
RH		 341
342 /* The NSI field in a D form instruction. This is the same as the
343 SI field, only negated. */
344#define NSI NB + 1
b84bf58a 345 { 0xffff, 0, insert_nsi, extract_nsi,
11b37b7b 346 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
252b5132 347
adadcc0c 348 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
914749f6 349#define RA NSI + 1
252b5132 350#define RA_MASK (0x1f << 16)
b84bf58a 351 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
252b5132 352
fdd12ef3
AM		 353 /* As above, but 0 in the RA field means zero, not r0. */
354#define RA0 RA + 1
b84bf58a 355 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
fdd12ef3
AM		 356
357 /* The RA field in the DQ form lq instruction, which has special
adadcc0c 358 value restrictions. */
fdd12ef3 359#define RAQ RA0 + 1
b84bf58a 360 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
adadcc0c 361
252b5132
RH		 362 /* The RA field in a D or X form instruction which is an updating
363 load, which means that the RA field may not be zero and may not
364 equal the RT field. */
adadcc0c 365#define RAL RAQ + 1
b84bf58a 366 { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
252b5132
RH		 367
368 /* The RA field in an lmw instruction, which has special value
369 restrictions. */
370#define RAM RAL + 1
b84bf58a 371 { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
252b5132
RH		 372
373 /* The RA field in a D or X form instruction which is an updating
374 store or an updating floating point load, which means that the RA
375 field may not be zero. */
376#define RAS RAM + 1
b84bf58a 377 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
252b5132 378
1f6c9eb0 379 /* The RA field of the tlbwe instruction, which is optional. */
fdd12ef3 380#define RAOPT RAS + 1
b84bf58a 381 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 382
252b5132 383 /* The RB field in an X, XO, M, or MDS form instruction. */
fdd12ef3 384#define RB RAOPT + 1
252b5132 385#define RB_MASK (0x1f << 11)
b84bf58a 386 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
252b5132
RH		 387
388 /* The RB field in an X form instruction when it must be the same as
389 the RS field in the instruction. This is used for extended
390 mnemonics like mr. */
391#define RBS RB + 1
b84bf58a 392 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
252b5132
RH		 393
394 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
395 instruction or the RT field in a D, DS, X, XFX or XO form
396 instruction. */
397#define RS RBS + 1
398#define RT RS
399#define RT_MASK (0x1f << 21)
b84bf58a 400 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
252b5132 401
717bbdf1
AM		 402 /* The RS and RT fields of the DS form stq instruction, which have
403 special value restrictions. */
adadcc0c 404#define RSQ RS + 1
717bbdf1 405#define RTQ RSQ
b84bf58a 406 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
adadcc0c 407
1f6c9eb0 408 /* The RS field of the tlbwe instruction, which is optional. */
717bbdf1 409#define RSO RSQ + 1
eed0d89a 410#define RTO RSO
b84bf58a 411 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 412
252b5132 413 /* The SH field in an X or M form instruction. */
1f6c9eb0 414#define SH RSO + 1
252b5132 415#define SH_MASK (0x1f << 11)
717bbdf1
AM		 416 /* The other UIMM field in a EVX form instruction. */
417#define EVUIMM SH
b84bf58a 418 { 0x1f, 11, NULL, NULL, 0 },
252b5132
RH		 419
420 /* The SH field in an MD form instruction. This is split. */
421#define SH6 SH + 1
422#define SH6_MASK ((0x1f << 11) | (1 << 1))
b84bf58a 423 { 0x3f, -1, insert_sh6, extract_sh6, 0 },
252b5132 424
1f6c9eb0
ZW		 425 /* The SH field of the tlbwe instruction, which is optional. */
426#define SHO SH6 + 1
b84bf58a 427 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
1f6c9eb0 428
252b5132 429 /* The SI field in a D form instruction. */
1f6c9eb0 430#define SI SHO + 1
b84bf58a 431 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
252b5132
RH		 432
433 /* The SI field in a D form instruction when we accept a wide range
434 of positive values. */
435#define SISIGNOPT SI + 1
b84bf58a 436 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
252b5132
RH		 437
438 /* The SPR field in an XFX form instruction. This is flipped--the
439 lower 5 bits are stored in the upper 5 and vice- versa. */
440#define SPR SISIGNOPT + 1
914749f6 441#define PMR SPR
252b5132 442#define SPR_MASK (0x3ff << 11)
b84bf58a 443 { 0x3ff, 11, insert_spr, extract_spr, 0 },
252b5132
RH		 444
445 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
446#define SPRBAT SPR + 1
447#define SPRBAT_MASK (0x3 << 17)
b84bf58a 448 { 0x3, 17, NULL, NULL, 0 },
252b5132
RH		 449
450 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
451#define SPRG SPRBAT + 1
b84bf58a 452 { 0x1f, 16, insert_sprg, extract_sprg, 0 },
252b5132
RH		 453
454 /* The SR field in an X form instruction. */
455#define SR SPRG + 1
b84bf58a 456 { 0xf, 16, NULL, NULL, 0 },
252b5132 457
f5c120c5
MG		 458 /* The STRM field in an X AltiVec form instruction. */
459#define STRM SR + 1
19a6653c
AM		 460 /* The T field in a tlbilx form instruction. */
461#define T STRM
b84bf58a 462 { 0x3, 21, NULL, NULL, 0 },
f5c120c5 463
252b5132 464 /* The SV field in a POWER SC form instruction. */
f5c120c5 465#define SV STRM + 1
b84bf58a 466 { 0x3fff, 2, NULL, NULL, 0 },
252b5132
RH		 467
468 /* The TBR field in an XFX form instruction. This is like the SPR
469 field, but it is optional. */
470#define TBR SV + 1
b84bf58a 471 { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
252b5132
RH		 472
473 /* The TO field in a D or X form instruction. */
474#define TO TBR + 1
19a6653c 475#define DUI TO
252b5132 476#define TO_MASK (0x1f << 21)
b84bf58a 477 { 0x1f, 21, NULL, NULL, 0 },
252b5132 478
252b5132 479 /* The UI field in a D form instruction. */
717bbdf1 480#define UI TO + 1
b84bf58a 481 { 0xffff, 0, NULL, NULL, 0 },
786e2c0f 482
112290ab 483 /* The VA field in a VA, VX or VXR form instruction. */
786e2c0f 484#define VA UI + 1
b84bf58a 485 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 486
112290ab 487 /* The VB field in a VA, VX or VXR form instruction. */
786e2c0f 488#define VB VA + 1
b84bf58a 489 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 490
112290ab 491 /* The VC field in a VA form instruction. */
786e2c0f 492#define VC VB + 1
b84bf58a 493 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 494
112290ab 495 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
786e2c0f
C		 496#define VD VC + 1
497#define VS VD
b84bf58a 498 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 499
8dbcd839 500 /* The SIMM field in a VX form instruction, and TE in Z form. */
786e2c0f 501#define SIMM VD + 1
8dbcd839 502#define TE SIMM
b84bf58a 503 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
786e2c0f 504
8dbcd839 505 /* The UIMM field in a VX form instruction. */
786e2c0f 506#define UIMM SIMM + 1
b84bf58a 507 { 0x1f, 16, NULL, NULL, 0 },
786e2c0f 508
112290ab 509 /* The SHB field in a VA form instruction. */
786e2c0f 510#define SHB UIMM + 1
b84bf58a 511 { 0xf, 6, NULL, NULL, 0 },
ff3a6ee3 512
112290ab 513 /* The other UIMM field in a half word EVX form instruction. */
717bbdf1 514#define EVUIMM_2 SHB + 1
b84bf58a 515 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
23976049 516
112290ab 517 /* The other UIMM field in a word EVX form instruction. */
23976049 518#define EVUIMM_4 EVUIMM_2 + 1
b84bf58a 519 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
23976049 520
112290ab 521 /* The other UIMM field in a double EVX form instruction. */
23976049 522#define EVUIMM_8 EVUIMM_4 + 1
b84bf58a 523 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
23976049 524
ff3a6ee3 525 /* The WS field. */
23976049 526#define WS EVUIMM_8 + 1
b84bf58a 527 { 0x7, 11, NULL, NULL, 0 },
ff3a6ee3 528
c3d65c1c
BE		 529 /* PowerPC paired singles extensions. */
530 /* W bit in the pair singles instructions for x type instructions. */
531#define PSWM WS + 1
532 { 0x1, 10, 0, 0, 0 },
533
534 /* IDX bits for quantization in the pair singles instructions. */
535#define PSQ PSWM + 1
536 { 0x7, 12, 0, 0, 0 },
537
538 /* IDX bits for quantization in the pair singles x-type instructions. */
539#define PSQM PSQ + 1
540 { 0x7, 7, 0, 0, 0 },
541
542 /* Smaller D field for quantization in the pair singles instructions. */
543#define PSD PSQM + 1
544 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
545
546#define A_L PSD + 1
ea192fa3 547#define W A_L
c3d65c1c 548#define MTMSRD_L W
b84bf58a 549 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
5ae2e65e 550
c3d65c1c 551#define RMC MTMSRD_L + 1
b84bf58a 552 { 0x3, 9, NULL, NULL, 0 },
702f0fb4
PB		 553
554#define R RMC + 1
b84bf58a 555 { 0x1, 16, NULL, NULL, 0 },
702f0fb4
PB		 556
557#define SP R + 1
b84bf58a 558 { 0x3, 19, NULL, NULL, 0 },
702f0fb4
PB		 559
560#define S SP + 1
b84bf58a 561 { 0x1, 20, NULL, NULL, 0 },
702f0fb4
PB		 562
563 /* SH field starting at bit position 16. */
564#define SH16 S + 1
0bbdef92
AM		 565 /* The DCM and DGM fields in a Z form instruction. */
566#define DCM SH16
567#define DGM DCM
b84bf58a 568 { 0x3f, 10, NULL, NULL, 0 },
702f0fb4 569
702f0fb4 570 /* The EH field in larx instruction. */
717bbdf1 571#define EH SH16 + 1
b84bf58a 572 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
ea192fa3
PB		 573
574 /* The L field in an mtfsf or XFL form instruction. */
575#define XFL_L EH + 1
576 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
081ba1b3
AM		 577
578 /* Xilinx APU related masks and macros */
579#define FCRT XFL_L + 1
580#define FCRT_MASK (0x1f << 21)
581 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
582
583 /* Xilinx FSL related masks and macros */
584#define FSL FCRT + 1
585#define FSL_MASK (0x1f << 11)
586 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
587
588 /* Xilinx UDI related masks and macros */
589#define URT FSL + 1
590 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
591
592#define URA URT + 1
593 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
594
595#define URB URA + 1
596 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
597
598#define URC URB + 1
599 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
600
9b4e5766
PB		 601 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
602#define XS6 URC + 1
603#define XT6 XS6
604 { 0x3f, -1, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
605
606 /* The XA field in an XX3 form instruction. This is split. */
607#define XA6 XT6 + 1
608 { 0x3f, -1, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
609
610 /* The XB field in an XX3 form instruction. This is split. */
611#define XB6 XA6 + 1
612 { 0x3f, -1, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
613
614 /* The XB field in an XX3 form instruction when it must be the same as
615 the XA field in the instruction. This is used in extended mnemonics
616 like xvmovdp. This is split. */
617#define XB6S XB6 + 1
618 { 0x3f, -1, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
619
620 /* The DM field in an XX3 form instruction. */
621#define DM XB6S + 1
622 { 0x3, 8, NULL, NULL, 0 },
252b5132
RH		 623};
624
b84bf58a
AM		 625const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
626 / sizeof (powerpc_operands[0]));
627
252b5132
RH		 628/* The functions used to insert and extract complicated operands. */
629
630/* The BA field in an XL form instruction when it must be the same as
631 the BT field in the same instruction. This operand is marked FAKE.
632 The insertion function just copies the BT field into the BA field,
633 and the extraction function just checks that the fields are the
634 same. */
635
252b5132 636static unsigned long
2fbfdc41
AM		 637insert_bat (unsigned long insn,
638 long value ATTRIBUTE_UNUSED,
fa452fa6 639 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 640 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 641{
642 return insn | (((insn >> 21) & 0x1f) << 16);
643}
644
645static long
2fbfdc41 646extract_bat (unsigned long insn,
fa452fa6 647 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 648 int *invalid)
252b5132 649{
8427c424 650 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
252b5132
RH		 651 *invalid = 1;
652 return 0;
653}
654
655/* The BB field in an XL form instruction when it must be the same as
656 the BA field in the same instruction. This operand is marked FAKE.
657 The insertion function just copies the BA field into the BB field,
658 and the extraction function just checks that the fields are the
659 same. */
660
252b5132 661static unsigned long
2fbfdc41
AM		 662insert_bba (unsigned long insn,
663 long value ATTRIBUTE_UNUSED,
fa452fa6 664 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 665 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 666{
667 return insn | (((insn >> 16) & 0x1f) << 11);
668}
669
670static long
2fbfdc41 671extract_bba (unsigned long insn,
fa452fa6 672 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 673 int *invalid)
252b5132 674{
8427c424 675 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 676 *invalid = 1;
677 return 0;
678}
679
252b5132
RH		 680/* The BD field in a B form instruction when the - modifier is used.
681 This modifier means that the branch is not expected to be taken.
94efba12
AM		 682 For chips built to versions of the architecture prior to version 2
683 (ie. not Power4 compatible), we set the y bit of the BO field to 1
684 if the offset is negative. When extracting, we require that the y
685 bit be 1 and that the offset be positive, since if the y bit is 0
686 we just want to print the normal form of the instruction.
687 Power4 compatible targets use two bits, "a", and "t", instead of
688 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
689 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
690 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
ba4e851b
AM		 691 for branch on CTR. We only handle the taken/not-taken hint here.
692 Note that we don't relax the conditions tested here when
693 disassembling with -Many because insns using extract_bdm and
694 extract_bdp always occur in pairs. One or the other will always
695 be valid. */
252b5132 696
252b5132 697static unsigned long
2fbfdc41
AM		 698insert_bdm (unsigned long insn,
699 long value,
fa452fa6 700 ppc_cpu_t dialect,
2fbfdc41 701 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 702{
94efba12 703 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 704 {
705 if ((value & 0x8000) != 0)
706 insn |= 1 << 21;
707 }
708 else
709 {
710 if ((insn & (0x14 << 21)) == (0x04 << 21))
711 insn |= 0x02 << 21;
712 else if ((insn & (0x14 << 21)) == (0x10 << 21))
713 insn |= 0x08 << 21;
714 }
252b5132
RH		 715 return insn | (value & 0xfffc);
716}
717
718static long
2fbfdc41 719extract_bdm (unsigned long insn,
fa452fa6 720 ppc_cpu_t dialect,
2fbfdc41 721 int *invalid)
252b5132 722{
8427c424 723 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e 724 {
8427c424
AM		 725 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
726 *invalid = 1;
802a735e 727 }
8427c424
AM		 728 else
729 {
730 if ((insn & (0x17 << 21)) != (0x06 << 21)
731 && (insn & (0x1d << 21)) != (0x18 << 21))
732 *invalid = 1;
733 }
734
802a735e 735 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 736}
737
738/* The BD field in a B form instruction when the + modifier is used.
739 This is like BDM, above, except that the branch is expected to be
740 taken. */
741
252b5132 742static unsigned long
2fbfdc41
AM		 743insert_bdp (unsigned long insn,
744 long value,
fa452fa6 745 ppc_cpu_t dialect,
2fbfdc41 746 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 747{
94efba12 748 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 749 {
750 if ((value & 0x8000) == 0)
751 insn |= 1 << 21;
752 }
753 else
754 {
755 if ((insn & (0x14 << 21)) == (0x04 << 21))
756 insn |= 0x03 << 21;
757 else if ((insn & (0x14 << 21)) == (0x10 << 21))
758 insn |= 0x09 << 21;
759 }
252b5132
RH		 760 return insn | (value & 0xfffc);
761}
762
763static long
2fbfdc41 764extract_bdp (unsigned long insn,
fa452fa6 765 ppc_cpu_t dialect,
2fbfdc41 766 int *invalid)
252b5132 767{
8427c424 768 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e 769 {
8427c424
AM		 770 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
771 *invalid = 1;
772 }
773 else
774 {
775 if ((insn & (0x17 << 21)) != (0x07 << 21)
776 && (insn & (0x1d << 21)) != (0x19 << 21))
777 *invalid = 1;
802a735e 778 }
8427c424 779
802a735e 780 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 781}
782
783/* Check for legal values of a BO field. */
784
785static int
fa452fa6 786valid_bo (long value, ppc_cpu_t dialect, int extract)
252b5132 787{
94efba12 788 if ((dialect & PPC_OPCODE_POWER4) == 0)
252b5132 789 {
ba4e851b 790 int valid;
802a735e
AM		 791 /* Certain encodings have bits that are required to be zero.
792 These are (z must be zero, y may be anything):
793 001zy
794 011zy
795 1z00y
796 1z01y
797 1z1zz
798 */
799 switch (value & 0x14)
800 {
801 default:
802 case 0:
ba4e851b
AM		 803 valid = 1;
804 break;
802a735e 805 case 0x4:
ba4e851b
AM		 806 valid = (value & 0x2) == 0;
807 break;
802a735e 808 case 0x10:
ba4e851b
AM		 809 valid = (value & 0x8) == 0;
810 break;
802a735e 811 case 0x14:
ba4e851b
AM		 812 valid = value == 0x14;
813 break;
802a735e 814 }
ba4e851b
AM		 815 /* When disassembling with -Many, accept power4 encodings too. */
816 if (valid
817 || (dialect & PPC_OPCODE_ANY) == 0
818 || !extract)
819 return valid;
802a735e 820 }
ba4e851b
AM		 821
822 /* Certain encodings have bits that are required to be zero.
823 These are (z must be zero, a & t may be anything):
824 0000z
825 0001z
826 0100z
827 0101z
828 001at
829 011at
830 1a00t
831 1a01t
832 1z1zz
833 */
834 if ((value & 0x14) == 0)
835 return (value & 0x1) == 0;
836 else if ((value & 0x14) == 0x14)
837 return value == 0x14;
802a735e 838 else
ba4e851b 839 return 1;
252b5132
RH		 840}
841
842/* The BO field in a B form instruction. Warn about attempts to set
843 the field to an illegal value. */
844
845static unsigned long
2fbfdc41
AM		 846insert_bo (unsigned long insn,
847 long value,
fa452fa6 848 ppc_cpu_t dialect,
2fbfdc41 849 const char **errmsg)
252b5132 850{
ba4e851b 851 if (!valid_bo (value, dialect, 0))
252b5132
RH		 852 *errmsg = _("invalid conditional option");
853 return insn | ((value & 0x1f) << 21);
854}
855
856static long
2fbfdc41 857extract_bo (unsigned long insn,
fa452fa6 858 ppc_cpu_t dialect,
2fbfdc41 859 int *invalid)
252b5132
RH		 860{
861 long value;
862
863 value = (insn >> 21) & 0x1f;
ba4e851b 864 if (!valid_bo (value, dialect, 1))
252b5132
RH		 865 *invalid = 1;
866 return value;
867}
868
869/* The BO field in a B form instruction when the + or - modifier is
870 used. This is like the BO field, but it must be even. When
871 extracting it, we force it to be even. */
872
873static unsigned long
2fbfdc41
AM		 874insert_boe (unsigned long insn,
875 long value,
fa452fa6 876 ppc_cpu_t dialect,
2fbfdc41 877 const char **errmsg)
252b5132 878{
ba4e851b 879 if (!valid_bo (value, dialect, 0))
8427c424
AM		 880 *errmsg = _("invalid conditional option");
881 else if ((value & 1) != 0)
882 *errmsg = _("attempt to set y bit when using + or - modifier");
883
252b5132
RH		 884 return insn | ((value & 0x1f) << 21);
885}
886
887static long
2fbfdc41 888extract_boe (unsigned long insn,
fa452fa6 889 ppc_cpu_t dialect,
2fbfdc41 890 int *invalid)
252b5132
RH		 891{
892 long value;
893
894 value = (insn >> 21) & 0x1f;
ba4e851b 895 if (!valid_bo (value, dialect, 1))
252b5132
RH		 896 *invalid = 1;
897 return value & 0x1e;
898}
899
2fbfdc41
AM		 900/* FXM mask in mfcr and mtcrf instructions. */
901
902static unsigned long
903insert_fxm (unsigned long insn,
904 long value,
fa452fa6 905 ppc_cpu_t dialect,
2fbfdc41 906 const char **errmsg)
c168870a 907{
98e69875
AM		 908 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
909 one bit of the mask field is set. */
910 if ((insn & (1 << 20)) != 0)
911 {
912 if (value == 0 || (value & -value) != value)
913 {
914 *errmsg = _("invalid mask field");
915 value = 0;
916 }
917 }
918
c168870a
AM		 919 /* If the optional field on mfcr is missing that means we want to use
920 the old form of the instruction that moves the whole cr. In that
921 case we'll have VALUE zero. There doesn't seem to be a way to
922 distinguish this from the case where someone writes mfcr %r3,0. */
98e69875 923 else if (value == 0)
c168870a
AM		 924 ;
925
926 /* If only one bit of the FXM field is set, we can use the new form
661bd698 927 of the instruction, which is faster. Unlike the Power4 branch hint
a30e9cc4
AM		 928 encoding, this is not backward compatible. Do not generate the
929 new form unless -mpower4 has been given, or -many and the two
930 operand form of mfcr was used. */
931 else if ((value & -value) == value
932 && ((dialect & PPC_OPCODE_POWER4) != 0
933 || ((dialect & PPC_OPCODE_ANY) != 0
934 && (insn & (0x3ff << 1)) == 19 << 1)))
c168870a
AM		 935 insn |= 1 << 20;
936
937 /* Any other value on mfcr is an error. */
938 else if ((insn & (0x3ff << 1)) == 19 << 1)
939 {
8427c424 940 *errmsg = _("ignoring invalid mfcr mask");
c168870a
AM		 941 value = 0;
942 }
943
944 return insn | ((value & 0xff) << 12);
945}
946
2fbfdc41
AM		 947static long
948extract_fxm (unsigned long insn,
fa452fa6 949 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 950 int *invalid)
c168870a
AM		 951{
952 long mask = (insn >> 12) & 0xff;
953
954 /* Is this a Power4 insn? */
955 if ((insn & (1 << 20)) != 0)
956 {
98e69875
AM		 957 /* Exactly one bit of MASK should be set. */
958 if (mask == 0 || (mask & -mask) != mask)
8427c424 959 *invalid = 1;
c168870a
AM		 960 }
961
962 /* Check that non-power4 form of mfcr has a zero MASK. */
963 else if ((insn & (0x3ff << 1)) == 19 << 1)
964 {
8427c424 965 if (mask != 0)
c168870a
AM		 966 *invalid = 1;
967 }
968
969 return mask;
970}
971
252b5132
RH		 972/* The MB and ME fields in an M form instruction expressed as a single
973 operand which is itself a bitmask. The extraction function always
974 marks it as invalid, since we never want to recognize an
975 instruction which uses a field of this type. */
976
977static unsigned long
2fbfdc41
AM		 978insert_mbe (unsigned long insn,
979 long value,
fa452fa6 980 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 981 const char **errmsg)
252b5132
RH		 982{
983 unsigned long uval, mask;
984 int mb, me, mx, count, last;
985
986 uval = value;
987
988 if (uval == 0)
989 {
8427c424 990 *errmsg = _("illegal bitmask");
252b5132
RH		 991 return insn;
992 }
993
994 mb = 0;
995 me = 32;
996 if ((uval & 1) != 0)
997 last = 1;
998 else
999 last = 0;
1000 count = 0;
1001
1002 /* mb: location of last 0->1 transition */
1003 /* me: location of last 1->0 transition */
1004 /* count: # transitions */
1005
0deb7ac5 1006 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
252b5132
RH		 1007 {
1008 if ((uval & mask) && !last)
1009 {
1010 ++count;
1011 mb = mx;
1012 last = 1;
1013 }
1014 else if (!(uval & mask) && last)
1015 {
1016 ++count;
1017 me = mx;
1018 last = 0;
1019 }
1020 }
1021 if (me == 0)
1022 me = 32;
1023
1024 if (count != 2 && (count != 0 || ! last))
8427c424 1025 *errmsg = _("illegal bitmask");
252b5132
RH		 1026
1027 return insn | (mb << 6) | ((me - 1) << 1);
1028}
1029
1030static long
2fbfdc41 1031extract_mbe (unsigned long insn,
fa452fa6 1032 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1033 int *invalid)
252b5132
RH		 1034{
1035 long ret;
1036 int mb, me;
1037 int i;
1038
8427c424 1039 *invalid = 1;
252b5132
RH		 1040
1041 mb = (insn >> 6) & 0x1f;
1042 me = (insn >> 1) & 0x1f;
1043 if (mb < me + 1)
1044 {
1045 ret = 0;
1046 for (i = mb; i <= me; i++)
0deb7ac5 1047 ret |= 1L << (31 - i);
252b5132
RH		 1048 }
1049 else if (mb == me + 1)
8427c424 1050 ret = ~0;
252b5132
RH		 1051 else /* (mb > me + 1) */
1052 {
2fbfdc41 1053 ret = ~0;
252b5132 1054 for (i = me + 1; i < mb; i++)
0deb7ac5 1055 ret &= ~(1L << (31 - i));
252b5132
RH		 1056 }
1057 return ret;
1058}
1059
1060/* The MB or ME field in an MD or MDS form instruction. The high bit
1061 is wrapped to the low end. */
1062
252b5132 1063static unsigned long
2fbfdc41
AM		 1064insert_mb6 (unsigned long insn,
1065 long value,
fa452fa6 1066 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1067 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1068{
1069 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1070}
1071
252b5132 1072static long
2fbfdc41 1073extract_mb6 (unsigned long insn,
fa452fa6 1074 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1075 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1076{
1077 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1078}
1079
1080/* The NB field in an X form instruction. The value 32 is stored as
1081 0. */
1082
252b5132 1083static long
2fbfdc41 1084extract_nb (unsigned long insn,
fa452fa6 1085 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1086 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1087{
1088 long ret;
1089
1090 ret = (insn >> 11) & 0x1f;
1091 if (ret == 0)
1092 ret = 32;
1093 return ret;
1094}
1095
1096/* The NSI field in a D form instruction. This is the same as the SI
1097 field, only negated. The extraction function always marks it as
1098 invalid, since we never want to recognize an instruction which uses
1099 a field of this type. */
1100
252b5132 1101static unsigned long
2fbfdc41
AM		 1102insert_nsi (unsigned long insn,
1103 long value,
fa452fa6 1104 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1105 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1106{
2fbfdc41 1107 return insn | (-value & 0xffff);
252b5132
RH		 1108}
1109
1110static long
2fbfdc41 1111extract_nsi (unsigned long insn,
fa452fa6 1112 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1113 int *invalid)
252b5132 1114{
8427c424 1115 *invalid = 1;
2fbfdc41 1116 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
252b5132
RH		 1117}
1118
1119/* The RA field in a D or X form instruction which is an updating
1120 load, which means that the RA field may not be zero and may not
1121 equal the RT field. */
1122
1123static unsigned long
2fbfdc41
AM		 1124insert_ral (unsigned long insn,
1125 long value,
fa452fa6 1126 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1127 const char **errmsg)
252b5132
RH		 1128{
1129 if (value == 0
1130 || (unsigned long) value == ((insn >> 21) & 0x1f))
1131 *errmsg = "invalid register operand when updating";
1132 return insn | ((value & 0x1f) << 16);
1133}
1134
1135/* The RA field in an lmw instruction, which has special value
1136 restrictions. */
1137
1138static unsigned long
2fbfdc41
AM		 1139insert_ram (unsigned long insn,
1140 long value,
fa452fa6 1141 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1142 const char **errmsg)
252b5132
RH		 1143{
1144 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1145 *errmsg = _("index register in load range");
1146 return insn | ((value & 0x1f) << 16);
1147}
1148
fdd12ef3 1149/* The RA field in the DQ form lq instruction, which has special
8427c424 1150 value restrictions. */
adadcc0c 1151
adadcc0c 1152static unsigned long
2fbfdc41
AM		 1153insert_raq (unsigned long insn,
1154 long value,
fa452fa6 1155 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1156 const char **errmsg)
adadcc0c
AM		 1157{
1158 long rtvalue = (insn & RT_MASK) >> 21;
1159
8427c424 1160 if (value == rtvalue)
adadcc0c
AM		 1161 *errmsg = _("source and target register operands must be different");
1162 return insn | ((value & 0x1f) << 16);
1163}
1164
252b5132
RH		 1165/* The RA field in a D or X form instruction which is an updating
1166 store or an updating floating point load, which means that the RA
1167 field may not be zero. */
1168
1169static unsigned long
2fbfdc41
AM		 1170insert_ras (unsigned long insn,
1171 long value,
fa452fa6 1172 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1173 const char **errmsg)
252b5132
RH		 1174{
1175 if (value == 0)
1176 *errmsg = _("invalid register operand when updating");
1177 return insn | ((value & 0x1f) << 16);
1178}
1179
1180/* The RB field in an X form instruction when it must be the same as
1181 the RS field in the instruction. This is used for extended
1182 mnemonics like mr. This operand is marked FAKE. The insertion
1183 function just copies the BT field into the BA field, and the
1184 extraction function just checks that the fields are the same. */
1185
252b5132 1186static unsigned long
2fbfdc41
AM		 1187insert_rbs (unsigned long insn,
1188 long value ATTRIBUTE_UNUSED,
fa452fa6 1189 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1190 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1191{
1192 return insn | (((insn >> 21) & 0x1f) << 11);
1193}
1194
1195static long
2fbfdc41 1196extract_rbs (unsigned long insn,
fa452fa6 1197 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1198 int *invalid)
252b5132 1199{
8427c424 1200 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 1201 *invalid = 1;
1202 return 0;
1203}
1204
1205/* The SH field in an MD form instruction. This is split. */
1206
252b5132 1207static unsigned long
2fbfdc41
AM		 1208insert_sh6 (unsigned long insn,
1209 long value,
fa452fa6 1210 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1211 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1212{
1213 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1214}
1215
252b5132 1216static long
2fbfdc41 1217extract_sh6 (unsigned long insn,
fa452fa6 1218 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1219 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1220{
1221 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1222}
1223
1224/* The SPR field in an XFX form instruction. This is flipped--the
1225 lower 5 bits are stored in the upper 5 and vice- versa. */
1226
1227static unsigned long
2fbfdc41
AM		 1228insert_spr (unsigned long insn,
1229 long value,
fa452fa6 1230 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1231 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1232{
1233 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1234}
1235
1236static long
2fbfdc41 1237extract_spr (unsigned long insn,
fa452fa6 1238 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1239 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1240{
1241 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1242}
1243
da99ee72
AM		 1244/* Some dialects have 8 SPRG registers instead of the standard 4. */
1245
1246static unsigned long
1247insert_sprg (unsigned long insn,
1248 long value,
fa452fa6 1249 ppc_cpu_t dialect,
da99ee72
AM		 1250 const char **errmsg)
1251{
da99ee72
AM		 1252 if (value > 7
1253 || (value > 3
081ba1b3 1254 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0))
da99ee72
AM		 1255 *errmsg = _("invalid sprg number");
1256
1257 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1258 user mode. Anything else must use spr 272..279. */
1259 if (value <= 3 || (insn & 0x100) != 0)
1260 value |= 0x10;
1261
1262 return insn | ((value & 0x17) << 16);
1263}
1264
1265static long
1266extract_sprg (unsigned long insn,
fa452fa6 1267 ppc_cpu_t dialect,
da99ee72
AM		 1268 int *invalid)
1269{
1270 unsigned long val = (insn >> 16) & 0x1f;
1271
1272 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1273 If not BOOKE or 405, then both use only 272..275. */
e1c93c69
AM		 1274 if ((val - 0x10 > 3 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0)
1275 || (val - 0x10 > 7 && (insn & 0x100) != 0)
1276 || val <= 3
1277 || (val & 8) != 0)
da99ee72
AM		 1278 *invalid = 1;
1279 return val & 7;
1280}
1281
252b5132
RH		 1282/* The TBR field in an XFX instruction. This is just like SPR, but it
1283 is optional. When TBR is omitted, it must be inserted as 268 (the
1284 magic number of the TB register). These functions treat 0
1285 (indicating an omitted optional operand) as 268. This means that
1286 ``mftb 4,0'' is not handled correctly. This does not matter very
1287 much, since the architecture manual does not define mftb as
1288 accepting any values other than 268 or 269. */
1289
1290#define TB (268)
1291
1292static unsigned long
2fbfdc41
AM		 1293insert_tbr (unsigned long insn,
1294 long value,
fa452fa6 1295 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1296 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1297{
1298 if (value == 0)
1299 value = TB;
1300 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1301}
1302
1303static long
2fbfdc41 1304extract_tbr (unsigned long insn,
fa452fa6 1305 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1306 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1307{
1308 long ret;
1309
1310 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1311 if (ret == TB)
1312 ret = 0;
1313 return ret;
1314}
9b4e5766
PB		 1315
1316/* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
1317
1318static unsigned long
1319insert_xt6 (unsigned long insn,
1320 long value,
1321 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1322 const char **errmsg ATTRIBUTE_UNUSED)
1323{
1324 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
1325}
1326
1327static long
1328extract_xt6 (unsigned long insn,
1329 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1330 int *invalid ATTRIBUTE_UNUSED)
1331{
1332 return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
1333}
1334
1335/* The XA field in an XX3 form instruction. This is split. */
1336
1337static unsigned long
1338insert_xa6 (unsigned long insn,
1339 long value,
1340 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1341 const char **errmsg ATTRIBUTE_UNUSED)
1342{
1343 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
1344}
1345
1346static long
1347extract_xa6 (unsigned long insn,
1348 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1349 int *invalid ATTRIBUTE_UNUSED)
1350{
1351 return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1352}
1353
1354/* The XB field in an XX3 form instruction. This is split. */
1355
1356static unsigned long
1357insert_xb6 (unsigned long insn,
1358 long value,
1359 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1360 const char **errmsg ATTRIBUTE_UNUSED)
1361{
1362 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1363}
1364
1365static long
1366extract_xb6 (unsigned long insn,
1367 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1368 int *invalid ATTRIBUTE_UNUSED)
1369{
1370 return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
1371}
1372
1373/* The XB field in an XX3 form instruction when it must be the same as
1374 the XA field in the instruction. This is used for extended
1375 mnemonics like xvmovdp. This operand is marked FAKE. The insertion
1376 function just copies the XA field into the XB field, and the
1377 extraction function just checks that the fields are the same. */
1378
1379static unsigned long
1380insert_xb6s (unsigned long insn,
1381 long value ATTRIBUTE_UNUSED,
1382 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1383 const char **errmsg ATTRIBUTE_UNUSED)
1384{
1385 return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
1386}
1387
1388static long
1389extract_xb6s (unsigned long insn,
1390 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1391 int *invalid)
1392{
1393 if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
1394 || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
1395 *invalid = 1;
1396 return 0;
1397}
252b5132
RH		 1398\f
1399/* Macros used to form opcodes. */
1400
1401/* The main opcode. */
1402#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1403#define OP_MASK OP (0x3f)
1404
1405/* The main opcode combined with a trap code in the TO field of a D
1406 form instruction. Used for extended mnemonics for the trap
1407 instructions. */
1408#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1409#define OPTO_MASK (OP_MASK | TO_MASK)
1410
1411/* The main opcode combined with a comparison size bit in the L field
1412 of a D form or X form instruction. Used for extended mnemonics for
1413 the comparison instructions. */
1414#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1415#define OPL_MASK OPL (0x3f,1)
1416
1417/* An A form instruction. */
1418#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1419#define A_MASK A (0x3f, 0x1f, 1)
1420
1421/* An A_MASK with the FRB field fixed. */
1422#define AFRB_MASK (A_MASK | FRB_MASK)
1423
1424/* An A_MASK with the FRC field fixed. */
1425#define AFRC_MASK (A_MASK | FRC_MASK)
1426
1427/* An A_MASK with the FRA and FRC fields fixed. */
1428#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1429
702f0fb4
PB		 1430/* An AFRAFRC_MASK, but with L bit clear. */
1431#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1432
252b5132
RH		 1433/* A B form instruction. */
1434#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1435#define B_MASK B (0x3f, 1, 1)
1436
1437/* A B form instruction setting the BO field. */
1438#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1439#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1440
1441/* A BBO_MASK with the y bit of the BO field removed. This permits
1442 matching a conditional branch regardless of the setting of the y
94efba12 1443 bit. Similarly for the 'at' bits used for power4 branch hints. */
de866fcc 1444#define Y_MASK (((unsigned long) 1) << 21)
802a735e
AM		 1445#define AT1_MASK (((unsigned long) 3) << 21)
1446#define AT2_MASK (((unsigned long) 9) << 21)
1447#define BBOY_MASK (BBO_MASK &~ Y_MASK)
1448#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
252b5132
RH		 1449
1450/* A B form instruction setting the BO field and the condition bits of
1451 the BI field. */
1452#define BBOCB(op, bo, cb, aa, lk) \
1453 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1454#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1455
1456/* A BBOCB_MASK with the y bit of the BO field removed. */
1457#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
802a735e
AM		 1458#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1459#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
252b5132
RH		 1460
1461/* A BBOYCB_MASK in which the BI field is fixed. */
1462#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
802a735e 1463#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
252b5132 1464
23976049
EZ		 1465/* An Context form instruction. */
1466#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
fdd12ef3 1467#define CTX_MASK CTX(0x3f, 0x7)
23976049
EZ		 1468
1469/* An User Context form instruction. */
1470#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
fdd12ef3 1471#define UCTX_MASK UCTX(0x3f, 0x1f)
23976049 1472
252b5132
RH		 1473/* The main opcode mask with the RA field clear. */
1474#define DRA_MASK (OP_MASK | RA_MASK)
1475
1476/* A DS form instruction. */
1477#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1478#define DS_MASK DSO (0x3f, 3)
1479
23976049
EZ		 1480/* An EVSEL form instruction. */
1481#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1482#define EVSEL_MASK EVSEL(0x3f, 0xff)
1483
252b5132
RH		 1484/* An M form instruction. */
1485#define M(op, rc) (OP (op) | ((rc) & 1))
1486#define M_MASK M (0x3f, 1)
1487
1488/* An M form instruction with the ME field specified. */
1489#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1490
1491/* An M_MASK with the MB and ME fields fixed. */
1492#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1493
1494/* An M_MASK with the SH and ME fields fixed. */
1495#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1496
1497/* An MD form instruction. */
1498#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1499#define MD_MASK MD (0x3f, 0x7, 1)
1500
1501/* An MD_MASK with the MB field fixed. */
1502#define MDMB_MASK (MD_MASK | MB6_MASK)
1503
1504/* An MD_MASK with the SH field fixed. */
1505#define MDSH_MASK (MD_MASK | SH6_MASK)
1506
1507/* An MDS form instruction. */
1508#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1509#define MDS_MASK MDS (0x3f, 0xf, 1)
1510
1511/* An MDS_MASK with the MB field fixed. */
1512#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1513
1514/* An SC form instruction. */
1515#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1516#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1517
112290ab 1518/* An VX form instruction. */
786e2c0f
C		 1519#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1520
112290ab 1521/* The mask for an VX form instruction. */
786e2c0f
C		 1522#define VX_MASK VX(0x3f, 0x7ff)
1523
112290ab 1524/* An VA form instruction. */
2613489e 1525#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
786e2c0f 1526
112290ab 1527/* The mask for an VA form instruction. */
2613489e 1528#define VXA_MASK VXA(0x3f, 0x3f)
786e2c0f 1529
112290ab 1530/* An VXR form instruction. */
786e2c0f
C		 1531#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1532
112290ab 1533/* The mask for a VXR form instruction. */
786e2c0f
C		 1534#define VXR_MASK VXR(0x3f, 0x3ff, 1)
1535
252b5132
RH		 1536/* An X form instruction. */
1537#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1538
9b4e5766
PB		 1539/* An XX3 form instruction. */
1540#define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
1541
1542#define XX3DM(op, xop, dm) (XX3 (op, ((unsigned long)(xop) & 0x1f)) \
1543 | ((((unsigned long)(dm)) & 0x3) << 8))
1544
702f0fb4
PB		 1545/* A Z form instruction. */
1546#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1547
252b5132
RH		 1548/* An X form instruction with the RC bit specified. */
1549#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1550
702f0fb4
PB		 1551/* A Z form instruction with the RC bit specified. */
1552#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1553
252b5132
RH		 1554/* The mask for an X form instruction. */
1555#define X_MASK XRC (0x3f, 0x3ff, 1)
1556
9b4e5766
PB		 1557/* The mask for an XX1 form instruction. */
1558#define XX1_MASK X (0x3f, 0x3ff)
1559
1560/* The mask for an XX3 form instruction. */
1561#define XX3_MASK XX3 (0x3f, 0xff)
1562
1563/* The mask for an XX3 form instruction with the DM bits specified. */
1564#define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
1565
702f0fb4
PB		 1566/* The mask for a Z form instruction. */
1567#define Z_MASK ZRC (0x3f, 0x1ff, 1)
0bbdef92 1568#define Z2_MASK ZRC (0x3f, 0xff, 1)
702f0fb4 1569
252b5132
RH		 1570/* An X_MASK with the RA field fixed. */
1571#define XRA_MASK (X_MASK | RA_MASK)
1572
ea192fa3
PB		 1573/* An XRA_MASK with the W field clear. */
1574#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
1575
252b5132
RH		 1576/* An X_MASK with the RB field fixed. */
1577#define XRB_MASK (X_MASK | RB_MASK)
1578
1579/* An X_MASK with the RT field fixed. */
1580#define XRT_MASK (X_MASK | RT_MASK)
1581
702f0fb4
PB		 1582/* An XRT_MASK mask with the L bits clear. */
1583#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1584
252b5132
RH		 1585/* An X_MASK with the RA and RB fields fixed. */
1586#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1587
112290ab 1588/* An XRARB_MASK, but with the L bit clear. */
5ae2e65e
AM		 1589#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1590
252b5132
RH		 1591/* An X_MASK with the RT and RA fields fixed. */
1592#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1593
98acc1c5
AM		 1594/* An XRTRA_MASK, but with L bit clear. */
1595#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1596
f3806e43
BE		 1597/* An X form instruction with the L bit specified. */
1598#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
252b5132 1599
19a6653c
AM		 1600/* An X form instruction with RT fields specified */
1601#define XRT(op, xop, rt) (X ((op), (xop)) \
1602 | ((((unsigned long)(rt)) & 0x1f) << 21))
1603
1604/* An X form instruction with RT and RA fields specified */
1605#define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
1606 | ((((unsigned long)(rt)) & 0x1f) << 21) \
1607 | ((((unsigned long)(ra)) & 0x1f) << 16))
1608
252b5132
RH		 1609/* The mask for an X form comparison instruction. */
1610#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1611
520ceea4
BE		 1612/* The mask for an X form comparison instruction with the L field
1613 fixed. */
1614#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
252b5132
RH		 1615
1616/* An X form trap instruction with the TO field specified. */
1617#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1618#define XTO_MASK (X_MASK | TO_MASK)
1619
e0c21649
GK		 1620/* An X form tlb instruction with the SH field specified. */
1621#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1622#define XTLB_MASK (X_MASK | SH_MASK)
1623
6ba045b1
AM		 1624/* An X form sync instruction. */
1625#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1626
1627/* An X form sync instruction with everything filled in except the LS field. */
1628#define XSYNC_MASK (0xff9fffff)
1629
702f0fb4
PB		 1630/* An X_MASK, but with the EH bit clear. */
1631#define XEH_MASK (X_MASK & ~((unsigned long )1))
1632
f5c120c5
MG		 1633/* An X form AltiVec dss instruction. */
1634#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1635#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1636
252b5132
RH		 1637/* An XFL form instruction. */
1638#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
ea192fa3 1639#define XFL_MASK XFL (0x3f, 0x3ff, 1)
252b5132 1640
23976049 1641/* An X form isel instruction. */
de866fcc
AM		 1642#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1643#define XISEL_MASK XISEL(0x3f, 0x1f)
23976049 1644
252b5132
RH		 1645/* An XL form instruction with the LK field set to 0. */
1646#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1647
1648/* An XL form instruction which uses the LK field. */
1649#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1650
1651/* The mask for an XL form instruction. */
1652#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1653
1654/* An XL form instruction which explicitly sets the BO field. */
1655#define XLO(op, bo, xop, lk) \
1656 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1657#define XLO_MASK (XL_MASK | BO_MASK)
1658
1659/* An XL form instruction which explicitly sets the y bit of the BO
1660 field. */
1661#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1662#define XLYLK_MASK (XL_MASK | Y_MASK)
1663
1664/* An XL form instruction which sets the BO field and the condition
1665 bits of the BI field. */
1666#define XLOCB(op, bo, cb, xop, lk) \
1667 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1668#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1669
1670/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1671#define XLBB_MASK (XL_MASK | BB_MASK)
1672#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1673#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1674
d0618d1c
AM		 1675/* A mask for branch instructions using the BH field. */
1676#define XLBH_MASK (XL_MASK | (0x1c << 11))
1677
252b5132
RH		 1678/* An XL_MASK with the BO and BB fields fixed. */
1679#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1680
1681/* An XL_MASK with the BO, BI and BB fields fixed. */
1682#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1683
1684/* An XO form instruction. */
1685#define XO(op, xop, oe, rc) \
1686 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1687#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1688
1689/* An XO_MASK with the RB field fixed. */
1690#define XORB_MASK (XO_MASK | RB_MASK)
1691
c3d65c1c
BE		 1692/* An XOPS form instruction for paired singles. */
1693#define XOPS(op, xop, rc) \
1694 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1695#define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
1696
1697
252b5132
RH		 1698/* An XS form instruction. */
1699#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1700#define XS_MASK XS (0x3f, 0x1ff, 1)
1701
1702/* A mask for the FXM version of an XFX form instruction. */
98e69875 1703#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
252b5132
RH		 1704
1705/* An XFX form instruction with the FXM field filled in. */
98e69875
AM		 1706#define XFXM(op, xop, fxm, p4) \
1707 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1708 | ((unsigned long)(p4) << 20))
252b5132
RH		 1709
1710/* An XFX form instruction with the SPR field filled in. */
1711#define XSPR(op, xop, spr) \
1712 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1713#define XSPR_MASK (X_MASK | SPR_MASK)
1714
1715/* An XFX form instruction with the SPR field filled in except for the
1716 SPRBAT field. */
1717#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1718
1719/* An XFX form instruction with the SPR field filled in except for the
1720 SPRG field. */
b84bf58a 1721#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
252b5132
RH		 1722
1723/* An X form instruction with everything filled in except the E field. */
1724#define XE_MASK (0xffff7fff)
1725
23976049
EZ		 1726/* An X form user context instruction. */
1727#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1728#define XUC_MASK XUC(0x3f, 0x1f)
1729
c3d65c1c
BE		 1730/* An XW form instruction. */
1731#define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
1732/* The mask for a G form instruction. rc not supported at present. */
1733#define XW_MASK XW (0x3f, 0x3f, 0)
1734
081ba1b3
AM		 1735/* An APU form instruction. */
1736#define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
1737
1738/* The mask for an APU form instruction. */
1739#define APU_MASK APU (0x3f, 0x3ff, 1)
1740#define APU_RT_MASK (APU_MASK | RT_MASK)
1741#define APU_RA_MASK (APU_MASK | RA_MASK)
1742
252b5132
RH		 1743/* The BO encodings used in extended conditional branch mnemonics. */
1744#define BODNZF (0x0)
1745#define BODNZFP (0x1)
1746#define BODZF (0x2)
1747#define BODZFP (0x3)
252b5132
RH		 1748#define BODNZT (0x8)
1749#define BODNZTP (0x9)
1750#define BODZT (0xa)
1751#define BODZTP (0xb)
802a735e
AM		 1752
1753#define BOF (0x4)
1754#define BOFP (0x5)
94efba12
AM		 1755#define BOFM4 (0x6)
1756#define BOFP4 (0x7)
252b5132
RH		 1757#define BOT (0xc)
1758#define BOTP (0xd)
94efba12
AM		 1759#define BOTM4 (0xe)
1760#define BOTP4 (0xf)
802a735e 1761
252b5132
RH		 1762#define BODNZ (0x10)
1763#define BODNZP (0x11)
1764#define BODZ (0x12)
1765#define BODZP (0x13)
94efba12
AM		 1766#define BODNZM4 (0x18)
1767#define BODNZP4 (0x19)
1768#define BODZM4 (0x1a)
1769#define BODZP4 (0x1b)
802a735e 1770
252b5132
RH		 1771#define BOU (0x14)
1772
1773/* The BI condition bit encodings used in extended conditional branch
1774 mnemonics. */
1775#define CBLT (0)
1776#define CBGT (1)
1777#define CBEQ (2)
1778#define CBSO (3)
1779
1780/* The TO encodings used in extended trap mnemonics. */
1781#define TOLGT (0x1)
1782#define TOLLT (0x2)
1783#define TOEQ (0x4)
1784#define TOLGE (0x5)
1785#define TOLNL (0x5)
1786#define TOLLE (0x6)
1787#define TOLNG (0x6)
1788#define TOGT (0x8)
1789#define TOGE (0xc)
1790#define TONL (0xc)
1791#define TOLT (0x10)
1792#define TOLE (0x14)
1793#define TONG (0x14)
1794#define TONE (0x18)
1795#define TOU (0x1f)
1796\f
1797/* Smaller names for the flags so each entry in the opcodes table will
1798 fit on a single line. */
1cb0a767 1799#define PPCNONE 0
252b5132 1800#undef PPC
de866fcc 1801#define PPC PPC_OPCODE_PPC
661bd698 1802#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
661bd698 1803#define POWER4 PPC_OPCODE_POWER4
1ed8e1e4 1804#define POWER5 PPC_OPCODE_POWER5
702f0fb4 1805#define POWER6 PPC_OPCODE_POWER6
ede602d7 1806#define CELL PPC_OPCODE_CELL
de866fcc
AM		 1807#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1808#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
418c1742 1809#define PPC403 PPC_OPCODE_403
081ba1b3 1810#define PPC405 PPC_OPCODE_405
7d5b217e 1811#define PPC440 PPC_OPCODE_440
c8187e15 1812#define PPC464 PPC440
252b5132 1813#define PPC750 PPC
33e8d5ac 1814#define PPC7450 PPC
252b5132 1815#define PPC860 PPC
c3d65c1c 1816#define PPCPS PPC_OPCODE_PPCPS
a404d431 1817#define PPCVEC PPC_OPCODE_ALTIVEC
9b4e5766 1818#define PPCVSX PPC_OPCODE_VSX
de866fcc
AM		 1819#define POWER PPC_OPCODE_POWER
1820#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1821#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1822#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1823#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1824#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1825#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
661bd698 1826#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
de866fcc
AM		 1827#define MFDEC1 PPC_OPCODE_POWER
1828#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
418c1742 1829#define BOOKE PPC_OPCODE_BOOKE
de866fcc 1830#define CLASSIC PPC_OPCODE_CLASSIC
36ae0db3 1831#define PPCE300 PPC_OPCODE_E300
23976049 1832#define PPCSPE PPC_OPCODE_SPE
de866fcc 1833#define PPCISEL PPC_OPCODE_ISEL
23976049 1834#define PPCEFS PPC_OPCODE_EFS
de866fcc 1835#define PPCBRLK PPC_OPCODE_BRLOCK
23976049 1836#define PPCPMR PPC_OPCODE_PMR
de866fcc 1837#define PPCCHLK PPC_OPCODE_CACHELCK
23976049 1838#define PPCRFMCI PPC_OPCODE_RFMCI
19a6653c 1839#define E500MC PPC_OPCODE_E500MC
252b5132
RH		 1840\f
1841/* The opcode table.
1842
1843 The format of the opcode table is:
1844
de866fcc 1845 NAME OPCODE MASK FLAGS {OPERANDS}
252b5132
RH		 1846
1847 NAME is the name of the instruction.
1848 OPCODE is the instruction opcode.
1849 MASK is the opcode mask; this is used to tell the disassembler
1850 which bits in the actual opcode must match OPCODE.
1851 FLAGS are flags indicated what processors support the instruction.
1852 OPERANDS is the list of operands.
1853
1854 The disassembler reads the table in order and prints the first
1855 instruction which matches, so this table is sorted to put more
de866fcc
AM		 1856 specific instructions before more general instructions.
1857
1858 This table must be sorted by major opcode. Please try to keep it
1859 vaguely sorted within major opcode too, except of course where
1860 constrained otherwise by disassembler operation. */
252b5132
RH		 1861
1862const struct powerpc_opcode powerpc_opcodes[] = {
1cb0a767
PB		 1863{"attn", X(0,256), X_MASK, POWER4, PPCNONE, {0}},
1864{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
1865{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
1866{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
1867{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
1868{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
1869{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
1870{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
1871{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
1872{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
1873{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
1874{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
1875{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
1876{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
1877{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
1878{"tdi", OP(2), OP_MASK, PPC64, PPCNONE, {TO, RA, SI}},
1879
1880{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
1881{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
1882{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
1883{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
1884{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
1885{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
1886{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
1887{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
1888{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
1889{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
1890{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
1891{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
1892{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
1893{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
1894{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
1895{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
1896{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
1897{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
1898{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
1899{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
1900{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
1901{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
1902{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
1903{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
1904{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
1905{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
1906{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
1907{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
1908{"twi", OP(3), OP_MASK, PPCCOM, PPCNONE, {TO, RA, SI}},
1909{"ti", OP(3), OP_MASK, PWRCOM, PPCNONE, {TO, RA, SI}},
1910
1911{"ps_cmpu0", X (4, 0), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
1912{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
1913{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
1914{"vrlb", VX (4, 4), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
1915{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
1916{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
1917{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
1918{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}},
1919{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
1920{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, PPCNONE, {FRS,RA,RB,PSWM,PSQM}},
1921{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
1922{"mulhhwu", XRC(4, 8,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
1923{"mulhhwu.", XRC(4, 8,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
1924{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
1925{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
1926{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
1927{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
1928{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
1929{"machhwu", XO (4, 12,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
1930{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
1931{"machhwu.", XO (4, 12,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
1932{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
1933{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
1934{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
1935{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
1936{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
1937{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
1938{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
1939{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
1940{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
1941{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
1942{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
1943{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
1944{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
1945{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
1946{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
1947{"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
1948{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
1949{"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
1950{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
1951{"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
1952{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
1953{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
1954{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
1955{"vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, SHB}},
1956{"ps_sel", A (4, 23,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
1957{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VC, VB}},
1958{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
1959{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VC, VB}},
1960{"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
1961{"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
1962{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
1963{"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
1964{"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
1965{"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
1966{"ps_msub", A (4, 28,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
1967{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
1968{"ps_madd", A (4, 29,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
1969{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
1970{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
1971{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
1972{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
1973{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
1974{"ps_cmpo0", X (4, 32), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
1975{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
1976{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
1977{"vrlh", VX (4, 68), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
1978{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
1979{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
1980{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
1981{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}},
1982{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
1983{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, PPCNONE, {FRS,RA,RB,PSWM,PSQM}},
1984{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
1985{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
1986{"mulhhw", XRC(4, 40,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
1987{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
1988{"mulhhw.", XRC(4, 40,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
1989{"machhw", XO (4, 44,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
1990{"machhw.", XO (4, 44,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
1991{"nmachhw", XO (4, 46,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
1992{"nmachhw.", XO (4, 46,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
1993{"ps_cmpu1", X (4, 64), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
1994{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
1995{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
1996{"vrlw", VX (4, 132), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
1997{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
1998{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
1999{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2000{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2001{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2002{"machhwsu", XO (4, 76,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2003{"machhwsu.", XO (4, 76,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2004{"ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
2005{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2006{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2007{"machhws", XO (4, 108,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2008{"machhws.", XO (4, 108,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2009{"nmachhws", XO (4, 110,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2010{"nmachhws.", XO (4, 110,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2011{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2012{"vslb", VX (4, 260), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2013{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2014{"vrefp", VX (4, 266), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2015{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2016{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2017{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2018{"mulchwu", XRC(4, 136,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2019{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2020{"mulchwu.", XRC(4, 136,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2021{"macchwu", XO (4, 140,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2022{"macchwu.", XO (4, 140,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2023{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2024{"vslh", VX (4, 324), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2025{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2026{"vrsqrtefp", VX (4, 330), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2027{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2028{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2029{"mulchw", XRC(4, 168,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2030{"mulchw.", XRC(4, 168,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2031{"macchw", XO (4, 172,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2032{"macchw.", XO (4, 172,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2033{"nmacchw", XO (4, 174,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2034{"nmacchw.", XO (4, 174,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2035{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2036{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2037{"vslw", VX (4, 388), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2038{"vexptefp", VX (4, 394), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2039{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2040{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2041{"macchwsu", XO (4, 204,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2042{"macchwsu.", XO (4, 204,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2043{"vsl", VX (4, 452), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2044{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2045{"vlogefp", VX (4, 458), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2046{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2047{"macchws", XO (4, 236,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2048{"macchws.", XO (4, 236,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2049{"nmacchws", XO (4, 238,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2050{"nmacchws.", XO (4, 238,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2051{"evaddw", VX (4, 512), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2052{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2053{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, PPCNONE, {RS, RB, UIMM}},
2054{"vminub", VX (4, 514), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2055{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2056{"evsubw", VX (4, 516), VX_MASK, PPCSPE, PPCNONE, {RS, RB, RA}},
2057{"vsrb", VX (4, 516), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2058{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, PPCNONE, {RS, UIMM, RB}},
2059{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, PPCNONE, {RS, RB, UIMM}},
2060{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2061{"evabs", VX (4, 520), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2062{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2063{"evneg", VX (4, 521), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2064{"evextsb", VX (4, 522), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2065{"vrfin", VX (4, 522), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2066{"evextsh", VX (4, 523), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2067{"evrndw", VX (4, 524), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2068{"vspltb", VX (4, 524), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
2069{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2070{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2071{"vupkhsb", VX (4, 526), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2072{"brinc", VX (4, 527), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2073{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2074{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2075{"evand", VX (4, 529), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2076{"evandc", VX (4, 530), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2077{"evxor", VX (4, 534), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2078{"evmr", VX (4, 535), VX_MASK, PPCSPE, PPCNONE, {RS, RA, BBA}},
2079{"evor", VX (4, 535), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2080{"evnor", VX (4, 536), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2081{"evnot", VX (4, 536), VX_MASK, PPCSPE, PPCNONE, {RS, RA, BBA}},
2082{"get", APU(4, 268,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
2083{"eveqv", VX (4, 537), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2084{"evorc", VX (4, 539), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2085{"evnand", VX (4, 542), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2086{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2087{"evsrws", VX (4, 545), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2088{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}},
2089{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}},
2090{"evslw", VX (4, 548), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2091{"evslwi", VX (4, 550), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}},
2092{"evrlw", VX (4, 552), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2093{"evsplati", VX (4, 553), VX_MASK, PPCSPE, PPCNONE, {RS, SIMM}},
2094{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}},
2095{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, PPCNONE, {RS, SIMM}},
2096{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2097{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2098{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2099{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2100{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2101{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2102{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2103{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2104{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2105{"cget", APU(4, 284,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
2106{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2107{"vminuh", VX (4, 578), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2108{"vsrh", VX (4, 580), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2109{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2110{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2111{"vrfiz", VX (4, 586), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2112{"vsplth", VX (4, 588), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
2113{"vupkhsh", VX (4, 590), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2114{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
2115{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, PPCNONE, {RS, RA, RB, CRFS}},
2116{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
2117{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2118{"vadduws", VX (4, 640), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2119{"evfssub", VX (4, 641), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2120{"vminuw", VX (4, 642), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2121{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2122{"vsrw", VX (4, 644), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2123{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2124{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2125{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2126{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2127{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2128{"vrfip", VX (4, 650), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2129{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2130{"vspltw", VX (4, 652), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
2131{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2132{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2133{"vupklsb", VX (4, 654), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2134{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2135{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2136{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2137{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2138{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2139{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2140{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2141{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2142{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2143{"put", APU(4, 332,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
2144{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
2145{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2146{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2147{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
2148{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
2149{"efsadd", VX (4, 704), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2150{"efssub", VX (4, 705), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2151{"efsabs", VX (4, 708), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
2152{"vsr", VX (4, 708), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2153{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
2154{"efsneg", VX (4, 710), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
2155{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2156{"efsmul", VX (4, 712), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2157{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2158{"vrfim", VX (4, 714), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2159{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2160{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2161{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2162{"vupklsh", VX (4, 718), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2163{"efscfd", VX (4, 719), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2164{"efscfui", VX (4, 720), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2165{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2166{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2167{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2168{"efsctui", VX (4, 724), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2169{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2170{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2171{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2172{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2173{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
2174{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2175{"efststgt", VX (4, 732), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2176{"efststlt", VX (4, 733), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2177{"efststeq", VX (4, 734), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2178{"efdadd", VX (4, 736), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2179{"efdsub", VX (4, 737), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2180{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2181{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2182{"efdabs", VX (4, 740), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
2183{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
2184{"efdneg", VX (4, 742), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
2185{"efdmul", VX (4, 744), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2186{"efddiv", VX (4, 745), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
2187{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2188{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2189{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2190{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2191{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2192{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2193{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2194{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2195{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2196{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2197{"efdctui", VX (4, 756), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2198{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2199{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2200{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2201{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2202{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
2203{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
2204{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2205{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2206{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
2207{"evlddx", VX (4, 768), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2208{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2209{"evldd", VX (4, 769), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
2210{"evldwx", VX (4, 770), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2211{"vminsb", VX (4, 770), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2212{"evldw", VX (4, 771), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
2213{"evldhx", VX (4, 772), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2214{"vsrab", VX (4, 772), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2215{"evldh", VX (4, 773), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
2216{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2217{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2218{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2219{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}},
2220{"vcfux", VX (4, 778), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
2221{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2222{"vspltisb", VX (4, 780), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}},
2223{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}},
2224{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2225{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2226{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}},
2227{"mullhwu", XRC(4, 392,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2228{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2229{"mullhwu.", XRC(4, 392,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2230{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2231{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2232{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2233{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2234{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2235{"maclhwu", XO (4, 396,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2236{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2237{"maclhwu.", XO (4, 396,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2238{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2239{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2240{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2241{"evstddx", VX (4, 800), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2242{"evstdd", VX (4, 801), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
2243{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2244{"evstdw", VX (4, 803), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
2245{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2246{"evstdh", VX (4, 805), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
2247{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2248{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2249{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2250{"evstwho", VX (4, 821), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2251{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2252{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2253{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2254{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
2255{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2256{"vminsh", VX (4, 834), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2257{"vsrah", VX (4, 836), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2258{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2259{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2260{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
2261{"vspltish", VX (4, 844), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}},
2262{"vupkhpx", VX (4, 846), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2263{"mullhw", XRC(4, 424,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2264{"mullhw.", XRC(4, 424,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2265{"maclhw", XO (4, 428,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2266{"maclhw.", XO (4, 428,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2267{"nmaclhw", XO (4, 430,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2268{"nmaclhw.", XO (4, 430,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2269{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2270{"vminsw", VX (4, 898), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2271{"vsraw", VX (4, 900), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2272{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2273{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
2274{"vspltisw", VX (4, 908), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}},
2275{"maclhwsu", XO (4, 460,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2276{"maclhwsu.", XO (4, 460,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2277{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2278{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
2279{"vupklpx", VX (4, 974), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
2280{"maclhws", XO (4, 492,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2281{"maclhws.", XO (4, 492,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2282{"nmaclhws", XO (4, 494,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2283{"nmaclhws.", XO (4, 494,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2284{"vsububm", VX (4,1024), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2285{"vavgub", VX (4,1026), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2286{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2287{"vand", VX (4,1028), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2288{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2289{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
2290{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
2291{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2292{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2293{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2294{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2295{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2296{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2297{"vslo", VX (4,1036), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2298{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2299{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2300{"machhwuo", XO (4, 12,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2301{"machhwuo.", XO (4, 12,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2302{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2303{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2304{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2305{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2306{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2307{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2308{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2309{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2310{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2311{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2312{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2313{"vavguh", VX (4,1090), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2314{"vandc", VX (4,1092), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2315{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2316{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
2317{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
2318{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2319{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2320{"vminfp", VX (4,1098), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2321{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2322{"vsro", VX (4,1100), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2323{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2324{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2325{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2326{"machhwo", XO (4, 44,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2327{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2328{"machhwo.", XO (4, 44,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2329{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2330{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2331{"nmachhwo", XO (4, 46,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2332{"nmachhwo.", XO (4, 46,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2333{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2334{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2335{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2336{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2337{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2338{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2339{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2340{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2341{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2342{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2343{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2344{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2345{"vavguw", VX (4,1154), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2346{"vor", VX (4,1156), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2347{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2348{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
2349{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
2350{"machhwsuo", XO (4, 76,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2351{"machhwsuo.", XO (4, 76,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2352{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2353{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2354{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2355{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2356{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2357{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2358{"evmra", VX (4,1220), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2359{"vxor", VX (4,1220), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2360{"evdivws", VX (4,1222), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2361{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2362{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
2363{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
2364{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2365{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2366{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2367{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2368{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
2369{"machhwso", XO (4, 108,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2370{"machhwso.", XO (4, 108,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2371{"nmachhwso", XO (4, 110,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2372{"nmachhwso.", XO (4, 110,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2373{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2374{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2375{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2376{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2377{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2378{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2379{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2380{"vnor", VX (4,1284), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2381{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2382{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
2383{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
2384{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2385{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2386{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2387{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2388{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2389{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2390{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2391{"macchwuo", XO (4, 140,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2392{"macchwuo.", XO (4, 140,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2393{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2394{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2395{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2396{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2397{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2398{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2399{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2400{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2401{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2402{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
2403{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
2404{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2405{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2406{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2407{"macchwo", XO (4, 172,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2408{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2409{"macchwo.", XO (4, 172,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2410{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2411{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2412{"nmacchwo", XO (4, 174,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2413{"nmacchwo.", XO (4, 174,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2414{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2415{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2416{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2417{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2418{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2419{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2420{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2421{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
2422{"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
2423{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2424{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2425{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2426{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2427{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2428{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2429{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2430{"macchwsuo", XO (4, 204,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2431{"macchwsuo.", XO (4, 204,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2432{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2433{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2434{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2435{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2436{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2437{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2438{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2439{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2440{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2441{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
2442{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
2443{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2444{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2445{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2446{"macchwso", XO (4, 236,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2447{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2448{"macchwso.", XO (4, 236,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2449{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2450{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2451{"nmacchwso", XO (4, 238,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2452{"nmacchwso.", XO (4, 238,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2453{"vsububs", VX (4,1536), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2454{"mfvscr", VX (4,1540), VX_MASK, PPCVEC, PPCNONE, {VD}},
2455{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2456{"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
2457{"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
2458{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2459{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2460{"mtvscr", VX (4,1604), VX_MASK, PPCVEC, PPCNONE, {VB}},
2461{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2462{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2463{"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
2464{"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
2465{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2466{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2467{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
2468{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
2469{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2470{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2471{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
2472{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
2473{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2474{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2475{"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
2476{"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
2477{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2478{"maclhwuo", XO (4, 396,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2479{"maclhwuo.", XO (4, 396,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2480{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2481{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2482{"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
2483{"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
2484{"maclhwo", XO (4, 428,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2485{"maclhwo.", XO (4, 428,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2486{"nmaclhwo", XO (4, 430,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2487{"nmaclhwo.", XO (4, 430,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2488{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2489{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2490{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
2491{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
2492{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2493{"maclhwsuo", XO (4, 460,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2494{"maclhwsuo.", XO (4, 460,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2495{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
2496{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
2497{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
2498{"maclhwso", XO (4, 492,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2499{"maclhwso.", XO (4, 492,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2500{"nmaclhwso", XO (4, 494,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2501{"nmaclhwso.", XO (4, 494,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
2502{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, PPCNONE, {RA, RB}},
2503
2504{"mulli", OP(7), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
2505{"muli", OP(7), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
2506
2507{"subfic", OP(8), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
2508{"sfi", OP(8), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
2509
2510{"dozi", OP(9), OP_MASK, M601, PPCNONE, {RT, RA, SI}},
2511
2512{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, UI}},
2513{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, UI}},
2514{"cmpli", OP(10), OP_MASK, PPC, PPCNONE, {BF, L, RA, UI}},
2515{"cmpli", OP(10), OP_MASK, PWRCOM, PPCNONE, {BF, RA, UI}},
2516
2517{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, SI}},
2518{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, SI}},
2519{"cmpi", OP(11), OP_MASK, PPC, PPCNONE, {BF, L, RA, SI}},
2520{"cmpi", OP(11), OP_MASK, PWRCOM, PPCNONE, {BF, RA, SI}},
2521
2522{"addic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
2523{"ai", OP(12), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
2524{"subic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, NSI}},
2525
2526{"addic.", OP(13), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
2527{"ai.", OP(13), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
2528{"subic.", OP(13), OP_MASK, PPCCOM, PPCNONE, {RT, RA, NSI}},
2529
2530{"li", OP(14), DRA_MASK, PPCCOM, PPCNONE, {RT, SI}},
2531{"lil", OP(14), DRA_MASK, PWRCOM, PPCNONE, {RT, SI}},
2532{"addi", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SI}},
2533{"cal", OP(14), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
2534{"subi", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSI}},
2535{"la", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, D, RA0}},
2536
2537{"lis", OP(15), DRA_MASK, PPCCOM, PPCNONE, {RT, SISIGNOPT}},
2538{"liu", OP(15), DRA_MASK, PWRCOM, PPCNONE, {RT, SISIGNOPT}},
2539{"addis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SISIGNOPT}},
2540{"cau", OP(15), OP_MASK, PWRCOM, PPCNONE, {RT, RA0, SISIGNOPT}},
2541{"subis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSI}},
2542
2543{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
2544{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
2545{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BD}},
2546{"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCNONE, {BD}},
2547{"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
2548{"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
2549{"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BD}},
2550{"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCNONE, {BD}},
2551{"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
2552{"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
2553{"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDA}},
2554{"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCNONE, {BDA}},
2555{"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
2556{"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
2557{"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDA}},
2558{"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCNONE, {BDA}},
2559{"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
2560{"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
2561{"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCNONE, {BD}},
2562{"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
2563{"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
2564{"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCNONE, {BD}},
2565{"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
2566{"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
2567{"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCNONE, {BDA}},
2568{"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
2569{"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
2570{"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCNONE, {BDA}},
2571
2572{"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2573{"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2574{"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2575{"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2576{"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2577{"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2578{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2579{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2580{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2581{"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2582{"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2583{"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2584{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2585{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2586{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2587{"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2588{"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2589{"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2590{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2591{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2592{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2593{"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2594{"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2595{"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2596{"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2597{"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2598{"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2599{"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2600{"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2601{"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2602{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2603{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2604{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2605{"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2606{"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2607{"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2608{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2609{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2610{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2611{"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2612{"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2613{"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2614{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2615{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2616{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2617{"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2618{"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2619{"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2620{"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2621{"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2622{"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2623{"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2624{"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2625{"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2626{"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2627{"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2628{"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2629{"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2630{"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2631{"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2632{"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2633{"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2634{"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2635{"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2636{"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2637{"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
2638{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2639{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2640{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2641{"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2642{"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2643{"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
2644{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2645{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2646{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2647{"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2648{"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2649{"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
2650{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2651{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2652{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2653{"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2654{"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2655{"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
2656
2657{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2658{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2659{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2660{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2661{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2662{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2663{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2664{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2665{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2666{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2667{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2668{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2669{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2670{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2671{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2672{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2673{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2674{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2675{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2676{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2677{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2678{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2679{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2680{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2681{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2682{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2683{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2684{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2685{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2686{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2687{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2688{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2689{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2690{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2691{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2692{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2693{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2694{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2695{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2696{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2697{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2698{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
2699{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2700{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2701{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
2702{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
2703{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
2704{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
2705{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2706{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2707{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2708{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2709{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2710{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
2711{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2712{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2713{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
2714{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
2715{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
2716{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
2717
2718{"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}},
2719{"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}},
2720{"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
2721{"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}},
2722{"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}},
2723{"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
2724{"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}},
2725{"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}},
2726{"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
2727{"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}},
2728{"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}},
2729{"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
2730{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}},
2731{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}},
2732{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
2733{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}},
2734{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}},
2735{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
2736{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}},
2737{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}},
2738{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
2739{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}},
2740{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}},
2741{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
2742
2743{"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
2744{"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
2745{"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
2746{"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
2747{"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
2748{"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
2749{"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
2750{"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
2751{"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
2752{"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
2753{"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
2754{"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
2755{"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
2756{"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
2757{"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
2758{"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
2759
2760{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}},
2761{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}},
2762{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
2763{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}},
2764{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}},
2765{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
2766{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}},
2767{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}},
2768{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
2769{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}},
2770{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}},
2771{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
2772{"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}},
2773{"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}},
2774{"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
2775{"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}},
2776{"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}},
2777{"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
2778{"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}},
2779{"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}},
2780{"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
2781{"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}},
2782{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}},
2783{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
2784
2785{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
2786{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
2787{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
2788{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
2789{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
2790{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
2791{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
2792{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
2793{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
2794{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
2795{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
2796{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
2797{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
2798{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
2799{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
2800{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
2801
2802{"bc-", B(16,0,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDM}},
2803{"bc+", B(16,0,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDP}},
2804{"bc", B(16,0,0), B_MASK, COM, PPCNONE, {BO, BI, BD}},
2805{"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDM}},
2806{"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDP}},
2807{"bcl", B(16,0,1), B_MASK, COM, PPCNONE, {BO, BI, BD}},
2808{"bca-", B(16,1,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDMA}},
2809{"bca+", B(16,1,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDPA}},
2810{"bca", B(16,1,0), B_MASK, COM, PPCNONE, {BO, BI, BDA}},
2811{"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDMA}},
2812{"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDPA}},
2813{"bcla", B(16,1,1), B_MASK, COM, PPCNONE, {BO, BI, BDA}},
2814
2815{"svc", SC(17,0,0), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}},
2816{"svcl", SC(17,0,1), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}},
2817{"sc", SC(17,1,0), SC_MASK, PPC, PPCNONE, {LEV}},
2818{"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCNONE, {SV}},
2819{"svcla", SC(17,1,1), SC_MASK, POWER, PPCNONE, {SV}},
2820
2821{"b", B(18,0,0), B_MASK, COM, PPCNONE, {LI}},
2822{"bl", B(18,0,1), B_MASK, COM, PPCNONE, {LI}},
2823{"ba", B(18,1,0), B_MASK, COM, PPCNONE, {LIA}},
2824{"bla", B(18,1,1), B_MASK, COM, PPCNONE, {LIA}},
2825
2826{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}},
2827
2828{"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
2829{"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, POWER4, {0}},
2830{"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
2831{"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, POWER4, {0}},
2832{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, POWER4, {0}},
2833{"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, POWER4, {0}},
2834{"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
2835{"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, POWER4, {0}},
2836{"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
2837{"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, POWER4, {0}},
2838{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, POWER4, {0}},
2839{"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, POWER4, {0}},
2840{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
2841{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCNONE, {0}},
2842{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
2843{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCNONE, {0}},
2844{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, PPCNONE, {0}},
2845{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, PPCNONE, {0}},
2846{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, PPCNONE, {0}},
2847{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, PPCNONE, {0}},
2848{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, PPCNONE, {0}},
2849{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, PPCNONE, {0}},
2850{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, PPCNONE, {0}},
2851{"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, PPCNONE, {0}},
2852
2853{"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2854{"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2855{"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
2856{"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2857{"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2858{"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
2859{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2860{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2861{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
2862{"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2863{"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2864{"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
2865{"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2866{"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2867{"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
2868{"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2869{"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2870{"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
2871{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2872{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2873{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
2874{"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2875{"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2876{"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
2877{"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2878{"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2879{"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
2880{"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2881{"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2882{"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
2883{"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2884{"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2885{"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
2886{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2887{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2888{"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2889{"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2890{"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
2891{"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2892{"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2893{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2894{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2895{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2896{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2897{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2898{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2899{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2900{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2901{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2902{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2903{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2904{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2905{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2906{"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2907{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2908{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2909{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2910{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2911{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2912{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2913{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2914{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2915{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2916{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2917{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2918{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2919{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2920{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2921{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2922{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2923{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2924{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2925{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2926{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2927{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2928{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2929{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2930{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2931{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2932{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2933{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2934{"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2935{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2936{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2937{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
2938{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2939{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2940{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
2941{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2942{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2943{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
2944{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2945{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2946{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
2947{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2948{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2949{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
2950{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2951{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2952{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
2953{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2954{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2955{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
2956{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2957{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2958{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2959{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2960{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
2961{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
2962{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2963{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2964{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2965{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2966{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2967{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2968{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2969{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2970{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2971{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2972{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
2973{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2974{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2975{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2976{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2977{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2978{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2979{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2980{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2981{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2982{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2983{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2984{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2985{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2986{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2987{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2988{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2989{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2990{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2991{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2992{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
2993
2994{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
2995{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
2996{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
2997{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
2998{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
2999{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3000{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3001{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3002{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3003{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3004{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3005{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3006{"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3007{"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3008{"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
3009{"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3010{"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3011{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
3012{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3013{"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3014{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
3015{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
3016{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
3017{"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
3018{"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3019{"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3020{"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3021{"bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3022{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3023{"bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3024{"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3025{"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3026{"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3027{"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3028{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3029{"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3030{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3031{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3032{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
3033{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3034{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3035{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
3036{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3037{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3038{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
3039{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
3040{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
3041{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
3042
3043{"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3044{"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3045{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3046{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3047{"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
3048{"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
3049{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
3050{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
3051
3052{"rfid", XL(19,18), 0xffffffff, PPC64, PPCNONE, {0}},
3053
3054{"crnot", XL(19,33), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}},
3055{"crnor", XL(19,33), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3056{"rfmci", X(19,38), 0xffffffff, PPCRFMCI, PPCNONE, {0}},
3057
3058{"rfdi", XL(19,39), 0xffffffff, E500MC, PPCNONE, {0}},
3059{"rfi", XL(19,50), 0xffffffff, COM, PPCNONE, {0}},
3060{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300, PPCNONE, {0}},
3061
3062{"rfsvc", XL(19,82), 0xffffffff, POWER, PPCNONE, {0}},
3063
3064{"rfgi", XL(19,102), 0xffffffff, E500MC, PPCNONE, {0}},
3065
3066{"crandc", XL(19,129), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3067
3068{"isync", XL(19,150), 0xffffffff, PPCCOM, PPCNONE, {0}},
3069{"ics", XL(19,150), 0xffffffff, PWRCOM, PPCNONE, {0}},
3070
3071{"crclr", XL(19,193), XL_MASK, PPCCOM, PPCNONE, {BT, BAT, BBA}},
3072{"crxor", XL(19,193), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3073
3074{"dnh", X(19,198), X_MASK, E500MC, PPCNONE, {DUI, DUIS}},
3075
3076{"crnand", XL(19,225), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3077
3078{"crand", XL(19,257), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3079
3080{"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPCNONE, {0}},
3081
3082{"crset", XL(19,289), XL_MASK, PPCCOM, PPCNONE, {BT, BAT, BBA}},
3083{"creqv", XL(19,289), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3084
3085{"doze", XL(19,402), 0xffffffff, POWER6, PPCNONE, {0}},
3086
3087{"crorc", XL(19,417), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3088
3089{"nap", XL(19,434), 0xffffffff, POWER6, PPCNONE, {0}},
3090
3091{"crmove", XL(19,449), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}},
3092{"cror", XL(19,449), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3093
3094{"sleep", XL(19,466), 0xffffffff, POWER6, PPCNONE, {0}},
3095{"rvwinkle", XL(19,498), 0xffffffff, POWER6, PPCNONE, {0}},
3096
3097{"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCNONE, {0}},
3098{"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCNONE, {0}},
3099
3100{"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3101{"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3102{"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3103{"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3104{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3105{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3106{"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3107{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3108{"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3109{"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3110{"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3111{"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3112{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3113{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3114{"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3115{"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3116{"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3117{"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3118{"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3119{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3120{"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3121{"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3122{"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3123{"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3124{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3125{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3126{"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3127{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3128{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3129{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3130{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3131{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3132{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3133{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3134{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3135{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3136{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3137{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3138{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3139{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3140{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3141{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3142{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3143{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3144{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3145{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3146{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3147{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3148{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3149{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3150{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3151{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3152{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3153{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3154{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3155{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3156{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3157{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3158{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3159{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3160{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3161{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3162{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3163{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3164{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3165{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3166{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3167{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3168{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3169{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3170{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3171{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3172{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3173{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3174{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3175{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3176{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3177{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3178{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3179{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3180{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3181{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3182{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3183{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3184{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3185{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3186{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3187{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3188{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3189{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3190{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3191{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3192{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3193{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3194{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3195{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3196{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3197{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3198{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3199{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
3200{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3201{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3202{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3203{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3204{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3205{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3206{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3207{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3208{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3209{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3210{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3211{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3212{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3213{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3214{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3215{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3216{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3217{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3218{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3219{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
3220
3221{"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3222{"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3223{"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3224{"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3225{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3226{"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3227{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
3228{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
3229{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
3230{"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
3231{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3232{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3233{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3234{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3235{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3236{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
3237{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
3238{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
3239{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
3240{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
3241
3242{"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3243{"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3244{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3245{"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3246{"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
3247{"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
3248{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
3249{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
3250
3251{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3252{"rlimi", M(20,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3253
3254{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3255{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3256
3257{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, SH}},
3258{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}},
3259{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3260{"rlinm", M(21,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3261{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, SH}},
3262{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}},
3263{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3264{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
3265
3266{"rlmi", M(22,0), M_MASK, M601, PPCNONE, {RA, RS, RB, MBE, ME}},
3267{"rlmi.", M(22,1), M_MASK, M601, PPCNONE, {RA, RS, RB, MBE, ME}},
3268
3269{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
3270{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
3271{"rlnm", M(23,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
3272{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
3273{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
3274{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
3275
3276{"nop", OP(24), 0xffffffff, PPCCOM, PPCNONE, {0}},
3277{"ori", OP(24), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
3278{"oril", OP(24), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
3279
3280{"oris", OP(25), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
3281{"oriu", OP(25), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
3282
3283{"xori", OP(26), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
3284{"xoril", OP(26), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
3285
3286{"xoris", OP(27), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
3287{"xoriu", OP(27), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
3288
3289{"andi.", OP(28), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
3290{"andil.", OP(28), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
3291
3292{"andis.", OP(29), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
3293{"andiu.", OP(29), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
3294
3295{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
3296{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCNONE, {RA, RS, MB6}},
3297{"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
3298{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
3299{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCNONE, {RA, RS, MB6}},
3300{"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
3301
3302{"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, ME6}},
3303{"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, ME6}},
3304
3305{"rldic", MD(30,2,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
3306{"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
3307
3308{"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
3309{"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
3310
3311{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCNONE, {RA, RS, RB}},
3312{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, MB6}},
3313{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCNONE, {RA, RS, RB}},
3314{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, MB6}},
3315
3316{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, ME6}},
3317{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, ME6}},
3318
3319{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}},
3320{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}},
3321{"cmp", X(31,0), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}},
3322{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPCNONE, {BF, RA, RB}},
3323
3324{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3325{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3326{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3327{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3328{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3329{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3330{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3331{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3332{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3333{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3334{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3335{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3336{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3337{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3338{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3339{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3340{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3341{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3342{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3343{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3344{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3345{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3346{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3347{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3348{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3349{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3350{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
3351{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
3352{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, PPCNONE, {0}},
3353{"tw", X(31,4), X_MASK, PPCCOM, PPCNONE, {TO, RA, RB}},
3354{"t", X(31,4), X_MASK, PWRCOM, PPCNONE, {TO, RA, RB}},
3355
3356{"lvsl", X(31,6), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
3357{"lvebx", X(31,7), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
3358{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
3359
3360{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3361{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
3362{"subc", XO(31,8,0,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
3363{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3364{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
3365{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}},
3366
3367{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
3368{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
3369
3370{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3371{"a", XO(31,10,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
3372{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3373{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
3374
3375{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
3376{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
3377
3378{"isellt", X(31,15), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}},
3379
3380{"mfcr", XFXM(31,19,0,0), XRARB_MASK, COM, POWER4, {RT}},
3381{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, PPCNONE, {RT, FXM4}},
3382{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, PPCNONE, {RT, FXM}},
3383
3384{"lwarx", X(31,20), XEH_MASK, PPC, PPCNONE, {RT, RA0, RB, EH}},
de866fcc 3385
1cb0a767
PB		 3386{"ldx", X(31,21), X_MASK, PPC64, PPCNONE, {RT, RA0, RB}},
3387
3388{"icbt", X(31,22), X_MASK, BOOKE|PPCE300, PPCNONE, {CT, RA, RB}},
3389
3390{"lwzx", X(31,23), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}},
3391{"lx", X(31,23), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
de866fcc 3392
1cb0a767
PB		 3393{"slw", XRC(31,24,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
3394{"sl", XRC(31,24,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
3395{"slw.", XRC(31,24,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
3396{"sl.", XRC(31,24,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
de866fcc 3397
1cb0a767
PB		 3398{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}},
3399{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
3400{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}},
3401{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
de866fcc 3402
1cb0a767
PB		 3403{"sld", XRC(31,27,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
3404{"sld.", XRC(31,27,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
de866fcc 3405
1cb0a767
PB		 3406{"and", XRC(31,28,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3407{"and.", XRC(31,28,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
de866fcc 3408
1cb0a767
PB		 3409{"maskg", XRC(31,29,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
3410{"maskg.", XRC(31,29,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
de866fcc 3411
1cb0a767
PB		 3412{"ldepx", X(31,29), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
3413{"lwepx", X(31,31), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
de866fcc 3414
1cb0a767
PB		 3415{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}},
3416{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}},
3417{"cmpl", X(31,32), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}},
3418{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPCNONE, {BF, RA, RB}},
de866fcc 3419
1cb0a767
PB		 3420{"lvsr", X(31,38), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
3421{"lvehx", X(31,39), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
3422{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
de866fcc 3423
1cb0a767 3424{"iselgt", X(31,47), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}},
de866fcc 3425
1cb0a767 3426{"lvewx", X(31,71), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
de866fcc 3427
1cb0a767 3428{"iseleq", X(31,79), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}},
de866fcc 3429
1cb0a767 3430{"isel", XISEL(31,15), XISEL_MASK, PPCISEL, PPCNONE, {RT, RA, RB, CRB}},
de866fcc 3431
1cb0a767
PB		 3432{"subf", XO(31,40,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
3433{"sub", XO(31,40,0,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
3434{"subf.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
3435{"sub.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
de866fcc 3436
1cb0a767 3437{"ldux", X(31,53), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}},
de866fcc 3438
1cb0a767 3439{"dcbst", X(31,54), XRT_MASK, PPC, PPCNONE, {RA, RB}},
de866fcc 3440
1cb0a767
PB		 3441{"lwzux", X(31,55), X_MASK, PPCCOM, PPCNONE, {RT, RAL, RB}},
3442{"lux", X(31,55), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
de866fcc 3443
1cb0a767
PB		 3444{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
3445{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
de866fcc 3446
1cb0a767
PB		 3447{"andc", XRC(31,60,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3448{"andc.", XRC(31,60,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
de866fcc 3449
1cb0a767 3450{"wait", X(31,62), 0xffffffff, E500MC, PPCNONE, {0}},
19a6653c 3451
1cb0a767 3452{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
19a6653c 3453
1cb0a767
PB		 3454{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3455{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3456{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3457{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3458{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3459{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3460{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3461{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3462{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3463{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3464{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3465{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3466{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3467{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
3468{"td", X(31,68), X_MASK, PPC64, PPCNONE, {TO, RA, RB}},
de866fcc 3469
1cb0a767
PB		 3470{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
3471{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
3472{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
de866fcc 3473
1cb0a767
PB		 3474{"mulhw", XO(31,75,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
3475{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
de866fcc 3476
1cb0a767
PB		 3477{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, PPCNONE, {RA, RS, RB}},
3478{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, PPCNONE, {RA, RS, RB}},
de866fcc 3479
1cb0a767 3480{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, PPCNONE, {SR, RS}},
de866fcc 3481
1cb0a767 3482{"mfmsr", X(31,83), XRARB_MASK, COM, PPCNONE, {RT}},
de866fcc 3483
1cb0a767 3484{"ldarx", X(31,84), XEH_MASK, PPC64, PPCNONE, {RT, RA0, RB, EH}},
de866fcc 3485
1cb0a767
PB		 3486{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPCNONE, {RA, RB}},
3487{"dcbf", X(31,86), XLRT_MASK, PPC, PPCNONE, {RA, RB, L}},
de866fcc 3488
1cb0a767 3489{"lbzx", X(31,87), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
de866fcc 3490
1cb0a767 3491{"lbepx", X(31,95), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
de866fcc 3492
1cb0a767
PB		 3493{"lvx", X(31,103), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
3494{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
de866fcc 3495
1cb0a767
PB		 3496{"neg", XO(31,104,0,0), XORB_MASK, COM, PPCNONE, {RT, RA}},
3497{"neg.", XO(31,104,0,1), XORB_MASK, COM, PPCNONE, {RT, RA}},
de866fcc 3498
1cb0a767
PB		 3499{"mul", XO(31,107,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
3500{"mul.", XO(31,107,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
de866fcc 3501
1cb0a767 3502{"mtsrdin", X(31,114), XRA_MASK, PPC64, PPCNONE, {RS, RB}},
de866fcc 3503
1cb0a767 3504{"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}},
de866fcc 3505
1cb0a767 3506{"lbzux", X(31,119), X_MASK, COM, PPCNONE, {RT, RAL, RB}},
de866fcc 3507
1cb0a767 3508{"popcntb", X(31,122), XRB_MASK, POWER5, PPCNONE, {RA, RS}},
de866fcc 3509
1cb0a767
PB		 3510{"not", XRC(31,124,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
3511{"nor", XRC(31,124,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3512{"not.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
3513{"nor.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
de866fcc 3514
1cb0a767 3515{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
19a6653c 3516
1cb0a767 3517{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE, PPCNONE, {RS}},
de866fcc 3518
1cb0a767 3519{"dcbtstls", X(31,134), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
de866fcc 3520
1cb0a767
PB		 3521{"stvebx", X(31,135), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
3522{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
de866fcc 3523
1cb0a767
PB		 3524{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3525{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
3526{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3527{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
de866fcc 3528
1cb0a767
PB		 3529{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3530{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
3531{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3532{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
de866fcc 3533
1cb0a767 3534{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
de866fcc 3535
1cb0a767
PB		 3536{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, PPCNONE, {RS}},
3537{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, PPCNONE, {FXM, RS}},
3538{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, PPCNONE, {FXM, RS}},
de866fcc 3539
1cb0a767 3540{"mtmsr", X(31,146), XRLARB_MASK, COM, PPCNONE, {RS, A_L}},
de866fcc 3541
1cb0a767 3542{"stdx", X(31,149), X_MASK, PPC64, PPCNONE, {RS, RA0, RB}},
de866fcc 3543
1cb0a767 3544{"stwcx.", XRC(31,150,1), X_MASK, PPC, PPCNONE, {RS, RA0, RB}},
de866fcc 3545
1cb0a767
PB		 3546{"stwx", X(31,151), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}},
3547{"stx", X(31,151), X_MASK, PWRCOM, PPCNONE, {RS, RA, RB}},
de866fcc 3548
1cb0a767
PB		 3549{"slq", XRC(31,152,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
3550{"slq.", XRC(31,152,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
de866fcc 3551
1cb0a767
PB		 3552{"sle", XRC(31,153,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
3553{"sle.", XRC(31,153,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
de866fcc 3554
1cb0a767 3555{"prtyw", X(31,154), XRB_MASK, POWER6, PPCNONE, {RA, RS}},
de866fcc 3556
1cb0a767 3557{"stdepx", X(31,157), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
19a6653c 3558
1cb0a767 3559{"stwepx", X(31,159), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
de866fcc 3560
1cb0a767 3561{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE, PPCNONE, {E}},
de866fcc 3562
1cb0a767 3563{"dcbtls", X(31,166), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
de866fcc 3564
1cb0a767
PB		 3565{"stvehx", X(31,167), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
3566{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
de866fcc 3567
1cb0a767 3568{"dcbtlse", X(31,174), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
de866fcc 3569
1cb0a767 3570{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, PPCNONE, {RS, A_L}},
de866fcc 3571
1cb0a767 3572{"stdux", X(31,181), X_MASK, PPC64, PPCNONE, {RS, RAS, RB}},
de866fcc 3573
1cb0a767
PB		 3574{"stwux", X(31,183), X_MASK, PPCCOM, PPCNONE, {RS, RAS, RB}},
3575{"stux", X(31,183), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
de866fcc 3576
1cb0a767
PB		 3577{"sliq", XRC(31,184,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
3578{"sliq.", XRC(31,184,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
de866fcc 3579
1cb0a767 3580{"prtyd", X(31,186), XRB_MASK, POWER6, PPCNONE, {RA, RS}},
252b5132 3581
1cb0a767
PB		 3582{"stvewx", X(31,199), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
3583{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
252b5132 3584
1cb0a767
PB		 3585{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3586{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
3587{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3588{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
252b5132 3589
1cb0a767
PB		 3590{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3591{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
3592{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3593{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
418c1742 3594
1cb0a767 3595{"msgsnd", XRTRA(31,206,0,0),XRTRA_MASK,E500MC, PPCNONE, {RB}},
19a6653c 3596
1cb0a767 3597{"mtsr", X(31,210), XRB_MASK|(1<<20), COM32, PPCNONE, {SR, RS}},
418c1742 3598
1cb0a767 3599{"stdcx.", XRC(31,214,1), X_MASK, PPC64, PPCNONE, {RS, RA0, RB}},
252b5132 3600
1cb0a767 3601{"stbx", X(31,215), X_MASK, COM, PPCNONE, {RS, RA0, RB}},
252b5132 3602
1cb0a767
PB		 3603{"sllq", XRC(31,216,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
3604{"sllq.", XRC(31,216,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
252b5132 3605
1cb0a767
PB		 3606{"sleq", XRC(31,217,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
3607{"sleq.", XRC(31,217,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
252b5132 3608
1cb0a767 3609{"stbepx", X(31,223), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
252b5132 3610
1cb0a767 3611{"icblc", X(31,230), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
7d5b217e 3612
1cb0a767
PB		 3613{"stvx", X(31,231), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
3614{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
f509565f 3615
1cb0a767
PB		 3616{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3617{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
3618{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3619{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
252b5132 3620
1cb0a767
PB		 3621{"mulld", XO(31,233,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
3622{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
252b5132 3623
1cb0a767
PB		 3624{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3625{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
3626{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
3627{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
252b5132 3628
1cb0a767
PB		 3629{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3630{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
3631{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3632{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
252b5132 3633
1cb0a767
PB		 3634{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC, PPCNONE, {RB}},
3635{"icblce", X(31,238), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
3636{"mtsrin", X(31,242), XRA_MASK, PPC32, PPCNONE, {RS, RB}},
3637{"mtsri", X(31,242), XRA_MASK, POWER32, PPCNONE, {RS, RB}},
418c1742 3638
1cb0a767 3639{"dcbtst", X(31,246), X_MASK, PPC, PPCNONE, {CT, RA, RB}},
418c1742 3640
1cb0a767 3641{"stbux", X(31,247), X_MASK, COM, PPCNONE, {RS, RAS, RB}},
252b5132 3642
1cb0a767
PB		 3643{"slliq", XRC(31,248,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
3644{"slliq.", XRC(31,248,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
252b5132 3645
1cb0a767 3646{"dcbtstep", XRT(31,255,0), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
19a6653c 3647
1cb0a767 3648{"mfdcrx", X(31,259), X_MASK, BOOKE, PPCNONE, {RS, RA}},
252b5132 3649
1cb0a767 3650{"icbt", X(31,262), XRT_MASK, PPC403, PPCNONE, {RA, RB}},
1ed8e1e4 3651
1cb0a767
PB		 3652{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
3653{"doz", XO(31,264,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
3654{"doz.", XO(31,264,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
252b5132 3655
1cb0a767
PB		 3656{"add", XO(31,266,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3657{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
3658{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
3659{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
418c1742 3660
1cb0a767 3661{"ehpriv", X(31,270), 0xffffffff, E500MC, PPCNONE, {0}},
19a6653c 3662
1cb0a767 3663{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, PPCNONE, {RB, L}},
418c1742 3664
1cb0a767
PB		 3665{"mfapidi", X(31,275), X_MASK, BOOKE, PPCNONE, {RT, RA}},
3666
3667{"lscbx", XRC(31,277,0), X_MASK, M601, PPCNONE, {RT, RA, RB}},
3668{"lscbx.", XRC(31,277,1), X_MASK, M601, PPCNONE, {RT, RA, RB}},
3669
3670{"dcbt", X(31,278), X_MASK, PPC, PPCNONE, {CT, RA, RB}},
3671
3672{"lhzx", X(31,279), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
3673
3674{"eqv", XRC(31,284,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3675{"eqv.", XRC(31,284,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3676
3677{"lhepx", X(31,287), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
3678
3679{"mfdcrux", X(31,291), X_MASK, PPC464, PPCNONE, {RS, RA}},
3680
3681{"tlbie", X(31,306), XRTLRA_MASK, PPC, PPCNONE, {RB, L}},
3682{"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}},
3683
3684{"eciwx", X(31,310), X_MASK, PPC, PPCNONE, {RT, RA, RB}},
3685
3686{"lhzux", X(31,311), X_MASK, COM, PPCNONE, {RT, RAL, RB}},
3687
3688{"xor", XRC(31,316,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3689{"xor.", XRC(31,316,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3690
3691{"dcbtep", XRT(31,319,0), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
3692
3693{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, PPCNONE, {RT}},
3694{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, PPCNONE, {RT}},
3695{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, PPCNONE, {RT}},
3696{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, PPCNONE, {RT}},
3697{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, PPCNONE, {RT}},
3698{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, PPCNONE, {RT}},
3699{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, PPCNONE, {RT}},
3700{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, PPCNONE, {RT}},
3701{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, PPCNONE, {RT}},
3702{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, PPCNONE, {RT}},
3703{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, PPCNONE, {RT}},
3704{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, PPCNONE, {RT}},
3705{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, PPCNONE, {RT}},
3706{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, PPCNONE, {RT}},
3707{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, PPCNONE, {RT}},
3708{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, PPCNONE, {RT}},
3709{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, PPCNONE, {RT}},
3710{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, PPCNONE, {RT}},
3711{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, PPCNONE, {RT}},
3712{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, PPCNONE, {RT}},
3713{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, PPCNONE, {RT}},
3714{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, PPCNONE, {RT}},
3715{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, PPCNONE, {RT}},
3716{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, PPCNONE, {RT}},
3717{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, PPCNONE, {RT}},
3718{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, PPCNONE, {RT}},
3719{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, PPCNONE, {RT}},
3720{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, PPCNONE, {RT}},
3721{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, PPCNONE, {RT}},
3722{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, PPCNONE, {RT}},
3723{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, PPCNONE, {RT}},
3724{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, PPCNONE, {RT}},
3725{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, PPCNONE, {RT}},
3726{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, PPCNONE, {RT}},
3727{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE, PPCNONE, {RT, SPR}},
3728
3729{"div", XO(31,331,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
3730{"div.", XO(31,331,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
3731
3732{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, PPCNONE, {RT, PMR}},
3733
3734{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, PPCNONE, {RT}},
3735{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, PPCNONE, {RT}},
3736{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, PPCNONE, {RT}},
3737{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, PPCNONE, {RT}},
3738{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, PPCNONE, {RT}},
3739{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, PPCNONE, {RT}},
3740{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, PPCNONE, {RT}},
3741{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, PPCNONE, {RT}},
3742{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, PPCNONE, {RT}},
3743{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, PPCNONE, {RT}},
3744{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, PPCNONE, {RT}},
3745{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, PPCNONE, {RT}},
3746{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, PPCNONE, {RT}},
3747{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, PPCNONE, {RT}},
3748{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, PPCNONE, {RT}},
3749{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, PPCNONE, {RT}},
3750{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3751{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3752{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3753{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3754{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3755{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3756{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, PPCNONE, {RT}},
3757{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, PPCNONE, {RT}},
3758{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, PPCNONE, {RT}},
3759{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, PPCNONE, {RT}},
3760{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, PPCNONE, {RT}},
3761{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, PPCNONE, {RT}},
3762{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, PPCNONE, {RT}},
3763{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, PPCNONE, {RT}},
3764{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, PPCNONE, {RT}},
3765{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, PPCNONE, {RT}},
3766{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, PPCNONE, {RT}},
3767{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, PPCNONE, {RT}},
3768{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, PPCNONE, {RT}},
3769{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, PPCNONE, {RT}},
3770{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, PPCNONE, {RT}},
3771{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, PPCNONE, {RT}},
3772{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, PPCNONE, {RT}},
3773{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3774{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, PPCNONE, {RT, SPRG}},
3775{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}},
3776{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}},
3777{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}},
3778{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}},
3779{"mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3780{"mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3781{"mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3782{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, PPCNONE, {RT}},
3783{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, PPCNONE, {RT}},
3784{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, PPCNONE, {RT}},
3785{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, PPCNONE, {RT}},
3786{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, PPCNONE, {RT}},
3787{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, PPCNONE, {RT}},
3788{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3789{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, PPCNONE, {RT}},
3790{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3791{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3792{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3793{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3794{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3795{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3796{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3797{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3798{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3799{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3800{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3801{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3802{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3803{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3804{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3805{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3806{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3807{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3808{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3809{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3810{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3811{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3812{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3813{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3814{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3815{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3816{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3817{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3818{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3819{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, PPCNONE, {RT}},
3820{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
3821{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, PPCNONE, {RT}},
3822{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, PPCNONE, {RT}},
3823{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
3824{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, PPCNONE, {RT, SPRBAT}},
3825{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
3826{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, PPCNONE, {RT, SPRBAT}},
3827{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
3828{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, PPCNONE, {RT}},
3829{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, PPCNONE, {RT, SPRBAT}},
3830{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, PPCNONE, {RT, SPRBAT}},
3831{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, PPCNONE, {RT}},
3832{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, PPCNONE, {RT}},
3833{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, PPCNONE, {RT}},
3834{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, PPCNONE, {RT}},
3835{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, PPCNONE, {RT}},
3836{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, PPCNONE, {RT}},
3837{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}},
3838{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}},
3839{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}},
3840{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}},
3841{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, PPCNONE, {RT}},
3842{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, PPCNONE, {RT}},
3843{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, PPCNONE, {RT}},
3844{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, PPCNONE, {RT}},
3845{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, PPCNONE, {RT}},
3846{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, PPCNONE, {RT}},
3847{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, PPCNONE, {RT}},
3848{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, PPCNONE, {RT}},
3849{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, PPCNONE, {RT}},
3850{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, PPCNONE, {RT}},
3851{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, PPCNONE, {RT}},
3852{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, PPCNONE, {RT}},
3853{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, PPCNONE, {RT}},
3854{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, PPCNONE, {RT}},
3855{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, PPCNONE, {RT}},
3856{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, PPCNONE, {RT}},
3857{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, PPCNONE, {RT}},
3858{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, PPCNONE, {RT}},
3859{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, PPCNONE, {RT}},
3860{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, PPCNONE, {RT}},
3861{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, PPCNONE, {RT}},
3862{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, PPCNONE, {RT}},
3863{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, PPCNONE, {RT}},
3864{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, PPCNONE, {RT}},
3865{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, PPCNONE, {RT}},
3866{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, PPCNONE, {RT}},
3867{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, PPCNONE, {RT}},
3868{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, PPCNONE, {RT}},
3869{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, PPCNONE, {RT}},
3870{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, PPCNONE, {RT}},
3871{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, PPCNONE, {RT}},
3872{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, PPCNONE, {RT}},
3873{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, PPCNONE, {RT}},
3874{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, PPCNONE, {RT}},
3875{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, PPCNONE, {RT}},
3876{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, PPCNONE, {RT}},
3877{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, PPCNONE, {RT}},
3878{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, PPCNONE, {RT}},
3879{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, PPCNONE, {RT}},
3880{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, PPCNONE, {RT}},
3881{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, PPCNONE, {RT}},
3882{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, PPCNONE, {RT}},
3883{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, PPCNONE, {RT}},
3884{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, PPCNONE, {RT}},
3885{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, PPCNONE, {RT}},
3886{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, PPCNONE, {RT}},
3887{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, PPCNONE, {RT}},
3888{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, PPCNONE, {RT}},
3889{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, PPCNONE, {RT}},
3890{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, PPCNONE, {RT}},
3891{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, PPCNONE, {RT}},
3892{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, PPCNONE, {RT}},
3893{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, PPCNONE, {RT}},
3894{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, PPCNONE, {RT}},
3895{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, PPCNONE, {RT}},
3896{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, PPCNONE, {RT}},
3897{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, PPCNONE, {RT}},
3898{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, PPCNONE, {RT}},
3899{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, PPCNONE, {RT}},
3900{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, PPCNONE, {RT}},
3901{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, PPCNONE, {RT}},
3902{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, PPCNONE, {RT}},
3903{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, PPCNONE, {RT}},
3904{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, PPCNONE, {RT}},
3905{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, PPCNONE, {RT}},
3906{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, PPCNONE, {RT}},
3907{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, PPCNONE, {RT}},
3908{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, PPCNONE, {RT}},
3909{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, PPCNONE, {RT}},
3910{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, PPCNONE, {RT}},
3911{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, PPCNONE, {RT}},
3912{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, PPCNONE, {RT}},
3913{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, PPCNONE, {RT}},
3914{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, PPCNONE, {RT}},
3915{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, PPCNONE, {RT}},
3916{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, PPCNONE, {RT}},
3917{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, PPCNONE, {RT}},
3918{"mfspr", X(31,339), X_MASK, COM, PPCNONE, {RT, SPR}},
3919
3920{"lwax", X(31,341), X_MASK, PPC64, PPCNONE, {RT, RA0, RB}},
3921
3922{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
3923
3924{"lhax", X(31,343), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
3925
3926{"lvxl", X(31,359), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
3927
3928{"abs", XO(31,360,0,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
3929{"abs.", XO(31,360,0,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
3930
3931{"divs", XO(31,363,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
3932{"divs.", XO(31,363,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
3933
3934{"tlbia", X(31,370), 0xffffffff, PPC, PPCNONE, {0}},
3935
3936{"mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, PPCNONE, {RT}},
3937{"mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, PPCNONE, {RT}},
3938{"mftb", X(31,371), X_MASK, CLASSIC, PPCNONE, {RT, TBR}},
3939
3940{"lwaux", X(31,373), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}},
3941
3942{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
3943
3944{"lhaux", X(31,375), X_MASK, COM, PPCNONE, {RT, RAL, RB}},
3945
3946{"mtdcrx", X(31,387), X_MASK, BOOKE, PPCNONE, {RA, RS}},
3947
3948{"dcblc", X(31,390), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
3949{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
3950
3951{"dcblce", X(31,398), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
3952
3953{"slbmte", X(31,402), XRA_MASK, PPC64, PPCNONE, {RS, RB}},
3954
3955{"sthx", X(31,407), X_MASK, COM, PPCNONE, {RS, RA0, RB}},
3956
3957{"orc", XRC(31,412,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3958{"orc.", XRC(31,412,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3959
3960{"sthepx", X(31,415), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
3961
3962{"mtdcrux", X(31,419), X_MASK, PPC464, PPCNONE, {RA, RS}},
3963
3964{"slbie", X(31,434), XRTRA_MASK, PPC64, PPCNONE, {RB}},
3965
3966{"ecowx", X(31,438), X_MASK, PPC, PPCNONE, {RT, RA, RB}},
3967
3968{"sthux", X(31,439), X_MASK, COM, PPCNONE, {RS, RAS, RB}},
3969
3970{"mdors", 0x7f9ce378, 0xffffffff, E500MC, PPCNONE, {0}},
3971
3972{"mr", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
3973{"or", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3974{"mr.", XRC(31,444,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
3975{"or.", XRC(31,444,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
3976
3977{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, PPCNONE, {RS}},
3978{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, PPCNONE, {RS}},
3979{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, PPCNONE, {RS}},
3980{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, PPCNONE, {RS}},
3981{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, PPCNONE, {RS}},
3982{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, PPCNONE, {RS}},
3983{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, PPCNONE, {RS}},
3984{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, PPCNONE, {RS}},
3985{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, PPCNONE, {RS}},
3986{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, PPCNONE, {RS}},
3987{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, PPCNONE, {RS}},
3988{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, PPCNONE, {RS}},
3989{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, PPCNONE, {RS}},
3990{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, PPCNONE, {RS}},
3991{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, PPCNONE, {RS}},
3992{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, PPCNONE, {RS}},
3993{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, PPCNONE, {RS}},
3994{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, PPCNONE, {RS}},
3995{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, PPCNONE, {RS}},
3996{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, PPCNONE, {RS}},
3997{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, PPCNONE, {RS}},
3998{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, PPCNONE, {RS}},
3999{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, PPCNONE, {RS}},
4000{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, PPCNONE, {RS}},
4001{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, PPCNONE, {RS}},
4002{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, PPCNONE, {RS}},
4003{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, PPCNONE, {RS}},
4004{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, PPCNONE, {RS}},
4005{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, PPCNONE, {RS}},
4006{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, PPCNONE, {RS}},
4007{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, PPCNONE, {RS}},
4008{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, PPCNONE, {RS}},
4009{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, PPCNONE, {RS}},
4010{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, PPCNONE, {RS}},
4011{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE, PPCNONE, {SPR, RS}},
4012
4013{"dccci", X(31,454), XRT_MASK, PPC403|PPC440, PPCNONE, {RA, RB}},
4014
4015{"divdu", XO(31,457,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
4016{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
4017
4018{"divwu", XO(31,459,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4019{"divwu.", XO(31,459,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4020
4021{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, PPCNONE, {PMR, RS}},
4022
4023{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, PPCNONE, {RS}},
4024{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, PPCNONE, {RS}},
4025{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, PPCNONE, {RS}},
4026{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, PPCNONE, {RS}},
4027{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, PPCNONE, {RS}},
4028{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, PPCNONE, {RS}},
4029{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, PPCNONE, {RS}},
4030{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, PPCNONE, {RS}},
4031{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, PPCNONE, {RS}},
4032{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, PPCNONE, {RS}},
4033{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, PPCNONE, {RS}},
4034{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, PPCNONE, {RS}},
4035{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, PPCNONE, {RS}},
4036{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, PPCNONE, {RS}},
4037{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, PPCNONE, {RS}},
4038{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4039{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4040{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4041{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4042{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4043{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4044{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4045{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, PPCNONE, {RS}},
4046{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, PPCNONE, {RS}},
4047{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, PPCNONE, {RS}},
4048{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, PPCNONE, {RS}},
4049{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, PPCNONE, {RS}},
4050{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, PPCNONE, {RS}},
4051{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, PPCNONE, {RS}},
4052{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, PPCNONE, {RS}},
4053{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, PPCNONE, {RS}},
4054{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, PPCNONE, {RS}},
4055{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, PPCNONE, {RS}},
4056{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, PPCNONE, {RS}},
4057{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, PPCNONE, {RS}},
4058{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, PPCNONE, {RS}},
4059{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, PPCNONE, {RS}},
4060{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, PPCNONE, {RS}},
4061{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, PPCNONE, {RS}},
4062{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4063{"mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, PPCNONE, {SPRG, RS}},
4064{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, PPCNONE, {RS}},
4065{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, PPCNONE, {RS}},
4066{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, PPCNONE, {RS}},
4067{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, PPCNONE, {RS}},
4068{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}},
4069{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}},
4070{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}},
4071{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}},
4072{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, PPCNONE, {RS}},
4073{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, PPCNONE, {RS}},
4074{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, PPCNONE, {RS}},
4075{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, PPCNONE, {RS}},
4076{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4077{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4078{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4079{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4080{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4081{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4082{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4083{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4084{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4085{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4086{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4087{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4088{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4089{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4090{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4091{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4092{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4093{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4094{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4095{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4096{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4097{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4098{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4099{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4100{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4101{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4102{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4103{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4104{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4105{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, PPCNONE, {RS}},
4106{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
4107{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, PPCNONE, {RS}},
4108{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, PPCNONE, {RS}},
4109{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
4110{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, PPCNONE, {SPRBAT, RS}},
4111{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
4112{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, PPCNONE, {SPRBAT, RS}},
4113{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
4114{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, PPCNONE, {RS}},
4115{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, PPCNONE, {SPRBAT, RS}},
4116{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, PPCNONE, {SPRBAT, RS}},
4117{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}},
4118{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}},
4119{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}},
4120{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, PPCNONE, {RS}},
4121{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, PPCNONE, {RS}},
4122{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, PPCNONE, {RS}},
4123{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, PPCNONE, {RS}},
4124{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, PPCNONE, {RS}},
4125{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, PPCNONE, {RS}},
4126{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, PPCNONE, {RS}},
4127{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, PPCNONE, {RS}},
4128{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, PPCNONE, {RS}},
4129{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, PPCNONE, {RS}},
4130{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, PPCNONE, {RS}},
4131{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, PPCNONE, {RS}},
4132{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, PPCNONE, {RS}},
4133{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, PPCNONE, {RS}},
4134{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, PPCNONE, {RS}},
4135{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, PPCNONE, {RS}},
4136{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, PPCNONE, {RS}},
4137{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, PPCNONE, {RS}},
4138{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, PPCNONE, {RS}},
4139{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, PPCNONE, {RS}},
4140{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, PPCNONE, {RS}},
4141{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, PPCNONE, {RS}},
4142{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, PPCNONE, {RS}},
4143{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, PPCNONE, {RS}},
4144{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, PPCNONE, {RS}},
4145{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, PPCNONE, {RS}},
4146{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, PPCNONE, {RS}},
4147{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, PPCNONE, {RS}},
4148{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, PPCNONE, {RS}},
4149{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, PPCNONE, {RS}},
4150{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, PPCNONE, {RS}},
4151{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, PPCNONE, {RS}},
4152{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, PPCNONE, {RS}},
4153{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, PPCNONE, {RS}},
4154{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, PPCNONE, {RS}},
4155{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, PPCNONE, {RS}},
4156{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, PPCNONE, {RS}},
4157{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, PPCNONE, {RS}},
4158{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, PPCNONE, {RS}},
4159{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, PPCNONE, {RS}},
4160{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, PPCNONE, {RS}},
4161{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, PPCNONE, {RS}},
4162{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, PPCNONE, {RS}},
4163{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, PPCNONE, {RS}},
4164{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, PPCNONE, {RS}},
4165{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, PPCNONE, {RS}},
4166{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, PPCNONE, {RS}},
4167{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, PPCNONE, {RS}},
4168{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, PPCNONE, {RS}},
4169{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, PPCNONE, {RS}},
4170{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, PPCNONE, {RS}},
4171{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, PPCNONE, {RS}},
4172{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, PPCNONE, {RS}},
4173{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, PPCNONE, {RS}},
4174{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, PPCNONE, {RS}},
4175{"mtspr", X(31,467), X_MASK, COM, PPCNONE, {SPR, RS}},
4176
4177{"dcbi", X(31,470), XRT_MASK, PPC, PPCNONE, {RA, RB}},
4178
4179{"nand", XRC(31,476,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
4180{"nand.", XRC(31,476,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
4181
4182{"dsn", X(31,483), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
4183
4184{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCNONE, {RT, RA, RB}},
4185
4186{"icbtls", X(31,486), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
4187
4188{"stvxl", X(31,487), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
4189
4190{"nabs", XO(31,488,0,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
4191{"nabs.", XO(31,488,0,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
4192
4193{"divd", XO(31,489,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
4194{"divd.", XO(31,489,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
4195
4196{"divw", XO(31,491,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4197{"divw.", XO(31,491,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4198
4199{"icbtlse", X(31,494), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
4200
4201{"slbia", X(31,498), 0xffffffff, PPC64, PPCNONE, {0}},
4202
4203{"cli", X(31,502), XRB_MASK, POWER, PPCNONE, {RT, RA}},
4204
4205{"cmpb", X(31,508), X_MASK, POWER6, PPCNONE, {RA, RS, RB}},
4206
4207{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, PPCNONE, {BF}},
252b5132 4208
1cb0a767 4209{"lbdx", X(31,515), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
19a6653c 4210
1cb0a767 4211{"bblels", X(31,518), X_MASK, PPCBRLK, PPCNONE, {0}},
252b5132 4212
1cb0a767
PB		 4213{"lvlx", X(31,519), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
4214{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
252b5132 4215
1cb0a767
PB		 4216{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4217{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4218{"subco", XO(31,8,1,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
4219{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4220{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4221{"subco.", XO(31,8,1,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
252b5132 4222
1cb0a767
PB		 4223{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4224{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4225{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4226{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
252b5132 4227
1cb0a767 4228{"clcs", X(31,531), XRB_MASK, M601, PPCNONE, {RT, RA}},
418c1742 4229
1cb0a767 4230{"ldbrx", X(31,532), X_MASK, CELL, PPCNONE, {RT, RA0, RB}},
418c1742 4231
1cb0a767
PB		 4232{"lswx", X(31,533), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}},
4233{"lsx", X(31,533), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
252b5132 4234
1cb0a767
PB		 4235{"lwbrx", X(31,534), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}},
4236{"lbrx", X(31,534), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
252b5132 4237
1cb0a767 4238{"lfsx", X(31,535), X_MASK, COM, PPCNONE, {FRT, RA0, RB}},
702f0fb4 4239
1cb0a767
PB		 4240{"srw", XRC(31,536,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
4241{"sr", XRC(31,536,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
4242{"srw.", XRC(31,536,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
4243{"sr.", XRC(31,536,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
252b5132 4244
1cb0a767
PB		 4245{"rrib", XRC(31,537,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4246{"rrib.", XRC(31,537,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
23976049 4247
1cb0a767
PB		 4248{"srd", XRC(31,539,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
4249{"srd.", XRC(31,539,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
f509565f 4250
1cb0a767
PB		 4251{"maskir", XRC(31,541,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4252{"maskir.", XRC(31,541,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
252b5132 4253
1cb0a767 4254{"lhdx", X(31,547), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
19a6653c 4255
1cb0a767 4256{"bbelr", X(31,550), X_MASK, PPCBRLK, PPCNONE, {0}},
418c1742 4257
1cb0a767
PB		 4258{"lvrx", X(31,551), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
4259{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
252b5132 4260
1cb0a767
PB		 4261{"subfo", XO(31,40,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4262{"subo", XO(31,40,1,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
4263{"subfo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4264{"subo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
252b5132 4265
1cb0a767 4266{"tlbsync", X(31,566), 0xffffffff, PPC, PPCNONE, {0}},
252b5132 4267
1cb0a767 4268{"lfsux", X(31,567), X_MASK, COM, PPCNONE, {FRT, RAS, RB}},
252b5132 4269
1cb0a767 4270{"lwdx", X(31,579), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
19a6653c 4271
1cb0a767 4272{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
081ba1b3 4273
1cb0a767 4274{"mfsr", X(31,595), XRB_MASK|(1<<20), COM32, PPCNONE, {RT, SR}},
252b5132 4275
1cb0a767
PB		 4276{"lswi", X(31,597), X_MASK, PPCCOM, PPCNONE, {RT, RA0, NB}},
4277{"lsi", X(31,597), X_MASK, PWRCOM, PPCNONE, {RT, RA0, NB}},
252b5132 4278
1cb0a767
PB		 4279{"msync", X(31,598), 0xffffffff, BOOKE, PPCNONE, {0}},
4280{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, PPCNONE, {0}},
4281{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}},
4282{"sync", X(31,598), XSYNC_MASK, PPCCOM, PPCNONE, {LS}},
4283{"dcs", X(31,598), 0xffffffff, PWRCOM, PPCNONE, {0}},
418c1742 4284
1cb0a767 4285{"lfdx", X(31,599), X_MASK, COM, PPCNONE, {FRT, RA0, RB}},
23976049 4286
1cb0a767
PB		 4287{"lfdepx", X(31,607), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
4288{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, PPCNONE, {FRT, RB}},
252b5132 4289
1cb0a767 4290{"lddx", X(31,611), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
19a6653c 4291
1cb0a767 4292{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
081ba1b3 4293
1cb0a767
PB		 4294{"nego", XO(31,104,1,0), XORB_MASK, COM, PPCNONE, {RT, RA}},
4295{"nego.", XO(31,104,1,1), XORB_MASK, COM, PPCNONE, {RT, RA}},
252b5132 4296
1cb0a767
PB		 4297{"mulo", XO(31,107,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4298{"mulo.", XO(31,107,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
252b5132 4299
1cb0a767 4300{"mfsri", X(31,627), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
252b5132 4301
1cb0a767 4302{"dclst", X(31,630), XRB_MASK, PWRCOM, PPCNONE, {RS, RA}},
252b5132 4303
1cb0a767 4304{"lfdux", X(31,631), X_MASK, COM, PPCNONE, {FRT, RAS, RB}},
252b5132 4305
1cb0a767 4306{"stbdx", X(31,643), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
19a6653c 4307
1cb0a767
PB		 4308{"stvlx", X(31,647), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
4309{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
23976049 4310
1cb0a767
PB		 4311{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4312{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4313{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4314{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
252b5132 4315
1cb0a767
PB		 4316{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4317{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4318{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4319{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
252b5132 4320
1cb0a767 4321{"mfsrin", X(31,659), XRA_MASK, PPC32, PPCNONE, {RT, RB}},
418c1742 4322
1cb0a767 4323{"stdbrx", X(31,660), X_MASK, CELL, PPCNONE, {RS, RA0, RB}},
252b5132 4324
1cb0a767
PB		 4325{"stswx", X(31,661), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}},
4326{"stsx", X(31,661), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
418c1742 4327
1cb0a767
PB		 4328{"stwbrx", X(31,662), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}},
4329{"stbrx", X(31,662), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
252b5132 4330
1cb0a767 4331{"stfsx", X(31,663), X_MASK, COM, PPCNONE, {FRS, RA0, RB}},
ede602d7 4332
1cb0a767
PB		 4333{"srq", XRC(31,664,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4334{"srq.", XRC(31,664,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
252b5132 4335
1cb0a767
PB		 4336{"sre", XRC(31,665,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4337{"sre.", XRC(31,665,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
252b5132 4338
1cb0a767 4339{"sthdx", X(31,675), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
19a6653c 4340
1cb0a767
PB		 4341{"stvrx", X(31,679), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
4342{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
252b5132 4343
1cb0a767 4344{"stfsux", X(31,695), X_MASK, COM, PPCNONE, {FRS, RAS, RB}},
252b5132 4345
1cb0a767
PB		 4346{"sriq", XRC(31,696,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
4347{"sriq.", XRC(31,696,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
252b5132 4348
1cb0a767 4349{"stwdx", X(31,707), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
19a6653c 4350
1cb0a767 4351{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
081ba1b3 4352
1cb0a767
PB		 4353{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4354{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
4355{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4356{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
418c1742 4357
1cb0a767
PB		 4358{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4359{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
4360{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4361{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
fdd12ef3 4362
1cb0a767
PB		 4363{"stswi", X(31,725), X_MASK, PPCCOM, PPCNONE, {RS, RA0, NB}},
4364{"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}},
252b5132 4365
1cb0a767 4366{"stfdx", X(31,727), X_MASK, COM, PPCNONE, {FRS, RA0, RB}},
252b5132 4367
1cb0a767
PB		 4368{"srlq", XRC(31,728,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4369{"srlq.", XRC(31,728,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
418c1742 4370
1cb0a767
PB		 4371{"sreq", XRC(31,729,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4372{"sreq.", XRC(31,729,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
252b5132 4373
1cb0a767
PB		 4374{"stfdepx", X(31,735), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
4375{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, PPCNONE, {RT, FRB}},
252b5132 4376
1cb0a767 4377{"stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
19a6653c 4378
1cb0a767 4379{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
081ba1b3 4380
1cb0a767
PB		 4381{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4382{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
4383{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4384{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
252b5132 4385
1cb0a767
PB		 4386{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
4387{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
252b5132 4388
1cb0a767
PB		 4389{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4390{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
4391{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
4392{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
418c1742 4393
1cb0a767
PB		 4394{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4395{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4396{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4397{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
702f0fb4 4398
1cb0a767
PB		 4399{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE, PPCNONE, {RA, RB}},
4400{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
252b5132 4401
1cb0a767 4402{"stfdux", X(31,759), X_MASK, COM, PPCNONE, {FRS, RAS, RB}},
252b5132 4403
1cb0a767
PB		 4404{"srliq", XRC(31,760,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
4405{"srliq.", XRC(31,760,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
252b5132 4406
1cb0a767
PB		 4407{"lvlxl", X(31,775), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
4408{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
ede602d7 4409
1cb0a767
PB		 4410{"dozo", XO(31,264,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4411{"dozo.", XO(31,264,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
252b5132 4412
1cb0a767
PB		 4413{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4414{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4415{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
4416{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
252b5132 4417
1cb0a767
PB		 4418{"tlbivax", X(31,786), XRT_MASK, BOOKE, PPCNONE, {RA, RB}},
4419{"tlbilx", X(31,787), X_MASK, E500MC, PPCNONE, {T, RA0, RB}},
4420{"tlbilxlpid", XTO(31,787,0), XTO_MASK, E500MC, PPCNONE, {0}},
4421{"tlbilxpid", XTO(31,787,1), XTO_MASK, E500MC, PPCNONE, {0}},
4422{"tlbilxva", XTO(31,787,3), XTO_MASK, E500MC, PPCNONE, {RA0, RB}},
252b5132 4423
1cb0a767 4424{"lwzcix", X(31,789), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
252b5132 4425
1cb0a767 4426{"lhbrx", X(31,790), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
252b5132 4427
1cb0a767
PB		 4428{"lfqx", X(31,791), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}},
4429{"lfdpx", X(31,791), X_MASK, POWER6, PPCNONE, {FRT, RA, RB}},
418c1742 4430
1cb0a767
PB		 4431{"sraw", XRC(31,792,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
4432{"sra", XRC(31,792,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
4433{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
4434{"sra.", XRC(31,792,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
fdd12ef3 4435
1cb0a767
PB		 4436{"srad", XRC(31,794,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
4437{"srad.", XRC(31,794,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
252b5132 4438
1cb0a767 4439{"lfddx", X(31,803), X_MASK, E500MC, PPCNONE, {FRT, RA, RB}},
19a6653c 4440
1cb0a767 4441{"lvrxl", X(31,807), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
252b5132 4442
1cb0a767 4443{"rac", X(31,818), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
252b5132 4444
1cb0a767 4445{"lhzcix", X(31,821), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
252b5132 4446
1cb0a767 4447{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, PPCNONE, {STRM}},
252b5132 4448
1cb0a767 4449{"lfqux", X(31,823), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}},
fdd12ef3 4450
1cb0a767
PB		 4451{"srawi", XRC(31,824,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, SH}},
4452{"srai", XRC(31,824,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}},
4453{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, SH}},
4454{"srai.", XRC(31,824,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}},
702f0fb4 4455
1cb0a767
PB		 4456{"sradi", XS(31,413,0), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
4457{"sradi.", XS(31,413,1), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
e0c21649 4458
1cb0a767
PB		 4459{"divo", XO(31,331,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4460{"divo.", XO(31,331,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
252b5132 4461
1cb0a767 4462{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
9b4e5766 4463
1cb0a767 4464{"slbmfev", X(31,851), XRA_MASK, PPC64, PPCNONE, {RT, RB}},
252b5132 4465
1cb0a767 4466{"lbzcix", X(31,853), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
418c1742 4467
1cb0a767
PB		 4468{"mbar", X(31,854), X_MASK, BOOKE, PPCNONE, {MO}},
4469{"eieio", X(31,854), 0xffffffff, PPC, PPCNONE, {0}},
418c1742 4470
1cb0a767 4471{"lfiwax", X(31,855), X_MASK, POWER6, PPCNONE, {FRT, RA0, RB}},
418c1742 4472
1cb0a767
PB		 4473{"abso", XO(31,360,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
4474{"abso.", XO(31,360,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
702f0fb4 4475
1cb0a767
PB		 4476{"divso", XO(31,363,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4477{"divso.", XO(31,363,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
252b5132 4478
1cb0a767 4479{"lxvd2ux", X(31,876), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
9b4e5766 4480
1cb0a767 4481{"ldcix", X(31,885), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
252b5132 4482
1cb0a767
PB		 4483{"stvlxl", X(31,903), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
4484{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
252b5132 4485
1cb0a767
PB		 4486{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, PPCNONE, {RTO, RA, RB}},
4487{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, PPCNONE, {RTO, RA, RB}},
252b5132 4488
1cb0a767 4489{"slbmfee", X(31,915), XRA_MASK, PPC64, PPCNONE, {RT, RB}},
702f0fb4 4490
1cb0a767 4491{"stwcix", X(31,917), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
f5c120c5 4492
1cb0a767 4493{"sthbrx", X(31,918), X_MASK, COM, PPCNONE, {RS, RA0, RB}},
252b5132 4494
1cb0a767
PB		 4495{"stfqx", X(31,919), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}},
4496{"stfdpx", X(31,919), X_MASK, POWER6, PPCNONE, {FRS, RA, RB}},
6ba045b1 4497
1cb0a767
PB		 4498{"sraq", XRC(31,920,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4499{"sraq.", XRC(31,920,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
702f0fb4 4500
1cb0a767
PB		 4501{"srea", XRC(31,921,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4502{"srea.", XRC(31,921,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
252b5132 4503
1cb0a767
PB		 4504{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}},
4505{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
4506{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}},
4507{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
702f0fb4 4508
1cb0a767 4509{"stfddx", X(31,931), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}},
19a6653c 4510
1cb0a767 4511{"stvrxl", X(31,935), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
6ba045b1 4512
1cb0a767
PB		 4513{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
4514{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
4515{"tlbre", X(31,946), X_MASK, PPC403|BOOKE, PPCNONE, {RSO, RAOPT, SHO}},
702f0fb4 4516
1cb0a767 4517{"sthcix", X(31,949), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
252b5132 4518
1cb0a767 4519{"stfqux", X(31,951), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}},
252b5132 4520
1cb0a767
PB		 4521{"sraiq", XRC(31,952,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
4522{"sraiq.", XRC(31,952,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
252b5132 4523
1cb0a767
PB		 4524{"extsb", XRC(31,954,0), XRB_MASK, PPC, PPCNONE, {RA, RS}},
4525{"extsb.", XRC(31,954,1), XRB_MASK, PPC, PPCNONE, {RA, RS}},
252b5132 4526
1cb0a767 4527{"iccci", X(31,966), XRT_MASK, PPC403|PPC440, PPCNONE, {RA, RB}},
418c1742 4528
1cb0a767
PB		 4529{"divduo", XO(31,457,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
4530{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
702f0fb4 4531
1cb0a767
PB		 4532{"divwuo", XO(31,459,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4533{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
252b5132 4534
1cb0a767 4535{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
9b4e5766 4536
1cb0a767
PB		 4537{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
4538{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
4539{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE, PPCNONE, {RSO, RAOPT, SHO}},
4540{"tlbld", X(31,978), XRTRA_MASK, PPC, PPCNONE, {RB}},
418c1742 4541
1cb0a767 4542{"stbcix", X(31,981), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
252b5132 4543
1cb0a767 4544{"icbi", X(31,982), XRT_MASK, PPC, PPCNONE, {RA, RB}},
252b5132 4545
1cb0a767 4546{"stfiwx", X(31,983), X_MASK, PPC, PPCNONE, {FRS, RA0, RB}},
702f0fb4 4547
1cb0a767
PB		 4548{"extsw", XRC(31,986,0), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
4549{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
252b5132 4550
1cb0a767 4551{"icbiep", XRT(31,991,0), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
19a6653c 4552
1cb0a767 4553{"icread", X(31,998), XRT_MASK, PPC403|PPC440, PPCNONE, {RA, RB}},
252b5132 4554
1cb0a767
PB		 4555{"nabso", XO(31,488,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
4556{"nabso.", XO(31,488,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
252b5132 4557
1cb0a767
PB		 4558{"divdo", XO(31,489,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
4559{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
418c1742 4560
1cb0a767
PB		 4561{"divwo", XO(31,491,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
4562{"divwo.", XO(31,491,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
702f0fb4 4563
1cb0a767 4564{"stxvd2ux", X(31,1004), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
9b4e5766 4565
1cb0a767 4566{"tlbli", X(31,1010), XRTRA_MASK, PPC, PPCNONE, {RB}},
252b5132 4567
1cb0a767 4568{"stdcix", X(31,1013), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
418c1742 4569
1cb0a767
PB		 4570{"dcbz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA, RB}},
4571{"dclz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA, RB}},
786e2c0f 4572
1cb0a767 4573{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
ede602d7 4574
1cb0a767
PB		 4575{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4, PPCNONE, {RA, RB}},
4576{"dcbzl", XOPL(31,1014,1), XRT_MASK, PPCCOM|E500MC,POWER4, {RA, RB}},
252b5132 4577
1cb0a767
PB		 4578{"cctpl", 0x7c210b78, 0xffffffff, CELL, PPCNONE, {0}},
4579{"cctpm", 0x7c421378, 0xffffffff, CELL, PPCNONE, {0}},
4580{"cctph", 0x7c631b78, 0xffffffff, CELL, PPCNONE, {0}},
252b5132 4581
1cb0a767
PB		 4582{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
4583{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
4584{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, PPCNONE, {0}},
252b5132 4585
1cb0a767
PB		 4586{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, PPCNONE, {0}},
4587{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, PPCNONE, {0}},
4588{"db12cyc", 0x7fdef378, 0xffffffff, CELL, PPCNONE, {0}},
4589{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, PPCNONE, {0}},
252b5132 4590
1cb0a767
PB		 4591{"lwz", OP(32), OP_MASK, PPCCOM, PPCNONE, {RT, D, RA0}},
4592{"l", OP(32), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
252b5132 4593
1cb0a767
PB		 4594{"lwzu", OP(33), OP_MASK, PPCCOM, PPCNONE, {RT, D, RAL}},
4595{"lu", OP(33), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
252b5132 4596
1cb0a767 4597{"lbz", OP(34), OP_MASK, COM, PPCNONE, {RT, D, RA0}},
252b5132 4598
1cb0a767 4599{"lbzu", OP(35), OP_MASK, COM, PPCNONE, {RT, D, RAL}},
252b5132 4600
1cb0a767
PB		 4601{"stw", OP(36), OP_MASK, PPCCOM, PPCNONE, {RS, D, RA0}},
4602{"st", OP(36), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}},
252b5132 4603
1cb0a767
PB		 4604{"stwu", OP(37), OP_MASK, PPCCOM, PPCNONE, {RS, D, RAS}},
4605{"stu", OP(37), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}},
252b5132 4606
1cb0a767 4607{"stb", OP(38), OP_MASK, COM, PPCNONE, {RS, D, RA0}},
252b5132 4608
1cb0a767 4609{"stbu", OP(39), OP_MASK, COM, PPCNONE, {RS, D, RAS}},
252b5132 4610
1cb0a767 4611{"lhz", OP(40), OP_MASK, COM, PPCNONE, {RT, D, RA0}},
252b5132 4612
1cb0a767 4613{"lhzu", OP(41), OP_MASK, COM, PPCNONE, {RT, D, RAL}},
252b5132 4614
1cb0a767 4615{"lha", OP(42), OP_MASK, COM, PPCNONE, {RT, D, RA0}},
252b5132 4616
1cb0a767 4617{"lhau", OP(43), OP_MASK, COM, PPCNONE, {RT, D, RAL}},
252b5132 4618
1cb0a767 4619{"sth", OP(44), OP_MASK, COM, PPCNONE, {RS, D, RA0}},
252b5132 4620
1cb0a767 4621{"sthu", OP(45), OP_MASK, COM, PPCNONE, {RS, D, RAS}},
252b5132 4622
1cb0a767
PB		 4623{"lmw", OP(46), OP_MASK, PPCCOM, PPCNONE, {RT, D, RAM}},
4624{"lm", OP(46), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
252b5132 4625
1cb0a767
PB		 4626{"stmw", OP(47), OP_MASK, PPCCOM, PPCNONE, {RS, D, RA0}},
4627{"stm", OP(47), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}},
252b5132 4628
1cb0a767 4629{"lfs", OP(48), OP_MASK, COM, PPCNONE, {FRT, D, RA0}},
252b5132 4630
1cb0a767 4631{"lfsu", OP(49), OP_MASK, COM, PPCNONE, {FRT, D, RAS}},
252b5132 4632
1cb0a767 4633{"lfd", OP(50), OP_MASK, COM, PPCNONE, {FRT, D, RA0}},
252b5132 4634
1cb0a767 4635{"lfdu", OP(51), OP_MASK, COM, PPCNONE, {FRT, D, RAS}},
252b5132 4636
1cb0a767 4637{"stfs", OP(52), OP_MASK, COM, PPCNONE, {FRS, D, RA0}},
adadcc0c 4638
1cb0a767 4639{"stfsu", OP(53), OP_MASK, COM, PPCNONE, {FRS, D, RAS}},
252b5132 4640
1cb0a767 4641{"stfd", OP(54), OP_MASK, COM, PPCNONE, {FRS, D, RA0}},
c3d65c1c 4642
1cb0a767 4643{"stfdu", OP(55), OP_MASK, COM, PPCNONE, {FRS, D, RAS}},
252b5132 4644
1cb0a767 4645{"lq", OP(56), OP_MASK, POWER4, PPCNONE, {RTQ, DQ, RAQ}},
c3d65c1c 4646
1cb0a767 4647{"lfq", OP(56), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}},
702f0fb4 4648
1cb0a767 4649{"psq_l", OP(56), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}},
418c1742 4650
1cb0a767 4651{"lfqu", OP(57), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}},
802a735e 4652
1cb0a767 4653{"psq_lu", OP(57), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}},
802a735e 4654
1cb0a767 4655{"lfdp", OP(57), OP_MASK, POWER6, PPCNONE, {FRT, D, RA0}},
fdd12ef3 4656
1cb0a767
PB		 4657{"ld", DSO(58,0), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}},
4658{"ldu", DSO(58,1), DS_MASK, PPC64, PPCNONE, {RT, DS, RAL}},
4659{"lwa", DSO(58,2), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}},
702f0fb4 4660
1cb0a767
PB		 4661{"dadd", XRC(59,2,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
4662{"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
252b5132 4663
1cb0a767
PB		 4664{"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}},
4665{"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}},
252b5132 4666
1cb0a767
PB		 4667{"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}},
4668{"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}},
252b5132 4669
1cb0a767
PB		 4670{"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}},
4671{"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}},
252b5132 4672
1cb0a767
PB		 4673{"fadds", A(59,21,0), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}},
4674{"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}},
252b5132 4675
1cb0a767
PB		 4676{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, PPCNONE, {FRT, FRB}},
4677{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, PPCNONE, {FRT, FRB}},
252b5132 4678
1cb0a767
PB		 4679{"fres", A(59,24,0), AFRALFRC_MASK, PPC, PPCNONE, {FRT, FRB, A_L}},
4680{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, PPCNONE, {FRT, FRB, A_L}},
1ed8e1e4 4681
1cb0a767
PB		 4682{"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCNONE, {FRT, FRA, FRC}},
4683{"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCNONE, {FRT, FRA, FRC}},
252b5132 4684
1cb0a767
PB		 4685{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, PPCNONE, {FRT, FRB, A_L}},
4686{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, PPCNONE, {FRT, FRB, A_L}},
252b5132 4687
1cb0a767
PB		 4688{"fmsubs", A(59,28,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
4689{"fmsubs.", A(59,28,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
252b5132 4690
1cb0a767
PB		 4691{"fmadds", A(59,29,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
4692{"fmadds.", A(59,29,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
252b5132 4693
1cb0a767
PB		 4694{"fnmsubs", A(59,30,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
4695{"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
702f0fb4 4696
1cb0a767
PB		 4697{"fnmadds", A(59,31,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
4698{"fnmadds.", A(59,31,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
702f0fb4 4699
1cb0a767
PB		 4700{"dmul", XRC(59,34,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
4701{"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
702f0fb4 4702
1cb0a767
PB		 4703{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
4704{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
702f0fb4 4705
1cb0a767
PB		 4706{"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
4707{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
702f0fb4 4708
1cb0a767
PB		 4709{"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCNONE, {TE, FRT,FRB,RMC}},
4710{"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCNONE, {TE, FRT,FRB,RMC}},
702f0fb4 4711
1cb0a767
PB		 4712{"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
4713{"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
702f0fb4 4714
1cb0a767
PB		 4715{"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
4716{"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
702f0fb4 4717
1cb0a767 4718{"dcmpo", X(59,130), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
702f0fb4 4719
1cb0a767
PB		 4720{"dtstex", X(59,162), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
4721{"dtstdc", Z(59,194), Z_MASK, POWER6, PPCNONE, {BF, FRA, DCM}},
4722{"dtstdg", Z(59,226), Z_MASK, POWER6, PPCNONE, {BF, FRA, DGM}},
702f0fb4 4723
1cb0a767
PB		 4724{"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
4725{"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
702f0fb4 4726
1cb0a767
PB		 4727{"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
4728{"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
702f0fb4 4729
1cb0a767
PB		 4730{"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
4731{"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
702f0fb4 4732
1cb0a767
PB		 4733{"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}},
4734{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}},
702f0fb4 4735
1cb0a767
PB		 4736{"dxex", XRC(59,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
4737{"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
702f0fb4 4738
1cb0a767
PB		 4739{"dsub", XRC(59,514,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
4740{"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
702f0fb4 4741
1cb0a767
PB		 4742{"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
4743{"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
702f0fb4 4744
1cb0a767 4745{"dcmpu", X(59,642), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
702f0fb4 4746
1cb0a767 4747{"dtstsf", X(59,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
702f0fb4 4748
1cb0a767
PB		 4749{"drsp", XRC(59,770,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
4750{"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
702f0fb4 4751
1cb0a767
PB		 4752{"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}},
4753{"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}},
252b5132 4754
1cb0a767
PB		 4755{"diex", XRC(59,866,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
4756{"diex.", XRC(59,866,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
8dbcd839 4757
1cb0a767 4758{"stfq", OP(60), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}},
252b5132 4759
1cb0a767 4760{"psq_st", OP(60), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
9b4e5766 4761
1cb0a767
PB		 4762{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
4763{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
4764{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, DM}},
4765{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
4766{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
9b4e5766 4767
1cb0a767 4768{"psq_stu", OP(61), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
702f0fb4 4769
1cb0a767 4770{"stfqu", OP(61), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}},
418c1742 4771
1cb0a767 4772{"stfdp", OP(61), OP_MASK, POWER6, PPCNONE, {FRT, D, RA0}},
802a735e 4773
1cb0a767
PB		 4774{"std", DSO(62,0), DS_MASK, PPC64, PPCNONE, {RS, DS, RA0}},
4775{"stdu", DSO(62,1), DS_MASK, PPC64, PPCNONE, {RS, DS, RAS}},
4776{"stq", DSO(62,2), DS_MASK, POWER4, PPCNONE, {RSQ, DS, RA0}},
fdd12ef3 4777
1cb0a767 4778{"fcmpu", X(63,0), X_MASK|(3<<21), COM, PPCNONE, {BF, FRA, FRB}},
252b5132 4779
1cb0a767
PB		 4780{"daddq", XRC(63,2,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
4781{"daddq.", XRC(63,2,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
702f0fb4 4782
1cb0a767
PB		 4783{"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
4784{"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
702f0fb4 4785
1cb0a767
PB		 4786{"fcpsgn", XRC(63,8,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
4787{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
702f0fb4 4788
1cb0a767
PB		 4789{"frsp", XRC(63,12,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
4790{"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
252b5132 4791
1cb0a767
PB		 4792{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCNONE, {FRT, FRB}},
4793{"fcir", XRC(63,14,0), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}},
4794{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCNONE, {FRT, FRB}},
4795{"fcir.", XRC(63,14,1), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}},
252b5132 4796
1cb0a767
PB		 4797{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCNONE, {FRT, FRB}},
4798{"fcirz", XRC(63,15,0), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}},
4799{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCNONE, {FRT, FRB}},
4800{"fcirz.", XRC(63,15,1), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}},
252b5132 4801
1cb0a767
PB		 4802{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}},
4803{"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
4804{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}},
4805{"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
252b5132 4806
1cb0a767
PB		 4807{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}},
4808{"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
4809{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}},
4810{"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
252b5132 4811
1cb0a767
PB		 4812{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}},
4813{"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
4814{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}},
4815{"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
252b5132 4816
1cb0a767
PB		 4817{"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, PPCNONE, {FRT, FRB}},
4818{"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, PPCNONE, {FRT, FRB}},
252b5132 4819
1cb0a767
PB		 4820{"fsel", A(63,23,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
4821{"fsel.", A(63,23,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
252b5132 4822
1cb0a767
PB		 4823{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, PPCNONE, {FRT, FRB, A_L}},
4824{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, PPCNONE, {FRT, FRB, A_L}},
1ed8e1e4 4825
1cb0a767
PB		 4826{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC}},
4827{"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}},
4828{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC}},
4829{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}},
252b5132 4830
1cb0a767
PB		 4831{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, PPCNONE, {FRT, FRB, A_L}},
4832{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, PPCNONE, {FRT, FRB, A_L}},
252b5132 4833
1cb0a767
PB		 4834{"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
4835{"fms", A(63,28,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
4836{"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
4837{"fms.", A(63,28,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
252b5132 4838
1cb0a767
PB		 4839{"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
4840{"fma", A(63,29,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
4841{"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
4842{"fma.", A(63,29,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
252b5132 4843
1cb0a767
PB		 4844{"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
4845{"fnms", A(63,30,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
4846{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
4847{"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
252b5132 4848
1cb0a767
PB		 4849{"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
4850{"fnma", A(63,31,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
4851{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
4852{"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
252b5132 4853
1cb0a767 4854{"fcmpo", X(63,32), X_MASK|(3<<21), COM, PPCNONE, {BF, FRA, FRB}},
252b5132 4855
1cb0a767
PB		 4856{"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
4857{"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
702f0fb4 4858
1cb0a767
PB		 4859{"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
4860{"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
702f0fb4 4861
1cb0a767
PB		 4862{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCNONE, {BT}},
4863{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCNONE, {BT}},
252b5132 4864
1cb0a767
PB		 4865{"fneg", XRC(63,40,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
4866{"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
252b5132 4867
1cb0a767 4868{"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}},
252b5132 4869
1cb0a767
PB		 4870{"dscliq", ZRC(63,66,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
4871{"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
702f0fb4 4872
1cb0a767
PB		 4873{"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, PPCNONE, {TE, FRT, FRB, RMC}},
4874{"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, PPCNONE, {TE, FRT, FRB, RMC}},
702f0fb4 4875
1cb0a767
PB		 4876{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCNONE, {BT}},
4877{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCNONE, {BT}},
252b5132 4878
1cb0a767
PB		 4879{"fmr", XRC(63,72,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
4880{"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
252b5132 4881
1cb0a767
PB		 4882{"dscriq", ZRC(63,98,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
4883{"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
702f0fb4 4884
1cb0a767
PB		 4885{"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
4886{"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
702f0fb4 4887
1cb0a767 4888{"dcmpoq", X(63,130), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
702f0fb4 4889
21169fcf
PB		 4890{"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6, {BFF, U}},
4891{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6, PPCNONE, {BFF, U, W}},
4892{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6, {BFF, U}},
4893{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6, PPCNONE, {BFF, U, W}},
252b5132 4894
1cb0a767
PB		 4895{"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
4896{"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
252b5132 4897
1cb0a767
PB		 4898{"dtstexq", X(63,162), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
4899{"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCNONE, {BF, FRA, DCM}},
4900{"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCNONE, {BF, FRA, DGM}},
702f0fb4 4901
1cb0a767
PB		 4902{"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
4903{"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
702f0fb4 4904
1cb0a767
PB		 4905{"dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
4906{"dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
702f0fb4 4907
1cb0a767
PB		 4908{"fabs", XRC(63,264,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
4909{"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
252b5132 4910
1cb0a767
PB		 4911{"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
4912{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
702f0fb4 4913
1cb0a767
PB		 4914{"ddedpdq", XRC(63,322,0), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}},
4915{"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}},
702f0fb4 4916
1cb0a767
PB		 4917{"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
4918{"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
702f0fb4 4919
1cb0a767
PB		 4920{"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
4921{"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
4922{"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
4923{"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
4924{"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
4925{"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
4926{"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
4927{"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
ce7a772b 4928
1cb0a767
PB		 4929{"dsubq", XRC(63,514,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
4930{"dsubq.", XRC(63,514,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
702f0fb4 4931
1cb0a767
PB		 4932{"ddivq", XRC(63,546,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
4933{"ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
702f0fb4 4934
1cb0a767
PB		 4935{"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCNONE, {FRT}},
4936{"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCNONE, {FRT}},
252b5132 4937
1cb0a767 4938{"dcmpuq", X(63,642), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
702f0fb4 4939
1cb0a767 4940{"dtstsfq", X(63,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
702f0fb4 4941
21169fcf
PB		 4942{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6, {FLM, FRB}},
4943{"mtfsf", XFL(63,711,0), XFL_MASK, POWER6, PPCNONE, {FLM, FRB, XFL_L, W}},
4944{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6, {FLM, FRB}},
4945{"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6, PPCNONE, {FLM, FRB, XFL_L, W}},
252b5132 4946
1cb0a767
PB		 4947{"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
4948{"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
702f0fb4 4949
1cb0a767
PB		 4950{"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
4951{"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
702f0fb4 4952
1cb0a767
PB		 4953{"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
4954{"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
252b5132 4955
1cb0a767
PB		 4956{"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
4957{"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
252b5132 4958
1cb0a767
PB		 4959{"denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}},
4960{"denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}},
702f0fb4 4961
1cb0a767
PB		 4962{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
4963{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
252b5132 4964
1cb0a767
PB		 4965{"diexq", XRC(63,866,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
4966{"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
702f0fb4 4967
252b5132
RH		 4968};
4969
4970const int powerpc_num_opcodes =
4971 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4972\f
4973/* The macro table. This is only used by the assembler. */
4974
4975/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4976 when x=0; 32-x when x is between 1 and 31; are negative if x is
4977 negative; and are 32 or more otherwise. This is what you want
4978 when, for instance, you are emulating a right shift by a
4979 rotate-left-and-mask, because the underlying instructions support
4980 shifts of size 0 but not shifts of size 32. By comparison, when
4981 extracting x bits from some word you want to use just 32-x, because
4982 the underlying instructions don't support extracting 0 bits but do
4983 support extracting the whole word (32 bits in this case). */
4984
4985const struct powerpc_macro powerpc_macros[] = {
de866fcc
AM		 4986{"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"},
4987{"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"},
4988{"extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)"},
4989{"extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)"},
4990{"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"},
4991{"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
4992{"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
4993{"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
4994{"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"},
4995{"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"},
4996{"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
4997{"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
4998{"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"},
4999{"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"},
5000{"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"},
5001{"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"},
5002
5003{"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
5004{"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
5005{"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
5006{"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
5007{"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
5008{"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
5009{"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
5010{"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
5011{"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
5012{"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
5013{"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
5014{"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
5015{"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
5016{"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
5017{"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5018{"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5019{"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5020{"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5021{"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
5022{"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
5023{"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
5024{"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
252b5132
RH		 5025};
5026
5027const int powerpc_num_macros =
5028 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
GDB Binutils - Deliverables
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