projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Remove empty .text disassembly
[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c
CommitLineData
252b5132 1/* ppc-opc.c -- PowerPC opcode list
112290ab 2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003
060d22b0 3 Free Software Foundation, Inc.
252b5132
RH		 4 Written by Ian Lance Taylor, Cygnus Support
5
112290ab 6 This file is part of GDB, GAS, and the GNU binutils.
252b5132 7
112290ab
NC		 8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
252b5132 12
112290ab
NC		 13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
252b5132 17
112290ab
NC		 18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
252b5132
RH		 22
23#include <stdio.h>
0d8dfecf 24#include "sysdep.h"
252b5132
RH		 25#include "opcode/ppc.h"
26#include "opintl.h"
27
28/* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
33 the .text section.
34
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
37 file. */
38\f
39/* Local insertion and extraction functions. */
40
c168870a
AM		 41static unsigned long insert_bat (unsigned long, long, int, const char **);
42static long extract_bat (unsigned long, int, int *);
43static unsigned long insert_bba (unsigned long, long, int, const char **);
44static long extract_bba (unsigned long, int, int *);
45static unsigned long insert_bd (unsigned long, long, int, const char **);
46static long extract_bd (unsigned long, int, int *);
47static unsigned long insert_bdm (unsigned long, long, int, const char **);
48static long extract_bdm (unsigned long, int, int *);
49static unsigned long insert_bdp (unsigned long, long, int, const char **);
50static long extract_bdp (unsigned long, int, int *);
c168870a
AM		 51static unsigned long insert_bo (unsigned long, long, int, const char **);
52static long extract_bo (unsigned long, int, int *);
53static unsigned long insert_boe (unsigned long, long, int, const char **);
54static long extract_boe (unsigned long, int, int *);
55static unsigned long insert_dq (unsigned long, long, int, const char **);
56static long extract_dq (unsigned long, int, int *);
57static unsigned long insert_ds (unsigned long, long, int, const char **);
58static long extract_ds (unsigned long, int, int *);
59static unsigned long insert_de (unsigned long, long, int, const char **);
60static long extract_de (unsigned long, int, int *);
61static unsigned long insert_des (unsigned long, long, int, const char **);
62static long extract_des (unsigned long, int, int *);
63static unsigned long insert_fxm (unsigned long, long, int, const char **);
64static long extract_fxm (unsigned long, int, int *);
65static unsigned long insert_li (unsigned long, long, int, const char **);
66static long extract_li (unsigned long, int, int *);
67static unsigned long insert_mbe (unsigned long, long, int, const char **);
68static long extract_mbe (unsigned long, int, int *);
69static unsigned long insert_mb6 (unsigned long, long, int, const char **);
70static long extract_mb6 (unsigned long, int, int *);
71static unsigned long insert_nb (unsigned long, long, int, const char **);
72static long extract_nb (unsigned long, int, int *);
73static unsigned long insert_nsi (unsigned long, long, int, const char **);
74static long extract_nsi (unsigned long, int, int *);
75static unsigned long insert_ral (unsigned long, long, int, const char **);
76static unsigned long insert_ram (unsigned long, long, int, const char **);
77static unsigned long insert_raq (unsigned long, long, int, const char **);
78static unsigned long insert_ras (unsigned long, long, int, const char **);
79static unsigned long insert_rbs (unsigned long, long, int, const char **);
80static long extract_rbs (unsigned long, int, int *);
81static unsigned long insert_rsq (unsigned long, long, int, const char **);
82static unsigned long insert_rtq (unsigned long, long, int, const char **);
83static unsigned long insert_sh6 (unsigned long, long, int, const char **);
84static long extract_sh6 (unsigned long, int, int *);
85static unsigned long insert_spr (unsigned long, long, int, const char **);
86static long extract_spr (unsigned long, int, int *);
87static unsigned long insert_tbr (unsigned long, long, int, const char **);
88static long extract_tbr (unsigned long, int, int *);
89static unsigned long insert_ev2 (unsigned long, long, int, const char **);
90static long extract_ev2 (unsigned long, int, int *);
91static unsigned long insert_ev4 (unsigned long, long, int, const char **);
92static long extract_ev4 (unsigned long, int, int *);
93static unsigned long insert_ev8 (unsigned long, long, int, const char **);
94static long extract_ev8 (unsigned long, int, int *);
252b5132
RH		 95\f
96/* The operands table.
97
98 The fields are bits, shift, insert, extract, flags.
99
100 We used to put parens around the various additions, like the one
101 for BA just below. However, that caused trouble with feeble
102 compilers with a limit on depth of a parenthesized expression, like
103 (reportedly) the compiler in Microsoft Developer Studio 5. So we
104 omit the parens, since the macros are never used in a context where
105 the addition will be ambiguous. */
106
107const struct powerpc_operand powerpc_operands[] =
108{
109 /* The zero index is used to indicate the end of the list of
110 operands. */
111#define UNUSED 0
11b37b7b 112 { 0, 0, 0, 0, 0 },
252b5132
RH		 113
114 /* The BA field in an XL form instruction. */
115#define BA UNUSED + 1
116#define BA_MASK (0x1f << 16)
11b37b7b 117 { 5, 16, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 118
119 /* The BA field in an XL form instruction when it must be the same
120 as the BT field in the same instruction. */
121#define BAT BA + 1
11b37b7b 122 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
252b5132
RH		 123
124 /* The BB field in an XL form instruction. */
125#define BB BAT + 1
126#define BB_MASK (0x1f << 11)
11b37b7b 127 { 5, 11, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 128
129 /* The BB field in an XL form instruction when it must be the same
130 as the BA field in the same instruction. */
131#define BBA BB + 1
11b37b7b 132 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
252b5132
RH		 133
134 /* The BD field in a B form instruction. The lower two bits are
135 forced to zero. */
136#define BD BBA + 1
11b37b7b 137 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 138
139 /* The BD field in a B form instruction when absolute addressing is
140 used. */
141#define BDA BD + 1
11b37b7b 142 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 143
144 /* The BD field in a B form instruction when the - modifier is used.
145 This sets the y bit of the BO field appropriately. */
146#define BDM BDA + 1
11b37b7b
AM		 147 { 16, 0, insert_bdm, extract_bdm,
148 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 149
150 /* The BD field in a B form instruction when the - modifier is used
151 and absolute address is used. */
152#define BDMA BDM + 1
11b37b7b
AM		 153 { 16, 0, insert_bdm, extract_bdm,
154 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 155
156 /* The BD field in a B form instruction when the + modifier is used.
157 This sets the y bit of the BO field appropriately. */
158#define BDP BDMA + 1
11b37b7b
AM		 159 { 16, 0, insert_bdp, extract_bdp,
160 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 161
162 /* The BD field in a B form instruction when the + modifier is used
163 and absolute addressing is used. */
164#define BDPA BDP + 1
11b37b7b
AM		 165 { 16, 0, insert_bdp, extract_bdp,
166 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 167
168 /* The BF field in an X or XL form instruction. */
169#define BF BDPA + 1
11b37b7b 170 { 3, 23, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 171
172 /* An optional BF field. This is used for comparison instructions,
173 in which an omitted BF field is taken as zero. */
174#define OBF BF + 1
11b37b7b 175 { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132
RH		 176
177 /* The BFA field in an X or XL form instruction. */
178#define BFA OBF + 1
11b37b7b 179 { 3, 18, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 180
181 /* The BI field in a B form or XL form instruction. */
182#define BI BFA + 1
183#define BI_MASK (0x1f << 16)
11b37b7b 184 { 5, 16, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 185
186 /* The BO field in a B form instruction. Certain values are
187 illegal. */
188#define BO BI + 1
189#define BO_MASK (0x1f << 21)
11b37b7b 190 { 5, 21, insert_bo, extract_bo, 0 },
252b5132
RH		 191
192 /* The BO field in a B form instruction when the + or - modifier is
193 used. This is like the BO field, but it must be even. */
194#define BOE BO + 1
11b37b7b 195 { 5, 21, insert_boe, extract_boe, 0 },
252b5132
RH		 196
197 /* The BT field in an X or XL form instruction. */
198#define BT BOE + 1
11b37b7b 199 { 5, 21, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 200
201 /* The condition register number portion of the BI field in a B form
202 or XL form instruction. This is used for the extended
203 conditional branch mnemonics, which set the lower two bits of the
204 BI field. This field is optional. */
205#define CR BT + 1
11b37b7b 206 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132 207
23976049
EZ		 208 /* The CRB field in an X form instruction. */
209#define CRB CR + 1
210 { 5, 6, 0, 0, 0 },
211
212 /* The CRFD field in an X form instruction. */
213#define CRFD CRB + 1
0ec499f7 214 { 3, 23, 0, 0, PPC_OPERAND_CR },
23976049
EZ		 215
216 /* The CRFS field in an X form instruction. */
217#define CRFS CRFD + 1
0ec499f7 218 { 3, 0, 0, 0, PPC_OPERAND_CR },
23976049 219
418c1742 220 /* The CT field in an X form instruction. */
23976049 221#define CT CRFS + 1
1f613cde 222 { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
418c1742 223
252b5132
RH		 224 /* The D field in a D form instruction. This is a displacement off
225 a register, and implies that the next operand is a register in
226 parentheses. */
418c1742 227#define D CT + 1
11b37b7b 228 { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
252b5132 229
418c1742
MG		 230 /* The DE field in a DE form instruction. This is like D, but is 12
231 bits only. */
232#define DE D + 1
233 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
234
235 /* The DES field in a DES form instruction. This is like DS, but is 14
236 bits only (12 stored.) */
237#define DES DE + 1
238 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
239
adadcc0c
AM		 240 /* The DQ field in a DQ form instruction. This is like D, but the
241 lower four bits are forced to zero. */
242#define DQ DES + 1
243 { 16, 0, insert_dq, extract_dq,
244 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
245
252b5132
RH		 246 /* The DS field in a DS form instruction. This is like D, but the
247 lower two bits are forced to zero. */
adadcc0c 248#define DS DQ + 1
6ba045b1
AM		 249 { 16, 0, insert_ds, extract_ds,
250 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
252b5132
RH		 251
252 /* The E field in a wrteei instruction. */
253#define E DS + 1
11b37b7b 254 { 1, 15, 0, 0, 0 },
252b5132
RH		 255
256 /* The FL1 field in a POWER SC form instruction. */
257#define FL1 E + 1
11b37b7b 258 { 4, 12, 0, 0, 0 },
252b5132
RH		 259
260 /* The FL2 field in a POWER SC form instruction. */
261#define FL2 FL1 + 1
11b37b7b 262 { 3, 2, 0, 0, 0 },
252b5132
RH		 263
264 /* The FLM field in an XFL form instruction. */
265#define FLM FL2 + 1
11b37b7b 266 { 8, 17, 0, 0, 0 },
252b5132
RH		 267
268 /* The FRA field in an X or A form instruction. */
269#define FRA FLM + 1
270#define FRA_MASK (0x1f << 16)
11b37b7b 271 { 5, 16, 0, 0, PPC_OPERAND_FPR },
252b5132
RH		 272
273 /* The FRB field in an X or A form instruction. */
274#define FRB FRA + 1
275#define FRB_MASK (0x1f << 11)
11b37b7b 276 { 5, 11, 0, 0, PPC_OPERAND_FPR },
252b5132
RH		 277
278 /* The FRC field in an A form instruction. */
279#define FRC FRB + 1
280#define FRC_MASK (0x1f << 6)
11b37b7b 281 { 5, 6, 0, 0, PPC_OPERAND_FPR },
252b5132
RH		 282
283 /* The FRS field in an X form instruction or the FRT field in a D, X
284 or A form instruction. */
285#define FRS FRC + 1
286#define FRT FRS
11b37b7b 287 { 5, 21, 0, 0, PPC_OPERAND_FPR },
252b5132
RH		 288
289 /* The FXM field in an XFX instruction. */
290#define FXM FRS + 1
291#define FXM_MASK (0xff << 12)
c168870a
AM		 292 { 8, 12, insert_fxm, extract_fxm, 0 },
293
294 /* Power4 version for mfcr. */
295#define FXM4 FXM + 1
296 { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
252b5132
RH		 297
298 /* The L field in a D or X form instruction. */
c168870a 299#define L FXM4 + 1
11b37b7b 300 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
252b5132
RH		 301
302 /* The LEV field in a POWER SC form instruction. */
303#define LEV L + 1
11b37b7b 304 { 7, 5, 0, 0, 0 },
252b5132
RH		 305
306 /* The LI field in an I form instruction. The lower two bits are
307 forced to zero. */
308#define LI LEV + 1
11b37b7b 309 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 310
311 /* The LI field in an I form instruction when used as an absolute
312 address. */
313#define LIA LI + 1
11b37b7b 314 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132 315
6ba045b1
AM		 316 /* The LS field in an X (sync) form instruction. */
317#define LS LIA + 1
318 { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
319
252b5132 320 /* The MB field in an M form instruction. */
6ba045b1 321#define MB LS + 1
252b5132 322#define MB_MASK (0x1f << 6)
11b37b7b 323 { 5, 6, 0, 0, 0 },
252b5132
RH		 324
325 /* The ME field in an M form instruction. */
326#define ME MB + 1
327#define ME_MASK (0x1f << 1)
11b37b7b 328 { 5, 1, 0, 0, 0 },
252b5132
RH		 329
330 /* The MB and ME fields in an M form instruction expressed a single
331 operand which is a bitmask indicating which bits to select. This
332 is a two operand form using PPC_OPERAND_NEXT. See the
333 description in opcode/ppc.h for what this means. */
334#define MBE ME + 1
11b37b7b
AM		 335 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
336 { 32, 0, insert_mbe, extract_mbe, 0 },
252b5132
RH		 337
338 /* The MB or ME field in an MD or MDS form instruction. The high
339 bit is wrapped to the low end. */
340#define MB6 MBE + 2
341#define ME6 MB6
342#define MB6_MASK (0x3f << 5)
11b37b7b 343 { 6, 5, insert_mb6, extract_mb6, 0 },
252b5132 344
9fa87a06
MG		 345 /* The MO field in an mbar instruction. */
346#define MO MB6 + 1
347 { 5, 21, 0, 0, 0 },
348
252b5132
RH		 349 /* The NB field in an X form instruction. The value 32 is stored as
350 0. */
9fa87a06 351#define NB MO + 1
11b37b7b 352 { 6, 11, insert_nb, extract_nb, 0 },
252b5132
RH		 353
354 /* The NSI field in a D form instruction. This is the same as the
355 SI field, only negated. */
356#define NSI NB + 1
357 { 16, 0, insert_nsi, extract_nsi,
11b37b7b 358 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
252b5132 359
adadcc0c 360 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
914749f6 361#define RA NSI + 1
252b5132 362#define RA_MASK (0x1f << 16)
11b37b7b 363 { 5, 16, 0, 0, PPC_OPERAND_GPR },
252b5132 364
adadcc0c
AM		 365 /* The RA field in the DQ form lq instruction, which has special
366 value restrictions. */
367#define RAQ RA + 1
368 { 5, 16, insert_raq, 0, PPC_OPERAND_GPR },
369
252b5132
RH		 370 /* The RA field in a D or X form instruction which is an updating
371 load, which means that the RA field may not be zero and may not
372 equal the RT field. */
adadcc0c 373#define RAL RAQ + 1
11b37b7b 374 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
252b5132
RH		 375
376 /* The RA field in an lmw instruction, which has special value
377 restrictions. */
378#define RAM RAL + 1
11b37b7b 379 { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
252b5132
RH		 380
381 /* The RA field in a D or X form instruction which is an updating
382 store or an updating floating point load, which means that the RA
383 field may not be zero. */
384#define RAS RAM + 1
11b37b7b 385 { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
252b5132
RH		 386
387 /* The RB field in an X, XO, M, or MDS form instruction. */
388#define RB RAS + 1
389#define RB_MASK (0x1f << 11)
11b37b7b 390 { 5, 11, 0, 0, PPC_OPERAND_GPR },
252b5132
RH		 391
392 /* The RB field in an X form instruction when it must be the same as
393 the RS field in the instruction. This is used for extended
394 mnemonics like mr. */
395#define RBS RB + 1
11b37b7b 396 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
252b5132
RH		 397
398 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
399 instruction or the RT field in a D, DS, X, XFX or XO form
400 instruction. */
401#define RS RBS + 1
402#define RT RS
403#define RT_MASK (0x1f << 21)
11b37b7b 404 { 5, 21, 0, 0, PPC_OPERAND_GPR },
252b5132 405
adadcc0c
AM		 406 /* The RS field of the DS form stq instruction, which has special
407 value restrictions. */
408#define RSQ RS + 1
409 { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR },
410
411 /* The RT field of the DQ form lq instruction, which has special
412 value restrictions. */
413#define RTQ RSQ + 1
414 { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR },
415
252b5132 416 /* The SH field in an X or M form instruction. */
adadcc0c 417#define SH RTQ + 1
252b5132 418#define SH_MASK (0x1f << 11)
11b37b7b 419 { 5, 11, 0, 0, 0 },
252b5132
RH		 420
421 /* The SH field in an MD form instruction. This is split. */
422#define SH6 SH + 1
423#define SH6_MASK ((0x1f << 11) | (1 << 1))
11b37b7b 424 { 6, 1, insert_sh6, extract_sh6, 0 },
252b5132
RH		 425
426 /* The SI field in a D form instruction. */
427#define SI SH6 + 1
11b37b7b 428 { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
252b5132
RH		 429
430 /* The SI field in a D form instruction when we accept a wide range
431 of positive values. */
432#define SISIGNOPT SI + 1
11b37b7b 433 { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
252b5132
RH		 434
435 /* The SPR field in an XFX form instruction. This is flipped--the
436 lower 5 bits are stored in the upper 5 and vice- versa. */
437#define SPR SISIGNOPT + 1
914749f6 438#define PMR SPR
252b5132 439#define SPR_MASK (0x3ff << 11)
11b37b7b 440 { 10, 11, insert_spr, extract_spr, 0 },
252b5132
RH		 441
442 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
443#define SPRBAT SPR + 1
444#define SPRBAT_MASK (0x3 << 17)
11b37b7b 445 { 2, 17, 0, 0, 0 },
252b5132
RH		 446
447 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
448#define SPRG SPRBAT + 1
449#define SPRG_MASK (0x3 << 16)
11b37b7b 450 { 2, 16, 0, 0, 0 },
252b5132
RH		 451
452 /* The SR field in an X form instruction. */
453#define SR SPRG + 1
11b37b7b 454 { 4, 16, 0, 0, 0 },
252b5132 455
f5c120c5
MG		 456 /* The STRM field in an X AltiVec form instruction. */
457#define STRM SR + 1
458#define STRM_MASK (0x3 << 21)
459 { 2, 21, 0, 0, 0 },
460
252b5132 461 /* The SV field in a POWER SC form instruction. */
f5c120c5 462#define SV STRM + 1
11b37b7b 463 { 14, 2, 0, 0, 0 },
252b5132
RH		 464
465 /* The TBR field in an XFX form instruction. This is like the SPR
466 field, but it is optional. */
467#define TBR SV + 1
11b37b7b 468 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
252b5132
RH		 469
470 /* The TO field in a D or X form instruction. */
471#define TO TBR + 1
472#define TO_MASK (0x1f << 21)
11b37b7b 473 { 5, 21, 0, 0, 0 },
252b5132
RH		 474
475 /* The U field in an X form instruction. */
476#define U TO + 1
11b37b7b 477 { 4, 12, 0, 0, 0 },
252b5132
RH		 478
479 /* The UI field in a D form instruction. */
480#define UI U + 1
11b37b7b 481 { 16, 0, 0, 0, 0 },
786e2c0f 482
112290ab 483 /* The VA field in a VA, VX or VXR form instruction. */
786e2c0f
C		 484#define VA UI + 1
485#define VA_MASK (0x1f << 16)
6ba045b1 486 { 5, 16, 0, 0, PPC_OPERAND_VR },
786e2c0f 487
112290ab 488 /* The VB field in a VA, VX or VXR form instruction. */
786e2c0f
C		 489#define VB VA + 1
490#define VB_MASK (0x1f << 11)
6ba045b1 491 { 5, 11, 0, 0, PPC_OPERAND_VR },
786e2c0f 492
112290ab 493 /* The VC field in a VA form instruction. */
786e2c0f
C		 494#define VC VB + 1
495#define VC_MASK (0x1f << 6)
6ba045b1 496 { 5, 6, 0, 0, PPC_OPERAND_VR },
786e2c0f 497
112290ab 498 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
786e2c0f
C		 499#define VD VC + 1
500#define VS VD
501#define VD_MASK (0x1f << 21)
6ba045b1 502 { 5, 21, 0, 0, PPC_OPERAND_VR },
786e2c0f 503
112290ab 504 /* The SIMM field in a VX form instruction. */
786e2c0f 505#define SIMM VD + 1
11b37b7b 506 { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
786e2c0f 507
112290ab 508 /* The UIMM field in a VX form instruction. */
786e2c0f 509#define UIMM SIMM + 1
11b37b7b 510 { 5, 16, 0, 0, 0 },
786e2c0f 511
112290ab 512 /* The SHB field in a VA form instruction. */
786e2c0f 513#define SHB UIMM + 1
11b37b7b 514 { 4, 6, 0, 0, 0 },
ff3a6ee3 515
112290ab 516 /* The other UIMM field in a EVX form instruction. */
23976049
EZ		 517#define EVUIMM SHB + 1
518 { 5, 11, 0, 0, 0 },
519
112290ab 520 /* The other UIMM field in a half word EVX form instruction. */
23976049 521#define EVUIMM_2 EVUIMM + 1
95e172a5 522 { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
23976049 523
112290ab 524 /* The other UIMM field in a word EVX form instruction. */
23976049 525#define EVUIMM_4 EVUIMM_2 + 1
95e172a5 526 { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
23976049 527
112290ab 528 /* The other UIMM field in a double EVX form instruction. */
23976049 529#define EVUIMM_8 EVUIMM_4 + 1
ced05688 530 { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
23976049 531
ff3a6ee3 532 /* The WS field. */
23976049 533#define WS EVUIMM_8 + 1
ff3a6ee3
TR		 534#define WS_MASK (0x7 << 11)
535 { 3, 11, 0, 0, 0 },
536
5ae2e65e
AM		 537 /* The L field in an mtmsrd instruction */
538#define MTMSRD_L WS + 1
539 { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL },
540
252b5132
RH		 541};
542
543/* The functions used to insert and extract complicated operands. */
544
545/* The BA field in an XL form instruction when it must be the same as
546 the BT field in the same instruction. This operand is marked FAKE.
547 The insertion function just copies the BT field into the BA field,
548 and the extraction function just checks that the fields are the
549 same. */
550
551/*ARGSUSED*/
552static unsigned long
2fbfdc41
AM		 553insert_bat (unsigned long insn,
554 long value ATTRIBUTE_UNUSED,
555 int dialect ATTRIBUTE_UNUSED,
556 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 557{
558 return insn | (((insn >> 21) & 0x1f) << 16);
559}
560
561static long
2fbfdc41
AM		 562extract_bat (unsigned long insn,
563 int dialect ATTRIBUTE_UNUSED,
564 int *invalid)
252b5132 565{
8427c424 566 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
252b5132
RH		 567 *invalid = 1;
568 return 0;
569}
570
571/* The BB field in an XL form instruction when it must be the same as
572 the BA field in the same instruction. This operand is marked FAKE.
573 The insertion function just copies the BA field into the BB field,
574 and the extraction function just checks that the fields are the
575 same. */
576
577/*ARGSUSED*/
578static unsigned long
2fbfdc41
AM		 579insert_bba (unsigned long insn,
580 long value ATTRIBUTE_UNUSED,
581 int dialect ATTRIBUTE_UNUSED,
582 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 583{
584 return insn | (((insn >> 16) & 0x1f) << 11);
585}
586
587static long
2fbfdc41
AM		 588extract_bba (unsigned long insn,
589 int dialect ATTRIBUTE_UNUSED,
590 int *invalid)
252b5132 591{
8427c424 592 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 593 *invalid = 1;
594 return 0;
595}
596
597/* The BD field in a B form instruction. The lower two bits are
598 forced to zero. */
599
600/*ARGSUSED*/
601static unsigned long
2fbfdc41
AM		 602insert_bd (unsigned long insn,
603 long value,
604 int dialect ATTRIBUTE_UNUSED,
605 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 606{
607 return insn | (value & 0xfffc);
608}
609
610/*ARGSUSED*/
611static long
2fbfdc41
AM		 612extract_bd (unsigned long insn,
613 int dialect ATTRIBUTE_UNUSED,
614 int *invalid ATTRIBUTE_UNUSED)
252b5132 615{
802a735e 616 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 617}
618
619/* The BD field in a B form instruction when the - modifier is used.
620 This modifier means that the branch is not expected to be taken.
94efba12
AM		 621 For chips built to versions of the architecture prior to version 2
622 (ie. not Power4 compatible), we set the y bit of the BO field to 1
623 if the offset is negative. When extracting, we require that the y
624 bit be 1 and that the offset be positive, since if the y bit is 0
625 we just want to print the normal form of the instruction.
626 Power4 compatible targets use two bits, "a", and "t", instead of
627 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
628 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
629 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
630 for branch on CTR. We only handle the taken/not-taken hint here. */
252b5132
RH		 631
632/*ARGSUSED*/
633static unsigned long
2fbfdc41
AM		 634insert_bdm (unsigned long insn,
635 long value,
636 int dialect,
637 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 638{
94efba12 639 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 640 {
641 if ((value & 0x8000) != 0)
642 insn |= 1 << 21;
643 }
644 else
645 {
646 if ((insn & (0x14 << 21)) == (0x04 << 21))
647 insn |= 0x02 << 21;
648 else if ((insn & (0x14 << 21)) == (0x10 << 21))
649 insn |= 0x08 << 21;
650 }
252b5132
RH		 651 return insn | (value & 0xfffc);
652}
653
654static long
2fbfdc41
AM		 655extract_bdm (unsigned long insn,
656 int dialect,
657 int *invalid)
252b5132 658{
8427c424 659 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e 660 {
8427c424
AM		 661 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
662 *invalid = 1;
802a735e 663 }
8427c424
AM		 664 else
665 {
666 if ((insn & (0x17 << 21)) != (0x06 << 21)
667 && (insn & (0x1d << 21)) != (0x18 << 21))
668 *invalid = 1;
669 }
670
802a735e 671 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 672}
673
674/* The BD field in a B form instruction when the + modifier is used.
675 This is like BDM, above, except that the branch is expected to be
676 taken. */
677
678/*ARGSUSED*/
679static unsigned long
2fbfdc41
AM		 680insert_bdp (unsigned long insn,
681 long value,
682 int dialect,
683 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 684{
94efba12 685 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 686 {
687 if ((value & 0x8000) == 0)
688 insn |= 1 << 21;
689 }
690 else
691 {
692 if ((insn & (0x14 << 21)) == (0x04 << 21))
693 insn |= 0x03 << 21;
694 else if ((insn & (0x14 << 21)) == (0x10 << 21))
695 insn |= 0x09 << 21;
696 }
252b5132
RH		 697 return insn | (value & 0xfffc);
698}
699
700static long
2fbfdc41
AM		 701extract_bdp (unsigned long insn,
702 int dialect,
703 int *invalid)
252b5132 704{
8427c424 705 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e 706 {
8427c424
AM		 707 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
708 *invalid = 1;
709 }
710 else
711 {
712 if ((insn & (0x17 << 21)) != (0x07 << 21)
713 && (insn & (0x1d << 21)) != (0x19 << 21))
714 *invalid = 1;
802a735e 715 }
8427c424 716
802a735e 717 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 718}
719
720/* Check for legal values of a BO field. */
721
722static int
2fbfdc41 723valid_bo (long value, int dialect)
252b5132 724{
94efba12 725 if ((dialect & PPC_OPCODE_POWER4) == 0)
252b5132 726 {
802a735e
AM		 727 /* Certain encodings have bits that are required to be zero.
728 These are (z must be zero, y may be anything):
729 001zy
730 011zy
731 1z00y
732 1z01y
733 1z1zz
734 */
735 switch (value & 0x14)
736 {
737 default:
738 case 0:
739 return 1;
740 case 0x4:
741 return (value & 0x2) == 0;
742 case 0x10:
743 return (value & 0x8) == 0;
744 case 0x14:
745 return value == 0x14;
746 }
747 }
748 else
749 {
750 /* Certain encodings have bits that are required to be zero.
751 These are (z must be zero, a & t may be anything):
752 0000z
753 0001z
754 0100z
755 0101z
756 001at
757 011at
758 1a00t
759 1a01t
760 1z1zz
761 */
762 if ((value & 0x14) == 0)
763 return (value & 0x1) == 0;
764 else if ((value & 0x14) == 0x14)
765 return value == 0x14;
766 else
767 return 1;
252b5132
RH		 768 }
769}
770
771/* The BO field in a B form instruction. Warn about attempts to set
772 the field to an illegal value. */
773
774static unsigned long
2fbfdc41
AM		 775insert_bo (unsigned long insn,
776 long value,
777 int dialect,
778 const char **errmsg)
252b5132 779{
8427c424 780 if (!valid_bo (value, dialect))
252b5132
RH		 781 *errmsg = _("invalid conditional option");
782 return insn | ((value & 0x1f) << 21);
783}
784
785static long
2fbfdc41
AM		 786extract_bo (unsigned long insn,
787 int dialect,
788 int *invalid)
252b5132
RH		 789{
790 long value;
791
792 value = (insn >> 21) & 0x1f;
8427c424 793 if (!valid_bo (value, dialect))
252b5132
RH		 794 *invalid = 1;
795 return value;
796}
797
798/* The BO field in a B form instruction when the + or - modifier is
799 used. This is like the BO field, but it must be even. When
800 extracting it, we force it to be even. */
801
802static unsigned long
2fbfdc41
AM		 803insert_boe (unsigned long insn,
804 long value,
805 int dialect,
806 const char **errmsg)
252b5132 807{
8427c424
AM		 808 if (!valid_bo (value, dialect))
809 *errmsg = _("invalid conditional option");
810 else if ((value & 1) != 0)
811 *errmsg = _("attempt to set y bit when using + or - modifier");
812
252b5132
RH		 813 return insn | ((value & 0x1f) << 21);
814}
815
816static long
2fbfdc41
AM		 817extract_boe (unsigned long insn,
818 int dialect,
819 int *invalid)
252b5132
RH		 820{
821 long value;
822
823 value = (insn >> 21) & 0x1f;
8427c424 824 if (!valid_bo (value, dialect))
252b5132
RH		 825 *invalid = 1;
826 return value & 0x1e;
827}
828
8427c424
AM		 829/* The DQ field in a DQ form instruction. This is like D, but the
830 lower four bits are forced to zero. */
adadcc0c
AM		 831
832/*ARGSUSED*/
833static unsigned long
2fbfdc41
AM		 834insert_dq (unsigned long insn,
835 long value,
836 int dialect ATTRIBUTE_UNUSED,
8427c424 837 const char **errmsg)
adadcc0c 838{
8427c424 839 if ((value & 0xf) != 0)
adadcc0c
AM		 840 *errmsg = _("offset not a multiple of 16");
841 return insn | (value & 0xfff0);
842}
843
844/*ARGSUSED*/
845static long
2fbfdc41
AM		 846extract_dq (unsigned long insn,
847 int dialect ATTRIBUTE_UNUSED,
848 int *invalid ATTRIBUTE_UNUSED)
adadcc0c
AM		 849{
850 return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
851}
852
23976049 853static unsigned long
2fbfdc41
AM		 854insert_ev2 (unsigned long insn,
855 long value,
856 int dialect ATTRIBUTE_UNUSED,
8427c424 857 const char **errmsg)
23976049 858{
8427c424 859 if ((value & 1) != 0)
23976049 860 *errmsg = _("offset not a multiple of 2");
8427c424 861 if ((value > 62) != 0)
23976049 862 *errmsg = _("offset greater than 62");
914749f6 863 return insn | ((value & 0x3e) << 10);
23976049
EZ		 864}
865
866static long
2fbfdc41
AM		 867extract_ev2 (unsigned long insn,
868 int dialect ATTRIBUTE_UNUSED,
869 int *invalid ATTRIBUTE_UNUSED)
23976049 870{
914749f6 871 return (insn >> 10) & 0x3e;
23976049
EZ		 872}
873
874static unsigned long
2fbfdc41
AM		 875insert_ev4 (unsigned long insn,
876 long value,
877 int dialect ATTRIBUTE_UNUSED,
8427c424 878 const char **errmsg)
23976049 879{
8427c424 880 if ((value & 3) != 0)
23976049 881 *errmsg = _("offset not a multiple of 4");
8427c424 882 if ((value > 124) != 0)
23976049 883 *errmsg = _("offset greater than 124");
914749f6 884 return insn | ((value & 0x7c) << 9);
23976049
EZ		 885}
886
887static long
2fbfdc41
AM		 888extract_ev4 (unsigned long insn,
889 int dialect ATTRIBUTE_UNUSED,
890 int *invalid ATTRIBUTE_UNUSED)
23976049 891{
914749f6 892 return (insn >> 9) & 0x7c;
23976049
EZ		 893}
894
895static unsigned long
2fbfdc41
AM		 896insert_ev8 (unsigned long insn,
897 long value,
898 int dialect ATTRIBUTE_UNUSED,
8427c424 899 const char **errmsg)
23976049 900{
8427c424 901 if ((value & 7) != 0)
23976049 902 *errmsg = _("offset not a multiple of 8");
8427c424 903 if ((value > 248) != 0)
23976049
EZ		 904 *errmsg = _("offset greater than 248");
905 return insn | ((value & 0xf8) << 8);
906}
907
908static long
2fbfdc41
AM		 909extract_ev8 (unsigned long insn,
910 int dialect ATTRIBUTE_UNUSED,
8427c424 911 int *invalid ATTRIBUTE_UNUSED)
23976049
EZ		 912{
913 return (insn >> 8) & 0xf8;
914}
915
252b5132
RH		 916/* The DS field in a DS form instruction. This is like D, but the
917 lower two bits are forced to zero. */
918
919/*ARGSUSED*/
920static unsigned long
2fbfdc41
AM		 921insert_ds (unsigned long insn,
922 long value,
923 int dialect ATTRIBUTE_UNUSED,
924 const char **errmsg)
252b5132 925{
8427c424 926 if ((value & 3) != 0)
6ba045b1 927 *errmsg = _("offset not a multiple of 4");
252b5132
RH		 928 return insn | (value & 0xfffc);
929}
930
931/*ARGSUSED*/
932static long
2fbfdc41
AM		 933extract_ds (unsigned long insn,
934 int dialect ATTRIBUTE_UNUSED,
935 int *invalid ATTRIBUTE_UNUSED)
252b5132 936{
802a735e 937 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 938}
939
418c1742
MG		 940/* The DE field in a DE form instruction. */
941
942/*ARGSUSED*/
943static unsigned long
2fbfdc41
AM		 944insert_de (unsigned long insn,
945 long value,
946 int dialect ATTRIBUTE_UNUSED,
947 const char **errmsg)
418c1742 948{
8427c424 949 if (value > 2047 || value < -2048)
418c1742
MG		 950 *errmsg = _("offset not between -2048 and 2047");
951 return insn | ((value << 4) & 0xfff0);
952}
953
954/*ARGSUSED*/
955static long
2fbfdc41
AM		 956extract_de (unsigned long insn,
957 int dialect ATTRIBUTE_UNUSED,
958 int *invalid ATTRIBUTE_UNUSED)
418c1742
MG		 959{
960 return (insn & 0xfff0) >> 4;
961}
962
963/* The DES field in a DES form instruction. */
964
965/*ARGSUSED*/
966static unsigned long
2fbfdc41
AM		 967insert_des (unsigned long insn,
968 long value,
969 int dialect ATTRIBUTE_UNUSED,
970 const char **errmsg)
418c1742 971{
8427c424 972 if (value > 8191 || value < -8192)
418c1742 973 *errmsg = _("offset not between -8192 and 8191");
8427c424 974 else if ((value & 3) != 0)
418c1742
MG		 975 *errmsg = _("offset not a multiple of 4");
976 return insn | ((value << 2) & 0xfff0);
977}
978
979/*ARGSUSED*/
980static long
2fbfdc41
AM		 981extract_des (unsigned long insn,
982 int dialect ATTRIBUTE_UNUSED,
983 int *invalid ATTRIBUTE_UNUSED)
418c1742 984{
802a735e 985 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
418c1742
MG		 986}
987
2fbfdc41
AM		 988/* FXM mask in mfcr and mtcrf instructions. */
989
990static unsigned long
991insert_fxm (unsigned long insn,
992 long value,
993 int dialect,
994 const char **errmsg)
c168870a
AM		 995{
996 /* If the optional field on mfcr is missing that means we want to use
997 the old form of the instruction that moves the whole cr. In that
998 case we'll have VALUE zero. There doesn't seem to be a way to
999 distinguish this from the case where someone writes mfcr %r3,0. */
1000 if (value == 0)
1001 ;
1002
1003 /* If only one bit of the FXM field is set, we can use the new form
1004 of the instruction, which is faster. */
1005 else if ((dialect & PPC_OPCODE_POWER4) != 0 && (value & -value) == value)
1006 insn |= 1 << 20;
1007
1008 /* Any other value on mfcr is an error. */
1009 else if ((insn & (0x3ff << 1)) == 19 << 1)
1010 {
8427c424 1011 *errmsg = _("ignoring invalid mfcr mask");
c168870a
AM		 1012 value = 0;
1013 }
1014
1015 return insn | ((value & 0xff) << 12);
1016}
1017
2fbfdc41
AM		 1018static long
1019extract_fxm (unsigned long insn,
1020 int dialect,
1021 int *invalid)
c168870a
AM		 1022{
1023 long mask = (insn >> 12) & 0xff;
1024
1025 /* Is this a Power4 insn? */
1026 if ((insn & (1 << 20)) != 0)
1027 {
1028 if ((dialect & PPC_OPCODE_POWER4) == 0)
8427c424 1029 *invalid = 1;
c168870a
AM		 1030 else
1031 {
1032 /* Exactly one bit of MASK should be set. */
8427c424 1033 if (mask == 0 || (mask & -mask) != mask)
c168870a
AM		 1034 *invalid = 1;
1035 }
1036 }
1037
1038 /* Check that non-power4 form of mfcr has a zero MASK. */
1039 else if ((insn & (0x3ff << 1)) == 19 << 1)
1040 {
8427c424 1041 if (mask != 0)
c168870a
AM		 1042 *invalid = 1;
1043 }
1044
1045 return mask;
1046}
1047
252b5132
RH		 1048/* The LI field in an I form instruction. The lower two bits are
1049 forced to zero. */
1050
1051/*ARGSUSED*/
1052static unsigned long
2fbfdc41
AM		 1053insert_li (unsigned long insn,
1054 long value,
1055 int dialect ATTRIBUTE_UNUSED,
1056 const char **errmsg)
252b5132 1057{
8427c424 1058 if ((value & 3) != 0)
252b5132
RH		 1059 *errmsg = _("ignoring least significant bits in branch offset");
1060 return insn | (value & 0x3fffffc);
1061}
1062
1063/*ARGSUSED*/
1064static long
2fbfdc41
AM		 1065extract_li (unsigned long insn,
1066 int dialect ATTRIBUTE_UNUSED,
1067 int *invalid ATTRIBUTE_UNUSED)
252b5132 1068{
802a735e 1069 return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
252b5132
RH		 1070}
1071
1072/* The MB and ME fields in an M form instruction expressed as a single
1073 operand which is itself a bitmask. The extraction function always
1074 marks it as invalid, since we never want to recognize an
1075 instruction which uses a field of this type. */
1076
1077static unsigned long
2fbfdc41
AM		 1078insert_mbe (unsigned long insn,
1079 long value,
1080 int dialect ATTRIBUTE_UNUSED,
1081 const char **errmsg)
252b5132
RH		 1082{
1083 unsigned long uval, mask;
1084 int mb, me, mx, count, last;
1085
1086 uval = value;
1087
1088 if (uval == 0)
1089 {
8427c424 1090 *errmsg = _("illegal bitmask");
252b5132
RH		 1091 return insn;
1092 }
1093
1094 mb = 0;
1095 me = 32;
1096 if ((uval & 1) != 0)
1097 last = 1;
1098 else
1099 last = 0;
1100 count = 0;
1101
1102 /* mb: location of last 0->1 transition */
1103 /* me: location of last 1->0 transition */
1104 /* count: # transitions */
1105
2fbfdc41 1106 for (mx = 0, mask = 1 << 31; mx < 32; ++mx, mask >>= 1)
252b5132
RH		 1107 {
1108 if ((uval & mask) && !last)
1109 {
1110 ++count;
1111 mb = mx;
1112 last = 1;
1113 }
1114 else if (!(uval & mask) && last)
1115 {
1116 ++count;
1117 me = mx;
1118 last = 0;
1119 }
1120 }
1121 if (me == 0)
1122 me = 32;
1123
1124 if (count != 2 && (count != 0 || ! last))
8427c424 1125 *errmsg = _("illegal bitmask");
252b5132
RH		 1126
1127 return insn | (mb << 6) | ((me - 1) << 1);
1128}
1129
1130static long
2fbfdc41
AM		 1131extract_mbe (unsigned long insn,
1132 int dialect ATTRIBUTE_UNUSED,
1133 int *invalid)
252b5132
RH		 1134{
1135 long ret;
1136 int mb, me;
1137 int i;
1138
8427c424 1139 *invalid = 1;
252b5132
RH		 1140
1141 mb = (insn >> 6) & 0x1f;
1142 me = (insn >> 1) & 0x1f;
1143 if (mb < me + 1)
1144 {
1145 ret = 0;
1146 for (i = mb; i <= me; i++)
2fbfdc41 1147 ret |= 1 << (31 - i);
252b5132
RH		 1148 }
1149 else if (mb == me + 1)
8427c424 1150 ret = ~0;
252b5132
RH		 1151 else /* (mb > me + 1) */
1152 {
2fbfdc41 1153 ret = ~0;
252b5132 1154 for (i = me + 1; i < mb; i++)
8427c424 1155 ret &= ~(1 << (31 - i));
252b5132
RH		 1156 }
1157 return ret;
1158}
1159
1160/* The MB or ME field in an MD or MDS form instruction. The high bit
1161 is wrapped to the low end. */
1162
1163/*ARGSUSED*/
1164static unsigned long
2fbfdc41
AM		 1165insert_mb6 (unsigned long insn,
1166 long value,
1167 int dialect ATTRIBUTE_UNUSED,
1168 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1169{
1170 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1171}
1172
1173/*ARGSUSED*/
1174static long
2fbfdc41
AM		 1175extract_mb6 (unsigned long insn,
1176 int dialect ATTRIBUTE_UNUSED,
1177 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1178{
1179 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1180}
1181
1182/* The NB field in an X form instruction. The value 32 is stored as
1183 0. */
1184
1185static unsigned long
2fbfdc41
AM		 1186insert_nb (unsigned long insn,
1187 long value,
1188 int dialect ATTRIBUTE_UNUSED,
1189 const char **errmsg)
252b5132
RH		 1190{
1191 if (value < 0 || value > 32)
1192 *errmsg = _("value out of range");
1193 if (value == 32)
1194 value = 0;
1195 return insn | ((value & 0x1f) << 11);
1196}
1197
1198/*ARGSUSED*/
1199static long
2fbfdc41
AM		 1200extract_nb (unsigned long insn,
1201 int dialect ATTRIBUTE_UNUSED,
1202 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1203{
1204 long ret;
1205
1206 ret = (insn >> 11) & 0x1f;
1207 if (ret == 0)
1208 ret = 32;
1209 return ret;
1210}
1211
1212/* The NSI field in a D form instruction. This is the same as the SI
1213 field, only negated. The extraction function always marks it as
1214 invalid, since we never want to recognize an instruction which uses
1215 a field of this type. */
1216
1217/*ARGSUSED*/
1218static unsigned long
2fbfdc41
AM		 1219insert_nsi (unsigned long insn,
1220 long value,
1221 int dialect ATTRIBUTE_UNUSED,
1222 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1223{
2fbfdc41 1224 return insn | (-value & 0xffff);
252b5132
RH		 1225}
1226
1227static long
2fbfdc41
AM		 1228extract_nsi (unsigned long insn,
1229 int dialect ATTRIBUTE_UNUSED,
1230 int *invalid)
252b5132 1231{
8427c424 1232 *invalid = 1;
2fbfdc41 1233 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
252b5132
RH		 1234}
1235
1236/* The RA field in a D or X form instruction which is an updating
1237 load, which means that the RA field may not be zero and may not
1238 equal the RT field. */
1239
1240static unsigned long
2fbfdc41
AM		 1241insert_ral (unsigned long insn,
1242 long value,
1243 int dialect ATTRIBUTE_UNUSED,
1244 const char **errmsg)
252b5132
RH		 1245{
1246 if (value == 0
1247 || (unsigned long) value == ((insn >> 21) & 0x1f))
1248 *errmsg = "invalid register operand when updating";
1249 return insn | ((value & 0x1f) << 16);
1250}
1251
1252/* The RA field in an lmw instruction, which has special value
1253 restrictions. */
1254
1255static unsigned long
2fbfdc41
AM		 1256insert_ram (unsigned long insn,
1257 long value,
1258 int dialect ATTRIBUTE_UNUSED,
1259 const char **errmsg)
252b5132
RH		 1260{
1261 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1262 *errmsg = _("index register in load range");
1263 return insn | ((value & 0x1f) << 16);
1264}
1265
8427c424
AM		 1266/* The RA field in the DQ form lq instruction, which has special
1267 value restrictions. */
adadcc0c
AM		 1268
1269/*ARGSUSED*/
1270static unsigned long
2fbfdc41
AM		 1271insert_raq (unsigned long insn,
1272 long value,
1273 int dialect ATTRIBUTE_UNUSED,
1274 const char **errmsg)
adadcc0c
AM		 1275{
1276 long rtvalue = (insn & RT_MASK) >> 21;
1277
8427c424 1278 if (value == rtvalue)
adadcc0c
AM		 1279 *errmsg = _("source and target register operands must be different");
1280 return insn | ((value & 0x1f) << 16);
1281}
1282
252b5132
RH		 1283/* The RA field in a D or X form instruction which is an updating
1284 store or an updating floating point load, which means that the RA
1285 field may not be zero. */
1286
1287static unsigned long
2fbfdc41
AM		 1288insert_ras (unsigned long insn,
1289 long value,
1290 int dialect ATTRIBUTE_UNUSED,
1291 const char **errmsg)
252b5132
RH		 1292{
1293 if (value == 0)
1294 *errmsg = _("invalid register operand when updating");
1295 return insn | ((value & 0x1f) << 16);
1296}
1297
1298/* The RB field in an X form instruction when it must be the same as
1299 the RS field in the instruction. This is used for extended
1300 mnemonics like mr. This operand is marked FAKE. The insertion
1301 function just copies the BT field into the BA field, and the
1302 extraction function just checks that the fields are the same. */
1303
1304/*ARGSUSED*/
1305static unsigned long
2fbfdc41
AM		 1306insert_rbs (unsigned long insn,
1307 long value ATTRIBUTE_UNUSED,
1308 int dialect ATTRIBUTE_UNUSED,
1309 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1310{
1311 return insn | (((insn >> 21) & 0x1f) << 11);
1312}
1313
1314static long
2fbfdc41
AM		 1315extract_rbs (unsigned long insn,
1316 int dialect ATTRIBUTE_UNUSED,
1317 int *invalid)
252b5132 1318{
8427c424 1319 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 1320 *invalid = 1;
1321 return 0;
1322}
1323
8427c424
AM		 1324/* The RT field of the DQ form lq instruction, which has special
1325 value restrictions. */
adadcc0c
AM		 1326
1327/*ARGSUSED*/
1328static unsigned long
2fbfdc41
AM		 1329insert_rtq (unsigned long insn,
1330 long value,
1331 int dialect ATTRIBUTE_UNUSED,
1332 const char **errmsg)
adadcc0c 1333{
8427c424 1334 if ((value & 1) != 0)
adadcc0c
AM		 1335 *errmsg = _("target register operand must be even");
1336 return insn | ((value & 0x1f) << 21);
1337}
1338
8427c424
AM		 1339/* The RS field of the DS form stq instruction, which has special
1340 value restrictions. */
adadcc0c
AM		 1341
1342/*ARGSUSED*/
1343static unsigned long
2fbfdc41
AM		 1344insert_rsq (unsigned long insn,
1345 long value ATTRIBUTE_UNUSED,
1346 int dialect ATTRIBUTE_UNUSED,
1347 const char **errmsg)
adadcc0c 1348{
8427c424 1349 if ((value & 1) != 0)
adadcc0c
AM		 1350 *errmsg = _("source register operand must be even");
1351 return insn | ((value & 0x1f) << 21);
1352}
1353
252b5132
RH		 1354/* The SH field in an MD form instruction. This is split. */
1355
1356/*ARGSUSED*/
1357static unsigned long
2fbfdc41
AM		 1358insert_sh6 (unsigned long insn,
1359 long value,
1360 int dialect ATTRIBUTE_UNUSED,
1361 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1362{
1363 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1364}
1365
1366/*ARGSUSED*/
1367static long
2fbfdc41
AM		 1368extract_sh6 (unsigned long insn,
1369 int dialect ATTRIBUTE_UNUSED,
1370 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1371{
1372 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1373}
1374
1375/* The SPR field in an XFX form instruction. This is flipped--the
1376 lower 5 bits are stored in the upper 5 and vice- versa. */
1377
1378static unsigned long
2fbfdc41
AM		 1379insert_spr (unsigned long insn,
1380 long value,
1381 int dialect ATTRIBUTE_UNUSED,
1382 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1383{
1384 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1385}
1386
1387static long
2fbfdc41
AM		 1388extract_spr (unsigned long insn,
1389 int dialect ATTRIBUTE_UNUSED,
1390 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1391{
1392 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1393}
1394
1395/* The TBR field in an XFX instruction. This is just like SPR, but it
1396 is optional. When TBR is omitted, it must be inserted as 268 (the
1397 magic number of the TB register). These functions treat 0
1398 (indicating an omitted optional operand) as 268. This means that
1399 ``mftb 4,0'' is not handled correctly. This does not matter very
1400 much, since the architecture manual does not define mftb as
1401 accepting any values other than 268 or 269. */
1402
1403#define TB (268)
1404
1405static unsigned long
2fbfdc41
AM		 1406insert_tbr (unsigned long insn,
1407 long value,
1408 int dialect ATTRIBUTE_UNUSED,
1409 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1410{
1411 if (value == 0)
1412 value = TB;
1413 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1414}
1415
1416static long
2fbfdc41
AM		 1417extract_tbr (unsigned long insn,
1418 int dialect ATTRIBUTE_UNUSED,
1419 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1420{
1421 long ret;
1422
1423 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1424 if (ret == TB)
1425 ret = 0;
1426 return ret;
1427}
1428\f
1429/* Macros used to form opcodes. */
1430
1431/* The main opcode. */
1432#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1433#define OP_MASK OP (0x3f)
1434
1435/* The main opcode combined with a trap code in the TO field of a D
1436 form instruction. Used for extended mnemonics for the trap
1437 instructions. */
1438#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1439#define OPTO_MASK (OP_MASK | TO_MASK)
1440
1441/* The main opcode combined with a comparison size bit in the L field
1442 of a D form or X form instruction. Used for extended mnemonics for
1443 the comparison instructions. */
1444#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1445#define OPL_MASK OPL (0x3f,1)
1446
1447/* An A form instruction. */
1448#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1449#define A_MASK A (0x3f, 0x1f, 1)
1450
1451/* An A_MASK with the FRB field fixed. */
1452#define AFRB_MASK (A_MASK | FRB_MASK)
1453
1454/* An A_MASK with the FRC field fixed. */
1455#define AFRC_MASK (A_MASK | FRC_MASK)
1456
1457/* An A_MASK with the FRA and FRC fields fixed. */
1458#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1459
1460/* A B form instruction. */
1461#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1462#define B_MASK B (0x3f, 1, 1)
1463
1464/* A B form instruction setting the BO field. */
1465#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1466#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1467
1468/* A BBO_MASK with the y bit of the BO field removed. This permits
1469 matching a conditional branch regardless of the setting of the y
94efba12 1470 bit. Similarly for the 'at' bits used for power4 branch hints. */
802a735e
AM		 1471#define Y_MASK (((unsigned long) 1) << 21)
1472#define AT1_MASK (((unsigned long) 3) << 21)
1473#define AT2_MASK (((unsigned long) 9) << 21)
1474#define BBOY_MASK (BBO_MASK &~ Y_MASK)
1475#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
252b5132
RH		 1476
1477/* A B form instruction setting the BO field and the condition bits of
1478 the BI field. */
1479#define BBOCB(op, bo, cb, aa, lk) \
1480 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1481#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1482
1483/* A BBOCB_MASK with the y bit of the BO field removed. */
1484#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
802a735e
AM		 1485#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1486#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
252b5132
RH		 1487
1488/* A BBOYCB_MASK in which the BI field is fixed. */
1489#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
802a735e 1490#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
252b5132 1491
23976049
EZ		 1492/* An Context form instruction. */
1493#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1494#define CTX_MASK CTX(0x3f, 0x7)
1495
1496/* An User Context form instruction. */
1497#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1498#define UCTX_MASK UCTX(0x3f, 0x1f)
1499
252b5132
RH		 1500/* The main opcode mask with the RA field clear. */
1501#define DRA_MASK (OP_MASK | RA_MASK)
1502
1503/* A DS form instruction. */
1504#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1505#define DS_MASK DSO (0x3f, 3)
1506
418c1742
MG		 1507/* A DE form instruction. */
1508#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1509#define DE_MASK DEO (0x3e, 0xf)
1510
23976049
EZ		 1511/* An EVSEL form instruction. */
1512#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1513#define EVSEL_MASK EVSEL(0x3f, 0xff)
1514
252b5132
RH		 1515/* An M form instruction. */
1516#define M(op, rc) (OP (op) | ((rc) & 1))
1517#define M_MASK M (0x3f, 1)
1518
1519/* An M form instruction with the ME field specified. */
1520#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1521
1522/* An M_MASK with the MB and ME fields fixed. */
1523#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1524
1525/* An M_MASK with the SH and ME fields fixed. */
1526#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1527
1528/* An MD form instruction. */
1529#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1530#define MD_MASK MD (0x3f, 0x7, 1)
1531
1532/* An MD_MASK with the MB field fixed. */
1533#define MDMB_MASK (MD_MASK | MB6_MASK)
1534
1535/* An MD_MASK with the SH field fixed. */
1536#define MDSH_MASK (MD_MASK | SH6_MASK)
1537
1538/* An MDS form instruction. */
1539#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1540#define MDS_MASK MDS (0x3f, 0xf, 1)
1541
1542/* An MDS_MASK with the MB field fixed. */
1543#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1544
1545/* An SC form instruction. */
1546#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1547#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1548
112290ab 1549/* An VX form instruction. */
786e2c0f
C		 1550#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1551
112290ab 1552/* The mask for an VX form instruction. */
786e2c0f
C		 1553#define VX_MASK VX(0x3f, 0x7ff)
1554
112290ab 1555/* An VA form instruction. */
2613489e 1556#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
786e2c0f 1557
112290ab 1558/* The mask for an VA form instruction. */
2613489e 1559#define VXA_MASK VXA(0x3f, 0x3f)
786e2c0f 1560
112290ab 1561/* An VXR form instruction. */
786e2c0f
C		 1562#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1563
112290ab 1564/* The mask for a VXR form instruction. */
786e2c0f
C		 1565#define VXR_MASK VXR(0x3f, 0x3ff, 1)
1566
252b5132
RH		 1567/* An X form instruction. */
1568#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1569
1570/* An X form instruction with the RC bit specified. */
1571#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1572
1573/* The mask for an X form instruction. */
1574#define X_MASK XRC (0x3f, 0x3ff, 1)
1575
1576/* An X_MASK with the RA field fixed. */
1577#define XRA_MASK (X_MASK | RA_MASK)
1578
1579/* An X_MASK with the RB field fixed. */
1580#define XRB_MASK (X_MASK | RB_MASK)
1581
1582/* An X_MASK with the RT field fixed. */
1583#define XRT_MASK (X_MASK | RT_MASK)
1584
1585/* An X_MASK with the RA and RB fields fixed. */
1586#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1587
112290ab 1588/* An XRARB_MASK, but with the L bit clear. */
5ae2e65e
AM		 1589#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1590
252b5132
RH		 1591/* An X_MASK with the RT and RA fields fixed. */
1592#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1593
98acc1c5
AM		 1594/* An XRTRA_MASK, but with L bit clear. */
1595#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1596
252b5132
RH		 1597/* An X form comparison instruction. */
1598#define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1599
1600/* The mask for an X form comparison instruction. */
1601#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1602
1603/* The mask for an X form comparison instruction with the L field
1604 fixed. */
1605#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1606
1607/* An X form trap instruction with the TO field specified. */
1608#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1609#define XTO_MASK (X_MASK | TO_MASK)
1610
e0c21649
GK		 1611/* An X form tlb instruction with the SH field specified. */
1612#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1613#define XTLB_MASK (X_MASK | SH_MASK)
1614
6ba045b1
AM		 1615/* An X form sync instruction. */
1616#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1617
1618/* An X form sync instruction with everything filled in except the LS field. */
1619#define XSYNC_MASK (0xff9fffff)
1620
f5c120c5
MG		 1621/* An X form AltiVec dss instruction. */
1622#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1623#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1624
252b5132
RH		 1625/* An XFL form instruction. */
1626#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1627#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1628
23976049
EZ		 1629/* An X form isel instruction. */
1630#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1631#define XISEL_MASK XISEL(0x3f, 0x1f)
1632
252b5132
RH		 1633/* An XL form instruction with the LK field set to 0. */
1634#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1635
1636/* An XL form instruction which uses the LK field. */
1637#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1638
1639/* The mask for an XL form instruction. */
1640#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1641
1642/* An XL form instruction which explicitly sets the BO field. */
1643#define XLO(op, bo, xop, lk) \
1644 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1645#define XLO_MASK (XL_MASK | BO_MASK)
1646
1647/* An XL form instruction which explicitly sets the y bit of the BO
1648 field. */
1649#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1650#define XLYLK_MASK (XL_MASK | Y_MASK)
1651
1652/* An XL form instruction which sets the BO field and the condition
1653 bits of the BI field. */
1654#define XLOCB(op, bo, cb, xop, lk) \
1655 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1656#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1657
1658/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1659#define XLBB_MASK (XL_MASK | BB_MASK)
1660#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1661#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1662
1663/* An XL_MASK with the BO and BB fields fixed. */
1664#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1665
1666/* An XL_MASK with the BO, BI and BB fields fixed. */
1667#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1668
1669/* An XO form instruction. */
1670#define XO(op, xop, oe, rc) \
1671 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1672#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1673
1674/* An XO_MASK with the RB field fixed. */
1675#define XORB_MASK (XO_MASK | RB_MASK)
1676
1677/* An XS form instruction. */
1678#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1679#define XS_MASK XS (0x3f, 0x1ff, 1)
1680
1681/* A mask for the FXM version of an XFX form instruction. */
c168870a 1682#define XFXFXM_MASK (X_MASK | (1 << 11))
252b5132
RH		 1683
1684/* An XFX form instruction with the FXM field filled in. */
1685#define XFXM(op, xop, fxm) \
1686 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1687
1688/* An XFX form instruction with the SPR field filled in. */
1689#define XSPR(op, xop, spr) \
1690 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1691#define XSPR_MASK (X_MASK | SPR_MASK)
1692
1693/* An XFX form instruction with the SPR field filled in except for the
1694 SPRBAT field. */
1695#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1696
1697/* An XFX form instruction with the SPR field filled in except for the
1698 SPRG field. */
1699#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1700
1701/* An X form instruction with everything filled in except the E field. */
1702#define XE_MASK (0xffff7fff)
1703
23976049
EZ		 1704/* An X form user context instruction. */
1705#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1706#define XUC_MASK XUC(0x3f, 0x1f)
1707
252b5132
RH		 1708/* The BO encodings used in extended conditional branch mnemonics. */
1709#define BODNZF (0x0)
1710#define BODNZFP (0x1)
1711#define BODZF (0x2)
1712#define BODZFP (0x3)
252b5132
RH		 1713#define BODNZT (0x8)
1714#define BODNZTP (0x9)
1715#define BODZT (0xa)
1716#define BODZTP (0xb)
802a735e
AM		 1717
1718#define BOF (0x4)
1719#define BOFP (0x5)
94efba12
AM		 1720#define BOFM4 (0x6)
1721#define BOFP4 (0x7)
252b5132
RH		 1722#define BOT (0xc)
1723#define BOTP (0xd)
94efba12
AM		 1724#define BOTM4 (0xe)
1725#define BOTP4 (0xf)
802a735e 1726
252b5132
RH		 1727#define BODNZ (0x10)
1728#define BODNZP (0x11)
1729#define BODZ (0x12)
1730#define BODZP (0x13)
94efba12
AM		 1731#define BODNZM4 (0x18)
1732#define BODNZP4 (0x19)
1733#define BODZM4 (0x1a)
1734#define BODZP4 (0x1b)
802a735e 1735
252b5132
RH		 1736#define BOU (0x14)
1737
1738/* The BI condition bit encodings used in extended conditional branch
1739 mnemonics. */
1740#define CBLT (0)
1741#define CBGT (1)
1742#define CBEQ (2)
1743#define CBSO (3)
1744
1745/* The TO encodings used in extended trap mnemonics. */
1746#define TOLGT (0x1)
1747#define TOLLT (0x2)
1748#define TOEQ (0x4)
1749#define TOLGE (0x5)
1750#define TOLNL (0x5)
1751#define TOLLE (0x6)
1752#define TOLNG (0x6)
1753#define TOGT (0x8)
1754#define TOGE (0xc)
1755#define TONL (0xc)
1756#define TOLT (0x10)
1757#define TOLE (0x14)
1758#define TONG (0x14)
1759#define TONE (0x18)
1760#define TOU (0x1f)
1761\f
1762/* Smaller names for the flags so each entry in the opcodes table will
1763 fit on a single line. */
1764#undef PPC
1765#define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY
1766#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
94efba12
AM		 1767#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1768#define POWER4 PPC_OPCODE_POWER4 | PPCCOM
802a735e
AM		 1769#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
1770#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
252b5132 1771#define PPCONLY PPC_OPCODE_PPC
418c1742 1772#define PPC403 PPC_OPCODE_403
e0c21649 1773#define PPC405 PPC403
252b5132
RH		 1774#define PPC750 PPC
1775#define PPC860 PPC
1cbbfaf9 1776#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC
252b5132
RH		 1777#define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY
1778#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1779#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1780#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
1781#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1782#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
1783#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
1784#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1785#define MFDEC1 PPC_OPCODE_POWER
dde1b132 1786#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
418c1742
MG		 1787#define BOOKE PPC_OPCODE_BOOKE
1788#define BOOKE64 PPC_OPCODE_BOOKE64
23976049
EZ		 1789#define CLASSIC PPC_OPCODE_CLASSIC
1790#define PPCSPE PPC_OPCODE_SPE
1791#define PPCISEL PPC_OPCODE_ISEL
1792#define PPCEFS PPC_OPCODE_EFS
1793#define PPCBRLK PPC_OPCODE_BRLOCK
1794#define PPCPMR PPC_OPCODE_PMR
1795#define PPCCHLK PPC_OPCODE_CACHELCK
dde1b132 1796#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
23976049 1797#define PPCRFMCI PPC_OPCODE_RFMCI
252b5132
RH		 1798\f
1799/* The opcode table.
1800
1801 The format of the opcode table is:
1802
1803 NAME OPCODE MASK FLAGS { OPERANDS }
1804
1805 NAME is the name of the instruction.
1806 OPCODE is the instruction opcode.
1807 MASK is the opcode mask; this is used to tell the disassembler
1808 which bits in the actual opcode must match OPCODE.
1809 FLAGS are flags indicated what processors support the instruction.
1810 OPERANDS is the list of operands.
1811
1812 The disassembler reads the table in order and prints the first
1813 instruction which matches, so this table is sorted to put more
1814 specific instructions before more general instructions. It is also
1815 sorted by major opcode. */
1816
1817const struct powerpc_opcode powerpc_opcodes[] = {
adadcc0c 1818{ "attn", X(0,256), X_MASK, POWER4, { 0 } },
252b5132
RH		 1819{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1820{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1821{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1822{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1823{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1824{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1825{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1826{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1827{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1828{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1829{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1830{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1831{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1832{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1833{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1834
1835{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1836{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1837{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1838{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1839{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1840{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1841{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1842{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1843{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1844{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1845{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1846{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1847{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1848{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1849{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1850{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1851{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1852{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1853{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1854{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1855{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1856{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1857{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1858{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1859{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1860{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1861{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1862{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1863{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1864{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
e0c21649
GK		 1865
1866{ "macchw", XO(4,172,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1867{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1868{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1869{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1870{ "macchws", XO(4,236,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1871{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1872{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1873{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1874{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1875{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1876{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1877{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1878{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1879{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1880{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1881{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1882{ "machhw", XO(4,44,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1883{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1884{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1885{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1886{ "machhws", XO(4,108,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1887{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1888{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1889{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1890{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1891{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1892{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1893{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1894{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1895{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1896{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1897{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1898{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1899{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1900{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1901{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1902{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1903{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1904{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1905{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1906{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1907{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1908{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1909{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1910{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1911{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1912{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1913{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1914{ "mulchw", XRC(4,168,0), X_MASK, PPC405, { RT, RA, RB } },
1915{ "mulchw.", XRC(4,168,1), X_MASK, PPC405, { RT, RA, RB } },
1916{ "mulchwu", XRC(4,136,0), X_MASK, PPC405, { RT, RA, RB } },
1917{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405, { RT, RA, RB } },
1918{ "mulhhw", XRC(4,40,0), X_MASK, PPC405, { RT, RA, RB } },
1919{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405, { RT, RA, RB } },
1920{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405, { RT, RA, RB } },
1921{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405, { RT, RA, RB } },
1922{ "mullhw", XRC(4,424,0), X_MASK, PPC405, { RT, RA, RB } },
1923{ "mullhw.", XRC(4,424,1), X_MASK, PPC405, { RT, RA, RB } },
1924{ "mullhwu", XRC(4,392,0), X_MASK, PPC405, { RT, RA, RB } },
1925{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405, { RT, RA, RB } },
1926{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1927{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1928{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1929{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1930{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1931{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1932{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1933{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1934{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1935{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1936{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1937{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1938{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1939{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1940{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1941{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1942{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1943{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1944{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1945{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1946{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1947{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1948{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1949{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } },
786e2c0f 1950{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
f5c120c5 1951{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
786e2c0f
C		 1952{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
1953{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
1954{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
1955{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
1956{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
1957{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
1958{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
1959{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
1960{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
1961{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
1962{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
1963{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
1964{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
1965{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
1966{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
1967{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
1968{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
1969{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
1970{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
1971{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1972{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1973{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1974{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1975{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1976{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1977{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1978{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1979{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1980{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1981{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1982{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1983{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1984{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1985{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1986{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1987{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1988{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1989{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1990{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1991{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1992{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1993{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1994{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1995{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1996{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1997{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1998{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1999{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2000{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2001{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
2002{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
294b41b3 2003{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
786e2c0f
C		 2004{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
2005{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
2006{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
2007{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
2008{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
2009{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
2010{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
2011{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2012{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2013{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
2014{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
2015{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
2016{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
2017{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
2018{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
2019{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
2020{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2021{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
2022{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
2023{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2024{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2025{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2026{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2027{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2028{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2029{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
d2f75a6f
GK		 2030{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2031{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2032{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
786e2c0f
C		 2033{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2034{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2035{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2036{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2037{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2038{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2039{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2040{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2041{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2042{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2043{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2044{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2045{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2046{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2047{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2048{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2049{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2050{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2051{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2052{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2053{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2054{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2055{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2056{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2057{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2058{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2059{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2060{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2061{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2062{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
2063{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2064{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2065{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2066{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2067{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2068{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
1da5001c 2069{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
786e2c0f
C		 2070{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2071{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2072{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2073{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2074{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2075{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2076{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2077{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2078{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2079{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2080{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2081{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2082{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2083{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2084{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2085{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2086{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2087{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2088{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2089{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2090{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2091{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2092{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2093{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2094{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2095{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2096{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2097{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2098{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2099{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2100{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2101{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2102{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2103{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2104{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2105{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2106{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
252b5132 2107
914749f6
AH		 2108{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2109{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2110{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2111{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2112{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2113{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2114{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2115{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2116{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2117{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2118{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2119{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2120{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2121
2122{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2123
2124{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2125{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
dde1b132 2126{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
914749f6
AH		 2127{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2128{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2129{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2130{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2131{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
dde1b132 2132{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
914749f6
AH		 2133{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2134
2135{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2136{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2137{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2138{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2139{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2140{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2141{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2142{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2143{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2144{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
fe587977
AH		 2145{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2146{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2147{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2148{ "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
23976049
EZ		 2149
2150{ "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2151{ "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2152{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2153{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2154{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
914749f6 2155{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
23976049
EZ		 2156
2157{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2158{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2159{ "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2160{ "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2161{ "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2162{ "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2163{ "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2164{ "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2165{ "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2166{ "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2167{ "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2168{ "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2169{ "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2170{ "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2171{ "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2172{ "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2173{ "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2174{ "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2175{ "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2176{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2177{ "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2178{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2179
2180{ "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2181{ "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2182{ "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2183{ "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2184{ "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2185{ "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2186{ "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2187{ "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2188{ "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2189{ "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2190{ "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2191{ "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2192{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2193{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2194
914749f6
AH		 2195{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2196{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2197{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2198{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2199{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2200{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2201{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
23976049
EZ		 2202{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2203{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2204{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2205{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2206{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2207{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
914749f6
AH		 2208{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2209{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2210{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2211{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2212{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2213{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2214{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2215{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2216{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2217{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2218
2219{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2220{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2221{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2222{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2223{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2224{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2225{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
23976049
EZ		 2226{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2227{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2228{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2229{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2230{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2231{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
914749f6
AH		 2232{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2233{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2234{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2235{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2236{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2237{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2238{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2239{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2240{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2241{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2242
914749f6
AH		 2243{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2244{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2245{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2246{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2247{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2248{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2249{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2250{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2251{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2252{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2253{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2254{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2255{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2256{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2257{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2258{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2259
2260{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2261{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2262{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2263{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2264{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2265{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2266{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2267{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2268{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2269{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2270{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2271{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2272
2273{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2274{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2275{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2276{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2277{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2278{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2279{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2280{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2281{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2282{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2283{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2284{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2285
2286{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2287{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2288{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2289{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2290{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2291{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2292
2293{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2294{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2295{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2296{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2297{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2298{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2299
2300{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2301{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2302{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2303{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2304{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2305{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2306{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2307{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2308
914749f6
AH		 2309{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2310{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2311
914749f6 2312{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
914749f6
AH		 2313{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2314{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2315{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2316
914749f6 2317{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
914749f6
AH		 2318{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2319{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2320{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2321
914749f6
AH		 2322{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2323{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2324{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2325{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2326{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2327{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2328{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2329{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2330
2331{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2332{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2333{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2334{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2335
2336{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2337{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2338{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2339{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2340
2341{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2342{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2343{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2344{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2345
2346{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2347{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2348{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2349{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2350
2351{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2352
2353{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2354{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
23976049 2355
252b5132
RH		 2356{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2357{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2358
2359{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2360{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2361
2362{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2363
418c1742
MG		 2364{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2365{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2366{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2367{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2368
252b5132
RH		 2369{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2370{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
2371{ "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } },
2372{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2373
2374{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2375{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
2376{ "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } },
2377{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2378
2379{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2380{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2381{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2382
2383{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2384{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2385{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2386
2387{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2388{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2389{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } },
2390{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } },
2391{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } },
2392{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } },
2393
2394{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2395{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2396{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } },
2397{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } },
2398{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } },
2399
112290ab
NC		 2400{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2401{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2402{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2403{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2404{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2405{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2406{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2407{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2408{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2409{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2410{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2411{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2412{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2413{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2414{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2415{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2416{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2417{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2418{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2419{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2420{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2421{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2422{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2423{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2424{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2425{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2426{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2427{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
802a735e
AM		 2428{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2429{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2430{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2431{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2432{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2433{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2434{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2435{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2436{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2437{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2438{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2439{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2440{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2441{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2442{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2443{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2444{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2445{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2446{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2447{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2448{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2449{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2450{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2451{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2452{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2453{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2454{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2455{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2456{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2457{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2458{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2459{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2460{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2461{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2462{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2463{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2464{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2465{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2466{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2467{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2468{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2469{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2470{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2471{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2472{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2473{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2474{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2475{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2476{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2477{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2478{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2479{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2480{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2481{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2482{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2483{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2484{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2485{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2486{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2487{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2488{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2489{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2490{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2491{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2492{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2493{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2494{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2495{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2496{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2497{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2498{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2499{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2500{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2501{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2502{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2503{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2504{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2505{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2506{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2507{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2508{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2509{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2510{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2511{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2512{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2513{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2514{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2515{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2516{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2517{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2518{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2519{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2520{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2521{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2522{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2523{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2524{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2525{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2526{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2527{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2528{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2529{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2530{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2531{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2532{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2533{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2534{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2535{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2536{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2537{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2538{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2539{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2540{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2541{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2542{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2543{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2544{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2545{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2546{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2547{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2548{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2549{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2550{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2551{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2552{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2553{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2554{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2555{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2556{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2557{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2558{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2559{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2560{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2561{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2562{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2563{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2564{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2565{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2566{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2567{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2568{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2569{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2570{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2571{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
94efba12
AM		 2572{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2573{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2574{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2575{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2576{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2577{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2578{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2579{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2580{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2581{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2582{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2583{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2584{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2585{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2586{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2587{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2588{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2589{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2590{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2591{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2592{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2593{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2594{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2595{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
802a735e
AM		 2596{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2597{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2598{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2599{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2600{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2601{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2602{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2603{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2604{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2605{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2606{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2607{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2608{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2609{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2610{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2611{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2612{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2613{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2614{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2615{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2616{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2617{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2618{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2619{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2620{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2621{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2622{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2623{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2624{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2625{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2626{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2627{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
94efba12
AM		 2628{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2629{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2630{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2631{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2632{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2633{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2634{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2635{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2636{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2637{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2638{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2639{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2640{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2641{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2642{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2643{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2644{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2645{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2646{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2647{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2648{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2649{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2650{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2651{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
d2f75a6f
GK		 2652{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2653{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
252b5132 2654{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
d2f75a6f
GK		 2655{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2656{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
252b5132 2657{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
d2f75a6f
GK		 2658{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2659{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
252b5132 2660{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
d2f75a6f
GK		 2661{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2662{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
252b5132
RH		 2663{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2664
2665{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
2666{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
2667{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
2668{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2669{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2670
418c1742
MG		 2671{ "b", B(18,0,0), B_MASK, COM, { LI } },
2672{ "bl", B(18,0,1), B_MASK, COM, { LI } },
2673{ "ba", B(18,1,0), B_MASK, COM, { LIA } },
2674{ "bla", B(18,1,1), B_MASK, COM, { LIA } },
252b5132 2675
112290ab 2676{ "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
252b5132
RH		 2677
2678{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2679{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2680{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2681{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2682{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12
AM		 2683{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2684{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2685{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2686{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2687{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12
AM		 2688{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2689{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2690{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2691{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2692{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12
AM		 2693{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2694{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2695{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2696{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2697{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12
AM		 2698{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2699{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2700{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2701{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2702{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2703{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2704{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2705{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2706{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2707{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2708{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2709{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2710{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2711{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2712{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2713{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2714{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2715{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2716{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2717{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2718{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2719{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2720{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2721{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2722{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2723{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2724{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2725{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2726{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2727{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2728{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2729{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2730{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2731{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2732{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2733{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2734{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2735{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2736{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2737{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2738{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2739{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2740{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2741{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2742{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2743{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2744{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2745{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2746{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2747{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2748{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2749{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2750{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2751{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2752{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2753{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2754{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2755{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2756{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2757{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2758{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2759{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2760{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2761{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2762{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2763{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2764{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2765{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2766{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2767{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2768{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2769{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2770{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2771{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2772{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2773{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2774{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2775{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2776{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2777{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2778{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2779{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2780{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2781{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2782{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2783{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2784{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2785{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2786{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2787{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2788{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2789{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2790{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2791{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2792{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2793{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2794{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2795{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2796{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2797{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2798{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2799{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2800{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2801{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2802{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2803{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2804{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2805{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2806{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2807{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2808{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2809{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2810{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2811{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2812{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2813{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2814{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2815{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2816{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2817{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2818{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2819{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2820{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2821{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2822{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2823{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2824{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2825{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2826{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2827{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2828{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2829{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2830{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2831{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2832{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2833{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2834{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2835{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2836{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2837{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2838{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2839{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2840{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2841{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2842{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2843{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2844{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2845{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2846{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2847{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2848{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2849{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2850{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2851{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2852{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2853{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2854{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2855{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2856{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2857{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2858{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2859{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2860{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2861{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2862{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2863{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2864{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2865{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2866{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2867{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2868{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2869{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2870{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2871{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2872{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2873{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2874{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2875{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2876{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2877{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2878{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2879{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2880{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2881{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2882{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2883{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2884{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2885{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2886{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2887{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2888{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2889{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132
RH		 2890{ "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } },
2891{ "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } },
d2f75a6f
GK		 2892{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2893{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2894{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2895{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
252b5132
RH		 2896{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2897{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
418c1742
MG		 2898{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
2899{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
252b5132 2900
f509565f
GK		 2901{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
2902
252b5132
RH		 2903{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
2904{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
112290ab 2905{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
252b5132
RH		 2906
2907{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
e0c21649 2908{ "rfci", XL(19,51), 0xffffffff, PPC403, { 0 } },
9fa87a06 2909{ "rfci", XL(19,51), 0xffffffff, BOOKE, { 0 } },
252b5132
RH		 2910
2911{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
2912
2913{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
2914
2915{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
2916{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
2917
2918{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2919{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
2920
2921{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
2922
2923{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
2924
2925{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2926{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
2927
2928{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
2929
2930{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
2931{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
2932
2933{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
2934{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
2935{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2936{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2937{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2938{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2939{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2940{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2941{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2942{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2943{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2944{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2945{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2946{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2947{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2948{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2949{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2950{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2951{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2952{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2953{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2954{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2955{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2956{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2957{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2958{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2959{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2960{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2961{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2962{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2963{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2964{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2965{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2966{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2967{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2968{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2969{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2970{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2971{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2972{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2973{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2974{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2975{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2976{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2977{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2978{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2979{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2980{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2981{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2982{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2983{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2984{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2985{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2986{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2987{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2988{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2989{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2990{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2991{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2992{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2993{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2994{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2995{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2996{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2997{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2998{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2999{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3000{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3001{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3002{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3003{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3004{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3005{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3006{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3007{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3008{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3009{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3010{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3011{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3012{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3013{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3014{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3015{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3016{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3017{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3018{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3019{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3020{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3021{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3022{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3023{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3024{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3025{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3026{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3027{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3028{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3029{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3030{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3031{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3032{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3033{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3034{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3035{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3036{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3037{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3038{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3039{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3040{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3041{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3042{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3043{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3044{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3045{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3046{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3047{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3048{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3049{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3050{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 3051{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3052{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3053{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3054{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3055{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 3056{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3057{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3058{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3059{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
252b5132 3060{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 3061{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3062{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3063{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3064{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
252b5132 3065{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 3066{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3067{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3068{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3069{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
252b5132 3070{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 3071{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3072{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3073{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3074{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
252b5132 3075{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } },
d2f75a6f
GK		 3076{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3077{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
252b5132 3078{ "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } },
d2f75a6f
GK		 3079{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3080{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
252b5132
RH		 3081{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3082{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
418c1742
MG		 3083{ "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
3084{ "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
252b5132
RH		 3085
3086{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3087{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3088
3089{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3090{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3091
3092{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3093{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3094{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3095{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3096{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3097{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3098{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3099{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3100
3101{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3102{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3103
418c1742
MG		 3104{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
3105{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
3106{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
3107{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
3108
252b5132
RH		 3109{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3110{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3111{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3112{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3113{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3114{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3115
3116{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3117{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3118{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3119
3120{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3121{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3122
3123{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3124{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3125
3126{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3127{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3128
3129{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3130{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3131
3132{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3133{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3134
3135{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3136{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3137{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3138{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3139{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3140{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3141
3142{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3143{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3144
3145{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3146{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3147
3148{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3149{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3150
3151{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3152{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3153{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3154{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3155
3156{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3157{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3158
3159{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3160{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3161{ "cmp", X(31,0), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
3162{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3163
3164{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3165{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3166{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3167{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3168{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3169{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3170{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3171{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3172{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3173{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3174{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3175{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3176{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3177{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3178{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3179{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3180{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3181{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3182{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3183{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3184{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3185{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3186{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3187{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3188{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3189{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3190{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3191{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3192{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
3193{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3194{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3195
3196{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3197{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3198{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3199{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3200{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3201{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3202{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3203{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3204{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3205{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3206{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3207{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3208
3209{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3210{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3211
3212{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3213{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3214{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3215{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3216{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3217{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3218{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3219{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3220
3221{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3222{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3223
dde1b132
NC		 3224{ "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3225{ "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3226{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3227{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
23976049 3228
c168870a
AM		 3229{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4, { RT } },
3230{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
252b5132
RH		 3231
3232{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
3233
3234{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } },
3235
418c1742
MG		 3236{ "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } },
3237
252b5132
RH		 3238{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } },
3239{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3240
3241{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3242{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3243{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3244{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3245
3246{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3247{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3248{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3249{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3250
3251{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3252{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3253
3254{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3255{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3256
3257{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3258{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3259
418c1742
MG		 3260{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3261
3262{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA, RB } },
3263
252b5132
RH		 3264{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3265{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3266{ "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
3267{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3268
3269{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3270{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3271{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3272{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3273{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3274{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3275{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3276{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3277
3278{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3279
3280{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3281
3282{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3283{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3284
418c1742
MG		 3285{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3286
3287{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3288
252b5132
RH		 3289{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3290{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3291
418c1742
MG		 3292{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3293{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
252b5132
RH		 3294
3295{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3296{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3297{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3298{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3299{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3300{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3301{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3302{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3303{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3304{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3305{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3306{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3307{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3308{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3309{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3310
3311{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3312{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3313
3314{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3315{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3316
f509565f
GK		 3317{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3318
252b5132
RH		 3319{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3320
3321{ "ldarx", X(31,84), X_MASK, PPC64, { RT, RA, RB } },
3322
3323{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
3324
3325{ "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } },
3326
418c1742
MG		 3327{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3328
3329{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA, RB } },
3330
252b5132
RH		 3331{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3332{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3333{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3334{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3335
3336{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3337{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3338{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3339{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3340
f509565f
GK		 3341{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3342
2dd46b8b 3343{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
252b5132
RH		 3344
3345{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3346
3347{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3348{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3349{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3350{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3351
418c1742
MG		 3352{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA, RB } },
3353
3354{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3355
252b5132 3356{ "wrtee", X(31,131), XRARB_MASK, PPC403, { RS } },
9fa87a06 3357{ "wrtee", X(31,131), XRARB_MASK, BOOKE, { RS } },
252b5132 3358
23976049
EZ		 3359{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3360
252b5132
RH		 3361{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3362{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3363{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3364{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3365{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3366{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3367{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3368{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3369
3370{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3371{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3372{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3373{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3374{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3375{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3376{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3377{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3378
dde1b132 3379{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 3380
c168870a 3381{ "mtcr", XFXM(31,144,0xff), XRARB_MASK, COM, { RS }},
252b5132
RH		 3382{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3383
3384{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3385
3386{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA, RB } },
3387
3388{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
3389
3390{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } },
3391{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3392
418c1742
MG		 3393{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA, RB } },
3394
3395{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA, RB } },
3396
252b5132
RH		 3397{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3398{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3399
3400{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3401{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3402
3403{ "wrteei", X(31,163), XE_MASK, PPC403, { E } },
9fa87a06 3404{ "wrteei", X(31,163), XE_MASK, BOOKE, { E } },
252b5132 3405
23976049 3406{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
dde1b132 3407{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 3408
82674a1f 3409{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
f509565f 3410
252b5132
RH		 3411{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3412
3413{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3414{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA, RB } },
3415
3416{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3417{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3418
418c1742
MG		 3419{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3420
252b5132
RH		 3421{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3422{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3423{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3424{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3425{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3426{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3427{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3428{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3429
3430{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3431{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3432{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3433{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3434{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3435{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3436{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3437{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3438
3439{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3440
3441{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } },
3442
418c1742 3443{ "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } },
252b5132
RH		 3444
3445{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3446{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3447
3448{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3449{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3450
418c1742
MG		 3451{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA, RB } },
3452
23976049
EZ		 3453{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3454
252b5132
RH		 3455{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3456{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3457{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3458{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3459{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3460{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3461{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3462{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3463
3464{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3465{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3466{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3467{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3468
3469{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3470{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3471{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3472{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3473{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3474{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3475{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3476{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3477
3478{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3479{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3480{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3481{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3482{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3483{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3484{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3485{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3486
dde1b132 3487{ "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
252b5132
RH		 3488{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3489{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3490
418c1742 3491{ "dcbtst", X(31,246), XRT_MASK, PPC, { CT, RA, RB } },
252b5132
RH		 3492
3493{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3494
3495{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3496{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3497
418c1742
MG		 3498{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3499
3500{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3501
9fa87a06
MG		 3502{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3503
0152a4c6
MG		 3504{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3505
252b5132
RH		 3506{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3507{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3508{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3509{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3510
3511{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3512{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3513{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3514{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3515{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3516{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3517{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3518{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3519
c1a34e60
AM		 3520{ "tlbiel", X(31,274), XRTRA_MASK, POWER4, { RB } },
3521
418c1742
MG		 3522{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3523
252b5132
RH		 3524{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3525{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3526
418c1742 3527{ "dcbt", X(31,278), XRT_MASK, PPC, { CT, RA, RB } },
252b5132
RH		 3528
3529{ "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } },
3530
252b5132
RH		 3531{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3532{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3533
418c1742
MG		 3534{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3535
3536{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA, RB } },
3537
98acc1c5 3538{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
252b5132
RH		 3539{ "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } },
3540
3541{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3542
3543{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3544
3545{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3546{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3547
418c1742
MG		 3548{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3549
dde1b132
NC		 3550{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3551{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3552{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3553{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3554{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3555{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3556{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3557{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3558{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3559{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3560{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3561{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3562{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
252b5132
RH		 3563{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3564{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3565{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3566{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3567{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3568{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3569{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3570{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3571{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3572{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3573{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3574{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3575{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3576{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3577{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3578{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3579{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3580{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3581{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3582{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3583{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3584{ "mfdcr", X(31,323), X_MASK, PPC403, { RT, SPR } },
3585{ "mfdcr", X(31,323), X_MASK, BOOKE, { RT, SPR } },
252b5132
RH		 3586
3587{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3588{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3589{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3590{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3591
914749f6 3592{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
23976049 3593
dde1b132
NC		 3594{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3595{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3596{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3597{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3598{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3599{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3600{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3601{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3602{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3603{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3604{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3605{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3606{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3607{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3608{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3609{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3610{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3611{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3612{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
3613{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
3614{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3615{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3616{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3617{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3618{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3619{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3620{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3621{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3622{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3623{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3624{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3625{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3626{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3627{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3628{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3629{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3630{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3631{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3632{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3633{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } },
3634{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
3635{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
3636{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
914749f6 3637{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
dde1b132
NC		 3638{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3639{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3640{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
3641{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3642{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3643{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3644{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3645{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3646{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3647{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3648{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3649{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
3650{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
3651{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
3652{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3653{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
3654{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
3655{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
3656{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
3657{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
3658{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
3659{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
3660{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
3661{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
3662{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
3663{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3664{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3665{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3666{ "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3667{ "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3668{ "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3669{ "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3670{ "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3671{ "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3672{ "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3673{ "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3674{ "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3675{ "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3676{ "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3677{ "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3678{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3679{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3680{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
914749f6 3681{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
dde1b132
NC		 3682{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3683{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3684{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3685{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3686{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3687{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3688{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3689{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3690{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3691{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3692{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3693{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3694{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3695{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3696{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3697{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3698{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3699{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3700{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3701{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3702{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3703{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3704{ "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3705{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3706{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3707{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3708{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3709{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3710{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3711{ "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3712{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3713{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3714{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3715{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3716{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3717{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3718{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3719{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3720{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3721{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3722{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3723{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3724{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3725{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3726{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
e0c21649
GK		 3727{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3728{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3729{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3730{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
252b5132
RH		 3731{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3732{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
e0c21649 3733{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
252b5132 3734{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
e0c21649 3735{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
252b5132 3736{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
e0c21649 3737{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
252b5132 3738{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
e0c21649 3739{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
252b5132 3740{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
e0c21649 3741{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
252b5132 3742{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
dde1b132
NC		 3743{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
3744{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3745{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3746{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3747{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
3748{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3749{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3750{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3751{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3752{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3753{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3754{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
3755{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3756{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3757{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3758{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3759{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3760{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3761{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3762{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3763{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3764{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3765{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3766{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3767{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3768{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3769{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3770{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3771{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3772{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
252b5132
RH		 3773
3774{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } },
3775
f5c120c5
MG		 3776{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3777{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3778
252b5132
RH		 3779{ "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } },
3780
418c1742
MG		 3781{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA, RB } },
3782
f5c120c5
MG		 3783{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3784{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3785
e0c21649 3786{ "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } },
252b5132
RH		 3787
3788{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3789{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3790{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3791{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3792
3793{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3794{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3795{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3796{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3797
3798{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3799
23976049
EZ		 3800{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3801{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
42a2f80a 3802{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
252b5132
RH		 3803
3804{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3805
3806{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3807
418c1742
MG		 3808{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3809
9fa87a06
MG		 3810{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3811
23976049
EZ		 3812{ "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3813
418c1742
MG		 3814{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3815{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3816
3817{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3818{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3819
dde1b132 3820{ "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 3821
6ba045b1
AM		 3822{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3823
252b5132
RH		 3824{ "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } },
3825
3826{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3827
3828{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3829
3830{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3831
3832{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3833
3834{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3835{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3836
3837{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3838{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3839
418c1742
MG		 3840{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA, RB } },
3841
252b5132
RH		 3842{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3843
3844{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
3845
3846{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3847
418c1742
MG		 3848{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3849
252b5132
RH		 3850{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
3851{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3852{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
3853{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3854
dde1b132
NC		 3855{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RT } },
3856{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RT } },
3857{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RT } },
3858{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RT } },
3859{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RT } },
3860{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RT } },
3861{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RT } },
3862{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RT } },
3863{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RT } },
3864{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RT } },
3865{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RT } },
3866{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RT } },
3867{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RT } },
252b5132
RH		 3868{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RT } },
3869{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RT } },
3870{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RT } },
3871{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RT } },
3872{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RT } },
3873{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RT } },
3874{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RT } },
3875{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RT } },
3876{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RT } },
3877{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RT } },
3878{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RT } },
3879{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RT } },
3880{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RT } },
3881{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RT } },
3882{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RT } },
3883{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RT } },
3884{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RT } },
3885{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RT } },
3886{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RT } },
3887{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3888{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RT } },
3889{ "mtdcr", X(31,451), X_MASK, PPC403, { SPR, RS } },
3890{ "mtdcr", X(31,451), X_MASK, BOOKE, { SPR, RS } },
252b5132 3891
418c1742
MG		 3892{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3893{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3894
252b5132
RH		 3895{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3896{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3897{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3898{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3899
418c1742
MG		 3900{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3901{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3902
252b5132
RH		 3903{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
3904{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
3905{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
3906{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
3907
dde1b132
NC		 3908{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
3909{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
3910{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
3911{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
3912{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
3913{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
3914{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
3915{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
3916{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
3917{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
3918{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
3919{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
3920{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
3921{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
3922{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
3923{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
3924{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
3925{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
3926{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
3927{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
3928{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
3929{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RT } },
3930{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RT } },
3931{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RT } },
3932{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RT } },
3933{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RT } },
3934{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RT } },
3935{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RT } },
3936{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RT } },
3937{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RT } },
3938{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RT } },
3939{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RT } },
3940{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RT } },
3941{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RT } },
3942{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RT } },
3943{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RT } },
3944{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RT } },
3945{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RT } },
3946{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
3947{ "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } },
3948{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RT } },
3949{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } },
3950{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RT } },
3951{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RT } },
3952{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405, { RT } },
3953{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, BOOKE, { RS } },
3954{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405, { RT } },
3955{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, BOOKE, { RS } },
3956{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405, { RT } },
3957{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, BOOKE, { RS } },
3958{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405, { RT } },
3959{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, BOOKE, { RS } },
3960{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
3961{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
3962{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
3963{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
3964{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
3965{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
3966{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
3967{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
3968{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
3969{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
3970{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
3971{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
3972{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
3973{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
3974{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
3975{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
3976{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
3977{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
3978{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
3979{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
3980{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
3981{ "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
3982{ "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
3983{ "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
3984{ "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
3985{ "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
3986{ "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
3987{ "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
3988{ "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
3989{ "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
3990{ "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
3991{ "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
3992{ "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
3993{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
42a2f80a 3994{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
dde1b132 3995{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
914749f6 3996{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
dde1b132
NC		 3997{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3998{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3999{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4000{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4001{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
4002{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
4003{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
4004{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RT } },
4005{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RT } },
4006{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RT } },
4007{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RT } },
4008{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RT } },
4009{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RT } },
4010{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RT } },
4011{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RT } },
4012{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RT } },
4013{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RT } },
4014{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RT } },
4015{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RT } },
4016{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RT } },
4017{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RT } },
4018{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RT } },
4019{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RT } },
4020{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RT } },
4021{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RT } },
4022{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RT } },
4023{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RT } },
4024{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RT } },
4025{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RT } },
4026{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RT } },
4027{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RT } },
4028{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RT } },
4029{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RT } },
4030{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RT } },
4031{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RT } },
4032{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RT } },
4033{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RT } },
4034{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RT } },
4035{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RT } },
4036{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RT } },
4037{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RT } },
4038{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RT } },
4039{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RT } },
4040{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RT } },
4041{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RT } },
4042{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RT } },
4043{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RT } },
4044{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RT } },
4045{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RT } },
4046{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RT } },
4047{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RT } },
4048{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RT } },
4049{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RT } },
4050{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RT } },
4051{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RT } },
4052{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RT } },
4053{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RT } },
4054{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RT } },
4055{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RT } },
4056{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RT } },
4057{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RT } },
4058{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RT } },
4059{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
252b5132
RH		 4060
4061{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4062
4063{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4064{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4065
418c1742
MG		 4066{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4067
4db3857a 4068{ "dcread", X(31,486), X_MASK, PPC403, { RT, RA, RB }},
252b5132 4069
914749f6 4070{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
23976049
EZ		 4071
4072{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4073
252b5132 4074{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
418c1742 4075{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
252b5132
RH		 4076{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4077{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
418c1742 4078{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
252b5132
RH		 4079{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4080
4081{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4082{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4083{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4084{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4085
418c1742
MG		 4086{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4087{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4088
252b5132
RH		 4089{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4090{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4091{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4092{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4093
dde1b132 4094{ "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 4095
252b5132
RH		 4096{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
4097
4098{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4099
418c1742
MG		 4100{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4101
252b5132
RH		 4102{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
4103
23976049 4104{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
dde1b132 4105{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
418c1742 4106
252b5132
RH		 4107{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4108
4109{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } },
4110{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4111
4112{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA, RB } },
4113{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4114
4115{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB } },
4116
4117{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4118{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4119{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4120{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4121
4122{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4123{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4124
4125{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4126{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4127
4128{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4129{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4130
418c1742
MG		 4131{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA, RB } },
4132
4133{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA, RB } },
4134
23976049 4135{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
252b5132
RH		 4136{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4137
4138{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4139
418c1742
MG		 4140{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4141
252b5132
RH		 4142{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4143
4144{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } },
4145{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } },
4146
6ba045b1
AM		 4147{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPCONLY, { 0 } },
4148{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
b6be6416 4149{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
6ba045b1 4150{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
252b5132
RH		 4151{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4152
4153{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } },
4154
418c1742
MG		 4155{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA, RB } },
4156
252b5132
RH		 4157{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4158
4159{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4160
4161{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4162
418c1742
MG		 4163{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4164
252b5132
RH		 4165{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4166
4167{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } },
4168{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA, RB } },
4169
4170{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA, RB } },
4171{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA, RB } },
4172
4173{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA, RB } },
4174
4175{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4176{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4177
4178{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4179{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4180
418c1742
MG		 4181{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA, RB } },
4182
4183{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA, RB } },
4184
252b5132
RH		 4185{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4186
4187{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4188{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4189
418c1742
MG		 4190{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4191
252b5132
RH		 4192{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } },
4193{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB } },
4194
4195{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA, RB } },
4196
4197{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4198{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4199
4200{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4201{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4202
418c1742
MG		 4203{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA, RB } },
4204
e0c21649 4205{ "dcba", X(31,758), XRT_MASK, PPC405, { RA, RB } },
9fa87a06 4206{ "dcba", X(31,758), XRT_MASK, BOOKE, { RA, RB } },
e0c21649 4207
252b5132
RH		 4208{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4209
4210{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4211{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4212
418c1742
MG		 4213{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4214
4215{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4216
4217{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
dde1b132 4218{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
418c1742 4219
252b5132
RH		 4220{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } },
4221
4222{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4223{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4224{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4225{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4226
4227{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4228{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4229
418c1742
MG		 4230{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA, RB } },
4231
4232{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA, RB } },
4233{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA, RB } },
4234
252b5132
RH		 4235{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4236
f5c120c5 4237{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
eb0fdfed 4238{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
f5c120c5 4239
252b5132
RH		 4240{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4241{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4242{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4243{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4244
6ba045b1
AM		 4245{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4246
b6be6416 4247{ "mbar", X(31,854), X_MASK, BOOKE, { MO } },
252b5132
RH		 4248{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4249
9fa87a06
MG		 4250{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
4251{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
252b5132 4252
9fa87a06 4253{ "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
7d4a12d2 4254{ "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } },
dde1b132
NC		 4255{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4256{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
418c1742 4257
6ba045b1
AM		 4258{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4259
252b5132
RH		 4260{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } },
4261
4262{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4263{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4264
4265{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4266{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4267
4268{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4269{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4270{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4271{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4272
418c1742
MG		 4273{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA, RB } },
4274
4275{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA, RB } },
4276
2e32aab9 4277{ "tlbre", X(31,946), X_MASK, BOOKE, { 0 } },
418c1742 4278
e0c21649
GK		 4279{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4280{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
1c7c333e 4281{ "tlbre", X(31,946), X_MASK, PPC403, { RS, RA, SH } },
252b5132
RH		 4282
4283{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4284{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4285
4286{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4287{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4288
418c1742
MG		 4289{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4290
e0c21649 4291{ "iccci", X(31,966), XRT_MASK, PPC403, { RA, RB } },
252b5132 4292
2e32aab9
NC		 4293{ "tlbwe", X(31,978), X_MASK, BOOKE, { 0 } },
4294
252b5132 4295{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
e0c21649
GK		 4296
4297{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4298{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
252b5132
RH		 4299{ "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } },
4300
4301{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4302
4303{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
4304
dde1b132
NC		 4305{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4306{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
252b5132
RH		 4307
4308{ "icread", X(31,998), XRT_MASK, PPC403, { RA, RB } },
4309
418c1742
MG		 4310{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4311{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA, RB } },
4312
252b5132
RH		 4313{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4314
4315{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4316{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4317
418c1742
MG		 4318{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4319
786e2c0f
C		 4320{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4321{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4322{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4323{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4324{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4325{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4326{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4327{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4328{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4329{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4330{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4331{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4332
252b5132
RH		 4333{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } },
4334{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } },
4335
4336{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4337{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA } },
4338
4339{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA } },
4340
4341{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4342
4343{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } },
4344{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA } },
4345
4346{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4347{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA } },
4348
4349{ "stb", OP(38), OP_MASK, COM, { RS, D, RA } },
4350
4351{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4352
4353{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA } },
4354
4355{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4356
4357{ "lha", OP(42), OP_MASK, COM, { RT, D, RA } },
4358
4359{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4360
4361{ "sth", OP(44), OP_MASK, COM, { RS, D, RA } },
4362
4363{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4364
4365{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4366{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA } },
4367
4368{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } },
4369{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA } },
4370
4371{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } },
4372
4373{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4374
4375{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } },
4376
4377{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4378
4379{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } },
4380
4381{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4382
4383{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } },
4384
4385{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4386
adadcc0c
AM		 4387{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
4388
252b5132
RH		 4389{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
4390
4391{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
4392
418c1742
MG		 4393{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA } },
4394{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4395{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA } },
4396{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4397{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA } },
4398{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4399{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA } },
4400{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4401{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA } },
4402{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4403{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA } },
4404{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4405{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA } },
4406{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4407
802a735e
AM		 4408{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA } },
4409
4410{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4411
4412{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } },
4413
252b5132
RH		 4414{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4415{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4416
4417{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4418{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4419
4420{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4421{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4422
4423{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4424{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4425
4426{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4427{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4428
4429{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4430{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4431
4432{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4433{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4434
4435{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4436{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4437
4438{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4439{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4440
4441{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4442{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4443
4444{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4445
4446{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4447
418c1742 4448{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA } },
418c1742 4449{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA } },
418c1742
MG		 4450{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA } },
4451{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4452{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA } },
4453{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4454{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA } },
4455{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4456{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA } },
4457{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4458{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA } },
4459{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4460
802a735e
AM		 4461{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } },
4462
4463{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
4464
adadcc0c
AM		 4465{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA } },
4466
252b5132
RH		 4467{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4468
4469{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4470{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4471
4472{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4473{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
4474{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4475{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4476
4477{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4478{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
4479{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4480{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4481
4482{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4483{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4484{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4485{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4486
4487{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4488{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4489{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4490{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4491
4492{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4493{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4494{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4495{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4496
4497{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4498{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4499
4500{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4501{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4502
4503{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4504{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4505{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4506{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4507
4508{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4509{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4510
4511{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4512{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4513{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4514{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4515
4516{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4517{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4518{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4519{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4520
4521{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4522{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4523{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4524{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4525
4526{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4527{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4528{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4529{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4530
4531{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4532
4533{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4534{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
4535
4536{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
4537{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
4538
4539{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4540
4541{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4542{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4543
4544{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4545{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4546
4547{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4548{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4549
4550{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4551{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4552
4553{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4554{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4555
4556{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4557{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4558
4559{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
4560{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
4561
4562{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
4563{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
4564
4565{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
4566{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
4567
4568{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
4569{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
4570
4571};
4572
4573const int powerpc_num_opcodes =
4574 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4575\f
4576/* The macro table. This is only used by the assembler. */
4577
4578/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4579 when x=0; 32-x when x is between 1 and 31; are negative if x is
4580 negative; and are 32 or more otherwise. This is what you want
4581 when, for instance, you are emulating a right shift by a
4582 rotate-left-and-mask, because the underlying instructions support
4583 shifts of size 0 but not shifts of size 32. By comparison, when
4584 extracting x bits from some word you want to use just 32-x, because
4585 the underlying instructions don't support extracting 0 bits but do
4586 support extracting the whole word (32 bits in this case). */
4587
4588const struct powerpc_macro powerpc_macros[] = {
4589{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
4590{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
4591{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4592{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4593{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4594{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4595{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4596{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4597{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
4598{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
4599{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4600{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4601{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
4602{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
4603{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
4604{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
4605
4606{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
4607{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
29ef7e54
AM		 4608{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4609{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
252b5132
RH		 4610{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4611{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4612{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4613{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4614{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4615{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4616{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
4617{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
4618{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
4619{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
4620{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4621{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4622{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4623{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4624{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
4625{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
4626{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4627{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
252b5132
RH		 4628};
4629
4630const int powerpc_num_macros =
4631 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
GDB Binutils - Deliverables
This page took 0.497176 seconds and 4 git commands to generate.