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* archures.c (bfd_default_compatible): Test bits_per_word.
[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c
CommitLineData
252b5132 1/* ppc-opc.c -- PowerPC opcode list
94efba12 2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002
060d22b0 3 Free Software Foundation, Inc.
252b5132
RH		 4 Written by Ian Lance Taylor, Cygnus Support
5
6This file is part of GDB, GAS, and the GNU binutils.
7
8GDB, GAS, and the GNU binutils are free software; you can redistribute
9them and/or modify them under the terms of the GNU General Public
10License as published by the Free Software Foundation; either version
112, or (at your option) any later version.
12
13GDB, GAS, and the GNU binutils are distributed in the hope that they
14will be useful, but WITHOUT ANY WARRANTY; without even the implied
15warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16the GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
19along with this file; see the file COPYING. If not, write to the Free
20Software Foundation, 59 Temple Place - Suite 330, Boston, MA
2102111-1307, USA. */
22
23#include <stdio.h>
0d8dfecf 24#include "sysdep.h"
252b5132
RH		 25#include "opcode/ppc.h"
26#include "opintl.h"
27
28/* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
33 the .text section.
34
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
37 file. */
38\f
39/* Local insertion and extraction functions. */
40
802a735e
AM		 41static unsigned long insert_bat
42 PARAMS ((unsigned long, long, int, const char **));
43static long extract_bat
44 PARAMS ((unsigned long, int, int *));
45static unsigned long insert_bba
46 PARAMS ((unsigned long, long, int, const char **));
47static long extract_bba
48 PARAMS ((unsigned long, int, int *));
49static unsigned long insert_bd
50 PARAMS ((unsigned long, long, int, const char **));
51static long extract_bd
52 PARAMS ((unsigned long, int, int *));
53static unsigned long insert_bdm
54 PARAMS ((unsigned long, long, int, const char **));
55static long extract_bdm
56 PARAMS ((unsigned long, int, int *));
57static unsigned long insert_bdp
58 PARAMS ((unsigned long, long, int, const char **));
59static long extract_bdp
60 PARAMS ((unsigned long, int, int *));
61static int valid_bo
62 PARAMS ((long, int));
63static unsigned long insert_bo
64 PARAMS ((unsigned long, long, int, const char **));
65static long extract_bo
66 PARAMS ((unsigned long, int, int *));
67static unsigned long insert_boe
68 PARAMS ((unsigned long, long, int, const char **));
69static long extract_boe
70 PARAMS ((unsigned long, int, int *));
71static unsigned long insert_ds
72 PARAMS ((unsigned long, long, int, const char **));
73static long extract_ds
74 PARAMS ((unsigned long, int, int *));
75static unsigned long insert_de
76 PARAMS ((unsigned long, long, int, const char **));
77static long extract_de
78 PARAMS ((unsigned long, int, int *));
79static unsigned long insert_des
80 PARAMS ((unsigned long, long, int, const char **));
81static long extract_des
82 PARAMS ((unsigned long, int, int *));
83static unsigned long insert_li
84 PARAMS ((unsigned long, long, int, const char **));
85static long extract_li
86 PARAMS ((unsigned long, int, int *));
87static unsigned long insert_mbe
88 PARAMS ((unsigned long, long, int, const char **));
89static long extract_mbe
90 PARAMS ((unsigned long, int, int *));
91static unsigned long insert_mb6
92 PARAMS ((unsigned long, long, int, const char **));
93static long extract_mb6
94 PARAMS ((unsigned long, int, int *));
95static unsigned long insert_nb
96 PARAMS ((unsigned long, long, int, const char **));
97static long extract_nb
98 PARAMS ((unsigned long, int, int *));
99static unsigned long insert_nsi
100 PARAMS ((unsigned long, long, int, const char **));
101static long extract_nsi
102 PARAMS ((unsigned long, int, int *));
103static unsigned long insert_ral
104 PARAMS ((unsigned long, long, int, const char **));
105static unsigned long insert_ram
106 PARAMS ((unsigned long, long, int, const char **));
107static unsigned long insert_ras
108 PARAMS ((unsigned long, long, int, const char **));
109static unsigned long insert_rbs
110 PARAMS ((unsigned long, long, int, const char **));
111static long extract_rbs
112 PARAMS ((unsigned long, int, int *));
113static unsigned long insert_sh6
114 PARAMS ((unsigned long, long, int, const char **));
115static long extract_sh6
116 PARAMS ((unsigned long, int, int *));
117static unsigned long insert_spr
118 PARAMS ((unsigned long, long, int, const char **));
119static long extract_spr
120 PARAMS ((unsigned long, int, int *));
121static unsigned long insert_tbr
122 PARAMS ((unsigned long, long, int, const char **));
123static long extract_tbr
124 PARAMS ((unsigned long, int, int *));
252b5132
RH		 125\f
126/* The operands table.
127
128 The fields are bits, shift, insert, extract, flags.
129
130 We used to put parens around the various additions, like the one
131 for BA just below. However, that caused trouble with feeble
132 compilers with a limit on depth of a parenthesized expression, like
133 (reportedly) the compiler in Microsoft Developer Studio 5. So we
134 omit the parens, since the macros are never used in a context where
135 the addition will be ambiguous. */
136
137const struct powerpc_operand powerpc_operands[] =
138{
139 /* The zero index is used to indicate the end of the list of
140 operands. */
141#define UNUSED 0
11b37b7b 142 { 0, 0, 0, 0, 0 },
252b5132
RH		 143
144 /* The BA field in an XL form instruction. */
145#define BA UNUSED + 1
146#define BA_MASK (0x1f << 16)
11b37b7b 147 { 5, 16, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 148
149 /* The BA field in an XL form instruction when it must be the same
150 as the BT field in the same instruction. */
151#define BAT BA + 1
11b37b7b 152 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
252b5132
RH		 153
154 /* The BB field in an XL form instruction. */
155#define BB BAT + 1
156#define BB_MASK (0x1f << 11)
11b37b7b 157 { 5, 11, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 158
159 /* The BB field in an XL form instruction when it must be the same
160 as the BA field in the same instruction. */
161#define BBA BB + 1
11b37b7b 162 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
252b5132
RH		 163
164 /* The BD field in a B form instruction. The lower two bits are
165 forced to zero. */
166#define BD BBA + 1
11b37b7b 167 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 168
169 /* The BD field in a B form instruction when absolute addressing is
170 used. */
171#define BDA BD + 1
11b37b7b 172 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 173
174 /* The BD field in a B form instruction when the - modifier is used.
175 This sets the y bit of the BO field appropriately. */
176#define BDM BDA + 1
11b37b7b
AM		 177 { 16, 0, insert_bdm, extract_bdm,
178 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 179
180 /* The BD field in a B form instruction when the - modifier is used
181 and absolute address is used. */
182#define BDMA BDM + 1
11b37b7b
AM		 183 { 16, 0, insert_bdm, extract_bdm,
184 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 185
186 /* The BD field in a B form instruction when the + modifier is used.
187 This sets the y bit of the BO field appropriately. */
188#define BDP BDMA + 1
11b37b7b
AM		 189 { 16, 0, insert_bdp, extract_bdp,
190 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 191
192 /* The BD field in a B form instruction when the + modifier is used
193 and absolute addressing is used. */
194#define BDPA BDP + 1
11b37b7b
AM		 195 { 16, 0, insert_bdp, extract_bdp,
196 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 197
198 /* The BF field in an X or XL form instruction. */
199#define BF BDPA + 1
11b37b7b 200 { 3, 23, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 201
202 /* An optional BF field. This is used for comparison instructions,
203 in which an omitted BF field is taken as zero. */
204#define OBF BF + 1
11b37b7b 205 { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132
RH		 206
207 /* The BFA field in an X or XL form instruction. */
208#define BFA OBF + 1
11b37b7b 209 { 3, 18, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 210
211 /* The BI field in a B form or XL form instruction. */
212#define BI BFA + 1
213#define BI_MASK (0x1f << 16)
11b37b7b 214 { 5, 16, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 215
216 /* The BO field in a B form instruction. Certain values are
217 illegal. */
218#define BO BI + 1
219#define BO_MASK (0x1f << 21)
11b37b7b 220 { 5, 21, insert_bo, extract_bo, 0 },
252b5132
RH		 221
222 /* The BO field in a B form instruction when the + or - modifier is
223 used. This is like the BO field, but it must be even. */
224#define BOE BO + 1
11b37b7b 225 { 5, 21, insert_boe, extract_boe, 0 },
252b5132
RH		 226
227 /* The BT field in an X or XL form instruction. */
228#define BT BOE + 1
11b37b7b 229 { 5, 21, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 230
231 /* The condition register number portion of the BI field in a B form
232 or XL form instruction. This is used for the extended
233 conditional branch mnemonics, which set the lower two bits of the
234 BI field. This field is optional. */
235#define CR BT + 1
11b37b7b 236 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132 237
418c1742
MG		 238 /* The CT field in an X form instruction. */
239#define CT CR + 1
1f613cde 240 { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
418c1742 241
252b5132
RH		 242 /* The D field in a D form instruction. This is a displacement off
243 a register, and implies that the next operand is a register in
244 parentheses. */
418c1742 245#define D CT + 1
11b37b7b 246 { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
252b5132 247
418c1742
MG		 248 /* The DE field in a DE form instruction. This is like D, but is 12
249 bits only. */
250#define DE D + 1
251 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
252
253 /* The DES field in a DES form instruction. This is like DS, but is 14
254 bits only (12 stored.) */
255#define DES DE + 1
256 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
257
252b5132
RH		 258 /* The DS field in a DS form instruction. This is like D, but the
259 lower two bits are forced to zero. */
418c1742 260#define DS DES + 1
6ba045b1
AM		 261 { 16, 0, insert_ds, extract_ds,
262 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
252b5132
RH		 263
264 /* The E field in a wrteei instruction. */
265#define E DS + 1
11b37b7b 266 { 1, 15, 0, 0, 0 },
252b5132
RH		 267
268 /* The FL1 field in a POWER SC form instruction. */
269#define FL1 E + 1
11b37b7b 270 { 4, 12, 0, 0, 0 },
252b5132
RH		 271
272 /* The FL2 field in a POWER SC form instruction. */
273#define FL2 FL1 + 1
11b37b7b 274 { 3, 2, 0, 0, 0 },
252b5132
RH		 275
276 /* The FLM field in an XFL form instruction. */
277#define FLM FL2 + 1
11b37b7b 278 { 8, 17, 0, 0, 0 },
252b5132
RH		 279
280 /* The FRA field in an X or A form instruction. */
281#define FRA FLM + 1
282#define FRA_MASK (0x1f << 16)
11b37b7b 283 { 5, 16, 0, 0, PPC_OPERAND_FPR },
252b5132
RH		 284
285 /* The FRB field in an X or A form instruction. */
286#define FRB FRA + 1
287#define FRB_MASK (0x1f << 11)
11b37b7b 288 { 5, 11, 0, 0, PPC_OPERAND_FPR },
252b5132
RH		 289
290 /* The FRC field in an A form instruction. */
291#define FRC FRB + 1
292#define FRC_MASK (0x1f << 6)
11b37b7b 293 { 5, 6, 0, 0, PPC_OPERAND_FPR },
252b5132
RH		 294
295 /* The FRS field in an X form instruction or the FRT field in a D, X
296 or A form instruction. */
297#define FRS FRC + 1
298#define FRT FRS
11b37b7b 299 { 5, 21, 0, 0, PPC_OPERAND_FPR },
252b5132
RH		 300
301 /* The FXM field in an XFX instruction. */
302#define FXM FRS + 1
303#define FXM_MASK (0xff << 12)
11b37b7b 304 { 8, 12, 0, 0, 0 },
252b5132
RH		 305
306 /* The L field in a D or X form instruction. */
307#define L FXM + 1
11b37b7b 308 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
252b5132
RH		 309
310 /* The LEV field in a POWER SC form instruction. */
311#define LEV L + 1
11b37b7b 312 { 7, 5, 0, 0, 0 },
252b5132
RH		 313
314 /* The LI field in an I form instruction. The lower two bits are
315 forced to zero. */
316#define LI LEV + 1
11b37b7b 317 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 318
319 /* The LI field in an I form instruction when used as an absolute
320 address. */
321#define LIA LI + 1
11b37b7b 322 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132 323
6ba045b1
AM		 324 /* The LS field in an X (sync) form instruction. */
325#define LS LIA + 1
326 { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
327
252b5132 328 /* The MB field in an M form instruction. */
6ba045b1 329#define MB LS + 1
252b5132 330#define MB_MASK (0x1f << 6)
11b37b7b 331 { 5, 6, 0, 0, 0 },
252b5132
RH		 332
333 /* The ME field in an M form instruction. */
334#define ME MB + 1
335#define ME_MASK (0x1f << 1)
11b37b7b 336 { 5, 1, 0, 0, 0 },
252b5132
RH		 337
338 /* The MB and ME fields in an M form instruction expressed a single
339 operand which is a bitmask indicating which bits to select. This
340 is a two operand form using PPC_OPERAND_NEXT. See the
341 description in opcode/ppc.h for what this means. */
342#define MBE ME + 1
11b37b7b
AM		 343 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
344 { 32, 0, insert_mbe, extract_mbe, 0 },
252b5132
RH		 345
346 /* The MB or ME field in an MD or MDS form instruction. The high
347 bit is wrapped to the low end. */
348#define MB6 MBE + 2
349#define ME6 MB6
350#define MB6_MASK (0x3f << 5)
11b37b7b 351 { 6, 5, insert_mb6, extract_mb6, 0 },
252b5132 352
9fa87a06
MG		 353 /* The MO field in an mbar instruction. */
354#define MO MB6 + 1
355 { 5, 21, 0, 0, 0 },
356
252b5132
RH		 357 /* The NB field in an X form instruction. The value 32 is stored as
358 0. */
9fa87a06 359#define NB MO + 1
11b37b7b 360 { 6, 11, insert_nb, extract_nb, 0 },
252b5132
RH		 361
362 /* The NSI field in a D form instruction. This is the same as the
363 SI field, only negated. */
364#define NSI NB + 1
365 { 16, 0, insert_nsi, extract_nsi,
11b37b7b 366 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 367
368 /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
369#define RA NSI + 1
370#define RA_MASK (0x1f << 16)
11b37b7b 371 { 5, 16, 0, 0, PPC_OPERAND_GPR },
252b5132
RH		 372
373 /* The RA field in a D or X form instruction which is an updating
374 load, which means that the RA field may not be zero and may not
375 equal the RT field. */
376#define RAL RA + 1
11b37b7b 377 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
252b5132
RH		 378
379 /* The RA field in an lmw instruction, which has special value
380 restrictions. */
381#define RAM RAL + 1
11b37b7b 382 { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
252b5132
RH		 383
384 /* The RA field in a D or X form instruction which is an updating
385 store or an updating floating point load, which means that the RA
386 field may not be zero. */
387#define RAS RAM + 1
11b37b7b 388 { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
252b5132
RH		 389
390 /* The RB field in an X, XO, M, or MDS form instruction. */
391#define RB RAS + 1
392#define RB_MASK (0x1f << 11)
11b37b7b 393 { 5, 11, 0, 0, PPC_OPERAND_GPR },
252b5132
RH		 394
395 /* The RB field in an X form instruction when it must be the same as
396 the RS field in the instruction. This is used for extended
397 mnemonics like mr. */
398#define RBS RB + 1
11b37b7b 399 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
252b5132
RH		 400
401 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
402 instruction or the RT field in a D, DS, X, XFX or XO form
403 instruction. */
404#define RS RBS + 1
405#define RT RS
406#define RT_MASK (0x1f << 21)
11b37b7b 407 { 5, 21, 0, 0, PPC_OPERAND_GPR },
252b5132
RH		 408
409 /* The SH field in an X or M form instruction. */
410#define SH RS + 1
411#define SH_MASK (0x1f << 11)
11b37b7b 412 { 5, 11, 0, 0, 0 },
252b5132
RH		 413
414 /* The SH field in an MD form instruction. This is split. */
415#define SH6 SH + 1
416#define SH6_MASK ((0x1f << 11) | (1 << 1))
11b37b7b 417 { 6, 1, insert_sh6, extract_sh6, 0 },
252b5132
RH		 418
419 /* The SI field in a D form instruction. */
420#define SI SH6 + 1
11b37b7b 421 { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
252b5132
RH		 422
423 /* The SI field in a D form instruction when we accept a wide range
424 of positive values. */
425#define SISIGNOPT SI + 1
11b37b7b 426 { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
252b5132
RH		 427
428 /* The SPR field in an XFX form instruction. This is flipped--the
429 lower 5 bits are stored in the upper 5 and vice- versa. */
430#define SPR SISIGNOPT + 1
431#define SPR_MASK (0x3ff << 11)
11b37b7b 432 { 10, 11, insert_spr, extract_spr, 0 },
252b5132
RH		 433
434 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
435#define SPRBAT SPR + 1
436#define SPRBAT_MASK (0x3 << 17)
11b37b7b 437 { 2, 17, 0, 0, 0 },
252b5132
RH		 438
439 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
440#define SPRG SPRBAT + 1
441#define SPRG_MASK (0x3 << 16)
11b37b7b 442 { 2, 16, 0, 0, 0 },
252b5132
RH		 443
444 /* The SR field in an X form instruction. */
445#define SR SPRG + 1
11b37b7b 446 { 4, 16, 0, 0, 0 },
252b5132 447
f5c120c5
MG		 448 /* The STRM field in an X AltiVec form instruction. */
449#define STRM SR + 1
450#define STRM_MASK (0x3 << 21)
451 { 2, 21, 0, 0, 0 },
452
252b5132 453 /* The SV field in a POWER SC form instruction. */
f5c120c5 454#define SV STRM + 1
11b37b7b 455 { 14, 2, 0, 0, 0 },
252b5132
RH		 456
457 /* The TBR field in an XFX form instruction. This is like the SPR
458 field, but it is optional. */
459#define TBR SV + 1
11b37b7b 460 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
252b5132
RH		 461
462 /* The TO field in a D or X form instruction. */
463#define TO TBR + 1
464#define TO_MASK (0x1f << 21)
11b37b7b 465 { 5, 21, 0, 0, 0 },
252b5132
RH		 466
467 /* The U field in an X form instruction. */
468#define U TO + 1
11b37b7b 469 { 4, 12, 0, 0, 0 },
252b5132
RH		 470
471 /* The UI field in a D form instruction. */
472#define UI U + 1
11b37b7b 473 { 16, 0, 0, 0, 0 },
786e2c0f
C		 474
475 /* The VA field in a VA, VX or VXR form instruction. */
476#define VA UI + 1
477#define VA_MASK (0x1f << 16)
6ba045b1 478 { 5, 16, 0, 0, PPC_OPERAND_VR },
786e2c0f
C		 479
480 /* The VB field in a VA, VX or VXR form instruction. */
481#define VB VA + 1
482#define VB_MASK (0x1f << 11)
6ba045b1 483 { 5, 11, 0, 0, PPC_OPERAND_VR },
786e2c0f
C		 484
485 /* The VC field in a VA form instruction. */
486#define VC VB + 1
487#define VC_MASK (0x1f << 6)
6ba045b1 488 { 5, 6, 0, 0, PPC_OPERAND_VR },
786e2c0f
C		 489
490 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
491#define VD VC + 1
492#define VS VD
493#define VD_MASK (0x1f << 21)
6ba045b1 494 { 5, 21, 0, 0, PPC_OPERAND_VR },
786e2c0f
C		 495
496 /* The SIMM field in a VX form instruction. */
497#define SIMM VD + 1
11b37b7b 498 { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
786e2c0f
C		 499
500 /* The UIMM field in a VX form instruction. */
501#define UIMM SIMM + 1
11b37b7b 502 { 5, 16, 0, 0, 0 },
786e2c0f
C		 503
504 /* The SHB field in a VA form instruction. */
505#define SHB UIMM + 1
11b37b7b 506 { 4, 6, 0, 0, 0 },
ff3a6ee3
TR		 507
508 /* The WS field. */
509#define WS SHB + 1
510#define WS_MASK (0x7 << 11)
511 { 3, 11, 0, 0, 0 },
512
252b5132
RH		 513};
514
515/* The functions used to insert and extract complicated operands. */
516
517/* The BA field in an XL form instruction when it must be the same as
518 the BT field in the same instruction. This operand is marked FAKE.
519 The insertion function just copies the BT field into the BA field,
520 and the extraction function just checks that the fields are the
521 same. */
522
523/*ARGSUSED*/
524static unsigned long
802a735e 525insert_bat (insn, value, dialect, errmsg)
252b5132 526 unsigned long insn;
9aaaa291 527 long value ATTRIBUTE_UNUSED;
802a735e 528 int dialect ATTRIBUTE_UNUSED;
9aaaa291 529 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 530{
531 return insn | (((insn >> 21) & 0x1f) << 16);
532}
533
534static long
802a735e 535extract_bat (insn, dialect, invalid)
252b5132 536 unsigned long insn;
802a735e 537 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 538 int *invalid;
539{
540 if (invalid != (int *) NULL
541 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
542 *invalid = 1;
543 return 0;
544}
545
546/* The BB field in an XL form instruction when it must be the same as
547 the BA field in the same instruction. This operand is marked FAKE.
548 The insertion function just copies the BA field into the BB field,
549 and the extraction function just checks that the fields are the
550 same. */
551
552/*ARGSUSED*/
553static unsigned long
802a735e 554insert_bba (insn, value, dialect, errmsg)
252b5132 555 unsigned long insn;
9aaaa291 556 long value ATTRIBUTE_UNUSED;
802a735e 557 int dialect ATTRIBUTE_UNUSED;
9aaaa291 558 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 559{
560 return insn | (((insn >> 16) & 0x1f) << 11);
561}
562
563static long
802a735e 564extract_bba (insn, dialect, invalid)
252b5132 565 unsigned long insn;
802a735e 566 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 567 int *invalid;
568{
569 if (invalid != (int *) NULL
570 && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
571 *invalid = 1;
572 return 0;
573}
574
575/* The BD field in a B form instruction. The lower two bits are
576 forced to zero. */
577
578/*ARGSUSED*/
579static unsigned long
802a735e 580insert_bd (insn, value, dialect, errmsg)
252b5132
RH		 581 unsigned long insn;
582 long value;
802a735e 583 int dialect ATTRIBUTE_UNUSED;
9aaaa291 584 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 585{
586 return insn | (value & 0xfffc);
587}
588
589/*ARGSUSED*/
590static long
802a735e 591extract_bd (insn, dialect, invalid)
252b5132 592 unsigned long insn;
802a735e 593 int dialect ATTRIBUTE_UNUSED;
9aaaa291 594 int *invalid ATTRIBUTE_UNUSED;
252b5132 595{
802a735e 596 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 597}
598
599/* The BD field in a B form instruction when the - modifier is used.
600 This modifier means that the branch is not expected to be taken.
94efba12
AM		 601 For chips built to versions of the architecture prior to version 2
602 (ie. not Power4 compatible), we set the y bit of the BO field to 1
603 if the offset is negative. When extracting, we require that the y
604 bit be 1 and that the offset be positive, since if the y bit is 0
605 we just want to print the normal form of the instruction.
606 Power4 compatible targets use two bits, "a", and "t", instead of
607 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
608 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
609 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
610 for branch on CTR. We only handle the taken/not-taken hint here. */
252b5132
RH		 611
612/*ARGSUSED*/
613static unsigned long
802a735e 614insert_bdm (insn, value, dialect, errmsg)
252b5132
RH		 615 unsigned long insn;
616 long value;
802a735e 617 int dialect;
9aaaa291 618 const char **errmsg ATTRIBUTE_UNUSED;
252b5132 619{
94efba12 620 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 621 {
622 if ((value & 0x8000) != 0)
623 insn |= 1 << 21;
624 }
625 else
626 {
627 if ((insn & (0x14 << 21)) == (0x04 << 21))
628 insn |= 0x02 << 21;
629 else if ((insn & (0x14 << 21)) == (0x10 << 21))
630 insn |= 0x08 << 21;
631 }
252b5132
RH		 632 return insn | (value & 0xfffc);
633}
634
635static long
802a735e 636extract_bdm (insn, dialect, invalid)
252b5132 637 unsigned long insn;
802a735e 638 int dialect;
252b5132
RH		 639 int *invalid;
640{
802a735e
AM		 641 if (invalid != (int *) NULL)
642 {
94efba12 643 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 644 {
645 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
646 *invalid = 1;
647 }
648 else
649 {
650 if ((insn & (0x17 << 21)) != (0x06 << 21)
651 && (insn & (0x1d << 21)) != (0x18 << 21))
652 *invalid = 1;
653 }
654 }
655 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 656}
657
658/* The BD field in a B form instruction when the + modifier is used.
659 This is like BDM, above, except that the branch is expected to be
660 taken. */
661
662/*ARGSUSED*/
663static unsigned long
802a735e 664insert_bdp (insn, value, dialect, errmsg)
252b5132
RH		 665 unsigned long insn;
666 long value;
802a735e 667 int dialect;
9aaaa291 668 const char **errmsg ATTRIBUTE_UNUSED;
252b5132 669{
94efba12 670 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 671 {
672 if ((value & 0x8000) == 0)
673 insn |= 1 << 21;
674 }
675 else
676 {
677 if ((insn & (0x14 << 21)) == (0x04 << 21))
678 insn |= 0x03 << 21;
679 else if ((insn & (0x14 << 21)) == (0x10 << 21))
680 insn |= 0x09 << 21;
681 }
252b5132
RH		 682 return insn | (value & 0xfffc);
683}
684
685static long
802a735e 686extract_bdp (insn, dialect, invalid)
252b5132 687 unsigned long insn;
802a735e 688 int dialect;
252b5132
RH		 689 int *invalid;
690{
802a735e
AM		 691 if (invalid != (int *) NULL)
692 {
94efba12 693 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 694 {
695 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
696 *invalid = 1;
697 }
698 else
699 {
700 if ((insn & (0x17 << 21)) != (0x07 << 21)
701 && (insn & (0x1d << 21)) != (0x19 << 21))
702 *invalid = 1;
703 }
704 }
705 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 706}
707
708/* Check for legal values of a BO field. */
709
710static int
802a735e 711valid_bo (value, dialect)
252b5132 712 long value;
802a735e 713 int dialect;
252b5132 714{
94efba12 715 if ((dialect & PPC_OPCODE_POWER4) == 0)
252b5132 716 {
802a735e
AM		 717 /* Certain encodings have bits that are required to be zero.
718 These are (z must be zero, y may be anything):
719 001zy
720 011zy
721 1z00y
722 1z01y
723 1z1zz
724 */
725 switch (value & 0x14)
726 {
727 default:
728 case 0:
729 return 1;
730 case 0x4:
731 return (value & 0x2) == 0;
732 case 0x10:
733 return (value & 0x8) == 0;
734 case 0x14:
735 return value == 0x14;
736 }
737 }
738 else
739 {
740 /* Certain encodings have bits that are required to be zero.
741 These are (z must be zero, a & t may be anything):
742 0000z
743 0001z
744 0100z
745 0101z
746 001at
747 011at
748 1a00t
749 1a01t
750 1z1zz
751 */
752 if ((value & 0x14) == 0)
753 return (value & 0x1) == 0;
754 else if ((value & 0x14) == 0x14)
755 return value == 0x14;
756 else
757 return 1;
252b5132
RH		 758 }
759}
760
761/* The BO field in a B form instruction. Warn about attempts to set
762 the field to an illegal value. */
763
764static unsigned long
802a735e 765insert_bo (insn, value, dialect, errmsg)
252b5132
RH		 766 unsigned long insn;
767 long value;
802a735e 768 int dialect;
252b5132
RH		 769 const char **errmsg;
770{
771 if (errmsg != (const char **) NULL
802a735e 772 && ! valid_bo (value, dialect))
252b5132
RH		 773 *errmsg = _("invalid conditional option");
774 return insn | ((value & 0x1f) << 21);
775}
776
777static long
802a735e 778extract_bo (insn, dialect, invalid)
252b5132 779 unsigned long insn;
802a735e 780 int dialect;
252b5132
RH		 781 int *invalid;
782{
783 long value;
784
785 value = (insn >> 21) & 0x1f;
786 if (invalid != (int *) NULL
802a735e 787 && ! valid_bo (value, dialect))
252b5132
RH		 788 *invalid = 1;
789 return value;
790}
791
792/* The BO field in a B form instruction when the + or - modifier is
793 used. This is like the BO field, but it must be even. When
794 extracting it, we force it to be even. */
795
796static unsigned long
802a735e 797insert_boe (insn, value, dialect, errmsg)
252b5132
RH		 798 unsigned long insn;
799 long value;
802a735e 800 int dialect;
252b5132
RH		 801 const char **errmsg;
802{
803 if (errmsg != (const char **) NULL)
804 {
802a735e 805 if (! valid_bo (value, dialect))
252b5132
RH		 806 *errmsg = _("invalid conditional option");
807 else if ((value & 1) != 0)
808 *errmsg = _("attempt to set y bit when using + or - modifier");
809 }
810 return insn | ((value & 0x1f) << 21);
811}
812
813static long
802a735e 814extract_boe (insn, dialect, invalid)
252b5132 815 unsigned long insn;
802a735e 816 int dialect;
252b5132
RH		 817 int *invalid;
818{
819 long value;
820
821 value = (insn >> 21) & 0x1f;
822 if (invalid != (int *) NULL
802a735e 823 && ! valid_bo (value, dialect))
252b5132
RH		 824 *invalid = 1;
825 return value & 0x1e;
826}
827
828/* The DS field in a DS form instruction. This is like D, but the
829 lower two bits are forced to zero. */
830
831/*ARGSUSED*/
832static unsigned long
802a735e 833insert_ds (insn, value, dialect, errmsg)
252b5132
RH		 834 unsigned long insn;
835 long value;
802a735e 836 int dialect ATTRIBUTE_UNUSED;
418c1742 837 const char **errmsg;
252b5132 838{
6ba045b1
AM		 839 if ((value & 3) != 0 && errmsg != NULL)
840 *errmsg = _("offset not a multiple of 4");
252b5132
RH		 841 return insn | (value & 0xfffc);
842}
843
844/*ARGSUSED*/
845static long
802a735e 846extract_ds (insn, dialect, invalid)
252b5132 847 unsigned long insn;
802a735e 848 int dialect ATTRIBUTE_UNUSED;
9aaaa291 849 int *invalid ATTRIBUTE_UNUSED;
252b5132 850{
802a735e 851 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 852}
853
418c1742
MG		 854/* The DE field in a DE form instruction. */
855
856/*ARGSUSED*/
857static unsigned long
802a735e 858insert_de (insn, value, dialect, errmsg)
418c1742
MG		 859 unsigned long insn;
860 long value;
802a735e 861 int dialect ATTRIBUTE_UNUSED;
418c1742
MG		 862 const char **errmsg;
863{
864 if ((value > 2047 || value < -2048) && errmsg != NULL)
865 *errmsg = _("offset not between -2048 and 2047");
866 return insn | ((value << 4) & 0xfff0);
867}
868
869/*ARGSUSED*/
870static long
802a735e 871extract_de (insn, dialect, invalid)
418c1742 872 unsigned long insn;
802a735e 873 int dialect ATTRIBUTE_UNUSED;
418c1742
MG		 874 int *invalid ATTRIBUTE_UNUSED;
875{
876 return (insn & 0xfff0) >> 4;
877}
878
879/* The DES field in a DES form instruction. */
880
881/*ARGSUSED*/
882static unsigned long
802a735e 883insert_des (insn, value, dialect, errmsg)
418c1742
MG		 884 unsigned long insn;
885 long value;
802a735e 886 int dialect ATTRIBUTE_UNUSED;
418c1742
MG		 887 const char **errmsg;
888{
889 if ((value > 8191 || value < -8192) && errmsg != NULL)
890 *errmsg = _("offset not between -8192 and 8191");
891 else if ((value & 3) != 0 && errmsg != NULL)
892 *errmsg = _("offset not a multiple of 4");
893 return insn | ((value << 2) & 0xfff0);
894}
895
896/*ARGSUSED*/
897static long
802a735e 898extract_des (insn, dialect, invalid)
418c1742 899 unsigned long insn;
802a735e 900 int dialect ATTRIBUTE_UNUSED;
418c1742
MG		 901 int *invalid ATTRIBUTE_UNUSED;
902{
802a735e 903 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
418c1742
MG		 904}
905
252b5132
RH		 906/* The LI field in an I form instruction. The lower two bits are
907 forced to zero. */
908
909/*ARGSUSED*/
910static unsigned long
802a735e 911insert_li (insn, value, dialect, errmsg)
252b5132
RH		 912 unsigned long insn;
913 long value;
802a735e 914 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 915 const char **errmsg;
916{
917 if ((value & 3) != 0 && errmsg != (const char **) NULL)
918 *errmsg = _("ignoring least significant bits in branch offset");
919 return insn | (value & 0x3fffffc);
920}
921
922/*ARGSUSED*/
923static long
802a735e 924extract_li (insn, dialect, invalid)
252b5132 925 unsigned long insn;
802a735e 926 int dialect ATTRIBUTE_UNUSED;
9aaaa291 927 int *invalid ATTRIBUTE_UNUSED;
252b5132 928{
802a735e 929 return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
252b5132
RH		 930}
931
932/* The MB and ME fields in an M form instruction expressed as a single
933 operand which is itself a bitmask. The extraction function always
934 marks it as invalid, since we never want to recognize an
935 instruction which uses a field of this type. */
936
937static unsigned long
802a735e 938insert_mbe (insn, value, dialect, errmsg)
252b5132
RH		 939 unsigned long insn;
940 long value;
802a735e 941 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 942 const char **errmsg;
943{
944 unsigned long uval, mask;
945 int mb, me, mx, count, last;
946
947 uval = value;
948
949 if (uval == 0)
950 {
951 if (errmsg != (const char **) NULL)
952 *errmsg = _("illegal bitmask");
953 return insn;
954 }
955
956 mb = 0;
957 me = 32;
958 if ((uval & 1) != 0)
959 last = 1;
960 else
961 last = 0;
962 count = 0;
963
964 /* mb: location of last 0->1 transition */
965 /* me: location of last 1->0 transition */
966 /* count: # transitions */
967
3eb9799d 968 for (mx = 0, mask = (long) 1 << 31; mx < 32; ++mx, mask >>= 1)
252b5132
RH		 969 {
970 if ((uval & mask) && !last)
971 {
972 ++count;
973 mb = mx;
974 last = 1;
975 }
976 else if (!(uval & mask) && last)
977 {
978 ++count;
979 me = mx;
980 last = 0;
981 }
982 }
983 if (me == 0)
984 me = 32;
985
986 if (count != 2 && (count != 0 || ! last))
987 {
988 if (errmsg != (const char **) NULL)
989 *errmsg = _("illegal bitmask");
990 }
991
992 return insn | (mb << 6) | ((me - 1) << 1);
993}
994
995static long
802a735e 996extract_mbe (insn, dialect, invalid)
252b5132 997 unsigned long insn;
802a735e 998 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 999 int *invalid;
1000{
1001 long ret;
1002 int mb, me;
1003 int i;
1004
1005 if (invalid != (int *) NULL)
1006 *invalid = 1;
1007
1008 mb = (insn >> 6) & 0x1f;
1009 me = (insn >> 1) & 0x1f;
1010 if (mb < me + 1)
1011 {
1012 ret = 0;
1013 for (i = mb; i <= me; i++)
1014 ret |= (long) 1 << (31 - i);
1015 }
1016 else if (mb == me + 1)
1017 ret = ~0;
1018 else /* (mb > me + 1) */
1019 {
1020 ret = ~ (long) 0;
1021 for (i = me + 1; i < mb; i++)
1022 ret &= ~ ((long) 1 << (31 - i));
1023 }
1024 return ret;
1025}
1026
1027/* The MB or ME field in an MD or MDS form instruction. The high bit
1028 is wrapped to the low end. */
1029
1030/*ARGSUSED*/
1031static unsigned long
802a735e 1032insert_mb6 (insn, value, dialect, errmsg)
252b5132
RH		 1033 unsigned long insn;
1034 long value;
802a735e 1035 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1036 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1037{
1038 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1039}
1040
1041/*ARGSUSED*/
1042static long
802a735e 1043extract_mb6 (insn, dialect, invalid)
252b5132 1044 unsigned long insn;
802a735e 1045 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1046 int *invalid ATTRIBUTE_UNUSED;
252b5132
RH		 1047{
1048 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1049}
1050
1051/* The NB field in an X form instruction. The value 32 is stored as
1052 0. */
1053
1054static unsigned long
802a735e 1055insert_nb (insn, value, dialect, errmsg)
252b5132
RH		 1056 unsigned long insn;
1057 long value;
802a735e 1058 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1059 const char **errmsg;
1060{
1061 if (value < 0 || value > 32)
1062 *errmsg = _("value out of range");
1063 if (value == 32)
1064 value = 0;
1065 return insn | ((value & 0x1f) << 11);
1066}
1067
1068/*ARGSUSED*/
1069static long
802a735e 1070extract_nb (insn, dialect, invalid)
252b5132 1071 unsigned long insn;
802a735e 1072 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1073 int *invalid ATTRIBUTE_UNUSED;
252b5132
RH		 1074{
1075 long ret;
1076
1077 ret = (insn >> 11) & 0x1f;
1078 if (ret == 0)
1079 ret = 32;
1080 return ret;
1081}
1082
1083/* The NSI field in a D form instruction. This is the same as the SI
1084 field, only negated. The extraction function always marks it as
1085 invalid, since we never want to recognize an instruction which uses
1086 a field of this type. */
1087
1088/*ARGSUSED*/
1089static unsigned long
802a735e 1090insert_nsi (insn, value, dialect, errmsg)
252b5132
RH		 1091 unsigned long insn;
1092 long value;
802a735e 1093 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1094 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1095{
1096 return insn | ((- value) & 0xffff);
1097}
1098
1099static long
802a735e 1100extract_nsi (insn, dialect, invalid)
252b5132 1101 unsigned long insn;
802a735e 1102 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1103 int *invalid;
1104{
1105 if (invalid != (int *) NULL)
1106 *invalid = 1;
802a735e 1107 return - (((insn & 0xffff) ^ 0x8000) - 0x8000);
252b5132
RH		 1108}
1109
1110/* The RA field in a D or X form instruction which is an updating
1111 load, which means that the RA field may not be zero and may not
1112 equal the RT field. */
1113
1114static unsigned long
802a735e 1115insert_ral (insn, value, dialect, errmsg)
252b5132
RH		 1116 unsigned long insn;
1117 long value;
802a735e 1118 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1119 const char **errmsg;
1120{
1121 if (value == 0
1122 || (unsigned long) value == ((insn >> 21) & 0x1f))
1123 *errmsg = "invalid register operand when updating";
1124 return insn | ((value & 0x1f) << 16);
1125}
1126
1127/* The RA field in an lmw instruction, which has special value
1128 restrictions. */
1129
1130static unsigned long
802a735e 1131insert_ram (insn, value, dialect, errmsg)
252b5132
RH		 1132 unsigned long insn;
1133 long value;
802a735e 1134 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1135 const char **errmsg;
1136{
1137 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1138 *errmsg = _("index register in load range");
1139 return insn | ((value & 0x1f) << 16);
1140}
1141
1142/* The RA field in a D or X form instruction which is an updating
1143 store or an updating floating point load, which means that the RA
1144 field may not be zero. */
1145
1146static unsigned long
802a735e 1147insert_ras (insn, value, dialect, errmsg)
252b5132
RH		 1148 unsigned long insn;
1149 long value;
802a735e 1150 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1151 const char **errmsg;
1152{
1153 if (value == 0)
1154 *errmsg = _("invalid register operand when updating");
1155 return insn | ((value & 0x1f) << 16);
1156}
1157
1158/* The RB field in an X form instruction when it must be the same as
1159 the RS field in the instruction. This is used for extended
1160 mnemonics like mr. This operand is marked FAKE. The insertion
1161 function just copies the BT field into the BA field, and the
1162 extraction function just checks that the fields are the same. */
1163
1164/*ARGSUSED*/
1165static unsigned long
802a735e 1166insert_rbs (insn, value, dialect, errmsg)
252b5132 1167 unsigned long insn;
9aaaa291 1168 long value ATTRIBUTE_UNUSED;
802a735e 1169 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1170 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1171{
1172 return insn | (((insn >> 21) & 0x1f) << 11);
1173}
1174
1175static long
802a735e 1176extract_rbs (insn, dialect, invalid)
252b5132 1177 unsigned long insn;
802a735e 1178 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1179 int *invalid;
1180{
1181 if (invalid != (int *) NULL
1182 && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1183 *invalid = 1;
1184 return 0;
1185}
1186
1187/* The SH field in an MD form instruction. This is split. */
1188
1189/*ARGSUSED*/
1190static unsigned long
802a735e 1191insert_sh6 (insn, value, dialect, errmsg)
252b5132
RH		 1192 unsigned long insn;
1193 long value;
802a735e 1194 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1195 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1196{
1197 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1198}
1199
1200/*ARGSUSED*/
1201static long
802a735e 1202extract_sh6 (insn, dialect, invalid)
252b5132 1203 unsigned long insn;
802a735e 1204 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1205 int *invalid ATTRIBUTE_UNUSED;
252b5132
RH		 1206{
1207 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1208}
1209
1210/* The SPR field in an XFX form instruction. This is flipped--the
1211 lower 5 bits are stored in the upper 5 and vice- versa. */
1212
1213static unsigned long
802a735e 1214insert_spr (insn, value, dialect, errmsg)
252b5132
RH		 1215 unsigned long insn;
1216 long value;
802a735e 1217 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1218 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1219{
1220 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1221}
1222
1223static long
802a735e 1224extract_spr (insn, dialect, invalid)
252b5132 1225 unsigned long insn;
802a735e 1226 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1227 int *invalid ATTRIBUTE_UNUSED;
252b5132
RH		 1228{
1229 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1230}
1231
1232/* The TBR field in an XFX instruction. This is just like SPR, but it
1233 is optional. When TBR is omitted, it must be inserted as 268 (the
1234 magic number of the TB register). These functions treat 0
1235 (indicating an omitted optional operand) as 268. This means that
1236 ``mftb 4,0'' is not handled correctly. This does not matter very
1237 much, since the architecture manual does not define mftb as
1238 accepting any values other than 268 or 269. */
1239
1240#define TB (268)
1241
1242static unsigned long
802a735e 1243insert_tbr (insn, value, dialect, errmsg)
252b5132
RH		 1244 unsigned long insn;
1245 long value;
802a735e 1246 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1247 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1248{
1249 if (value == 0)
1250 value = TB;
1251 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1252}
1253
1254static long
802a735e 1255extract_tbr (insn, dialect, invalid)
252b5132 1256 unsigned long insn;
802a735e 1257 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1258 int *invalid ATTRIBUTE_UNUSED;
252b5132
RH		 1259{
1260 long ret;
1261
1262 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1263 if (ret == TB)
1264 ret = 0;
1265 return ret;
1266}
1267\f
1268/* Macros used to form opcodes. */
1269
1270/* The main opcode. */
1271#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1272#define OP_MASK OP (0x3f)
1273
1274/* The main opcode combined with a trap code in the TO field of a D
1275 form instruction. Used for extended mnemonics for the trap
1276 instructions. */
1277#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1278#define OPTO_MASK (OP_MASK | TO_MASK)
1279
1280/* The main opcode combined with a comparison size bit in the L field
1281 of a D form or X form instruction. Used for extended mnemonics for
1282 the comparison instructions. */
1283#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1284#define OPL_MASK OPL (0x3f,1)
1285
1286/* An A form instruction. */
1287#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1288#define A_MASK A (0x3f, 0x1f, 1)
1289
1290/* An A_MASK with the FRB field fixed. */
1291#define AFRB_MASK (A_MASK | FRB_MASK)
1292
1293/* An A_MASK with the FRC field fixed. */
1294#define AFRC_MASK (A_MASK | FRC_MASK)
1295
1296/* An A_MASK with the FRA and FRC fields fixed. */
1297#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1298
1299/* A B form instruction. */
1300#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1301#define B_MASK B (0x3f, 1, 1)
1302
1303/* A B form instruction setting the BO field. */
1304#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1305#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1306
1307/* A BBO_MASK with the y bit of the BO field removed. This permits
1308 matching a conditional branch regardless of the setting of the y
94efba12 1309 bit. Similarly for the 'at' bits used for power4 branch hints. */
802a735e
AM		 1310#define Y_MASK (((unsigned long) 1) << 21)
1311#define AT1_MASK (((unsigned long) 3) << 21)
1312#define AT2_MASK (((unsigned long) 9) << 21)
1313#define BBOY_MASK (BBO_MASK &~ Y_MASK)
1314#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
252b5132
RH		 1315
1316/* A B form instruction setting the BO field and the condition bits of
1317 the BI field. */
1318#define BBOCB(op, bo, cb, aa, lk) \
1319 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1320#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1321
1322/* A BBOCB_MASK with the y bit of the BO field removed. */
1323#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
802a735e
AM		 1324#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1325#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
252b5132
RH		 1326
1327/* A BBOYCB_MASK in which the BI field is fixed. */
1328#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
802a735e 1329#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
252b5132
RH		 1330
1331/* The main opcode mask with the RA field clear. */
1332#define DRA_MASK (OP_MASK | RA_MASK)
1333
1334/* A DS form instruction. */
1335#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1336#define DS_MASK DSO (0x3f, 3)
1337
418c1742
MG		 1338/* A DE form instruction. */
1339#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1340#define DE_MASK DEO (0x3e, 0xf)
1341
252b5132
RH		 1342/* An M form instruction. */
1343#define M(op, rc) (OP (op) | ((rc) & 1))
1344#define M_MASK M (0x3f, 1)
1345
1346/* An M form instruction with the ME field specified. */
1347#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1348
1349/* An M_MASK with the MB and ME fields fixed. */
1350#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1351
1352/* An M_MASK with the SH and ME fields fixed. */
1353#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1354
1355/* An MD form instruction. */
1356#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1357#define MD_MASK MD (0x3f, 0x7, 1)
1358
1359/* An MD_MASK with the MB field fixed. */
1360#define MDMB_MASK (MD_MASK | MB6_MASK)
1361
1362/* An MD_MASK with the SH field fixed. */
1363#define MDSH_MASK (MD_MASK | SH6_MASK)
1364
1365/* An MDS form instruction. */
1366#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1367#define MDS_MASK MDS (0x3f, 0xf, 1)
1368
1369/* An MDS_MASK with the MB field fixed. */
1370#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1371
1372/* An SC form instruction. */
1373#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1374#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1375
786e2c0f
C		 1376/* An VX form instruction. */
1377#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1378
1379/* The mask for an VX form instruction. */
1380#define VX_MASK VX(0x3f, 0x7ff)
1381
1382/* An VA form instruction. */
2613489e 1383#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
786e2c0f
C		 1384
1385/* The mask for an VA form instruction. */
2613489e 1386#define VXA_MASK VXA(0x3f, 0x3f)
786e2c0f
C		 1387
1388/* An VXR form instruction. */
1389#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1390
1391/* The mask for a VXR form instruction. */
1392#define VXR_MASK VXR(0x3f, 0x3ff, 1)
1393
252b5132
RH		 1394/* An X form instruction. */
1395#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1396
1397/* An X form instruction with the RC bit specified. */
1398#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1399
1400/* The mask for an X form instruction. */
1401#define X_MASK XRC (0x3f, 0x3ff, 1)
1402
1403/* An X_MASK with the RA field fixed. */
1404#define XRA_MASK (X_MASK | RA_MASK)
1405
1406/* An X_MASK with the RB field fixed. */
1407#define XRB_MASK (X_MASK | RB_MASK)
1408
1409/* An X_MASK with the RT field fixed. */
1410#define XRT_MASK (X_MASK | RT_MASK)
1411
1412/* An X_MASK with the RA and RB fields fixed. */
1413#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1414
1415/* An X_MASK with the RT and RA fields fixed. */
1416#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1417
1418/* An X form comparison instruction. */
1419#define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1420
1421/* The mask for an X form comparison instruction. */
1422#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1423
1424/* The mask for an X form comparison instruction with the L field
1425 fixed. */
1426#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1427
1428/* An X form trap instruction with the TO field specified. */
1429#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1430#define XTO_MASK (X_MASK | TO_MASK)
1431
e0c21649
GK		 1432/* An X form tlb instruction with the SH field specified. */
1433#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1434#define XTLB_MASK (X_MASK | SH_MASK)
1435
6ba045b1
AM		 1436/* An X form sync instruction. */
1437#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1438
1439/* An X form sync instruction with everything filled in except the LS field. */
1440#define XSYNC_MASK (0xff9fffff)
1441
f5c120c5
MG		 1442/* An X form AltiVec dss instruction. */
1443#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1444#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1445
252b5132
RH		 1446/* An XFL form instruction. */
1447#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1448#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1449
1450/* An XL form instruction with the LK field set to 0. */
1451#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1452
1453/* An XL form instruction which uses the LK field. */
1454#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1455
1456/* The mask for an XL form instruction. */
1457#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1458
1459/* An XL form instruction which explicitly sets the BO field. */
1460#define XLO(op, bo, xop, lk) \
1461 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1462#define XLO_MASK (XL_MASK | BO_MASK)
1463
1464/* An XL form instruction which explicitly sets the y bit of the BO
1465 field. */
1466#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1467#define XLYLK_MASK (XL_MASK | Y_MASK)
1468
1469/* An XL form instruction which sets the BO field and the condition
1470 bits of the BI field. */
1471#define XLOCB(op, bo, cb, xop, lk) \
1472 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1473#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1474
1475/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1476#define XLBB_MASK (XL_MASK | BB_MASK)
1477#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1478#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1479
1480/* An XL_MASK with the BO and BB fields fixed. */
1481#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1482
1483/* An XL_MASK with the BO, BI and BB fields fixed. */
1484#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1485
1486/* An XO form instruction. */
1487#define XO(op, xop, oe, rc) \
1488 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1489#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1490
1491/* An XO_MASK with the RB field fixed. */
1492#define XORB_MASK (XO_MASK | RB_MASK)
1493
1494/* An XS form instruction. */
1495#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1496#define XS_MASK XS (0x3f, 0x1ff, 1)
1497
1498/* A mask for the FXM version of an XFX form instruction. */
1499#define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11))
1500
1501/* An XFX form instruction with the FXM field filled in. */
1502#define XFXM(op, xop, fxm) \
1503 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1504
1505/* An XFX form instruction with the SPR field filled in. */
1506#define XSPR(op, xop, spr) \
1507 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1508#define XSPR_MASK (X_MASK | SPR_MASK)
1509
1510/* An XFX form instruction with the SPR field filled in except for the
1511 SPRBAT field. */
1512#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1513
1514/* An XFX form instruction with the SPR field filled in except for the
1515 SPRG field. */
1516#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1517
1518/* An X form instruction with everything filled in except the E field. */
1519#define XE_MASK (0xffff7fff)
1520
1521/* The BO encodings used in extended conditional branch mnemonics. */
1522#define BODNZF (0x0)
1523#define BODNZFP (0x1)
1524#define BODZF (0x2)
1525#define BODZFP (0x3)
252b5132
RH		 1526#define BODNZT (0x8)
1527#define BODNZTP (0x9)
1528#define BODZT (0xa)
1529#define BODZTP (0xb)
802a735e
AM		 1530
1531#define BOF (0x4)
1532#define BOFP (0x5)
94efba12
AM		 1533#define BOFM4 (0x6)
1534#define BOFP4 (0x7)
252b5132
RH		 1535#define BOT (0xc)
1536#define BOTP (0xd)
94efba12
AM		 1537#define BOTM4 (0xe)
1538#define BOTP4 (0xf)
802a735e 1539
252b5132
RH		 1540#define BODNZ (0x10)
1541#define BODNZP (0x11)
1542#define BODZ (0x12)
1543#define BODZP (0x13)
94efba12
AM		 1544#define BODNZM4 (0x18)
1545#define BODNZP4 (0x19)
1546#define BODZM4 (0x1a)
1547#define BODZP4 (0x1b)
802a735e 1548
252b5132
RH		 1549#define BOU (0x14)
1550
1551/* The BI condition bit encodings used in extended conditional branch
1552 mnemonics. */
1553#define CBLT (0)
1554#define CBGT (1)
1555#define CBEQ (2)
1556#define CBSO (3)
1557
1558/* The TO encodings used in extended trap mnemonics. */
1559#define TOLGT (0x1)
1560#define TOLLT (0x2)
1561#define TOEQ (0x4)
1562#define TOLGE (0x5)
1563#define TOLNL (0x5)
1564#define TOLLE (0x6)
1565#define TOLNG (0x6)
1566#define TOGT (0x8)
1567#define TOGE (0xc)
1568#define TONL (0xc)
1569#define TOLT (0x10)
1570#define TOLE (0x14)
1571#define TONG (0x14)
1572#define TONE (0x18)
1573#define TOU (0x1f)
1574\f
1575/* Smaller names for the flags so each entry in the opcodes table will
1576 fit on a single line. */
1577#undef PPC
1578#define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY
1579#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
94efba12
AM		 1580#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1581#define POWER4 PPC_OPCODE_POWER4 | PPCCOM
802a735e
AM		 1582#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
1583#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
252b5132 1584#define PPCONLY PPC_OPCODE_PPC
418c1742 1585#define PPC403 PPC_OPCODE_403
e0c21649 1586#define PPC405 PPC403
252b5132
RH		 1587#define PPC750 PPC
1588#define PPC860 PPC
1cbbfaf9 1589#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC
252b5132
RH		 1590#define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY
1591#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1592#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1593#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
1594#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1595#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
1596#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
1597#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1598#define MFDEC1 PPC_OPCODE_POWER
1599#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601
418c1742
MG		 1600#define BOOKE PPC_OPCODE_BOOKE
1601#define BOOKE64 PPC_OPCODE_BOOKE64
252b5132
RH		 1602\f
1603/* The opcode table.
1604
1605 The format of the opcode table is:
1606
1607 NAME OPCODE MASK FLAGS { OPERANDS }
1608
1609 NAME is the name of the instruction.
1610 OPCODE is the instruction opcode.
1611 MASK is the opcode mask; this is used to tell the disassembler
1612 which bits in the actual opcode must match OPCODE.
1613 FLAGS are flags indicated what processors support the instruction.
1614 OPERANDS is the list of operands.
1615
1616 The disassembler reads the table in order and prints the first
1617 instruction which matches, so this table is sorted to put more
1618 specific instructions before more general instructions. It is also
1619 sorted by major opcode. */
1620
1621const struct powerpc_opcode powerpc_opcodes[] = {
1622{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1623{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1624{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1625{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1626{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1627{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1628{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1629{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1630{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1631{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1632{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1633{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1634{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1635{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1636{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1637
1638{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1639{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1640{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1641{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1642{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1643{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1644{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1645{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1646{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1647{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1648{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1649{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1650{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1651{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1652{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1653{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1654{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1655{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1656{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1657{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1658{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1659{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1660{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1661{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1662{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1663{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1664{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1665{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1666{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1667{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
e0c21649
GK		 1668
1669{ "macchw", XO(4,172,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1670{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1671{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1672{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1673{ "macchws", XO(4,236,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1674{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1675{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1676{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1677{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1678{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1679{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1680{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1681{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1682{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1683{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1684{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1685{ "machhw", XO(4,44,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1686{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1687{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1688{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1689{ "machhws", XO(4,108,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1690{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1691{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1692{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1693{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1694{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1695{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1696{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1697{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1698{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1699{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1700{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1701{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1702{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1703{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1704{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1705{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1706{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1707{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1708{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1709{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1710{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1711{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1712{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1713{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1714{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1715{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1716{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1717{ "mulchw", XRC(4,168,0), X_MASK, PPC405, { RT, RA, RB } },
1718{ "mulchw.", XRC(4,168,1), X_MASK, PPC405, { RT, RA, RB } },
1719{ "mulchwu", XRC(4,136,0), X_MASK, PPC405, { RT, RA, RB } },
1720{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405, { RT, RA, RB } },
1721{ "mulhhw", XRC(4,40,0), X_MASK, PPC405, { RT, RA, RB } },
1722{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405, { RT, RA, RB } },
1723{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405, { RT, RA, RB } },
1724{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405, { RT, RA, RB } },
1725{ "mullhw", XRC(4,424,0), X_MASK, PPC405, { RT, RA, RB } },
1726{ "mullhw.", XRC(4,424,1), X_MASK, PPC405, { RT, RA, RB } },
1727{ "mullhwu", XRC(4,392,0), X_MASK, PPC405, { RT, RA, RB } },
1728{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405, { RT, RA, RB } },
1729{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1730{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1731{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1732{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1733{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1734{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1735{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1736{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1737{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1738{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1739{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1740{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1741{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1742{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1743{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1744{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1745{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1746{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1747{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1748{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1749{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1750{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1751{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1752{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } },
786e2c0f 1753{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
f5c120c5 1754{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
786e2c0f
C		 1755{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
1756{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
1757{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
1758{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
1759{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
1760{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
1761{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
1762{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
1763{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
1764{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
1765{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
1766{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
1767{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
1768{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
1769{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
1770{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
1771{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
1772{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
1773{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
1774{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1775{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1776{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1777{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1778{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1779{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1780{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1781{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1782{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1783{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1784{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1785{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1786{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1787{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1788{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1789{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1790{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1791{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1792{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1793{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1794{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1795{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1796{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1797{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1798{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1799{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1800{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1801{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1802{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1803{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1804{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
1805{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
1806{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1807{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
1808{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
1809{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
1810{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
1811{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
1812{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
1813{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
1814{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1815{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1816{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
1817{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
1818{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
1819{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
1820{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
1821{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
1822{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
1823{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1824{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
1825{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
1826{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
1827{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
1828{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
1829{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
1830{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1831{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1832{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
d2f75a6f
GK		 1833{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1834{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1835{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
786e2c0f
C		 1836{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
1837{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
1838{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
1839{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
1840{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
1841{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
1842{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
1843{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
1844{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
1845{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
1846{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
1847{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1848{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
1849{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
1850{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
1851{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
1852{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
1853{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
1854{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
1855{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
1856{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
1857{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
1858{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
1859{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
1860{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
1861{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
1862{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
1863{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
1864{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
1865{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
1866{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1867{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
1868{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
1869{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
1870{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
1871{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
1da5001c 1872{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
786e2c0f
C		 1873{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1874{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1875{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
1876{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
1877{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
1878{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1879{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
1880{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
1881{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
1882{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
1883{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
1884{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
1885{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
1886{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
1887{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
1888{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
1889{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
1890{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
1891{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
1892{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
1893{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
1894{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
1895{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
1896{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
1897{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
1898{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
1899{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
1900{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
1901{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
1902{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
1903{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
1904{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
1905{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
1906{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
1907{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
1908{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
1909{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
252b5132
RH		 1910
1911{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
1912{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
1913
1914{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
1915{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
1916
1917{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
1918
418c1742
MG		 1919{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
1920{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
1921{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
1922{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
1923
252b5132
RH		 1924{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
1925{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
1926{ "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } },
1927{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
1928
1929{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
1930{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
1931{ "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } },
1932{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
1933
1934{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
1935{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
1936{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
1937
1938{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
1939{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
1940{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
1941
1942{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
1943{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
1944{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } },
1945{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } },
1946{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } },
1947{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } },
1948
1949{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
1950{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
1951{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } },
1952{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } },
1953{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } },
1954
802a735e
AM		 1955{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
1956{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
1957{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
1958{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
1959{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
1960{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
1961{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
1962{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
1963{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
1964{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
1965{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
1966{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
1967{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
1968{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
1969{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
1970{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
1971{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
1972{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
1973{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
1974{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
1975{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
1976{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
1977{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
1978{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
1979{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
1980{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
1981{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
1982{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
1983{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1984{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1985{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
1986{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1987{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1988{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
1989{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1990{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1991{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
1992{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1993{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1994{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
1995{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1996{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1997{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
1998{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1999{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2000{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2001{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2002{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2003{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2004{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2005{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2006{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2007{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2008{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2009{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2010{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2011{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2012{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2013{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2014{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2015{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2016{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2017{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2018{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2019{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2020{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2021{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2022{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2023{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2024{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2025{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2026{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2027{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2028{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2029{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2030{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2031{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2032{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2033{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2034{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2035{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2036{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2037{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2038{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2039{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2040{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2041{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2042{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2043{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2044{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2045{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2046{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2047{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2048{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2049{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2050{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2051{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2052{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2053{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2054{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2055{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2056{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2057{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2058{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2059{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2060{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2061{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2062{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2063{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2064{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2065{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2066{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2067{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2068{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2069{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2070{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2071{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2072{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2073{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2074{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2075{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2076{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2077{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2078{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2079{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2080{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2081{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2082{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2083{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2084{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2085{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2086{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2087{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2088{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2089{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2090{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2091{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2092{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2093{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2094{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2095{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2096{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2097{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2098{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2099{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2100{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2101{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2102{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2103{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2104{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2105{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2106{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2107{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2108{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2109{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2110{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2111{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2112{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2113{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2114{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2115{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2116{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2117{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2118{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2119{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2120{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2121{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2122{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2123{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2124{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2125{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2126{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
94efba12
AM		 2127{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2128{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2129{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2130{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2131{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2132{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2133{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2134{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2135{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2136{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2137{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2138{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2139{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2140{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2141{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2142{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2143{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2144{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2145{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2146{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2147{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2148{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2149{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2150{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
802a735e
AM		 2151{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2152{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2153{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2154{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2155{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2156{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2157{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2158{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2159{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2160{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2161{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2162{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2163{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2164{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2165{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2166{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2167{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2168{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2169{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2170{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2171{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2172{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2173{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2174{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2175{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2176{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2177{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2178{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2179{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2180{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2181{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2182{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
94efba12
AM		 2183{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2184{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2185{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2186{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2187{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2188{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2189{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2190{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2191{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2192{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2193{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2194{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2195{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2196{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2197{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2198{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2199{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2200{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2201{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2202{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2203{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2204{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2205{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2206{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
d2f75a6f
GK		 2207{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2208{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
252b5132 2209{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
d2f75a6f
GK		 2210{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2211{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
252b5132 2212{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
d2f75a6f
GK		 2213{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2214{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
252b5132 2215{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
d2f75a6f
GK		 2216{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2217{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
252b5132
RH		 2218{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2219
2220{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
2221{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
2222{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
2223{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2224{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2225
418c1742
MG		 2226{ "b", B(18,0,0), B_MASK, COM, { LI } },
2227{ "bl", B(18,0,1), B_MASK, COM, { LI } },
2228{ "ba", B(18,1,0), B_MASK, COM, { LIA } },
2229{ "bla", B(18,1,1), B_MASK, COM, { LIA } },
252b5132
RH		 2230
2231{ "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
2232
2233{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2234{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2235{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2236{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2237{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12
AM		 2238{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2239{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2240{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2241{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2242{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12
AM		 2243{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2244{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2245{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2246{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2247{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12
AM		 2248{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2249{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2250{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2251{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2252{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12
AM		 2253{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2254{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2255{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2256{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2257{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2258{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2259{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2260{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2261{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2262{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2263{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2264{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2265{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2266{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2267{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2268{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2269{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2270{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2271{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2272{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2273{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2274{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2275{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2276{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2277{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2278{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2279{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2280{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2281{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2282{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2283{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2284{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2285{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2286{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2287{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2288{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2289{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2290{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2291{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2292{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2293{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2294{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2295{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2296{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2297{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2298{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2299{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2300{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2301{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2302{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2303{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2304{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2305{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2306{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2307{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2308{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2309{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2310{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2311{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2312{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2313{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2314{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2315{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2316{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2317{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2318{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2319{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2320{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2321{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2322{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2323{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2324{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2325{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2326{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2327{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2328{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2329{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2330{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2331{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2332{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2333{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2334{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2335{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2336{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2337{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2338{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2339{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2340{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2341{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2342{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2343{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2344{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2345{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2346{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2347{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2348{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2349{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2350{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2351{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2352{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2353{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2354{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2355{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2356{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2357{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2358{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2359{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2360{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2361{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2362{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2363{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2364{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2365{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2366{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2367{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2368{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2369{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2370{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2371{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2372{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2373{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2374{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2375{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2376{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2377{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2378{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2379{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2380{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2381{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2382{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2383{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2384{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2385{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2386{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2387{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2388{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2389{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2390{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2391{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2392{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2393{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2394{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2395{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2396{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2397{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2398{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2399{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2400{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2401{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2402{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2403{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2404{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2405{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2406{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2407{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2408{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2409{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2410{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2411{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2412{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2413{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2414{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2415{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2416{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2417{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2418{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2419{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2420{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2421{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2422{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2423{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2424{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2425{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2426{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2427{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2428{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2429{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2430{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2431{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2432{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2433{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2434{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2435{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2436{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2437{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2438{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2439{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2440{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2441{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2442{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2443{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2444{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132
RH		 2445{ "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } },
2446{ "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } },
d2f75a6f
GK		 2447{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2448{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2449{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2450{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
252b5132
RH		 2451{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2452{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
418c1742
MG		 2453{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
2454{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
252b5132 2455
f509565f
GK		 2456{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
2457
252b5132
RH		 2458{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
2459{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
2460
2461{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
e0c21649 2462{ "rfci", XL(19,51), 0xffffffff, PPC403, { 0 } },
9fa87a06 2463{ "rfci", XL(19,51), 0xffffffff, BOOKE, { 0 } },
252b5132
RH		 2464
2465{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
2466
2467{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
2468
2469{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
2470{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
2471
2472{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2473{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
2474
2475{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
2476
2477{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
2478
2479{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2480{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
2481
2482{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
2483
2484{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
2485{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
2486
2487{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
2488{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
2489{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2490{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2491{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2492{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2493{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2494{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2495{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2496{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2497{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2498{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2499{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2500{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2501{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2502{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2503{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2504{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2505{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2506{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2507{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2508{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2509{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2510{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2511{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2512{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2513{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2514{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2515{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2516{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2517{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2518{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2519{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2520{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2521{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2522{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2523{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2524{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2525{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2526{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2527{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2528{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2529{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2530{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2531{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2532{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2533{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2534{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2535{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2536{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2537{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2538{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2539{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2540{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2541{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2542{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2543{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2544{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2545{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2546{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2547{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2548{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2549{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2550{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2551{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2552{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2553{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2554{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2555{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2556{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2557{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2558{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2559{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2560{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2561{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2562{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2563{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2564{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2565{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2566{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2567{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2568{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2569{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2570{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2571{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2572{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2573{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2574{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2575{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2576{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2577{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2578{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2579{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2580{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2581{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2582{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2583{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2584{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2585{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2586{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2587{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2588{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2589{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2590{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2591{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2592{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2593{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2594{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2595{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2596{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2597{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2598{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2599{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2600{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2601{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2602{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2603{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2604{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12
AM		 2605{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2606{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2607{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2608{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2609{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2610{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
2611{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
2612{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
2613{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
252b5132 2614{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2615{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
2616{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
2617{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
2618{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
252b5132 2619{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2620{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
2621{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
2622{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
2623{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
252b5132 2624{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2625{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
2626{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
2627{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
2628{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
252b5132 2629{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } },
d2f75a6f
GK		 2630{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2631{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
252b5132 2632{ "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } },
d2f75a6f
GK		 2633{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2634{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
252b5132
RH		 2635{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
2636{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
418c1742
MG		 2637{ "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
2638{ "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
252b5132
RH		 2639
2640{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2641{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2642
2643{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2644{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2645
2646{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
2647{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
2648{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2649{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2650{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
2651{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
2652{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2653{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2654
2655{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
2656{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
2657
418c1742
MG		 2658{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
2659{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
2660{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
2661{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
2662
252b5132
RH		 2663{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
2664{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
2665{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
2666{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
2667{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
2668{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
2669
2670{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
2671{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
2672{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
2673
2674{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
2675{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
2676
2677{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
2678{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
2679
2680{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
2681{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
2682
2683{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
2684{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
2685
2686{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
2687{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
2688
2689{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
2690{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
2691{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2692{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
2693{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
2694{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2695
2696{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
2697{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
2698
2699{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2700{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2701
2702{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2703{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2704
2705{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
2706{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
2707{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
2708{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
2709
2710{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
2711{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
2712
2713{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
2714{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
2715{ "cmp", X(31,0), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
2716{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
2717
2718{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
2719{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
2720{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
2721{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
2722{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
2723{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
2724{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
2725{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
2726{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
2727{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
2728{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
2729{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
2730{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
2731{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
2732{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
2733{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
2734{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
2735{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
2736{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
2737{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
2738{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
2739{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
2740{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
2741{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
2742{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
2743{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
2744{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
2745{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
2746{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
2747{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
2748{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
2749
2750{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2751{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2752{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
2753{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2754{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2755{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
2756{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2757{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2758{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
2759{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2760{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2761{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
2762
2763{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2764{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2765
2766{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2767{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2768{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2769{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2770{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2771{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2772{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2773{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2774
2775{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
2776{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
2777
2778{ "mfcr", X(31,19), XRARB_MASK, COM, { RT } },
2779
2780{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
2781
2782{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } },
2783
418c1742
MG		 2784{ "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } },
2785
252b5132
RH		 2786{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } },
2787{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
2788
2789{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
2790{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
2791{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
2792{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
2793
2794{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
2795{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
2796{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
2797{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
2798
2799{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
2800{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
2801
2802{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
2803{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
2804
2805{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
2806{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
2807
418c1742
MG		 2808{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
2809
2810{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA, RB } },
2811
252b5132
RH		 2812{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
2813{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
2814{ "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
2815{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
2816
2817{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
2818{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
2819{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
2820{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
2821{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
2822{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
2823{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
2824{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
2825
2826{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
2827
2828{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
2829
2830{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
2831{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
2832
418c1742
MG		 2833{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
2834
2835{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
2836
252b5132
RH		 2837{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
2838{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
2839
418c1742
MG		 2840{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
2841{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
252b5132
RH		 2842
2843{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
2844{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
2845{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
2846{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
2847{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
2848{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
2849{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
2850{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
2851{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
2852{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
2853{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
2854{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
2855{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
2856{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
2857{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
2858
2859{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2860{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2861
2862{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
2863{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
2864
f509565f
GK		 2865{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
2866
252b5132
RH		 2867{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
2868
2869{ "ldarx", X(31,84), X_MASK, PPC64, { RT, RA, RB } },
2870
2871{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
2872
2873{ "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } },
2874
418c1742
MG		 2875{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
2876
2877{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA, RB } },
2878
252b5132
RH		 2879{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
2880{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
2881{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
2882{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
2883
2884{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
2885{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
2886{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
2887{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
2888
f509565f
GK		 2889{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
2890
2dd46b8b 2891{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
252b5132
RH		 2892
2893{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
2894
2895{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
2896{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
2897{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
2898{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
2899
418c1742
MG		 2900{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA, RB } },
2901
2902{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
2903
252b5132 2904{ "wrtee", X(31,131), XRARB_MASK, PPC403, { RS } },
9fa87a06 2905{ "wrtee", X(31,131), XRARB_MASK, BOOKE, { RS } },
252b5132
RH		 2906
2907{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2908{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2909{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2910{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2911{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2912{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2913{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2914{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2915
2916{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2917{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2918{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2919{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2920{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2921{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2922{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2923{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2924
2925{ "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM, { RS }},
2926{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
2927
2928{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
2929
2930{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA, RB } },
2931
2932{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
2933
2934{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } },
2935{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
2936
418c1742
MG		 2937{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA, RB } },
2938
2939{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA, RB } },
2940
252b5132
RH		 2941{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
2942{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
2943
2944{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
2945{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
2946
2947{ "wrteei", X(31,163), XE_MASK, PPC403, { E } },
9fa87a06 2948{ "wrteei", X(31,163), XE_MASK, BOOKE, { E } },
252b5132 2949
f509565f
GK		 2950{ "mtmsrd", X(31,178), XRARB_MASK, PPC64, { RS } },
2951
252b5132
RH		 2952{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
2953
2954{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
2955{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA, RB } },
2956
2957{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
2958{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
2959
418c1742
MG		 2960{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
2961
252b5132
RH		 2962{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2963{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
2964{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2965{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
2966{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2967{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
2968{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
2969{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
2970
2971{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2972{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
2973{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2974{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
2975{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2976{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
2977{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
2978{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
2979
2980{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
2981
2982{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } },
2983
418c1742 2984{ "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } },
252b5132
RH		 2985
2986{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
2987{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
2988
2989{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
2990{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
2991
418c1742
MG		 2992{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA, RB } },
2993
252b5132
RH		 2994{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2995{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
2996{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2997{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
2998{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2999{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3000{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3001{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3002
3003{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3004{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3005{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3006{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3007
3008{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3009{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3010{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3011{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3012{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3013{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3014{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3015{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3016
3017{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3018{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3019{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3020{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3021{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3022{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3023{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3024{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3025
3026{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3027{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3028
418c1742 3029{ "dcbtst", X(31,246), XRT_MASK, PPC, { CT, RA, RB } },
252b5132
RH		 3030
3031{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3032
3033{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3034{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3035
418c1742
MG		 3036{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3037
3038{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3039
9fa87a06
MG		 3040{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3041
0152a4c6
MG		 3042{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3043
252b5132
RH		 3044{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3045{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3046{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3047{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3048
3049{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3050{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3051{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3052{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3053{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3054{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3055{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3056{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3057
418c1742
MG		 3058{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3059
252b5132
RH		 3060{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3061{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3062
418c1742 3063{ "dcbt", X(31,278), XRT_MASK, PPC, { CT, RA, RB } },
252b5132
RH		 3064
3065{ "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } },
3066
252b5132
RH		 3067{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3068{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3069
418c1742
MG		 3070{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3071
3072{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA, RB } },
3073
252b5132
RH		 3074{ "tlbie", X(31,306), XRTRA_MASK, PPC, { RB } },
3075{ "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } },
3076
3077{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3078
3079{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3080
3081{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3082{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3083
418c1742
MG		 3084{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3085
252b5132
RH		 3086{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3087{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3088{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3089{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3090{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3091{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3092{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3093{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3094{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3095{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3096{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3097{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3098{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3099{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3100{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3101{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3102{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3103{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3104{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3105{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3106{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3107{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3108{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3109{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3110{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3111{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3112{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3113{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3114{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3115{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3116{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3117{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3118{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3119{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
e0c21649 3120{ "mfdcr", X(31,323), X_MASK, PPC403, { RT, SPR } },
9fa87a06 3121{ "mfdcr", X(31,323), X_MASK, BOOKE, { RT, SPR } },
252b5132
RH		 3122
3123{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3124{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3125{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3126{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3127
3128{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3129{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3130{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3131{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3132{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3133{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3134{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3135{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3136{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3137{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3138{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3139{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3140{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3141{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3142{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3143{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3144{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3145{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3146{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3147{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3148{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3149{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3150{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3151{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3152{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3153{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3154{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3155{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3156{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3157{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3158{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
473d3293 3159{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
e0c21649
GK		 3160{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } },
3161{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
3162{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
3163{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
252b5132
RH		 3164{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
3165{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3166{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3167{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3168{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3169{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3170{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3171{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3172{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3173{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3174{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3175{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3176{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3177{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3178{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3179{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3180{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3181{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3182{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3183{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3184{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3185{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3186{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3187{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3188{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3189{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3190{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3191{ "mfm_casid",XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3192{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3193{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3194{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3195{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3196{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3197{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3198{ "mfmi_dbcam",XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3199{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3200{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3201{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3202{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3203{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
e0c21649
GK		 3204{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3205{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3206{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
3207{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
252b5132
RH		 3208{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3209{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3210{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3211{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3212{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3213{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3214{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
e0c21649
GK		 3215{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3216{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3217{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3218{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
252b5132
RH		 3219{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3220{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
e0c21649 3221{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
252b5132 3222{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
e0c21649 3223{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
252b5132 3224{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
e0c21649 3225{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
252b5132 3226{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
e0c21649 3227{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
252b5132 3228{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
e0c21649 3229{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
252b5132
RH		 3230{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
3231{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3232{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3233{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3234{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
3235{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3236{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3237{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3238{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3239{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3240{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3241{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
3242{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
e0c21649 3243{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
252b5132
RH		 3244{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3245{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3246{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3247{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3248{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3249{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3250{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3251{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3252{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3253{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3254{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3255{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3256{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3257{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3258{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3259{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3260
3261{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } },
3262
f5c120c5
MG		 3263{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3264{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3265
252b5132
RH		 3266{ "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } },
3267
418c1742
MG		 3268{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA, RB } },
3269
f5c120c5
MG		 3270{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3271{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3272
e0c21649 3273{ "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } },
252b5132
RH		 3274
3275{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3276{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3277{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3278{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3279
3280{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3281{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3282{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3283{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3284
3285{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3286
e0c21649 3287{ "mftbl", XSPR(31,371,268), XSPR_MASK, PPC, { RT } },
252b5132
RH		 3288{ "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } },
3289{ "mftb", X(31,371), X_MASK, PPC, { RT, TBR } },
3290
3291{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3292
3293{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3294
418c1742
MG		 3295{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3296
9fa87a06
MG		 3297{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3298
418c1742
MG		 3299{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3300{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3301
3302{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3303{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3304
6ba045b1
AM		 3305{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3306
252b5132
RH		 3307{ "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } },
3308
3309{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3310
3311{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3312
3313{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3314
3315{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3316
3317{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3318{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3319
3320{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3321{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3322
418c1742
MG		 3323{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA, RB } },
3324
252b5132
RH		 3325{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3326
3327{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
3328
3329{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3330
418c1742
MG		 3331{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3332
252b5132
RH		 3333{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
3334{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3335{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
3336{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3337
3338{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RT } },
3339{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RT } },
3340{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RT } },
3341{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RT } },
3342{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RT } },
3343{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RT } },
3344{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RT } },
3345{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RT } },
3346{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RT } },
3347{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RT } },
3348{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RT } },
3349{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RT } },
3350{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RT } },
3351{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RT } },
3352{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RT } },
3353{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RT } },
3354{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RT } },
3355{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RT } },
3356{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RT } },
3357{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RT } },
3358{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RT } },
3359{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RT } },
3360{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RT } },
3361{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RT } },
3362{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RT } },
3363{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RT } },
3364{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RT } },
3365{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RT } },
3366{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RT } },
3367{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RT } },
3368{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RT } },
3369{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RT } },
3370{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RT } },
3371{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RT } },
e0c21649 3372{ "mtdcr", X(31,451), X_MASK, PPC403, { SPR, RS } },
9fa87a06 3373{ "mtdcr", X(31,451), X_MASK, BOOKE, { SPR, RS } },
252b5132 3374
418c1742
MG		 3375{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3376{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3377
252b5132
RH		 3378{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3379{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3380{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3381{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3382
418c1742
MG		 3383{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3384{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3385
252b5132
RH		 3386{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
3387{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
3388{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
3389{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
3390
3391{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
3392{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
3393{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
3394{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
3395{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
3396{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
3397{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
3398{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
3399{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
3400{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
3401{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
3402{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
3403{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
3404{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
3405{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RT } },
3406{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RT } },
3407{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RT } },
3408{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RT } },
3409{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RT } },
3410{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RT } },
3411{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RT } },
3412{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RT } },
3413{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RT } },
3414{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RT } },
3415{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RT } },
3416{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RT } },
3417{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RT } },
3418{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RT } },
3419{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RT } },
3420{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RT } },
473d3293 3421{ "mtvrsave",XSPR(31,467,256), XSPR_MASK, PPCVEC, { RT } },
252b5132
RH		 3422{ "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } },
3423{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RT } },
3424{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } },
3425{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RT } },
3426{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RT } },
e0c21649
GK		 3427{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405, { RT } },
3428{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405, { RT } },
3429{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405, { RT } },
3430{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405, { RT } },
252b5132
RH		 3431{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
3432{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
3433{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
3434{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
3435{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3436{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3437{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3438{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3439{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RT } },
3440{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RT } },
e0c21649
GK		 3441{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RT } },
3442{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RT } },
3443{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RT } },
3444{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RT } },
3445{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RT } },
3446{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RT } },
3447{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RT } },
3448{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RT } },
3449{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RT } },
3450{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RT } },
252b5132
RH		 3451{ "mticdbdr",XSPR(31,467,979), XSPR_MASK, PPC403, { RT } },
3452{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RT } },
e0c21649 3453{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RT } },
252b5132
RH		 3454{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RT } },
3455{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RT } },
3456{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RT } },
3457{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RT } },
3458{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RT } },
3459{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RT } },
3460{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RT } },
3461{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RT } },
3462{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RT } },
3463{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RT } },
e0c21649 3464{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RT } },
252b5132
RH		 3465{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RT } },
3466{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RT } },
3467{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RT } },
3468{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RT } },
3469{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RT } },
3470{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RT } },
3471{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RT } },
3472{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RT } },
3473{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RT } },
3474{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RT } },
24a7a601
C		 3475{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RT } },
3476{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RT } },
3477{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RT } },
3478{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RT } },
3479{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RT } },
3480{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RT } },
3481{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RT } },
3482{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RT } },
3483{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RT } },
3484{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RT } },
3485{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RT } },
3486{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RT } },
3487{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RT } },
3488{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RT } },
3489{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RT } },
3490{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RT } },
3491{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RT } },
3492{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RT } },
3493{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RT } },
252b5132
RH		 3494{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
3495
3496{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
3497
3498{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
3499{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
3500
418c1742
MG		 3501{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
3502
4db3857a 3503{ "dcread", X(31,486), X_MASK, PPC403, { RT, RA, RB }},
252b5132
RH		 3504
3505{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
418c1742 3506{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
252b5132
RH		 3507{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
3508{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
418c1742 3509{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
252b5132
RH		 3510{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
3511
3512{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3513{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3514{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3515{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3516
418c1742
MG		 3517{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3518{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3519
252b5132
RH		 3520{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
3521{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
3522{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
3523{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
3524
3525{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
3526
3527{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
3528
418c1742
MG		 3529{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
3530
252b5132
RH		 3531{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
3532
418c1742
MG		 3533{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE, { BF } },
3534
252b5132
RH		 3535{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
3536
3537{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } },
3538{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
3539
3540{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA, RB } },
3541{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
3542
3543{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB } },
3544
3545{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
3546{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
3547{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
3548{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
3549
3550{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
3551{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
3552
3553{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
3554{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
3555
3556{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
3557{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
3558
418c1742
MG		 3559{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA, RB } },
3560
3561{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA, RB } },
3562
252b5132
RH		 3563{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
3564
3565{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
3566
418c1742
MG		 3567{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
3568
252b5132
RH		 3569{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
3570
3571{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } },
3572{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } },
3573
6ba045b1
AM		 3574{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPCONLY, { 0 } },
3575{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
3576{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
252b5132 3577{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
9fa87a06 3578{ "msync", X(31,598), 0xf80007fe, BOOKE, { 0 } },
252b5132
RH		 3579
3580{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } },
3581
418c1742
MG		 3582{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA, RB } },
3583
252b5132
RH		 3584{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
3585
3586{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
3587
3588{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
3589
418c1742
MG		 3590{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
3591
252b5132
RH		 3592{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
3593
3594{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } },
3595{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA, RB } },
3596
3597{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA, RB } },
3598{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA, RB } },
3599
3600{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA, RB } },
3601
3602{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
3603{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
3604
3605{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
3606{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
3607
418c1742
MG		 3608{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA, RB } },
3609
3610{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA, RB } },
3611
252b5132
RH		 3612{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
3613
3614{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
3615{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
3616
418c1742
MG		 3617{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
3618
252b5132
RH		 3619{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } },
3620{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB } },
3621
3622{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA, RB } },
3623
3624{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
3625{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
3626
3627{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
3628{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
3629
418c1742
MG		 3630{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA, RB } },
3631
e0c21649 3632{ "dcba", X(31,758), XRT_MASK, PPC405, { RA, RB } },
9fa87a06 3633{ "dcba", X(31,758), XRT_MASK, BOOKE, { RA, RB } },
e0c21649 3634
252b5132
RH		 3635{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
3636
3637{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
3638{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
3639
418c1742
MG		 3640{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
3641
3642{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
3643
3644{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
3645{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE, { RA, RB } },
3646
252b5132
RH		 3647{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } },
3648
3649{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
3650{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
3651{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
3652{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
3653
3654{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
3655{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
3656
418c1742
MG		 3657{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA, RB } },
3658
3659{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA, RB } },
3660{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA, RB } },
3661
252b5132
RH		 3662{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
3663
f5c120c5
MG		 3664{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
3665{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { STRM } },
3666
252b5132
RH		 3667{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
3668{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
3669{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
3670{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
3671
6ba045b1
AM		 3672{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
3673
252b5132 3674{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
9fa87a06 3675{ "mbar", X(31,854), 0xffffffff, BOOKE, { MO } },
252b5132 3676
9fa87a06
MG		 3677{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
3678{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
252b5132 3679
9fa87a06
MG		 3680{ "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
3681{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE, { RA, RB } },
418c1742 3682
6ba045b1
AM		 3683{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
3684
252b5132
RH		 3685{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } },
3686
3687{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
3688{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
3689
3690{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
3691{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
3692
3693{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
3694{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
3695{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
3696{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
3697
418c1742
MG		 3698{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA, RB } },
3699
3700{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA, RB } },
3701
ff3a6ee3 3702{ "tlbre", X(31,946), X_MASK, BOOKE, { RT, RA, WS } },
418c1742 3703
e0c21649
GK		 3704{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
3705{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
252b5132
RH		 3706
3707{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
3708{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
3709
3710{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
3711{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
3712
418c1742
MG		 3713{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
3714
e0c21649 3715{ "iccci", X(31,966), XRT_MASK, PPC403, { RA, RB } },
252b5132
RH		 3716
3717{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
e0c21649
GK		 3718
3719{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
3720{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
252b5132
RH		 3721{ "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } },
3722
ff3a6ee3 3723{ "tlbwe", X(31,978), X_MASK, BOOKE, { RT, RA, WS } },
9fa87a06 3724
252b5132
RH		 3725{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
3726
3727{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
3728
3729{ "extsw", XRC(31,986,0), XRB_MASK, PPC, { RA, RS } },
3730{ "extsw.", XRC(31,986,1), XRB_MASK, PPC, { RA, RS } },
3731
3732{ "icread", X(31,998), XRT_MASK, PPC403, { RA, RB } },
3733
418c1742
MG		 3734{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
3735{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA, RB } },
3736
252b5132
RH		 3737{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
3738
3739{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
3740{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
3741
418c1742
MG		 3742{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
3743
786e2c0f
C		 3744{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
3745{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
3746{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
3747{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
3748{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
3749{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
3750{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
3751{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
3752{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
3753{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
3754{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
3755{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
3756
252b5132
RH		 3757{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } },
3758{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } },
3759
3760{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
3761{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA } },
3762
3763{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA } },
3764
3765{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
3766
3767{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } },
3768{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA } },
3769
3770{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
3771{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA } },
3772
3773{ "stb", OP(38), OP_MASK, COM, { RS, D, RA } },
3774
3775{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
3776
3777{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA } },
3778
3779{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
3780
3781{ "lha", OP(42), OP_MASK, COM, { RT, D, RA } },
3782
3783{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
3784
3785{ "sth", OP(44), OP_MASK, COM, { RS, D, RA } },
3786
3787{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
3788
3789{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
3790{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA } },
3791
3792{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } },
3793{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA } },
3794
3795{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } },
3796
3797{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
3798
3799{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } },
3800
3801{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
3802
3803{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } },
3804
3805{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
3806
3807{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } },
3808
3809{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
3810
3811{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
3812
3813{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
3814
418c1742
MG		 3815{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA } },
3816{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
3817{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA } },
3818{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
3819{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA } },
3820{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
3821{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA } },
3822{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
3823{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA } },
3824{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
3825{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA } },
3826{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
3827{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA } },
3828{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
3829
802a735e
AM		 3830{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA } },
3831
3832{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
3833
3834{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } },
3835
252b5132
RH		 3836{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3837{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3838
3839{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3840{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3841
3842{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3843{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3844
3845{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
3846{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
3847
3848{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
3849{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
3850
3851{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
3852{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
3853
3854{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3855{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3856
3857{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3858{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3859
3860{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3861{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3862
3863{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3864{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3865
3866{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
3867
3868{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
3869
418c1742 3870{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA } },
418c1742 3871{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA } },
418c1742
MG		 3872{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA } },
3873{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
3874{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA } },
3875{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
3876{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA } },
3877{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
3878{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA } },
3879{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
3880{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA } },
3881{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
3882
802a735e
AM		 3883{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } },
3884
3885{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
3886
252b5132
RH		 3887{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
3888
3889{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
3890{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
3891
3892{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
3893{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
3894{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
3895{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
3896
3897{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
3898{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
3899{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
3900{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
3901
3902{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3903{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3904{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3905{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3906
3907{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3908{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3909{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3910{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3911
3912{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3913{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3914{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3915{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3916
3917{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
3918{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
3919
3920{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3921{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3922
3923{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
3924{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
3925{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
3926{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
3927
3928{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
3929{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
3930
3931{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3932{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3933{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3934{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3935
3936{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3937{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3938{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3939{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3940
3941{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3942{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3943{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3944{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3945
3946{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3947{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3948{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3949{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3950
3951{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
3952
3953{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
3954{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
3955
3956{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
3957{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
3958
3959{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
3960
3961{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
3962{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
3963
3964{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
3965{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
3966
3967{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3968{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3969
3970{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
3971{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
3972
3973{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
3974{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
3975
3976{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
3977{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
3978
3979{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
3980{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
3981
3982{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
3983{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
3984
3985{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
3986{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
3987
3988{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
3989{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
3990
3991};
3992
3993const int powerpc_num_opcodes =
3994 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
3995\f
3996/* The macro table. This is only used by the assembler. */
3997
3998/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
3999 when x=0; 32-x when x is between 1 and 31; are negative if x is
4000 negative; and are 32 or more otherwise. This is what you want
4001 when, for instance, you are emulating a right shift by a
4002 rotate-left-and-mask, because the underlying instructions support
4003 shifts of size 0 but not shifts of size 32. By comparison, when
4004 extracting x bits from some word you want to use just 32-x, because
4005 the underlying instructions don't support extracting 0 bits but do
4006 support extracting the whole word (32 bits in this case). */
4007
4008const struct powerpc_macro powerpc_macros[] = {
4009{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
4010{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
4011{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4012{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4013{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4014{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4015{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4016{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4017{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
4018{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
4019{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4020{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4021{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
4022{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
4023{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
4024{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
4025
4026{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
4027{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
4028{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
4029{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
4030{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4031{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4032{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4033{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4034{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4035{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4036{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
4037{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
4038{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
4039{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
4040{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4041{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4042{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4043{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4044{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
4045{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
4046{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4047{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4048
4049};
4050
4051const int powerpc_num_macros =
4052 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
GDB Binutils - Deliverables
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