projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Automatic date update in version.in
[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c
CommitLineData
252b5132 1/* ppc-opc.c -- PowerPC opcode list
6f2750fe 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
252b5132
RH		 3 Written by Ian Lance Taylor, Cygnus Support
4
9b201bb5 5 This file is part of the GNU opcodes library.
252b5132 6
9b201bb5
NC		 7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
252b5132 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
252b5132 16
112290ab 17 You should have received a copy of the GNU General Public License
9b201bb5
NC		 18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
252b5132 21
0d8dfecf 22#include "sysdep.h"
df7b86aa 23#include <stdio.h>
252b5132
RH		 24#include "opcode/ppc.h"
25#include "opintl.h"
26
27/* This file holds the PowerPC opcode table. The opcode table
28 includes almost all of the extended instruction mnemonics. This
29 permits the disassembler to use them, and simplifies the assembler
30 logic, at the cost of increasing the table size. The table is
31 strictly constant data, so the compiler should be able to put it in
32 the .text section.
33
34 This file also holds the operand table. All knowledge about
35 inserting operands into instructions and vice-versa is kept in this
36 file. */
37\f
38/* Local insertion and extraction functions. */
39
b9c361e0
JL		 40static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **);
41static long extract_arx (unsigned long, ppc_cpu_t, int *);
42static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **);
43static long extract_ary (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 44static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
45static long extract_bat (unsigned long, ppc_cpu_t, int *);
46static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
47static long extract_bba (unsigned long, ppc_cpu_t, int *);
48static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
49static long extract_bdm (unsigned long, ppc_cpu_t, int *);
50static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
51static long extract_bdp (unsigned long, ppc_cpu_t, int *);
52static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
53static long extract_bo (unsigned long, ppc_cpu_t, int *);
54static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
55static long extract_boe (unsigned long, ppc_cpu_t, int *);
7b934113 56static unsigned long insert_esync (unsigned long, long, ppc_cpu_t, const char **);
a680de9a
PB		 57static unsigned long insert_dcmxs (unsigned long, long, ppc_cpu_t, const char **);
58static long extract_dcmxs (unsigned long, ppc_cpu_t, int *);
59static unsigned long insert_dxd (unsigned long, long, ppc_cpu_t, const char **);
60static long extract_dxd (unsigned long, ppc_cpu_t, int *);
61static unsigned long insert_dxdn (unsigned long, long, ppc_cpu_t, const char **);
62static long extract_dxdn (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 63static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
64static long extract_fxm (unsigned long, ppc_cpu_t, int *);
a680de9a
PB		 65static unsigned long insert_l0 (unsigned long, long, ppc_cpu_t, const char **);
66static long extract_l0 (unsigned long, ppc_cpu_t, int *);
67static unsigned long insert_l1 (unsigned long, long, ppc_cpu_t, const char **);
68static long extract_l1 (unsigned long, ppc_cpu_t, int *);
b9c361e0
JL		 69static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
70static long extract_li20 (unsigned long, ppc_cpu_t, int *);
aea77599 71static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
fa452fa6
PB		 72static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
73static long extract_mbe (unsigned long, ppc_cpu_t, int *);
74static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
75static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
76static long extract_nb (unsigned long, ppc_cpu_t, int *);
989993d8 77static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **);
fa452fa6
PB		 78static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
79static long extract_nsi (unsigned long, ppc_cpu_t, int *);
b9c361e0
JL		 80static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **);
81static long extract_oimm (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 82static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
83static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
84static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
85static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
86static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
87static long extract_rbs (unsigned long, ppc_cpu_t, int *);
989993d8 88static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **);
b9c361e0
JL		 89static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **);
90static long extract_rx (unsigned long, ppc_cpu_t, int *);
91static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **);
92static long extract_ry (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 93static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
94static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
b9c361e0
JL		 95static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **);
96static long extract_sci8 (unsigned long, ppc_cpu_t, int *);
97static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **);
98static long extract_sci8n (unsigned long, ppc_cpu_t, int *);
99static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **);
100static long extract_sd4h (unsigned long, ppc_cpu_t, int *);
101static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **);
102static long extract_sd4w (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 103static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
104static long extract_spr (unsigned long, ppc_cpu_t, int *);
105static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
106static long extract_sprg (unsigned long, ppc_cpu_t, int *);
107static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
108static long extract_tbr (unsigned long, ppc_cpu_t, int *);
9b4e5766
PB		 109static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
110static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
a680de9a
PB		 111static unsigned long insert_xtq6 (unsigned long, long, ppc_cpu_t, const char **);
112static long extract_xtq6 (unsigned long, ppc_cpu_t, int *);
9b4e5766
PB		 113static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
114static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
115static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
116static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
117static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
118static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
066be9f7
PB		 119static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
120static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
121static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
122static long extract_dm (unsigned long, ppc_cpu_t, int *);
b9c361e0
JL		 123static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **);
124static long extract_vlesi (unsigned long, ppc_cpu_t, int *);
125static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **);
126static long extract_vlensi (unsigned long, ppc_cpu_t, int *);
127static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **);
128static long extract_vleui (unsigned long, ppc_cpu_t, int *);
129static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **);
130static long extract_vleil (unsigned long, ppc_cpu_t, int *);
252b5132
RH		 131\f
132/* The operands table.
133
717bbdf1 134 The fields are bitm, shift, insert, extract, flags.
252b5132
RH		 135
136 We used to put parens around the various additions, like the one
137 for BA just below. However, that caused trouble with feeble
138 compilers with a limit on depth of a parenthesized expression, like
139 (reportedly) the compiler in Microsoft Developer Studio 5. So we
140 omit the parens, since the macros are never used in a context where
141 the addition will be ambiguous. */
142
143const struct powerpc_operand powerpc_operands[] =
144{
145 /* The zero index is used to indicate the end of the list of
146 operands. */
147#define UNUSED 0
bbac1f2a 148 { 0, 0, NULL, NULL, 0 },
252b5132
RH		 149
150 /* The BA field in an XL form instruction. */
151#define BA UNUSED + 1
717bbdf1
AM		 152 /* The BI field in a B form or XL form instruction. */
153#define BI BA
154#define BI_MASK (0x1f << 16)
b9c361e0 155 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
252b5132
RH		 156
157 /* The BA field in an XL form instruction when it must be the same
158 as the BT field in the same instruction. */
159#define BAT BA + 1
b84bf58a 160 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
252b5132
RH		 161
162 /* The BB field in an XL form instruction. */
163#define BB BAT + 1
164#define BB_MASK (0x1f << 11)
b9c361e0 165 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT },
252b5132
RH		 166
167 /* The BB field in an XL form instruction when it must be the same
168 as the BA field in the same instruction. */
169#define BBA BB + 1
c7a5aa9c
PB		 170 /* The VB field in a VX form instruction when it must be the same
171 as the VA field in the same instruction. */
172#define VBA BBA
b84bf58a 173 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
252b5132
RH		 174
175 /* The BD field in a B form instruction. The lower two bits are
176 forced to zero. */
177#define BD BBA + 1
b84bf58a 178 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 179
180 /* The BD field in a B form instruction when absolute addressing is
181 used. */
182#define BDA BD + 1
b84bf58a 183 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 184
185 /* The BD field in a B form instruction when the - modifier is used.
186 This sets the y bit of the BO field appropriately. */
187#define BDM BDA + 1
b84bf58a 188 { 0xfffc, 0, insert_bdm, extract_bdm,
e43de63c 189 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 190
191 /* The BD field in a B form instruction when the - modifier is used
192 and absolute address is used. */
193#define BDMA BDM + 1
b84bf58a 194 { 0xfffc, 0, insert_bdm, extract_bdm,
e43de63c 195 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 196
197 /* The BD field in a B form instruction when the + modifier is used.
198 This sets the y bit of the BO field appropriately. */
199#define BDP BDMA + 1
b84bf58a 200 { 0xfffc, 0, insert_bdp, extract_bdp,
e43de63c 201 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 202
203 /* The BD field in a B form instruction when the + modifier is used
204 and absolute addressing is used. */
205#define BDPA BDP + 1
b84bf58a 206 { 0xfffc, 0, insert_bdp, extract_bdp,
e43de63c 207 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 208
209 /* The BF field in an X or XL form instruction. */
210#define BF BDPA + 1
717bbdf1
AM		 211 /* The CRFD field in an X form instruction. */
212#define CRFD BF
b9c361e0
JL		 213 /* The CRD field in an XL form instruction. */
214#define CRD BF
215 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG },
252b5132 216
ea192fa3
PB		 217 /* The BF field in an X or XL form instruction. */
218#define BFF BF + 1
219 { 0x7, 23, NULL, NULL, 0 },
220
252b5132
RH		 221 /* An optional BF field. This is used for comparison instructions,
222 in which an omitted BF field is taken as zero. */
ea192fa3 223#define OBF BFF + 1
b9c361e0 224 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
252b5132
RH		 225
226 /* The BFA field in an X or XL form instruction. */
227#define BFA OBF + 1
b9c361e0 228 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG },
252b5132 229
252b5132
RH		 230 /* The BO field in a B form instruction. Certain values are
231 illegal. */
717bbdf1 232#define BO BFA + 1
252b5132 233#define BO_MASK (0x1f << 21)
b84bf58a 234 { 0x1f, 21, insert_bo, extract_bo, 0 },
252b5132
RH		 235
236 /* The BO field in a B form instruction when the + or - modifier is
237 used. This is like the BO field, but it must be even. */
238#define BOE BO + 1
b84bf58a 239 { 0x1e, 21, insert_boe, extract_boe, 0 },
252b5132 240
6fd3a02d
PB		 241 /* The RM field in an X form instruction. */
242#define RM BOE + 1
243 { 0x3, 11, NULL, NULL, 0 },
244
245#define BH RM + 1
b84bf58a 246 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
d0618d1c 247
252b5132 248 /* The BT field in an X or XL form instruction. */
d0618d1c 249#define BT BH + 1
b9c361e0
JL		 250 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT },
251
252 /* The BI16 field in a BD8 form instruction. */
253#define BI16 BT + 1
254 { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT },
255
256 /* The BI32 field in a BD15 form instruction. */
257#define BI32 BI16 + 1
258 { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
259
260 /* The BO32 field in a BD15 form instruction. */
261#define BO32 BI32 + 1
262 { 0x3, 20, NULL, NULL, 0 },
263
264 /* The B8 field in a BD8 form instruction. */
265#define B8 BO32 + 1
266 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
267
268 /* The B15 field in a BD15 form instruction. The lowest bit is
269 forced to zero. */
270#define B15 B8 + 1
271 { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
272
273 /* The B24 field in a BD24 form instruction. The lowest bit is
274 forced to zero. */
275#define B24 B15 + 1
276 { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 277
278 /* The condition register number portion of the BI field in a B form
279 or XL form instruction. This is used for the extended
280 conditional branch mnemonics, which set the lower two bits of the
281 BI field. This field is optional. */
b9c361e0
JL		 282#define CR B24 + 1
283 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
252b5132 284
23976049
EZ		 285 /* The CRB field in an X form instruction. */
286#define CRB CR + 1
717bbdf1
AM		 287 /* The MB field in an M form instruction. */
288#define MB CRB
289#define MB_MASK (0x1f << 6)
b84bf58a 290 { 0x1f, 6, NULL, NULL, 0 },
23976049 291
b9c361e0
JL		 292 /* The CRD32 field in an XL form instruction. */
293#define CRD32 CRB + 1
294 { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG },
295
23976049 296 /* The CRFS field in an X form instruction. */
b9c361e0
JL		 297#define CRFS CRD32 + 1
298 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG },
299
300#define CRS CRFS + 1
301 { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
23976049 302
418c1742 303 /* The CT field in an X form instruction. */
b9c361e0 304#define CT CRS + 1
717bbdf1
AM		 305 /* The MO field in an mbar instruction. */
306#define MO CT
b84bf58a 307 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
418c1742 308
252b5132
RH		 309 /* The D field in a D form instruction. This is a displacement off
310 a register, and implies that the next operand is a register in
311 parentheses. */
418c1742 312#define D CT + 1
b84bf58a 313 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
252b5132 314
b9c361e0
JL		 315 /* The D8 field in a D form instruction. This is a displacement off
316 a register, and implies that the next operand is a register in
317 parentheses. */
318#define D8 D + 1
319 { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
320
a680de9a
PB		 321 /* The DCMX field in an X form instruction. */
322#define DCMX D8 + 1
323 { 0x7f, 16, NULL, NULL, 0 },
324
325 /* The split DCMX field in an X form instruction. */
326#define DCMXS DCMX + 1
327 { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 },
328
adadcc0c
AM		 329 /* The DQ field in a DQ form instruction. This is like D, but the
330 lower four bits are forced to zero. */
a680de9a 331#define DQ DCMXS + 1
b84bf58a
AM		 332 { 0xfff0, 0, NULL, NULL,
333 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
adadcc0c 334
252b5132
RH		 335 /* The DS field in a DS form instruction. This is like D, but the
336 lower two bits are forced to zero. */
adadcc0c 337#define DS DQ + 1
b84bf58a
AM		 338 { 0xfffc, 0, NULL, NULL,
339 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
252b5132 340
c0637f3a
PB		 341 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
342 unsigned imediate */
19a6653c 343#define DUIS DS + 1
c0637f3a 344#define BHRBE DUIS
19a6653c
AM		 345 { 0x3ff, 11, NULL, NULL, 0 },
346
a680de9a
PB		 347 /* The split D field in a DX form instruction. */
348#define DXD DUIS + 1
349 { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd,
350 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
351
352 /* The split ND field in a DX form instruction.
353 This is the same as the DX field, only negated. */
354#define NDXD DXD + 1
355 { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn,
356 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
357
252b5132 358 /* The E field in a wrteei instruction. */
c3d65c1c 359 /* And the W bit in the pair singles instructions. */
c0637f3a 360 /* And the ST field in a VX form instruction. */
a680de9a 361#define E NDXD + 1
c3d65c1c 362#define PSW E
c0637f3a 363#define ST E
b84bf58a 364 { 0x1, 15, NULL, NULL, 0 },
252b5132
RH		 365
366 /* The FL1 field in a POWER SC form instruction. */
367#define FL1 E + 1
717bbdf1
AM		 368 /* The U field in an X form instruction. */
369#define U FL1
b84bf58a 370 { 0xf, 12, NULL, NULL, 0 },
252b5132
RH		 371
372 /* The FL2 field in a POWER SC form instruction. */
373#define FL2 FL1 + 1
b84bf58a 374 { 0x7, 2, NULL, NULL, 0 },
252b5132
RH		 375
376 /* The FLM field in an XFL form instruction. */
377#define FLM FL2 + 1
b84bf58a 378 { 0xff, 17, NULL, NULL, 0 },
252b5132
RH		 379
380 /* The FRA field in an X or A form instruction. */
381#define FRA FLM + 1
382#define FRA_MASK (0x1f << 16)
b84bf58a 383 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
252b5132 384
989993d8
JB		 385 /* The FRAp field of DFP instructions. */
386#define FRAp FRA + 1
387 { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR },
388
252b5132 389 /* The FRB field in an X or A form instruction. */
989993d8 390#define FRB FRAp + 1
252b5132 391#define FRB_MASK (0x1f << 11)
b84bf58a 392 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
252b5132 393
989993d8
JB		 394 /* The FRBp field of DFP instructions. */
395#define FRBp FRB + 1
396 { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR },
397
252b5132 398 /* The FRC field in an A form instruction. */
989993d8 399#define FRC FRBp + 1
252b5132 400#define FRC_MASK (0x1f << 6)
b84bf58a 401 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 402
403 /* The FRS field in an X form instruction or the FRT field in a D, X
404 or A form instruction. */
405#define FRS FRC + 1
406#define FRT FRS
b84bf58a 407 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
252b5132 408
989993d8
JB		 409 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
410 instructions. */
411#define FRSp FRS + 1
412#define FRTp FRSp
413 { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR },
414
252b5132 415 /* The FXM field in an XFX instruction. */
989993d8 416#define FXM FRSp + 1
b84bf58a 417 { 0xff, 12, insert_fxm, extract_fxm, 0 },
c168870a
AM		 418
419 /* Power4 version for mfcr. */
420#define FXM4 FXM + 1
e43de63c
AM		 421 { 0xff, 12, insert_fxm, extract_fxm,
422 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
11a0cf2e
PB		 423 /* If the FXM4 operand is ommitted, use the sentinel value -1. */
424 { -1, -1, NULL, NULL, 0},
252b5132 425
b9c361e0 426 /* The IMM20 field in an LI instruction. */
11a0cf2e 427#define IMM20 FXM4 + 2
b9c361e0
JL		 428 { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},
429
252b5132 430 /* The L field in a D or X form instruction. */
b9c361e0 431#define L IMM20 + 1
5817ffd1
PB		 432 /* The R field in a HTM X form instruction. */
433#define HTM_R L
b84bf58a 434 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
252b5132 435
a680de9a
PB		 436 /* The L field in an X form instruction which must be zero. */
437#define L0 L + 1
438 { 0x1, 21, insert_l0, extract_l0, PPC_OPERAND_OPTIONAL },
439
440 /* The L field in an X form instruction which must be one. */
441#define L1 L0 + 1
442 { 0x1, 21, insert_l1, extract_l1, 0 },
443
1ed8e1e4 444 /* The LEV field in a POWER SVC form instruction. */
a680de9a 445#define SVC_LEV L1 + 1
b84bf58a 446 { 0x7f, 5, NULL, NULL, 0 },
252b5132 447
1ed8e1e4
AM		 448 /* The LEV field in an SC form instruction. */
449#define LEV SVC_LEV + 1
b84bf58a 450 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
1ed8e1e4 451
252b5132
RH		 452 /* The LI field in an I form instruction. The lower two bits are
453 forced to zero. */
454#define LI LEV + 1
b84bf58a 455 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 456
457 /* The LI field in an I form instruction when used as an absolute
458 address. */
459#define LIA LI + 1
b84bf58a 460 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132 461
066be9f7 462 /* The LS or WC field in an X (sync or wait) form instruction. */
6ba045b1 463#define LS LIA + 1
066be9f7 464#define WC LS
7b934113 465 { 0x3, 21, insert_ls, NULL, PPC_OPERAND_OPTIONAL },
6ba045b1 466
252b5132 467 /* The ME field in an M form instruction. */
717bbdf1 468#define ME LS + 1
252b5132 469#define ME_MASK (0x1f << 1)
b84bf58a 470 { 0x1f, 1, NULL, NULL, 0 },
252b5132
RH		 471
472 /* The MB and ME fields in an M form instruction expressed a single
473 operand which is a bitmask indicating which bits to select. This
474 is a two operand form using PPC_OPERAND_NEXT. See the
475 description in opcode/ppc.h for what this means. */
476#define MBE ME + 1
b84bf58a 477 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
eb42fac1 478 { -1, 0, insert_mbe, extract_mbe, 0 },
252b5132
RH		 479
480 /* The MB or ME field in an MD or MDS form instruction. The high
481 bit is wrapped to the low end. */
482#define MB6 MBE + 2
483#define ME6 MB6
484#define MB6_MASK (0x3f << 5)
b84bf58a 485 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
252b5132
RH		 486
487 /* The NB field in an X form instruction. The value 32 is stored as
488 0. */
717bbdf1 489#define NB MB6 + 1
b84bf58a 490 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
252b5132 491
989993d8
JB		 492 /* The NBI field in an lswi instruction, which has special value
493 restrictions. The value 32 is stored as 0. */
494#define NBI NB + 1
495 { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 },
496
252b5132
RH		 497 /* The NSI field in a D form instruction. This is the same as the
498 SI field, only negated. */
989993d8 499#define NSI NBI + 1
b84bf58a 500 { 0xffff, 0, insert_nsi, extract_nsi,
e43de63c
AM		 501 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
502
503 /* The NSI field in a D form instruction when we accept a wide range
504 of positive values. */
505#define NSISIGNOPT NSI + 1
514e58b7 506 { 0xffff, 0, insert_nsi, extract_nsi,
e43de63c 507 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
252b5132 508
adadcc0c 509 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
e43de63c 510#define RA NSISIGNOPT + 1
252b5132 511#define RA_MASK (0x1f << 16)
b84bf58a 512 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
252b5132 513
fdd12ef3
AM		 514 /* As above, but 0 in the RA field means zero, not r0. */
515#define RA0 RA + 1
b84bf58a 516 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
fdd12ef3 517
989993d8 518 /* The RA field in the DQ form lq or an lswx instruction, which have special
adadcc0c 519 value restrictions. */
fdd12ef3 520#define RAQ RA0 + 1
989993d8 521#define RAX RAQ
b84bf58a 522 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
adadcc0c 523
252b5132
RH		 524 /* The RA field in a D or X form instruction which is an updating
525 load, which means that the RA field may not be zero and may not
526 equal the RT field. */
adadcc0c 527#define RAL RAQ + 1
b84bf58a 528 { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
252b5132
RH		 529
530 /* The RA field in an lmw instruction, which has special value
531 restrictions. */
532#define RAM RAL + 1
b84bf58a 533 { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
252b5132
RH		 534
535 /* The RA field in a D or X form instruction which is an updating
536 store or an updating floating point load, which means that the RA
537 field may not be zero. */
538#define RAS RAM + 1
b84bf58a 539 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
252b5132 540
cee62821
PB		 541 /* The RA field of the tlbwe, dccci and iccci instructions,
542 which are optional. */
fdd12ef3 543#define RAOPT RAS + 1
b84bf58a 544 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 545
252b5132 546 /* The RB field in an X, XO, M, or MDS form instruction. */
fdd12ef3 547#define RB RAOPT + 1
252b5132 548#define RB_MASK (0x1f << 11)
b84bf58a 549 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
252b5132
RH		 550
551 /* The RB field in an X form instruction when it must be the same as
552 the RS field in the instruction. This is used for extended
553 mnemonics like mr. */
554#define RBS RB + 1
b84bf58a 555 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
252b5132 556
989993d8
JB		 557 /* The RB field in an lswx instruction, which has special value
558 restrictions. */
559#define RBX RBS + 1
560 { 0x1f, 11, insert_rbx, NULL, PPC_OPERAND_GPR },
561
cee62821 562 /* The RB field of the dccci and iccci instructions, which are optional. */
989993d8 563#define RBOPT RBX + 1
cee62821
PB		 564 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
565
a680de9a
PB		 566 /* The RC register field in an maddld, maddhd or maddhdu instruction. */
567#define RC RBOPT + 1
568 { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR },
569
252b5132
RH		 570 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
571 instruction or the RT field in a D, DS, X, XFX or XO form
572 instruction. */
a680de9a 573#define RS RC + 1
252b5132
RH		 574#define RT RS
575#define RT_MASK (0x1f << 21)
b9c361e0 576#define RD RS
b84bf58a 577 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
252b5132 578
588925d0
PB		 579 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
580 which have special value restrictions. */
adadcc0c 581#define RSQ RS + 1
717bbdf1 582#define RTQ RSQ
588925d0 583 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR },
adadcc0c 584
1f6c9eb0 585 /* The RS field of the tlbwe instruction, which is optional. */
717bbdf1 586#define RSO RSQ + 1
eed0d89a 587#define RTO RSO
b84bf58a 588 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 589
b9c361e0
JL		 590 /* The RX field of the SE_RR form instruction. */
591#define RX RSO + 1
592 { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR },
593
594 /* The ARX field of the SE_RR form instruction. */
595#define ARX RX + 1
596 { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR },
597
598 /* The RY field of the SE_RR form instruction. */
599#define RY ARX + 1
600#define RZ RY
601 { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR },
602
603 /* The ARY field of the SE_RR form instruction. */
604#define ARY RY + 1
605 { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR },
606
607 /* The SCLSCI8 field in a D form instruction. */
608#define SCLSCI8 ARY + 1
609 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 },
610
611 /* The SCLSCI8N field in a D form instruction. This is the same as the
612 SCLSCI8 field, only negated. */
613#define SCLSCI8N SCLSCI8 + 1
614 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n,
e43de63c 615 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
b9c361e0
JL		 616
617 /* The SD field of the SD4 form instruction. */
618#define SE_SD SCLSCI8N + 1
619 { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS },
620
621 /* The SD field of the SD4 form instruction, for halfword. */
622#define SE_SDH SE_SD + 1
623 { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS },
624
625 /* The SD field of the SD4 form instruction, for word. */
626#define SE_SDW SE_SDH + 1
627 { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS },
628
252b5132 629 /* The SH field in an X or M form instruction. */
b9c361e0 630#define SH SE_SDW + 1
252b5132 631#define SH_MASK (0x1f << 11)
717bbdf1
AM		 632 /* The other UIMM field in a EVX form instruction. */
633#define EVUIMM SH
a680de9a
PB		 634 /* The FC field in an atomic X form instruction. */
635#define FC SH
b84bf58a 636 { 0x1f, 11, NULL, NULL, 0 },
252b5132 637
5817ffd1
PB		 638 /* The SI field in a HTM X form instruction. */
639#define HTM_SI SH + 1
640 { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED },
641
252b5132 642 /* The SH field in an MD form instruction. This is split. */
5817ffd1 643#define SH6 HTM_SI + 1
252b5132 644#define SH6_MASK ((0x1f << 11) | (1 << 1))
b9c361e0 645 { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
252b5132 646
1f6c9eb0
ZW		 647 /* The SH field of the tlbwe instruction, which is optional. */
648#define SHO SH6 + 1
b84bf58a 649 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
1f6c9eb0 650
252b5132 651 /* The SI field in a D form instruction. */
1f6c9eb0 652#define SI SHO + 1
b84bf58a 653 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
252b5132
RH		 654
655 /* The SI field in a D form instruction when we accept a wide range
656 of positive values. */
657#define SISIGNOPT SI + 1
b84bf58a 658 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
252b5132 659
b9c361e0
JL		 660 /* The SI8 field in a D form instruction. */
661#define SI8 SISIGNOPT + 1
662 { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
663
252b5132
RH		 664 /* The SPR field in an XFX form instruction. This is flipped--the
665 lower 5 bits are stored in the upper 5 and vice- versa. */
b9c361e0 666#define SPR SI8 + 1
914749f6 667#define PMR SPR
aea77599 668#define TMR SPR
252b5132 669#define SPR_MASK (0x3ff << 11)
b84bf58a 670 { 0x3ff, 11, insert_spr, extract_spr, 0 },
252b5132
RH		 671
672 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
673#define SPRBAT SPR + 1
674#define SPRBAT_MASK (0x3 << 17)
b84bf58a 675 { 0x3, 17, NULL, NULL, 0 },
252b5132
RH		 676
677 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
678#define SPRG SPRBAT + 1
b84bf58a 679 { 0x1f, 16, insert_sprg, extract_sprg, 0 },
252b5132
RH		 680
681 /* The SR field in an X form instruction. */
682#define SR SPRG + 1
fb048c26
PB		 683 /* The 4-bit UIMM field in a VX form instruction. */
684#define UIMM4 SR
b84bf58a 685 { 0xf, 16, NULL, NULL, 0 },
252b5132 686
f5c120c5
MG		 687 /* The STRM field in an X AltiVec form instruction. */
688#define STRM SR + 1
19a6653c
AM		 689 /* The T field in a tlbilx form instruction. */
690#define T STRM
b84bf58a 691 { 0x3, 21, NULL, NULL, 0 },
f5c120c5 692
aea77599
AM		 693 /* The ESYNC field in an X (sync) form instruction. */
694#define ESYNC STRM + 1
7b934113 695 { 0xf, 16, insert_esync, NULL, PPC_OPERAND_OPTIONAL },
aea77599 696
252b5132 697 /* The SV field in a POWER SC form instruction. */
aea77599 698#define SV ESYNC + 1
b84bf58a 699 { 0x3fff, 2, NULL, NULL, 0 },
252b5132
RH		 700
701 /* The TBR field in an XFX form instruction. This is like the SPR
702 field, but it is optional. */
703#define TBR SV + 1
e43de63c
AM		 704 { 0x3ff, 11, insert_tbr, extract_tbr,
705 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
11a0cf2e
PB		 706 /* If the TBR operand is ommitted, use the value 268. */
707 { -1, 268, NULL, NULL, 0},
252b5132
RH		 708
709 /* The TO field in a D or X form instruction. */
11a0cf2e 710#define TO TBR + 2
19a6653c 711#define DUI TO
252b5132 712#define TO_MASK (0x1f << 21)
b84bf58a 713 { 0x1f, 21, NULL, NULL, 0 },
252b5132 714
252b5132 715 /* The UI field in a D form instruction. */
717bbdf1 716#define UI TO + 1
b84bf58a 717 { 0xffff, 0, NULL, NULL, 0 },
786e2c0f 718
a47622ac
AM		 719#define UISIGNOPT UI + 1
720 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT },
721
b9c361e0 722 /* The IMM field in an SE_IM5 instruction. */
a47622ac 723#define UI5 UISIGNOPT + 1
b9c361e0
JL		 724 { 0x1f, 4, NULL, NULL, 0 },
725
726 /* The OIMM field in an SE_OIM5 instruction. */
727#define OIMM5 UI5 + 1
728 { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 },
729
730 /* The UI7 field in an SE_LI instruction. */
731#define UI7 OIMM5 + 1
732 { 0x7f, 4, NULL, NULL, 0 },
733
112290ab 734 /* The VA field in a VA, VX or VXR form instruction. */
b9c361e0 735#define VA UI7 + 1
b84bf58a 736 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 737
112290ab 738 /* The VB field in a VA, VX or VXR form instruction. */
786e2c0f 739#define VB VA + 1
b84bf58a 740 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 741
112290ab 742 /* The VC field in a VA form instruction. */
786e2c0f 743#define VC VB + 1
b84bf58a 744 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 745
112290ab 746 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
786e2c0f
C		 747#define VD VC + 1
748#define VS VD
b84bf58a 749 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 750
8dbcd839 751 /* The SIMM field in a VX form instruction, and TE in Z form. */
786e2c0f 752#define SIMM VD + 1
8dbcd839 753#define TE SIMM
b84bf58a 754 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
786e2c0f 755
8dbcd839 756 /* The UIMM field in a VX form instruction. */
786e2c0f 757#define UIMM SIMM + 1
aea77599 758#define DCTL UIMM
b84bf58a 759 { 0x1f, 16, NULL, NULL, 0 },
786e2c0f 760
fb048c26
PB		 761 /* The 3-bit UIMM field in a VX form instruction. */
762#define UIMM3 UIMM + 1
763 { 0x7, 16, NULL, NULL, 0 },
764
a680de9a
PB		 765 /* The 6-bit UIM field in a X form instruction. */
766#define UIM6 UIMM3 + 1
767 { 0x3f, 16, NULL, NULL, 0 },
768
c0637f3a 769 /* The SIX field in a VX form instruction. */
a680de9a 770#define SIX UIM6 + 1
c0637f3a
PB		 771 { 0xf, 11, NULL, NULL, 0 },
772
773 /* The PS field in a VX form instruction. */
774#define PS SIX + 1
775 { 0x1, 9, NULL, NULL, 0 },
776
112290ab 777 /* The SHB field in a VA form instruction. */
c0637f3a 778#define SHB PS + 1
b84bf58a 779 { 0xf, 6, NULL, NULL, 0 },
ff3a6ee3 780
112290ab 781 /* The other UIMM field in a half word EVX form instruction. */
717bbdf1 782#define EVUIMM_2 SHB + 1
b84bf58a 783 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
23976049 784
112290ab 785 /* The other UIMM field in a word EVX form instruction. */
23976049 786#define EVUIMM_4 EVUIMM_2 + 1
b84bf58a 787 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
23976049 788
112290ab 789 /* The other UIMM field in a double EVX form instruction. */
23976049 790#define EVUIMM_8 EVUIMM_4 + 1
b84bf58a 791 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
23976049 792
6fd3a02d 793 /* The WS or DRM field in an X form instruction. */
23976049 794#define WS EVUIMM_8 + 1
6fd3a02d 795#define DRM WS
b84bf58a 796 { 0x7, 11, NULL, NULL, 0 },
ff3a6ee3 797
c3d65c1c
BE		 798 /* PowerPC paired singles extensions. */
799 /* W bit in the pair singles instructions for x type instructions. */
800#define PSWM WS + 1
b9c361e0
JL		 801 /* The BO16 field in a BD8 form instruction. */
802#define BO16 PSWM
c3d65c1c
BE		 803 { 0x1, 10, 0, 0, 0 },
804
805 /* IDX bits for quantization in the pair singles instructions. */
806#define PSQ PSWM + 1
807 { 0x7, 12, 0, 0, 0 },
808
809 /* IDX bits for quantization in the pair singles x-type instructions. */
810#define PSQM PSQ + 1
811 { 0x7, 7, 0, 0, 0 },
812
813 /* Smaller D field for quantization in the pair singles instructions. */
814#define PSD PSQM + 1
815 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
816
a680de9a 817 /* The L field in an mtmsrd or A form instruction or R or W in an X form. */
c3d65c1c 818#define A_L PSD + 1
ea192fa3 819#define W A_L
a680de9a 820#define X_R A_L
b84bf58a 821 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
5ae2e65e 822
19dfcc89 823 /* The RMC or CY field in a Z23 form instruction. */
99a2c561 824#define RMC A_L + 1
19dfcc89 825#define CY RMC
b84bf58a 826 { 0x3, 9, NULL, NULL, 0 },
702f0fb4
PB		 827
828#define R RMC + 1
b84bf58a 829 { 0x1, 16, NULL, NULL, 0 },
702f0fb4 830
a680de9a
PB		 831#define RIC R + 1
832 { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL },
833
834#define PRS RIC + 1
835 { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
836
837#define SP PRS + 1
b84bf58a 838 { 0x3, 19, NULL, NULL, 0 },
702f0fb4
PB		 839
840#define S SP + 1
b84bf58a 841 { 0x1, 20, NULL, NULL, 0 },
702f0fb4 842
c0637f3a
PB		 843 /* The S field in a XL form instruction. */
844#define SXL S + 1
11a0cf2e
PB		 845 { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
846 /* If the SXL operand is ommitted, use the value 1. */
847 { -1, 1, NULL, NULL, 0},
c0637f3a 848
702f0fb4 849 /* SH field starting at bit position 16. */
11a0cf2e 850#define SH16 SXL + 2
0bbdef92
AM		 851 /* The DCM and DGM fields in a Z form instruction. */
852#define DCM SH16
853#define DGM DCM
b84bf58a 854 { 0x3f, 10, NULL, NULL, 0 },
702f0fb4 855
702f0fb4 856 /* The EH field in larx instruction. */
717bbdf1 857#define EH SH16 + 1
b84bf58a 858 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
ea192fa3
PB		 859
860 /* The L field in an mtfsf or XFL form instruction. */
5817ffd1 861 /* The A field in a HTM X form instruction. */
ea192fa3 862#define XFL_L EH + 1
5817ffd1 863#define HTM_A XFL_L
ea192fa3 864 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
081ba1b3
AM		 865
866 /* Xilinx APU related masks and macros */
867#define FCRT XFL_L + 1
868#define FCRT_MASK (0x1f << 21)
869 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
870
43e65147 871 /* Xilinx FSL related masks and macros */
081ba1b3
AM		 872#define FSL FCRT + 1
873#define FSL_MASK (0x1f << 11)
43e65147 874 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
081ba1b3 875
43e65147 876 /* Xilinx UDI related masks and macros */
081ba1b3
AM		 877#define URT FSL + 1
878 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
879
880#define URA URT + 1
881 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
882
883#define URB URA + 1
884 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
885
886#define URC URB + 1
887 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
888
b9c361e0
JL		 889 /* The VLESIMM field in a D form instruction. */
890#define VLESIMM URC + 1
891 { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
e43de63c 892 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
b9c361e0
JL		 893
894 /* The VLENSIMM field in a D form instruction. */
895#define VLENSIMM VLESIMM + 1
896 { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi,
e43de63c 897 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
b9c361e0
JL		 898
899 /* The VLEUIMM field in a D form instruction. */
900#define VLEUIMM VLENSIMM + 1
901 { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 },
902
903 /* The VLEUIMML field in a D form instruction. */
904#define VLEUIMML VLEUIMM + 1
905 { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 },
906
9b4e5766 907 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
b9c361e0 908#define XS6 VLEUIMML + 1
9b4e5766 909#define XT6 XS6
b9c361e0 910 { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
9b4e5766 911
a680de9a
PB		 912 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
913#define XSQ6 XT6 + 1
914#define XTQ6 XSQ6
915 { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR },
916
9b4e5766 917 /* The XA field in an XX3 form instruction. This is split. */
a680de9a 918#define XA6 XTQ6 + 1
b9c361e0 919 { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
9b4e5766 920
066be9f7 921 /* The XB field in an XX2 or XX3 form instruction. This is split. */
9b4e5766 922#define XB6 XA6 + 1
b9c361e0 923 { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
9b4e5766
PB		 924
925 /* The XB field in an XX3 form instruction when it must be the same as
926 the XA field in the instruction. This is used in extended mnemonics
927 like xvmovdp. This is split. */
928#define XB6S XB6 + 1
b9c361e0 929 { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
9b4e5766 930
066be9f7
PB		 931 /* The XC field in an XX4 form instruction. This is split. */
932#define XC6 XB6S + 1
b9c361e0 933 { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
066be9f7
PB		 934
935 /* The DM or SHW field in an XX3 form instruction. */
936#define DM XC6 + 1
937#define SHW DM
9b4e5766 938 { 0x3, 8, NULL, NULL, 0 },
066be9f7
PB		 939
940 /* The DM field in an extended mnemonic XX3 form instruction. */
941#define DMEX DM + 1
942 { 0x3, 8, insert_dm, extract_dm, 0 },
943
944 /* The UIM field in an XX2 form instruction. */
945#define UIM DMEX + 1
fb048c26
PB		 946 /* The 2-bit UIMM field in a VX form instruction. */
947#define UIMM2 UIM
a680de9a
PB		 948 /* The 2-bit L field in a darn instruction. */
949#define LRAND UIM
066be9f7 950 { 0x3, 16, NULL, NULL, 0 },
e0d602ec
BE		 951
952#define ERAT_T UIM + 1
953 { 0x7, 21, NULL, NULL, 0 },
4bc0608a
PB		 954
955#define IH ERAT_T + 1
956 { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
a680de9a
PB		 957
958 /* The 8-bit IMM8 field in a XX1 form instruction. */
959#define IMM8 IH + 1
1178da44 960 { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT },
252b5132
RH		 961};
962
b84bf58a
AM		 963const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
964 / sizeof (powerpc_operands[0]));
965
252b5132
RH		 966/* The functions used to insert and extract complicated operands. */
967
b9c361e0
JL		 968/* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
969
970static unsigned long
971insert_arx (unsigned long insn,
972 long value,
973 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
974 const char **errmsg ATTRIBUTE_UNUSED)
975{
976 if (value >= 8 && value < 24)
977 return insn | ((value - 8) & 0xf);
978 else
979 {
980 *errmsg = _("invalid register");
981 return 0;
982 }
983}
984
985static long
986extract_arx (unsigned long insn,
987 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
988 int *invalid ATTRIBUTE_UNUSED)
43e65147 989{
b9c361e0
JL		 990 return (insn & 0xf) + 8;
991}
992
993static unsigned long
994insert_ary (unsigned long insn,
995 long value,
996 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
997 const char **errmsg ATTRIBUTE_UNUSED)
998{
999 if (value >= 8 && value < 24)
1000 return insn | (((value - 8) & 0xf) << 4);
1001 else
1002 {
1003 *errmsg = _("invalid register");
1004 return 0;
1005 }
1006}
1007
1008static long
1009extract_ary (unsigned long insn,
1010 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1011 int *invalid ATTRIBUTE_UNUSED)
1012{
1013 return ((insn >> 4) & 0xf) + 8;
1014}
1015
1016static unsigned long
1017insert_rx (unsigned long insn,
1018 long value,
1019 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1020 const char **errmsg)
1021{
1022 if (value >= 0 && value < 8)
1023 return insn | value;
1024 else if (value >= 24 && value <= 31)
1025 return insn | (value - 16);
1026 else
1027 {
1028 *errmsg = _("invalid register");
1029 return 0;
1030 }
1031}
1032
1033static long
1034extract_rx (unsigned long insn,
1035 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1036 int *invalid ATTRIBUTE_UNUSED)
1037{
1038 int value = insn & 0xf;
1039 if (value >= 0 && value < 8)
1040 return value;
1041 else
1042 return value + 16;
1043}
1044
1045static unsigned long
1046insert_ry (unsigned long insn,
1047 long value,
1048 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1049 const char **errmsg)
1050{
1051 if (value >= 0 && value < 8)
1052 return insn | (value << 4);
1053 else if (value >= 24 && value <= 31)
1054 return insn | ((value - 16) << 4);
1055 else
1056 {
1057 *errmsg = _("invalid register");
1058 return 0;
1059 }
1060}
1061
1062static long
1063extract_ry (unsigned long insn,
1064 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1065 int *invalid ATTRIBUTE_UNUSED)
1066{
1067 int value = (insn >> 4) & 0xf;
1068 if (value >= 0 && value < 8)
1069 return value;
1070 else
1071 return value + 16;
1072}
1073
252b5132
RH		 1074/* The BA field in an XL form instruction when it must be the same as
1075 the BT field in the same instruction. This operand is marked FAKE.
1076 The insertion function just copies the BT field into the BA field,
1077 and the extraction function just checks that the fields are the
1078 same. */
1079
252b5132 1080static unsigned long
2fbfdc41
AM		 1081insert_bat (unsigned long insn,
1082 long value ATTRIBUTE_UNUSED,
fa452fa6 1083 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1084 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1085{
1086 return insn | (((insn >> 21) & 0x1f) << 16);
1087}
1088
1089static long
2fbfdc41 1090extract_bat (unsigned long insn,
fa452fa6 1091 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1092 int *invalid)
252b5132 1093{
8427c424 1094 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
252b5132
RH		 1095 *invalid = 1;
1096 return 0;
1097}
1098
1099/* The BB field in an XL form instruction when it must be the same as
1100 the BA field in the same instruction. This operand is marked FAKE.
1101 The insertion function just copies the BA field into the BB field,
1102 and the extraction function just checks that the fields are the
1103 same. */
1104
252b5132 1105static unsigned long
2fbfdc41
AM		 1106insert_bba (unsigned long insn,
1107 long value ATTRIBUTE_UNUSED,
fa452fa6 1108 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1109 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1110{
1111 return insn | (((insn >> 16) & 0x1f) << 11);
1112}
1113
1114static long
2fbfdc41 1115extract_bba (unsigned long insn,
fa452fa6 1116 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1117 int *invalid)
252b5132 1118{
8427c424 1119 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 1120 *invalid = 1;
1121 return 0;
1122}
1123
252b5132
RH		 1124/* The BD field in a B form instruction when the - modifier is used.
1125 This modifier means that the branch is not expected to be taken.
94efba12
AM		 1126 For chips built to versions of the architecture prior to version 2
1127 (ie. not Power4 compatible), we set the y bit of the BO field to 1
1128 if the offset is negative. When extracting, we require that the y
1129 bit be 1 and that the offset be positive, since if the y bit is 0
1130 we just want to print the normal form of the instruction.
1131 Power4 compatible targets use two bits, "a", and "t", instead of
1132 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
1133 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
1134 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
ba4e851b
AM		 1135 for branch on CTR. We only handle the taken/not-taken hint here.
1136 Note that we don't relax the conditions tested here when
1137 disassembling with -Many because insns using extract_bdm and
1138 extract_bdp always occur in pairs. One or the other will always
1139 be valid. */
252b5132 1140
8ebac3aa
AM		 1141#define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1142
252b5132 1143static unsigned long
2fbfdc41
AM		 1144insert_bdm (unsigned long insn,
1145 long value,
fa452fa6 1146 ppc_cpu_t dialect,
2fbfdc41 1147 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1148{
8ebac3aa 1149 if ((dialect & ISA_V2) == 0)
802a735e
AM		 1150 {
1151 if ((value & 0x8000) != 0)
1152 insn |= 1 << 21;
1153 }
1154 else
1155 {
1156 if ((insn & (0x14 << 21)) == (0x04 << 21))
1157 insn |= 0x02 << 21;
1158 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1159 insn |= 0x08 << 21;
1160 }
252b5132
RH		 1161 return insn | (value & 0xfffc);
1162}
1163
1164static long
2fbfdc41 1165extract_bdm (unsigned long insn,
fa452fa6 1166 ppc_cpu_t dialect,
2fbfdc41 1167 int *invalid)
252b5132 1168{
8ebac3aa 1169 if ((dialect & ISA_V2) == 0)
802a735e 1170 {
8427c424
AM		 1171 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
1172 *invalid = 1;
802a735e 1173 }
8427c424
AM		 1174 else
1175 {
1176 if ((insn & (0x17 << 21)) != (0x06 << 21)
1177 && (insn & (0x1d << 21)) != (0x18 << 21))
1178 *invalid = 1;
1179 }
1180
802a735e 1181 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 1182}
1183
1184/* The BD field in a B form instruction when the + modifier is used.
1185 This is like BDM, above, except that the branch is expected to be
1186 taken. */
1187
252b5132 1188static unsigned long
2fbfdc41
AM		 1189insert_bdp (unsigned long insn,
1190 long value,
fa452fa6 1191 ppc_cpu_t dialect,
2fbfdc41 1192 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1193{
8ebac3aa 1194 if ((dialect & ISA_V2) == 0)
802a735e
AM		 1195 {
1196 if ((value & 0x8000) == 0)
1197 insn |= 1 << 21;
1198 }
1199 else
1200 {
1201 if ((insn & (0x14 << 21)) == (0x04 << 21))
1202 insn |= 0x03 << 21;
1203 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1204 insn |= 0x09 << 21;
1205 }
252b5132
RH		 1206 return insn | (value & 0xfffc);
1207}
1208
1209static long
2fbfdc41 1210extract_bdp (unsigned long insn,
fa452fa6 1211 ppc_cpu_t dialect,
2fbfdc41 1212 int *invalid)
252b5132 1213{
8ebac3aa 1214 if ((dialect & ISA_V2) == 0)
802a735e 1215 {
8427c424
AM		 1216 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
1217 *invalid = 1;
1218 }
1219 else
1220 {
1221 if ((insn & (0x17 << 21)) != (0x07 << 21)
1222 && (insn & (0x1d << 21)) != (0x19 << 21))
1223 *invalid = 1;
802a735e 1224 }
8427c424 1225
802a735e 1226 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 1227}
1228
8ebac3aa
AM		 1229static inline int
1230valid_bo_pre_v2 (long value)
252b5132 1231{
8ebac3aa
AM		 1232 /* Certain encodings have bits that are required to be zero.
1233 These are (z must be zero, y may be anything):
43e65147
L		 1234 0000y
1235 0001y
8ebac3aa 1236 001zy
43e65147
L		 1237 0100y
1238 0101y
8ebac3aa
AM		 1239 011zy
1240 1z00y
1241 1z01y
1242 1z1zz
1243 */
1244 if ((value & 0x14) == 0)
1245 return 1;
1246 else if ((value & 0x14) == 0x4)
1247 return (value & 0x2) == 0;
1248 else if ((value & 0x14) == 0x10)
1249 return (value & 0x8) == 0;
1250 else
1251 return value == 0x14;
1252}
ba4e851b 1253
8ebac3aa
AM		 1254static inline int
1255valid_bo_post_v2 (long value)
1256{
ba4e851b
AM		 1257 /* Certain encodings have bits that are required to be zero.
1258 These are (z must be zero, a & t may be anything):
1259 0000z
1260 0001z
8ebac3aa 1261 001at
ba4e851b
AM		 1262 0100z
1263 0101z
ba4e851b
AM		 1264 011at
1265 1a00t
1266 1a01t
1267 1z1zz
1268 */
1269 if ((value & 0x14) == 0)
1270 return (value & 0x1) == 0;
1271 else if ((value & 0x14) == 0x14)
1272 return value == 0x14;
802a735e 1273 else
ba4e851b 1274 return 1;
252b5132
RH		 1275}
1276
8ebac3aa
AM		 1277/* Check for legal values of a BO field. */
1278
1279static int
1280valid_bo (long value, ppc_cpu_t dialect, int extract)
1281{
1282 int valid_y = valid_bo_pre_v2 (value);
1283 int valid_at = valid_bo_post_v2 (value);
1284
1285 /* When disassembling with -Many, accept either encoding on the
1286 second pass through opcodes. */
1287 if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY)
1288 return valid_y || valid_at;
1289 if ((dialect & ISA_V2) == 0)
1290 return valid_y;
1291 else
1292 return valid_at;
1293}
1294
252b5132
RH		 1295/* The BO field in a B form instruction. Warn about attempts to set
1296 the field to an illegal value. */
1297
1298static unsigned long
2fbfdc41
AM		 1299insert_bo (unsigned long insn,
1300 long value,
fa452fa6 1301 ppc_cpu_t dialect,
2fbfdc41 1302 const char **errmsg)
252b5132 1303{
ba4e851b 1304 if (!valid_bo (value, dialect, 0))
252b5132 1305 *errmsg = _("invalid conditional option");
989993d8
JB		 1306 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1307 *errmsg = _("invalid counter access");
252b5132
RH		 1308 return insn | ((value & 0x1f) << 21);
1309}
1310
1311static long
2fbfdc41 1312extract_bo (unsigned long insn,
fa452fa6 1313 ppc_cpu_t dialect,
2fbfdc41 1314 int *invalid)
252b5132
RH		 1315{
1316 long value;
1317
1318 value = (insn >> 21) & 0x1f;
ba4e851b 1319 if (!valid_bo (value, dialect, 1))
252b5132
RH		 1320 *invalid = 1;
1321 return value;
1322}
1323
1324/* The BO field in a B form instruction when the + or - modifier is
1325 used. This is like the BO field, but it must be even. When
1326 extracting it, we force it to be even. */
1327
1328static unsigned long
2fbfdc41
AM		 1329insert_boe (unsigned long insn,
1330 long value,
fa452fa6 1331 ppc_cpu_t dialect,
2fbfdc41 1332 const char **errmsg)
252b5132 1333{
ba4e851b 1334 if (!valid_bo (value, dialect, 0))
8427c424 1335 *errmsg = _("invalid conditional option");
989993d8
JB		 1336 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1337 *errmsg = _("invalid counter access");
8427c424
AM		 1338 else if ((value & 1) != 0)
1339 *errmsg = _("attempt to set y bit when using + or - modifier");
1340
252b5132
RH		 1341 return insn | ((value & 0x1f) << 21);
1342}
1343
1344static long
2fbfdc41 1345extract_boe (unsigned long insn,
fa452fa6 1346 ppc_cpu_t dialect,
2fbfdc41 1347 int *invalid)
252b5132
RH		 1348{
1349 long value;
1350
1351 value = (insn >> 21) & 0x1f;
ba4e851b 1352 if (!valid_bo (value, dialect, 1))
252b5132
RH		 1353 *invalid = 1;
1354 return value & 0x1e;
1355}
1356
a680de9a
PB		 1357/* The DCMX field in a X form instruction when the field is split
1358 into separate DC, DM and DX fields. */
1359
1360static unsigned long
1361insert_dcmxs (unsigned long insn,
1362 long value,
1363 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1364 const char **errmsg ATTRIBUTE_UNUSED)
1365{
1366 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3) | (value & 0x40);
1367}
1368
1369static long
1370extract_dcmxs (unsigned long insn,
1371 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1372 int *invalid ATTRIBUTE_UNUSED)
1373{
1374 return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1375}
1376
1377/* The D field in a DX form instruction when the field is split
1378 into separate D0, D1 and D2 fields. */
1379
1380static unsigned long
1381insert_dxd (unsigned long insn,
1382 long value,
1383 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1384 const char **errmsg ATTRIBUTE_UNUSED)
1385{
1386 return insn | (value & 0xffc1) | ((value & 0x3e) << 15);
1387}
1388
1389static long
1390extract_dxd (unsigned long insn,
1391 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1392 int *invalid ATTRIBUTE_UNUSED)
1393{
1394 unsigned long dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e);
1395 return (dxd ^ 0x8000) - 0x8000;
1396}
1397
1398static unsigned long
1399insert_dxdn (unsigned long insn,
1400 long value,
1401 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1402 const char **errmsg ATTRIBUTE_UNUSED)
1403{
1404 return insert_dxd (insn, -value, dialect, errmsg);
1405}
1406
1407static long
1408extract_dxdn (unsigned long insn,
1409 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1410 int *invalid ATTRIBUTE_UNUSED)
1411{
1412 return -extract_dxd (insn, dialect, invalid);
1413}
1414
2fbfdc41
AM		 1415/* FXM mask in mfcr and mtcrf instructions. */
1416
1417static unsigned long
1418insert_fxm (unsigned long insn,
1419 long value,
fa452fa6 1420 ppc_cpu_t dialect,
2fbfdc41 1421 const char **errmsg)
c168870a 1422{
98e69875
AM		 1423 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1424 one bit of the mask field is set. */
1425 if ((insn & (1 << 20)) != 0)
1426 {
1427 if (value == 0 || (value & -value) != value)
1428 {
1429 *errmsg = _("invalid mask field");
1430 value = 0;
1431 }
1432 }
1433
c168870a 1434 /* If only one bit of the FXM field is set, we can use the new form
661bd698 1435 of the instruction, which is faster. Unlike the Power4 branch hint
a30e9cc4
AM		 1436 encoding, this is not backward compatible. Do not generate the
1437 new form unless -mpower4 has been given, or -many and the two
1438 operand form of mfcr was used. */
11a0cf2e
PB		 1439 else if (value > 0
1440 && (value & -value) == value
a30e9cc4
AM		 1441 && ((dialect & PPC_OPCODE_POWER4) != 0
1442 || ((dialect & PPC_OPCODE_ANY) != 0
1443 && (insn & (0x3ff << 1)) == 19 << 1)))
c168870a
AM		 1444 insn |= 1 << 20;
1445
1446 /* Any other value on mfcr is an error. */
1447 else if ((insn & (0x3ff << 1)) == 19 << 1)
1448 {
11a0cf2e
PB		 1449 /* A value of -1 means we used the one operand form of
1450 mfcr which is valid. */
1451 if (value != -1)
b817670b 1452 *errmsg = _("invalid mfcr mask");
c168870a
AM		 1453 value = 0;
1454 }
1455
1456 return insn | ((value & 0xff) << 12);
1457}
1458
2fbfdc41
AM		 1459static long
1460extract_fxm (unsigned long insn,
fa452fa6 1461 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1462 int *invalid)
c168870a
AM		 1463{
1464 long mask = (insn >> 12) & 0xff;
1465
1466 /* Is this a Power4 insn? */
1467 if ((insn & (1 << 20)) != 0)
1468 {
98e69875
AM		 1469 /* Exactly one bit of MASK should be set. */
1470 if (mask == 0 || (mask & -mask) != mask)
8427c424 1471 *invalid = 1;
c168870a
AM		 1472 }
1473
1474 /* Check that non-power4 form of mfcr has a zero MASK. */
1475 else if ((insn & (0x3ff << 1)) == 19 << 1)
1476 {
8427c424 1477 if (mask != 0)
c168870a 1478 *invalid = 1;
11a0cf2e
PB		 1479 else
1480 mask = -1;
c168870a
AM		 1481 }
1482
1483 return mask;
1484}
1485
a680de9a
PB		 1486/* The L field in an X form instruction which must have the value zero. */
1487
1488static unsigned long
1489insert_l0 (unsigned long insn,
1490 long value,
1491 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1492 const char **errmsg)
1493{
1494 if (value != 0)
1495 *errmsg = _("invalid operand constant");
1496 return insn & ~(0x1 << 21);
1497}
1498
1499static long
1500extract_l0 (unsigned long insn,
1501 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1502 int *invalid)
1503{
1504 long value;
1505
1506 value = (insn >> 21) & 0x1;
1507 if (value != 0)
1508 *invalid = 1;
1509 return value;
1510}
1511
1512/* The L field in an X form instruction which must have the value one. */
1513
1514static unsigned long
1515insert_l1 (unsigned long insn,
1516 long value,
1517 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1518 const char **errmsg)
1519{
1520 if (value != 1)
1521 *errmsg = _("invalid operand constant");
1522 return insn | (0x1 << 21);
1523}
1524
1525static long
1526extract_l1 (unsigned long insn,
1527 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1528 int *invalid)
1529{
1530 long value;
1531
1532 value = (insn >> 21) & 0x1;
1533 if (value != 1)
1534 *invalid = 1;
1535 return value;
1536}
1537
b9c361e0
JL		 1538static unsigned long
1539insert_li20 (unsigned long insn,
1540 long value,
1541 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1542 const char **errmsg ATTRIBUTE_UNUSED)
1543{
1544 return insn | ((value & 0xf0000) >> 5) | ((value & 0x0f800) << 5) | (value & 0x7ff);
1545}
1546
1547static long
1548extract_li20 (unsigned long insn,
1549 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1550 int *invalid ATTRIBUTE_UNUSED)
1551{
1552 long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
1553
1554 return ext
1555 | (((insn >> 11) & 0xf) << 16)
1556 | (((insn >> 17) & 0xf) << 12)
1557 | (((insn >> 16) & 0x1) << 11)
1558 | (insn & 0x7ff);
1559}
1560
7b934113
PB		 1561/* The 2-bit L field in a SYNC or WC field in a WAIT instruction.
1562 For SYNC, some L values are reserved:
1563 * Value 3 is reserved on newer server cpus.
1564 * Values 2 and 3 are reserved on all other cpus. */
aea77599
AM		 1565
1566static unsigned long
1567insert_ls (unsigned long insn,
1568 long value,
7b934113
PB		 1569 ppc_cpu_t dialect,
1570 const char **errmsg)
1571{
1572 /* For SYNC, some L values are illegal. */
1573 if (((insn >> 1) & 0x3ff) == 598)
1574 {
1575 long max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1;
1576 if (value > max_lvalue)
1577 {
1578 *errmsg = _("illegal L operand value");
1579 return insn;
1580 }
1581 }
1582
1583 return insn | ((value & 0x3) << 21);
1584}
1585
1586/* The 4-bit E field in a sync instruction that accepts 2 operands.
1587 If ESYNC is non-zero, then the L field must be either 0 or 1 and
1588 the complement of ESYNC-bit2. */
1589
1590static unsigned long
1591insert_esync (unsigned long insn,
1592 long value,
a680de9a 1593 ppc_cpu_t dialect,
7b934113 1594 const char **errmsg)
aea77599 1595{
a680de9a 1596 unsigned long ls = (insn >> 21) & 0x03;
aea77599 1597
aea77599
AM		 1598 if (value == 0)
1599 {
a680de9a
PB		 1600 if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1)
1601 || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2))
1602 *errmsg = _("illegal L operand value");
aea77599
AM		 1603 return insn;
1604 }
7b934113
PB		 1605
1606 if ((ls & ~0x1)
1607 || (((value >> 1) & 0x1) ^ ls) == 0)
1608 *errmsg = _("incompatible L operand value");
1609
1610 return insn | ((value & 0xf) << 16);
aea77599
AM		 1611}
1612
252b5132
RH		 1613/* The MB and ME fields in an M form instruction expressed as a single
1614 operand which is itself a bitmask. The extraction function always
1615 marks it as invalid, since we never want to recognize an
1616 instruction which uses a field of this type. */
1617
1618static unsigned long
2fbfdc41
AM		 1619insert_mbe (unsigned long insn,
1620 long value,
fa452fa6 1621 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1622 const char **errmsg)
252b5132
RH		 1623{
1624 unsigned long uval, mask;
1625 int mb, me, mx, count, last;
1626
1627 uval = value;
1628
1629 if (uval == 0)
1630 {
8427c424 1631 *errmsg = _("illegal bitmask");
252b5132
RH		 1632 return insn;
1633 }
1634
1635 mb = 0;
1636 me = 32;
1637 if ((uval & 1) != 0)
1638 last = 1;
1639 else
1640 last = 0;
1641 count = 0;
1642
1643 /* mb: location of last 0->1 transition */
1644 /* me: location of last 1->0 transition */
1645 /* count: # transitions */
1646
0deb7ac5 1647 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
252b5132
RH		 1648 {
1649 if ((uval & mask) && !last)
1650 {
1651 ++count;
1652 mb = mx;
1653 last = 1;
1654 }
1655 else if (!(uval & mask) && last)
1656 {
1657 ++count;
1658 me = mx;
1659 last = 0;
1660 }
1661 }
1662 if (me == 0)
1663 me = 32;
1664
1665 if (count != 2 && (count != 0 || ! last))
8427c424 1666 *errmsg = _("illegal bitmask");
252b5132
RH		 1667
1668 return insn | (mb << 6) | ((me - 1) << 1);
1669}
1670
1671static long
2fbfdc41 1672extract_mbe (unsigned long insn,
fa452fa6 1673 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1674 int *invalid)
252b5132
RH		 1675{
1676 long ret;
1677 int mb, me;
1678 int i;
1679
8427c424 1680 *invalid = 1;
252b5132
RH		 1681
1682 mb = (insn >> 6) & 0x1f;
1683 me = (insn >> 1) & 0x1f;
1684 if (mb < me + 1)
1685 {
1686 ret = 0;
1687 for (i = mb; i <= me; i++)
0deb7ac5 1688 ret |= 1L << (31 - i);
252b5132
RH		 1689 }
1690 else if (mb == me + 1)
8427c424 1691 ret = ~0;
252b5132
RH		 1692 else /* (mb > me + 1) */
1693 {
2fbfdc41 1694 ret = ~0;
252b5132 1695 for (i = me + 1; i < mb; i++)
0deb7ac5 1696 ret &= ~(1L << (31 - i));
252b5132
RH		 1697 }
1698 return ret;
1699}
1700
1701/* The MB or ME field in an MD or MDS form instruction. The high bit
1702 is wrapped to the low end. */
1703
252b5132 1704static unsigned long
2fbfdc41
AM		 1705insert_mb6 (unsigned long insn,
1706 long value,
fa452fa6 1707 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1708 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1709{
1710 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1711}
1712
252b5132 1713static long
2fbfdc41 1714extract_mb6 (unsigned long insn,
fa452fa6 1715 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1716 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1717{
1718 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1719}
1720
1721/* The NB field in an X form instruction. The value 32 is stored as
1722 0. */
1723
252b5132 1724static long
2fbfdc41 1725extract_nb (unsigned long insn,
fa452fa6 1726 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1727 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1728{
1729 long ret;
1730
1731 ret = (insn >> 11) & 0x1f;
1732 if (ret == 0)
1733 ret = 32;
1734 return ret;
1735}
1736
989993d8
JB		 1737/* The NB field in an lswi instruction, which has special value
1738 restrictions. The value 32 is stored as 0. */
1739
1740static unsigned long
1741insert_nbi (unsigned long insn,
1742 long value,
1743 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1744 const char **errmsg ATTRIBUTE_UNUSED)
1745{
1746 long rtvalue = (insn & RT_MASK) >> 21;
1747 long ravalue = (insn & RA_MASK) >> 16;
1748
1749 if (value == 0)
1750 value = 32;
1751 if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32
1752 : ravalue))
1753 *errmsg = _("address register in load range");
1754 return insn | ((value & 0x1f) << 11);
1755}
1756
252b5132
RH		 1757/* The NSI field in a D form instruction. This is the same as the SI
1758 field, only negated. The extraction function always marks it as
1759 invalid, since we never want to recognize an instruction which uses
1760 a field of this type. */
1761
252b5132 1762static unsigned long
2fbfdc41
AM		 1763insert_nsi (unsigned long insn,
1764 long value,
fa452fa6 1765 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1766 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1767{
2fbfdc41 1768 return insn | (-value & 0xffff);
252b5132
RH		 1769}
1770
1771static long
2fbfdc41 1772extract_nsi (unsigned long insn,
fa452fa6 1773 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1774 int *invalid)
252b5132 1775{
8427c424 1776 *invalid = 1;
2fbfdc41 1777 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
252b5132
RH		 1778}
1779
1780/* The RA field in a D or X form instruction which is an updating
1781 load, which means that the RA field may not be zero and may not
1782 equal the RT field. */
1783
1784static unsigned long
2fbfdc41
AM		 1785insert_ral (unsigned long insn,
1786 long value,
fa452fa6 1787 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1788 const char **errmsg)
252b5132
RH		 1789{
1790 if (value == 0
1791 || (unsigned long) value == ((insn >> 21) & 0x1f))
1792 *errmsg = "invalid register operand when updating";
1793 return insn | ((value & 0x1f) << 16);
1794}
1795
1796/* The RA field in an lmw instruction, which has special value
1797 restrictions. */
1798
1799static unsigned long
2fbfdc41
AM		 1800insert_ram (unsigned long insn,
1801 long value,
fa452fa6 1802 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1803 const char **errmsg)
252b5132
RH		 1804{
1805 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1806 *errmsg = _("index register in load range");
1807 return insn | ((value & 0x1f) << 16);
1808}
1809
989993d8 1810/* The RA field in the DQ form lq or an lswx instruction, which have special
8427c424 1811 value restrictions. */
adadcc0c 1812
adadcc0c 1813static unsigned long
2fbfdc41
AM		 1814insert_raq (unsigned long insn,
1815 long value,
fa452fa6 1816 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1817 const char **errmsg)
adadcc0c
AM		 1818{
1819 long rtvalue = (insn & RT_MASK) >> 21;
1820
8427c424 1821 if (value == rtvalue)
adadcc0c
AM		 1822 *errmsg = _("source and target register operands must be different");
1823 return insn | ((value & 0x1f) << 16);
1824}
1825
252b5132
RH		 1826/* The RA field in a D or X form instruction which is an updating
1827 store or an updating floating point load, which means that the RA
1828 field may not be zero. */
1829
1830static unsigned long
2fbfdc41
AM		 1831insert_ras (unsigned long insn,
1832 long value,
fa452fa6 1833 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1834 const char **errmsg)
252b5132
RH		 1835{
1836 if (value == 0)
1837 *errmsg = _("invalid register operand when updating");
1838 return insn | ((value & 0x1f) << 16);
1839}
1840
1841/* The RB field in an X form instruction when it must be the same as
1842 the RS field in the instruction. This is used for extended
1843 mnemonics like mr. This operand is marked FAKE. The insertion
1844 function just copies the BT field into the BA field, and the
1845 extraction function just checks that the fields are the same. */
1846
252b5132 1847static unsigned long
2fbfdc41
AM		 1848insert_rbs (unsigned long insn,
1849 long value ATTRIBUTE_UNUSED,
fa452fa6 1850 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1851 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1852{
1853 return insn | (((insn >> 21) & 0x1f) << 11);
1854}
1855
1856static long
2fbfdc41 1857extract_rbs (unsigned long insn,
fa452fa6 1858 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1859 int *invalid)
252b5132 1860{
8427c424 1861 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 1862 *invalid = 1;
1863 return 0;
1864}
1865
989993d8
JB		 1866/* The RB field in an lswx instruction, which has special value
1867 restrictions. */
1868
1869static unsigned long
1870insert_rbx (unsigned long insn,
1871 long value,
1872 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1873 const char **errmsg)
1874{
1875 long rtvalue = (insn & RT_MASK) >> 21;
1876
1877 if (value == rtvalue)
1878 *errmsg = _("source and target register operands must be different");
1879 return insn | ((value & 0x1f) << 11);
1880}
1881
b9c361e0
JL		 1882/* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1883static unsigned long
1884insert_sci8 (unsigned long insn,
1885 long value,
1886 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1887 const char **errmsg)
1888{
943d398f
AM		 1889 unsigned int fill_scale = 0;
1890 unsigned long ui8 = value;
b9c361e0 1891
943d398f
AM		 1892 if ((ui8 & 0xffffff00) == 0)
1893 ;
1894 else if ((ui8 & 0xffffff00) == 0xffffff00)
1895 fill_scale = 0x400;
1896 else if ((ui8 & 0xffff00ff) == 0)
b9c361e0 1897 {
943d398f
AM		 1898 fill_scale = 1 << 8;
1899 ui8 >>= 8;
b9c361e0 1900 }
943d398f 1901 else if ((ui8 & 0xffff00ff) == 0xffff00ff)
b9c361e0 1902 {
943d398f
AM		 1903 fill_scale = 0x400 | (1 << 8);
1904 ui8 >>= 8;
b9c361e0 1905 }
943d398f 1906 else if ((ui8 & 0xff00ffff) == 0)
b9c361e0 1907 {
943d398f
AM		 1908 fill_scale = 2 << 8;
1909 ui8 >>= 16;
b9c361e0 1910 }
943d398f 1911 else if ((ui8 & 0xff00ffff) == 0xff00ffff)
b9c361e0 1912 {
943d398f
AM		 1913 fill_scale = 0x400 | (2 << 8);
1914 ui8 >>= 16;
b9c361e0 1915 }
943d398f 1916 else if ((ui8 & 0x00ffffff) == 0)
b9c361e0 1917 {
943d398f
AM		 1918 fill_scale = 3 << 8;
1919 ui8 >>= 24;
b9c361e0 1920 }
943d398f 1921 else if ((ui8 & 0x00ffffff) == 0x00ffffff)
b9c361e0 1922 {
943d398f
AM		 1923 fill_scale = 0x400 | (3 << 8);
1924 ui8 >>= 24;
b9c361e0 1925 }
943d398f 1926 else
b9c361e0 1927 {
943d398f
AM		 1928 *errmsg = _("illegal immediate value");
1929 ui8 = 0;
b9c361e0 1930 }
b9c361e0 1931
943d398f 1932 return insn | fill_scale | (ui8 & 0xff);
b9c361e0
JL		 1933}
1934
1935static long
1936extract_sci8 (unsigned long insn,
1937 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1938 int *invalid ATTRIBUTE_UNUSED)
1939{
943d398f
AM		 1940 int fill = insn & 0x400;
1941 int scale_factor = (insn & 0x300) >> 5;
1942 long value = (insn & 0xff) << scale_factor;
1943
1944 if (fill != 0)
1945 value |= ~((long) 0xff << scale_factor);
1946 return value;
b9c361e0
JL		 1947}
1948
1949static unsigned long
1950insert_sci8n (unsigned long insn,
1951 long value,
943d398f 1952 ppc_cpu_t dialect,
b9c361e0
JL		 1953 const char **errmsg)
1954{
943d398f 1955 return insert_sci8 (insn, -value, dialect, errmsg);
b9c361e0
JL		 1956}
1957
1958static long
1959extract_sci8n (unsigned long insn,
943d398f
AM		 1960 ppc_cpu_t dialect,
1961 int *invalid)
b9c361e0 1962{
943d398f 1963 return -extract_sci8 (insn, dialect, invalid);
b9c361e0
JL		 1964}
1965
1966static unsigned long
1967insert_sd4h (unsigned long insn,
1968 long value,
1969 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1970 const char **errmsg ATTRIBUTE_UNUSED)
1971{
1972 return insn | ((value & 0x1e) << 7);
1973}
1974
1975static long
1976extract_sd4h (unsigned long insn,
1977 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1978 int *invalid ATTRIBUTE_UNUSED)
1979{
1980 return ((insn >> 8) & 0xf) << 1;
1981}
1982
1983static unsigned long
1984insert_sd4w (unsigned long insn,
1985 long value,
1986 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1987 const char **errmsg ATTRIBUTE_UNUSED)
1988{
1989 return insn | ((value & 0x3c) << 6);
1990}
1991
1992static long
1993extract_sd4w (unsigned long insn,
1994 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1995 int *invalid ATTRIBUTE_UNUSED)
1996{
1997 return ((insn >> 8) & 0xf) << 2;
1998}
1999
2000static unsigned long
2001insert_oimm (unsigned long insn,
2002 long value,
2003 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2004 const char **errmsg ATTRIBUTE_UNUSED)
2005{
2006 return insn | (((value - 1) & 0x1f) << 4);
2007}
2008
2009static long
2010extract_oimm (unsigned long insn,
2011 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2012 int *invalid ATTRIBUTE_UNUSED)
2013{
2014 return ((insn >> 4) & 0x1f) + 1;
2015}
2016
252b5132
RH		 2017/* The SH field in an MD form instruction. This is split. */
2018
252b5132 2019static unsigned long
2fbfdc41
AM		 2020insert_sh6 (unsigned long insn,
2021 long value,
fa452fa6 2022 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 2023 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 2024{
6fd3a02d
PB		 2025 /* SH6 operand in the rldixor instructions. */
2026 if (PPC_OP (insn) == 4)
2027 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 5);
2028 else
2029 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
252b5132
RH		 2030}
2031
252b5132 2032static long
2fbfdc41 2033extract_sh6 (unsigned long insn,
fa452fa6 2034 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 2035 int *invalid ATTRIBUTE_UNUSED)
252b5132 2036{
6fd3a02d
PB		 2037 /* SH6 operand in the rldixor instructions. */
2038 if (PPC_OP (insn) == 4)
2039 return ((insn >> 6) & 0x1f) | ((insn << 5) & 0x20);
2040 else
2041 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
252b5132
RH		 2042}
2043
2044/* The SPR field in an XFX form instruction. This is flipped--the
2045 lower 5 bits are stored in the upper 5 and vice- versa. */
2046
2047static unsigned long
2fbfdc41
AM		 2048insert_spr (unsigned long insn,
2049 long value,
fa452fa6 2050 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 2051 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 2052{
2053 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
2054}
2055
2056static long
2fbfdc41 2057extract_spr (unsigned long insn,
fa452fa6 2058 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 2059 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 2060{
2061 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
2062}
2063
da99ee72 2064/* Some dialects have 8 SPRG registers instead of the standard 4. */
14b57c7c 2065#define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405)
da99ee72
AM		 2066
2067static unsigned long
2068insert_sprg (unsigned long insn,
2069 long value,
fa452fa6 2070 ppc_cpu_t dialect,
da99ee72
AM		 2071 const char **errmsg)
2072{
da99ee72 2073 if (value > 7
98c76446 2074 || (value > 3 && (dialect & ALLOW8_SPRG) == 0))
da99ee72
AM		 2075 *errmsg = _("invalid sprg number");
2076
2077 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
2078 user mode. Anything else must use spr 272..279. */
2079 if (value <= 3 || (insn & 0x100) != 0)
2080 value |= 0x10;
2081
2082 return insn | ((value & 0x17) << 16);
2083}
2084
2085static long
2086extract_sprg (unsigned long insn,
fa452fa6 2087 ppc_cpu_t dialect,
da99ee72
AM		 2088 int *invalid)
2089{
2090 unsigned long val = (insn >> 16) & 0x1f;
2091
2092 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
98c76446
AM		 2093 If not BOOKE, 405 or VLE, then both use only 272..275. */
2094 if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0)
e1c93c69
AM		 2095 || (val - 0x10 > 7 && (insn & 0x100) != 0)
2096 || val <= 3
2097 || (val & 8) != 0)
da99ee72
AM		 2098 *invalid = 1;
2099 return val & 7;
2100}
2101
252b5132 2102/* The TBR field in an XFX instruction. This is just like SPR, but it
11a0cf2e 2103 is optional. */
252b5132 2104
252b5132 2105static unsigned long
2fbfdc41
AM		 2106insert_tbr (unsigned long insn,
2107 long value,
fa452fa6 2108 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
8514e4db 2109 const char **errmsg)
252b5132 2110{
8514e4db
AM		 2111 if (value != 268 && value != 269)
2112 *errmsg = _("invalid tbr number");
252b5132
RH		 2113 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
2114}
2115
2116static long
2fbfdc41 2117extract_tbr (unsigned long insn,
fa452fa6 2118 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
8514e4db 2119 int *invalid)
252b5132
RH		 2120{
2121 long ret;
2122
2123 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
8514e4db
AM		 2124 if (ret != 268 && ret != 269)
2125 *invalid = 1;
252b5132
RH		 2126 return ret;
2127}
9b4e5766
PB		 2128
2129/* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
2130
2131static unsigned long
2132insert_xt6 (unsigned long insn,
2133 long value,
2134 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2135 const char **errmsg ATTRIBUTE_UNUSED)
2136{
2137 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
2138}
2139
2140static long
2141extract_xt6 (unsigned long insn,
2142 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2143 int *invalid ATTRIBUTE_UNUSED)
2144{
2145 return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
2146}
2147
a680de9a
PB		 2148/* The XT and XS fields in an DQ form VSX instruction. This is split. */
2149static unsigned long
2150insert_xtq6 (unsigned long insn,
2151 long value,
2152 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2153 const char **errmsg ATTRIBUTE_UNUSED)
2154{
2155 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2);
2156}
2157
2158static long
2159extract_xtq6 (unsigned long insn,
2160 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2161 int *invalid ATTRIBUTE_UNUSED)
2162{
2163 return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f);
2164}
2165
9b4e5766
PB		 2166/* The XA field in an XX3 form instruction. This is split. */
2167
2168static unsigned long
2169insert_xa6 (unsigned long insn,
2170 long value,
2171 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2172 const char **errmsg ATTRIBUTE_UNUSED)
2173{
2174 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
2175}
2176
2177static long
2178extract_xa6 (unsigned long insn,
2179 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2180 int *invalid ATTRIBUTE_UNUSED)
2181{
2182 return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
2183}
2184
2185/* The XB field in an XX3 form instruction. This is split. */
2186
2187static unsigned long
2188insert_xb6 (unsigned long insn,
2189 long value,
2190 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2191 const char **errmsg ATTRIBUTE_UNUSED)
2192{
2193 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
2194}
2195
2196static long
2197extract_xb6 (unsigned long insn,
2198 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2199 int *invalid ATTRIBUTE_UNUSED)
2200{
2201 return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
2202}
2203
2204/* The XB field in an XX3 form instruction when it must be the same as
2205 the XA field in the instruction. This is used for extended
2206 mnemonics like xvmovdp. This operand is marked FAKE. The insertion
2207 function just copies the XA field into the XB field, and the
2208 extraction function just checks that the fields are the same. */
2209
2210static unsigned long
2211insert_xb6s (unsigned long insn,
2212 long value ATTRIBUTE_UNUSED,
2213 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2214 const char **errmsg ATTRIBUTE_UNUSED)
2215{
2216 return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
2217}
2218
2219static long
2220extract_xb6s (unsigned long insn,
2221 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2222 int *invalid)
2223{
2224 if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
2225 || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
2226 *invalid = 1;
2227 return 0;
2228}
066be9f7
PB		 2229
2230/* The XC field in an XX4 form instruction. This is split. */
2231
2232static unsigned long
2233insert_xc6 (unsigned long insn,
2234 long value,
2235 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2236 const char **errmsg ATTRIBUTE_UNUSED)
2237{
2238 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
2239}
2240
2241static long
2242extract_xc6 (unsigned long insn,
2243 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2244 int *invalid ATTRIBUTE_UNUSED)
2245{
2246 return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
2247}
2248
2249static unsigned long
2250insert_dm (unsigned long insn,
2251 long value,
2252 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2253 const char **errmsg)
2254{
2255 if (value != 0 && value != 1)
2256 *errmsg = _("invalid constant");
2257 return insn | (((value) ? 3 : 0) << 8);
2258}
2259
2260static long
2261extract_dm (unsigned long insn,
2262 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2263 int *invalid)
2264{
2265 long value;
2266
2267 value = (insn >> 8) & 3;
2268 if (value != 0 && value != 3)
2269 *invalid = 1;
2270 return (value) ? 1 : 0;
2271}
7b934113 2272
b9c361e0
JL		 2273/* The VLESIMM field in an I16A form instruction. This is split. */
2274
2275static unsigned long
2276insert_vlesi (unsigned long insn,
2277 long value,
2278 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2279 const char **errmsg ATTRIBUTE_UNUSED)
2280{
2281 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2282}
2283
2284static long
2285extract_vlesi (unsigned long insn,
2286 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2287 int *invalid ATTRIBUTE_UNUSED)
2288{
b9c361e0 2289 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
9f0682fe 2290 value = (value ^ 0x8000) - 0x8000;
b9c361e0
JL		 2291 return value;
2292}
2293
2294static unsigned long
2295insert_vlensi (unsigned long insn,
2296 long value,
2297 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2298 const char **errmsg ATTRIBUTE_UNUSED)
2299{
2300 value = -value;
2301 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2302}
2303static long
2304extract_vlensi (unsigned long insn,
2305 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2306 int *invalid ATTRIBUTE_UNUSED)
2307{
2308 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
9f0682fe
AM		 2309 value = (value ^ 0x8000) - 0x8000;
2310 /* Don't use for disassembly. */
b9c361e0
JL		 2311 *invalid = 1;
2312 return -value;
2313}
2314
2315/* The VLEUIMM field in an I16A form instruction. This is split. */
2316
2317static unsigned long
2318insert_vleui (unsigned long insn,
2319 long value,
2320 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2321 const char **errmsg ATTRIBUTE_UNUSED)
2322{
2323 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2324}
2325
2326static long
2327extract_vleui (unsigned long insn,
2328 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2329 int *invalid ATTRIBUTE_UNUSED)
2330{
2331 return ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2332}
2333
2334/* The VLEUIMML field in an I16L form instruction. This is split. */
2335
2336static unsigned long
2337insert_vleil (unsigned long insn,
2338 long value,
2339 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2340 const char **errmsg ATTRIBUTE_UNUSED)
2341{
2342 return insn | ((value & 0xf800) << 5) | (value & 0x7ff);
2343}
2344
2345static long
2346extract_vleil (unsigned long insn,
2347 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2348 int *invalid ATTRIBUTE_UNUSED)
2349{
2350 return ((insn >> 5) & 0xf800) | (insn & 0x7ff);
2351}
2352
252b5132
RH		 2353\f
2354/* Macros used to form opcodes. */
2355
2356/* The main opcode. */
2357#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
2358#define OP_MASK OP (0x3f)
2359
2360/* The main opcode combined with a trap code in the TO field of a D
2361 form instruction. Used for extended mnemonics for the trap
2362 instructions. */
2363#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
2364#define OPTO_MASK (OP_MASK | TO_MASK)
2365
2366/* The main opcode combined with a comparison size bit in the L field
2367 of a D form or X form instruction. Used for extended mnemonics for
2368 the comparison instructions. */
2369#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
2370#define OPL_MASK OPL (0x3f,1)
2371
b9c361e0
JL		 2372/* The main opcode combined with an update code in D form instruction.
2373 Used for extended mnemonics for VLE memory instructions. */
2374#define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
2375#define OPVUP_MASK OPVUP (0x3f, 0xff)
2376
dfdaec14
AJ		 2377/* The main opcode combined with an update code and the RT fields specified in
2378 D form instruction. Used for VLE volatile context save/restore
2379 instructions. */
2380#define OPVUPRT(x,vup,rt) (OPVUP (x, vup) | ((((unsigned long)(rt)) & 0x1f) << 21))
2381#define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f)
2382
252b5132
RH		 2383/* An A form instruction. */
2384#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
2385#define A_MASK A (0x3f, 0x1f, 1)
2386
2387/* An A_MASK with the FRB field fixed. */
2388#define AFRB_MASK (A_MASK | FRB_MASK)
2389
2390/* An A_MASK with the FRC field fixed. */
2391#define AFRC_MASK (A_MASK | FRC_MASK)
2392
2393/* An A_MASK with the FRA and FRC fields fixed. */
2394#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
2395
702f0fb4
PB		 2396/* An AFRAFRC_MASK, but with L bit clear. */
2397#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
2398
252b5132
RH		 2399/* A B form instruction. */
2400#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
2401#define B_MASK B (0x3f, 1, 1)
2402
b9c361e0
JL		 2403/* A BD8 form instruction. This is a 16-bit instruction. */
2404#define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
2405#define BD8_MASK BD8 (0x3f, 1, 1)
2406
2407/* Another BD8 form instruction. This is a 16-bit instruction. */
2408#define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
2409#define BD8IO_MASK BD8IO (0x1f)
2410
2411/* A BD8 form instruction for simplified mnemonics. */
2412#define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2413/* A mask that excludes BO32 and BI32. */
2414#define EBD8IO1_MASK 0xf800
2415/* A mask that includes BO32 and excludes BI32. */
2416#define EBD8IO2_MASK 0xfc00
2417/* A mask that include BO32 AND BI32. */
2418#define EBD8IO3_MASK 0xff00
2419
2420/* A BD15 form instruction. */
2421#define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
2422#define BD15_MASK BD15 (0x3f, 0xf, 1)
2423
2424/* A BD15 form instruction for extended conditional branch mnemonics. */
2425#define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
2426#define EBD15_MASK 0xfff00001
2427
2428/* A BD15 form instruction for extended conditional branch mnemonics with BI. */
2429#define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
2430 | (((aa) & 0xf) << 22) \
2431 | (((bo) & 0x3) << 20) \
2432 | (((bi) & 0x3) << 16) \
2433 | ((lk) & 1)
2434#define EBD15BI_MASK 0xfff30001
2435
2436/* A BD24 form instruction. */
2437#define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
2438#define BD24_MASK BD24 (0x3f, 1, 1)
2439
252b5132
RH		 2440/* A B form instruction setting the BO field. */
2441#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2442#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
2443
2444/* A BBO_MASK with the y bit of the BO field removed. This permits
2445 matching a conditional branch regardless of the setting of the y
94efba12 2446 bit. Similarly for the 'at' bits used for power4 branch hints. */
de866fcc 2447#define Y_MASK (((unsigned long) 1) << 21)
802a735e
AM		 2448#define AT1_MASK (((unsigned long) 3) << 21)
2449#define AT2_MASK (((unsigned long) 9) << 21)
2450#define BBOY_MASK (BBO_MASK &~ Y_MASK)
2451#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
252b5132
RH		 2452
2453/* A B form instruction setting the BO field and the condition bits of
2454 the BI field. */
2455#define BBOCB(op, bo, cb, aa, lk) \
2456 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
2457#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
2458
2459/* A BBOCB_MASK with the y bit of the BO field removed. */
2460#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
802a735e
AM		 2461#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
2462#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
252b5132
RH		 2463
2464/* A BBOYCB_MASK in which the BI field is fixed. */
2465#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
802a735e 2466#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
252b5132 2467
b9c361e0
JL		 2468/* A VLE C form instruction. */
2469#define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
2470#define C_LK_MASK C_LK(0x7fff, 1)
2471#define C(x) ((((unsigned long)(x)) & 0xffff))
2472#define C_MASK C(0xffff)
2473
23976049
EZ		 2474/* An Context form instruction. */
2475#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
fdd12ef3 2476#define CTX_MASK CTX(0x3f, 0x7)
23976049
EZ		 2477
2478/* An User Context form instruction. */
2479#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
fdd12ef3 2480#define UCTX_MASK UCTX(0x3f, 0x1f)
23976049 2481
252b5132
RH		 2482/* The main opcode mask with the RA field clear. */
2483#define DRA_MASK (OP_MASK | RA_MASK)
2484
a680de9a
PB		 2485/* A DQ form VSX instruction. */
2486#define DQX(op, xop) (OP (op) | ((xop) & 0x7))
2487#define DQX_MASK DQX (0x3f, 7)
2488
252b5132
RH		 2489/* A DS form instruction. */
2490#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
2491#define DS_MASK DSO (0x3f, 3)
2492
a680de9a
PB		 2493/* An DX form instruction. */
2494#define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2495#define DX_MASK DX (0x3f, 0x1f)
2496
23976049
EZ		 2497/* An EVSEL form instruction. */
2498#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
2499#define EVSEL_MASK EVSEL(0x3f, 0xff)
2500
b9c361e0
JL		 2501/* An IA16 form instruction. */
2502#define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2503#define IA16_MASK IA16(0x3f, 0x1f)
2504
2505/* An I16A form instruction. */
2506#define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2507#define I16A_MASK I16A(0x3f, 0x1f)
2508
2509/* An I16L form instruction. */
2510#define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2511#define I16L_MASK I16L(0x3f, 0x1f)
2512
2513/* An IM7 form instruction. */
2514#define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
2515#define IM7_MASK IM7(0x1f)
2516
252b5132
RH		 2517/* An M form instruction. */
2518#define M(op, rc) (OP (op) | ((rc) & 1))
2519#define M_MASK M (0x3f, 1)
2520
b9c361e0
JL		 2521/* An LI20 form instruction. */
2522#define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
2523#define LI20_MASK LI20(0x3f, 0x1)
2524
252b5132
RH		 2525/* An M form instruction with the ME field specified. */
2526#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
2527
2528/* An M_MASK with the MB and ME fields fixed. */
2529#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2530
2531/* An M_MASK with the SH and ME fields fixed. */
2532#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
2533
2534/* An MD form instruction. */
2535#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
2536#define MD_MASK MD (0x3f, 0x7, 1)
2537
2538/* An MD_MASK with the MB field fixed. */
2539#define MDMB_MASK (MD_MASK | MB6_MASK)
2540
2541/* An MD_MASK with the SH field fixed. */
2542#define MDSH_MASK (MD_MASK | SH6_MASK)
2543
2544/* An MDS form instruction. */
2545#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
2546#define MDS_MASK MDS (0x3f, 0xf, 1)
2547
2548/* An MDS_MASK with the MB field fixed. */
2549#define MDSMB_MASK (MDS_MASK | MB6_MASK)
2550
2551/* An SC form instruction. */
2552#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
2553#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
2554
b9c361e0
JL		 2555/* An SCI8 form instruction. */
2556#define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
2557#define SCI8_MASK SCI8(0x3f, 0x1f)
2558
2559/* An SCI8 form instruction. */
2560#define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
2561#define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2562
2563/* An SD4 form instruction. This is a 16-bit instruction. */
43e65147 2564#define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
b9c361e0
JL		 2565#define SD4_MASK SD4(0xf)
2566
2567/* An SE_IM5 form instruction. This is a 16-bit instruction. */
2568#define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
2569#define SE_IM5_MASK SE_IM5(0x3f, 1)
2570
2571/* An SE_R form instruction. This is a 16-bit instruction. */
2572#define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
2573#define SE_R_MASK SE_R(0x3f, 0x3f)
2574
2575/* An SE_RR form instruction. This is a 16-bit instruction. */
2576#define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
2577#define SE_RR_MASK SE_RR(0x3f, 3)
2578
2579/* A VX form instruction. */
786e2c0f
C		 2580#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2581
112290ab 2582/* The mask for an VX form instruction. */
786e2c0f
C		 2583#define VX_MASK VX(0x3f, 0x7ff)
2584
fb048c26
PB		 2585/* A VX_MASK with the VA field fixed. */
2586#define VXVA_MASK (VX_MASK | (0x1f << 16))
2587
2588/* A VX_MASK with the VB field fixed. */
2589#define VXVB_MASK (VX_MASK | (0x1f << 11))
2590
2591/* A VX_MASK with the VA and VB fields fixed. */
2592#define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2593
2594/* A VX_MASK with the VD and VA fields fixed. */
2595#define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2596
2597/* A VX_MASK with a UIMM4 field. */
2598#define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
2599
2600/* A VX_MASK with a UIMM3 field. */
2601#define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2602
2603/* A VX_MASK with a UIMM2 field. */
2604#define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
2605
c0637f3a
PB		 2606/* A VX_MASK with a PS field. */
2607#define VXPS_MASK (VX_MASK & ~(0x1 << 9))
2608
a680de9a
PB		 2609/* A VX_MASK with the VA field fixed with a PS field. */
2610#define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9))
2611
b9c361e0 2612/* A VA form instruction. */
2613489e 2613#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
786e2c0f 2614
112290ab 2615/* The mask for an VA form instruction. */
2613489e 2616#define VXA_MASK VXA(0x3f, 0x3f)
786e2c0f 2617
382c72e9
PB		 2618/* A VXA_MASK with a SHB field. */
2619#define VXASHB_MASK (VXA_MASK | (1 << 10))
2620
b9c361e0 2621/* A VXR form instruction. */
786e2c0f
C		 2622#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
2623
112290ab 2624/* The mask for a VXR form instruction. */
786e2c0f
C		 2625#define VXR_MASK VXR(0x3f, 0x3ff, 1)
2626
a680de9a
PB		 2627/* A VX form instruction with a VA tertiary opcode. */
2628#define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16))
2629
6fd3a02d
PB		 2630#define VXASH(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2631#define VXASH_MASK VXASH (0x3f, 0x1f)
2632
252b5132
RH		 2633/* An X form instruction. */
2634#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2635
a680de9a
PB		 2636/* A X form instruction for Quad-Precision FP Instructions. */
2637#define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16))
2638
b9c361e0
JL		 2639/* An EX form instruction. */
2640#define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2641
2642/* The mask for an EX form instruction. */
2643#define EX_MASK EX (0x3f, 0x7ff)
2644
066be9f7
PB		 2645/* An XX2 form instruction. */
2646#define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
2647
a680de9a
PB		 2648/* A XX2 form instruction with the VA bits specified. */
2649#define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16))
2650
9b4e5766
PB		 2651/* An XX3 form instruction. */
2652#define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
2653
066be9f7
PB		 2654/* An XX3 form instruction with the RC bit specified. */
2655#define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
2656
2657/* An XX4 form instruction. */
2658#define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
9b4e5766 2659
702f0fb4
PB		 2660/* A Z form instruction. */
2661#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
2662
252b5132
RH		 2663/* An X form instruction with the RC bit specified. */
2664#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
2665
a680de9a
PB		 2666/* A X form instruction for Quad-Precision FP Instructions with RC bit. */
2667#define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1))
2668
6fd3a02d
PB		 2669/* An X form instruction with the RA bits specified as two ops. */
2670#define XMMF(op, xop, mop0, mop1) (X ((op), (xop)) | ((mop0) & 3) << 19 | ((mop1) & 7) << 16)
2671
702f0fb4
PB		 2672/* A Z form instruction with the RC bit specified. */
2673#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
2674
252b5132
RH		 2675/* The mask for an X form instruction. */
2676#define X_MASK XRC (0x3f, 0x3ff, 1)
2677
a680de9a
PB		 2678/* The mask for an X form instruction with the BF bits specified. */
2679#define XBF_MASK (X_MASK | (3 << 21))
2680
e0d602ec
BE		 2681/* An X form wait instruction with everything filled in except the WC field. */
2682#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2683
9b4e5766
PB		 2684/* The mask for an XX1 form instruction. */
2685#define XX1_MASK X (0x3f, 0x3ff)
2686
c0637f3a
PB		 2687/* An XX1_MASK with the RB field fixed. */
2688#define XX1RB_MASK (XX1_MASK | RB_MASK)
2689
066be9f7
PB		 2690/* The mask for an XX2 form instruction. */
2691#define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
2692
2693/* The mask for an XX2 form instruction with the UIM bits specified. */
2694#define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
2695
a680de9a
PB		 2696/* The mask for an XX2 form instruction with the 4 UIM bits specified. */
2697#define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20))
2698
066be9f7
PB		 2699/* The mask for an XX2 form instruction with the BF bits specified. */
2700#define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
2701
a680de9a
PB		 2702/* The mask for an XX2 form instruction with the BF and DCMX bits specified. */
2703#define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1)
2704
2705/* The mask for an XX2 form instruction with a split DCMX bits specified. */
2706#define XX2DCMXS_MASK XX2 (0x3f, 0x1ee)
2707
9b4e5766
PB		 2708/* The mask for an XX3 form instruction. */
2709#define XX3_MASK XX3 (0x3f, 0xff)
2710
066be9f7
PB		 2711/* The mask for an XX3 form instruction with the BF bits specified. */
2712#define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
2713
2714/* The mask for an XX3 form instruction with the DM or SHW bits specified. */
9b4e5766 2715#define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
066be9f7
PB		 2716#define XX3SHW_MASK XX3DM_MASK
2717
2718/* The mask for an XX4 form instruction. */
2719#define XX4_MASK XX4 (0x3f, 0x3)
2720
2721/* An X form wait instruction with everything filled in except the WC field. */
2722#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
9b4e5766 2723
6fd3a02d
PB		 2724/* The mask for an XMMF form instruction. */
2725#define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1))
2726
702f0fb4
PB		 2727/* The mask for a Z form instruction. */
2728#define Z_MASK ZRC (0x3f, 0x1ff, 1)
0bbdef92 2729#define Z2_MASK ZRC (0x3f, 0xff, 1)
702f0fb4 2730
a680de9a 2731/* An X_MASK with the RA/VA field fixed. */
252b5132 2732#define XRA_MASK (X_MASK | RA_MASK)
a680de9a 2733#define XVA_MASK XRA_MASK
252b5132 2734
a680de9a 2735/* An XRA_MASK with the A_L/W field clear. */
ea192fa3 2736#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
a680de9a 2737#define XRLA_MASK XWRA_MASK
ea192fa3 2738
252b5132
RH		 2739/* An X_MASK with the RB field fixed. */
2740#define XRB_MASK (X_MASK | RB_MASK)
2741
2742/* An X_MASK with the RT field fixed. */
2743#define XRT_MASK (X_MASK | RT_MASK)
2744
702f0fb4
PB		 2745/* An XRT_MASK mask with the L bits clear. */
2746#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
2747
252b5132
RH		 2748/* An X_MASK with the RA and RB fields fixed. */
2749#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
2750
a680de9a
PB		 2751/* An XBF_MASK with the RA and RB fields fixed. */
2752#define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK)
2753
112290ab 2754/* An XRARB_MASK, but with the L bit clear. */
5ae2e65e
AM		 2755#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
2756
a680de9a
PB		 2757/* An XRARB_MASK, but with the L bits in a darn instruction clear. */
2758#define XLRAND_MASK (XRARB_MASK & ~((unsigned long) 3 << 16))
2759
252b5132
RH		 2760/* An X_MASK with the RT and RA fields fixed. */
2761#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
2762
5817ffd1
PB		 2763/* An X_MASK with the RT and RB fields fixed. */
2764#define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
2765
98acc1c5
AM		 2766/* An XRTRA_MASK, but with L bit clear. */
2767#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
2768
5817ffd1
PB		 2769/* An X_MASK with the RT, RA and RB fields fixed. */
2770#define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
2771
2772/* An XRTRARB_MASK, but with L bit clear. */
2773#define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21))
2774
2775/* An XRTRARB_MASK, but with A bit clear. */
2776#define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25))
2777
2778/* An XRTRARB_MASK, but with BF bits clear. */
2779#define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23))
2780
f3806e43
BE		 2781/* An X form instruction with the L bit specified. */
2782#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
252b5132 2783
e0d602ec
BE		 2784/* An X form instruction with the L bits specified. */
2785#define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2786
5817ffd1
PB		 2787/* An X form instruction with the L bit and RC bit specified. */
2788#define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21))
2789
19a6653c
AM		 2790/* An X form instruction with RT fields specified */
2791#define XRT(op, xop, rt) (X ((op), (xop)) \
2792 | ((((unsigned long)(rt)) & 0x1f) << 21))
2793
2794/* An X form instruction with RT and RA fields specified */
2795#define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
2796 | ((((unsigned long)(rt)) & 0x1f) << 21) \
2797 | ((((unsigned long)(ra)) & 0x1f) << 16))
2798
252b5132
RH		 2799/* The mask for an X form comparison instruction. */
2800#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
2801
520ceea4
BE		 2802/* The mask for an X form comparison instruction with the L field
2803 fixed. */
2804#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
252b5132
RH		 2805
2806/* An X form trap instruction with the TO field specified. */
2807#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
2808#define XTO_MASK (X_MASK | TO_MASK)
2809
e0c21649
GK		 2810/* An X form tlb instruction with the SH field specified. */
2811#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
2812#define XTLB_MASK (X_MASK | SH_MASK)
2813
6ba045b1
AM		 2814/* An X form sync instruction. */
2815#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2816
2817/* An X form sync instruction with everything filled in except the LS field. */
2818#define XSYNC_MASK (0xff9fffff)
2819
aea77599
AM		 2820/* An X form sync instruction with everything filled in except the L and E fields. */
2821#define XSYNCLE_MASK (0xff90ffff)
2822
702f0fb4
PB		 2823/* An X_MASK, but with the EH bit clear. */
2824#define XEH_MASK (X_MASK & ~((unsigned long )1))
2825
f5c120c5
MG		 2826/* An X form AltiVec dss instruction. */
2827#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
2828#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
2829
252b5132
RH		 2830/* An XFL form instruction. */
2831#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
ea192fa3 2832#define XFL_MASK XFL (0x3f, 0x3ff, 1)
252b5132 2833
23976049 2834/* An X form isel instruction. */
de866fcc
AM		 2835#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2836#define XISEL_MASK XISEL(0x3f, 0x1f)
23976049 2837
252b5132
RH		 2838/* An XL form instruction with the LK field set to 0. */
2839#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2840
2841/* An XL form instruction which uses the LK field. */
2842#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
2843
2844/* The mask for an XL form instruction. */
2845#define XL_MASK XLLK (0x3f, 0x3ff, 1)
2846
c0637f3a
PB		 2847/* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
2848#define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
2849
252b5132
RH		 2850/* An XL form instruction which explicitly sets the BO field. */
2851#define XLO(op, bo, xop, lk) \
2852 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2853#define XLO_MASK (XL_MASK | BO_MASK)
2854
2855/* An XL form instruction which explicitly sets the y bit of the BO
2856 field. */
2857#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
2858#define XLYLK_MASK (XL_MASK | Y_MASK)
2859
2860/* An XL form instruction which sets the BO field and the condition
2861 bits of the BI field. */
2862#define XLOCB(op, bo, cb, xop, lk) \
2863 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
2864#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
2865
2866/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
2867#define XLBB_MASK (XL_MASK | BB_MASK)
2868#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
2869#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
2870
d0618d1c
AM		 2871/* A mask for branch instructions using the BH field. */
2872#define XLBH_MASK (XL_MASK | (0x1c << 11))
2873
252b5132
RH		 2874/* An XL_MASK with the BO and BB fields fixed. */
2875#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
2876
2877/* An XL_MASK with the BO, BI and BB fields fixed. */
2878#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
2879
e01d869a
AM		 2880/* An X form mbar instruction with MO field. */
2881#define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
2882
252b5132
RH		 2883/* An XO form instruction. */
2884#define XO(op, xop, oe, rc) \
2885 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
2886#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
2887
2888/* An XO_MASK with the RB field fixed. */
2889#define XORB_MASK (XO_MASK | RB_MASK)
2890
c3d65c1c
BE		 2891/* An XOPS form instruction for paired singles. */
2892#define XOPS(op, xop, rc) \
2893 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2894#define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
2895
2896
252b5132
RH		 2897/* An XS form instruction. */
2898#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
2899#define XS_MASK XS (0x3f, 0x1ff, 1)
2900
2901/* A mask for the FXM version of an XFX form instruction. */
98e69875 2902#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
252b5132
RH		 2903
2904/* An XFX form instruction with the FXM field filled in. */
98e69875
AM		 2905#define XFXM(op, xop, fxm, p4) \
2906 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
2907 | ((unsigned long)(p4) << 20))
252b5132
RH		 2908
2909/* An XFX form instruction with the SPR field filled in. */
2910#define XSPR(op, xop, spr) \
2911 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
2912#define XSPR_MASK (X_MASK | SPR_MASK)
2913
2914/* An XFX form instruction with the SPR field filled in except for the
2915 SPRBAT field. */
2916#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
2917
2918/* An XFX form instruction with the SPR field filled in except for the
2919 SPRG field. */
b84bf58a 2920#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
252b5132
RH		 2921
2922/* An X form instruction with everything filled in except the E field. */
2923#define XE_MASK (0xffff7fff)
2924
23976049
EZ		 2925/* An X form user context instruction. */
2926#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2927#define XUC_MASK XUC(0x3f, 0x1f)
2928
c3d65c1c
BE		 2929/* An XW form instruction. */
2930#define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
2931/* The mask for a G form instruction. rc not supported at present. */
2932#define XW_MASK XW (0x3f, 0x3f, 0)
2933
081ba1b3
AM		 2934/* An APU form instruction. */
2935#define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
2936
2937/* The mask for an APU form instruction. */
2938#define APU_MASK APU (0x3f, 0x3ff, 1)
2939#define APU_RT_MASK (APU_MASK | RT_MASK)
2940#define APU_RA_MASK (APU_MASK | RA_MASK)
2941
252b5132
RH		 2942/* The BO encodings used in extended conditional branch mnemonics. */
2943#define BODNZF (0x0)
2944#define BODNZFP (0x1)
2945#define BODZF (0x2)
2946#define BODZFP (0x3)
252b5132
RH		 2947#define BODNZT (0x8)
2948#define BODNZTP (0x9)
2949#define BODZT (0xa)
2950#define BODZTP (0xb)
802a735e
AM		 2951
2952#define BOF (0x4)
2953#define BOFP (0x5)
94efba12
AM		 2954#define BOFM4 (0x6)
2955#define BOFP4 (0x7)
252b5132
RH		 2956#define BOT (0xc)
2957#define BOTP (0xd)
94efba12
AM		 2958#define BOTM4 (0xe)
2959#define BOTP4 (0xf)
802a735e 2960
252b5132
RH		 2961#define BODNZ (0x10)
2962#define BODNZP (0x11)
2963#define BODZ (0x12)
2964#define BODZP (0x13)
94efba12
AM		 2965#define BODNZM4 (0x18)
2966#define BODNZP4 (0x19)
2967#define BODZM4 (0x1a)
2968#define BODZP4 (0x1b)
802a735e 2969
252b5132
RH		 2970#define BOU (0x14)
2971
b9c361e0
JL		 2972/* The BO16 encodings used in extended VLE conditional branch mnemonics. */
2973#define BO16F (0x0)
2974#define BO16T (0x1)
2975
2976/* The BO32 encodings used in extended VLE conditional branch mnemonics. */
2977#define BO32F (0x0)
2978#define BO32T (0x1)
2979#define BO32DNZ (0x2)
2980#define BO32DZ (0x3)
2981
252b5132
RH		 2982/* The BI condition bit encodings used in extended conditional branch
2983 mnemonics. */
2984#define CBLT (0)
2985#define CBGT (1)
2986#define CBEQ (2)
2987#define CBSO (3)
2988
2989/* The TO encodings used in extended trap mnemonics. */
2990#define TOLGT (0x1)
2991#define TOLLT (0x2)
2992#define TOEQ (0x4)
2993#define TOLGE (0x5)
2994#define TOLNL (0x5)
2995#define TOLLE (0x6)
2996#define TOLNG (0x6)
2997#define TOGT (0x8)
2998#define TOGE (0xc)
2999#define TONL (0xc)
3000#define TOLT (0x10)
3001#define TOLE (0x14)
3002#define TONG (0x14)
3003#define TONE (0x18)
3004#define TOU (0x1f)
3005\f
3006/* Smaller names for the flags so each entry in the opcodes table will
3007 fit on a single line. */
3008#undef PPC
de866fcc 3009#define PPC PPC_OPCODE_PPC
661bd698 3010#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
661bd698 3011#define POWER4 PPC_OPCODE_POWER4
1ed8e1e4 3012#define POWER5 PPC_OPCODE_POWER5
702f0fb4 3013#define POWER6 PPC_OPCODE_POWER6
066be9f7 3014#define POWER7 PPC_OPCODE_POWER7
5817ffd1 3015#define POWER8 PPC_OPCODE_POWER8
a680de9a 3016#define POWER9 PPC_OPCODE_POWER9
ede602d7 3017#define CELL PPC_OPCODE_CELL
bdc70b4a 3018#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
6b069ee7 3019#define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
bdc70b4a 3020 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
418c1742 3021#define PPC403 PPC_OPCODE_403
081ba1b3 3022#define PPC405 PPC_OPCODE_405
7d5b217e 3023#define PPC440 PPC_OPCODE_440
c8187e15 3024#define PPC464 PPC440
9fe54b1c 3025#define PPC476 PPC_OPCODE_476
ef5a96d5
AM		 3026#define PPC750 PPC_OPCODE_750
3027#define PPC7450 PPC_OPCODE_7450
3028#define PPC860 PPC_OPCODE_860
c3d65c1c 3029#define PPCPS PPC_OPCODE_PPCPS
a404d431 3030#define PPCVEC PPC_OPCODE_ALTIVEC
aea77599 3031#define PPCVEC2 PPC_OPCODE_ALTIVEC2
a680de9a 3032#define PPCVEC3 PPC_OPCODE_ALTIVEC2
9b4e5766 3033#define PPCVSX PPC_OPCODE_VSX
c0637f3a 3034#define PPCVSX2 PPC_OPCODE_VSX
a680de9a 3035#define PPCVSX3 PPC_OPCODE_VSX3
de866fcc
AM		 3036#define POWER PPC_OPCODE_POWER
3037#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
81a0b7e2
AM		 3038#define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
3039#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
de866fcc 3040#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
de866fcc 3041#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
661bd698 3042#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
de866fcc 3043#define MFDEC1 PPC_OPCODE_POWER
bdc70b4a 3044#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
418c1742 3045#define BOOKE PPC_OPCODE_BOOKE
14b57c7c 3046#define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
36ae0db3 3047#define PPCE300 PPC_OPCODE_E300
14b57c7c
AM		 3048#define PPCSPE PPC_OPCODE_SPE
3049#define PPCISEL PPC_OPCODE_ISEL
3050#define PPCEFS PPC_OPCODE_EFS
de866fcc 3051#define PPCBRLK PPC_OPCODE_BRLOCK
23976049 3052#define PPCPMR PPC_OPCODE_PMR
aea77599 3053#define PPCTMR PPC_OPCODE_TMR
de866fcc 3054#define PPCCHLK PPC_OPCODE_CACHELCK
23976049 3055#define PPCRFMCI PPC_OPCODE_RFMCI
19a6653c 3056#define E500MC PPC_OPCODE_E500MC
634b50f2 3057#define PPCA2 PPC_OPCODE_A2
43e65147 3058#define TITAN PPC_OPCODE_TITAN
14b57c7c 3059#define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
e01d869a 3060#define E500 PPC_OPCODE_E500
aea77599 3061#define E6500 PPC_OPCODE_E6500
b9c361e0 3062#define PPCVLE PPC_OPCODE_VLE
5817ffd1 3063#define PPCHTM PPC_OPCODE_HTM
dfdaec14 3064#define E200Z4 PPC_OPCODE_E200Z4
4fff86c5
PB		 3065/* The list of embedded processors that use the embedded operand ordering
3066 for the 3 operand dcbt and dcbtst instructions. */
3067#define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
14b57c7c 3068 | PPC_OPCODE_A2)
4fff86c5
PB		 3069
3070
252b5132
RH		 3071\f
3072/* The opcode table.
3073
3074 The format of the opcode table is:
3075
8ebac3aa 3076 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
252b5132
RH		 3077
3078 NAME is the name of the instruction.
3079 OPCODE is the instruction opcode.
3080 MASK is the opcode mask; this is used to tell the disassembler
3081 which bits in the actual opcode must match OPCODE.
8ebac3aa
AM		 3082 FLAGS are flags indicating which processors support the instruction.
3083 ANTI indicates which processors don't support the instruction.
252b5132
RH		 3084 OPERANDS is the list of operands.
3085
3086 The disassembler reads the table in order and prints the first
3087 instruction which matches, so this table is sorted to put more
de866fcc
AM		 3088 specific instructions before more general instructions.
3089
3090 This table must be sorted by major opcode. Please try to keep it
3091 vaguely sorted within major opcode too, except of course where
3092 constrained otherwise by disassembler operation. */
252b5132
RH		 3093
3094const struct powerpc_opcode powerpc_opcodes[] = {
14b57c7c
AM		 3095{"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}},
3096{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3097{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3098{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3099{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3100{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3101{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3102{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3103{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3104{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3105{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3106{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3107{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3108{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3109{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3110{"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3111{"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}},
3112
3113{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3114{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3115{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3116{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3117{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3118{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3119{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3120{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3121{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3122{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3123{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3124{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3125{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3126{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3127{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3128{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3129{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3130{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3131{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3132{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3133{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3134{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3135{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3136{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3137{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3138{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3139{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3140{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3141{"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3142{"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3143{"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}},
3144{"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}},
3145
3146{"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3147{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3148{"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
3149{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3150{"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3151{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3152{"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3153{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3154{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3155{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
3156{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3157{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
3158{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3159{"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3160{"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3161{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3162{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3163{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3164{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3165{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3166{"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3167{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3168{"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3169{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3170{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
6fd3a02d 3171{"rldixor", VXASH(4,26), VXASH_MASK, POWER9, 0, {RA, RS, SH6, RB}},
14b57c7c
AM		 3172{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3173{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3174{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3175{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3176{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3177{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3178{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3179{"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
3180{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3181{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3182{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3183{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3184{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3185{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3186{"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3187{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3188{"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3189{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3190{"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3191{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3192{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3193{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3194{"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}},
3195{"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3196{"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3197{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
3198{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3199{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
3200{"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3201{"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3202{"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3203{"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3204{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3205{"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3206{"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3207{"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3208{"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3209{"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3210{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3211{"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3212{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
6fd3a02d
PB		 3213{"xor3", VXA(4, 54), VXA_MASK, POWER9, 0, {RA, RS, RB, RC}},
3214{"nandxor", VXA(4, 55), VXA_MASK, POWER9, 0, {RA, RS, RB, RC}},
14b57c7c
AM		 3215{"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
3216{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3217{"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3218{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3219{"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3220{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3221{"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3222{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3223{"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3224{"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3225{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3226{"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3227{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3228{"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3229{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3230{"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3231{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3232{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3233{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
3234{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3235{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
3236{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3237{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3238{"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3239{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3240{"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3241{"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3242{"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3243{"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3244{"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3245{"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3246{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3247{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3248{"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3249{"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3250{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3251{"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3252{"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3253{"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3254{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3255{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3256{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3257{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3258{"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3259{"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3260{"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3261{"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3262{"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3263{"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3264{"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3265{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3266{"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3267{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3268{"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3269{"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3270{"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3271{"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3272{"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3273{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3274{"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3275{"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3276{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3277{"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3278{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3279{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3280{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3281{"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3282{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3283{"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3284{"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3285{"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3286{"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3287{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3288{"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3289{"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3290{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3291{"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3292{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3293{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3294{"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3295{"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3296{"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3297{"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3298{"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3299{"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3300{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3301{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3302{"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3303{"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3304{"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3305{"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3306{"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3307{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3308{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3309{"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3310{"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3311{"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3312{"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3313{"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3314{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3315{"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3316{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3317{"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3318{"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3319{"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3320{"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3321{"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3322{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3323{"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
3324{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3325{"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3326{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3327{"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
3328{"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3329{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
3330{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3331{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3332{"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}},
3333{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3334{"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}},
3335{"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}},
3336{"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3337{"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}},
3338{"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}},
3339{"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}},
3340{"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3341{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},
3342{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},
3343{"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3344{"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3345{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3346{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3347{"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3348{"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3349{"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3350{"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
3351{"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3352{"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3353{"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
3354{"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3355{"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3356{"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3357{"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3358{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3359{"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3360{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3361{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3362{"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3363{"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3364{"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3365{"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}},
3366{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3367{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}},
3368{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3369{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3370{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3371{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3372{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3373{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3374{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3375{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3376{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3377{"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3378{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3379{"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3380{"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3381{"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3382{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3383{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3384{"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3385{"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}},
3386{"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3387{"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3388{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3389{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},
3390{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3391{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3392{"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3393{"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3394{"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3395{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},
3396{"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3397{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
3398{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
3399{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3400{"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3401{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3402{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3403{"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3404{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3405{"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
3406{"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3407{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3408{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3409{"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3410{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
3411{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
3412{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
3413{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
3414{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
3415{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
3416{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
3417{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
3418{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},
3419{"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3420{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},
3421{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3422{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3423{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3424{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3425{"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3426{"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3427{"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3428{"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
3429{"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3430{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
3431{"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
3432{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3433{"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3434{"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3435{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3436{"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3437{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3438{"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3439{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3440{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3441{"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3442{"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
3443{"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
3444{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
3445{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
3446{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
3447{"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
3448{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
3449{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
3450{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
3451{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
3452{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3453{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
3454{"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3455{"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3456{"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3457{"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3458{"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3459{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}},
3460{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}},
3461{"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
3462{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
3463{"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
3464{"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3465{"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3466{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}},
3467{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}},
3468{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3469{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3470{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3471{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
3472{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}},
3473{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}},
3474{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
3475{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
3476{"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
3477{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
3478{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
3479{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
3480{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}},
3481{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3482{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}},
3483{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3484{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3485{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3486{"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3487{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3488{"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3489{"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3490{"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3491{"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3492{"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3493{"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3494{"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3495{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3496{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3497{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3498{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3499{"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3500{"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3501{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3502{"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3503{"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3504{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3505{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3506{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3507{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3508{"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3509{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3510{"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3511{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3512{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3513{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3514{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3515{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3516{"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3517{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3518{"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3519{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3520{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3521{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3522{"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3523{"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3524{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3525{"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3526{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3527{"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3528{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3529{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3530{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3531{"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3532{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3533{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3534{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3535{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3536{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3537{"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3538{"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3539{"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3540{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3541{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3542{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3543{"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3544{"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3545{"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3546{"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3547{"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3548{"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3549{"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3550{"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3551{"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3552{"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3553{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3554{"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3555{"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3556{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3557{"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3558{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3559{"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3560{"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3561{"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3562{"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3563{"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3564{"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3565{"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3566{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3567{"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3568{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3569{"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3570{"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3571{"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3572{"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3573{"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3574{"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3575{"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3576{"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3577{"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
3578{"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3579{"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3580{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3581{"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3582{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3583{"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3584{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3585{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3586{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3587{"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3588{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3589{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3590{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3591{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3592{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3593{"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3594{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3595{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3596{"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3597{"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3598{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3599{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3600{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3601{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3602{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3603{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3604{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3605{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3606{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3607{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3608{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3609{"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
3610{"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3611{"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3612{"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3613{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3614{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3615{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3616{"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3617{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3618{"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3619{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3620{"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3621{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3622{"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3623{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3624{"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3625{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3626{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3627{"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3628{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3629{"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3630{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3631{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3632{"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3633{"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3634{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3635{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3636{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3637{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3638{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3639{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3640{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3641{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3642{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3643{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3644{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3645{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3646{"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3647{"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3648{"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3649{"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
3650{"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3651{"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3652{"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3653{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3654{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3655{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3656{"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3657{"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3658{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3659{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3660{"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3661{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}},
3662{"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3663{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}},
3664{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}},
3665{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}},
3666{"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}},
3667{"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3668{"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3669{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3670{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3671{"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3672{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3673{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3674{"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3675{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}},
3676{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},
3677{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},
3678{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},
3679{"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3680{"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3681{"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3682{"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3683{"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3684{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3685{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3686{"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3687{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3688{"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3689{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3690{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3691{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3692{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3693{"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
3694{"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3695{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3696{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3697{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3698{"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3699{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3700{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3701{"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3702{"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3703{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3704{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3705{"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3706{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3707{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3708{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3709{"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3710{"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3711{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3712{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3713{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3714{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3715{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3716{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3717{"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3718{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3719{"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3720{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3721{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3722{"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3723{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3724{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3725{"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3726{"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3727{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3728{"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3729{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3730{"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3731{"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3732{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3733{"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3734{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3735{"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3736{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3737{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3738{"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3739{"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3740{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3741{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3742{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3743{"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3744{"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3745{"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3746{"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3747{"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3748{"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3749{"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3750{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3751{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3752{"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3753{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3754{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3755{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3756{"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3757{"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3758{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3759{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3760{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3761{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3762{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3763{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3764{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3765{"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3766{"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3767{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3768{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3769{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3770{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3771{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3772{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3773{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3774{"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3775{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3776{"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3777{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3778{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3779{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3780{"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}},
3781{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3782{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3783{"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3784{"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3785{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3786{"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3787{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3788{"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3789{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3790{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3791{"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3792{"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3793{"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3794{"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
3795{"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
3796{"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3797{"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3798{"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3799{"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3800{"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3801{"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3802{"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3803{"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3804{"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3805{"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3806{"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3807{"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3808{"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3809{"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3810{"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}},
3811{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
9fe54b1c
PB		 3812{"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3813{"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3814{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3815{"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3816{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3817{"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}},
3818{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3819{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
9fe54b1c
PB		 3820{"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3821{"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3822{"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3823{"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3824{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3825{"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
3826{"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3827{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
9fe54b1c
PB		 3828{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3829{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3830{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3831{"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3832{"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3833{"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
3834{"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3835{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
9fe54b1c 3836{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c 3837{"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
9fe54b1c 3838{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3839{"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3840{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3841{"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3842{"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3843{"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3844{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
9fe54b1c
PB		 3845{"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3846{"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3847{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3848{"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3849{"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3850{"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3851{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3852{"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3853{"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3854{"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3855{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3856{"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
9fe54b1c
PB		 3857{"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3858{"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3859{"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3860{"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3861{"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3862{"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3863{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3864{"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3865{"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3866{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
9fe54b1c
PB		 3867{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3868{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3869{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3870{"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3871{"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3872{"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3873{"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3874{"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3875{"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3876{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
9fe54b1c 3877{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c 3878{"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
9fe54b1c 3879{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3880{"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3881{"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3882{"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3883{"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3884{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}},
3885
3886{"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3887{"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3888
3889{"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3890{"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3891
3892{"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}},
3893
3894{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}},
3895{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}},
3896{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L, RA, UISIGNOPT}},
3897{"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}},
3898
3899{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}},
3900{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}},
3901{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L, RA, SI}},
3902{"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}},
3903
3904{"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3905{"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3906{"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
3907
3908{"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3909{"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3910{"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
3911
3912{"li", OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}},
3913{"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}},
3914{"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}},
3915{"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
3916{"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}},
3917{"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
3918
3919{"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE, {RT, SISIGNOPT}},
3920{"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE, {RT, SISIGNOPT}},
3921{"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
3922{"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
3923{"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}},
3924
3925{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3926{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3927{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
3928{"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
3929{"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3930{"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3931{"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
3932{"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
3933{"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3934{"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3935{"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
3936{"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
3937{"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3938{"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3939{"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
3940{"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
3941{"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3942{"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3943{"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCVLE, {BD}},
3944{"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3945{"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3946{"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCVLE, {BD}},
3947{"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3948{"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3949{"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCVLE, {BDA}},
3950{"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3951{"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3952{"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCVLE, {BDA}},
3953
3954{"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3955{"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3956{"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3957{"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3958{"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3959{"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3960{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3961{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3962{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3963{"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3964{"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3965{"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3966{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3967{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3968{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3969{"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3970{"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3971{"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3972{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3973{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3974{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3975{"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3976{"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3977{"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3978{"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3979{"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3980{"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3981{"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3982{"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3983{"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3984{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3985{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3986{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3987{"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3988{"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3989{"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3990{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3991{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3992{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3993{"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3994{"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3995{"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3996{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3997{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3998{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3999{"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4000{"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4001{"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4002{"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4003{"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4004{"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4005{"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4006{"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4007{"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4008{"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4009{"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4010{"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4011{"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4012{"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4013{"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4014{"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4015{"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4016{"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4017{"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4018{"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4019{"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4020{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4021{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4022{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4023{"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4024{"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4025{"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4026{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4027{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4028{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4029{"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4030{"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4031{"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4032{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4033{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4034{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4035{"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4036{"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4037{"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4038
4039{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4040{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4041{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4042{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4043{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4044{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4045{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4046{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4047{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4048{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4049{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4050{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4051{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4052{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4053{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4054{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4055{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4056{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4057{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4058{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4059{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4060{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4061{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4062{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4063{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4064{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4065{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4066{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4067{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4068{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4069{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4070{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4071{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4072{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4073{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4074{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4075{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4076{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4077{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4078{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4079{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4080{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4081{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4082{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4083{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4084{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4085{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4086{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4087{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4088{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4089{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4090{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4091{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4092{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4093{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4094{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4095{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4096{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4097{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4098{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4099
4100{"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4101{"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4102{"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4103{"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4104{"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4105{"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4106{"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4107{"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4108{"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4109{"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4110{"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4111{"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4112{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4113{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4114{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4115{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4116{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4117{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4118{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4119{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4120{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4121{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4122{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4123{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4124
4125{"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4126{"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4127{"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4128{"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4129{"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4130{"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4131{"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4132{"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4133{"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4134{"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4135{"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4136{"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4137{"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4138{"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4139{"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4140{"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4141
4142{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4143{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4144{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4145{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4146{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4147{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4148{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4149{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4150{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4151{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4152{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4153{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4154{"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4155{"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4156{"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4157{"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4158{"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4159{"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4160{"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4161{"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4162{"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4163{"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4164{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4165{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4166
4167{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4168{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4169{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4170{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4171{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4172{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4173{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4174{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4175{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4176{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4177{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4178{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4179{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4180{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4181{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4182{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4183
4184{"bc-", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
4185{"bc+", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
4186{"bc", B(16,0,0), B_MASK, COM, PPCVLE, {BO, BI, BD}},
4187{"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
4188{"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
4189{"bcl", B(16,0,1), B_MASK, COM, PPCVLE, {BO, BI, BD}},
4190{"bca-", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
4191{"bca+", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
4192{"bca", B(16,1,0), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
4193{"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
4194{"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
4195{"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
4196
4197{"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
4198{"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
4199{"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}},
4200{"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
4201{"svcla", SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}},
4202
4203{"b", B(18,0,0), B_MASK, COM, PPCVLE, {LI}},
4204{"bl", B(18,0,1), B_MASK, COM, PPCVLE, {LI}},
4205{"ba", B(18,1,0), B_MASK, COM, PPCVLE, {LIA}},
4206{"bla", B(18,1,1), B_MASK, COM, PPCVLE, {LIA}},
4207
4208{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
4209
4210{"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}},
4211{"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}},
4212
4213{"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4214{"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4215{"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4216{"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4217{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4218{"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4219{"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4220{"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4221{"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4222{"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4223{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4224{"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4225{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4226{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
4227{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4228{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
4229{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4230{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4231{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4232{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4233{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4234{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4235{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4236{"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4237
4238{"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4239{"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4240{"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4241{"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4242{"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4243{"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4244{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4245{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4246{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4247{"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4248{"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4249{"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4250{"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4251{"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4252{"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4253{"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4254{"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4255{"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4256{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4257{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4258{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4259{"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4260{"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4261{"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4262{"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4263{"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4264{"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4265{"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4266{"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4267{"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4268{"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4269{"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4270{"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4271{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4272{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4273{"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4274{"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4275{"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4276{"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4277{"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4278{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4279{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4280{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4281{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4282{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4283{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4284{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4285{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4286{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4287{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4288{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4289{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4290{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4291{"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4292{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4293{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4294{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4295{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4296{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4297{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4298{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4299{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4300{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4301{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4302{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4303{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4304{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4305{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4306{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4307{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4308{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4309{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4310{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4311{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4312{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4313{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4314{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4315{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4316{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4317{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4318{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4319{"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4320{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4321{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4322{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4323{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4324{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4325{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4326{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4327{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4328{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4329{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4330{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4331{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4332{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4333{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4334{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4335{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4336{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4337{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4338{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4339{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4340{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4341{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4342{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4343{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4344{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4345{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4346{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4347{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4348{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4349{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4350{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4351{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4352{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4353{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4354{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4355{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4356{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4357{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4358{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4359{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4360{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4361{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4362{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4363{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4364{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4365{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4366{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4367{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4368{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4369{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4370{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4371{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4372{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4373{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4374{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4375{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4376{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4377{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4378
4379{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4380{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4381{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4382{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4383{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4384{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4385{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4386{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4387{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4388{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4389{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4390{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4391{"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4392{"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4393{"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4394{"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4395{"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4396{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4397{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4398{"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4399{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4400{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4401{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4402{"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4403{"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4404{"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4405{"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4406{"bdnztlrl-", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4407{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4408{"bdnztlrl+", XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4409{"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4410{"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4411{"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4412{"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4413{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4414{"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4415{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4416{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4417{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4418{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4419{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4420{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4421{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4422{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4423{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4424{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4425{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4426{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4427
4428{"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4429{"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4430{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4431{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4432{"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4433{"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4434{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4435{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4436
4437{"rfid", XL(19,18), 0xffffffff, PPC64, PPCVLE, {0}},
4438
4439{"crnot", XL(19,33), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
4440{"crnor", XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4441{"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}},
4442
4443{"rfdi", XL(19,39), 0xffffffff, E500MC, PPCVLE, {0}},
4444{"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}},
4445{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}},
4446
4447{"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}},
4448
4449{"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}},
4450
4451{"crandc", XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4452
4453{"rfebb", XL(19,146), XLS_MASK, POWER8, PPCVLE, {SXL}},
4454
4455{"isync", XL(19,150), 0xffffffff, PPCCOM, PPCVLE, {0}},
4456{"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}},
4457
4458{"crclr", XL(19,193), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
4459{"crxor", XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4460
4461{"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}},
4462
4463{"crnand", XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4464
4465{"crand", XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4466
4467{"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476|PPCVLE, {0}},
4468
4469{"crset", XL(19,289), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
4470{"creqv", XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4471
4472{"urfid", XL(19,306), 0xffffffff, POWER9, PPCVLE, {0}},
4473{"stop", XL(19,370), 0xffffffff, POWER9, PPCVLE, {0}},
4474
4475{"doze", XL(19,402), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4476
4477{"crorc", XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4478
4479{"nap", XL(19,434), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4480
4481{"crmove", XL(19,449), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
4482{"cror", XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4483
4484{"sleep", XL(19,466), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4485{"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4486
4487{"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCVLE, {0}},
4488{"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCVLE, {0}},
4489
4490{"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4491{"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4492{"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4493{"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4494{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4495{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4496{"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4497{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4498{"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4499{"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4500{"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4501{"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4502{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4503{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4504{"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4505{"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4506{"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4507{"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4508{"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4509{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4510{"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4511{"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4512{"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4513{"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4514{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4515{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4516{"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4517{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4518{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4519{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4520{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4521{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4522{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4523{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4524{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4525{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4526{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4527{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4528{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4529{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4530{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4531{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4532{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4533{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4534{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4535{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4536{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4537{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4538{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4539{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4540{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4541{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4542{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4543{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4544{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4545{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4546{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4547{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4548{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4549{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4550{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4551{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4552{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4553{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4554{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4555{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4556{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4557{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4558{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4559{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4560{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4561{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4562{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4563{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4564{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4565{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4566{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4567{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4568{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4569{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4570{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4571{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4572{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4573{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4574{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4575{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4576{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4577{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4578{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4579{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4580{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4581{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4582{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4583{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4584{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4585{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4586{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4587{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4588{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4589{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4590{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4591{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4592{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4593{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4594{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4595{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4596{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4597{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4598{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4599{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4600{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4601{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4602{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4603{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4604{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4605{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4606{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4607{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4608{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4609{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4610
4611{"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4612{"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4613{"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4614{"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4615{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4616{"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4617{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4618{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4619{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4620{"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4621{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4622{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4623{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4624{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4625{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4626{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4627{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4628{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4629{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4630{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4631
4632{"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4633{"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4634{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4635{"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4636{"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4637{"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4638{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4639{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4640
4641{"bctar-", XLYLK(19,560,0,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4642{"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4643{"bctar+", XLYLK(19,560,1,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4644{"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4645{"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
4646{"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
4647
4648{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4649{"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4650
4651{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4652{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4653
4654{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4655{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4656{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4657{"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4658{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4659{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4660{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4661{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4662
4663{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4664{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4665
4666{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4667{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4668{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4669{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4670{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4671{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4672
4673{"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}},
4674{"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4675{"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4676
4677{"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4678{"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4679
4680{"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}},
4681{"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4682{"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4683
4684{"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4685{"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4686
4687{"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4688{"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4689
4690{"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4691{"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4692
4693{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
4694{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
4695{"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4696{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
4697{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
4698{"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4699
4700{"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
4701{"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
4702
4703{"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4704{"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4705
4706{"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4707{"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4708
4709{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4710{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4711{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4712{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4713
4714{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4715{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4716
4717{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4718{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
4719{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L, RA, RB}},
bdc70b4a 4720{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
1cb0a767 4721
14b57c7c
AM		 4722{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4723{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4724{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4725{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4726{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}},
4727{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}},
4728{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4729{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4730{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4731{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4732{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4733{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4734{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4735{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4736{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4737{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4738{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4739{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4740{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4741{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4742{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4743{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4744{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4745{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4746{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4747{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4748{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4749{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4750{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}},
4751{"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}},
4752{"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}},
4753{"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}},
4754{"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
4755
4756{"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4757{"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4758{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4759
4760{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4761{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4762{"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4763{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4764{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4765{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4766
4767{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4768{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4769
4770{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4771{"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4772{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4773{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4774
4775{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4776{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4777
4778{"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
4779
4780{"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4781
4782{"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}},
4783{"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}},
4784{"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4785{"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}},
4786
4787{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}},
4788{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}},
4789
4790{"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}},
4791
4792{"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},
4793
4794{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}},
4795
4796{"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
4797{"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4798
4799{"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4800{"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4801{"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4802{"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4803
4804{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
4805{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
4806{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
4807{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
4808
4809{"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}},
4810{"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}},
4811
4812{"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}},
4813{"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}},
4814
4815{"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
4816{"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
4817
4818{"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4819
4820{"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}},
4821{"wait", X(31,30), XWC_MASK, POWER9, 0, {WC}},
4822
4823{"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4824
4825{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4826{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
4827{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L, RA, RB}},
bdc70b4a 4828{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
de866fcc 4829
14b57c7c
AM		 4830{"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4831{"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4832{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
de866fcc 4833
14b57c7c 4834{"mviwsplt", X(31,46), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
e67ed0e8 4835
14b57c7c 4836{"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
de866fcc 4837
14b57c7c 4838{"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
de866fcc 4839
14b57c7c 4840{"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}},
066be9f7 4841
14b57c7c 4842{"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
c0637f3a 4843
14b57c7c 4844{"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
de866fcc 4845
14b57c7c 4846{"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}},
de866fcc 4847
14b57c7c
AM		 4848{"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4849{"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}},
4850{"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4851{"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}},
de866fcc 4852
14b57c7c
AM		 4853{"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
4854{"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
4855{"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4856{"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}},
e0d602ec 4857
14b57c7c 4858{"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
066be9f7 4859
14b57c7c 4860{"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}},
43e65147 4861
14b57c7c 4862{"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}},
43e65147 4863
14b57c7c
AM		 4864{"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}},
4865{"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
de866fcc 4866
14b57c7c
AM		 4867{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}},
4868{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}},
de866fcc 4869
14b57c7c
AM		 4870{"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}},
4871{"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}},
de866fcc 4872
14b57c7c
AM		 4873{"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
4874{"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
4875{"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}},
43e65147 4876
14b57c7c 4877{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
19a6653c 4878
14b57c7c
AM		 4879{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}},
4880{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}},
4881{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}},
4882{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}},
4883{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}},
4884{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}},
4885{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}},
4886{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}},
4887{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}},
4888{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}},
4889{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}},
4890{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}},
4891{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}},
4892{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}},
4893{"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}},
4894{"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}},
de866fcc 4895
14b57c7c
AM		 4896{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4897{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4898{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
43e65147 4899
14b57c7c
AM		 4900{"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4901{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
de866fcc 4902
14b57c7c
AM		 4903{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
4904{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
de866fcc 4905
14b57c7c 4906{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}},
de866fcc 4907
14b57c7c 4908{"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}},
43e65147 4909
14b57c7c 4910{"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
de866fcc 4911
c7a8dbf9 4912{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},
14b57c7c 4913{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L}},
de866fcc 4914
14b57c7c 4915{"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
43e65147 4916
14b57c7c 4917{"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
de866fcc 4918
14b57c7c 4919{"dni", XRC(31,97,1), XRB_MASK, E6500, 0, {DUI, DCTL}},
aea77599 4920
14b57c7c
AM		 4921{"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4922{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
de866fcc 4923
14b57c7c
AM		 4924{"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}},
4925{"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}},
de866fcc 4926
14b57c7c
AM		 4927{"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
4928{"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
de866fcc 4929
14b57c7c 4930{"mvidsplt", X(31,110), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
aea77599 4931
14b57c7c 4932{"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}},
de866fcc 4933
14b57c7c
AM		 4934{"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
4935{"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4936{"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
c0637f3a 4937
14b57c7c 4938{"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
066be9f7 4939
14b57c7c 4940{"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}},
de866fcc 4941
14b57c7c 4942{"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}},
43e65147 4943
14b57c7c 4944{"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}},
de866fcc 4945
14b57c7c
AM		 4946{"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RBS}},
4947{"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}},
4948{"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RBS}},
4949{"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}},
19a6653c 4950
14b57c7c 4951{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
43e65147 4952
6fd3a02d
PB		 4953{"setb", VX(31,256), VXVB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
4954{"setbool", VX(31,257), VXVB_MASK, POWER9, 0, {RT, BA}},
a680de9a 4955
14b57c7c 4956{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}},
43e65147 4957
14b57c7c 4958{"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
de866fcc 4959
14b57c7c
AM		 4960{"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4961{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
de866fcc 4962
14b57c7c
AM		 4963{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4964{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4965{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4966{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
de866fcc 4967
14b57c7c
AM		 4968{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4969{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4970{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4971{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
de866fcc 4972
14b57c7c 4973{"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
c0637f3a 4974
14b57c7c
AM		 4975{"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}},
4976{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
de866fcc 4977
14b57c7c
AM		 4978{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, 0, {RS}},
4979{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}},
4980{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}},
de866fcc 4981
14b57c7c 4982{"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}},
de866fcc 4983
14b57c7c 4984{"mtsle", X(31,147), XRTLRARB_MASK, POWER8, 0, {L}},
c0637f3a 4985
14b57c7c
AM		 4986{"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}},
4987{"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
e0d602ec 4988
14b57c7c 4989{"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}},
43e65147 4990
14b57c7c 4991{"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}},
43e65147 4992
14b57c7c
AM		 4993{"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
4994{"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}},
de866fcc 4995
14b57c7c
AM		 4996{"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}},
4997{"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}},
de866fcc 4998
14b57c7c
AM		 4999{"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}},
5000{"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}},
de866fcc 5001
14b57c7c 5002{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}},
de866fcc 5003
6fd3a02d
PB		 5004{"brw", X(31,155), XRB_MASK, POWER9, 0, {RA, RS}},
5005
14b57c7c 5006{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
43e65147 5007
14b57c7c 5008{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
43e65147 5009
14b57c7c 5010{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}},
43e65147 5011
14b57c7c 5012{"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
de866fcc 5013
14b57c7c
AM		 5014{"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5015{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
de866fcc 5016
14b57c7c
AM		 5017{"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
5018{"addex.", ZRC(31,170,1), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
19dfcc89 5019
14b57c7c
AM		 5020{"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}},
5021{"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
de866fcc 5022
14b57c7c 5023{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}},
de866fcc 5024
14b57c7c
AM		 5025{"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5026{"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5027{"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5028{"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}},
e0d602ec 5029
14b57c7c 5030{"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}},
de866fcc 5031
14b57c7c
AM		 5032{"stqcx.", XRC(31,182,1), X_MASK, POWER8, 0, {RSQ, RA0, RB}},
5033{"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}},
e0d602ec 5034
14b57c7c
AM		 5035{"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}},
5036{"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
de866fcc 5037
14b57c7c
AM		 5038{"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}},
5039{"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}},
de866fcc 5040
14b57c7c 5041{"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}},
252b5132 5042
6fd3a02d
PB		 5043{"brd", X(31,187), XRB_MASK, POWER9, 0, {RA, RS}},
5044
14b57c7c 5045{"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}},
a680de9a 5046
14b57c7c 5047{"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},
aea77599 5048
14b57c7c
AM		 5049{"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5050{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 5051
14b57c7c
AM		 5052{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5053{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5054{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5055{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
252b5132 5056
14b57c7c
AM		 5057{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5058{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5059{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5060{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
418c1742 5061
14b57c7c 5062{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
19a6653c 5063
14b57c7c 5064{"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
418c1742 5065
14b57c7c
AM		 5066{"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5067{"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5068{"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5069{"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}},
e0d602ec 5070
14b57c7c 5071{"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
e0d602ec 5072
14b57c7c 5073{"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}},
43e65147 5074
14b57c7c 5075{"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}},
252b5132 5076
14b57c7c
AM		 5077{"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}},
5078{"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 5079
14b57c7c
AM		 5080{"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
5081{"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 5082
6fd3a02d
PB		 5083{"brh", X(31,219), XRB_MASK, POWER9, 0, {RA, RS}},
5084
14b57c7c 5085{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
43e65147 5086
14b57c7c 5087{"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}},
a680de9a 5088
14b57c7c 5089{"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
7d5b217e 5090
14b57c7c
AM		 5091{"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5092{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
f509565f 5093
14b57c7c
AM		 5094{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5095{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5096{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5097{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
252b5132 5098
14b57c7c
AM		 5099{"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5100{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
43e65147 5101
14b57c7c
AM		 5102{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5103{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5104{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5105{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
252b5132 5106
14b57c7c
AM		 5107{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5108{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5109{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5110{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 5111
14b57c7c
AM		 5112{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
5113{"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
5114{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
bdc70b4a 5115{"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
418c1742 5116
14b57c7c
AM		 5117{"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5118{"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5119{"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
c0637f3a 5120
14b57c7c
AM		 5121{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5122{"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5123{"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5124{"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
4fff86c5 5125
14b57c7c 5126{"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}},
252b5132 5127
14b57c7c
AM		 5128{"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}},
5129{"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}},
252b5132 5130
14b57c7c 5131{"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}},
066be9f7 5132
14b57c7c 5133{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
19a6653c 5134
14b57c7c
AM		 5135{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
5136{"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}},
252b5132 5137
14b57c7c 5138{"lvexbx", X(31,261), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 5139
14b57c7c 5140{"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}},
1ed8e1e4 5141
14b57c7c 5142{"lvepxl", X(31,263), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 5143
14b57c7c
AM		 5144{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5145{"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5146{"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 5147
14b57c7c 5148{"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}},
a680de9a 5149
14b57c7c
AM		 5150{"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5151{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5152{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5153{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
418c1742 5154
14b57c7c 5155{"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}},
a680de9a 5156
14b57c7c
AM		 5157{"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}},
5158{"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 5159
14b57c7c 5160{"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}},
19a6653c 5161
14b57c7c 5162{"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}},
a680de9a 5163{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, L}},
418c1742 5164
14b57c7c 5165{"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
1cb0a767 5166
14b57c7c 5167{"lqarx", X(31,276), XEH_MASK, POWER8, 0, {RTQ, RAX, RBX, EH}},
c0637f3a 5168
14b57c7c
AM		 5169{"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}},
5170{"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},
1cb0a767 5171
14b57c7c
AM		 5172{"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5173{"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5174{"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5175{"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
4fff86c5 5176
14b57c7c 5177{"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}},
1cb0a767 5178
14b57c7c 5179{"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}},
066be9f7 5180
14b57c7c
AM		 5181{"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}},
5182{"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}},
1cb0a767 5183
14b57c7c 5184{"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
1cb0a767 5185
14b57c7c 5186{"mfdcrux", X(31,291), X_MASK, PPC464, 0, {RS, RA}},
1cb0a767 5187
14b57c7c
AM		 5188{"lvexhx", X(31,293), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5189{"lvepx", X(31,295), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 5190
14b57c7c 5191{"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 5192
14b57c7c 5193{"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
c0637f3a 5194
14b57c7c
AM		 5195{"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
5196{"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},
5197{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, L}},
5198{"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},
1cb0a767 5199
14b57c7c 5200{"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},
a680de9a 5201
14b57c7c 5202{"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}},
a680de9a 5203
14b57c7c 5204{"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
1cb0a767 5205
14b57c7c 5206{"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}},
1cb0a767 5207
14b57c7c 5208{"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}},
066be9f7 5209
14b57c7c
AM		 5210{"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}},
5211{"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}},
1cb0a767 5212
14b57c7c 5213{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
1cb0a767 5214
14b57c7c
AM		 5215{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}},
5216{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}},
5217{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}},
5218{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}},
5219{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}},
5220{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}},
5221{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}},
5222{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}},
5223{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}},
5224{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}},
5225{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}},
5226{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}},
5227{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}},
5228{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}},
5229{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}},
5230{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}},
5231{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}},
5232{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}},
5233{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}},
5234{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}},
5235{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}},
5236{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}},
5237{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}},
5238{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}},
5239{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}},
5240{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}},
5241{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}},
5242{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}},
5243{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}},
5244{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}},
5245{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}},
5246{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}},
5247{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}},
5248{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}},
5249{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
5250{"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}},
1cb0a767 5251
14b57c7c 5252{"lvexwx", X(31,325), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 5253
14b57c7c 5254{"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}},
9fe54b1c 5255
14b57c7c
AM		 5256{"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5257{"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
1cb0a767 5258
14b57c7c 5259{"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
066be9f7 5260
14b57c7c
AM		 5261{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
5262{"mftmr", X(31,366), X_MASK, PPCTMR|E6500, 0, {RT, TMR}},
1cb0a767 5263
14b57c7c
AM		 5264{"slbsync", X(31,338), 0xffffffff, POWER9, 0, {0}},
5265
5266{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}},
5267{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}},
5268{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
5269{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
5270{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}},
5271{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}},
5272{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}},
5273{"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}},
5274{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}},
5275{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
5276{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
bdc70b4a 5277{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}},
14b57c7c
AM		 5278{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}},
5279{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}},
5280{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}},
5281{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}},
5282{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}},
5283{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}},
5284{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}},
5285{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}},
5286{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}},
5287{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}},
5288{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}},
5289{"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}},
5290{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}},
5291{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}},
5292{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}},
5293{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}},
5294{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}},
5295{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}},
5296{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}},
5297{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}},
5298{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}},
5299{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}},
5300{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}},
5301{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}},
5302{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}},
5303{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}},
5304{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}},
5305{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}},
5306{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}},
5307{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}},
5308{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}},
5309{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5310{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5311{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5312{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5313{"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5314{"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}},
5315{"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5316{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}},
5317{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}},
5318{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}},
5319{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}},
5320{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}},
5321{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
5322{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}},
5323{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}},
5324{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}},
5325{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}},
5326{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}},
5327{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}},
5328{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}},
5329{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}},
5330{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}},
5331{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}},
5332{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}},
5333{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}},
5334{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}},
5335{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}},
5336{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}},
5337{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}},
5338{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}},
5339{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}},
5340{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}},
5341{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}},
5342{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}},
5343{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}},
5344{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}},
5345{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}},
5346{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}},
5347{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}},
5348{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}},
5349{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}},
5350{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}},
5351{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}},
5352{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}},
5353{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}},
5354{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}},
5355{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}},
5356{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}},
5357{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, 0, {RT}},
5358{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5359{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, 0, {RT}},
5360{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5361{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}},
5362{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}},
5363{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5364{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5365{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}},
5366{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}},
5367{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}},
5368{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}},
5369{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}},
5370{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}},
5371{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}},
5372{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}},
5373{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}},
5374{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}},
5375{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}},
5376{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}},
5377{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}},
5378{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}},
5379{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}},
5380{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}},
5381{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}},
5382{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}},
5383{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}},
5384{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}},
5385{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}},
5386{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}},
5387{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}},
5388{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}},
5389{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}},
5390{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}},
5391{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}},
5392{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}},
5393{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}},
5394{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}},
5395{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}},
5396{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}},
5397{"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}},
5398{"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}},
5399{"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}},
5400{"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}},
5401{"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}},
5402{"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}},
5403{"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}},
5404{"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}},
5405{"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}},
5406{"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}},
5407{"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}},
5408{"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}},
5409{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}},
5410{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}},
5411{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}},
5412{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}},
5413{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}},
5414{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}},
5415{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}},
5416{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}},
5417{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}},
5418{"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}},
5419{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}},
5420{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}},
5421{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}},
5422{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}},
5423{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}},
5424{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}},
5425{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}},
5426{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}},
5427{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}},
5428{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}},
5429{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}},
5430{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}},
5431{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}},
5432{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}},
5433{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}},
5434{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}},
5435{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}},
5436{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}},
5437{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}},
5438{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}},
5439{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}},
5440{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}},
5441{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}},
5442{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}},
5443{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}},
5444{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}},
5445{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}},
5446{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}},
5447{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}},
5448{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}},
5449{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}},
5450{"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}},
5451{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}},
5452{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}},
5453{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}},
5454{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}},
5455{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}},
5456{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}},
5457{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}},
5458{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}},
5459{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}},
5460{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}},
5461{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}},
5462{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}},
5463{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}},
5464{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}},
5465{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}},
5466{"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}},
5467
5468{"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}},
5469
5470{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
5471
5472{"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}},
5473
5474{"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5475
5476{"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}},
5477{"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}},
5478
5479{"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5480{"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5481
5482{"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5483
5484{"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}},
1cb0a767 5485
db76a700 5486{"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}},
14b57c7c 5487{"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
db76a700 5488{"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}},
1cb0a767 5489
14b57c7c 5490{"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}},
1cb0a767 5491
14b57c7c 5492{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
1cb0a767 5493
14b57c7c 5494{"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}},
1cb0a767 5495
14b57c7c 5496{"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
066be9f7 5497
14b57c7c
AM		 5498{"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
5499{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}},
1cb0a767 5500
14b57c7c 5501{"stvexbx", X(31,389), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 5502
14b57c7c
AM		 5503{"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5504{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
1cb0a767 5505
14b57c7c
AM		 5506{"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5507{"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5508{"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5509{"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
066be9f7 5510
14b57c7c
AM		 5511{"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5512{"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
a680de9a 5513
14b57c7c 5514{"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
1cb0a767 5515
14b57c7c 5516{"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}},
1cb0a767 5517
14b57c7c 5518{"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}},
a680de9a 5519
14b57c7c 5520{"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}},
c0637f3a 5521
14b57c7c
AM		 5522{"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
5523{"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
e0d602ec 5524
14b57c7c 5525{"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}},
1cb0a767 5526
14b57c7c
AM		 5527{"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}},
5528{"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}},
1cb0a767 5529
14b57c7c 5530{"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
1cb0a767 5531
14b57c7c 5532{"mtdcrux", X(31,419), X_MASK, PPC464, 0, {RA, RS}},
1cb0a767 5533
14b57c7c 5534{"stvexhx", X(31,421), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 5535
14b57c7c 5536{"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}},
aea77599 5537
14b57c7c
AM		 5538{"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5539{"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5540{"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5541{"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
066be9f7 5542
14b57c7c 5543{"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
a680de9a 5544
14b57c7c 5545{"clrbhrb", X(31,430), 0xffffffff, POWER8, 0, {0}},
c0637f3a 5546
14b57c7c 5547{"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}},
1cb0a767 5548
14b57c7c 5549{"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 5550
14b57c7c 5551{"lwzmx", X(31,437), X_MASK, POWER9, 0, {RT, RA0, RB}},
19dfcc89 5552
14b57c7c 5553{"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
1cb0a767 5554
14b57c7c 5555{"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
1cb0a767 5556
14b57c7c 5557{"mdors", 0x7f9ce378, 0xffffffff, E500MC, 0, {0}},
1cb0a767 5558
14b57c7c 5559{"miso", 0x7f5ad378, 0xffffffff, E6500, 0, {0}},
aea77599 5560
9f6a6cc0 5561/* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
14b57c7c
AM		 5562 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
5563{"yield", 0x7f7bdb78, 0xffffffff, POWER7, 0, {0}},
5564{"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, 0, {0}},
5565{"mdoom", 0x7fdef378, 0xffffffff, POWER7, 0, {0}},
5566{"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RBS}},
5567{"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},
5568{"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RBS}},
5569{"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}},
5570
5571{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}},
5572{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}},
5573{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}},
5574{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}},
5575{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}},
5576{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}},
5577{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}},
5578{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}},
5579{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}},
5580{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}},
5581{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}},
5582{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}},
5583{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}},
5584{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}},
5585{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}},
5586{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}},
5587{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}},
5588{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}},
5589{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}},
5590{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}},
5591{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}},
5592{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}},
5593{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}},
5594{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}},
5595{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}},
5596{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}},
5597{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}},
5598{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}},
5599{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}},
5600{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}},
5601{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}},
5602{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}},
5603{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}},
5604{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}},
5605{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}},
5606{"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}},
5607
5608{"stvexwx", X(31,453), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5609
5610{"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
5611{"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
5612
5613{"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5614{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5615
5616{"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5617{"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5618
5619{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
5620{"mttmr", X(31,494), X_MASK, PPCTMR|E6500, 0, {TMR, RS}},
5621
5622{"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}},
5623
5624{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}},
5625{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}},
5626{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}},
5627{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}},
5628{"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}},
5629{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}},
5630{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
5631{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}},
5632{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}},
5633{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}},
5634{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, 0, {RS}},
5635{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, 0, {RS}},
5636{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}},
5637{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}},
5638{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}},
5639{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}},
5640{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}},
5641{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}},
5642{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}},
5643{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}},
5644{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}},
5645{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}},
5646{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}},
5647{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}},
5648{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}},
5649{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}},
5650{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, 0, {RS}},
5651{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, 0, {RS}},
5652{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, 0, {RS}},
5653{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, 0, {RS}},
5654{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}},
5655{"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}},
5656{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}},
5657{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}},
5658{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}},
5659{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}},
5660{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}},
5661{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}},
5662{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}},
5663{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}},
5664{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}},
5665{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}},
5666{"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}},
5667{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}},
5668{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}},
5669{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}},
5670{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}},
5671{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5672{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5673{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5674{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5675{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, 0, {RS}},
5676{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}},
5677{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}},
5678{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}},
5679{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}},
5680{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}},
5681{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}},
5682{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}},
5683{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}},
5684{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}},
5685{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}},
5686{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}},
5687{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}},
5688{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}},
5689{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}},
5690{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}},
5691{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}},
5692{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}},
5693{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}},
5694{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}},
5695{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}},
5696{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, 0, {RS}},
5697{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, 0, {RS}},
5698{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, 0, {RS}},
5699{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, 0, {RS}},
5700{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, 0, {RS}},
5701{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, 0, {RS}},
5702{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, 0, {RS}},
5703{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, 0, {RS}},
5704{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, 0, {RS}},
5705{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, 0, {RS}},
5706{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}},
5707{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}},
5708{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}},
5709{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}},
5710{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}},
5711{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}},
5712{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, 0, {RS}},
5713{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5714{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, 0, {RS}},
5715{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5716{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}},
5717{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}},
5718{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5719{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5720{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}},
5721{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}},
5722{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}},
5723{"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}},
5724{"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}},
5725{"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}},
5726{"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, 0, {RS}},
5727{"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, 0, {RS}},
5728{"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}},
5729{"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}},
5730{"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}},
5731{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}},
5732{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}},
5733{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}},
5734{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, 0, {RS}},
5735{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, 0, {RS}},
5736{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, 0, {RS}},
5737{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, 0, {RS}},
5738{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, 0, {RS}},
5739{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, 0, {RS}},
5740{"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, 0, {RS}},
5741{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0, {RS}},
5742{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, 0, {RS}},
5743{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, 0, {RS}},
5744{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, 0, {RS}},
5745{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, 0, {RS}},
5746{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, 0, {RS}},
5747{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, 0, {RS}},
5748{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, 0, {RS}},
5749{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, 0, {RS}},
5750{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, 0, {RS}},
5751{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, 0, {RS}},
5752{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, 0, {RS}},
5753{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, 0, {RS}},
5754{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, 0, {RS}},
5755{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, 0, {RS}},
5756{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, 0, {RS}},
5757{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, 0, {RS}},
5758{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, 0, {RS}},
5759{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, 0, {RS}},
5760{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, 0, {RS}},
5761{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, 0, {RS}},
5762{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, 0, {RS}},
5763{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, 0, {RS}},
5764{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, 0, {RS}},
5765{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, 0, {RS}},
5766{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, 0, {RS}},
5767{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, 0, {RS}},
5768{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}},
5769{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}},
5770{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}},
5771{"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}},
5772{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}},
5773{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}},
5774{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}},
5775{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}},
5776{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}},
5777{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}},
5778{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, 0, {RS}},
5779{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, 0, {RS}},
5780{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, 0, {RS}},
5781{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, 0, {RS}},
5782{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, 0, {RS}},
5783{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, 0, {RS}},
5784{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, 0, {RS}},
5785{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, 0, {RS}},
5786{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, 0, {RS}},
5787{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, 0, {RS}},
5788{"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}},
5789
5790{"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}},
5791
5792{"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}},
5793{"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}},
5794
5795{"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}},
5796
5797{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}},
5798
5799{"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5800
5801{"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5802
5803{"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}},
5804{"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}},
5805
5806{"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5807{"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5808
5809{"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5810{"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5811
5812{"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
5813
5814{"slbia", X(31,498), 0xff1fffff, POWER6, 0, {IH}},
4bc0608a 5815{"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}},
1cb0a767 5816
14b57c7c 5817{"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}},
1cb0a767 5818
14b57c7c 5819{"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
066be9f7 5820
14b57c7c 5821{"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}},
1cb0a767 5822
14b57c7c 5823{"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}},
252b5132 5824
dfdaec14 5825{"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
14b57c7c 5826{"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},
19a6653c 5827
14b57c7c 5828{"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
252b5132 5829
14b57c7c
AM		 5830{"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}},
5831{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 5832
14b57c7c
AM		 5833{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5834{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5835{"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
5836{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5837{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5838{"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
43e65147 5839
14b57c7c
AM		 5840{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5841{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5842{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5843{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 5844
14b57c7c 5845{"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
c0637f3a 5846
14b57c7c 5847{"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}},
418c1742 5848
14b57c7c 5849{"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}},
418c1742 5850
14b57c7c
AM		 5851{"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}},
5852{"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 5853
14b57c7c
AM		 5854{"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
5855{"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 5856
14b57c7c 5857{"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
702f0fb4 5858
14b57c7c
AM		 5859{"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5860{"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
5861{"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5862{"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
252b5132 5863
14b57c7c
AM		 5864{"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}},
5865{"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}},
23976049 5866
14b57c7c
AM		 5867{"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}},
5868{"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}},
a680de9a 5869
14b57c7c
AM		 5870{"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}},
5871{"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}},
f509565f 5872
14b57c7c
AM		 5873{"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},
5874{"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 5875
dfdaec14 5876{"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
14b57c7c 5877{"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},
19a6653c 5878
14b57c7c 5879{"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 5880
14b57c7c 5881{"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}},
418c1742 5882
14b57c7c
AM		 5883{"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}},
5884{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 5885
14b57c7c
AM		 5886{"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5887{"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}},
5888{"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5889{"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}},
252b5132 5890
14b57c7c 5891{"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}},
252b5132 5892
14b57c7c 5893{"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
252b5132 5894
14b57c7c
AM		 5895{"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}},
5896{"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}},
a680de9a 5897
14b57c7c 5898{"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
a680de9a 5899
dfdaec14 5900{"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
14b57c7c 5901{"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},
19a6653c 5902
14b57c7c 5903{"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 5904
14b57c7c 5905{"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}},
a680de9a 5906
14b57c7c 5907{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
081ba1b3 5908
14b57c7c 5909{"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
066be9f7 5910
14b57c7c 5911{"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
252b5132 5912
14b57c7c
AM		 5913{"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}},
5914{"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}},
252b5132 5915
dc302c00 5916{"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},
e01d869a 5917{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
14b57c7c
AM		 5918{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}},
5919{"sync", X(31,598), XSYNCLE_MASK, POWER9|E6500, 0, {LS, ESYNC}},
5920{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476|POWER9, {LS}},
5921{"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}},
5922{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
5923{"lwsync", X(31,598), 0xffffffff, E500, 0, {0}},
5924{"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}},
418c1742 5925
14b57c7c 5926{"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
23976049 5927
066be9f7 5928{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
14b57c7c 5929{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}},
252b5132 5930
14b57c7c 5931{"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}},
19a6653c 5932
14b57c7c 5933{"lvswx", X(31,613), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 5934
14b57c7c 5935{"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}},
a680de9a 5936
14b57c7c 5937{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
081ba1b3 5938
14b57c7c
AM		 5939{"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}},
5940{"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}},
252b5132 5941
14b57c7c
AM		 5942{"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
5943{"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 5944
14b57c7c 5945{"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},
252b5132 5946
14b57c7c 5947{"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}},
252b5132 5948
14b57c7c 5949{"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
252b5132 5950
dfdaec14 5951{"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
14b57c7c 5952{"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}},
19a6653c 5953
14b57c7c
AM		 5954{"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
5955{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
23976049 5956
14b57c7c 5957{"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
c0637f3a 5958
14b57c7c 5959{"tbegin.", XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}},
5817ffd1 5960
14b57c7c
AM		 5961{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5962{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5963{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5964{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 5965
14b57c7c
AM		 5966{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5967{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5968{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5969{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 5970
14b57c7c 5971{"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
418c1742 5972
14b57c7c 5973{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}},
252b5132 5974
14b57c7c
AM		 5975{"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},
5976{"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
418c1742 5977
14b57c7c
AM		 5978{"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
5979{"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
252b5132 5980
14b57c7c 5981{"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
ede602d7 5982
14b57c7c
AM		 5983{"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}},
5984{"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 5985
14b57c7c
AM		 5986{"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},
5987{"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 5988
dfdaec14 5989{"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
14b57c7c 5990{"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}},
19a6653c 5991
14b57c7c 5992{"stvfrx", X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 5993
14b57c7c
AM		 5994{"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}},
5995{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 5996
14b57c7c
AM		 5997{"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}},
5998{"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}},
5817ffd1 5999
14b57c7c 6000{"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
066be9f7 6001
14b57c7c 6002{"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
252b5132 6003
14b57c7c
AM		 6004{"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},
6005{"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
252b5132 6006
dfdaec14 6007{"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},
14b57c7c 6008{"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}},
19a6653c 6009
14b57c7c 6010{"stvflx", X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 6011
14b57c7c 6012{"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}},
a680de9a 6013
14b57c7c 6014{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
081ba1b3 6015
14b57c7c 6016{"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
066be9f7 6017
14b57c7c 6018{"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}},
5817ffd1 6019
14b57c7c
AM		 6020{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6021{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6022{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6023{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
418c1742 6024
14b57c7c
AM		 6025{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6026{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6027{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6028{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
fdd12ef3 6029
14b57c7c
AM		 6030{"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},
6031{"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}},
252b5132 6032
14b57c7c 6033{"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
066be9f7 6034
14b57c7c 6035{"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
252b5132 6036
14b57c7c
AM		 6037{"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}},
6038{"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}},
418c1742 6039
14b57c7c
AM		 6040{"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}},
6041{"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 6042
066be9f7 6043{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
14b57c7c 6044{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}},
252b5132 6045
14b57c7c 6046{"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}},
19a6653c 6047
14b57c7c 6048{"stvswx", X(31,741), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 6049
14b57c7c 6050{"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}},
a680de9a 6051
14b57c7c 6052{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
081ba1b3 6053
14b57c7c
AM		 6054{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6055{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6056{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6057{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
252b5132 6058
14b57c7c
AM		 6059{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6060{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
252b5132 6061
14b57c7c
AM		 6062{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6063{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6064{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6065{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
418c1742 6066
14b57c7c
AM		 6067{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6068{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6069{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6070{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
702f0fb4 6071
14b57c7c
AM		 6072{"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6073{"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6074{"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}},
5817ffd1 6075
14b57c7c 6076{"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}},
a680de9a 6077
14b57c7c
AM		 6078{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
6079{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}},
252b5132 6080
14b57c7c 6081{"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
252b5132 6082
14b57c7c
AM		 6083{"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}},
6084{"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}},
252b5132 6085
14b57c7c 6086{"lvsm", X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
a680de9a 6087
14b57c7c
AM		 6088{"copy_first", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},
6089{"copy", X(31,774), XLRT_MASK, POWER9, 0, {RA0, RB, L}},
a680de9a 6090
14b57c7c
AM		 6091{"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6092{"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},
6093{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
ede602d7 6094
14b57c7c
AM		 6095{"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6096{"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 6097
14b57c7c
AM		 6098{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6099{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6100{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6101{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 6102
14b57c7c
AM		 6103{"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}},
6104{"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}},
a680de9a 6105
14b57c7c
AM		 6106{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
6107{"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
066be9f7 6108
14b57c7c 6109{"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
5817ffd1 6110
14b57c7c 6111{"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
252b5132 6112
14b57c7c 6113{"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}},
252b5132 6114
14b57c7c 6115{"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}},
252b5132 6116
14b57c7c
AM		 6117{"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA0, RB}},
6118{"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}},
418c1742 6119
14b57c7c
AM		 6120{"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6121{"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6122{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6123{"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
fdd12ef3 6124
14b57c7c
AM		 6125{"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}},
6126{"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}},
252b5132 6127
14b57c7c 6128{"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}},
19a6653c 6129
14b57c7c
AM		 6130{"lvtrxl", X(31,805), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6131{"stvepx", X(31,807), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6132{"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}},
252b5132 6133
14b57c7c
AM		 6134{"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6135{"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 6136
14b57c7c 6137{"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
5817ffd1 6138
14b57c7c 6139{"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}},
252b5132 6140
14b57c7c 6141{"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}},
e0d602ec 6142
14b57c7c 6143{"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}},
252b5132 6144
14b57c7c 6145{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, 0, {STRM}},
252b5132 6146
14b57c7c 6147{"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}},
fdd12ef3 6148
14b57c7c
AM		 6149{"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6150{"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}},
6151{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6152{"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}},
702f0fb4 6153
14b57c7c
AM		 6154{"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}},
6155{"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}},
e0c21649 6156
14b57c7c 6157{"lvtlxl", X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 6158
14b57c7c 6159{"cp_abort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}},
a680de9a 6160
14b57c7c
AM		 6161{"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6162{"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 6163
14b57c7c 6164{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
a680de9a 6165{"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}},
9b4e5766 6166
14b57c7c 6167{"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
5817ffd1 6168
14b57c7c 6169{"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}},
e0d602ec 6170
14b57c7c 6171{"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
a680de9a 6172{"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}},
252b5132 6173
14b57c7c 6174{"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}},
418c1742 6175
9fe54b1c 6176{"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}},
14b57c7c
AM		 6177{"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}},
6178{"eieio", XMBAR(31,854,1),0xffffffff, E500, 0, {0}},
6179{"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, 0, {0}},
418c1742 6180
14b57c7c 6181{"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}},
418c1742 6182
14b57c7c 6183{"lvswxl", X(31,869), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 6184
14b57c7c
AM		 6185{"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}},
6186{"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}},
702f0fb4 6187
14b57c7c
AM		 6188{"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6189{"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 6190
14b57c7c 6191{"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 6192
14b57c7c 6193{"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
5817ffd1 6194
14b57c7c 6195{"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}},
a680de9a 6196
14b57c7c 6197{"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}},
252b5132 6198
14b57c7c 6199{"msgsync", X(31,886), 0xffffffff, POWER9, 0, {0}},
a680de9a 6200
14b57c7c 6201{"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}},
066be9f7 6202
14b57c7c
AM		 6203{"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}},
6204{"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}},
a680de9a 6205
14b57c7c
AM		 6206{"paste", XRC(31,902,0), XLRT_MASK, POWER9, 0, {RA0, RB, L0}},
6207{"paste_last", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}},
6208{"paste.", XRC(31,902,1), XLRT_MASK, POWER9, 0, {RA0, RB, L1}},
a680de9a 6209
14b57c7c
AM		 6210{"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},
6211{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 6212
14b57c7c
AM		 6213{"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6214{"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6215{"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6216{"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
066be9f7 6217
14b57c7c
AM		 6218{"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
6219{"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
066be9f7 6220
14b57c7c 6221{"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}},
5817ffd1 6222
14b57c7c
AM		 6223{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
6224{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
252b5132 6225
14b57c7c 6226{"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
a680de9a 6227{"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}},
702f0fb4 6228
14b57c7c 6229{"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}},
f5c120c5 6230
14b57c7c 6231{"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}},
252b5132 6232
14b57c7c
AM		 6233{"stfdpx", X(31,919), X_MASK, POWER6, POWER7, {FRSp, RA0, RB}},
6234{"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}},
6ba045b1 6235
14b57c7c
AM		 6236{"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}},
6237{"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}},
702f0fb4 6238
14b57c7c
AM		 6239{"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}},
6240{"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 6241
14b57c7c
AM		 6242{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
6243{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
6244{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
6245{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
702f0fb4 6246
14b57c7c 6247{"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}},
19a6653c 6248
14b57c7c 6249{"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 6250
14b57c7c
AM		 6251{"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}},
6252{"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L}},
6253{"wclr", X(31,934), X_MASK, PPCA2, 0, {L, RA0, RB}},
85d4ac0b 6254
14b57c7c 6255{"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
6ba045b1 6256
14b57c7c
AM		 6257{"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6258{"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6259{"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6260{"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
066be9f7 6261
14b57c7c
AM		 6262{"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6263{"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
a680de9a 6264
14b57c7c 6265{"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}},
5817ffd1 6266
e0d602ec
BE		 6267{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
6268{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
14b57c7c 6269{"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
702f0fb4 6270
14b57c7c 6271{"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}},
252b5132 6272
14b57c7c
AM		 6273{"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}},
6274{"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}},
51b5d4a8 6275
14b57c7c 6276{"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}},
252b5132 6277
14b57c7c
AM		 6278{"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}},
6279{"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}},
252b5132 6280
14b57c7c
AM		 6281{"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}},
6282{"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}},
252b5132 6283
14b57c7c 6284{"stvflxl", X(31,965), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 6285
14b57c7c
AM		 6286{"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
6287{"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
43e65147 6288
14b57c7c
AM		 6289{"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6290{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
43e65147 6291
14b57c7c
AM		 6292{"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6293{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
252b5132 6294
14b57c7c 6295{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
a680de9a 6296{"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}},
9b4e5766 6297
9fe54b1c 6298{"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
14b57c7c
AM		 6299{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}},
6300{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}},
6301{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
418c1742 6302
14b57c7c 6303{"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}},
c4e676f1 6304
14b57c7c 6305{"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}},
252b5132 6306
14b57c7c 6307{"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}},
252b5132 6308
14b57c7c 6309{"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
702f0fb4 6310
14b57c7c
AM		 6311{"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}},
6312{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}},
252b5132 6313
14b57c7c 6314{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
19a6653c 6315
14b57c7c 6316{"stvswxl", X(31,997), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 6317
14b57c7c 6318{"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}},
252b5132 6319
14b57c7c
AM		 6320{"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}},
6321{"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}},
252b5132 6322
14b57c7c
AM		 6323{"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6324{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
43e65147 6325
14b57c7c
AM		 6326{"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6327{"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
418c1742 6328
14b57c7c 6329{"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
a680de9a 6330
14b57c7c 6331{"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, 0, {0}},
702f0fb4 6332
14b57c7c 6333{"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},
252b5132 6334
14b57c7c 6335{"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}},
418c1742 6336
14b57c7c
AM		 6337{"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
6338{"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
786e2c0f 6339
14b57c7c 6340{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
ede602d7 6341
14b57c7c 6342{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}},
252b5132 6343
14b57c7c
AM		 6344{"cctpl", 0x7c210b78, 0xffffffff, CELL, 0, {0}},
6345{"cctpm", 0x7c421378, 0xffffffff, CELL, 0, {0}},
6346{"cctph", 0x7c631b78, 0xffffffff, CELL, 0, {0}},
252b5132 6347
14b57c7c
AM		 6348{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6349{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6350{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}},
252b5132 6351
14b57c7c
AM		 6352{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, 0, {0}},
6353{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, 0, {0}},
6354{"db12cyc", 0x7fdef378, 0xffffffff, CELL, 0, {0}},
6355{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, 0, {0}},
252b5132 6356
14b57c7c
AM		 6357{"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
6358{"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
252b5132 6359
14b57c7c
AM		 6360{"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}},
6361{"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
252b5132 6362
14b57c7c 6363{"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
252b5132 6364
14b57c7c 6365{"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
252b5132 6366
14b57c7c
AM		 6367{"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
6368{"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
252b5132 6369
14b57c7c
AM		 6370{"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}},
6371{"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
252b5132 6372
14b57c7c 6373{"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
252b5132 6374
14b57c7c 6375{"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
252b5132 6376
14b57c7c 6377{"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
252b5132 6378
14b57c7c 6379{"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
252b5132 6380
14b57c7c 6381{"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
252b5132 6382
14b57c7c 6383{"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
252b5132 6384
14b57c7c 6385{"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
252b5132 6386
14b57c7c 6387{"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
252b5132 6388
14b57c7c
AM		 6389{"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}},
6390{"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
252b5132 6391
14b57c7c
AM		 6392{"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
6393{"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
252b5132 6394
14b57c7c 6395{"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
252b5132 6396
14b57c7c 6397{"lfsu", OP(49), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
252b5132 6398
14b57c7c 6399{"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
252b5132 6400
14b57c7c 6401{"lfdu", OP(51), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
252b5132 6402
14b57c7c 6403{"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
adadcc0c 6404
14b57c7c 6405{"stfsu", OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
252b5132 6406
14b57c7c 6407{"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
c3d65c1c 6408
14b57c7c 6409{"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
252b5132 6410
14b57c7c
AM		 6411{"lq", OP(56), OP_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}},
6412{"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6413{"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
418c1742 6414
14b57c7c
AM		 6415{"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
6416{"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
6417{"lfdp", OP(57), OP_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}},
6418{"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6419{"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
802a735e 6420
14b57c7c
AM		 6421{"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
6422{"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}},
6423{"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
702f0fb4 6424
14b57c7c
AM		 6425{"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6426{"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
252b5132 6427
14b57c7c
AM		 6428{"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
6429{"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
252b5132 6430
14b57c7c
AM		 6431{"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6432{"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
252b5132 6433
14b57c7c
AM		 6434{"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6435{"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
252b5132 6436
14b57c7c
AM		 6437{"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6438{"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
252b5132 6439
14b57c7c
AM		 6440{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
6441{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
252b5132 6442
14b57c7c
AM		 6443{"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6444{"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6445{"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6446{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
1ed8e1e4 6447
14b57c7c
AM		 6448{"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6449{"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
252b5132 6450
14b57c7c
AM		 6451{"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6452{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6453{"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6454{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
252b5132 6455
14b57c7c
AM		 6456{"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6457{"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6458
14b57c7c
AM		 6459{"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6460{"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6461
14b57c7c
AM		 6462{"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6463{"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
702f0fb4 6464
14b57c7c
AM		 6465{"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6466{"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
702f0fb4 6467
14b57c7c
AM		 6468{"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6469{"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
702f0fb4 6470
14b57c7c
AM		 6471{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
6472{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
702f0fb4 6473
14b57c7c
AM		 6474{"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6475{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
702f0fb4 6476
14b57c7c
AM		 6477{"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
6478{"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
702f0fb4 6479
14b57c7c
AM		 6480{"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6481{"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
702f0fb4 6482
14b57c7c
AM		 6483{"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6484{"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
702f0fb4 6485
14b57c7c 6486{"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
702f0fb4 6487
14b57c7c
AM		 6488{"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6489{"dtstdc", Z(59,194), Z_MASK, POWER6, PPCVLE, {BF, FRA, DCM}},
6490{"dtstdg", Z(59,226), Z_MASK, POWER6, PPCVLE, {BF, FRA, DGM}},
6491
6492{"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6493{"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6494
6495{"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6496{"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6497
6498{"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6499{"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6500
6501{"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
6502{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
6503
6504{"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6505{"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6506
6507{"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6508{"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6509
6510{"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6511{"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6512
6513{"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6514
6515{"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6516{"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}},
6517
6518{"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6519{"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6520
6521{"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6522{"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6523
6524{"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
6525{"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
6526
6527{"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6528{"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6529
6530{"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6531{"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6532
6533{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6534{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6535
6536{"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6537{"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6538{"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, SHW}},
6539{"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6540{"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6541{"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6542{"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}},
6543{"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6544{"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6545{"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S, DMEX}},
6546{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6547{"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6548{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6549{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, DM}},
6550{"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6551{"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6552{"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6553{"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6554{"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6555{"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6556{"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6557{"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6558{"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6559{"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6560{"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6561{"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6562{"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6563{"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6564{"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6565{"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6566{"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6567{"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6568{"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6569{"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6570{"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6571{"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6572{"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6573{"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6574{"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6575{"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6576{"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6577{"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6578{"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6579{"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6580{"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6581{"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCVLE, {BF, XA6, XB6}},
6582{"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6583{"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6584{"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6585{"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6586{"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6587{"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6588{"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6589{"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6590{"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6591{"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6592{"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6593{"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6594{"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6595{"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6596{"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6597{"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6598{"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6599{"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6600{"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6601{"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCVLE, {XT6, XB6, UIM}},
6602{"xxextractuw", XX2(60,165), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
6603{"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6604{"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6605{"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6606{"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6607{"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6608{"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6609{"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6610{"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6611{"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3, PPCVLE, {XT6, IMM8}},
6612{"xxinsertw", XX2(60,181), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
6613{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6614{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6615{"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6616{"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6617{"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6618{"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6619{"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6620{"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6621{"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6622{"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6623{"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6624{"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6625{"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6626{"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6627{"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6628{"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6629{"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6630{"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6631{"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6632{"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6633{"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6634{"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6635{"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6636{"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6637{"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6638{"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6639{"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6640{"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6641{"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6642{"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6643{"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6644{"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6645{"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6646{"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6647{"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6648{"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6649{"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6650{"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6651{"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6652{"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6653{"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6654{"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6655{"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6656{"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6657{"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
6658{"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6659{"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6660{"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6661{"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6662{"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6663{"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6664{"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6665{"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6666{"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6667{"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6668{"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6669{"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6670{"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6671{"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6672{"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6673{"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
6674{"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
6675{"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6676{"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6677{"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6678{"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6679{"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6680{"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6681{"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6682{"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
6683{"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6684{"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6685{"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6686{"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6687{"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6688{"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6689{"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6690{"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6691{"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6692{"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6693{"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6694{"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6695{"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6696{"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6697{"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6698{"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6699{"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6700{"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
6701{"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6702{"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6703{"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6704{"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6705{"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6706{"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6707{"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6708{"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6709{"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}},
6710{"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6711{"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6712{"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6713{"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6714{"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6715{"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6716{"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6717{"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6718{"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6719{"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6720{"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6721{"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6722{"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6723{"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6724{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6725{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6726{"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6727{"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6728{"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6729{"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
6730{"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6731{"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6732{"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6733{"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6734
6735{"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
6736{"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
6737
6738{"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}},
6739{"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}},
6740{"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
6741{"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
6742{"stfdp", OP(61), OP_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}},
6743{"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
6744{"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
6745
6746{"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}},
6747{"stdu", DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}},
6748{"stq", DSO(62,2), DS_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}},
6749
6750{"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
6751
6752{"daddq", XRC(63,2,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6753{"daddq.", XRC(63,2,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6754
6755{"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
6756{"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
6757
6758{"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6759{"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6760
6761{"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6762{"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6763
6764{"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
6765{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
6766
6767{"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6768{"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6769
6770{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6771{"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6772{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6773{"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6774
6775{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6776{"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6777{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6778{"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6779
6780{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6781{"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6782{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6783{"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6784
6785{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6786{"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6787{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6788{"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6789
6790{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6791{"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6792{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6793{"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6794
6795{"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
6796{"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
6797
6798{"fsel", A(63,23,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6799{"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6800
6801{"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6802{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6803{"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6804{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
1ed8e1e4 6805
14b57c7c
AM		 6806{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6807{"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
6808{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6809{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
252b5132 6810
14b57c7c
AM		 6811{"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6812{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6813{"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6814{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
252b5132 6815
14b57c7c
AM		 6816{"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6817{"fms", A(63,28,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6818{"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6819{"fms.", A(63,28,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6820
14b57c7c
AM		 6821{"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6822{"fma", A(63,29,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6823{"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6824{"fma.", A(63,29,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6825
14b57c7c
AM		 6826{"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6827{"fnms", A(63,30,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6828{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6829{"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6830
14b57c7c
AM		 6831{"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6832{"fnma", A(63,31,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6833{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6834{"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6835
14b57c7c 6836{"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
252b5132 6837
14b57c7c
AM		 6838{"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6839{"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
702f0fb4 6840
14b57c7c
AM		 6841{"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
6842{"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
702f0fb4 6843
14b57c7c
AM		 6844{"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6845{"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6846
14b57c7c 6847{"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
a680de9a 6848
14b57c7c
AM		 6849{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BT}},
6850{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BT}},
252b5132 6851
14b57c7c
AM		 6852{"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6853{"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
252b5132 6854
14b57c7c 6855{"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
252b5132 6856
14b57c7c
AM		 6857{"dscliq", ZRC(63,66,0), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6858{"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
702f0fb4 6859
14b57c7c
AM		 6860{"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
6861{"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
702f0fb4 6862
14b57c7c
AM		 6863{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BT}},
6864{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BT}},
252b5132 6865
14b57c7c
AM		 6866{"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6867{"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
252b5132 6868
14b57c7c
AM		 6869{"dscriq", ZRC(63,98,0), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6870{"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
702f0fb4 6871
14b57c7c
AM		 6872{"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6873{"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
702f0fb4 6874
14b57c7c 6875{"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6876
14b57c7c 6877{"ftdiv", X(63,128), XBF_MASK, POWER7, PPCVLE, {BF, FRA, FRB}},
066be9f7 6878
14b57c7c 6879{"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
702f0fb4 6880
14b57c7c 6881{"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
a680de9a 6882
14b57c7c
AM		 6883{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
6884{"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
6885{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
6886{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
252b5132 6887
14b57c7c
AM		 6888{"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6889{"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
252b5132 6890
14b57c7c
AM		 6891{"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6892{"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6893{"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6894{"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
066be9f7 6895
14b57c7c 6896{"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCVLE, {BF, FRB}},
066be9f7 6897
14b57c7c 6898{"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
a680de9a 6899
14b57c7c 6900{"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
a680de9a 6901
14b57c7c
AM		 6902{"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DCM}},
6903{"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DGM}},
702f0fb4 6904
14b57c7c
AM		 6905{"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6906{"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
702f0fb4 6907
14b57c7c
AM		 6908{"dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6909{"dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
702f0fb4 6910
14b57c7c
AM		 6911{"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6912{"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
252b5132 6913
14b57c7c
AM		 6914{"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6915{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
702f0fb4 6916
14b57c7c
AM		 6917{"ddedpdq", XRC(63,322,0), X_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
6918{"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
702f0fb4 6919
14b57c7c
AM		 6920{"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6921{"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
702f0fb4 6922
14b57c7c
AM		 6923{"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6924{"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6925
14b57c7c
AM		 6926{"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6927{"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
a680de9a 6928
14b57c7c
AM		 6929{"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6930{"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6931
14b57c7c
AM		 6932{"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6933{"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
a680de9a 6934
14b57c7c
AM		 6935{"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6936{"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6937
14b57c7c
AM		 6938{"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6939{"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
a680de9a 6940
14b57c7c
AM		 6941{"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6942{"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6943
14b57c7c
AM		 6944{"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6945{"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
ce7a772b 6946
14b57c7c
AM		 6947{"dsubq", XRC(63,514,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6948{"dsubq.", XRC(63,514,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
702f0fb4 6949
14b57c7c
AM		 6950{"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6951{"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6952
14b57c7c
AM		 6953{"ddivq", XRC(63,546,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6954{"ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
702f0fb4 6955
14b57c7c
AM		 6956{"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6957{"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6958
14b57c7c
AM		 6959{"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
6960{"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
252b5132 6961
6fd3a02d
PB		 6962{"mffsce", XMMF(63,583,0,1), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
6963{"mffscdrn", XMMF(63,583,2,4), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
6964{"mffscdrni", XMMF(63,583,2,5), XMMF_MASK|(3<<14), POWER9, PPCVLE, {FRT, DRM}},
6965{"mffscrn", XMMF(63,583,2,6), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
6966{"mffscrni", XMMF(63,583,2,7), XMMF_MASK|(7<<13), POWER9, PPCVLE, {FRT, RM}},
6967{"mffsl", XMMF(63,583,3,0), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
6968
14b57c7c 6969{"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
702f0fb4 6970
14b57c7c 6971{"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
a680de9a 6972
14b57c7c
AM		 6973{"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}},
6974{"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}},
a680de9a 6975
14b57c7c 6976{"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}},
702f0fb4 6977
14b57c7c
AM		 6978{"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
6979{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
6980{"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
6981{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
252b5132 6982
14b57c7c
AM		 6983{"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
6984{"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
702f0fb4 6985
14b57c7c
AM		 6986{"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6987{"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
702f0fb4 6988
14b57c7c
AM		 6989{"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6990{"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6991{"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6992{"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6993{"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6994{"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6995{"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
a680de9a 6996
14b57c7c
AM		 6997{"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6998{"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6999{"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7000{"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
252b5132 7001
14b57c7c
AM		 7002{"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7003{"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
7004{"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7005{"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
252b5132 7006
14b57c7c
AM		 7007{"denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
7008{"denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
702f0fb4 7009
14b57c7c
AM		 7010{"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7011{"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7012{"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7013{"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7014{"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7015{"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7016{"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7017{"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7018{"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
a680de9a 7019
14b57c7c 7020{"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
c0637f3a 7021
14b57c7c
AM		 7022{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7023{"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
7024{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7025{"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
252b5132 7026
14b57c7c
AM		 7027{"diexq", XRC(63,866,0), X_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
7028{"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
702f0fb4 7029
14b57c7c 7030{"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 7031
14b57c7c
AM		 7032{"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7033{"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
066be9f7 7034
14b57c7c
AM		 7035{"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7036{"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
066be9f7 7037
14b57c7c 7038{"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
c0637f3a 7039
14b57c7c
AM		 7040{"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7041{"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
252b5132
RH		 7042};
7043
7044const int powerpc_num_opcodes =
7045 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
7046\f
b9c361e0
JL		 7047/* The VLE opcode table.
7048
7049 The format of this opcode table is the same as the main opcode table. */
7050
7051const struct powerpc_opcode vle_opcodes[] = {
14b57c7c
AM		 7052{"se_illegal", C(0), C_MASK, PPCVLE, 0, {}},
7053{"se_isync", C(1), C_MASK, PPCVLE, 0, {}},
7054{"se_sc", C(2), C_MASK, PPCVLE, 0, {}},
7055{"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, 0, {}},
7056{"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, 0, {}},
7057{"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, 0, {}},
7058{"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, 0, {}},
7059{"se_rfi", C(8), C_MASK, PPCVLE, 0, {}},
7060{"se_rfci", C(9), C_MASK, PPCVLE, 0, {}},
7061{"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}},
7062{"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}},
7063{"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}},
7064{"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}},
7065{"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}},
7066{"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, 0, {RX}},
7067{"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, 0, {RX}},
7068{"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, 0, {RX}},
7069{"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, 0, {RX}},
7070{"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, 0, {RX}},
7071{"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, 0, {RX}},
7072{"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, 0, {RX}},
7073{"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7074{"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}},
7075{"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}},
7076{"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7077{"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7078{"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7079{"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7080{"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7081{"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7082{"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7083{"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7084
7085{"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
dfdaec14 7086{"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
14b57c7c 7087{"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
dfdaec14 7088{"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
14b57c7c
AM		 7089{"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7090{"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7091{"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7092{"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7093{"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7094{"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7095{"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7096{"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7097{"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7098{"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7099{"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7100{"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7101{"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, 0, {0}},
7102{"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7103{"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7104{"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7105{"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7106{"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7107{"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7108{"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7109{"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7110{"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7111{"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7112{"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7113{"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7114{"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
dfdaec14
AJ		 7115{"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7116{"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7117{"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7118{"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7119{"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7120{"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7121{"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7122{"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7123{"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7124{"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
14b57c7c
AM		 7125{"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
7126{"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7127{"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}},
7128
7129{"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7130{"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7131{"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7132{"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7133{"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7134{"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7135{"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7136
7137{"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7138{"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7139{"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7140
7141{"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7142{"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7143{"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7144{"se_nop", SE_RR(17,0), 0xffff, PPCVLE, 0, {0}},
7145{"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7146{"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7147{"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7148{"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7149{"se_li", IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}},
7150
7151{"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7152{"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7153{"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7154{"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7155
7156{"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7157{"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7158{"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7159{"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7160{"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7161{"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7162{"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7163
7164{"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7165{"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7166{"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7167{"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7168{"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7169{"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
7170{"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
7171{"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
14b57c7c
AM		 7172{"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7173{"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
14b57c7c
AM		 7174{"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
7175{"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7176{"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
7177{"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7178{"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}},
7179{"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}},
7180{"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}},
7181{"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}},
7182{"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}},
7183{"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
7184{"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
7185{"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
7186{"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
7187{"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7188{"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7189{"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7190{"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7191{"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7192{"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7193{"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7194{"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7195{"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7196{"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7197{"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7198{"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7199{"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7200{"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7201{"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7202{"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7203{"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7204{"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7205{"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7206{"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7207{"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7208{"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7209{"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7210{"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7211{"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
7212{"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
7213
7214{"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7215{"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7216{"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7217{"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7218
7219{"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
7220{"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
7221{"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7222{"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7223{"e_crnot", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7224{"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7225{"e_crclr", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7226{"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7227{"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}},
7228{"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7229{"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7230
7231{"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7232
7233{"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
7234{"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
7235
7236{"e_crset", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7237{"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7238
7239{"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7240{"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7241
7242{"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7243
7244{"e_crmove", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7245{"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7246
7247{"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, 0, {RS}},
7248
7249{"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7250{"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7251
7252{"se_lbz", SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
7253
7254{"se_stb", SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
7255
7256{"se_lhz", SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
7257
7258{"se_sth", SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
7259
7260{"se_lwz", SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
7261
7262{"se_stw", SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
7263
7264{"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7265{"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7266{"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7267{"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7268{"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7269{"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7270{"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7271{"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
7272{"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7273{"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7274{"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7275{"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7276{"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7277{"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
7278{"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}},
7279{"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}},
7280{"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}},
b9c361e0
JL		 7281};
7282
7283const int vle_num_opcodes =
7284 sizeof (vle_opcodes) / sizeof (vle_opcodes[0]);
7285\f
252b5132
RH		 7286/* The macro table. This is only used by the assembler. */
7287
7288/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
7289 when x=0; 32-x when x is between 1 and 31; are negative if x is
7290 negative; and are 32 or more otherwise. This is what you want
7291 when, for instance, you are emulating a right shift by a
7292 rotate-left-and-mask, because the underlying instructions support
7293 shifts of size 0 but not shifts of size 32. By comparison, when
7294 extracting x bits from some word you want to use just 32-x, because
7295 the underlying instructions don't support extracting 0 bits but do
7296 support extracting the whole word (32 bits in this case). */
7297
7298const struct powerpc_macro powerpc_macros[] = {
de866fcc
AM		 7299{"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"},
7300{"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"},
bdc7fcfe
AM		 7301{"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
7302{"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
de866fcc
AM		 7303{"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"},
7304{"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
7305{"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
7306{"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
7307{"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"},
7308{"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"},
7309{"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
7310{"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
7311{"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"},
7312{"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"},
7313{"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"},
14b57c7c 7314{"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"},
de866fcc
AM		 7315
7316{"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
7317{"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
7318{"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7319{"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7320{"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7321{"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7322{"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7323{"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7324{"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7325{"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7326{"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
7327{"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
7328{"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
7329{"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
7330{"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7331{"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7332{"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7333{"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7334{"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
7335{"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
7336{"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
7337{"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
a4ebc835
AM		 7338
7339{"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"},
7340{"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7341{"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7342{"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7343{"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"},
7344{"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7345{"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"},
7346{"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7347{"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"},
7348{"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"},
7349{"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
252b5132
RH		 7350};
7351
7352const int powerpc_num_macros =
7353 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
GDB Binutils - Deliverables
This page took 1.770288 seconds and 4 git commands to generate.